1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
34 #include "stringpool.h"
40 #include "diagnostic-core.h"
42 #include "fold-const.h"
43 #include "stor-layout.h"
47 #include "insn-attr.h"
51 #include "common/common-target.h"
53 #include "langhooks.h"
56 #include "tree-pass.h"
60 /* This file should be included last. */
61 #include "target-def.h"
65 struct processor_costs
{
69 /* Integer signed load */
72 /* Integer zeroed load */
78 /* fmov, fneg, fabs */
82 const int float_plusminus
;
88 const int float_cmove
;
94 const int float_div_sf
;
97 const int float_div_df
;
100 const int float_sqrt_sf
;
103 const int float_sqrt_df
;
111 /* integer multiply cost for each bit set past the most
112 significant 3, so the formula for multiply cost becomes:
115 highest_bit = highest_clear_bit(rs1);
117 highest_bit = highest_set_bit(rs1);
120 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
122 A value of zero indicates that the multiply costs is fixed,
124 const int int_mul_bit_factor
;
135 /* penalty for shifts, due to scheduling rules etc. */
136 const int shift_penalty
;
140 struct processor_costs cypress_costs
= {
141 COSTS_N_INSNS (2), /* int load */
142 COSTS_N_INSNS (2), /* int signed load */
143 COSTS_N_INSNS (2), /* int zeroed load */
144 COSTS_N_INSNS (2), /* float load */
145 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
146 COSTS_N_INSNS (5), /* fadd, fsub */
147 COSTS_N_INSNS (1), /* fcmp */
148 COSTS_N_INSNS (1), /* fmov, fmovr */
149 COSTS_N_INSNS (7), /* fmul */
150 COSTS_N_INSNS (37), /* fdivs */
151 COSTS_N_INSNS (37), /* fdivd */
152 COSTS_N_INSNS (63), /* fsqrts */
153 COSTS_N_INSNS (63), /* fsqrtd */
154 COSTS_N_INSNS (1), /* imul */
155 COSTS_N_INSNS (1), /* imulX */
156 0, /* imul bit factor */
157 COSTS_N_INSNS (1), /* idiv */
158 COSTS_N_INSNS (1), /* idivX */
159 COSTS_N_INSNS (1), /* movcc/movr */
160 0, /* shift penalty */
164 struct processor_costs supersparc_costs
= {
165 COSTS_N_INSNS (1), /* int load */
166 COSTS_N_INSNS (1), /* int signed load */
167 COSTS_N_INSNS (1), /* int zeroed load */
168 COSTS_N_INSNS (0), /* float load */
169 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
170 COSTS_N_INSNS (3), /* fadd, fsub */
171 COSTS_N_INSNS (3), /* fcmp */
172 COSTS_N_INSNS (1), /* fmov, fmovr */
173 COSTS_N_INSNS (3), /* fmul */
174 COSTS_N_INSNS (6), /* fdivs */
175 COSTS_N_INSNS (9), /* fdivd */
176 COSTS_N_INSNS (12), /* fsqrts */
177 COSTS_N_INSNS (12), /* fsqrtd */
178 COSTS_N_INSNS (4), /* imul */
179 COSTS_N_INSNS (4), /* imulX */
180 0, /* imul bit factor */
181 COSTS_N_INSNS (4), /* idiv */
182 COSTS_N_INSNS (4), /* idivX */
183 COSTS_N_INSNS (1), /* movcc/movr */
184 1, /* shift penalty */
188 struct processor_costs hypersparc_costs
= {
189 COSTS_N_INSNS (1), /* int load */
190 COSTS_N_INSNS (1), /* int signed load */
191 COSTS_N_INSNS (1), /* int zeroed load */
192 COSTS_N_INSNS (1), /* float load */
193 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
194 COSTS_N_INSNS (1), /* fadd, fsub */
195 COSTS_N_INSNS (1), /* fcmp */
196 COSTS_N_INSNS (1), /* fmov, fmovr */
197 COSTS_N_INSNS (1), /* fmul */
198 COSTS_N_INSNS (8), /* fdivs */
199 COSTS_N_INSNS (12), /* fdivd */
200 COSTS_N_INSNS (17), /* fsqrts */
201 COSTS_N_INSNS (17), /* fsqrtd */
202 COSTS_N_INSNS (17), /* imul */
203 COSTS_N_INSNS (17), /* imulX */
204 0, /* imul bit factor */
205 COSTS_N_INSNS (17), /* idiv */
206 COSTS_N_INSNS (17), /* idivX */
207 COSTS_N_INSNS (1), /* movcc/movr */
208 0, /* shift penalty */
212 struct processor_costs leon_costs
= {
213 COSTS_N_INSNS (1), /* int load */
214 COSTS_N_INSNS (1), /* int signed load */
215 COSTS_N_INSNS (1), /* int zeroed load */
216 COSTS_N_INSNS (1), /* float load */
217 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
218 COSTS_N_INSNS (1), /* fadd, fsub */
219 COSTS_N_INSNS (1), /* fcmp */
220 COSTS_N_INSNS (1), /* fmov, fmovr */
221 COSTS_N_INSNS (1), /* fmul */
222 COSTS_N_INSNS (15), /* fdivs */
223 COSTS_N_INSNS (15), /* fdivd */
224 COSTS_N_INSNS (23), /* fsqrts */
225 COSTS_N_INSNS (23), /* fsqrtd */
226 COSTS_N_INSNS (5), /* imul */
227 COSTS_N_INSNS (5), /* imulX */
228 0, /* imul bit factor */
229 COSTS_N_INSNS (5), /* idiv */
230 COSTS_N_INSNS (5), /* idivX */
231 COSTS_N_INSNS (1), /* movcc/movr */
232 0, /* shift penalty */
236 struct processor_costs leon3_costs
= {
237 COSTS_N_INSNS (1), /* int load */
238 COSTS_N_INSNS (1), /* int signed load */
239 COSTS_N_INSNS (1), /* int zeroed load */
240 COSTS_N_INSNS (1), /* float load */
241 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
242 COSTS_N_INSNS (1), /* fadd, fsub */
243 COSTS_N_INSNS (1), /* fcmp */
244 COSTS_N_INSNS (1), /* fmov, fmovr */
245 COSTS_N_INSNS (1), /* fmul */
246 COSTS_N_INSNS (14), /* fdivs */
247 COSTS_N_INSNS (15), /* fdivd */
248 COSTS_N_INSNS (22), /* fsqrts */
249 COSTS_N_INSNS (23), /* fsqrtd */
250 COSTS_N_INSNS (5), /* imul */
251 COSTS_N_INSNS (5), /* imulX */
252 0, /* imul bit factor */
253 COSTS_N_INSNS (35), /* idiv */
254 COSTS_N_INSNS (35), /* idivX */
255 COSTS_N_INSNS (1), /* movcc/movr */
256 0, /* shift penalty */
260 struct processor_costs sparclet_costs
= {
261 COSTS_N_INSNS (3), /* int load */
262 COSTS_N_INSNS (3), /* int signed load */
263 COSTS_N_INSNS (1), /* int zeroed load */
264 COSTS_N_INSNS (1), /* float load */
265 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
266 COSTS_N_INSNS (1), /* fadd, fsub */
267 COSTS_N_INSNS (1), /* fcmp */
268 COSTS_N_INSNS (1), /* fmov, fmovr */
269 COSTS_N_INSNS (1), /* fmul */
270 COSTS_N_INSNS (1), /* fdivs */
271 COSTS_N_INSNS (1), /* fdivd */
272 COSTS_N_INSNS (1), /* fsqrts */
273 COSTS_N_INSNS (1), /* fsqrtd */
274 COSTS_N_INSNS (5), /* imul */
275 COSTS_N_INSNS (5), /* imulX */
276 0, /* imul bit factor */
277 COSTS_N_INSNS (5), /* idiv */
278 COSTS_N_INSNS (5), /* idivX */
279 COSTS_N_INSNS (1), /* movcc/movr */
280 0, /* shift penalty */
284 struct processor_costs ultrasparc_costs
= {
285 COSTS_N_INSNS (2), /* int load */
286 COSTS_N_INSNS (3), /* int signed load */
287 COSTS_N_INSNS (2), /* int zeroed load */
288 COSTS_N_INSNS (2), /* float load */
289 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
290 COSTS_N_INSNS (4), /* fadd, fsub */
291 COSTS_N_INSNS (1), /* fcmp */
292 COSTS_N_INSNS (2), /* fmov, fmovr */
293 COSTS_N_INSNS (4), /* fmul */
294 COSTS_N_INSNS (13), /* fdivs */
295 COSTS_N_INSNS (23), /* fdivd */
296 COSTS_N_INSNS (13), /* fsqrts */
297 COSTS_N_INSNS (23), /* fsqrtd */
298 COSTS_N_INSNS (4), /* imul */
299 COSTS_N_INSNS (4), /* imulX */
300 2, /* imul bit factor */
301 COSTS_N_INSNS (37), /* idiv */
302 COSTS_N_INSNS (68), /* idivX */
303 COSTS_N_INSNS (2), /* movcc/movr */
304 2, /* shift penalty */
308 struct processor_costs ultrasparc3_costs
= {
309 COSTS_N_INSNS (2), /* int load */
310 COSTS_N_INSNS (3), /* int signed load */
311 COSTS_N_INSNS (3), /* int zeroed load */
312 COSTS_N_INSNS (2), /* float load */
313 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
314 COSTS_N_INSNS (4), /* fadd, fsub */
315 COSTS_N_INSNS (5), /* fcmp */
316 COSTS_N_INSNS (3), /* fmov, fmovr */
317 COSTS_N_INSNS (4), /* fmul */
318 COSTS_N_INSNS (17), /* fdivs */
319 COSTS_N_INSNS (20), /* fdivd */
320 COSTS_N_INSNS (20), /* fsqrts */
321 COSTS_N_INSNS (29), /* fsqrtd */
322 COSTS_N_INSNS (6), /* imul */
323 COSTS_N_INSNS (6), /* imulX */
324 0, /* imul bit factor */
325 COSTS_N_INSNS (40), /* idiv */
326 COSTS_N_INSNS (71), /* idivX */
327 COSTS_N_INSNS (2), /* movcc/movr */
328 0, /* shift penalty */
332 struct processor_costs niagara_costs
= {
333 COSTS_N_INSNS (3), /* int load */
334 COSTS_N_INSNS (3), /* int signed load */
335 COSTS_N_INSNS (3), /* int zeroed load */
336 COSTS_N_INSNS (9), /* float load */
337 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
338 COSTS_N_INSNS (8), /* fadd, fsub */
339 COSTS_N_INSNS (26), /* fcmp */
340 COSTS_N_INSNS (8), /* fmov, fmovr */
341 COSTS_N_INSNS (29), /* fmul */
342 COSTS_N_INSNS (54), /* fdivs */
343 COSTS_N_INSNS (83), /* fdivd */
344 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
345 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
346 COSTS_N_INSNS (11), /* imul */
347 COSTS_N_INSNS (11), /* imulX */
348 0, /* imul bit factor */
349 COSTS_N_INSNS (72), /* idiv */
350 COSTS_N_INSNS (72), /* idivX */
351 COSTS_N_INSNS (1), /* movcc/movr */
352 0, /* shift penalty */
356 struct processor_costs niagara2_costs
= {
357 COSTS_N_INSNS (3), /* int load */
358 COSTS_N_INSNS (3), /* int signed load */
359 COSTS_N_INSNS (3), /* int zeroed load */
360 COSTS_N_INSNS (3), /* float load */
361 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
362 COSTS_N_INSNS (6), /* fadd, fsub */
363 COSTS_N_INSNS (6), /* fcmp */
364 COSTS_N_INSNS (6), /* fmov, fmovr */
365 COSTS_N_INSNS (6), /* fmul */
366 COSTS_N_INSNS (19), /* fdivs */
367 COSTS_N_INSNS (33), /* fdivd */
368 COSTS_N_INSNS (19), /* fsqrts */
369 COSTS_N_INSNS (33), /* fsqrtd */
370 COSTS_N_INSNS (5), /* imul */
371 COSTS_N_INSNS (5), /* imulX */
372 0, /* imul bit factor */
373 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
374 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
375 COSTS_N_INSNS (1), /* movcc/movr */
376 0, /* shift penalty */
380 struct processor_costs niagara3_costs
= {
381 COSTS_N_INSNS (3), /* int load */
382 COSTS_N_INSNS (3), /* int signed load */
383 COSTS_N_INSNS (3), /* int zeroed load */
384 COSTS_N_INSNS (3), /* float load */
385 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
386 COSTS_N_INSNS (9), /* fadd, fsub */
387 COSTS_N_INSNS (9), /* fcmp */
388 COSTS_N_INSNS (9), /* fmov, fmovr */
389 COSTS_N_INSNS (9), /* fmul */
390 COSTS_N_INSNS (23), /* fdivs */
391 COSTS_N_INSNS (37), /* fdivd */
392 COSTS_N_INSNS (23), /* fsqrts */
393 COSTS_N_INSNS (37), /* fsqrtd */
394 COSTS_N_INSNS (9), /* imul */
395 COSTS_N_INSNS (9), /* imulX */
396 0, /* imul bit factor */
397 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
398 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
399 COSTS_N_INSNS (1), /* movcc/movr */
400 0, /* shift penalty */
404 struct processor_costs niagara4_costs
= {
405 COSTS_N_INSNS (5), /* int load */
406 COSTS_N_INSNS (5), /* int signed load */
407 COSTS_N_INSNS (5), /* int zeroed load */
408 COSTS_N_INSNS (5), /* float load */
409 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
410 COSTS_N_INSNS (11), /* fadd, fsub */
411 COSTS_N_INSNS (11), /* fcmp */
412 COSTS_N_INSNS (11), /* fmov, fmovr */
413 COSTS_N_INSNS (11), /* fmul */
414 COSTS_N_INSNS (24), /* fdivs */
415 COSTS_N_INSNS (37), /* fdivd */
416 COSTS_N_INSNS (24), /* fsqrts */
417 COSTS_N_INSNS (37), /* fsqrtd */
418 COSTS_N_INSNS (12), /* imul */
419 COSTS_N_INSNS (12), /* imulX */
420 0, /* imul bit factor */
421 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
422 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
423 COSTS_N_INSNS (1), /* movcc/movr */
424 0, /* shift penalty */
428 struct processor_costs niagara7_costs
= {
429 COSTS_N_INSNS (5), /* int load */
430 COSTS_N_INSNS (5), /* int signed load */
431 COSTS_N_INSNS (5), /* int zeroed load */
432 COSTS_N_INSNS (5), /* float load */
433 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
434 COSTS_N_INSNS (11), /* fadd, fsub */
435 COSTS_N_INSNS (11), /* fcmp */
436 COSTS_N_INSNS (11), /* fmov, fmovr */
437 COSTS_N_INSNS (11), /* fmul */
438 COSTS_N_INSNS (24), /* fdivs */
439 COSTS_N_INSNS (37), /* fdivd */
440 COSTS_N_INSNS (24), /* fsqrts */
441 COSTS_N_INSNS (37), /* fsqrtd */
442 COSTS_N_INSNS (12), /* imul */
443 COSTS_N_INSNS (12), /* imulX */
444 0, /* imul bit factor */
445 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
446 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
447 COSTS_N_INSNS (1), /* movcc/movr */
448 0, /* shift penalty */
451 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
453 #ifdef HAVE_AS_RELAX_OPTION
454 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
455 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
456 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
457 somebody does not branch between the sethi and jmp. */
458 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
460 #define LEAF_SIBCALL_SLOT_RESERVED_P \
461 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
464 /* Vector to say how input registers are mapped to output registers.
465 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
466 eliminate it. You must use -fomit-frame-pointer to get that. */
467 char leaf_reg_remap
[] =
468 { 0, 1, 2, 3, 4, 5, 6, 7,
469 -1, -1, -1, -1, -1, -1, 14, -1,
470 -1, -1, -1, -1, -1, -1, -1, -1,
471 8, 9, 10, 11, 12, 13, -1, 15,
473 32, 33, 34, 35, 36, 37, 38, 39,
474 40, 41, 42, 43, 44, 45, 46, 47,
475 48, 49, 50, 51, 52, 53, 54, 55,
476 56, 57, 58, 59, 60, 61, 62, 63,
477 64, 65, 66, 67, 68, 69, 70, 71,
478 72, 73, 74, 75, 76, 77, 78, 79,
479 80, 81, 82, 83, 84, 85, 86, 87,
480 88, 89, 90, 91, 92, 93, 94, 95,
481 96, 97, 98, 99, 100, 101, 102};
483 /* Vector, indexed by hard register number, which contains 1
484 for a register that is allowable in a candidate for leaf
485 function treatment. */
486 char sparc_leaf_regs
[] =
487 { 1, 1, 1, 1, 1, 1, 1, 1,
488 0, 0, 0, 0, 0, 0, 1, 0,
489 0, 0, 0, 0, 0, 0, 0, 0,
490 1, 1, 1, 1, 1, 1, 0, 1,
491 1, 1, 1, 1, 1, 1, 1, 1,
492 1, 1, 1, 1, 1, 1, 1, 1,
493 1, 1, 1, 1, 1, 1, 1, 1,
494 1, 1, 1, 1, 1, 1, 1, 1,
495 1, 1, 1, 1, 1, 1, 1, 1,
496 1, 1, 1, 1, 1, 1, 1, 1,
497 1, 1, 1, 1, 1, 1, 1, 1,
498 1, 1, 1, 1, 1, 1, 1, 1,
499 1, 1, 1, 1, 1, 1, 1};
501 struct GTY(()) machine_function
503 /* Size of the frame of the function. */
504 HOST_WIDE_INT frame_size
;
506 /* Size of the frame of the function minus the register window save area
507 and the outgoing argument area. */
508 HOST_WIDE_INT apparent_frame_size
;
510 /* Register we pretend the frame pointer is allocated to. Normally, this
511 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
512 record "offset" separately as it may be too big for (reg + disp). */
514 HOST_WIDE_INT frame_base_offset
;
516 /* Number of global or FP registers to be saved (as 4-byte quantities). */
517 int n_global_fp_regs
;
519 /* True if the current function is leaf and uses only leaf regs,
520 so that the SPARC leaf function optimization can be applied.
521 Private version of crtl->uses_only_leaf_regs, see
522 sparc_expand_prologue for the rationale. */
525 /* True if the prologue saves local or in registers. */
526 bool save_local_in_regs_p
;
528 /* True if the data calculated by sparc_expand_prologue are valid. */
529 bool prologue_data_valid_p
;
532 #define sparc_frame_size cfun->machine->frame_size
533 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
534 #define sparc_frame_base_reg cfun->machine->frame_base_reg
535 #define sparc_frame_base_offset cfun->machine->frame_base_offset
536 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
537 #define sparc_leaf_function_p cfun->machine->leaf_function_p
538 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
539 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
541 /* 1 if the next opcode is to be specially indented. */
542 int sparc_indent_opcode
= 0;
544 static void sparc_option_override (void);
545 static void sparc_init_modes (void);
546 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
547 const_tree
, bool, bool, int *, int *);
549 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
550 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
552 static void sparc_emit_set_const32 (rtx
, rtx
);
553 static void sparc_emit_set_const64 (rtx
, rtx
);
554 static void sparc_output_addr_vec (rtx
);
555 static void sparc_output_addr_diff_vec (rtx
);
556 static void sparc_output_deferred_case_vectors (void);
557 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
558 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
559 static rtx
sparc_builtin_saveregs (void);
560 static int epilogue_renumber (rtx
*, int);
561 static bool sparc_assemble_integer (rtx
, unsigned int, int);
562 static int set_extends (rtx_insn
*);
563 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
564 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
565 #ifdef TARGET_SOLARIS
566 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
567 tree
) ATTRIBUTE_UNUSED
;
569 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
570 static int sparc_issue_rate (void);
571 static void sparc_sched_init (FILE *, int, int);
572 static int sparc_use_sched_lookahead (void);
574 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
575 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
576 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
577 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
578 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
580 static bool sparc_function_ok_for_sibcall (tree
, tree
);
581 static void sparc_init_libfuncs (void);
582 static void sparc_init_builtins (void);
583 static void sparc_fpu_init_builtins (void);
584 static void sparc_vis_init_builtins (void);
585 static tree
sparc_builtin_decl (unsigned, bool);
586 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
587 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
588 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
589 HOST_WIDE_INT
, tree
);
590 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
591 HOST_WIDE_INT
, const_tree
);
592 static struct machine_function
* sparc_init_machine_status (void);
593 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
594 static rtx
sparc_tls_get_addr (void);
595 static rtx
sparc_tls_got (void);
596 static int sparc_register_move_cost (machine_mode
,
597 reg_class_t
, reg_class_t
);
598 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
599 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
600 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
601 static bool sparc_function_value_regno_p (const unsigned int);
602 static rtx
sparc_struct_value_rtx (tree
, int);
603 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
604 int *, const_tree
, int);
605 static bool sparc_return_in_memory (const_tree
, const_tree
);
606 static bool sparc_strict_argument_naming (cumulative_args_t
);
607 static void sparc_va_start (tree
, rtx
);
608 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
609 static bool sparc_vector_mode_supported_p (machine_mode
);
610 static bool sparc_tls_referenced_p (rtx
);
611 static rtx
sparc_legitimize_tls_address (rtx
);
612 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
613 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
614 static rtx
sparc_delegitimize_address (rtx
);
615 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
616 static bool sparc_pass_by_reference (cumulative_args_t
,
617 machine_mode
, const_tree
, bool);
618 static void sparc_function_arg_advance (cumulative_args_t
,
619 machine_mode
, const_tree
, bool);
620 static rtx
sparc_function_arg_1 (cumulative_args_t
,
621 machine_mode
, const_tree
, bool, bool);
622 static rtx
sparc_function_arg (cumulative_args_t
,
623 machine_mode
, const_tree
, bool);
624 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
625 machine_mode
, const_tree
, bool);
626 static unsigned int sparc_function_arg_boundary (machine_mode
,
628 static int sparc_arg_partial_bytes (cumulative_args_t
,
629 machine_mode
, tree
, bool);
630 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
631 static void sparc_file_end (void);
632 static bool sparc_frame_pointer_required (void);
633 static bool sparc_can_eliminate (const int, const int);
634 static rtx
sparc_builtin_setjmp_frame_value (void);
635 static void sparc_conditional_register_usage (void);
636 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
637 static const char *sparc_mangle_type (const_tree
);
639 static void sparc_trampoline_init (rtx
, tree
, rtx
);
640 static machine_mode
sparc_preferred_simd_mode (machine_mode
);
641 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
642 static bool sparc_print_operand_punct_valid_p (unsigned char);
643 static void sparc_print_operand (FILE *, rtx
, int);
644 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
645 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
647 secondary_reload_info
*);
648 static machine_mode
sparc_cstore_mode (enum insn_code icode
);
649 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
651 #ifdef SUBTARGET_ATTRIBUTE_TABLE
652 /* Table of valid machine attributes. */
653 static const struct attribute_spec sparc_attribute_table
[] =
655 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
657 SUBTARGET_ATTRIBUTE_TABLE
,
658 { NULL
, 0, 0, false, false, false, NULL
, false }
662 /* Option handling. */
665 enum cmodel sparc_cmodel
;
667 char sparc_hard_reg_printed
[8];
669 /* Initialize the GCC target structure. */
671 /* The default is to use .half rather than .short for aligned HI objects. */
672 #undef TARGET_ASM_ALIGNED_HI_OP
673 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
675 #undef TARGET_ASM_UNALIGNED_HI_OP
676 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
677 #undef TARGET_ASM_UNALIGNED_SI_OP
678 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
679 #undef TARGET_ASM_UNALIGNED_DI_OP
680 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
682 /* The target hook has to handle DI-mode values. */
683 #undef TARGET_ASM_INTEGER
684 #define TARGET_ASM_INTEGER sparc_assemble_integer
686 #undef TARGET_ASM_FUNCTION_PROLOGUE
687 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
688 #undef TARGET_ASM_FUNCTION_EPILOGUE
689 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
691 #undef TARGET_SCHED_ADJUST_COST
692 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
693 #undef TARGET_SCHED_ISSUE_RATE
694 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
695 #undef TARGET_SCHED_INIT
696 #define TARGET_SCHED_INIT sparc_sched_init
697 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
698 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
700 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
701 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
703 #undef TARGET_INIT_LIBFUNCS
704 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
706 #undef TARGET_LEGITIMIZE_ADDRESS
707 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
708 #undef TARGET_DELEGITIMIZE_ADDRESS
709 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
710 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
711 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
713 #undef TARGET_INIT_BUILTINS
714 #define TARGET_INIT_BUILTINS sparc_init_builtins
715 #undef TARGET_BUILTIN_DECL
716 #define TARGET_BUILTIN_DECL sparc_builtin_decl
717 #undef TARGET_EXPAND_BUILTIN
718 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
719 #undef TARGET_FOLD_BUILTIN
720 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
723 #undef TARGET_HAVE_TLS
724 #define TARGET_HAVE_TLS true
727 #undef TARGET_CANNOT_FORCE_CONST_MEM
728 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
730 #undef TARGET_ASM_OUTPUT_MI_THUNK
731 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
732 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
733 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
735 #undef TARGET_RTX_COSTS
736 #define TARGET_RTX_COSTS sparc_rtx_costs
737 #undef TARGET_ADDRESS_COST
738 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
739 #undef TARGET_REGISTER_MOVE_COST
740 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
742 #undef TARGET_PROMOTE_FUNCTION_MODE
743 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
745 #undef TARGET_FUNCTION_VALUE
746 #define TARGET_FUNCTION_VALUE sparc_function_value
747 #undef TARGET_LIBCALL_VALUE
748 #define TARGET_LIBCALL_VALUE sparc_libcall_value
749 #undef TARGET_FUNCTION_VALUE_REGNO_P
750 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
752 #undef TARGET_STRUCT_VALUE_RTX
753 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
754 #undef TARGET_RETURN_IN_MEMORY
755 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
756 #undef TARGET_MUST_PASS_IN_STACK
757 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
758 #undef TARGET_PASS_BY_REFERENCE
759 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
760 #undef TARGET_ARG_PARTIAL_BYTES
761 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
762 #undef TARGET_FUNCTION_ARG_ADVANCE
763 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
764 #undef TARGET_FUNCTION_ARG
765 #define TARGET_FUNCTION_ARG sparc_function_arg
766 #undef TARGET_FUNCTION_INCOMING_ARG
767 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
768 #undef TARGET_FUNCTION_ARG_BOUNDARY
769 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
771 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
772 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
773 #undef TARGET_STRICT_ARGUMENT_NAMING
774 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
776 #undef TARGET_EXPAND_BUILTIN_VA_START
777 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
778 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
779 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
781 #undef TARGET_VECTOR_MODE_SUPPORTED_P
782 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
784 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
785 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
787 #ifdef SUBTARGET_INSERT_ATTRIBUTES
788 #undef TARGET_INSERT_ATTRIBUTES
789 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
792 #ifdef SUBTARGET_ATTRIBUTE_TABLE
793 #undef TARGET_ATTRIBUTE_TABLE
794 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
797 #undef TARGET_OPTION_OVERRIDE
798 #define TARGET_OPTION_OVERRIDE sparc_option_override
800 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
801 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
802 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
805 #undef TARGET_ASM_FILE_END
806 #define TARGET_ASM_FILE_END sparc_file_end
808 #undef TARGET_FRAME_POINTER_REQUIRED
809 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
811 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
812 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
814 #undef TARGET_CAN_ELIMINATE
815 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
817 #undef TARGET_PREFERRED_RELOAD_CLASS
818 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
820 #undef TARGET_SECONDARY_RELOAD
821 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
823 #undef TARGET_CONDITIONAL_REGISTER_USAGE
824 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
826 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
827 #undef TARGET_MANGLE_TYPE
828 #define TARGET_MANGLE_TYPE sparc_mangle_type
832 #define TARGET_LRA_P hook_bool_void_false
834 #undef TARGET_LEGITIMATE_ADDRESS_P
835 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
837 #undef TARGET_LEGITIMATE_CONSTANT_P
838 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
840 #undef TARGET_TRAMPOLINE_INIT
841 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
843 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
844 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
845 #undef TARGET_PRINT_OPERAND
846 #define TARGET_PRINT_OPERAND sparc_print_operand
847 #undef TARGET_PRINT_OPERAND_ADDRESS
848 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
850 /* The value stored by LDSTUB. */
851 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
852 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
854 #undef TARGET_CSTORE_MODE
855 #define TARGET_CSTORE_MODE sparc_cstore_mode
857 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
858 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
860 struct gcc_target targetm
= TARGET_INITIALIZER
;
862 /* Return the memory reference contained in X if any, zero otherwise. */
867 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
876 /* We use a machine specific pass to enable workarounds for errata.
877 We need to have the (essentially) final form of the insn stream in order
878 to properly detect the various hazards. Therefore, this machine specific
879 pass runs as late as possible. The pass is inserted in the pass pipeline
880 at the end of sparc_option_override. */
883 sparc_do_work_around_errata (void)
885 rtx_insn
*insn
, *next
;
887 /* Force all instructions to be split into their final form. */
888 split_all_insns_noflow ();
890 /* Now look for specific patterns in the insn stream. */
891 for (insn
= get_insns (); insn
; insn
= next
)
893 bool insert_nop
= false;
896 /* Look into the instruction in a delay slot. */
897 if (NONJUMP_INSN_P (insn
))
898 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
899 insn
= seq
->insn (1);
901 /* Look for a single-word load into an odd-numbered FP register. */
903 && NONJUMP_INSN_P (insn
)
904 && (set
= single_set (insn
)) != NULL_RTX
905 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
906 && MEM_P (SET_SRC (set
))
907 && REG_P (SET_DEST (set
))
908 && REGNO (SET_DEST (set
)) > 31
909 && REGNO (SET_DEST (set
)) % 2 != 0)
911 /* The wrong dependency is on the enclosing double register. */
912 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
913 unsigned int src1
, src2
, dest
;
916 next
= next_active_insn (insn
);
919 /* If the insn is a branch, then it cannot be problematic. */
920 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
924 code
= INSN_CODE (next
);
928 case CODE_FOR_adddf3
:
929 case CODE_FOR_subdf3
:
930 case CODE_FOR_muldf3
:
931 case CODE_FOR_divdf3
:
932 dest
= REGNO (recog_data
.operand
[0]);
933 src1
= REGNO (recog_data
.operand
[1]);
934 src2
= REGNO (recog_data
.operand
[2]);
939 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
940 if ((src1
== x
|| src2
== x
)
941 && (dest
== src1
|| dest
== src2
))
948 FPOPd %fx, %fx, %fx */
951 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
956 case CODE_FOR_sqrtdf2
:
957 dest
= REGNO (recog_data
.operand
[0]);
958 src1
= REGNO (recog_data
.operand
[1]);
962 if (src1
== x
&& dest
== src1
)
971 /* Look for a single-word load into an integer register. */
972 else if (sparc_fix_ut699
973 && NONJUMP_INSN_P (insn
)
974 && (set
= single_set (insn
)) != NULL_RTX
975 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
976 && mem_ref (SET_SRC (set
)) != NULL_RTX
977 && REG_P (SET_DEST (set
))
978 && REGNO (SET_DEST (set
)) < 32)
980 /* There is no problem if the second memory access has a data
981 dependency on the first single-cycle load. */
982 rtx x
= SET_DEST (set
);
984 next
= next_active_insn (insn
);
987 /* If the insn is a branch, then it cannot be problematic. */
988 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
991 /* Look for a second memory access to/from an integer register. */
992 if ((set
= single_set (next
)) != NULL_RTX
)
994 rtx src
= SET_SRC (set
);
995 rtx dest
= SET_DEST (set
);
998 /* LDD is affected. */
999 if ((mem
= mem_ref (src
)) != NULL_RTX
1001 && REGNO (dest
) < 32
1002 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1005 /* STD is *not* affected. */
1006 else if (MEM_P (dest
)
1007 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1008 && (src
== CONST0_RTX (GET_MODE (dest
))
1011 && REGNO (src
) != REGNO (x
)))
1012 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1017 /* Look for a single-word load/operation into an FP register. */
1018 else if (sparc_fix_ut699
1019 && NONJUMP_INSN_P (insn
)
1020 && (set
= single_set (insn
)) != NULL_RTX
1021 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1022 && REG_P (SET_DEST (set
))
1023 && REGNO (SET_DEST (set
)) > 31)
1025 /* Number of instructions in the problematic window. */
1026 const int n_insns
= 4;
1027 /* The problematic combination is with the sibling FP register. */
1028 const unsigned int x
= REGNO (SET_DEST (set
));
1029 const unsigned int y
= x
^ 1;
1033 next
= next_active_insn (insn
);
1036 /* If the insn is a branch, then it cannot be problematic. */
1037 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1040 /* Look for a second load/operation into the sibling FP register. */
1041 if (!((set
= single_set (next
)) != NULL_RTX
1042 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1043 && REG_P (SET_DEST (set
))
1044 && REGNO (SET_DEST (set
)) == y
))
1047 /* Look for a (possible) store from the FP register in the next N
1048 instructions, but bail out if it is again modified or if there
1049 is a store from the sibling FP register before this store. */
1050 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1054 after
= next_active_insn (after
);
1058 /* This is a branch with an empty delay slot. */
1059 if (!NONJUMP_INSN_P (after
))
1066 /* This is a branch with a filled delay slot. */
1067 else if (rtx_sequence
*seq
=
1068 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1073 after
= seq
->insn (1);
1075 /* This is a regular instruction. */
1079 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1081 const rtx src
= SET_SRC (set
);
1082 const rtx dest
= SET_DEST (set
);
1083 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1085 /* If the FP register is again modified before the store,
1086 then the store isn't affected. */
1088 && (REGNO (dest
) == x
1089 || (REGNO (dest
) == y
&& size
== 8)))
1092 if (MEM_P (dest
) && REG_P (src
))
1094 /* If there is a store from the sibling FP register
1095 before the store, then the store is not affected. */
1096 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1099 /* Otherwise, the store is affected. */
1100 if (REGNO (src
) == x
&& size
== 4)
1108 /* If we have a branch in the first M instructions, then we
1109 cannot see the (M+2)th instruction so we play safe. */
1110 if (branch_p
&& i
<= (n_insns
- 2))
1119 next
= NEXT_INSN (insn
);
1122 emit_insn_before (gen_nop (), next
);
1130 const pass_data pass_data_work_around_errata
=
1132 RTL_PASS
, /* type */
1133 "errata", /* name */
1134 OPTGROUP_NONE
, /* optinfo_flags */
1135 TV_MACH_DEP
, /* tv_id */
1136 0, /* properties_required */
1137 0, /* properties_provided */
1138 0, /* properties_destroyed */
1139 0, /* todo_flags_start */
1140 0, /* todo_flags_finish */
1143 class pass_work_around_errata
: public rtl_opt_pass
1146 pass_work_around_errata(gcc::context
*ctxt
)
1147 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1150 /* opt_pass methods: */
1151 virtual bool gate (function
*)
1153 /* The only errata we handle are those of the AT697F and UT699. */
1154 return sparc_fix_at697f
!= 0 || sparc_fix_ut699
!= 0;
1157 virtual unsigned int execute (function
*)
1159 return sparc_do_work_around_errata ();
1162 }; // class pass_work_around_errata
1167 make_pass_work_around_errata (gcc::context
*ctxt
)
1169 return new pass_work_around_errata (ctxt
);
1172 /* Helpers for TARGET_DEBUG_OPTIONS. */
1174 dump_target_flag_bits (const int flags
)
1176 if (flags
& MASK_64BIT
)
1177 fprintf (stderr
, "64BIT ");
1178 if (flags
& MASK_APP_REGS
)
1179 fprintf (stderr
, "APP_REGS ");
1180 if (flags
& MASK_FASTER_STRUCTS
)
1181 fprintf (stderr
, "FASTER_STRUCTS ");
1182 if (flags
& MASK_FLAT
)
1183 fprintf (stderr
, "FLAT ");
1184 if (flags
& MASK_FMAF
)
1185 fprintf (stderr
, "FMAF ");
1186 if (flags
& MASK_FPU
)
1187 fprintf (stderr
, "FPU ");
1188 if (flags
& MASK_HARD_QUAD
)
1189 fprintf (stderr
, "HARD_QUAD ");
1190 if (flags
& MASK_POPC
)
1191 fprintf (stderr
, "POPC ");
1192 if (flags
& MASK_PTR64
)
1193 fprintf (stderr
, "PTR64 ");
1194 if (flags
& MASK_STACK_BIAS
)
1195 fprintf (stderr
, "STACK_BIAS ");
1196 if (flags
& MASK_UNALIGNED_DOUBLES
)
1197 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1198 if (flags
& MASK_V8PLUS
)
1199 fprintf (stderr
, "V8PLUS ");
1200 if (flags
& MASK_VIS
)
1201 fprintf (stderr
, "VIS ");
1202 if (flags
& MASK_VIS2
)
1203 fprintf (stderr
, "VIS2 ");
1204 if (flags
& MASK_VIS3
)
1205 fprintf (stderr
, "VIS3 ");
1206 if (flags
& MASK_VIS4
)
1207 fprintf (stderr
, "VIS4 ");
1208 if (flags
& MASK_CBCOND
)
1209 fprintf (stderr
, "CBCOND ");
1210 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1211 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1212 if (flags
& MASK_SPARCLET
)
1213 fprintf (stderr
, "SPARCLET ");
1214 if (flags
& MASK_SPARCLITE
)
1215 fprintf (stderr
, "SPARCLITE ");
1216 if (flags
& MASK_V8
)
1217 fprintf (stderr
, "V8 ");
1218 if (flags
& MASK_V9
)
1219 fprintf (stderr
, "V9 ");
1223 dump_target_flags (const char *prefix
, const int flags
)
1225 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1226 dump_target_flag_bits (flags
);
1227 fprintf(stderr
, "]\n");
1230 /* Validate and override various options, and do some machine dependent
1234 sparc_option_override (void)
1236 static struct code_model
{
1237 const char *const name
;
1238 const enum cmodel value
;
1239 } const cmodels
[] = {
1241 { "medlow", CM_MEDLOW
},
1242 { "medmid", CM_MEDMID
},
1243 { "medany", CM_MEDANY
},
1244 { "embmedany", CM_EMBMEDANY
},
1245 { NULL
, (enum cmodel
) 0 }
1247 const struct code_model
*cmodel
;
1248 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1249 static struct cpu_default
{
1251 const enum processor_type processor
;
1252 } const cpu_default
[] = {
1253 /* There must be one entry here for each TARGET_CPU value. */
1254 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1255 { TARGET_CPU_v8
, PROCESSOR_V8
},
1256 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1257 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1258 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1259 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1260 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1261 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1262 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1263 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1264 { TARGET_CPU_v9
, PROCESSOR_V9
},
1265 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1266 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1267 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1268 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1269 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1270 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1271 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1272 { -1, PROCESSOR_V7
}
1274 const struct cpu_default
*def
;
1275 /* Table of values for -m{cpu,tune}=. This must match the order of
1276 the enum processor_type in sparc-opts.h. */
1277 static struct cpu_table
{
1278 const char *const name
;
1281 } const cpu_table
[] = {
1282 { "v7", MASK_ISA
, 0 },
1283 { "cypress", MASK_ISA
, 0 },
1284 { "v8", MASK_ISA
, MASK_V8
},
1285 /* TI TMS390Z55 supersparc */
1286 { "supersparc", MASK_ISA
, MASK_V8
},
1287 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1288 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1289 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1290 { "leon3v7", MASK_ISA
, MASK_LEON3
|MASK_FPU
},
1291 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1292 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1293 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1294 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1295 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1296 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1297 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1298 /* TEMIC sparclet */
1299 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1300 { "v9", MASK_ISA
, MASK_V9
},
1301 /* UltraSPARC I, II, IIi */
1302 { "ultrasparc", MASK_ISA
,
1303 /* Although insns using %y are deprecated, it is a clear win. */
1304 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1305 /* UltraSPARC III */
1306 /* ??? Check if %y issue still holds true. */
1307 { "ultrasparc3", MASK_ISA
,
1308 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1310 { "niagara", MASK_ISA
,
1311 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1313 { "niagara2", MASK_ISA
,
1314 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1316 { "niagara3", MASK_ISA
,
1317 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
1319 { "niagara4", MASK_ISA
,
1320 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1322 { "niagara7", MASK_ISA
,
1323 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
},
1325 const struct cpu_table
*cpu
;
1329 if (sparc_debug_string
!= NULL
)
1334 p
= ASTRDUP (sparc_debug_string
);
1335 while ((q
= strtok (p
, ",")) != NULL
)
1349 if (! strcmp (q
, "all"))
1350 mask
= MASK_DEBUG_ALL
;
1351 else if (! strcmp (q
, "options"))
1352 mask
= MASK_DEBUG_OPTIONS
;
1354 error ("unknown -mdebug-%s switch", q
);
1357 sparc_debug
&= ~mask
;
1359 sparc_debug
|= mask
;
1363 if (TARGET_DEBUG_OPTIONS
)
1365 dump_target_flags("Initial target_flags", target_flags
);
1366 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1369 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1370 SUBTARGET_OVERRIDE_OPTIONS
;
1373 #ifndef SPARC_BI_ARCH
1374 /* Check for unsupported architecture size. */
1375 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1376 error ("%s is not supported by this configuration",
1377 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1380 /* We force all 64bit archs to use 128 bit long double */
1381 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1383 error ("-mlong-double-64 not allowed with -m64");
1384 target_flags
|= MASK_LONG_DOUBLE_128
;
1387 /* Code model selection. */
1388 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1390 #ifdef SPARC_BI_ARCH
1392 sparc_cmodel
= CM_32
;
1395 if (sparc_cmodel_string
!= NULL
)
1399 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1400 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1402 if (cmodel
->name
== NULL
)
1403 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1405 sparc_cmodel
= cmodel
->value
;
1408 error ("-mcmodel= is not supported on 32 bit systems");
1411 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1412 for (i
= 8; i
< 16; i
++)
1413 if (!call_used_regs
[i
])
1415 error ("-fcall-saved-REG is not supported for out registers");
1416 call_used_regs
[i
] = 1;
1419 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1421 /* Set the default CPU. */
1422 if (!global_options_set
.x_sparc_cpu_and_features
)
1424 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1425 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1427 gcc_assert (def
->cpu
!= -1);
1428 sparc_cpu_and_features
= def
->processor
;
1431 if (!global_options_set
.x_sparc_cpu
)
1432 sparc_cpu
= sparc_cpu_and_features
;
1434 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1436 if (TARGET_DEBUG_OPTIONS
)
1438 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1439 fprintf (stderr
, "sparc_cpu: %s\n",
1440 cpu_table
[(int) sparc_cpu
].name
);
1441 dump_target_flags ("cpu->disable", cpu
->disable
);
1442 dump_target_flags ("cpu->enable", cpu
->enable
);
1445 target_flags
&= ~cpu
->disable
;
1446 target_flags
|= (cpu
->enable
1447 #ifndef HAVE_AS_FMAF_HPC_VIS3
1448 & ~(MASK_FMAF
| MASK_VIS3
)
1450 #ifndef HAVE_AS_SPARC4
1453 #ifndef HAVE_AS_SPARC5_VIS4
1456 #ifndef HAVE_AS_LEON
1457 & ~(MASK_LEON
| MASK_LEON3
)
1461 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1462 the processor default. */
1463 if (target_flags_explicit
& MASK_FPU
)
1464 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1466 /* -mvis2 implies -mvis */
1468 target_flags
|= MASK_VIS
;
1470 /* -mvis3 implies -mvis2 and -mvis */
1472 target_flags
|= MASK_VIS2
| MASK_VIS
;
1474 /* -mvis4 implies -mvis3, -mvis2 and -mvis */
1476 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1478 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4 or -mfmaf if FPU is
1481 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1484 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1486 -m64 also implies v9. */
1487 if (TARGET_VIS
|| TARGET_ARCH64
)
1489 target_flags
|= MASK_V9
;
1490 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1493 /* -mvis also implies -mv8plus on 32-bit */
1494 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1495 target_flags
|= MASK_V8PLUS
;
1497 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1498 if (TARGET_V9
&& TARGET_ARCH32
)
1499 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1501 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1502 if (! TARGET_V9
|| TARGET_ARCH64
)
1503 target_flags
&= ~MASK_V8PLUS
;
1505 /* Don't use stack biasing in 32 bit mode. */
1507 target_flags
&= ~MASK_STACK_BIAS
;
1509 /* Supply a default value for align_functions. */
1510 if (align_functions
== 0
1511 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1512 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1513 || sparc_cpu
== PROCESSOR_NIAGARA
1514 || sparc_cpu
== PROCESSOR_NIAGARA2
1515 || sparc_cpu
== PROCESSOR_NIAGARA3
1516 || sparc_cpu
== PROCESSOR_NIAGARA4
1517 || sparc_cpu
== PROCESSOR_NIAGARA7
))
1518 align_functions
= 32;
1520 /* Validate PCC_STRUCT_RETURN. */
1521 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1522 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1524 /* Only use .uaxword when compiling for a 64-bit target. */
1526 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1528 /* Do various machine dependent initializations. */
1529 sparc_init_modes ();
1531 /* Set up function hooks. */
1532 init_machine_status
= sparc_init_machine_status
;
1537 case PROCESSOR_CYPRESS
:
1538 sparc_costs
= &cypress_costs
;
1541 case PROCESSOR_SPARCLITE
:
1542 case PROCESSOR_SUPERSPARC
:
1543 sparc_costs
= &supersparc_costs
;
1545 case PROCESSOR_F930
:
1546 case PROCESSOR_F934
:
1547 case PROCESSOR_HYPERSPARC
:
1548 case PROCESSOR_SPARCLITE86X
:
1549 sparc_costs
= &hypersparc_costs
;
1551 case PROCESSOR_LEON
:
1552 sparc_costs
= &leon_costs
;
1554 case PROCESSOR_LEON3
:
1555 case PROCESSOR_LEON3V7
:
1556 sparc_costs
= &leon3_costs
;
1558 case PROCESSOR_SPARCLET
:
1559 case PROCESSOR_TSC701
:
1560 sparc_costs
= &sparclet_costs
;
1563 case PROCESSOR_ULTRASPARC
:
1564 sparc_costs
= &ultrasparc_costs
;
1566 case PROCESSOR_ULTRASPARC3
:
1567 sparc_costs
= &ultrasparc3_costs
;
1569 case PROCESSOR_NIAGARA
:
1570 sparc_costs
= &niagara_costs
;
1572 case PROCESSOR_NIAGARA2
:
1573 sparc_costs
= &niagara2_costs
;
1575 case PROCESSOR_NIAGARA3
:
1576 sparc_costs
= &niagara3_costs
;
1578 case PROCESSOR_NIAGARA4
:
1579 sparc_costs
= &niagara4_costs
;
1581 case PROCESSOR_NIAGARA7
:
1582 sparc_costs
= &niagara7_costs
;
1584 case PROCESSOR_NATIVE
:
1588 if (sparc_memory_model
== SMM_DEFAULT
)
1590 /* Choose the memory model for the operating system. */
1591 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1592 if (os_default
!= SMM_DEFAULT
)
1593 sparc_memory_model
= os_default
;
1594 /* Choose the most relaxed model for the processor. */
1596 sparc_memory_model
= SMM_RMO
;
1597 else if (TARGET_LEON3
)
1598 sparc_memory_model
= SMM_TSO
;
1599 else if (TARGET_LEON
)
1600 sparc_memory_model
= SMM_SC
;
1602 sparc_memory_model
= SMM_PSO
;
1604 sparc_memory_model
= SMM_SC
;
1607 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1608 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1609 target_flags
|= MASK_LONG_DOUBLE_128
;
1612 if (TARGET_DEBUG_OPTIONS
)
1613 dump_target_flags ("Final target_flags", target_flags
);
1615 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
1616 can run at the same time. More important, it is the threshold
1617 defining when additional prefetches will be dropped by the
1620 The UltraSPARC-III features a documented prefetch queue with a
1621 size of 8. Additional prefetches issued in the cpu are
1624 Niagara processors are different. In these processors prefetches
1625 are handled much like regular loads. The L1 miss buffer is 32
1626 entries, but prefetches start getting affected when 30 entries
1627 become occupied. That occupation could be a mix of regular loads
1628 and prefetches though. And that buffer is shared by all threads.
1629 Once the threshold is reached, if the core is running a single
1630 thread the prefetch will retry. If more than one thread is
1631 running, the prefetch will be dropped.
1633 All this makes it very difficult to determine how many
1634 simultaneous prefetches can be issued simultaneously, even in a
1635 single-threaded program. Experimental results show that setting
1636 this parameter to 32 works well when the number of threads is not
1638 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1639 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1640 || sparc_cpu
== PROCESSOR_NIAGARA
1641 || sparc_cpu
== PROCESSOR_NIAGARA2
1642 || sparc_cpu
== PROCESSOR_NIAGARA3
1643 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1645 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1646 ? 8 : (sparc_cpu
== PROCESSOR_NIAGARA7
1648 global_options
.x_param_values
,
1649 global_options_set
.x_param_values
);
1651 /* For PARAM_L1_CACHE_LINE_SIZE we use the default 32 bytes (see
1652 params.def), so no maybe_set_param_value is needed.
1654 The Oracle SPARC Architecture (previously the UltraSPARC
1655 Architecture) specification states that when a PREFETCH[A]
1656 instruction is executed an implementation-specific amount of data
1657 is prefetched, and that it is at least 64 bytes long (aligned to
1660 However, this is not correct. The M7 (and implementations prior
1661 to that) does not guarantee a 64B prefetch into a cache if the
1662 line size is smaller. A single cache line is all that is ever
1663 prefetched. So for the M7, where the L1D$ has 32B lines and the
1664 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
1665 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
1666 is a read_n prefetch, which is the only type which allocates to
1669 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
1670 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
1671 Niagara processors feature a L1D$ of 16KB. */
1672 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
1673 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1674 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1675 || sparc_cpu
== PROCESSOR_NIAGARA
1676 || sparc_cpu
== PROCESSOR_NIAGARA2
1677 || sparc_cpu
== PROCESSOR_NIAGARA3
1678 || sparc_cpu
== PROCESSOR_NIAGARA4
1679 || sparc_cpu
== PROCESSOR_NIAGARA7
)
1681 global_options
.x_param_values
,
1682 global_options_set
.x_param_values
);
1685 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
1686 that 512 is the default in params.def. */
1687 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
1688 (sparc_cpu
== PROCESSOR_NIAGARA4
1689 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
1691 global_options
.x_param_values
,
1692 global_options_set
.x_param_values
);
1695 /* Disable save slot sharing for call-clobbered registers by default.
1696 The IRA sharing algorithm works on single registers only and this
1697 pessimizes for double floating-point registers. */
1698 if (!global_options_set
.x_flag_ira_share_save_slots
)
1699 flag_ira_share_save_slots
= 0;
1701 /* We register a machine specific pass to work around errata, if any.
1702 The pass mut be scheduled as late as possible so that we have the
1703 (essentially) final form of the insn stream to work on.
1704 Registering the pass must be done at start up. It's convenient to
1706 opt_pass
*errata_pass
= make_pass_work_around_errata (g
);
1707 struct register_pass_info insert_pass_work_around_errata
=
1709 errata_pass
, /* pass */
1710 "dbr", /* reference_pass_name */
1711 1, /* ref_pass_instance_number */
1712 PASS_POS_INSERT_AFTER
/* po_op */
1714 register_pass (&insert_pass_work_around_errata
);
1717 /* Miscellaneous utilities. */
1719 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1720 or branch on register contents instructions. */
1723 v9_regcmp_p (enum rtx_code code
)
1725 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1726 || code
== LE
|| code
== GT
);
1729 /* Nonzero if OP is a floating point constant which can
1730 be loaded into an integer register using a single
1731 sethi instruction. */
1736 if (GET_CODE (op
) == CONST_DOUBLE
)
1740 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1741 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1747 /* Nonzero if OP is a floating point constant which can
1748 be loaded into an integer register using a single
1754 if (GET_CODE (op
) == CONST_DOUBLE
)
1758 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1759 return SPARC_SIMM13_P (i
);
1765 /* Nonzero if OP is a floating point constant which can
1766 be loaded into an integer register using a high/losum
1767 instruction sequence. */
1770 fp_high_losum_p (rtx op
)
1772 /* The constraints calling this should only be in
1773 SFmode move insns, so any constant which cannot
1774 be moved using a single insn will do. */
1775 if (GET_CODE (op
) == CONST_DOUBLE
)
1779 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1780 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1786 /* Return true if the address of LABEL can be loaded by means of the
1787 mov{si,di}_pic_label_ref patterns in PIC mode. */
1790 can_use_mov_pic_label_ref (rtx label
)
1792 /* VxWorks does not impose a fixed gap between segments; the run-time
1793 gap can be different from the object-file gap. We therefore can't
1794 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1795 are absolutely sure that X is in the same segment as the GOT.
1796 Unfortunately, the flexibility of linker scripts means that we
1797 can't be sure of that in general, so assume that GOT-relative
1798 accesses are never valid on VxWorks. */
1799 if (TARGET_VXWORKS_RTP
)
1802 /* Similarly, if the label is non-local, it might end up being placed
1803 in a different section than the current one; now mov_pic_label_ref
1804 requires the label and the code to be in the same section. */
1805 if (LABEL_REF_NONLOCAL_P (label
))
1808 /* Finally, if we are reordering basic blocks and partition into hot
1809 and cold sections, this might happen for any label. */
1810 if (flag_reorder_blocks_and_partition
)
1816 /* Expand a move instruction. Return true if all work is done. */
1819 sparc_expand_move (machine_mode mode
, rtx
*operands
)
1821 /* Handle sets of MEM first. */
1822 if (GET_CODE (operands
[0]) == MEM
)
1824 /* 0 is a register (or a pair of registers) on SPARC. */
1825 if (register_or_zero_operand (operands
[1], mode
))
1828 if (!reload_in_progress
)
1830 operands
[0] = validize_mem (operands
[0]);
1831 operands
[1] = force_reg (mode
, operands
[1]);
1835 /* Fixup TLS cases. */
1837 && CONSTANT_P (operands
[1])
1838 && sparc_tls_referenced_p (operands
[1]))
1840 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1844 /* Fixup PIC cases. */
1845 if (flag_pic
&& CONSTANT_P (operands
[1]))
1847 if (pic_address_needs_scratch (operands
[1]))
1848 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1850 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1851 if (GET_CODE (operands
[1]) == LABEL_REF
1852 && can_use_mov_pic_label_ref (operands
[1]))
1856 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1862 gcc_assert (TARGET_ARCH64
);
1863 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1868 if (symbolic_operand (operands
[1], mode
))
1871 = sparc_legitimize_pic_address (operands
[1],
1873 ? operands
[0] : NULL_RTX
);
1878 /* If we are trying to toss an integer constant into FP registers,
1879 or loading a FP or vector constant, force it into memory. */
1880 if (CONSTANT_P (operands
[1])
1881 && REG_P (operands
[0])
1882 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1883 || SCALAR_FLOAT_MODE_P (mode
)
1884 || VECTOR_MODE_P (mode
)))
1886 /* emit_group_store will send such bogosity to us when it is
1887 not storing directly into memory. So fix this up to avoid
1888 crashes in output_constant_pool. */
1889 if (operands
[1] == const0_rtx
)
1890 operands
[1] = CONST0_RTX (mode
);
1892 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1893 always other regs. */
1894 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1895 && (const_zero_operand (operands
[1], mode
)
1896 || const_all_ones_operand (operands
[1], mode
)))
1899 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1900 /* We are able to build any SF constant in integer registers
1901 with at most 2 instructions. */
1903 /* And any DF constant in integer registers. */
1905 && ! can_create_pseudo_p ())))
1908 operands
[1] = force_const_mem (mode
, operands
[1]);
1909 if (!reload_in_progress
)
1910 operands
[1] = validize_mem (operands
[1]);
1914 /* Accept non-constants and valid constants unmodified. */
1915 if (!CONSTANT_P (operands
[1])
1916 || GET_CODE (operands
[1]) == HIGH
1917 || input_operand (operands
[1], mode
))
1923 /* All QImode constants require only one insn, so proceed. */
1928 sparc_emit_set_const32 (operands
[0], operands
[1]);
1932 /* input_operand should have filtered out 32-bit mode. */
1933 sparc_emit_set_const64 (operands
[0], operands
[1]);
1939 /* TImode isn't available in 32-bit mode. */
1940 split_double (operands
[1], &high
, &low
);
1941 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1943 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1955 /* Load OP1, a 32-bit constant, into OP0, a register.
1956 We know it can't be done in one insn when we get
1957 here, the move expander guarantees this. */
1960 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1962 machine_mode mode
= GET_MODE (op0
);
1965 if (can_create_pseudo_p ())
1966 temp
= gen_reg_rtx (mode
);
1968 if (GET_CODE (op1
) == CONST_INT
)
1970 gcc_assert (!small_int_operand (op1
, mode
)
1971 && !const_high_operand (op1
, mode
));
1973 /* Emit them as real moves instead of a HIGH/LO_SUM,
1974 this way CSE can see everything and reuse intermediate
1975 values if it wants. */
1976 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
1977 & ~(HOST_WIDE_INT
) 0x3ff)));
1979 emit_insn (gen_rtx_SET (op0
,
1980 gen_rtx_IOR (mode
, temp
,
1981 GEN_INT (INTVAL (op1
) & 0x3ff))));
1985 /* A symbol, emit in the traditional way. */
1986 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
1987 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1991 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1992 If TEMP is nonzero, we are forbidden to use any other scratch
1993 registers. Otherwise, we are allowed to generate them as needed.
1995 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1996 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1999 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2001 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
2004 if (temp
&& GET_MODE (temp
) == TImode
)
2007 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2010 /* SPARC-V9 code-model support. */
2011 switch (sparc_cmodel
)
2014 /* The range spanned by all instructions in the object is less
2015 than 2^31 bytes (2GB) and the distance from any instruction
2016 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2017 than 2^31 bytes (2GB).
2019 The executable must be in the low 4TB of the virtual address
2022 sethi %hi(symbol), %temp1
2023 or %temp1, %lo(symbol), %reg */
2025 temp1
= temp
; /* op0 is allowed. */
2027 temp1
= gen_reg_rtx (DImode
);
2029 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2030 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2034 /* The range spanned by all instructions in the object is less
2035 than 2^31 bytes (2GB) and the distance from any instruction
2036 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2037 than 2^31 bytes (2GB).
2039 The executable must be in the low 16TB of the virtual address
2042 sethi %h44(symbol), %temp1
2043 or %temp1, %m44(symbol), %temp2
2044 sllx %temp2, 12, %temp3
2045 or %temp3, %l44(symbol), %reg */
2050 temp3
= temp
; /* op0 is allowed. */
2054 temp1
= gen_reg_rtx (DImode
);
2055 temp2
= gen_reg_rtx (DImode
);
2056 temp3
= gen_reg_rtx (DImode
);
2059 emit_insn (gen_seth44 (temp1
, op1
));
2060 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2061 emit_insn (gen_rtx_SET (temp3
,
2062 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2063 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2067 /* The range spanned by all instructions in the object is less
2068 than 2^31 bytes (2GB) and the distance from any instruction
2069 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2070 than 2^31 bytes (2GB).
2072 The executable can be placed anywhere in the virtual address
2075 sethi %hh(symbol), %temp1
2076 sethi %lm(symbol), %temp2
2077 or %temp1, %hm(symbol), %temp3
2078 sllx %temp3, 32, %temp4
2079 or %temp4, %temp2, %temp5
2080 or %temp5, %lo(symbol), %reg */
2083 /* It is possible that one of the registers we got for operands[2]
2084 might coincide with that of operands[0] (which is why we made
2085 it TImode). Pick the other one to use as our scratch. */
2086 if (rtx_equal_p (temp
, op0
))
2088 gcc_assert (ti_temp
);
2089 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2092 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2099 temp1
= gen_reg_rtx (DImode
);
2100 temp2
= gen_reg_rtx (DImode
);
2101 temp3
= gen_reg_rtx (DImode
);
2102 temp4
= gen_reg_rtx (DImode
);
2103 temp5
= gen_reg_rtx (DImode
);
2106 emit_insn (gen_sethh (temp1
, op1
));
2107 emit_insn (gen_setlm (temp2
, op1
));
2108 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2109 emit_insn (gen_rtx_SET (temp4
,
2110 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2111 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2112 emit_insn (gen_setlo (op0
, temp5
, op1
));
2116 /* Old old old backwards compatibility kruft here.
2117 Essentially it is MEDLOW with a fixed 64-bit
2118 virtual base added to all data segment addresses.
2119 Text-segment stuff is computed like MEDANY, we can't
2120 reuse the code above because the relocation knobs
2123 Data segment: sethi %hi(symbol), %temp1
2124 add %temp1, EMBMEDANY_BASE_REG, %temp2
2125 or %temp2, %lo(symbol), %reg */
2126 if (data_segment_operand (op1
, GET_MODE (op1
)))
2130 temp1
= temp
; /* op0 is allowed. */
2135 temp1
= gen_reg_rtx (DImode
);
2136 temp2
= gen_reg_rtx (DImode
);
2139 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2140 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2141 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2144 /* Text segment: sethi %uhi(symbol), %temp1
2145 sethi %hi(symbol), %temp2
2146 or %temp1, %ulo(symbol), %temp3
2147 sllx %temp3, 32, %temp4
2148 or %temp4, %temp2, %temp5
2149 or %temp5, %lo(symbol), %reg */
2154 /* It is possible that one of the registers we got for operands[2]
2155 might coincide with that of operands[0] (which is why we made
2156 it TImode). Pick the other one to use as our scratch. */
2157 if (rtx_equal_p (temp
, op0
))
2159 gcc_assert (ti_temp
);
2160 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2163 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2170 temp1
= gen_reg_rtx (DImode
);
2171 temp2
= gen_reg_rtx (DImode
);
2172 temp3
= gen_reg_rtx (DImode
);
2173 temp4
= gen_reg_rtx (DImode
);
2174 temp5
= gen_reg_rtx (DImode
);
2177 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2178 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2179 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2180 emit_insn (gen_rtx_SET (temp4
,
2181 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2182 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2183 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2192 /* These avoid problems when cross compiling. If we do not
2193 go through all this hair then the optimizer will see
2194 invalid REG_EQUAL notes or in some cases none at all. */
2195 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2196 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2197 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2198 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2200 /* The optimizer is not to assume anything about exactly
2201 which bits are set for a HIGH, they are unspecified.
2202 Unfortunately this leads to many missed optimizations
2203 during CSE. We mask out the non-HIGH bits, and matches
2204 a plain movdi, to alleviate this problem. */
2206 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2208 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2212 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2214 return gen_rtx_SET (dest
, GEN_INT (val
));
2218 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2220 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2224 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2226 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2229 /* Worker routines for 64-bit constant formation on arch64.
2230 One of the key things to be doing in these emissions is
2231 to create as many temp REGs as possible. This makes it
2232 possible for half-built constants to be used later when
2233 such values are similar to something required later on.
2234 Without doing this, the optimizer cannot see such
2237 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2238 unsigned HOST_WIDE_INT
, int);
2241 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2242 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2244 unsigned HOST_WIDE_INT high_bits
;
2247 high_bits
= (~low_bits
) & 0xffffffff;
2249 high_bits
= low_bits
;
2251 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2254 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2258 /* If we are XOR'ing with -1, then we should emit a one's complement
2259 instead. This way the combiner will notice logical operations
2260 such as ANDN later on and substitute. */
2261 if ((low_bits
& 0x3ff) == 0x3ff)
2263 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2267 emit_insn (gen_rtx_SET (op0
,
2268 gen_safe_XOR64 (temp
,
2269 (-(HOST_WIDE_INT
)0x400
2270 | (low_bits
& 0x3ff)))));
2275 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2276 unsigned HOST_WIDE_INT
, int);
2279 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2280 unsigned HOST_WIDE_INT high_bits
,
2281 unsigned HOST_WIDE_INT low_immediate
,
2286 if ((high_bits
& 0xfffffc00) != 0)
2288 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2289 if ((high_bits
& ~0xfffffc00) != 0)
2290 emit_insn (gen_rtx_SET (op0
,
2291 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2297 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2301 /* Now shift it up into place. */
2302 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2303 GEN_INT (shift_count
))));
2305 /* If there is a low immediate part piece, finish up by
2306 putting that in as well. */
2307 if (low_immediate
!= 0)
2308 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2311 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2312 unsigned HOST_WIDE_INT
);
2314 /* Full 64-bit constant decomposition. Even though this is the
2315 'worst' case, we still optimize a few things away. */
2317 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2318 unsigned HOST_WIDE_INT high_bits
,
2319 unsigned HOST_WIDE_INT low_bits
)
2323 if (can_create_pseudo_p ())
2324 sub_temp
= gen_reg_rtx (DImode
);
2326 if ((high_bits
& 0xfffffc00) != 0)
2328 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2329 if ((high_bits
& ~0xfffffc00) != 0)
2330 emit_insn (gen_rtx_SET (sub_temp
,
2331 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2337 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2341 if (can_create_pseudo_p ())
2343 rtx temp2
= gen_reg_rtx (DImode
);
2344 rtx temp3
= gen_reg_rtx (DImode
);
2345 rtx temp4
= gen_reg_rtx (DImode
);
2347 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2350 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2351 if ((low_bits
& ~0xfffffc00) != 0)
2353 emit_insn (gen_rtx_SET (temp3
,
2354 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2355 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2359 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2364 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2365 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2366 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2369 /* We are in the middle of reload, so this is really
2370 painful. However we do still make an attempt to
2371 avoid emitting truly stupid code. */
2372 if (low1
!= const0_rtx
)
2374 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2375 GEN_INT (to_shift
))));
2376 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2384 if (low2
!= const0_rtx
)
2386 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2387 GEN_INT (to_shift
))));
2388 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2396 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2397 GEN_INT (to_shift
))));
2398 if (low3
!= const0_rtx
)
2399 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2404 /* Analyze a 64-bit constant for certain properties. */
2405 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2406 unsigned HOST_WIDE_INT
,
2407 int *, int *, int *);
2410 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2411 unsigned HOST_WIDE_INT low_bits
,
2412 int *hbsp
, int *lbsp
, int *abbasp
)
2414 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2417 lowest_bit_set
= highest_bit_set
= -1;
2421 if ((lowest_bit_set
== -1)
2422 && ((low_bits
>> i
) & 1))
2424 if ((highest_bit_set
== -1)
2425 && ((high_bits
>> (32 - i
- 1)) & 1))
2426 highest_bit_set
= (64 - i
- 1);
2429 && ((highest_bit_set
== -1)
2430 || (lowest_bit_set
== -1)));
2436 if ((lowest_bit_set
== -1)
2437 && ((high_bits
>> i
) & 1))
2438 lowest_bit_set
= i
+ 32;
2439 if ((highest_bit_set
== -1)
2440 && ((low_bits
>> (32 - i
- 1)) & 1))
2441 highest_bit_set
= 32 - i
- 1;
2444 && ((highest_bit_set
== -1)
2445 || (lowest_bit_set
== -1)));
2447 /* If there are no bits set this should have gone out
2448 as one instruction! */
2449 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2450 all_bits_between_are_set
= 1;
2451 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2455 if ((low_bits
& (1 << i
)) != 0)
2460 if ((high_bits
& (1 << (i
- 32))) != 0)
2463 all_bits_between_are_set
= 0;
2466 *hbsp
= highest_bit_set
;
2467 *lbsp
= lowest_bit_set
;
2468 *abbasp
= all_bits_between_are_set
;
2471 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2474 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2475 unsigned HOST_WIDE_INT low_bits
)
2477 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2480 || high_bits
== 0xffffffff)
2483 analyze_64bit_constant (high_bits
, low_bits
,
2484 &highest_bit_set
, &lowest_bit_set
,
2485 &all_bits_between_are_set
);
2487 if ((highest_bit_set
== 63
2488 || lowest_bit_set
== 0)
2489 && all_bits_between_are_set
!= 0)
2492 if ((highest_bit_set
- lowest_bit_set
) < 21)
2498 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2499 unsigned HOST_WIDE_INT
,
2502 static unsigned HOST_WIDE_INT
2503 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2504 unsigned HOST_WIDE_INT low_bits
,
2505 int lowest_bit_set
, int shift
)
2507 HOST_WIDE_INT hi
, lo
;
2509 if (lowest_bit_set
< 32)
2511 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2512 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2517 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2519 gcc_assert (! (hi
& lo
));
2523 /* Here we are sure to be arch64 and this is an integer constant
2524 being loaded into a register. Emit the most efficient
2525 insn sequence possible. Detection of all the 1-insn cases
2526 has been done already. */
2528 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2530 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2531 int lowest_bit_set
, highest_bit_set
;
2532 int all_bits_between_are_set
;
2535 /* Sanity check that we know what we are working with. */
2536 gcc_assert (TARGET_ARCH64
2537 && (GET_CODE (op0
) == SUBREG
2538 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2540 if (! can_create_pseudo_p ())
2543 if (GET_CODE (op1
) != CONST_INT
)
2545 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2550 temp
= gen_reg_rtx (DImode
);
2552 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2553 low_bits
= (INTVAL (op1
) & 0xffffffff);
2555 /* low_bits bits 0 --> 31
2556 high_bits bits 32 --> 63 */
2558 analyze_64bit_constant (high_bits
, low_bits
,
2559 &highest_bit_set
, &lowest_bit_set
,
2560 &all_bits_between_are_set
);
2562 /* First try for a 2-insn sequence. */
2564 /* These situations are preferred because the optimizer can
2565 * do more things with them:
2567 * sllx %reg, shift, %reg
2569 * srlx %reg, shift, %reg
2570 * 3) mov some_small_const, %reg
2571 * sllx %reg, shift, %reg
2573 if (((highest_bit_set
== 63
2574 || lowest_bit_set
== 0)
2575 && all_bits_between_are_set
!= 0)
2576 || ((highest_bit_set
- lowest_bit_set
) < 12))
2578 HOST_WIDE_INT the_const
= -1;
2579 int shift
= lowest_bit_set
;
2581 if ((highest_bit_set
!= 63
2582 && lowest_bit_set
!= 0)
2583 || all_bits_between_are_set
== 0)
2586 create_simple_focus_bits (high_bits
, low_bits
,
2589 else if (lowest_bit_set
== 0)
2590 shift
= -(63 - highest_bit_set
);
2592 gcc_assert (SPARC_SIMM13_P (the_const
));
2593 gcc_assert (shift
!= 0);
2595 emit_insn (gen_safe_SET64 (temp
, the_const
));
2597 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
2600 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
2601 GEN_INT (-shift
))));
2605 /* Now a range of 22 or less bits set somewhere.
2606 * 1) sethi %hi(focus_bits), %reg
2607 * sllx %reg, shift, %reg
2608 * 2) sethi %hi(focus_bits), %reg
2609 * srlx %reg, shift, %reg
2611 if ((highest_bit_set
- lowest_bit_set
) < 21)
2613 unsigned HOST_WIDE_INT focus_bits
=
2614 create_simple_focus_bits (high_bits
, low_bits
,
2615 lowest_bit_set
, 10);
2617 gcc_assert (SPARC_SETHI_P (focus_bits
));
2618 gcc_assert (lowest_bit_set
!= 10);
2620 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2622 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2623 if (lowest_bit_set
< 10)
2624 emit_insn (gen_rtx_SET (op0
,
2625 gen_rtx_LSHIFTRT (DImode
, temp
,
2626 GEN_INT (10 - lowest_bit_set
))));
2627 else if (lowest_bit_set
> 10)
2628 emit_insn (gen_rtx_SET (op0
,
2629 gen_rtx_ASHIFT (DImode
, temp
,
2630 GEN_INT (lowest_bit_set
- 10))));
2634 /* 1) sethi %hi(low_bits), %reg
2635 * or %reg, %lo(low_bits), %reg
2636 * 2) sethi %hi(~low_bits), %reg
2637 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2640 || high_bits
== 0xffffffff)
2642 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2643 (high_bits
== 0xffffffff));
2647 /* Now, try 3-insn sequences. */
2649 /* 1) sethi %hi(high_bits), %reg
2650 * or %reg, %lo(high_bits), %reg
2651 * sllx %reg, 32, %reg
2655 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2659 /* We may be able to do something quick
2660 when the constant is negated, so try that. */
2661 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2662 (~low_bits
) & 0xfffffc00))
2664 /* NOTE: The trailing bits get XOR'd so we need the
2665 non-negated bits, not the negated ones. */
2666 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2668 if ((((~high_bits
) & 0xffffffff) == 0
2669 && ((~low_bits
) & 0x80000000) == 0)
2670 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2671 && ((~low_bits
) & 0x80000000) != 0))
2673 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2675 if ((SPARC_SETHI_P (fast_int
)
2676 && (~high_bits
& 0xffffffff) == 0)
2677 || SPARC_SIMM13_P (fast_int
))
2678 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2680 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2685 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2686 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2687 sparc_emit_set_const64 (temp
, negated_const
);
2690 /* If we are XOR'ing with -1, then we should emit a one's complement
2691 instead. This way the combiner will notice logical operations
2692 such as ANDN later on and substitute. */
2693 if (trailing_bits
== 0x3ff)
2695 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2699 emit_insn (gen_rtx_SET (op0
,
2700 gen_safe_XOR64 (temp
,
2701 (-0x400 | trailing_bits
))));
2706 /* 1) sethi %hi(xxx), %reg
2707 * or %reg, %lo(xxx), %reg
2708 * sllx %reg, yyy, %reg
2710 * ??? This is just a generalized version of the low_bits==0
2711 * thing above, FIXME...
2713 if ((highest_bit_set
- lowest_bit_set
) < 32)
2715 unsigned HOST_WIDE_INT focus_bits
=
2716 create_simple_focus_bits (high_bits
, low_bits
,
2719 /* We can't get here in this state. */
2720 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2722 /* So what we know is that the set bits straddle the
2723 middle of the 64-bit word. */
2724 sparc_emit_set_const64_quick2 (op0
, temp
,
2730 /* 1) sethi %hi(high_bits), %reg
2731 * or %reg, %lo(high_bits), %reg
2732 * sllx %reg, 32, %reg
2733 * or %reg, low_bits, %reg
2735 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
2737 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2741 /* The easiest way when all else fails, is full decomposition. */
2742 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2745 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2746 return the mode to be used for the comparison. For floating-point,
2747 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2748 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2749 processing is needed. */
2752 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2754 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2780 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2781 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2783 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2784 return CCX_NOOVmode
;
2790 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2797 /* Emit the compare insn and return the CC reg for a CODE comparison
2798 with operands X and Y. */
2801 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2806 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2809 mode
= SELECT_CC_MODE (code
, x
, y
);
2811 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2812 fcc regs (cse can't tell they're really call clobbered regs and will
2813 remove a duplicate comparison even if there is an intervening function
2814 call - it will then try to reload the cc reg via an int reg which is why
2815 we need the movcc patterns). It is possible to provide the movcc
2816 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2817 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2818 to tell cse that CCFPE mode registers (even pseudos) are call
2821 /* ??? This is an experiment. Rather than making changes to cse which may
2822 or may not be easy/clean, we do our own cse. This is possible because
2823 we will generate hard registers. Cse knows they're call clobbered (it
2824 doesn't know the same thing about pseudos). If we guess wrong, no big
2825 deal, but if we win, great! */
2827 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2828 #if 1 /* experiment */
2831 /* We cycle through the registers to ensure they're all exercised. */
2832 static int next_fcc_reg
= 0;
2833 /* Previous x,y for each fcc reg. */
2834 static rtx prev_args
[4][2];
2836 /* Scan prev_args for x,y. */
2837 for (reg
= 0; reg
< 4; reg
++)
2838 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2843 prev_args
[reg
][0] = x
;
2844 prev_args
[reg
][1] = y
;
2845 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2847 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2850 cc_reg
= gen_reg_rtx (mode
);
2851 #endif /* ! experiment */
2852 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2853 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2855 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2857 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2858 will only result in an unrecognizable insn so no point in asserting. */
2859 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2865 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2868 gen_compare_reg (rtx cmp
)
2870 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2873 /* This function is used for v9 only.
2874 DEST is the target of the Scc insn.
2875 CODE is the code for an Scc's comparison.
2876 X and Y are the values we compare.
2878 This function is needed to turn
2881 (gt (reg:CCX 100 %icc)
2885 (gt:DI (reg:CCX 100 %icc)
2888 IE: The instruction recognizer needs to see the mode of the comparison to
2889 find the right instruction. We could use "gt:DI" right in the
2890 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2893 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2896 && (GET_MODE (x
) == DImode
2897 || GET_MODE (dest
) == DImode
))
2900 /* Try to use the movrCC insns. */
2902 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2904 && v9_regcmp_p (compare_code
))
2909 /* Special case for op0 != 0. This can be done with one instruction if
2912 if (compare_code
== NE
2913 && GET_MODE (dest
) == DImode
2914 && rtx_equal_p (op0
, dest
))
2916 emit_insn (gen_rtx_SET (dest
,
2917 gen_rtx_IF_THEN_ELSE (DImode
,
2918 gen_rtx_fmt_ee (compare_code
, DImode
,
2925 if (reg_overlap_mentioned_p (dest
, op0
))
2927 /* Handle the case where dest == x.
2928 We "early clobber" the result. */
2929 op0
= gen_reg_rtx (GET_MODE (x
));
2930 emit_move_insn (op0
, x
);
2933 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
2934 if (GET_MODE (op0
) != DImode
)
2936 temp
= gen_reg_rtx (DImode
);
2937 convert_move (temp
, op0
, 0);
2941 emit_insn (gen_rtx_SET (dest
,
2942 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2943 gen_rtx_fmt_ee (compare_code
, DImode
,
2951 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2954 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2955 && GET_MODE (x
) != CCX_NOOVmode
);
2957 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
2958 emit_insn (gen_rtx_SET (dest
,
2959 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2960 gen_rtx_fmt_ee (compare_code
,
2961 GET_MODE (x
), x
, y
),
2962 const1_rtx
, dest
)));
2968 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2969 without jumps using the addx/subx instructions. */
2972 emit_scc_insn (rtx operands
[])
2979 /* The quad-word fp compare library routines all return nonzero to indicate
2980 true, which is different from the equivalent libgcc routines, so we must
2981 handle them specially here. */
2982 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2984 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2985 GET_CODE (operands
[1]));
2986 operands
[2] = XEXP (operands
[1], 0);
2987 operands
[3] = XEXP (operands
[1], 1);
2990 code
= GET_CODE (operands
[1]);
2994 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2995 more applications). The exception to this is "reg != 0" which can
2996 be done in one instruction on v9 (so we do it). */
2999 if (GET_MODE (x
) == SImode
)
3003 pat
= gen_seqsidi_special (operands
[0], x
, y
);
3005 pat
= gen_seqsisi_special (operands
[0], x
, y
);
3009 else if (GET_MODE (x
) == DImode
)
3011 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
3019 if (GET_MODE (x
) == SImode
)
3023 pat
= gen_snesidi_special (operands
[0], x
, y
);
3025 pat
= gen_snesisi_special (operands
[0], x
, y
);
3029 else if (GET_MODE (x
) == DImode
)
3033 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
3035 pat
= gen_snedi_special (operands
[0], x
, y
);
3043 && GET_MODE (x
) == DImode
3045 && (code
== GTU
|| code
== LTU
))
3046 && gen_v9_scc (operands
[0], code
, x
, y
))
3049 /* We can do LTU and GEU using the addx/subx instructions too. And
3050 for GTU/LEU, if both operands are registers swap them and fall
3051 back to the easy case. */
3052 if (code
== GTU
|| code
== LEU
)
3054 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3055 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3060 code
= swap_condition (code
);
3065 || (!TARGET_VIS3
&& code
== GEU
))
3067 emit_insn (gen_rtx_SET (operands
[0],
3068 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3069 gen_compare_reg_1 (code
, x
, y
),
3074 /* All the posibilities to use addx/subx based sequences has been
3075 exhausted, try for a 3 instruction sequence using v9 conditional
3077 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3080 /* Nope, do branches. */
3084 /* Emit a conditional jump insn for the v9 architecture using comparison code
3085 CODE and jump target LABEL.
3086 This function exists to take advantage of the v9 brxx insns. */
3089 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3091 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3092 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3093 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3095 gen_rtx_LABEL_REF (VOIDmode
, label
),
3099 /* Emit a conditional jump insn for the UA2011 architecture using
3100 comparison code CODE and jump target LABEL. This function exists
3101 to take advantage of the UA2011 Compare and Branch insns. */
3104 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3108 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3109 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3111 gen_rtx_LABEL_REF (VOIDmode
, label
),
3114 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3118 emit_conditional_branch_insn (rtx operands
[])
3120 /* The quad-word fp compare library routines all return nonzero to indicate
3121 true, which is different from the equivalent libgcc routines, so we must
3122 handle them specially here. */
3123 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3125 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3126 GET_CODE (operands
[0]));
3127 operands
[1] = XEXP (operands
[0], 0);
3128 operands
[2] = XEXP (operands
[0], 1);
3131 /* If we can tell early on that the comparison is against a constant
3132 that won't fit in the 5-bit signed immediate field of a cbcond,
3133 use one of the other v9 conditional branch sequences. */
3135 && GET_CODE (operands
[1]) == REG
3136 && (GET_MODE (operands
[1]) == SImode
3137 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3138 && (GET_CODE (operands
[2]) != CONST_INT
3139 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3141 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3145 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3146 && GET_CODE (operands
[1]) == REG
3147 && GET_MODE (operands
[1]) == DImode
)
3149 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3153 operands
[1] = gen_compare_reg (operands
[0]);
3154 operands
[2] = const0_rtx
;
3155 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3156 operands
[1], operands
[2]);
3157 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3162 /* Generate a DFmode part of a hard TFmode register.
3163 REG is the TFmode hard register, LOW is 1 for the
3164 low 64bit of the register and 0 otherwise.
3167 gen_df_reg (rtx reg
, int low
)
3169 int regno
= REGNO (reg
);
3171 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3172 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3173 return gen_rtx_REG (DFmode
, regno
);
3176 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3177 Unlike normal calls, TFmode operands are passed by reference. It is
3178 assumed that no more than 3 operands are required. */
3181 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3183 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3186 /* We only expect to be called for conversions, unary, and binary ops. */
3187 gcc_assert (nargs
== 2 || nargs
== 3);
3189 for (i
= 0; i
< nargs
; ++i
)
3191 rtx this_arg
= operands
[i
];
3194 /* TFmode arguments and return values are passed by reference. */
3195 if (GET_MODE (this_arg
) == TFmode
)
3197 int force_stack_temp
;
3199 force_stack_temp
= 0;
3200 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3201 force_stack_temp
= 1;
3203 if (GET_CODE (this_arg
) == MEM
3204 && ! force_stack_temp
)
3206 tree expr
= MEM_EXPR (this_arg
);
3208 mark_addressable (expr
);
3209 this_arg
= XEXP (this_arg
, 0);
3211 else if (CONSTANT_P (this_arg
)
3212 && ! force_stack_temp
)
3214 this_slot
= force_const_mem (TFmode
, this_arg
);
3215 this_arg
= XEXP (this_slot
, 0);
3219 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3221 /* Operand 0 is the return value. We'll copy it out later. */
3223 emit_move_insn (this_slot
, this_arg
);
3225 ret_slot
= this_slot
;
3227 this_arg
= XEXP (this_slot
, 0);
3234 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3236 if (GET_MODE (operands
[0]) == TFmode
)
3239 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3240 arg
[0], GET_MODE (arg
[0]),
3241 arg
[1], GET_MODE (arg
[1]));
3243 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3244 arg
[0], GET_MODE (arg
[0]),
3245 arg
[1], GET_MODE (arg
[1]),
3246 arg
[2], GET_MODE (arg
[2]));
3249 emit_move_insn (operands
[0], ret_slot
);
3255 gcc_assert (nargs
== 2);
3257 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3258 GET_MODE (operands
[0]), 1,
3259 arg
[1], GET_MODE (arg
[1]));
3261 if (ret
!= operands
[0])
3262 emit_move_insn (operands
[0], ret
);
3266 /* Expand soft-float TFmode calls to sparc abi routines. */
3269 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3291 emit_soft_tfmode_libcall (func
, 3, operands
);
3295 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3299 gcc_assert (code
== SQRT
);
3302 emit_soft_tfmode_libcall (func
, 2, operands
);
3306 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3313 switch (GET_MODE (operands
[1]))
3326 case FLOAT_TRUNCATE
:
3327 switch (GET_MODE (operands
[0]))
3341 switch (GET_MODE (operands
[1]))
3346 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3356 case UNSIGNED_FLOAT
:
3357 switch (GET_MODE (operands
[1]))
3362 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3373 switch (GET_MODE (operands
[0]))
3387 switch (GET_MODE (operands
[0]))
3404 emit_soft_tfmode_libcall (func
, 2, operands
);
3407 /* Expand a hard-float tfmode operation. All arguments must be in
3411 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3415 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3417 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3418 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3422 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3423 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3424 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3425 operands
[1], operands
[2]);
3428 if (register_operand (operands
[0], VOIDmode
))
3431 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3433 emit_insn (gen_rtx_SET (dest
, op
));
3435 if (dest
!= operands
[0])
3436 emit_move_insn (operands
[0], dest
);
3440 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3442 if (TARGET_HARD_QUAD
)
3443 emit_hard_tfmode_operation (code
, operands
);
3445 emit_soft_tfmode_binop (code
, operands
);
3449 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3451 if (TARGET_HARD_QUAD
)
3452 emit_hard_tfmode_operation (code
, operands
);
3454 emit_soft_tfmode_unop (code
, operands
);
3458 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3460 if (TARGET_HARD_QUAD
)
3461 emit_hard_tfmode_operation (code
, operands
);
3463 emit_soft_tfmode_cvt (code
, operands
);
3466 /* Return nonzero if a branch/jump/call instruction will be emitting
3467 nop into its delay slot. */
3470 empty_delay_slot (rtx_insn
*insn
)
3474 /* If no previous instruction (should not happen), return true. */
3475 if (PREV_INSN (insn
) == NULL
)
3478 seq
= NEXT_INSN (PREV_INSN (insn
));
3479 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3485 /* Return nonzero if we should emit a nop after a cbcond instruction.
3486 The cbcond instruction does not have a delay slot, however there is
3487 a severe performance penalty if a control transfer appears right
3488 after a cbcond. Therefore we emit a nop when we detect this
3492 emit_cbcond_nop (rtx_insn
*insn
)
3494 rtx next
= next_active_insn (insn
);
3499 if (NONJUMP_INSN_P (next
)
3500 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3501 next
= XVECEXP (PATTERN (next
), 0, 0);
3502 else if (CALL_P (next
)
3503 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3505 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3507 if (GET_CODE (delay
) == RETURN
)
3509 /* It's a sibling call. Do not emit the nop if we're going
3510 to emit something other than the jump itself as the first
3511 instruction of the sibcall sequence. */
3512 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3517 if (NONJUMP_INSN_P (next
))
3523 /* Return nonzero if TRIAL can go into the call delay slot. */
3526 eligible_for_call_delay (rtx_insn
*trial
)
3530 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3534 call __tls_get_addr, %tgd_call (foo)
3535 add %l7, %o0, %o0, %tgd_add (foo)
3536 while Sun as/ld does not. */
3537 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3540 pat
= PATTERN (trial
);
3542 /* We must reject tgd_add{32|64}, i.e.
3543 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3544 and tldm_add{32|64}, i.e.
3545 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3547 if (GET_CODE (pat
) == SET
3548 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3550 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3552 if (GET_CODE (unspec
) == UNSPEC
3553 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3554 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3561 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3562 instruction. RETURN_P is true if the v9 variant 'return' is to be
3563 considered in the test too.
3565 TRIAL must be a SET whose destination is a REG appropriate for the
3566 'restore' instruction or, if RETURN_P is true, for the 'return'
3570 eligible_for_restore_insn (rtx trial
, bool return_p
)
3572 rtx pat
= PATTERN (trial
);
3573 rtx src
= SET_SRC (pat
);
3574 bool src_is_freg
= false;
3577 /* Since we now can do moves between float and integer registers when
3578 VIS3 is enabled, we have to catch this case. We can allow such
3579 moves when doing a 'return' however. */
3581 if (GET_CODE (src_reg
) == SUBREG
)
3582 src_reg
= SUBREG_REG (src_reg
);
3583 if (GET_CODE (src_reg
) == REG
3584 && SPARC_FP_REG_P (REGNO (src_reg
)))
3587 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3588 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3589 && arith_operand (src
, GET_MODE (src
))
3593 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3595 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3598 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3599 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3600 && arith_double_operand (src
, GET_MODE (src
))
3602 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3604 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3605 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3608 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3609 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3612 /* If we have the 'return' instruction, anything that does not use
3613 local or output registers and can go into a delay slot wins. */
3614 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3617 /* The 'restore src1,src2,dest' pattern for SImode. */
3618 else if (GET_CODE (src
) == PLUS
3619 && register_operand (XEXP (src
, 0), SImode
)
3620 && arith_operand (XEXP (src
, 1), SImode
))
3623 /* The 'restore src1,src2,dest' pattern for DImode. */
3624 else if (GET_CODE (src
) == PLUS
3625 && register_operand (XEXP (src
, 0), DImode
)
3626 && arith_double_operand (XEXP (src
, 1), DImode
))
3629 /* The 'restore src1,%lo(src2),dest' pattern. */
3630 else if (GET_CODE (src
) == LO_SUM
3631 && ! TARGET_CM_MEDMID
3632 && ((register_operand (XEXP (src
, 0), SImode
)
3633 && immediate_operand (XEXP (src
, 1), SImode
))
3635 && register_operand (XEXP (src
, 0), DImode
)
3636 && immediate_operand (XEXP (src
, 1), DImode
))))
3639 /* The 'restore src,src,dest' pattern. */
3640 else if (GET_CODE (src
) == ASHIFT
3641 && (register_operand (XEXP (src
, 0), SImode
)
3642 || register_operand (XEXP (src
, 0), DImode
))
3643 && XEXP (src
, 1) == const1_rtx
)
3649 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3652 eligible_for_return_delay (rtx_insn
*trial
)
3657 /* If the function uses __builtin_eh_return, the eh_return machinery
3658 occupies the delay slot. */
3659 if (crtl
->calls_eh_return
)
3662 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3665 /* In the case of a leaf or flat function, anything can go into the slot. */
3666 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3669 if (!NONJUMP_INSN_P (trial
))
3672 pat
= PATTERN (trial
);
3673 if (GET_CODE (pat
) == PARALLEL
)
3679 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3681 rtx expr
= XVECEXP (pat
, 0, i
);
3682 if (GET_CODE (expr
) != SET
)
3684 if (GET_CODE (SET_DEST (expr
)) != REG
)
3686 regno
= REGNO (SET_DEST (expr
));
3687 if (regno
>= 8 && regno
< 24)
3690 return !epilogue_renumber (&pat
, 1);
3693 if (GET_CODE (pat
) != SET
)
3696 if (GET_CODE (SET_DEST (pat
)) != REG
)
3699 regno
= REGNO (SET_DEST (pat
));
3701 /* Otherwise, only operations which can be done in tandem with
3702 a `restore' or `return' insn can go into the delay slot. */
3703 if (regno
>= 8 && regno
< 24)
3706 /* If this instruction sets up floating point register and we have a return
3707 instruction, it can probably go in. But restore will not work
3709 if (! SPARC_INT_REG_P (regno
))
3710 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3712 return eligible_for_restore_insn (trial
, true);
3715 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3718 eligible_for_sibcall_delay (rtx_insn
*trial
)
3722 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3725 if (!NONJUMP_INSN_P (trial
))
3728 pat
= PATTERN (trial
);
3730 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3732 /* If the tail call is done using the call instruction,
3733 we have to restore %o7 in the delay slot. */
3734 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3737 /* %g1 is used to build the function address */
3738 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3744 if (GET_CODE (pat
) != SET
)
3747 /* Otherwise, only operations which can be done in tandem with
3748 a `restore' insn can go into the delay slot. */
3749 if (GET_CODE (SET_DEST (pat
)) != REG
3750 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3751 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3754 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3756 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3759 return eligible_for_restore_insn (trial
, false);
3762 /* Determine if it's legal to put X into the constant pool. This
3763 is not possible if X contains the address of a symbol that is
3764 not constant (TLS) or not known at final link time (PIC). */
3767 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
3769 switch (GET_CODE (x
))
3772 case CONST_WIDE_INT
:
3775 /* Accept all non-symbolic constants. */
3779 /* Labels are OK iff we are non-PIC. */
3780 return flag_pic
!= 0;
3783 /* 'Naked' TLS symbol references are never OK,
3784 non-TLS symbols are OK iff we are non-PIC. */
3785 if (SYMBOL_REF_TLS_MODEL (x
))
3788 return flag_pic
!= 0;
3791 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3794 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3795 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3803 /* Global Offset Table support. */
3804 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3805 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3807 /* Return the SYMBOL_REF for the Global Offset Table. */
3809 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3814 if (!sparc_got_symbol
)
3815 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3817 return sparc_got_symbol
;
3820 /* Ensure that we are not using patterns that are not OK with PIC. */
3830 op
= recog_data
.operand
[i
];
3831 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3832 && (GET_CODE (op
) != CONST
3833 || (GET_CODE (XEXP (op
, 0)) == MINUS
3834 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3835 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3843 /* Return true if X is an address which needs a temporary register when
3844 reloaded while generating PIC code. */
3847 pic_address_needs_scratch (rtx x
)
3849 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3850 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3851 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3852 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3853 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3859 /* Determine if a given RTX is a valid constant. We already know this
3860 satisfies CONSTANT_P. */
3863 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
3865 switch (GET_CODE (x
))
3869 if (sparc_tls_referenced_p (x
))
3874 /* Floating point constants are generally not ok.
3875 The only exception is 0.0 and all-ones in VIS. */
3877 && SCALAR_FLOAT_MODE_P (mode
)
3878 && (const_zero_operand (x
, mode
)
3879 || const_all_ones_operand (x
, mode
)))
3885 /* Vector constants are generally not ok.
3886 The only exception is 0 or -1 in VIS. */
3888 && (const_zero_operand (x
, mode
)
3889 || const_all_ones_operand (x
, mode
)))
3901 /* Determine if a given RTX is a valid constant address. */
3904 constant_address_p (rtx x
)
3906 switch (GET_CODE (x
))
3914 if (flag_pic
&& pic_address_needs_scratch (x
))
3916 return sparc_legitimate_constant_p (Pmode
, x
);
3919 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3926 /* Nonzero if the constant value X is a legitimate general operand
3927 when generating PIC code. It is given that flag_pic is on and
3928 that X satisfies CONSTANT_P. */
3931 legitimate_pic_operand_p (rtx x
)
3933 if (pic_address_needs_scratch (x
))
3935 if (sparc_tls_referenced_p (x
))
3940 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3942 && INTVAL (X) >= -0x1000 \
3943 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
3945 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3947 && INTVAL (X) >= -0x1000 \
3948 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
3950 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3952 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3953 ordinarily. This changes a bit when generating PIC. */
3956 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
3958 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3960 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3962 else if (GET_CODE (addr
) == PLUS
)
3964 rs1
= XEXP (addr
, 0);
3965 rs2
= XEXP (addr
, 1);
3967 /* Canonicalize. REG comes first, if there are no regs,
3968 LO_SUM comes first. */
3970 && GET_CODE (rs1
) != SUBREG
3972 || GET_CODE (rs2
) == SUBREG
3973 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3975 rs1
= XEXP (addr
, 1);
3976 rs2
= XEXP (addr
, 0);
3980 && rs1
== pic_offset_table_rtx
3982 && GET_CODE (rs2
) != SUBREG
3983 && GET_CODE (rs2
) != LO_SUM
3984 && GET_CODE (rs2
) != MEM
3985 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3986 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3987 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3989 || GET_CODE (rs1
) == SUBREG
)
3990 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3995 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3996 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3998 /* We prohibit REG + REG for TFmode when there are no quad move insns
3999 and we consequently need to split. We do this because REG+REG
4000 is not an offsettable address. If we get the situation in reload
4001 where source and destination of a movtf pattern are both MEMs with
4002 REG+REG address, then only one of them gets converted to an
4003 offsettable address. */
4005 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4008 /* Likewise for TImode, but in all cases. */
4012 /* We prohibit REG + REG on ARCH32 if not optimizing for
4013 DFmode/DImode because then mem_min_alignment is likely to be zero
4014 after reload and the forced split would lack a matching splitter
4016 if (TARGET_ARCH32
&& !optimize
4017 && (mode
== DFmode
|| mode
== DImode
))
4020 else if (USE_AS_OFFSETABLE_LO10
4021 && GET_CODE (rs1
) == LO_SUM
4023 && ! TARGET_CM_MEDMID
4024 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4027 imm1
= XEXP (rs1
, 1);
4028 rs1
= XEXP (rs1
, 0);
4029 if (!CONSTANT_P (imm1
)
4030 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4034 else if (GET_CODE (addr
) == LO_SUM
)
4036 rs1
= XEXP (addr
, 0);
4037 imm1
= XEXP (addr
, 1);
4039 if (!CONSTANT_P (imm1
)
4040 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4043 /* We can't allow TFmode in 32-bit mode, because an offset greater
4044 than the alignment (8) may cause the LO_SUM to overflow. */
4045 if (mode
== TFmode
&& TARGET_ARCH32
)
4048 /* During reload, accept the HIGH+LO_SUM construct generated by
4049 sparc_legitimize_reload_address. */
4050 if (reload_in_progress
4051 && GET_CODE (rs1
) == HIGH
4052 && XEXP (rs1
, 0) == imm1
)
4055 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4060 if (GET_CODE (rs1
) == SUBREG
)
4061 rs1
= SUBREG_REG (rs1
);
4067 if (GET_CODE (rs2
) == SUBREG
)
4068 rs2
= SUBREG_REG (rs2
);
4075 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4076 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4081 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4082 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4083 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4085 && (! SPARC_INT_REG_P (REGNO (rs2
))
4086 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4087 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4093 /* Return the SYMBOL_REF for the tls_get_addr function. */
4095 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4098 sparc_tls_get_addr (void)
4100 if (!sparc_tls_symbol
)
4101 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4103 return sparc_tls_symbol
;
4106 /* Return the Global Offset Table to be used in TLS mode. */
4109 sparc_tls_got (void)
4111 /* In PIC mode, this is just the PIC offset table. */
4114 crtl
->uses_pic_offset_table
= 1;
4115 return pic_offset_table_rtx
;
4118 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4119 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4120 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4122 load_got_register ();
4123 return global_offset_table_rtx
;
4126 /* In all other cases, we load a new pseudo with the GOT symbol. */
4127 return copy_to_reg (sparc_got ());
4130 /* Return true if X contains a thread-local symbol. */
4133 sparc_tls_referenced_p (rtx x
)
4135 if (!TARGET_HAVE_TLS
)
4138 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4139 x
= XEXP (XEXP (x
, 0), 0);
4141 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4144 /* That's all we handle in sparc_legitimize_tls_address for now. */
4148 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4149 this (thread-local) address. */
4152 sparc_legitimize_tls_address (rtx addr
)
4154 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4157 gcc_assert (can_create_pseudo_p ());
4159 if (GET_CODE (addr
) == SYMBOL_REF
)
4160 switch (SYMBOL_REF_TLS_MODEL (addr
))
4162 case TLS_MODEL_GLOBAL_DYNAMIC
:
4164 temp1
= gen_reg_rtx (SImode
);
4165 temp2
= gen_reg_rtx (SImode
);
4166 ret
= gen_reg_rtx (Pmode
);
4167 o0
= gen_rtx_REG (Pmode
, 8);
4168 got
= sparc_tls_got ();
4169 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4170 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4173 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4174 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4179 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4180 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4183 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4184 insn
= get_insns ();
4186 emit_libcall_block (insn
, ret
, o0
, addr
);
4189 case TLS_MODEL_LOCAL_DYNAMIC
:
4191 temp1
= gen_reg_rtx (SImode
);
4192 temp2
= gen_reg_rtx (SImode
);
4193 temp3
= gen_reg_rtx (Pmode
);
4194 ret
= gen_reg_rtx (Pmode
);
4195 o0
= gen_rtx_REG (Pmode
, 8);
4196 got
= sparc_tls_got ();
4197 emit_insn (gen_tldm_hi22 (temp1
));
4198 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4201 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4202 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4207 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4208 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4211 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4212 insn
= get_insns ();
4214 emit_libcall_block (insn
, temp3
, o0
,
4215 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4216 UNSPEC_TLSLD_BASE
));
4217 temp1
= gen_reg_rtx (SImode
);
4218 temp2
= gen_reg_rtx (SImode
);
4219 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4220 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4222 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4224 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4227 case TLS_MODEL_INITIAL_EXEC
:
4228 temp1
= gen_reg_rtx (SImode
);
4229 temp2
= gen_reg_rtx (SImode
);
4230 temp3
= gen_reg_rtx (Pmode
);
4231 got
= sparc_tls_got ();
4232 emit_insn (gen_tie_hi22 (temp1
, addr
));
4233 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4235 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4237 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4240 ret
= gen_reg_rtx (Pmode
);
4242 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4245 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4249 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4252 case TLS_MODEL_LOCAL_EXEC
:
4253 temp1
= gen_reg_rtx (Pmode
);
4254 temp2
= gen_reg_rtx (Pmode
);
4257 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4258 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4262 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4263 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4265 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4272 else if (GET_CODE (addr
) == CONST
)
4276 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4278 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4279 offset
= XEXP (XEXP (addr
, 0), 1);
4281 base
= force_operand (base
, NULL_RTX
);
4282 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4283 offset
= force_reg (Pmode
, offset
);
4284 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4288 gcc_unreachable (); /* for now ... */
4293 /* Legitimize PIC addresses. If the address is already position-independent,
4294 we return ORIG. Newly generated position-independent addresses go into a
4295 reg. This is REG if nonzero, otherwise we allocate register(s) as
4299 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4301 bool gotdata_op
= false;
4303 if (GET_CODE (orig
) == SYMBOL_REF
4304 /* See the comment in sparc_expand_move. */
4305 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4307 rtx pic_ref
, address
;
4312 gcc_assert (can_create_pseudo_p ());
4313 reg
= gen_reg_rtx (Pmode
);
4318 /* If not during reload, allocate another temp reg here for loading
4319 in the address, so that these instructions can be optimized
4321 rtx temp_reg
= (! can_create_pseudo_p ()
4322 ? reg
: gen_reg_rtx (Pmode
));
4324 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4325 won't get confused into thinking that these two instructions
4326 are loading in the true address of the symbol. If in the
4327 future a PIC rtx exists, that should be used instead. */
4330 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4331 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4335 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4336 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4344 crtl
->uses_pic_offset_table
= 1;
4348 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4349 pic_offset_table_rtx
,
4352 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4353 pic_offset_table_rtx
,
4359 = gen_const_mem (Pmode
,
4360 gen_rtx_PLUS (Pmode
,
4361 pic_offset_table_rtx
, address
));
4362 insn
= emit_move_insn (reg
, pic_ref
);
4365 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4367 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4370 else if (GET_CODE (orig
) == CONST
)
4374 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4375 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4380 gcc_assert (can_create_pseudo_p ());
4381 reg
= gen_reg_rtx (Pmode
);
4384 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4385 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4386 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4387 base
== reg
? NULL_RTX
: reg
);
4389 if (GET_CODE (offset
) == CONST_INT
)
4391 if (SMALL_INT (offset
))
4392 return plus_constant (Pmode
, base
, INTVAL (offset
));
4393 else if (can_create_pseudo_p ())
4394 offset
= force_reg (Pmode
, offset
);
4396 /* If we reach here, then something is seriously wrong. */
4399 return gen_rtx_PLUS (Pmode
, base
, offset
);
4401 else if (GET_CODE (orig
) == LABEL_REF
)
4402 /* ??? We ought to be checking that the register is live instead, in case
4403 it is eliminated. */
4404 crtl
->uses_pic_offset_table
= 1;
4409 /* Try machine-dependent ways of modifying an illegitimate address X
4410 to be legitimate. If we find one, return the new, valid address.
4412 OLDX is the address as it was before break_out_memory_refs was called.
4413 In some cases it is useful to look at this to decide what needs to be done.
4415 MODE is the mode of the operand pointed to by X.
4417 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4420 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4425 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4426 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4427 force_operand (XEXP (x
, 0), NULL_RTX
));
4428 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4429 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4430 force_operand (XEXP (x
, 1), NULL_RTX
));
4431 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4432 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4434 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4435 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4436 force_operand (XEXP (x
, 1), NULL_RTX
));
4438 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4441 if (sparc_tls_referenced_p (x
))
4442 x
= sparc_legitimize_tls_address (x
);
4444 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4445 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4446 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4447 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4448 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4449 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4450 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4451 else if (GET_CODE (x
) == SYMBOL_REF
4452 || GET_CODE (x
) == CONST
4453 || GET_CODE (x
) == LABEL_REF
)
4454 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4459 /* Delegitimize an address that was legitimized by the above function. */
4462 sparc_delegitimize_address (rtx x
)
4464 x
= delegitimize_mem_from_attrs (x
);
4466 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4467 switch (XINT (XEXP (x
, 1), 1))
4469 case UNSPEC_MOVE_PIC
:
4471 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4472 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4478 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4479 if (GET_CODE (x
) == MINUS
4480 && REG_P (XEXP (x
, 0))
4481 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4482 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4483 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4484 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4486 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4487 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4493 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4494 replace the input X, or the original X if no replacement is called for.
4495 The output parameter *WIN is 1 if the calling macro should goto WIN,
4498 For SPARC, we wish to handle addresses by splitting them into
4499 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4500 This cuts the number of extra insns by one.
4502 Do nothing when generating PIC code and the address is a symbolic
4503 operand or requires a scratch register. */
4506 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4507 int opnum
, int type
,
4508 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4510 /* Decompose SImode constants into HIGH+LO_SUM. */
4512 && (mode
!= TFmode
|| TARGET_ARCH64
)
4513 && GET_MODE (x
) == SImode
4514 && GET_CODE (x
) != LO_SUM
4515 && GET_CODE (x
) != HIGH
4516 && sparc_cmodel
<= CM_MEDLOW
4518 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4520 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4521 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4522 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4523 opnum
, (enum reload_type
)type
);
4528 /* We have to recognize what we have already generated above. */
4529 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4531 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4532 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4533 opnum
, (enum reload_type
)type
);
4542 /* Return true if ADDR (a legitimate address expression)
4543 has an effect that depends on the machine mode it is used for.
4549 is not equivalent to
4551 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4553 because [%l7+a+1] is interpreted as the address of (a+1). */
4557 sparc_mode_dependent_address_p (const_rtx addr
,
4558 addr_space_t as ATTRIBUTE_UNUSED
)
4560 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4562 rtx op0
= XEXP (addr
, 0);
4563 rtx op1
= XEXP (addr
, 1);
4564 if (op0
== pic_offset_table_rtx
4565 && symbolic_operand (op1
, VOIDmode
))
4572 #ifdef HAVE_GAS_HIDDEN
4573 # define USE_HIDDEN_LINKONCE 1
4575 # define USE_HIDDEN_LINKONCE 0
4579 get_pc_thunk_name (char name
[32], unsigned int regno
)
4581 const char *reg_name
= reg_names
[regno
];
4583 /* Skip the leading '%' as that cannot be used in a
4587 if (USE_HIDDEN_LINKONCE
)
4588 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4590 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4593 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4596 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4598 int orig_flag_pic
= flag_pic
;
4601 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4604 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4606 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4607 flag_pic
= orig_flag_pic
;
4612 /* Emit code to load the GOT register. */
4615 load_got_register (void)
4617 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4618 if (!global_offset_table_rtx
)
4619 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4621 if (TARGET_VXWORKS_RTP
)
4622 emit_insn (gen_vxworks_load_got ());
4625 /* The GOT symbol is subject to a PC-relative relocation so we need a
4626 helper function to add the PC value and thus get the final value. */
4627 if (!got_helper_rtx
)
4630 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4631 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4634 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4636 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4639 /* Need to emit this whether or not we obey regdecls,
4640 since setjmp/longjmp can cause life info to screw up.
4641 ??? In the case where we don't obey regdecls, this is not sufficient
4642 since we may not fall out the bottom. */
4643 emit_use (global_offset_table_rtx
);
4646 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4647 address of the call target. */
4650 sparc_emit_call_insn (rtx pat
, rtx addr
)
4654 insn
= emit_call_insn (pat
);
4656 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4657 if (TARGET_VXWORKS_RTP
4659 && GET_CODE (addr
) == SYMBOL_REF
4660 && (SYMBOL_REF_DECL (addr
)
4661 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4662 : !SYMBOL_REF_LOCAL_P (addr
)))
4664 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4665 crtl
->uses_pic_offset_table
= 1;
4669 /* Return 1 if RTX is a MEM which is known to be aligned to at
4670 least a DESIRED byte boundary. */
4673 mem_min_alignment (rtx mem
, int desired
)
4675 rtx addr
, base
, offset
;
4677 /* If it's not a MEM we can't accept it. */
4678 if (GET_CODE (mem
) != MEM
)
4682 if (!TARGET_UNALIGNED_DOUBLES
4683 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4686 /* ??? The rest of the function predates MEM_ALIGN so
4687 there is probably a bit of redundancy. */
4688 addr
= XEXP (mem
, 0);
4689 base
= offset
= NULL_RTX
;
4690 if (GET_CODE (addr
) == PLUS
)
4692 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4694 base
= XEXP (addr
, 0);
4696 /* What we are saying here is that if the base
4697 REG is aligned properly, the compiler will make
4698 sure any REG based index upon it will be so
4700 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4701 offset
= XEXP (addr
, 1);
4703 offset
= const0_rtx
;
4706 else if (GET_CODE (addr
) == REG
)
4709 offset
= const0_rtx
;
4712 if (base
!= NULL_RTX
)
4714 int regno
= REGNO (base
);
4716 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4718 /* Check if the compiler has recorded some information
4719 about the alignment of the base REG. If reload has
4720 completed, we already matched with proper alignments.
4721 If not running global_alloc, reload might give us
4722 unaligned pointer to local stack though. */
4724 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4725 || (optimize
&& reload_completed
))
4726 && (INTVAL (offset
) & (desired
- 1)) == 0)
4731 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4735 else if (! TARGET_UNALIGNED_DOUBLES
4736 || CONSTANT_P (addr
)
4737 || GET_CODE (addr
) == LO_SUM
)
4739 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4740 is true, in which case we can only assume that an access is aligned if
4741 it is to a constant address, or the address involves a LO_SUM. */
4745 /* An obviously unaligned address. */
4750 /* Vectors to keep interesting information about registers where it can easily
4751 be got. We used to use the actual mode value as the bit number, but there
4752 are more than 32 modes now. Instead we use two tables: one indexed by
4753 hard register number, and one indexed by mode. */
4755 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4756 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4757 mapped into one sparc_mode_class mode. */
4759 enum sparc_mode_class
{
4760 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4761 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4765 /* Modes for single-word and smaller quantities. */
4767 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4769 /* Modes for double-word and smaller quantities. */
4770 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4772 /* Modes for quad-word and smaller quantities. */
4773 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4775 /* Modes for 8-word and smaller quantities. */
4776 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4778 /* Modes for single-float quantities. */
4779 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4781 /* Modes for double-float and smaller quantities. */
4782 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4784 /* Modes for quad-float and smaller quantities. */
4785 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4787 /* Modes for quad-float pairs and smaller quantities. */
4788 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4790 /* Modes for double-float only quantities. */
4791 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4793 /* Modes for quad-float and double-float only quantities. */
4794 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4796 /* Modes for quad-float pairs and double-float only quantities. */
4797 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4799 /* Modes for condition codes. */
4800 #define CC_MODES (1 << (int) CC_MODE)
4801 #define CCFP_MODES (1 << (int) CCFP_MODE)
4803 /* Value is 1 if register/mode pair is acceptable on sparc.
4805 The funny mixture of D and T modes is because integer operations
4806 do not specially operate on tetra quantities, so non-quad-aligned
4807 registers can hold quadword quantities (except %o4 and %i4 because
4808 they cross fixed registers).
4810 ??? Note that, despite the settings, non-double-aligned parameter
4811 registers can hold double-word quantities in 32-bit mode. */
4813 /* This points to either the 32 bit or the 64 bit version. */
4814 const int *hard_regno_mode_classes
;
4816 static const int hard_32bit_mode_classes
[] = {
4817 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4818 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4819 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4820 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4822 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4823 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4824 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4825 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4827 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4828 and none can hold SFmode/SImode values. */
4829 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4830 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4831 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4832 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4835 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4837 /* %icc, %sfp, %gsr */
4838 CC_MODES
, 0, D_MODES
4841 static const int hard_64bit_mode_classes
[] = {
4842 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4843 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4844 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4845 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4847 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4848 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4849 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4850 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4852 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4853 and none can hold SFmode/SImode values. */
4854 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4855 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4856 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4857 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4860 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4862 /* %icc, %sfp, %gsr */
4863 CC_MODES
, 0, D_MODES
4866 int sparc_mode_class
[NUM_MACHINE_MODES
];
4868 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4871 sparc_init_modes (void)
4875 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4877 machine_mode m
= (machine_mode
) i
;
4878 unsigned int size
= GET_MODE_SIZE (m
);
4880 switch (GET_MODE_CLASS (m
))
4883 case MODE_PARTIAL_INT
:
4884 case MODE_COMPLEX_INT
:
4886 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
4888 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4890 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4891 else if (size
== 16)
4892 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4893 else if (size
== 32)
4894 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4896 sparc_mode_class
[i
] = 0;
4898 case MODE_VECTOR_INT
:
4900 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4902 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4904 sparc_mode_class
[i
] = 0;
4907 case MODE_COMPLEX_FLOAT
:
4909 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4911 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4912 else if (size
== 16)
4913 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4914 else if (size
== 32)
4915 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4917 sparc_mode_class
[i
] = 0;
4920 if (m
== CCFPmode
|| m
== CCFPEmode
)
4921 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4923 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4926 sparc_mode_class
[i
] = 0;
4932 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4934 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4936 /* Initialize the array used by REGNO_REG_CLASS. */
4937 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4939 if (i
< 16 && TARGET_V8PLUS
)
4940 sparc_regno_reg_class
[i
] = I64_REGS
;
4941 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4942 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4944 sparc_regno_reg_class
[i
] = FP_REGS
;
4946 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4948 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4950 sparc_regno_reg_class
[i
] = NO_REGS
;
4954 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4957 save_global_or_fp_reg_p (unsigned int regno
,
4958 int leaf_function ATTRIBUTE_UNUSED
)
4960 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4963 /* Return whether the return address register (%i7) is needed. */
4966 return_addr_reg_needed_p (int leaf_function
)
4968 /* If it is live, for example because of __builtin_return_address (0). */
4969 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4972 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4974 /* Loading the GOT register clobbers %o7. */
4975 || crtl
->uses_pic_offset_table
4976 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4982 /* Return whether REGNO, a local or in register, must be saved/restored. */
4985 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4987 /* General case: call-saved registers live at some point. */
4988 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4991 /* Frame pointer register (%fp) if needed. */
4992 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4995 /* Return address register (%i7) if needed. */
4996 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4999 /* GOT register (%l7) if needed. */
5000 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
5003 /* If the function accesses prior frames, the frame pointer and the return
5004 address of the previous frame must be saved on the stack. */
5005 if (crtl
->accesses_prior_frames
5006 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5012 /* Compute the frame size required by the function. This function is called
5013 during the reload pass and also by sparc_expand_prologue. */
5016 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5018 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5019 int args_size
, n_global_fp_regs
= 0;
5020 bool save_local_in_regs_p
= false;
5023 /* If the function allocates dynamic stack space, the dynamic offset is
5024 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5025 if (leaf_function
&& !cfun
->calls_alloca
)
5028 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5030 /* Calculate space needed for global registers. */
5033 for (i
= 0; i
< 8; i
++)
5034 if (save_global_or_fp_reg_p (i
, 0))
5035 n_global_fp_regs
+= 2;
5039 for (i
= 0; i
< 8; i
+= 2)
5040 if (save_global_or_fp_reg_p (i
, 0)
5041 || save_global_or_fp_reg_p (i
+ 1, 0))
5042 n_global_fp_regs
+= 2;
5045 /* In the flat window model, find out which local and in registers need to
5046 be saved. We don't reserve space in the current frame for them as they
5047 will be spilled into the register window save area of the caller's frame.
5048 However, as soon as we use this register window save area, we must create
5049 that of the current frame to make it the live one. */
5051 for (i
= 16; i
< 32; i
++)
5052 if (save_local_or_in_reg_p (i
, leaf_function
))
5054 save_local_in_regs_p
= true;
5058 /* Calculate space needed for FP registers. */
5059 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5060 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5061 n_global_fp_regs
+= 2;
5064 && n_global_fp_regs
== 0
5066 && !save_local_in_regs_p
)
5067 frame_size
= apparent_frame_size
= 0;
5070 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5071 apparent_frame_size
= ROUND_UP (size
- STARTING_FRAME_OFFSET
, 8);
5072 apparent_frame_size
+= n_global_fp_regs
* 4;
5074 /* We need to add the size of the outgoing argument area. */
5075 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5077 /* And that of the register window save area. */
5078 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5080 /* Finally, bump to the appropriate alignment. */
5081 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5084 /* Set up values for use in prologue and epilogue. */
5085 sparc_frame_size
= frame_size
;
5086 sparc_apparent_frame_size
= apparent_frame_size
;
5087 sparc_n_global_fp_regs
= n_global_fp_regs
;
5088 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5093 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5096 sparc_initial_elimination_offset (int to
)
5100 if (to
== STACK_POINTER_REGNUM
)
5101 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5105 offset
+= SPARC_STACK_BIAS
;
5109 /* Output any necessary .register pseudo-ops. */
5112 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5114 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5120 /* Check if %g[2367] were used without
5121 .register being printed for them already. */
5122 for (i
= 2; i
< 8; i
++)
5124 if (df_regs_ever_live_p (i
)
5125 && ! sparc_hard_reg_printed
[i
])
5127 sparc_hard_reg_printed
[i
] = 1;
5128 /* %g7 is used as TLS base register, use #ignore
5129 for it instead of #scratch. */
5130 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5131 i
== 7 ? "ignore" : "scratch");
5138 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5140 #if PROBE_INTERVAL > 4096
5141 #error Cannot use indexed addressing mode for stack probing
5144 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5145 inclusive. These are offsets from the current stack pointer.
5147 Note that we don't use the REG+REG addressing mode for the probes because
5148 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5149 so the advantages of having a single code win here. */
5152 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5154 rtx g1
= gen_rtx_REG (Pmode
, 1);
5156 /* See if we have a constant small number of probes to generate. If so,
5157 that's the easy case. */
5158 if (size
<= PROBE_INTERVAL
)
5160 emit_move_insn (g1
, GEN_INT (first
));
5161 emit_insn (gen_rtx_SET (g1
,
5162 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5163 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5166 /* The run-time loop is made up of 9 insns in the generic case while the
5167 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5168 else if (size
<= 4 * PROBE_INTERVAL
)
5172 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5173 emit_insn (gen_rtx_SET (g1
,
5174 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5175 emit_stack_probe (g1
);
5177 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5178 it exceeds SIZE. If only two probes are needed, this will not
5179 generate any code. Then probe at FIRST + SIZE. */
5180 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5182 emit_insn (gen_rtx_SET (g1
,
5183 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5184 emit_stack_probe (g1
);
5187 emit_stack_probe (plus_constant (Pmode
, g1
,
5188 (i
- PROBE_INTERVAL
) - size
));
5191 /* Otherwise, do the same as above, but in a loop. Note that we must be
5192 extra careful with variables wrapping around because we might be at
5193 the very top (or the very bottom) of the address space and we have
5194 to be able to handle this case properly; in particular, we use an
5195 equality test for the loop condition. */
5198 HOST_WIDE_INT rounded_size
;
5199 rtx g4
= gen_rtx_REG (Pmode
, 4);
5201 emit_move_insn (g1
, GEN_INT (first
));
5204 /* Step 1: round SIZE to the previous multiple of the interval. */
5206 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5207 emit_move_insn (g4
, GEN_INT (rounded_size
));
5210 /* Step 2: compute initial and final value of the loop counter. */
5212 /* TEST_ADDR = SP + FIRST. */
5213 emit_insn (gen_rtx_SET (g1
,
5214 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5216 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5217 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5222 while (TEST_ADDR != LAST_ADDR)
5224 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5228 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5229 until it is equal to ROUNDED_SIZE. */
5232 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5234 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5237 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5238 that SIZE is equal to ROUNDED_SIZE. */
5240 if (size
!= rounded_size
)
5241 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5244 /* Make sure nothing is scheduled before we are done. */
5245 emit_insn (gen_blockage ());
5248 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5249 absolute addresses. */
5252 output_probe_stack_range (rtx reg1
, rtx reg2
)
5254 static int labelno
= 0;
5258 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5261 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5263 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5265 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5266 output_asm_insn ("add\t%0, %1, %0", xops
);
5268 /* Test if TEST_ADDR == LAST_ADDR. */
5270 output_asm_insn ("cmp\t%0, %1", xops
);
5272 /* Probe at TEST_ADDR and branch. */
5274 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5276 fputs ("\tbne\t", asm_out_file
);
5277 assemble_name_raw (asm_out_file
, loop_lab
);
5278 fputc ('\n', asm_out_file
);
5279 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5280 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5285 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5286 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5287 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5288 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5289 the action to be performed if it returns false. Return the new offset. */
5291 typedef bool (*sorr_pred_t
) (unsigned int, int);
5292 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5295 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5296 int offset
, int leaf_function
, sorr_pred_t save_p
,
5297 sorr_act_t action_true
, sorr_act_t action_false
)
5303 if (TARGET_ARCH64
&& high
<= 32)
5307 for (i
= low
; i
< high
; i
++)
5309 if (save_p (i
, leaf_function
))
5311 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5313 if (action_true
== SORR_SAVE
)
5315 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5316 RTX_FRAME_RELATED_P (insn
) = 1;
5318 else /* action_true == SORR_RESTORE */
5320 /* The frame pointer must be restored last since its old
5321 value may be used as base address for the frame. This
5322 is problematic in 64-bit mode only because of the lack
5323 of double-word load instruction. */
5324 if (i
== HARD_FRAME_POINTER_REGNUM
)
5327 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5331 else if (action_false
== SORR_ADVANCE
)
5337 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5338 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5343 for (i
= low
; i
< high
; i
+= 2)
5345 bool reg0
= save_p (i
, leaf_function
);
5346 bool reg1
= save_p (i
+ 1, leaf_function
);
5352 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5357 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5362 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5368 if (action_false
== SORR_ADVANCE
)
5373 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5374 if (action_true
== SORR_SAVE
)
5376 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5377 RTX_FRAME_RELATED_P (insn
) = 1;
5381 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5383 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5384 RTX_FRAME_RELATED_P (set1
) = 1;
5386 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5388 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5389 RTX_FRAME_RELATED_P (set2
) = 1;
5390 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5391 gen_rtx_PARALLEL (VOIDmode
,
5392 gen_rtvec (2, set1
, set2
)));
5395 else /* action_true == SORR_RESTORE */
5396 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5398 /* Bump and round down to double word
5399 in case we already bumped by 4. */
5400 offset
= ROUND_DOWN (offset
+ 8, 8);
5407 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5410 emit_adjust_base_to_offset (rtx base
, int offset
)
5412 /* ??? This might be optimized a little as %g1 might already have a
5413 value close enough that a single add insn will do. */
5414 /* ??? Although, all of this is probably only a temporary fix because
5415 if %g1 can hold a function result, then sparc_expand_epilogue will
5416 lose (the result will be clobbered). */
5417 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5418 emit_move_insn (new_base
, GEN_INT (offset
));
5419 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5423 /* Emit code to save/restore call-saved global and FP registers. */
5426 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5428 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5430 base
= emit_adjust_base_to_offset (base
, offset
);
5435 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5436 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5437 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5438 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5441 /* Emit code to save/restore call-saved local and in registers. */
5444 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5446 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5448 base
= emit_adjust_base_to_offset (base
, offset
);
5452 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5453 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5456 /* Emit a window_save insn. */
5459 emit_window_save (rtx increment
)
5461 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5462 RTX_FRAME_RELATED_P (insn
) = 1;
5464 /* The incoming return address (%o7) is saved in %i7. */
5465 add_reg_note (insn
, REG_CFA_REGISTER
,
5466 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5468 INCOMING_RETURN_ADDR_REGNUM
)));
5470 /* The window save event. */
5471 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5473 /* The CFA is %fp, the hard frame pointer. */
5474 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5475 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5476 INCOMING_FRAME_SP_OFFSET
));
5481 /* Generate an increment for the stack pointer. */
5484 gen_stack_pointer_inc (rtx increment
)
5486 return gen_rtx_SET (stack_pointer_rtx
,
5487 gen_rtx_PLUS (Pmode
,
5492 /* Expand the function prologue. The prologue is responsible for reserving
5493 storage for the frame, saving the call-saved registers and loading the
5494 GOT register if needed. */
5497 sparc_expand_prologue (void)
5502 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5503 on the final value of the flag means deferring the prologue/epilogue
5504 expansion until just before the second scheduling pass, which is too
5505 late to emit multiple epilogues or return insns.
5507 Of course we are making the assumption that the value of the flag
5508 will not change between now and its final value. Of the three parts
5509 of the formula, only the last one can reasonably vary. Let's take a
5510 closer look, after assuming that the first two ones are set to true
5511 (otherwise the last value is effectively silenced).
5513 If only_leaf_regs_used returns false, the global predicate will also
5514 be false so the actual frame size calculated below will be positive.
5515 As a consequence, the save_register_window insn will be emitted in
5516 the instruction stream; now this insn explicitly references %fp
5517 which is not a leaf register so only_leaf_regs_used will always
5518 return false subsequently.
5520 If only_leaf_regs_used returns true, we hope that the subsequent
5521 optimization passes won't cause non-leaf registers to pop up. For
5522 example, the regrename pass has special provisions to not rename to
5523 non-leaf registers in a leaf function. */
5524 sparc_leaf_function_p
5525 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5527 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5529 if (flag_stack_usage_info
)
5530 current_function_static_stack_size
= size
;
5532 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5534 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5536 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5537 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5538 size
- STACK_CHECK_PROTECT
);
5541 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5546 else if (sparc_leaf_function_p
)
5548 rtx size_int_rtx
= GEN_INT (-size
);
5551 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5552 else if (size
<= 8192)
5554 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5555 RTX_FRAME_RELATED_P (insn
) = 1;
5557 /* %sp is still the CFA register. */
5558 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5562 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5563 emit_move_insn (size_rtx
, size_int_rtx
);
5564 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5565 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5566 gen_stack_pointer_inc (size_int_rtx
));
5569 RTX_FRAME_RELATED_P (insn
) = 1;
5573 rtx size_int_rtx
= GEN_INT (-size
);
5576 emit_window_save (size_int_rtx
);
5577 else if (size
<= 8192)
5579 emit_window_save (GEN_INT (-4096));
5581 /* %sp is not the CFA register anymore. */
5582 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5584 /* Make sure no %fp-based store is issued until after the frame is
5585 established. The offset between the frame pointer and the stack
5586 pointer is calculated relative to the value of the stack pointer
5587 at the end of the function prologue, and moving instructions that
5588 access the stack via the frame pointer between the instructions
5589 that decrement the stack pointer could result in accessing the
5590 register window save area, which is volatile. */
5591 emit_insn (gen_frame_blockage ());
5595 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5596 emit_move_insn (size_rtx
, size_int_rtx
);
5597 emit_window_save (size_rtx
);
5601 if (sparc_leaf_function_p
)
5603 sparc_frame_base_reg
= stack_pointer_rtx
;
5604 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5608 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5609 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5612 if (sparc_n_global_fp_regs
> 0)
5613 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5614 sparc_frame_base_offset
5615 - sparc_apparent_frame_size
,
5618 /* Load the GOT register if needed. */
5619 if (crtl
->uses_pic_offset_table
)
5620 load_got_register ();
5622 /* Advertise that the data calculated just above are now valid. */
5623 sparc_prologue_data_valid_p
= true;
5626 /* Expand the function prologue. The prologue is responsible for reserving
5627 storage for the frame, saving the call-saved registers and loading the
5628 GOT register if needed. */
5631 sparc_flat_expand_prologue (void)
5636 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5638 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5640 if (flag_stack_usage_info
)
5641 current_function_static_stack_size
= size
;
5643 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5645 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5647 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5648 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5649 size
- STACK_CHECK_PROTECT
);
5652 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5655 if (sparc_save_local_in_regs_p
)
5656 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5663 rtx size_int_rtx
, size_rtx
;
5665 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5667 /* We establish the frame (i.e. decrement the stack pointer) first, even
5668 if we use a frame pointer, because we cannot clobber any call-saved
5669 registers, including the frame pointer, if we haven't created a new
5670 register save area, for the sake of compatibility with the ABI. */
5672 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5673 else if (size
<= 8192 && !frame_pointer_needed
)
5675 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5676 RTX_FRAME_RELATED_P (insn
) = 1;
5677 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5681 size_rtx
= gen_rtx_REG (Pmode
, 1);
5682 emit_move_insn (size_rtx
, size_int_rtx
);
5683 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5684 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5685 gen_stack_pointer_inc (size_int_rtx
));
5687 RTX_FRAME_RELATED_P (insn
) = 1;
5689 /* Ensure nothing is scheduled until after the frame is established. */
5690 emit_insn (gen_blockage ());
5692 if (frame_pointer_needed
)
5694 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
5695 gen_rtx_MINUS (Pmode
,
5698 RTX_FRAME_RELATED_P (insn
) = 1;
5700 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5701 gen_rtx_SET (hard_frame_pointer_rtx
,
5702 plus_constant (Pmode
, stack_pointer_rtx
,
5706 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5708 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5709 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5711 insn
= emit_move_insn (i7
, o7
);
5712 RTX_FRAME_RELATED_P (insn
) = 1;
5714 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
5716 /* Prevent this instruction from ever being considered dead,
5717 even if this function has no epilogue. */
5722 if (frame_pointer_needed
)
5724 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5725 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5729 sparc_frame_base_reg
= stack_pointer_rtx
;
5730 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5733 if (sparc_n_global_fp_regs
> 0)
5734 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5735 sparc_frame_base_offset
5736 - sparc_apparent_frame_size
,
5739 /* Load the GOT register if needed. */
5740 if (crtl
->uses_pic_offset_table
)
5741 load_got_register ();
5743 /* Advertise that the data calculated just above are now valid. */
5744 sparc_prologue_data_valid_p
= true;
5747 /* This function generates the assembly code for function entry, which boils
5748 down to emitting the necessary .register directives. */
5751 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5753 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5755 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5757 sparc_output_scratch_registers (file
);
5760 /* Expand the function epilogue, either normal or part of a sibcall.
5761 We emit all the instructions except the return or the call. */
5764 sparc_expand_epilogue (bool for_eh
)
5766 HOST_WIDE_INT size
= sparc_frame_size
;
5768 if (sparc_n_global_fp_regs
> 0)
5769 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5770 sparc_frame_base_offset
5771 - sparc_apparent_frame_size
,
5774 if (size
== 0 || for_eh
)
5776 else if (sparc_leaf_function_p
)
5779 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5780 else if (size
<= 8192)
5782 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5783 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5787 rtx reg
= gen_rtx_REG (Pmode
, 1);
5788 emit_move_insn (reg
, GEN_INT (size
));
5789 emit_insn (gen_stack_pointer_inc (reg
));
5794 /* Expand the function epilogue, either normal or part of a sibcall.
5795 We emit all the instructions except the return or the call. */
5798 sparc_flat_expand_epilogue (bool for_eh
)
5800 HOST_WIDE_INT size
= sparc_frame_size
;
5802 if (sparc_n_global_fp_regs
> 0)
5803 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5804 sparc_frame_base_offset
5805 - sparc_apparent_frame_size
,
5808 /* If we have a frame pointer, we'll need both to restore it before the
5809 frame is destroyed and use its current value in destroying the frame.
5810 Since we don't have an atomic way to do that in the flat window model,
5811 we save the current value into a temporary register (%g1). */
5812 if (frame_pointer_needed
&& !for_eh
)
5813 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5815 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5816 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5817 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5819 if (sparc_save_local_in_regs_p
)
5820 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5821 sparc_frame_base_offset
,
5824 if (size
== 0 || for_eh
)
5826 else if (frame_pointer_needed
)
5828 /* Make sure the frame is destroyed after everything else is done. */
5829 emit_insn (gen_blockage ());
5831 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5836 emit_insn (gen_blockage ());
5839 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5840 else if (size
<= 8192)
5842 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5843 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5847 rtx reg
= gen_rtx_REG (Pmode
, 1);
5848 emit_move_insn (reg
, GEN_INT (size
));
5849 emit_insn (gen_stack_pointer_inc (reg
));
5854 /* Return true if it is appropriate to emit `return' instructions in the
5855 body of a function. */
5858 sparc_can_use_return_insn_p (void)
5860 return sparc_prologue_data_valid_p
5861 && sparc_n_global_fp_regs
== 0
5863 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5864 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5867 /* This function generates the assembly code for function exit. */
5870 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5872 /* If the last two instructions of a function are "call foo; dslot;"
5873 the return address might point to the first instruction in the next
5874 function and we have to output a dummy nop for the sake of sane
5875 backtraces in such cases. This is pointless for sibling calls since
5876 the return address is explicitly adjusted. */
5878 rtx_insn
*insn
= get_last_insn ();
5880 rtx last_real_insn
= prev_real_insn (insn
);
5882 && NONJUMP_INSN_P (last_real_insn
)
5883 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5884 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5887 && CALL_P (last_real_insn
)
5888 && !SIBLING_CALL_P (last_real_insn
))
5889 fputs("\tnop\n", file
);
5891 sparc_output_deferred_case_vectors ();
5894 /* Output a 'restore' instruction. */
5897 output_restore (rtx pat
)
5903 fputs ("\t restore\n", asm_out_file
);
5907 gcc_assert (GET_CODE (pat
) == SET
);
5909 operands
[0] = SET_DEST (pat
);
5910 pat
= SET_SRC (pat
);
5912 switch (GET_CODE (pat
))
5915 operands
[1] = XEXP (pat
, 0);
5916 operands
[2] = XEXP (pat
, 1);
5917 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5920 operands
[1] = XEXP (pat
, 0);
5921 operands
[2] = XEXP (pat
, 1);
5922 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5925 operands
[1] = XEXP (pat
, 0);
5926 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5927 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5931 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5936 /* Output a return. */
5939 output_return (rtx_insn
*insn
)
5941 if (crtl
->calls_eh_return
)
5943 /* If the function uses __builtin_eh_return, the eh_return
5944 machinery occupies the delay slot. */
5945 gcc_assert (!final_sequence
);
5947 if (flag_delayed_branch
)
5949 if (!TARGET_FLAT
&& TARGET_V9
)
5950 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5954 fputs ("\trestore\n", asm_out_file
);
5956 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5959 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5964 fputs ("\trestore\n", asm_out_file
);
5966 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5967 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5970 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5972 /* This is a leaf or flat function so we don't have to bother restoring
5973 the register window, which frees us from dealing with the convoluted
5974 semantics of restore/return. We simply output the jump to the
5975 return address and the insn in the delay slot (if any). */
5977 return "jmp\t%%o7+%)%#";
5981 /* This is a regular function so we have to restore the register window.
5982 We may have a pending insn for the delay slot, which will be either
5983 combined with the 'restore' instruction or put in the delay slot of
5984 the 'return' instruction. */
5990 delay
= NEXT_INSN (insn
);
5993 pat
= PATTERN (delay
);
5995 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5997 epilogue_renumber (&pat
, 0);
5998 return "return\t%%i7+%)%#";
6002 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6003 output_restore (pat
);
6004 PATTERN (delay
) = gen_blockage ();
6005 INSN_CODE (delay
) = -1;
6010 /* The delay slot is empty. */
6012 return "return\t%%i7+%)\n\t nop";
6013 else if (flag_delayed_branch
)
6014 return "jmp\t%%i7+%)\n\t restore";
6016 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6023 /* Output a sibling call. */
6026 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6030 gcc_assert (flag_delayed_branch
);
6032 operands
[0] = call_operand
;
6034 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6036 /* This is a leaf or flat function so we don't have to bother restoring
6037 the register window. We simply output the jump to the function and
6038 the insn in the delay slot (if any). */
6040 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6043 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6046 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6047 it into branch if possible. */
6048 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6053 /* This is a regular function so we have to restore the register window.
6054 We may have a pending insn for the delay slot, which will be combined
6055 with the 'restore' instruction. */
6057 output_asm_insn ("call\t%a0, 0", operands
);
6061 rtx_insn
*delay
= NEXT_INSN (insn
);
6064 output_restore (PATTERN (delay
));
6066 PATTERN (delay
) = gen_blockage ();
6067 INSN_CODE (delay
) = -1;
6070 output_restore (NULL_RTX
);
6076 /* Functions for handling argument passing.
6078 For 32-bit, the first 6 args are normally in registers and the rest are
6079 pushed. Any arg that starts within the first 6 words is at least
6080 partially passed in a register unless its data type forbids.
6082 For 64-bit, the argument registers are laid out as an array of 16 elements
6083 and arguments are added sequentially. The first 6 int args and up to the
6084 first 16 fp args (depending on size) are passed in regs.
6086 Slot Stack Integral Float Float in structure Double Long Double
6087 ---- ----- -------- ----- ------------------ ------ -----------
6088 15 [SP+248] %f31 %f30,%f31 %d30
6089 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6090 13 [SP+232] %f27 %f26,%f27 %d26
6091 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6092 11 [SP+216] %f23 %f22,%f23 %d22
6093 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6094 9 [SP+200] %f19 %f18,%f19 %d18
6095 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6096 7 [SP+184] %f15 %f14,%f15 %d14
6097 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6098 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6099 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6100 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6101 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6102 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6103 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6105 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6107 Integral arguments are always passed as 64-bit quantities appropriately
6110 Passing of floating point values is handled as follows.
6111 If a prototype is in scope:
6112 If the value is in a named argument (i.e. not a stdarg function or a
6113 value not part of the `...') then the value is passed in the appropriate
6115 If the value is part of the `...' and is passed in one of the first 6
6116 slots then the value is passed in the appropriate int reg.
6117 If the value is part of the `...' and is not passed in one of the first 6
6118 slots then the value is passed in memory.
6119 If a prototype is not in scope:
6120 If the value is one of the first 6 arguments the value is passed in the
6121 appropriate integer reg and the appropriate fp reg.
6122 If the value is not one of the first 6 arguments the value is passed in
6123 the appropriate fp reg and in memory.
6126 Summary of the calling conventions implemented by GCC on the SPARC:
6129 size argument return value
6131 small integer <4 int. reg. int. reg.
6132 word 4 int. reg. int. reg.
6133 double word 8 int. reg. int. reg.
6135 _Complex small integer <8 int. reg. int. reg.
6136 _Complex word 8 int. reg. int. reg.
6137 _Complex double word 16 memory int. reg.
6139 vector integer <=8 int. reg. FP reg.
6140 vector integer >8 memory memory
6142 float 4 int. reg. FP reg.
6143 double 8 int. reg. FP reg.
6144 long double 16 memory memory
6146 _Complex float 8 memory FP reg.
6147 _Complex double 16 memory FP reg.
6148 _Complex long double 32 memory FP reg.
6150 vector float any memory memory
6152 aggregate any memory memory
6157 size argument return value
6159 small integer <8 int. reg. int. reg.
6160 word 8 int. reg. int. reg.
6161 double word 16 int. reg. int. reg.
6163 _Complex small integer <16 int. reg. int. reg.
6164 _Complex word 16 int. reg. int. reg.
6165 _Complex double word 32 memory int. reg.
6167 vector integer <=16 FP reg. FP reg.
6168 vector integer 16<s<=32 memory FP reg.
6169 vector integer >32 memory memory
6171 float 4 FP reg. FP reg.
6172 double 8 FP reg. FP reg.
6173 long double 16 FP reg. FP reg.
6175 _Complex float 8 FP reg. FP reg.
6176 _Complex double 16 FP reg. FP reg.
6177 _Complex long double 32 memory FP reg.
6179 vector float <=16 FP reg. FP reg.
6180 vector float 16<s<=32 memory FP reg.
6181 vector float >32 memory memory
6183 aggregate <=16 reg. reg.
6184 aggregate 16<s<=32 memory reg.
6185 aggregate >32 memory memory
6189 Note #1: complex floating-point types follow the extended SPARC ABIs as
6190 implemented by the Sun compiler.
6192 Note #2: integral vector types follow the scalar floating-point types
6193 conventions to match what is implemented by the Sun VIS SDK.
6195 Note #3: floating-point vector types follow the aggregate types
6199 /* Maximum number of int regs for args. */
6200 #define SPARC_INT_ARG_MAX 6
6201 /* Maximum number of fp regs for args. */
6202 #define SPARC_FP_ARG_MAX 16
6203 /* Number of words (partially) occupied for a given size in units. */
6204 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6206 /* Handle the INIT_CUMULATIVE_ARGS macro.
6207 Initialize a variable CUM of type CUMULATIVE_ARGS
6208 for a call to a function whose data type is FNTYPE.
6209 For a library call, FNTYPE is 0. */
6212 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6215 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6216 cum
->libcall_p
= !fntype
;
6219 /* Handle promotion of pointer and integer arguments. */
6222 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6223 int *punsignedp
, const_tree
, int)
6225 if (type
&& POINTER_TYPE_P (type
))
6227 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6231 /* Integral arguments are passed as full words, as per the ABI. */
6232 if (GET_MODE_CLASS (mode
) == MODE_INT
6233 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6239 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6242 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6244 return TARGET_ARCH64
? true : false;
6247 /* Traverse the record TYPE recursively and call FUNC on its fields.
6248 NAMED is true if this is for a named parameter. DATA is passed
6249 to FUNC for each field. OFFSET is the starting position and
6250 PACKED is true if we are inside a packed record. */
6252 template <typename T
, void Func (const_tree
, HOST_WIDE_INT
, bool, T
*)>
6254 traverse_record_type (const_tree type
, bool named
, T
*data
,
6255 HOST_WIDE_INT offset
= 0, bool packed
= false)
6257 /* The ABI obviously doesn't specify how packed structures are passed.
6258 These are passed in integer regs if possible, otherwise memory. */
6260 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6261 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6267 /* Walk the real fields, but skip those with no size or a zero size.
6268 ??? Fields with variable offset are handled as having zero offset. */
6269 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6270 if (TREE_CODE (field
) == FIELD_DECL
)
6272 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6275 HOST_WIDE_INT bitpos
= offset
;
6276 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6277 bitpos
+= int_bit_position (field
);
6279 tree field_type
= TREE_TYPE (field
);
6280 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6281 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6286 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6287 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6293 /* Handle recursive register classifying for structure layout. */
6297 bool int_regs
; /* true if field eligible to int registers. */
6298 bool fp_regs
; /* true if field eligible to FP registers. */
6299 bool fp_regs_in_first_word
; /* true if such field in first word. */
6302 /* A subroutine of function_arg_slotno. Classify the field. */
6305 classify_registers (const_tree
, HOST_WIDE_INT bitpos
, bool fp
,
6306 classify_data_t
*data
)
6310 data
->fp_regs
= true;
6311 if (bitpos
< BITS_PER_WORD
)
6312 data
->fp_regs_in_first_word
= true;
6315 data
->int_regs
= true;
6318 /* Compute the slot number to pass an argument in.
6319 Return the slot number or -1 if passing on the stack.
6321 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6322 the preceding args and about the function being called.
6323 MODE is the argument's machine mode.
6324 TYPE is the data type of the argument (as a tree).
6325 This is null for libcalls where that information may
6327 NAMED is nonzero if this argument is a named parameter
6328 (otherwise it is an extra parameter matching an ellipsis).
6329 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6330 *PREGNO records the register number to use if scalar type.
6331 *PPADDING records the amount of padding needed in words. */
6334 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6335 const_tree type
, bool named
, bool incoming
,
6336 int *pregno
, int *ppadding
)
6338 int regbase
= (incoming
6339 ? SPARC_INCOMING_INT_ARG_FIRST
6340 : SPARC_OUTGOING_INT_ARG_FIRST
);
6341 int slotno
= cum
->words
;
6342 enum mode_class mclass
;
6347 if (type
&& TREE_ADDRESSABLE (type
))
6353 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6356 /* For SPARC64, objects requiring 16-byte alignment get it. */
6358 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6359 && (slotno
& 1) != 0)
6360 slotno
++, *ppadding
= 1;
6362 mclass
= GET_MODE_CLASS (mode
);
6363 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6365 /* Vector types deserve special treatment because they are
6366 polymorphic wrt their mode, depending upon whether VIS
6367 instructions are enabled. */
6368 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6370 /* The SPARC port defines no floating-point vector modes. */
6371 gcc_assert (mode
== BLKmode
);
6375 /* Integral vector types should either have a vector
6376 mode or an integral mode, because we are guaranteed
6377 by pass_by_reference that their size is not greater
6378 than 16 bytes and TImode is 16-byte wide. */
6379 gcc_assert (mode
!= BLKmode
);
6381 /* Vector integers are handled like floats according to
6383 mclass
= MODE_FLOAT
;
6390 case MODE_COMPLEX_FLOAT
:
6391 case MODE_VECTOR_INT
:
6392 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6394 /* If all arg slots are filled, then must pass on stack. */
6395 if (slotno
>= SPARC_FP_ARG_MAX
)
6398 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6399 /* Arguments filling only one single FP register are
6400 right-justified in the outer double FP register. */
6401 if (GET_MODE_SIZE (mode
) <= 4)
6408 case MODE_COMPLEX_INT
:
6409 /* If all arg slots are filled, then must pass on stack. */
6410 if (slotno
>= SPARC_INT_ARG_MAX
)
6413 regno
= regbase
+ slotno
;
6417 if (mode
== VOIDmode
)
6418 /* MODE is VOIDmode when generating the actual call. */
6421 gcc_assert (mode
== BLKmode
);
6425 || (TREE_CODE (type
) != RECORD_TYPE
6426 && TREE_CODE (type
) != VECTOR_TYPE
))
6428 /* If all arg slots are filled, then must pass on stack. */
6429 if (slotno
>= SPARC_INT_ARG_MAX
)
6432 regno
= regbase
+ slotno
;
6434 else /* TARGET_ARCH64 && type */
6436 /* If all arg slots are filled, then must pass on stack. */
6437 if (slotno
>= SPARC_FP_ARG_MAX
)
6440 if (TREE_CODE (type
) == RECORD_TYPE
)
6442 classify_data_t data
= { false, false, false };
6443 traverse_record_type
<classify_data_t
, classify_registers
>
6444 (type
, named
, &data
);
6446 /* If all slots are filled except for the last one, but there
6447 is no FP field in the first word, then must pass on stack. */
6449 && !data
.fp_regs_in_first_word
6450 && slotno
>= SPARC_FP_ARG_MAX
- 1)
6453 /* If there are only int args and all int slots are filled,
6454 then must pass on stack. */
6457 && slotno
>= SPARC_INT_ARG_MAX
)
6461 /* PREGNO isn't set since both int and FP regs can be used. */
6474 /* Handle recursive register counting/assigning for structure layout. */
6478 int slotno
; /* slot number of the argument. */
6479 int regbase
; /* regno of the base register. */
6480 int intoffset
; /* offset of the first pending integer field. */
6481 int nregs
; /* number of words passed in registers. */
6482 bool stack
; /* true if part of the argument is on the stack. */
6483 rtx ret
; /* return expression being built. */
6486 /* A subroutine of function_arg_record_value. Compute the number of integer
6487 registers to be assigned between PARMS->intoffset and BITPOS. Return
6488 true if at least one integer register is assigned or false otherwise. */
6491 compute_int_layout (HOST_WIDE_INT bitpos
, assign_data_t
*data
, int *pnregs
)
6493 if (data
->intoffset
< 0)
6496 const int intoffset
= data
->intoffset
;
6497 data
->intoffset
= -1;
6499 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6500 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
6501 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
6502 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6504 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
6506 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
6508 /* We need to pass this field (partly) on the stack. */
6519 /* A subroutine of function_arg_record_value. Compute the number and the mode
6520 of the FP registers to be assigned for FIELD. Return true if at least one
6521 FP register is assigned or false otherwise. */
6524 compute_fp_layout (const_tree field
, HOST_WIDE_INT bitpos
,
6525 assign_data_t
*data
,
6526 int *pnregs
, machine_mode
*pmode
)
6528 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6529 machine_mode mode
= DECL_MODE (field
);
6532 /* Slots are counted as words while regs are counted as having the size of
6533 the (inner) mode. */
6534 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
&& mode
== BLKmode
)
6536 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6537 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6539 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6541 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6547 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
6549 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
6551 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
6552 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
6554 /* We need to pass this field (partly) on the stack. */
6566 /* A subroutine of function_arg_record_value. Count the number of registers
6567 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
6570 count_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6571 assign_data_t
*data
)
6578 if (compute_int_layout (bitpos
, data
, &nregs
))
6579 data
->nregs
+= nregs
;
6581 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6582 data
->nregs
+= nregs
;
6586 if (data
->intoffset
< 0)
6587 data
->intoffset
= bitpos
;
6591 /* A subroutine of function_arg_record_value. Assign the bits of the
6592 structure between PARMS->intoffset and BITPOS to integer registers. */
6595 assign_int_registers (HOST_WIDE_INT bitpos
, assign_data_t
*data
)
6597 int intoffset
= data
->intoffset
;
6601 if (!compute_int_layout (bitpos
, data
, &nregs
))
6604 /* If this is the trailing part of a word, only load that much into
6605 the register. Otherwise load the whole register. Note that in
6606 the latter case we may pick up unwanted bits. It's not a problem
6607 at the moment but may wish to revisit. */
6608 if (intoffset
% BITS_PER_WORD
!= 0)
6609 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6614 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6615 unsigned int regno
= data
->regbase
+ this_slotno
;
6616 intoffset
/= BITS_PER_UNIT
;
6620 rtx reg
= gen_rtx_REG (mode
, regno
);
6621 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6622 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6626 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
6628 while (--nregs
> 0);
6631 /* A subroutine of function_arg_record_value. Assign FIELD at position
6632 BITPOS to FP registers. */
6635 assign_fp_registers (const_tree field
, HOST_WIDE_INT bitpos
,
6636 assign_data_t
*data
)
6641 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6644 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6645 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6646 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6648 int pos
= bitpos
/ BITS_PER_UNIT
;
6652 rtx reg
= gen_rtx_REG (mode
, regno
);
6653 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6654 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6656 regno
+= GET_MODE_SIZE (mode
) / 4;
6657 pos
+= GET_MODE_SIZE (mode
);
6659 while (--nregs
> 0);
6662 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
6663 the structure between PARMS->intoffset and BITPOS to registers. */
6666 assign_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6667 assign_data_t
*data
)
6671 assign_int_registers (bitpos
, data
);
6673 assign_fp_registers (field
, bitpos
, data
);
6677 if (data
->intoffset
< 0)
6678 data
->intoffset
= bitpos
;
6682 /* Used by function_arg and sparc_function_value_1 to implement the complex
6683 conventions of the 64-bit ABI for passing and returning structures.
6684 Return an expression valid as a return value for the FUNCTION_ARG
6685 and TARGET_FUNCTION_VALUE.
6687 TYPE is the data type of the argument (as a tree).
6688 This is null for libcalls where that information may
6690 MODE is the argument's machine mode.
6691 SLOTNO is the index number of the argument's slot in the parameter array.
6692 NAMED is true if this argument is a named parameter
6693 (otherwise it is an extra parameter matching an ellipsis).
6694 REGBASE is the regno of the base register for the parameter array. */
6697 function_arg_record_value (const_tree type
, machine_mode mode
,
6698 int slotno
, bool named
, int regbase
)
6700 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6704 data
.slotno
= slotno
;
6705 data
.regbase
= regbase
;
6707 /* Count how many registers we need. */
6711 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
6713 /* Take into account pending integer fields. */
6714 if (compute_int_layout (typesize
* BITS_PER_UNIT
, &data
, &nregs
))
6715 data
.nregs
+= nregs
;
6717 /* Allocate the vector and handle some annoying special cases. */
6722 /* ??? Empty structure has no value? Duh? */
6725 /* Though there's nothing really to store, return a word register
6726 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6727 leads to breakage due to the fact that there are zero bytes to
6729 return gen_rtx_REG (mode
, regbase
);
6732 /* ??? C++ has structures with no fields, and yet a size. Give up
6733 for now and pass everything back in integer registers. */
6734 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6735 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6736 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6739 gcc_assert (nregs
> 0);
6741 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
6743 /* If at least one field must be passed on the stack, generate
6744 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6745 also be passed on the stack. We can't do much better because the
6746 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6747 of structures for which the fields passed exclusively in registers
6748 are not at the beginning of the structure. */
6750 XVECEXP (data
.ret
, 0, 0)
6751 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6753 /* Assign the registers. */
6756 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
6758 /* Assign pending integer fields. */
6759 assign_int_registers (typesize
* BITS_PER_UNIT
, &data
);
6761 gcc_assert (data
.nregs
== nregs
);
6766 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6767 of the 64-bit ABI for passing and returning unions.
6768 Return an expression valid as a return value for the FUNCTION_ARG
6769 and TARGET_FUNCTION_VALUE.
6771 SIZE is the size in bytes of the union.
6772 MODE is the argument's machine mode.
6773 REGNO is the hard register the union will be passed in. */
6776 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
6779 int nwords
= CEIL_NWORDS (size
), i
;
6782 /* See comment in previous function for empty structures. */
6784 return gen_rtx_REG (mode
, regno
);
6786 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6789 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6791 for (i
= 0; i
< nwords
; i
++)
6793 /* Unions are passed left-justified. */
6794 XVECEXP (regs
, 0, i
)
6795 = gen_rtx_EXPR_LIST (VOIDmode
,
6796 gen_rtx_REG (word_mode
, regno
),
6797 GEN_INT (UNITS_PER_WORD
* i
));
6804 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6805 for passing and returning BLKmode vectors.
6806 Return an expression valid as a return value for the FUNCTION_ARG
6807 and TARGET_FUNCTION_VALUE.
6809 SIZE is the size in bytes of the vector.
6810 REGNO is the FP hard register the vector will be passed in. */
6813 function_arg_vector_value (int size
, int regno
)
6815 const int nregs
= MAX (1, size
/ 8);
6816 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6819 XVECEXP (regs
, 0, 0)
6820 = gen_rtx_EXPR_LIST (VOIDmode
,
6821 gen_rtx_REG (SImode
, regno
),
6824 for (int i
= 0; i
< nregs
; i
++)
6825 XVECEXP (regs
, 0, i
)
6826 = gen_rtx_EXPR_LIST (VOIDmode
,
6827 gen_rtx_REG (DImode
, regno
+ 2*i
),
6833 /* Determine where to put an argument to a function.
6834 Value is zero to push the argument on the stack,
6835 or a hard register in which to store the argument.
6837 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6838 the preceding args and about the function being called.
6839 MODE is the argument's machine mode.
6840 TYPE is the data type of the argument (as a tree).
6841 This is null for libcalls where that information may
6843 NAMED is true if this argument is a named parameter
6844 (otherwise it is an extra parameter matching an ellipsis).
6845 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6846 TARGET_FUNCTION_INCOMING_ARG. */
6849 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
6850 const_tree type
, bool named
, bool incoming
)
6852 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6854 int regbase
= (incoming
6855 ? SPARC_INCOMING_INT_ARG_FIRST
6856 : SPARC_OUTGOING_INT_ARG_FIRST
);
6857 int slotno
, regno
, padding
;
6858 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6860 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming
,
6865 /* Vector types deserve special treatment because they are polymorphic wrt
6866 their mode, depending upon whether VIS instructions are enabled. */
6867 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6869 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6870 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6871 || (TARGET_ARCH64
&& size
<= 16));
6873 if (mode
== BLKmode
)
6874 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
6876 mclass
= MODE_FLOAT
;
6880 return gen_rtx_REG (mode
, regno
);
6882 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6883 and are promoted to registers if possible. */
6884 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6886 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6887 gcc_assert (size
<= 16);
6889 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6892 /* Unions up to 16 bytes in size are passed in integer registers. */
6893 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6895 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6896 gcc_assert (size
<= 16);
6898 return function_arg_union_value (size
, mode
, slotno
, regno
);
6901 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6902 but also have the slot allocated for them.
6903 If no prototype is in scope fp values in register slots get passed
6904 in two places, either fp regs and int regs or fp regs and memory. */
6905 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6906 && SPARC_FP_REG_P (regno
))
6908 rtx reg
= gen_rtx_REG (mode
, regno
);
6909 if (cum
->prototype_p
|| cum
->libcall_p
)
6915 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6919 /* On incoming, we don't need to know that the value
6920 is passed in %f0 and %i0, and it confuses other parts
6921 causing needless spillage even on the simplest cases. */
6925 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6926 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6928 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6929 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6931 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6935 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6936 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6937 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6942 /* All other aggregate types are passed in an integer register in a mode
6943 corresponding to the size of the type. */
6944 else if (type
&& AGGREGATE_TYPE_P (type
))
6946 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6947 gcc_assert (size
<= 16);
6949 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6952 return gen_rtx_REG (mode
, regno
);
6955 /* Handle the TARGET_FUNCTION_ARG target hook. */
6958 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
6959 const_tree type
, bool named
)
6961 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6964 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6967 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
6968 const_tree type
, bool named
)
6970 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6973 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6976 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
6978 return ((TARGET_ARCH64
6979 && (GET_MODE_ALIGNMENT (mode
) == 128
6980 || (type
&& TYPE_ALIGN (type
) == 128)))
6985 /* For an arg passed partly in registers and partly in memory,
6986 this is the number of bytes of registers used.
6987 For args passed entirely in registers or entirely in memory, zero.
6989 Any arg that starts in the first 6 regs but won't entirely fit in them
6990 needs partial registers on v8. On v9, structures with integer
6991 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6992 values that begin in the last fp reg [where "last fp reg" varies with the
6993 mode] will be split between that reg and memory. */
6996 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
6997 tree type
, bool named
)
6999 int slotno
, regno
, padding
;
7001 /* We pass false for incoming here, it doesn't matter. */
7002 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7003 false, ®no
, &padding
);
7010 if ((slotno
+ (mode
== BLKmode
7011 ? CEIL_NWORDS (int_size_in_bytes (type
))
7012 : CEIL_NWORDS (GET_MODE_SIZE (mode
))))
7013 > SPARC_INT_ARG_MAX
)
7014 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7018 /* We are guaranteed by pass_by_reference that the size of the
7019 argument is not greater than 16 bytes, so we only need to return
7020 one word if the argument is partially passed in registers. */
7022 if (type
&& AGGREGATE_TYPE_P (type
))
7024 int size
= int_size_in_bytes (type
);
7026 if (size
> UNITS_PER_WORD
7027 && (slotno
== SPARC_INT_ARG_MAX
- 1
7028 || slotno
== SPARC_FP_ARG_MAX
- 1))
7029 return UNITS_PER_WORD
;
7031 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7032 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7033 && ! (TARGET_FPU
&& named
)))
7035 /* The complex types are passed as packed types. */
7036 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7037 && slotno
== SPARC_INT_ARG_MAX
- 1)
7038 return UNITS_PER_WORD
;
7040 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7042 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7044 return UNITS_PER_WORD
;
7051 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7052 Specify whether to pass the argument by reference. */
7055 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7056 machine_mode mode
, const_tree type
,
7057 bool named ATTRIBUTE_UNUSED
)
7060 /* Original SPARC 32-bit ABI says that structures and unions,
7061 and quad-precision floats are passed by reference. For Pascal,
7062 also pass arrays by reference. All other base types are passed
7065 Extended ABI (as implemented by the Sun compiler) says that all
7066 complex floats are passed by reference. Pass complex integers
7067 in registers up to 8 bytes. More generally, enforce the 2-word
7068 cap for passing arguments in registers.
7070 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7071 integers are passed like floats of the same size, that is in
7072 registers up to 8 bytes. Pass all vector floats by reference
7073 like structure and unions. */
7074 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7076 /* Catch CDImode, TFmode, DCmode and TCmode. */
7077 || GET_MODE_SIZE (mode
) > 8
7079 && TREE_CODE (type
) == VECTOR_TYPE
7080 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7082 /* Original SPARC 64-bit ABI says that structures and unions
7083 smaller than 16 bytes are passed in registers, as well as
7084 all other base types.
7086 Extended ABI (as implemented by the Sun compiler) says that
7087 complex floats are passed in registers up to 16 bytes. Pass
7088 all complex integers in registers up to 16 bytes. More generally,
7089 enforce the 2-word cap for passing arguments in registers.
7091 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7092 integers are passed like floats of the same size, that is in
7093 registers (up to 16 bytes). Pass all vector floats like structure
7096 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7097 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7098 /* Catch CTImode and TCmode. */
7099 || GET_MODE_SIZE (mode
) > 16);
7102 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7103 Update the data in CUM to advance over an argument
7104 of mode MODE and data type TYPE.
7105 TYPE is null for libcalls where that information may not be available. */
7108 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7109 const_tree type
, bool named
)
7111 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7114 /* We pass false for incoming here, it doesn't matter. */
7115 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7117 /* If argument requires leading padding, add it. */
7118 cum
->words
+= padding
;
7121 cum
->words
+= (mode
== BLKmode
7122 ? CEIL_NWORDS (int_size_in_bytes (type
))
7123 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7126 if (type
&& AGGREGATE_TYPE_P (type
))
7128 int size
= int_size_in_bytes (type
);
7132 else if (size
<= 16)
7134 else /* passed by reference */
7138 cum
->words
+= (mode
== BLKmode
7139 ? CEIL_NWORDS (int_size_in_bytes (type
))
7140 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7144 /* Handle the FUNCTION_ARG_PADDING macro.
7145 For the 64 bit ABI structs are always stored left shifted in their
7149 function_arg_padding (machine_mode mode
, const_tree type
)
7151 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7154 /* Fall back to the default. */
7155 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7158 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7159 Specify whether to return the return value in memory. */
7162 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7165 /* Original SPARC 32-bit ABI says that structures and unions,
7166 and quad-precision floats are returned in memory. All other
7167 base types are returned in registers.
7169 Extended ABI (as implemented by the Sun compiler) says that
7170 all complex floats are returned in registers (8 FP registers
7171 at most for '_Complex long double'). Return all complex integers
7172 in registers (4 at most for '_Complex long long').
7174 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7175 integers are returned like floats of the same size, that is in
7176 registers up to 8 bytes and in memory otherwise. Return all
7177 vector floats in memory like structure and unions; note that
7178 they always have BLKmode like the latter. */
7179 return (TYPE_MODE (type
) == BLKmode
7180 || TYPE_MODE (type
) == TFmode
7181 || (TREE_CODE (type
) == VECTOR_TYPE
7182 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7184 /* Original SPARC 64-bit ABI says that structures and unions
7185 smaller than 32 bytes are returned in registers, as well as
7186 all other base types.
7188 Extended ABI (as implemented by the Sun compiler) says that all
7189 complex floats are returned in registers (8 FP registers at most
7190 for '_Complex long double'). Return all complex integers in
7191 registers (4 at most for '_Complex TItype').
7193 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7194 integers are returned like floats of the same size, that is in
7195 registers. Return all vector floats like structure and unions;
7196 note that they always have BLKmode like the latter. */
7197 return (TYPE_MODE (type
) == BLKmode
7198 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7201 /* Handle the TARGET_STRUCT_VALUE target hook.
7202 Return where to find the structure return value address. */
7205 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7214 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7215 STRUCT_VALUE_OFFSET
));
7217 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7218 STRUCT_VALUE_OFFSET
));
7220 /* Only follow the SPARC ABI for fixed-size structure returns.
7221 Variable size structure returns are handled per the normal
7222 procedures in GCC. This is enabled by -mstd-struct-return */
7224 && sparc_std_struct_return
7225 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7226 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7228 /* We must check and adjust the return address, as it is optional
7229 as to whether the return object is really provided. */
7230 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7231 rtx scratch
= gen_reg_rtx (SImode
);
7232 rtx_code_label
*endlab
= gen_label_rtx ();
7234 /* Calculate the return object size. */
7235 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7236 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7237 /* Construct a temporary return value. */
7239 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7241 /* Implement SPARC 32-bit psABI callee return struct checking:
7243 Fetch the instruction where we will return to and see if
7244 it's an unimp instruction (the most significant 10 bits
7246 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7247 plus_constant (Pmode
,
7249 /* Assume the size is valid and pre-adjust. */
7250 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7251 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7253 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7254 /* Write the address of the memory pointed to by temp_val into
7255 the memory pointed to by mem. */
7256 emit_move_insn (mem
, XEXP (temp_val
, 0));
7257 emit_label (endlab
);
7264 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7265 For v9, function return values are subject to the same rules as arguments,
7266 except that up to 32 bytes may be returned in registers. */
7269 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7272 /* Beware that the two values are swapped here wrt function_arg. */
7273 int regbase
= (outgoing
7274 ? SPARC_INCOMING_INT_ARG_FIRST
7275 : SPARC_OUTGOING_INT_ARG_FIRST
);
7276 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7279 /* Vector types deserve special treatment because they are polymorphic wrt
7280 their mode, depending upon whether VIS instructions are enabled. */
7281 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7283 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7284 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7285 || (TARGET_ARCH64
&& size
<= 32));
7287 if (mode
== BLKmode
)
7288 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7290 mclass
= MODE_FLOAT
;
7293 if (TARGET_ARCH64
&& type
)
7295 /* Structures up to 32 bytes in size are returned in registers. */
7296 if (TREE_CODE (type
) == RECORD_TYPE
)
7298 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7299 gcc_assert (size
<= 32);
7301 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7304 /* Unions up to 32 bytes in size are returned in integer registers. */
7305 else if (TREE_CODE (type
) == UNION_TYPE
)
7307 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7308 gcc_assert (size
<= 32);
7310 return function_arg_union_value (size
, mode
, 0, regbase
);
7313 /* Objects that require it are returned in FP registers. */
7314 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7317 /* All other aggregate types are returned in an integer register in a
7318 mode corresponding to the size of the type. */
7319 else if (AGGREGATE_TYPE_P (type
))
7321 /* All other aggregate types are passed in an integer register
7322 in a mode corresponding to the size of the type. */
7323 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7324 gcc_assert (size
<= 32);
7326 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7328 /* ??? We probably should have made the same ABI change in
7329 3.4.0 as the one we made for unions. The latter was
7330 required by the SCD though, while the former is not
7331 specified, so we favored compatibility and efficiency.
7333 Now we're stuck for aggregates larger than 16 bytes,
7334 because OImode vanished in the meantime. Let's not
7335 try to be unduly clever, and simply follow the ABI
7336 for unions in that case. */
7337 if (mode
== BLKmode
)
7338 return function_arg_union_value (size
, mode
, 0, regbase
);
7343 /* We should only have pointer and integer types at this point. This
7344 must match sparc_promote_function_mode. */
7345 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7349 /* We should only have pointer and integer types at this point, except with
7350 -freg-struct-return. This must match sparc_promote_function_mode. */
7351 else if (TARGET_ARCH32
7352 && !(type
&& AGGREGATE_TYPE_P (type
))
7353 && mclass
== MODE_INT
7354 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7357 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7358 regno
= SPARC_FP_ARG_FIRST
;
7362 return gen_rtx_REG (mode
, regno
);
7365 /* Handle TARGET_FUNCTION_VALUE.
7366 On the SPARC, the value is found in the first "output" register, but the
7367 called function leaves it in the first "input" register. */
7370 sparc_function_value (const_tree valtype
,
7371 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7374 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7377 /* Handle TARGET_LIBCALL_VALUE. */
7380 sparc_libcall_value (machine_mode mode
,
7381 const_rtx fun ATTRIBUTE_UNUSED
)
7383 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7386 /* Handle FUNCTION_VALUE_REGNO_P.
7387 On the SPARC, the first "output" reg is used for integer values, and the
7388 first floating point register is used for floating point values. */
7391 sparc_function_value_regno_p (const unsigned int regno
)
7393 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7396 /* Do what is necessary for `va_start'. We look at the current function
7397 to determine if stdarg or varargs is used and return the address of
7398 the first unnamed parameter. */
7401 sparc_builtin_saveregs (void)
7403 int first_reg
= crtl
->args
.info
.words
;
7407 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7408 emit_move_insn (gen_rtx_MEM (word_mode
,
7409 gen_rtx_PLUS (Pmode
,
7411 GEN_INT (FIRST_PARM_OFFSET (0)
7414 gen_rtx_REG (word_mode
,
7415 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7417 address
= gen_rtx_PLUS (Pmode
,
7419 GEN_INT (FIRST_PARM_OFFSET (0)
7420 + UNITS_PER_WORD
* first_reg
));
7425 /* Implement `va_start' for stdarg. */
7428 sparc_va_start (tree valist
, rtx nextarg
)
7430 nextarg
= expand_builtin_saveregs ();
7431 std_expand_builtin_va_start (valist
, nextarg
);
7434 /* Implement `va_arg' for stdarg. */
7437 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7440 HOST_WIDE_INT size
, rsize
, align
;
7443 tree ptrtype
= build_pointer_type (type
);
7445 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7448 size
= rsize
= UNITS_PER_WORD
;
7454 size
= int_size_in_bytes (type
);
7455 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7460 /* For SPARC64, objects requiring 16-byte alignment get it. */
7461 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7462 align
= 2 * UNITS_PER_WORD
;
7464 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7465 are left-justified in their slots. */
7466 if (AGGREGATE_TYPE_P (type
))
7469 size
= rsize
= UNITS_PER_WORD
;
7479 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7480 incr
= fold_convert (sizetype
, incr
);
7481 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7483 incr
= fold_convert (ptr_type_node
, incr
);
7486 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7489 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7490 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7494 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7495 addr
= build_va_arg_indirect_ref (addr
);
7498 /* If the address isn't aligned properly for the type, we need a temporary.
7499 FIXME: This is inefficient, usually we can do this in registers. */
7500 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7502 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7503 tree dest_addr
= build_fold_addr_expr (tmp
);
7504 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7505 3, dest_addr
, addr
, size_int (rsize
));
7506 TREE_ADDRESSABLE (tmp
) = 1;
7507 gimplify_and_add (copy
, pre_p
);
7512 addr
= fold_convert (ptrtype
, addr
);
7514 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7515 gimplify_assign (valist
, incr
, post_p
);
7517 return build_va_arg_indirect_ref (addr
);
7520 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7521 Specify whether the vector mode is supported by the hardware. */
7524 sparc_vector_mode_supported_p (machine_mode mode
)
7526 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7529 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7532 sparc_preferred_simd_mode (machine_mode mode
)
7550 /* Return the string to output an unconditional branch to LABEL, which is
7551 the operand number of the label.
7553 DEST is the destination insn (i.e. the label), INSN is the source. */
7556 output_ubranch (rtx dest
, rtx_insn
*insn
)
7558 static char string
[64];
7559 bool v9_form
= false;
7563 /* Even if we are trying to use cbcond for this, evaluate
7564 whether we can use V9 branches as our backup plan. */
7567 if (INSN_ADDRESSES_SET_P ())
7568 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7569 - INSN_ADDRESSES (INSN_UID (insn
)));
7571 /* Leave some instructions for "slop". */
7572 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7577 bool emit_nop
= emit_cbcond_nop (insn
);
7581 if (delta
< -500 || delta
> 500)
7587 rval
= "ba,a,pt\t%%xcc, %l0";
7594 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7596 rval
= "cwbe\t%%g0, %%g0, %l0";
7602 strcpy (string
, "ba%*,pt\t%%xcc, ");
7604 strcpy (string
, "b%*\t");
7606 p
= strchr (string
, '\0');
7617 /* Return the string to output a conditional branch to LABEL, which is
7618 the operand number of the label. OP is the conditional expression.
7619 XEXP (OP, 0) is assumed to be a condition code register (integer or
7620 floating point) and its mode specifies what kind of comparison we made.
7622 DEST is the destination insn (i.e. the label), INSN is the source.
7624 REVERSED is nonzero if we should reverse the sense of the comparison.
7626 ANNUL is nonzero if we should generate an annulling branch. */
7629 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7632 static char string
[64];
7633 enum rtx_code code
= GET_CODE (op
);
7634 rtx cc_reg
= XEXP (op
, 0);
7635 machine_mode mode
= GET_MODE (cc_reg
);
7636 const char *labelno
, *branch
;
7637 int spaces
= 8, far
;
7640 /* v9 branches are limited to +-1MB. If it is too far away,
7653 fbne,a,pn %fcc2, .LC29
7661 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7664 /* Reversal of FP compares takes care -- an ordered compare
7665 becomes an unordered compare and vice versa. */
7666 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7667 code
= reverse_condition_maybe_unordered (code
);
7669 code
= reverse_condition (code
);
7672 /* Start by writing the branch condition. */
7673 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7724 /* ??? !v9: FP branches cannot be preceded by another floating point
7725 insn. Because there is currently no concept of pre-delay slots,
7726 we can fix this only by always emitting a nop before a floating
7731 strcpy (string
, "nop\n\t");
7732 strcat (string
, branch
);
7745 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7757 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7778 strcpy (string
, branch
);
7780 spaces
-= strlen (branch
);
7781 p
= strchr (string
, '\0');
7783 /* Now add the annulling, the label, and a possible noop. */
7796 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7798 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7799 - INSN_ADDRESSES (INSN_UID (insn
)));
7800 /* Leave some instructions for "slop". */
7801 if (delta
< -260000 || delta
>= 260000)
7805 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7807 static char v9_fcc_labelno
[] = "%%fccX, ";
7808 /* Set the char indicating the number of the fcc reg to use. */
7809 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7810 labelno
= v9_fcc_labelno
;
7813 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7817 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7819 labelno
= "%%xcc, ";
7824 labelno
= "%%icc, ";
7829 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7832 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7845 strcpy (p
, labelno
);
7846 p
= strchr (p
, '\0');
7849 strcpy (p
, ".+12\n\t nop\n\tb\t");
7850 /* Skip the next insn if requested or
7851 if we know that it will be a nop. */
7852 if (annul
|| ! final_sequence
)
7866 /* Emit a library call comparison between floating point X and Y.
7867 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7868 Return the new operator to be used in the comparison sequence.
7870 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7871 values as arguments instead of the TFmode registers themselves,
7872 that's why we cannot call emit_float_lib_cmp. */
7875 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7878 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7880 enum rtx_code new_comparison
;
7885 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7889 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7893 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7897 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7901 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7905 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7916 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7927 tree expr
= MEM_EXPR (x
);
7929 mark_addressable (expr
);
7934 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7935 emit_move_insn (slot0
, x
);
7940 tree expr
= MEM_EXPR (y
);
7942 mark_addressable (expr
);
7947 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7948 emit_move_insn (slot1
, y
);
7951 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7952 emit_library_call (libfunc
, LCT_NORMAL
,
7954 XEXP (slot0
, 0), Pmode
,
7955 XEXP (slot1
, 0), Pmode
);
7960 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7961 emit_library_call (libfunc
, LCT_NORMAL
,
7963 x
, TFmode
, y
, TFmode
);
7968 /* Immediately move the result of the libcall into a pseudo
7969 register so reload doesn't clobber the value if it needs
7970 the return register for a spill reg. */
7971 result
= gen_reg_rtx (mode
);
7972 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7977 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7980 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7981 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7984 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7985 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7987 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7989 tem
= gen_reg_rtx (mode
);
7991 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7993 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7994 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7997 tem
= gen_reg_rtx (mode
);
7999 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8001 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8002 tem2
= gen_reg_rtx (mode
);
8004 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8006 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8007 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8008 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8014 /* Generate an unsigned DImode to FP conversion. This is the same code
8015 optabs would emit if we didn't have TFmode patterns. */
8018 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8020 rtx i0
, i1
, f0
, in
, out
;
8023 in
= force_reg (DImode
, operands
[1]);
8024 rtx_code_label
*neglab
= gen_label_rtx ();
8025 rtx_code_label
*donelab
= gen_label_rtx ();
8026 i0
= gen_reg_rtx (DImode
);
8027 i1
= gen_reg_rtx (DImode
);
8028 f0
= gen_reg_rtx (mode
);
8030 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8032 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8033 emit_jump_insn (gen_jump (donelab
));
8036 emit_label (neglab
);
8038 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8039 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8040 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8041 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8042 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8044 emit_label (donelab
);
8047 /* Generate an FP to unsigned DImode conversion. This is the same code
8048 optabs would emit if we didn't have TFmode patterns. */
8051 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8053 rtx i0
, i1
, f0
, in
, out
, limit
;
8056 in
= force_reg (mode
, operands
[1]);
8057 rtx_code_label
*neglab
= gen_label_rtx ();
8058 rtx_code_label
*donelab
= gen_label_rtx ();
8059 i0
= gen_reg_rtx (DImode
);
8060 i1
= gen_reg_rtx (DImode
);
8061 limit
= gen_reg_rtx (mode
);
8062 f0
= gen_reg_rtx (mode
);
8064 emit_move_insn (limit
,
8065 const_double_from_real_value (
8066 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8067 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8069 emit_insn (gen_rtx_SET (out
,
8070 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8071 emit_jump_insn (gen_jump (donelab
));
8074 emit_label (neglab
);
8076 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8077 emit_insn (gen_rtx_SET (i0
,
8078 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8079 emit_insn (gen_movdi (i1
, const1_rtx
));
8080 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8081 emit_insn (gen_xordi3 (out
, i0
, i1
));
8083 emit_label (donelab
);
8086 /* Return the string to output a compare and branch instruction to DEST.
8087 DEST is the destination insn (i.e. the label), INSN is the source,
8088 and OP is the conditional expression. */
8091 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8093 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8094 enum rtx_code code
= GET_CODE (op
);
8095 const char *cond_str
, *tmpl
;
8096 int far
, emit_nop
, len
;
8097 static char string
[64];
8100 /* Compare and Branch is limited to +-2KB. If it is too far away,
8112 len
= get_attr_length (insn
);
8115 emit_nop
= len
== 2;
8118 code
= reverse_condition (code
);
8120 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8133 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8148 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8176 int veryfar
= 1, delta
;
8178 if (INSN_ADDRESSES_SET_P ())
8180 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8181 - INSN_ADDRESSES (INSN_UID (insn
)));
8182 /* Leave some instructions for "slop". */
8183 if (delta
>= -260000 && delta
< 260000)
8188 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8190 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8195 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8197 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8200 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8205 /* Return the string to output a conditional branch to LABEL, testing
8206 register REG. LABEL is the operand number of the label; REG is the
8207 operand number of the reg. OP is the conditional expression. The mode
8208 of REG says what kind of comparison we made.
8210 DEST is the destination insn (i.e. the label), INSN is the source.
8212 REVERSED is nonzero if we should reverse the sense of the comparison.
8214 ANNUL is nonzero if we should generate an annulling branch. */
8217 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8218 int annul
, rtx_insn
*insn
)
8220 static char string
[64];
8221 enum rtx_code code
= GET_CODE (op
);
8222 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8227 /* branch on register are limited to +-128KB. If it is too far away,
8240 brgez,a,pn %o1, .LC29
8246 ba,pt %xcc, .LC29 */
8248 far
= get_attr_length (insn
) >= 3;
8250 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8252 code
= reverse_condition (code
);
8254 /* Only 64 bit versions of these instructions exist. */
8255 gcc_assert (mode
== DImode
);
8257 /* Start by writing the branch condition. */
8262 strcpy (string
, "brnz");
8266 strcpy (string
, "brz");
8270 strcpy (string
, "brgez");
8274 strcpy (string
, "brlz");
8278 strcpy (string
, "brlez");
8282 strcpy (string
, "brgz");
8289 p
= strchr (string
, '\0');
8291 /* Now add the annulling, reg, label, and nop. */
8298 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8301 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
8306 *p
= p
< string
+ 8 ? '\t' : ' ';
8314 int veryfar
= 1, delta
;
8316 if (INSN_ADDRESSES_SET_P ())
8318 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8319 - INSN_ADDRESSES (INSN_UID (insn
)));
8320 /* Leave some instructions for "slop". */
8321 if (delta
>= -260000 && delta
< 260000)
8325 strcpy (p
, ".+12\n\t nop\n\t");
8326 /* Skip the next insn if requested or
8327 if we know that it will be a nop. */
8328 if (annul
|| ! final_sequence
)
8338 strcpy (p
, "ba,pt\t%%xcc, ");
8352 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8353 Such instructions cannot be used in the delay slot of return insn on v9.
8354 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8358 epilogue_renumber (register rtx
*where
, int test
)
8360 register const char *fmt
;
8362 register enum rtx_code code
;
8367 code
= GET_CODE (*where
);
8372 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8374 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8375 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8381 case CONST_WIDE_INT
:
8385 /* Do not replace the frame pointer with the stack pointer because
8386 it can cause the delayed instruction to load below the stack.
8387 This occurs when instructions like:
8389 (set (reg/i:SI 24 %i0)
8390 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8391 (const_int -20 [0xffffffec])) 0))
8393 are in the return delayed slot. */
8395 if (GET_CODE (XEXP (*where
, 0)) == REG
8396 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8397 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8398 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8403 if (SPARC_STACK_BIAS
8404 && GET_CODE (XEXP (*where
, 0)) == REG
8405 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8413 fmt
= GET_RTX_FORMAT (code
);
8415 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8420 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8421 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8424 else if (fmt
[i
] == 'e'
8425 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8431 /* Leaf functions and non-leaf functions have different needs. */
8434 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8437 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8439 static const int *const reg_alloc_orders
[] = {
8440 reg_leaf_alloc_order
,
8441 reg_nonleaf_alloc_order
};
8444 order_regs_for_local_alloc (void)
8446 static int last_order_nonleaf
= 1;
8448 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8450 last_order_nonleaf
= !last_order_nonleaf
;
8451 memcpy ((char *) reg_alloc_order
,
8452 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8453 FIRST_PSEUDO_REGISTER
* sizeof (int));
8457 /* Return 1 if REG and MEM are legitimate enough to allow the various
8458 mem<-->reg splits to be run. */
8461 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8463 /* Punt if we are here by mistake. */
8464 gcc_assert (reload_completed
);
8466 /* We must have an offsettable memory reference. */
8467 if (! offsettable_memref_p (mem
))
8470 /* If we have legitimate args for ldd/std, we do not want
8471 the split to happen. */
8472 if ((REGNO (reg
) % 2) == 0
8473 && mem_min_alignment (mem
, 8))
8480 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8483 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8487 if (GET_CODE (reg1
) == SUBREG
)
8488 reg1
= SUBREG_REG (reg1
);
8489 if (GET_CODE (reg1
) != REG
)
8491 regno1
= REGNO (reg1
);
8493 if (GET_CODE (reg2
) == SUBREG
)
8494 reg2
= SUBREG_REG (reg2
);
8495 if (GET_CODE (reg2
) != REG
)
8497 regno2
= REGNO (reg2
);
8499 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8504 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8505 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8512 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8513 This makes them candidates for using ldd and std insns.
8515 Note reg1 and reg2 *must* be hard registers. */
8518 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8520 /* We might have been passed a SUBREG. */
8521 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8524 if (REGNO (reg1
) % 2 != 0)
8527 /* Integer ldd is deprecated in SPARC V9 */
8528 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8531 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8534 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8537 This can only happen when addr1 and addr2, the addresses in mem1
8538 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8539 addr1 must also be aligned on a 64-bit boundary.
8541 Also iff dependent_reg_rtx is not null it should not be used to
8542 compute the address for mem1, i.e. we cannot optimize a sequence
8554 But, note that the transformation from:
8559 is perfectly fine. Thus, the peephole2 patterns always pass us
8560 the destination register of the first load, never the second one.
8562 For stores we don't have a similar problem, so dependent_reg_rtx is
8566 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8570 HOST_WIDE_INT offset1
;
8572 /* The mems cannot be volatile. */
8573 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8576 /* MEM1 should be aligned on a 64-bit boundary. */
8577 if (MEM_ALIGN (mem1
) < 64)
8580 addr1
= XEXP (mem1
, 0);
8581 addr2
= XEXP (mem2
, 0);
8583 /* Extract a register number and offset (if used) from the first addr. */
8584 if (GET_CODE (addr1
) == PLUS
)
8586 /* If not a REG, return zero. */
8587 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8591 reg1
= REGNO (XEXP (addr1
, 0));
8592 /* The offset must be constant! */
8593 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8595 offset1
= INTVAL (XEXP (addr1
, 1));
8598 else if (GET_CODE (addr1
) != REG
)
8602 reg1
= REGNO (addr1
);
8603 /* This was a simple (mem (reg)) expression. Offset is 0. */
8607 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8608 if (GET_CODE (addr2
) != PLUS
)
8611 if (GET_CODE (XEXP (addr2
, 0)) != REG
8612 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8615 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8618 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8621 /* The first offset must be evenly divisible by 8 to ensure the
8622 address is 64 bit aligned. */
8623 if (offset1
% 8 != 0)
8626 /* The offset for the second addr must be 4 more than the first addr. */
8627 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8630 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8635 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8638 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
8640 rtx x
= widen_memory_access (mem1
, mode
, 0);
8641 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8645 /* Return 1 if reg is a pseudo, or is the first register in
8646 a hard register pair. This makes it suitable for use in
8647 ldd and std insns. */
8650 register_ok_for_ldd (rtx reg
)
8652 /* We might have been passed a SUBREG. */
8656 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8657 return (REGNO (reg
) % 2 == 0);
8662 /* Return 1 if OP, a MEM, has an address which is known to be
8663 aligned to an 8-byte boundary. */
8666 memory_ok_for_ldd (rtx op
)
8668 /* In 64-bit mode, we assume that the address is word-aligned. */
8669 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8672 if (! can_create_pseudo_p ()
8673 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8679 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8682 sparc_print_operand_punct_valid_p (unsigned char code
)
8695 /* Implement TARGET_PRINT_OPERAND.
8696 Print operand X (an rtx) in assembler syntax to file FILE.
8697 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8698 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8701 sparc_print_operand (FILE *file
, rtx x
, int code
)
8706 /* Output an insn in a delay slot. */
8708 sparc_indent_opcode
= 1;
8710 fputs ("\n\t nop", file
);
8713 /* Output an annul flag if there's nothing for the delay slot and we
8714 are optimizing. This is always used with '(' below.
8715 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8716 this is a dbx bug. So, we only do this when optimizing.
8717 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8718 Always emit a nop in case the next instruction is a branch. */
8719 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8723 /* Output a 'nop' if there's nothing for the delay slot and we are
8724 not optimizing. This is always used with '*' above. */
8725 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8726 fputs ("\n\t nop", file
);
8727 else if (final_sequence
)
8728 sparc_indent_opcode
= 1;
8731 /* Output the right displacement from the saved PC on function return.
8732 The caller may have placed an "unimp" insn immediately after the call
8733 so we have to account for it. This insn is used in the 32-bit ABI
8734 when calling a function that returns a non zero-sized structure. The
8735 64-bit ABI doesn't have it. Be careful to have this test be the same
8736 as that for the call. The exception is when sparc_std_struct_return
8737 is enabled, the psABI is followed exactly and the adjustment is made
8738 by the code in sparc_struct_value_rtx. The call emitted is the same
8739 when sparc_std_struct_return is enabled. */
8741 && cfun
->returns_struct
8742 && !sparc_std_struct_return
8743 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8744 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8746 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8752 /* Output the Embedded Medium/Anywhere code model base register. */
8753 fputs (EMBMEDANY_BASE_REG
, file
);
8756 /* Print some local dynamic TLS name. */
8757 if (const char *name
= get_some_local_dynamic_name ())
8758 assemble_name (file
, name
);
8760 output_operand_lossage ("'%%&' used without any "
8761 "local dynamic TLS references");
8765 /* Adjust the operand to take into account a RESTORE operation. */
8766 if (GET_CODE (x
) == CONST_INT
)
8768 else if (GET_CODE (x
) != REG
)
8769 output_operand_lossage ("invalid %%Y operand");
8770 else if (REGNO (x
) < 8)
8771 fputs (reg_names
[REGNO (x
)], file
);
8772 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8773 fputs (reg_names
[REGNO (x
)-16], file
);
8775 output_operand_lossage ("invalid %%Y operand");
8778 /* Print out the low order register name of a register pair. */
8779 if (WORDS_BIG_ENDIAN
)
8780 fputs (reg_names
[REGNO (x
)+1], file
);
8782 fputs (reg_names
[REGNO (x
)], file
);
8785 /* Print out the high order register name of a register pair. */
8786 if (WORDS_BIG_ENDIAN
)
8787 fputs (reg_names
[REGNO (x
)], file
);
8789 fputs (reg_names
[REGNO (x
)+1], file
);
8792 /* Print out the second register name of a register pair or quad.
8793 I.e., R (%o0) => %o1. */
8794 fputs (reg_names
[REGNO (x
)+1], file
);
8797 /* Print out the third register name of a register quad.
8798 I.e., S (%o0) => %o2. */
8799 fputs (reg_names
[REGNO (x
)+2], file
);
8802 /* Print out the fourth register name of a register quad.
8803 I.e., T (%o0) => %o3. */
8804 fputs (reg_names
[REGNO (x
)+3], file
);
8807 /* Print a condition code register. */
8808 if (REGNO (x
) == SPARC_ICC_REG
)
8810 /* We don't handle CC[X]_NOOVmode because they're not supposed
8812 if (GET_MODE (x
) == CCmode
)
8813 fputs ("%icc", file
);
8814 else if (GET_MODE (x
) == CCXmode
)
8815 fputs ("%xcc", file
);
8820 /* %fccN register */
8821 fputs (reg_names
[REGNO (x
)], file
);
8824 /* Print the operand's address only. */
8825 output_address (GET_MODE (x
), XEXP (x
, 0));
8828 /* In this case we need a register. Use %g0 if the
8829 operand is const0_rtx. */
8831 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8833 fputs ("%g0", file
);
8840 switch (GET_CODE (x
))
8842 case IOR
: fputs ("or", file
); break;
8843 case AND
: fputs ("and", file
); break;
8844 case XOR
: fputs ("xor", file
); break;
8845 default: output_operand_lossage ("invalid %%A operand");
8850 switch (GET_CODE (x
))
8852 case IOR
: fputs ("orn", file
); break;
8853 case AND
: fputs ("andn", file
); break;
8854 case XOR
: fputs ("xnor", file
); break;
8855 default: output_operand_lossage ("invalid %%B operand");
8859 /* This is used by the conditional move instructions. */
8862 enum rtx_code rc
= GET_CODE (x
);
8866 case NE
: fputs ("ne", file
); break;
8867 case EQ
: fputs ("e", file
); break;
8868 case GE
: fputs ("ge", file
); break;
8869 case GT
: fputs ("g", file
); break;
8870 case LE
: fputs ("le", file
); break;
8871 case LT
: fputs ("l", file
); break;
8872 case GEU
: fputs ("geu", file
); break;
8873 case GTU
: fputs ("gu", file
); break;
8874 case LEU
: fputs ("leu", file
); break;
8875 case LTU
: fputs ("lu", file
); break;
8876 case LTGT
: fputs ("lg", file
); break;
8877 case UNORDERED
: fputs ("u", file
); break;
8878 case ORDERED
: fputs ("o", file
); break;
8879 case UNLT
: fputs ("ul", file
); break;
8880 case UNLE
: fputs ("ule", file
); break;
8881 case UNGT
: fputs ("ug", file
); break;
8882 case UNGE
: fputs ("uge", file
); break;
8883 case UNEQ
: fputs ("ue", file
); break;
8884 default: output_operand_lossage ("invalid %%C operand");
8889 /* This are used by the movr instruction pattern. */
8892 enum rtx_code rc
= GET_CODE (x
);
8895 case NE
: fputs ("ne", file
); break;
8896 case EQ
: fputs ("e", file
); break;
8897 case GE
: fputs ("gez", file
); break;
8898 case LT
: fputs ("lz", file
); break;
8899 case LE
: fputs ("lez", file
); break;
8900 case GT
: fputs ("gz", file
); break;
8901 default: output_operand_lossage ("invalid %%D operand");
8908 /* Print a sign-extended character. */
8909 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8910 fprintf (file
, "%d", i
);
8915 /* Operand must be a MEM; write its address. */
8916 if (GET_CODE (x
) != MEM
)
8917 output_operand_lossage ("invalid %%f operand");
8918 output_address (GET_MODE (x
), XEXP (x
, 0));
8923 /* Print a sign-extended 32-bit value. */
8925 if (GET_CODE(x
) == CONST_INT
)
8929 output_operand_lossage ("invalid %%s operand");
8932 i
= trunc_int_for_mode (i
, SImode
);
8933 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8938 /* Do nothing special. */
8942 /* Undocumented flag. */
8943 output_operand_lossage ("invalid operand output code");
8946 if (GET_CODE (x
) == REG
)
8947 fputs (reg_names
[REGNO (x
)], file
);
8948 else if (GET_CODE (x
) == MEM
)
8951 /* Poor Sun assembler doesn't understand absolute addressing. */
8952 if (CONSTANT_P (XEXP (x
, 0)))
8953 fputs ("%g0+", file
);
8954 output_address (GET_MODE (x
), XEXP (x
, 0));
8957 else if (GET_CODE (x
) == HIGH
)
8959 fputs ("%hi(", file
);
8960 output_addr_const (file
, XEXP (x
, 0));
8963 else if (GET_CODE (x
) == LO_SUM
)
8965 sparc_print_operand (file
, XEXP (x
, 0), 0);
8966 if (TARGET_CM_MEDMID
)
8967 fputs ("+%l44(", file
);
8969 fputs ("+%lo(", file
);
8970 output_addr_const (file
, XEXP (x
, 1));
8973 else if (GET_CODE (x
) == CONST_DOUBLE
)
8974 output_operand_lossage ("floating-point constant not a valid immediate operand");
8976 output_addr_const (file
, x
);
8979 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8982 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
8984 register rtx base
, index
= 0;
8986 register rtx addr
= x
;
8989 fputs (reg_names
[REGNO (addr
)], file
);
8990 else if (GET_CODE (addr
) == PLUS
)
8992 if (CONST_INT_P (XEXP (addr
, 0)))
8993 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8994 else if (CONST_INT_P (XEXP (addr
, 1)))
8995 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8997 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8998 if (GET_CODE (base
) == LO_SUM
)
9000 gcc_assert (USE_AS_OFFSETABLE_LO10
9002 && ! TARGET_CM_MEDMID
);
9003 output_operand (XEXP (base
, 0), 0);
9004 fputs ("+%lo(", file
);
9005 output_address (VOIDmode
, XEXP (base
, 1));
9006 fprintf (file
, ")+%d", offset
);
9010 fputs (reg_names
[REGNO (base
)], file
);
9012 fprintf (file
, "%+d", offset
);
9013 else if (REG_P (index
))
9014 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9015 else if (GET_CODE (index
) == SYMBOL_REF
9016 || GET_CODE (index
) == LABEL_REF
9017 || GET_CODE (index
) == CONST
)
9018 fputc ('+', file
), output_addr_const (file
, index
);
9019 else gcc_unreachable ();
9022 else if (GET_CODE (addr
) == MINUS
9023 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9025 output_addr_const (file
, XEXP (addr
, 0));
9027 output_addr_const (file
, XEXP (addr
, 1));
9028 fputs ("-.)", file
);
9030 else if (GET_CODE (addr
) == LO_SUM
)
9032 output_operand (XEXP (addr
, 0), 0);
9033 if (TARGET_CM_MEDMID
)
9034 fputs ("+%l44(", file
);
9036 fputs ("+%lo(", file
);
9037 output_address (VOIDmode
, XEXP (addr
, 1));
9041 && GET_CODE (addr
) == CONST
9042 && GET_CODE (XEXP (addr
, 0)) == MINUS
9043 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9044 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9045 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9047 addr
= XEXP (addr
, 0);
9048 output_addr_const (file
, XEXP (addr
, 0));
9049 /* Group the args of the second CONST in parenthesis. */
9051 /* Skip past the second CONST--it does nothing for us. */
9052 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9053 /* Close the parenthesis. */
9058 output_addr_const (file
, addr
);
9062 /* Target hook for assembling integer objects. The sparc version has
9063 special handling for aligned DI-mode objects. */
9066 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9068 /* ??? We only output .xword's for symbols and only then in environments
9069 where the assembler can handle them. */
9070 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9074 assemble_integer_with_op ("\t.xword\t", x
);
9079 assemble_aligned_integer (4, const0_rtx
);
9080 assemble_aligned_integer (4, x
);
9084 return default_assemble_integer (x
, size
, aligned_p
);
9087 /* Return the value of a code used in the .proc pseudo-op that says
9088 what kind of result this function returns. For non-C types, we pick
9089 the closest C type. */
9091 #ifndef SHORT_TYPE_SIZE
9092 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9095 #ifndef INT_TYPE_SIZE
9096 #define INT_TYPE_SIZE BITS_PER_WORD
9099 #ifndef LONG_TYPE_SIZE
9100 #define LONG_TYPE_SIZE BITS_PER_WORD
9103 #ifndef LONG_LONG_TYPE_SIZE
9104 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9107 #ifndef FLOAT_TYPE_SIZE
9108 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9111 #ifndef DOUBLE_TYPE_SIZE
9112 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9115 #ifndef LONG_DOUBLE_TYPE_SIZE
9116 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9120 sparc_type_code (register tree type
)
9122 register unsigned long qualifiers
= 0;
9123 register unsigned shift
;
9125 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9126 setting more, since some assemblers will give an error for this. Also,
9127 we must be careful to avoid shifts of 32 bits or more to avoid getting
9128 unpredictable results. */
9130 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9132 switch (TREE_CODE (type
))
9138 qualifiers
|= (3 << shift
);
9143 qualifiers
|= (2 << shift
);
9147 case REFERENCE_TYPE
:
9149 qualifiers
|= (1 << shift
);
9153 return (qualifiers
| 8);
9156 case QUAL_UNION_TYPE
:
9157 return (qualifiers
| 9);
9160 return (qualifiers
| 10);
9163 return (qualifiers
| 16);
9166 /* If this is a range type, consider it to be the underlying
9168 if (TREE_TYPE (type
) != 0)
9171 /* Carefully distinguish all the standard types of C,
9172 without messing up if the language is not C. We do this by
9173 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9174 look at both the names and the above fields, but that's redundant.
9175 Any type whose size is between two C types will be considered
9176 to be the wider of the two types. Also, we do not have a
9177 special code to use for "long long", so anything wider than
9178 long is treated the same. Note that we can't distinguish
9179 between "int" and "long" in this code if they are the same
9180 size, but that's fine, since neither can the assembler. */
9182 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9183 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9185 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9186 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9188 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9189 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9192 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9195 /* If this is a range type, consider it to be the underlying
9197 if (TREE_TYPE (type
) != 0)
9200 /* Carefully distinguish all the standard types of C,
9201 without messing up if the language is not C. */
9203 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9204 return (qualifiers
| 6);
9207 return (qualifiers
| 7);
9209 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9210 /* ??? We need to distinguish between double and float complex types,
9211 but I don't know how yet because I can't reach this code from
9212 existing front-ends. */
9213 return (qualifiers
| 7); /* Who knows? */
9216 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9222 gcc_unreachable (); /* Not a type! */
9229 /* Nested function support. */
9231 /* Emit RTL insns to initialize the variable parts of a trampoline.
9232 FNADDR is an RTX for the address of the function's pure code.
9233 CXT is an RTX for the static chain value for the function.
9235 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9236 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9237 (to store insns). This is a bit excessive. Perhaps a different
9238 mechanism would be better here.
9240 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9243 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9245 /* SPARC 32-bit trampoline:
9248 sethi %hi(static), %g2
9250 or %g2, %lo(static), %g2
9252 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9253 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9257 (adjust_address (m_tramp
, SImode
, 0),
9258 expand_binop (SImode
, ior_optab
,
9259 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9260 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9261 NULL_RTX
, 1, OPTAB_DIRECT
));
9264 (adjust_address (m_tramp
, SImode
, 4),
9265 expand_binop (SImode
, ior_optab
,
9266 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9267 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9268 NULL_RTX
, 1, OPTAB_DIRECT
));
9271 (adjust_address (m_tramp
, SImode
, 8),
9272 expand_binop (SImode
, ior_optab
,
9273 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9274 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9275 NULL_RTX
, 1, OPTAB_DIRECT
));
9278 (adjust_address (m_tramp
, SImode
, 12),
9279 expand_binop (SImode
, ior_optab
,
9280 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9281 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9282 NULL_RTX
, 1, OPTAB_DIRECT
));
9284 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9285 aligned on a 16 byte boundary so one flush clears it all. */
9286 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9287 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9288 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9289 && sparc_cpu
!= PROCESSOR_NIAGARA
9290 && sparc_cpu
!= PROCESSOR_NIAGARA2
9291 && sparc_cpu
!= PROCESSOR_NIAGARA3
9292 && sparc_cpu
!= PROCESSOR_NIAGARA4
9293 && sparc_cpu
!= PROCESSOR_NIAGARA7
)
9294 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9296 /* Call __enable_execute_stack after writing onto the stack to make sure
9297 the stack address is accessible. */
9298 #ifdef HAVE_ENABLE_EXECUTE_STACK
9299 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9300 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9305 /* The 64-bit version is simpler because it makes more sense to load the
9306 values as "immediate" data out of the trampoline. It's also easier since
9307 we can read the PC without clobbering a register. */
9310 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9312 /* SPARC 64-bit trampoline:
9321 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9322 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9323 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9324 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9325 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9326 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9327 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9328 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9329 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9330 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9331 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9333 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9334 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9335 && sparc_cpu
!= PROCESSOR_NIAGARA
9336 && sparc_cpu
!= PROCESSOR_NIAGARA2
9337 && sparc_cpu
!= PROCESSOR_NIAGARA3
9338 && sparc_cpu
!= PROCESSOR_NIAGARA4
9339 && sparc_cpu
!= PROCESSOR_NIAGARA7
)
9340 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9342 /* Call __enable_execute_stack after writing onto the stack to make sure
9343 the stack address is accessible. */
9344 #ifdef HAVE_ENABLE_EXECUTE_STACK
9345 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9346 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9350 /* Worker for TARGET_TRAMPOLINE_INIT. */
9353 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9355 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9356 cxt
= force_reg (Pmode
, cxt
);
9358 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9360 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9363 /* Adjust the cost of a scheduling dependency. Return the new cost of
9364 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9367 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
9370 enum attr_type insn_type
;
9372 if (recog_memoized (insn
) < 0)
9375 insn_type
= get_attr_type (insn
);
9379 /* Data dependency; DEP_INSN writes a register that INSN reads some
9382 /* if a load, then the dependence must be on the memory address;
9383 add an extra "cycle". Note that the cost could be two cycles
9384 if the reg was written late in an instruction group; we ca not tell
9386 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9389 /* Get the delay only if the address of the store is the dependence. */
9390 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9392 rtx pat
= PATTERN(insn
);
9393 rtx dep_pat
= PATTERN (dep_insn
);
9395 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9396 return cost
; /* This should not happen! */
9398 /* The dependency between the two instructions was on the data that
9399 is being stored. Assume that this implies that the address of the
9400 store is not dependent. */
9401 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9404 return cost
+ 3; /* An approximation. */
9407 /* A shift instruction cannot receive its data from an instruction
9408 in the same cycle; add a one cycle penalty. */
9409 if (insn_type
== TYPE_SHIFT
)
9410 return cost
+ 3; /* Split before cascade into shift. */
9414 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9415 INSN writes some cycles later. */
9417 /* These are only significant for the fpu unit; writing a fp reg before
9418 the fpu has finished with it stalls the processor. */
9420 /* Reusing an integer register causes no problems. */
9421 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9429 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
9432 enum attr_type insn_type
, dep_type
;
9433 rtx pat
= PATTERN(insn
);
9434 rtx dep_pat
= PATTERN (dep_insn
);
9436 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9439 insn_type
= get_attr_type (insn
);
9440 dep_type
= get_attr_type (dep_insn
);
9445 /* Data dependency; DEP_INSN writes a register that INSN reads some
9452 /* Get the delay iff the address of the store is the dependence. */
9453 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9456 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9463 /* If a load, then the dependence must be on the memory address. If
9464 the addresses aren't equal, then it might be a false dependency */
9465 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9467 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9468 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9469 || GET_CODE (SET_SRC (pat
)) != MEM
9470 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9471 XEXP (SET_SRC (pat
), 0)))
9479 /* Compare to branch latency is 0. There is no benefit from
9480 separating compare and branch. */
9481 if (dep_type
== TYPE_COMPARE
)
9483 /* Floating point compare to branch latency is less than
9484 compare to conditional move. */
9485 if (dep_type
== TYPE_FPCMP
)
9494 /* Anti-dependencies only penalize the fpu unit. */
9495 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9507 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
9512 case PROCESSOR_SUPERSPARC
:
9513 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9515 case PROCESSOR_HYPERSPARC
:
9516 case PROCESSOR_SPARCLITE86X
:
9517 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9526 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9527 int sched_verbose ATTRIBUTE_UNUSED
,
9528 int max_ready ATTRIBUTE_UNUSED
)
9532 sparc_use_sched_lookahead (void)
9534 if (sparc_cpu
== PROCESSOR_NIAGARA
9535 || sparc_cpu
== PROCESSOR_NIAGARA2
9536 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9538 if (sparc_cpu
== PROCESSOR_NIAGARA4
9539 || sparc_cpu
== PROCESSOR_NIAGARA7
)
9541 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9542 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9544 if ((1 << sparc_cpu
) &
9545 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9546 (1 << PROCESSOR_SPARCLITE86X
)))
9552 sparc_issue_rate (void)
9556 case PROCESSOR_NIAGARA
:
9557 case PROCESSOR_NIAGARA2
:
9558 case PROCESSOR_NIAGARA3
:
9561 case PROCESSOR_NIAGARA4
:
9562 case PROCESSOR_NIAGARA7
:
9564 /* Assume V9 processors are capable of at least dual-issue. */
9566 case PROCESSOR_SUPERSPARC
:
9568 case PROCESSOR_HYPERSPARC
:
9569 case PROCESSOR_SPARCLITE86X
:
9571 case PROCESSOR_ULTRASPARC
:
9572 case PROCESSOR_ULTRASPARC3
:
9578 set_extends (rtx_insn
*insn
)
9580 register rtx pat
= PATTERN (insn
);
9582 switch (GET_CODE (SET_SRC (pat
)))
9584 /* Load and some shift instructions zero extend. */
9587 /* sethi clears the high bits */
9589 /* LO_SUM is used with sethi. sethi cleared the high
9590 bits and the values used with lo_sum are positive */
9592 /* Store flag stores 0 or 1 */
9602 rtx op0
= XEXP (SET_SRC (pat
), 0);
9603 rtx op1
= XEXP (SET_SRC (pat
), 1);
9604 if (GET_CODE (op1
) == CONST_INT
)
9605 return INTVAL (op1
) >= 0;
9606 if (GET_CODE (op0
) != REG
)
9608 if (sparc_check_64 (op0
, insn
) == 1)
9610 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9615 rtx op0
= XEXP (SET_SRC (pat
), 0);
9616 rtx op1
= XEXP (SET_SRC (pat
), 1);
9617 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9619 if (GET_CODE (op1
) == CONST_INT
)
9620 return INTVAL (op1
) >= 0;
9621 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9624 return GET_MODE (SET_SRC (pat
)) == SImode
;
9625 /* Positive integers leave the high bits zero. */
9627 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
9630 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9632 return sparc_check_64 (SET_SRC (pat
), insn
);
9638 /* We _ought_ to have only one kind per function, but... */
9639 static GTY(()) rtx sparc_addr_diff_list
;
9640 static GTY(()) rtx sparc_addr_list
;
9643 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9645 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9647 sparc_addr_diff_list
9648 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9650 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9654 sparc_output_addr_vec (rtx vec
)
9656 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9657 int idx
, vlen
= XVECLEN (body
, 0);
9659 #ifdef ASM_OUTPUT_ADDR_VEC_START
9660 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9663 #ifdef ASM_OUTPUT_CASE_LABEL
9664 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9667 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9670 for (idx
= 0; idx
< vlen
; idx
++)
9672 ASM_OUTPUT_ADDR_VEC_ELT
9673 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9676 #ifdef ASM_OUTPUT_ADDR_VEC_END
9677 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9682 sparc_output_addr_diff_vec (rtx vec
)
9684 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9685 rtx base
= XEXP (XEXP (body
, 0), 0);
9686 int idx
, vlen
= XVECLEN (body
, 1);
9688 #ifdef ASM_OUTPUT_ADDR_VEC_START
9689 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9692 #ifdef ASM_OUTPUT_CASE_LABEL
9693 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9696 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9699 for (idx
= 0; idx
< vlen
; idx
++)
9701 ASM_OUTPUT_ADDR_DIFF_ELT
9704 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9705 CODE_LABEL_NUMBER (base
));
9708 #ifdef ASM_OUTPUT_ADDR_VEC_END
9709 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9714 sparc_output_deferred_case_vectors (void)
9719 if (sparc_addr_list
== NULL_RTX
9720 && sparc_addr_diff_list
== NULL_RTX
)
9723 /* Align to cache line in the function's code section. */
9724 switch_to_section (current_function_section ());
9726 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9728 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9730 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9731 sparc_output_addr_vec (XEXP (t
, 0));
9732 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9733 sparc_output_addr_diff_vec (XEXP (t
, 0));
9735 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9738 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9739 unknown. Return 1 if the high bits are zero, -1 if the register is
9742 sparc_check_64 (rtx x
, rtx_insn
*insn
)
9744 /* If a register is set only once it is safe to ignore insns this
9745 code does not know how to handle. The loop will either recognize
9746 the single set and return the correct value or fail to recognize
9751 gcc_assert (GET_CODE (x
) == REG
);
9753 if (GET_MODE (x
) == DImode
)
9754 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9756 if (flag_expensive_optimizations
9757 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9763 insn
= get_last_insn_anywhere ();
9768 while ((insn
= PREV_INSN (insn
)))
9770 switch (GET_CODE (insn
))
9783 rtx pat
= PATTERN (insn
);
9784 if (GET_CODE (pat
) != SET
)
9786 if (rtx_equal_p (x
, SET_DEST (pat
)))
9787 return set_extends (insn
);
9788 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9789 return set_extends (insn
);
9790 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9798 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9799 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9802 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
9804 static char asm_code
[60];
9806 /* The scratch register is only required when the destination
9807 register is not a 64-bit global or out register. */
9808 if (which_alternative
!= 2)
9809 operands
[3] = operands
[0];
9811 /* We can only shift by constants <= 63. */
9812 if (GET_CODE (operands
[2]) == CONST_INT
)
9813 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9815 if (GET_CODE (operands
[1]) == CONST_INT
)
9817 output_asm_insn ("mov\t%1, %3", operands
);
9821 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9822 if (sparc_check_64 (operands
[1], insn
) <= 0)
9823 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9824 output_asm_insn ("or\t%L1, %3, %3", operands
);
9827 strcpy (asm_code
, opcode
);
9829 if (which_alternative
!= 2)
9830 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9833 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9836 /* Output rtl to increment the profiler label LABELNO
9837 for profiling a function entry. */
9840 sparc_profile_hook (int labelno
)
9845 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9846 if (NO_PROFILE_COUNTERS
)
9848 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9852 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9853 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9854 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9858 #ifdef TARGET_SOLARIS
9859 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9862 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9863 tree decl ATTRIBUTE_UNUSED
)
9865 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9867 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9871 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9873 if (!(flags
& SECTION_DEBUG
))
9874 fputs (",#alloc", asm_out_file
);
9875 if (flags
& SECTION_WRITE
)
9876 fputs (",#write", asm_out_file
);
9877 if (flags
& SECTION_TLS
)
9878 fputs (",#tls", asm_out_file
);
9879 if (flags
& SECTION_CODE
)
9880 fputs (",#execinstr", asm_out_file
);
9882 if (flags
& SECTION_NOTYPE
)
9884 else if (flags
& SECTION_BSS
)
9885 fputs (",#nobits", asm_out_file
);
9887 fputs (",#progbits", asm_out_file
);
9889 fputc ('\n', asm_out_file
);
9891 #endif /* TARGET_SOLARIS */
9893 /* We do not allow indirect calls to be optimized into sibling calls.
9895 We cannot use sibling calls when delayed branches are disabled
9896 because they will likely require the call delay slot to be filled.
9898 Also, on SPARC 32-bit we cannot emit a sibling call when the
9899 current function returns a structure. This is because the "unimp
9900 after call" convention would cause the callee to return to the
9901 wrong place. The generic code already disallows cases where the
9902 function being called returns a structure.
9904 It may seem strange how this last case could occur. Usually there
9905 is code after the call which jumps to epilogue code which dumps the
9906 return value into the struct return area. That ought to invalidate
9907 the sibling call right? Well, in the C++ case we can end up passing
9908 the pointer to the struct return area to a constructor (which returns
9909 void) and then nothing else happens. Such a sibling call would look
9910 valid without the added check here.
9912 VxWorks PIC PLT entries require the global pointer to be initialized
9913 on entry. We therefore can't emit sibling calls to them. */
9915 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9918 && flag_delayed_branch
9919 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9920 && !(TARGET_VXWORKS_RTP
9922 && !targetm
.binds_local_p (decl
)));
9925 /* libfunc renaming. */
9928 sparc_init_libfuncs (void)
9932 /* Use the subroutines that Sun's library provides for integer
9933 multiply and divide. The `*' prevents an underscore from
9934 being prepended by the compiler. .umul is a little faster
9936 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9937 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9938 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9939 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9940 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9942 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9943 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9944 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9945 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9946 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9947 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9949 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9950 is because with soft-float, the SFmode and DFmode sqrt
9951 instructions will be absent, and the compiler will notice and
9952 try to use the TFmode sqrt instruction for calls to the
9953 builtin function sqrt, but this fails. */
9955 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9957 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9958 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9959 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9960 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9961 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9962 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9964 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9965 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9966 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9967 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9969 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9970 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9971 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9972 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9974 if (DITF_CONVERSION_LIBFUNCS
)
9976 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9977 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9978 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9979 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9982 if (SUN_CONVERSION_LIBFUNCS
)
9984 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9985 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9986 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9987 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9992 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9993 do not exist in the library. Make sure the compiler does not
9994 emit calls to them by accident. (It should always use the
9995 hardware instructions.) */
9996 set_optab_libfunc (smul_optab
, SImode
, 0);
9997 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9998 set_optab_libfunc (udiv_optab
, SImode
, 0);
9999 set_optab_libfunc (smod_optab
, SImode
, 0);
10000 set_optab_libfunc (umod_optab
, SImode
, 0);
10002 if (SUN_INTEGER_MULTIPLY_64
)
10004 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10005 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10006 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10007 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10008 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10011 if (SUN_CONVERSION_LIBFUNCS
)
10013 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10014 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10015 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10016 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10021 /* SPARC builtins. */
10022 enum sparc_builtins
10024 /* FPU builtins. */
10025 SPARC_BUILTIN_LDFSR
,
10026 SPARC_BUILTIN_STFSR
,
10028 /* VIS 1.0 builtins. */
10029 SPARC_BUILTIN_FPACK16
,
10030 SPARC_BUILTIN_FPACK32
,
10031 SPARC_BUILTIN_FPACKFIX
,
10032 SPARC_BUILTIN_FEXPAND
,
10033 SPARC_BUILTIN_FPMERGE
,
10034 SPARC_BUILTIN_FMUL8X16
,
10035 SPARC_BUILTIN_FMUL8X16AU
,
10036 SPARC_BUILTIN_FMUL8X16AL
,
10037 SPARC_BUILTIN_FMUL8SUX16
,
10038 SPARC_BUILTIN_FMUL8ULX16
,
10039 SPARC_BUILTIN_FMULD8SUX16
,
10040 SPARC_BUILTIN_FMULD8ULX16
,
10041 SPARC_BUILTIN_FALIGNDATAV4HI
,
10042 SPARC_BUILTIN_FALIGNDATAV8QI
,
10043 SPARC_BUILTIN_FALIGNDATAV2SI
,
10044 SPARC_BUILTIN_FALIGNDATADI
,
10045 SPARC_BUILTIN_WRGSR
,
10046 SPARC_BUILTIN_RDGSR
,
10047 SPARC_BUILTIN_ALIGNADDR
,
10048 SPARC_BUILTIN_ALIGNADDRL
,
10049 SPARC_BUILTIN_PDIST
,
10050 SPARC_BUILTIN_EDGE8
,
10051 SPARC_BUILTIN_EDGE8L
,
10052 SPARC_BUILTIN_EDGE16
,
10053 SPARC_BUILTIN_EDGE16L
,
10054 SPARC_BUILTIN_EDGE32
,
10055 SPARC_BUILTIN_EDGE32L
,
10056 SPARC_BUILTIN_FCMPLE16
,
10057 SPARC_BUILTIN_FCMPLE32
,
10058 SPARC_BUILTIN_FCMPNE16
,
10059 SPARC_BUILTIN_FCMPNE32
,
10060 SPARC_BUILTIN_FCMPGT16
,
10061 SPARC_BUILTIN_FCMPGT32
,
10062 SPARC_BUILTIN_FCMPEQ16
,
10063 SPARC_BUILTIN_FCMPEQ32
,
10064 SPARC_BUILTIN_FPADD16
,
10065 SPARC_BUILTIN_FPADD16S
,
10066 SPARC_BUILTIN_FPADD32
,
10067 SPARC_BUILTIN_FPADD32S
,
10068 SPARC_BUILTIN_FPSUB16
,
10069 SPARC_BUILTIN_FPSUB16S
,
10070 SPARC_BUILTIN_FPSUB32
,
10071 SPARC_BUILTIN_FPSUB32S
,
10072 SPARC_BUILTIN_ARRAY8
,
10073 SPARC_BUILTIN_ARRAY16
,
10074 SPARC_BUILTIN_ARRAY32
,
10076 /* VIS 2.0 builtins. */
10077 SPARC_BUILTIN_EDGE8N
,
10078 SPARC_BUILTIN_EDGE8LN
,
10079 SPARC_BUILTIN_EDGE16N
,
10080 SPARC_BUILTIN_EDGE16LN
,
10081 SPARC_BUILTIN_EDGE32N
,
10082 SPARC_BUILTIN_EDGE32LN
,
10083 SPARC_BUILTIN_BMASK
,
10084 SPARC_BUILTIN_BSHUFFLEV4HI
,
10085 SPARC_BUILTIN_BSHUFFLEV8QI
,
10086 SPARC_BUILTIN_BSHUFFLEV2SI
,
10087 SPARC_BUILTIN_BSHUFFLEDI
,
10089 /* VIS 3.0 builtins. */
10090 SPARC_BUILTIN_CMASK8
,
10091 SPARC_BUILTIN_CMASK16
,
10092 SPARC_BUILTIN_CMASK32
,
10093 SPARC_BUILTIN_FCHKSM16
,
10094 SPARC_BUILTIN_FSLL16
,
10095 SPARC_BUILTIN_FSLAS16
,
10096 SPARC_BUILTIN_FSRL16
,
10097 SPARC_BUILTIN_FSRA16
,
10098 SPARC_BUILTIN_FSLL32
,
10099 SPARC_BUILTIN_FSLAS32
,
10100 SPARC_BUILTIN_FSRL32
,
10101 SPARC_BUILTIN_FSRA32
,
10102 SPARC_BUILTIN_PDISTN
,
10103 SPARC_BUILTIN_FMEAN16
,
10104 SPARC_BUILTIN_FPADD64
,
10105 SPARC_BUILTIN_FPSUB64
,
10106 SPARC_BUILTIN_FPADDS16
,
10107 SPARC_BUILTIN_FPADDS16S
,
10108 SPARC_BUILTIN_FPSUBS16
,
10109 SPARC_BUILTIN_FPSUBS16S
,
10110 SPARC_BUILTIN_FPADDS32
,
10111 SPARC_BUILTIN_FPADDS32S
,
10112 SPARC_BUILTIN_FPSUBS32
,
10113 SPARC_BUILTIN_FPSUBS32S
,
10114 SPARC_BUILTIN_FUCMPLE8
,
10115 SPARC_BUILTIN_FUCMPNE8
,
10116 SPARC_BUILTIN_FUCMPGT8
,
10117 SPARC_BUILTIN_FUCMPEQ8
,
10118 SPARC_BUILTIN_FHADDS
,
10119 SPARC_BUILTIN_FHADDD
,
10120 SPARC_BUILTIN_FHSUBS
,
10121 SPARC_BUILTIN_FHSUBD
,
10122 SPARC_BUILTIN_FNHADDS
,
10123 SPARC_BUILTIN_FNHADDD
,
10124 SPARC_BUILTIN_UMULXHI
,
10125 SPARC_BUILTIN_XMULX
,
10126 SPARC_BUILTIN_XMULXHI
,
10128 /* VIS 4.0 builtins. */
10129 SPARC_BUILTIN_FPADD8
,
10130 SPARC_BUILTIN_FPADDS8
,
10131 SPARC_BUILTIN_FPADDUS8
,
10132 SPARC_BUILTIN_FPADDUS16
,
10133 SPARC_BUILTIN_FPCMPLE8
,
10134 SPARC_BUILTIN_FPCMPGT8
,
10135 SPARC_BUILTIN_FPCMPULE16
,
10136 SPARC_BUILTIN_FPCMPUGT16
,
10137 SPARC_BUILTIN_FPCMPULE32
,
10138 SPARC_BUILTIN_FPCMPUGT32
,
10139 SPARC_BUILTIN_FPMAX8
,
10140 SPARC_BUILTIN_FPMAX16
,
10141 SPARC_BUILTIN_FPMAX32
,
10142 SPARC_BUILTIN_FPMAXU8
,
10143 SPARC_BUILTIN_FPMAXU16
,
10144 SPARC_BUILTIN_FPMAXU32
,
10145 SPARC_BUILTIN_FPMIN8
,
10146 SPARC_BUILTIN_FPMIN16
,
10147 SPARC_BUILTIN_FPMIN32
,
10148 SPARC_BUILTIN_FPMINU8
,
10149 SPARC_BUILTIN_FPMINU16
,
10150 SPARC_BUILTIN_FPMINU32
,
10151 SPARC_BUILTIN_FPSUB8
,
10152 SPARC_BUILTIN_FPSUBS8
,
10153 SPARC_BUILTIN_FPSUBUS8
,
10154 SPARC_BUILTIN_FPSUBUS16
,
10159 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10160 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10162 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10163 function decl or NULL_TREE if the builtin was not added. */
10166 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10170 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10174 sparc_builtins
[code
] = t
;
10175 sparc_builtins_icode
[code
] = icode
;
10181 /* Likewise, but also marks the function as "const". */
10184 def_builtin_const (const char *name
, enum insn_code icode
,
10185 enum sparc_builtins code
, tree type
)
10187 tree t
= def_builtin (name
, icode
, code
, type
);
10190 TREE_READONLY (t
) = 1;
10195 /* Implement the TARGET_INIT_BUILTINS target hook.
10196 Create builtin functions for special SPARC instructions. */
10199 sparc_init_builtins (void)
10202 sparc_fpu_init_builtins ();
10205 sparc_vis_init_builtins ();
10208 /* Create builtin functions for FPU instructions. */
10211 sparc_fpu_init_builtins (void)
10214 = build_function_type_list (void_type_node
,
10215 build_pointer_type (unsigned_type_node
), 0);
10216 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10217 SPARC_BUILTIN_LDFSR
, ftype
);
10218 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10219 SPARC_BUILTIN_STFSR
, ftype
);
10222 /* Create builtin functions for VIS instructions. */
10225 sparc_vis_init_builtins (void)
10227 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10228 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10229 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10230 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10231 tree v2si
= build_vector_type (intSI_type_node
, 2);
10232 tree v1si
= build_vector_type (intSI_type_node
, 1);
10234 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10235 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10236 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10237 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10238 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10239 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10240 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10241 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10242 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10243 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10244 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10245 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10246 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10247 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10248 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10250 intDI_type_node
, 0);
10251 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10253 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10255 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10257 intDI_type_node
, 0);
10258 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10260 intSI_type_node
, 0);
10261 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10263 intSI_type_node
, 0);
10264 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10266 intDI_type_node
, 0);
10267 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10270 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10273 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10275 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10277 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10279 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10281 tree void_ftype_di
= build_function_type_list (void_type_node
,
10282 intDI_type_node
, 0);
10283 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10284 void_type_node
, 0);
10285 tree void_ftype_si
= build_function_type_list (void_type_node
,
10286 intSI_type_node
, 0);
10287 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10289 float_type_node
, 0);
10290 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10292 double_type_node
, 0);
10294 /* Packing and expanding vectors. */
10295 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10296 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10297 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10298 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10299 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10300 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10301 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10302 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10303 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10304 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10306 /* Multiplications. */
10307 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10308 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10309 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10310 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10311 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10312 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10313 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10314 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10315 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10316 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10317 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10318 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10319 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10320 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10322 /* Data aligning. */
10323 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10324 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10325 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10326 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10327 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10328 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10329 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10330 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10332 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10333 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10334 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10335 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10339 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10340 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10341 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10342 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10346 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10347 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10348 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10349 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10352 /* Pixel distance. */
10353 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10354 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10356 /* Edge handling. */
10359 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10360 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10361 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10362 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10363 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10364 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10365 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10366 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10367 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10368 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10369 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10370 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10374 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10375 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10376 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10377 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10378 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10379 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10380 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10381 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10382 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10383 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10384 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10385 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10388 /* Pixel compare. */
10391 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10392 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10393 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10394 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10395 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10396 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10397 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10398 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10399 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10400 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10401 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10402 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10403 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10404 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10405 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10406 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10410 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10411 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10412 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10413 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10414 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10415 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10416 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10417 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10418 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10419 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10420 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10421 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10422 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10423 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10424 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10425 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10428 /* Addition and subtraction. */
10429 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10430 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10431 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10432 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10433 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10434 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10435 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10436 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10437 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10438 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10439 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10440 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10441 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10442 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10443 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10444 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10446 /* Three-dimensional array addressing. */
10449 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10450 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10451 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10452 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10453 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10454 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10458 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10459 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10460 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10461 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10462 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10463 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10468 /* Edge handling. */
10471 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10472 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10473 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10474 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10475 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10476 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10477 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10478 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10479 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10480 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10481 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10482 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10486 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10487 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10488 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10489 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10490 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10491 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10492 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10493 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10494 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10495 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10496 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10497 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10500 /* Byte mask and shuffle. */
10502 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10503 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10505 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10506 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10507 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10508 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10509 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10510 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10511 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10512 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10513 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10514 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10521 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10522 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10523 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10524 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10525 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10526 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10530 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10531 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10532 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10533 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10534 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10535 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10538 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10539 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10541 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10542 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10543 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10544 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10545 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10546 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10547 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10548 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10549 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10550 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10551 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10552 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10553 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10554 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10555 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10556 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10559 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10560 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10562 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10563 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10565 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10566 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10567 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10568 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10569 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10570 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10572 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10573 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10574 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10575 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10576 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10577 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10578 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10579 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10580 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10581 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10582 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10583 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10584 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10585 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10586 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10587 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10591 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10592 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10593 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10594 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10595 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10596 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10597 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10598 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10602 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10603 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10604 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10605 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
10606 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10607 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
10608 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10609 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
10612 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10613 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
10614 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10615 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
10616 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10617 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
10618 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10619 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
10620 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10621 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
10622 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10623 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
10625 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10626 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
10627 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10628 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
10629 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10630 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
10635 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
10636 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
10637 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
10638 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
10639 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
10640 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
10641 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
10642 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
10647 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
10648 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
10649 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
10650 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
10651 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
10652 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
10653 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
10654 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
10655 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
10656 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
10657 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
10658 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
10662 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
10663 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
10664 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
10665 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
10666 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
10667 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
10668 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
10669 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
10670 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
10671 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
10672 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
10673 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
10676 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
10677 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
10678 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
10679 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
10680 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
10681 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
10682 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
10683 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
10684 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
10685 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
10686 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
10687 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
10688 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
10689 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
10690 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
10691 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
10692 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
10693 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
10694 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
10695 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
10696 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
10697 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
10698 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
10699 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
10700 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
10701 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
10702 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
10703 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
10704 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
10705 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
10706 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
10707 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
10711 /* Implement TARGET_BUILTIN_DECL hook. */
10714 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10716 if (code
>= SPARC_BUILTIN_MAX
)
10717 return error_mark_node
;
10719 return sparc_builtins
[code
];
10722 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10725 sparc_expand_builtin (tree exp
, rtx target
,
10726 rtx subtarget ATTRIBUTE_UNUSED
,
10727 machine_mode tmode ATTRIBUTE_UNUSED
,
10728 int ignore ATTRIBUTE_UNUSED
)
10730 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10731 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10732 enum insn_code icode
= sparc_builtins_icode
[code
];
10733 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10734 call_expr_arg_iterator iter
;
10741 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10743 || GET_MODE (target
) != tmode
10744 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10745 op
[0] = gen_reg_rtx (tmode
);
10750 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10752 const struct insn_operand_data
*insn_op
;
10755 if (arg
== error_mark_node
)
10759 idx
= arg_count
- !nonvoid
;
10760 insn_op
= &insn_data
[icode
].operand
[idx
];
10761 op
[arg_count
] = expand_normal (arg
);
10763 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
10765 if (!address_operand (op
[arg_count
], SImode
))
10767 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
10768 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
10770 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
10773 else if (insn_op
->mode
== V1DImode
10774 && GET_MODE (op
[arg_count
]) == DImode
)
10775 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10777 else if (insn_op
->mode
== V1SImode
10778 && GET_MODE (op
[arg_count
]) == SImode
)
10779 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10781 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10783 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10789 pat
= GEN_FCN (icode
) (op
[0]);
10793 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10795 pat
= GEN_FCN (icode
) (op
[1]);
10798 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10801 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10804 gcc_unreachable ();
10812 return (nonvoid
? op
[0] : const0_rtx
);
10815 /* Return the upper 16 bits of the 8x16 multiplication. */
10818 sparc_vis_mul8x16 (int e8
, int e16
)
10820 return (e8
* e16
+ 128) / 256;
10823 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10824 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10827 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
10828 tree inner_type
, tree cst0
, tree cst1
)
10830 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10835 case SPARC_BUILTIN_FMUL8X16
:
10836 for (i
= 0; i
< num
; ++i
)
10839 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10840 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10841 n_elts
[i
] = build_int_cst (inner_type
, val
);
10845 case SPARC_BUILTIN_FMUL8X16AU
:
10846 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10848 for (i
= 0; i
< num
; ++i
)
10851 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10853 n_elts
[i
] = build_int_cst (inner_type
, val
);
10857 case SPARC_BUILTIN_FMUL8X16AL
:
10858 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10860 for (i
= 0; i
< num
; ++i
)
10863 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10865 n_elts
[i
] = build_int_cst (inner_type
, val
);
10870 gcc_unreachable ();
10874 /* Implement TARGET_FOLD_BUILTIN hook.
10876 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10877 result of the function call is ignored. NULL_TREE is returned if the
10878 function could not be folded. */
10881 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10882 tree
*args
, bool ignore
)
10884 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10885 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10886 tree arg0
, arg1
, arg2
;
10891 case SPARC_BUILTIN_LDFSR
:
10892 case SPARC_BUILTIN_STFSR
:
10893 case SPARC_BUILTIN_ALIGNADDR
:
10894 case SPARC_BUILTIN_WRGSR
:
10895 case SPARC_BUILTIN_BMASK
:
10896 case SPARC_BUILTIN_CMASK8
:
10897 case SPARC_BUILTIN_CMASK16
:
10898 case SPARC_BUILTIN_CMASK32
:
10902 return build_zero_cst (rtype
);
10907 case SPARC_BUILTIN_FEXPAND
:
10911 if (TREE_CODE (arg0
) == VECTOR_CST
)
10913 tree inner_type
= TREE_TYPE (rtype
);
10917 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10918 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10919 n_elts
[i
] = build_int_cst (inner_type
,
10921 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10922 return build_vector (rtype
, n_elts
);
10926 case SPARC_BUILTIN_FMUL8X16
:
10927 case SPARC_BUILTIN_FMUL8X16AU
:
10928 case SPARC_BUILTIN_FMUL8X16AL
:
10934 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10936 tree inner_type
= TREE_TYPE (rtype
);
10937 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10938 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
10939 return build_vector (rtype
, n_elts
);
10943 case SPARC_BUILTIN_FPMERGE
:
10949 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10951 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10953 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10955 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10956 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10959 return build_vector (rtype
, n_elts
);
10963 case SPARC_BUILTIN_PDIST
:
10964 case SPARC_BUILTIN_PDISTN
:
10969 if (code
== SPARC_BUILTIN_PDIST
)
10975 arg2
= integer_zero_node
;
10977 if (TREE_CODE (arg0
) == VECTOR_CST
10978 && TREE_CODE (arg1
) == VECTOR_CST
10979 && TREE_CODE (arg2
) == INTEGER_CST
)
10981 bool overflow
= false;
10982 widest_int result
= wi::to_widest (arg2
);
10986 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10988 tree e0
= VECTOR_CST_ELT (arg0
, i
);
10989 tree e1
= VECTOR_CST_ELT (arg1
, i
);
10991 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10993 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
10994 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
10995 if (wi::neg_p (tmp
))
10996 tmp
= wi::neg (tmp
, &neg2_ovf
);
10999 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11000 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
11003 gcc_assert (!overflow
);
11005 return wide_int_to_tree (rtype
, result
);
11015 /* ??? This duplicates information provided to the compiler by the
11016 ??? scheduler description. Some day, teach genautomata to output
11017 ??? the latencies and then CSE will just use that. */
11020 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11021 int opno ATTRIBUTE_UNUSED
,
11022 int *total
, bool speed ATTRIBUTE_UNUSED
)
11024 int code
= GET_CODE (x
);
11025 bool float_mode_p
= FLOAT_MODE_P (mode
);
11036 case CONST_WIDE_INT
:
11038 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11040 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11059 /* If outer-code was a sign or zero extension, a cost
11060 of COSTS_N_INSNS (1) was already added in. This is
11061 why we are subtracting it back out. */
11062 if (outer_code
== ZERO_EXTEND
)
11064 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11066 else if (outer_code
== SIGN_EXTEND
)
11068 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11070 else if (float_mode_p
)
11072 *total
= sparc_costs
->float_load
;
11076 *total
= sparc_costs
->int_load
;
11084 *total
= sparc_costs
->float_plusminus
;
11086 *total
= COSTS_N_INSNS (1);
11093 gcc_assert (float_mode_p
);
11094 *total
= sparc_costs
->float_mul
;
11097 if (GET_CODE (sub
) == NEG
)
11098 sub
= XEXP (sub
, 0);
11099 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
11102 if (GET_CODE (sub
) == NEG
)
11103 sub
= XEXP (sub
, 0);
11104 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
11110 *total
= sparc_costs
->float_mul
;
11111 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11112 *total
= COSTS_N_INSNS (25);
11118 if (sparc_costs
->int_mul_bit_factor
)
11122 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11124 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11125 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11133 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11134 bit_cost
= COSTS_N_INSNS (bit_cost
);
11137 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11138 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11140 *total
= sparc_costs
->int_mul
+ bit_cost
;
11147 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11156 if (mode
== DFmode
)
11157 *total
= sparc_costs
->float_div_df
;
11159 *total
= sparc_costs
->float_div_sf
;
11163 if (mode
== DImode
)
11164 *total
= sparc_costs
->int_divX
;
11166 *total
= sparc_costs
->int_div
;
11171 if (! float_mode_p
)
11173 *total
= COSTS_N_INSNS (1);
11180 case UNSIGNED_FLOAT
:
11184 case FLOAT_TRUNCATE
:
11185 *total
= sparc_costs
->float_move
;
11189 if (mode
== DFmode
)
11190 *total
= sparc_costs
->float_sqrt_df
;
11192 *total
= sparc_costs
->float_sqrt_sf
;
11197 *total
= sparc_costs
->float_cmp
;
11199 *total
= COSTS_N_INSNS (1);
11204 *total
= sparc_costs
->float_cmove
;
11206 *total
= sparc_costs
->int_cmove
;
11210 /* Handle the NAND vector patterns. */
11211 if (sparc_vector_mode_supported_p (mode
)
11212 && GET_CODE (XEXP (x
, 0)) == NOT
11213 && GET_CODE (XEXP (x
, 1)) == NOT
)
11215 *total
= COSTS_N_INSNS (1);
11226 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11229 general_or_i64_p (reg_class_t rclass
)
11231 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11234 /* Implement TARGET_REGISTER_MOVE_COST. */
11237 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
11238 reg_class_t from
, reg_class_t to
)
11240 bool need_memory
= false;
11242 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11243 need_memory
= true;
11244 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11245 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11249 int size
= GET_MODE_SIZE (mode
);
11250 if (size
== 8 || size
== 4)
11252 if (! TARGET_ARCH32
|| size
== 4)
11258 need_memory
= true;
11263 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11264 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11265 || sparc_cpu
== PROCESSOR_NIAGARA
11266 || sparc_cpu
== PROCESSOR_NIAGARA2
11267 || sparc_cpu
== PROCESSOR_NIAGARA3
11268 || sparc_cpu
== PROCESSOR_NIAGARA4
11269 || sparc_cpu
== PROCESSOR_NIAGARA7
)
11278 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11279 This is achieved by means of a manual dynamic stack space allocation in
11280 the current frame. We make the assumption that SEQ doesn't contain any
11281 function calls, with the possible exception of calls to the GOT helper. */
11284 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11286 /* We must preserve the lowest 16 words for the register save area. */
11287 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11288 /* We really need only 2 words of fresh stack space. */
11289 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11292 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11293 SPARC_STACK_BIAS
+ offset
));
11295 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11296 emit_insn (gen_rtx_SET (slot
, reg
));
11298 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11302 emit_insn (gen_rtx_SET (reg2
,
11303 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11304 emit_insn (gen_rtx_SET (reg
, slot
));
11305 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11308 /* Output the assembler code for a thunk function. THUNK_DECL is the
11309 declaration for the thunk function itself, FUNCTION is the decl for
11310 the target function. DELTA is an immediate constant offset to be
11311 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11312 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11315 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11316 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11319 rtx this_rtx
, funexp
;
11321 unsigned int int_arg_first
;
11323 reload_completed
= 1;
11324 epilogue_completed
= 1;
11326 emit_note (NOTE_INSN_PROLOGUE_END
);
11330 sparc_leaf_function_p
= 1;
11332 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11334 else if (flag_delayed_branch
)
11336 /* We will emit a regular sibcall below, so we need to instruct
11337 output_sibcall that we are in a leaf function. */
11338 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11340 /* This will cause final.c to invoke leaf_renumber_regs so we
11341 must behave as if we were in a not-yet-leafified function. */
11342 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11346 /* We will emit the sibcall manually below, so we will need to
11347 manually spill non-leaf registers. */
11348 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11350 /* We really are in a leaf function. */
11351 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11354 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11355 returns a structure, the structure return pointer is there instead. */
11357 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11358 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11360 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11362 /* Add DELTA. When possible use a plain add, otherwise load it into
11363 a register first. */
11366 rtx delta_rtx
= GEN_INT (delta
);
11368 if (! SPARC_SIMM13_P (delta
))
11370 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11371 emit_move_insn (scratch
, delta_rtx
);
11372 delta_rtx
= scratch
;
11375 /* THIS_RTX += DELTA. */
11376 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11379 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11382 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11383 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11385 gcc_assert (vcall_offset
< 0);
11387 /* SCRATCH = *THIS_RTX. */
11388 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11390 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11391 may not have any available scratch register at this point. */
11392 if (SPARC_SIMM13_P (vcall_offset
))
11394 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11395 else if (! fixed_regs
[5]
11396 /* The below sequence is made up of at least 2 insns,
11397 while the default method may need only one. */
11398 && vcall_offset
< -8192)
11400 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11401 emit_move_insn (scratch2
, vcall_offset_rtx
);
11402 vcall_offset_rtx
= scratch2
;
11406 rtx increment
= GEN_INT (-4096);
11408 /* VCALL_OFFSET is a negative number whose typical range can be
11409 estimated as -32768..0 in 32-bit mode. In almost all cases
11410 it is therefore cheaper to emit multiple add insns than
11411 spilling and loading the constant into a register (at least
11413 while (! SPARC_SIMM13_P (vcall_offset
))
11415 emit_insn (gen_add2_insn (scratch
, increment
));
11416 vcall_offset
+= 4096;
11418 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11421 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11422 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11423 gen_rtx_PLUS (Pmode
,
11425 vcall_offset_rtx
)));
11427 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11428 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11431 /* Generate a tail call to the target function. */
11432 if (! TREE_USED (function
))
11434 assemble_external (function
);
11435 TREE_USED (function
) = 1;
11437 funexp
= XEXP (DECL_RTL (function
), 0);
11439 if (flag_delayed_branch
)
11441 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
11442 insn
= emit_call_insn (gen_sibcall (funexp
));
11443 SIBLING_CALL_P (insn
) = 1;
11447 /* The hoops we have to jump through in order to generate a sibcall
11448 without using delay slots... */
11449 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
11453 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
11455 load_got_register (); /* clobbers %o7 */
11456 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
11457 seq
= get_insns ();
11459 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
11461 else if (TARGET_ARCH32
)
11463 emit_insn (gen_rtx_SET (scratch
,
11464 gen_rtx_HIGH (SImode
, funexp
)));
11465 emit_insn (gen_rtx_SET (scratch
,
11466 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
11468 else /* TARGET_ARCH64 */
11470 switch (sparc_cmodel
)
11474 /* The destination can serve as a temporary. */
11475 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
11480 /* The destination cannot serve as a temporary. */
11481 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
11483 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
11484 seq
= get_insns ();
11486 emit_and_preserve (seq
, spill_reg
, 0);
11490 gcc_unreachable ();
11494 emit_jump_insn (gen_indirect_jump (scratch
));
11499 /* Run just enough of rest_of_compilation to get the insns emitted.
11500 There's not really enough bulk here to make other passes such as
11501 instruction scheduling worth while. Note that use_thunk calls
11502 assemble_start_function and assemble_end_function. */
11503 insn
= get_insns ();
11504 shorten_branches (insn
);
11505 final_start_function (insn
, file
, 1);
11506 final (insn
, file
, 1);
11507 final_end_function ();
11509 reload_completed
= 0;
11510 epilogue_completed
= 0;
11513 /* Return true if sparc_output_mi_thunk would be able to output the
11514 assembler code for the thunk function specified by the arguments
11515 it is passed, and false otherwise. */
11517 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
11518 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
11519 HOST_WIDE_INT vcall_offset
,
11520 const_tree function ATTRIBUTE_UNUSED
)
11522 /* Bound the loop used in the default method above. */
11523 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
11526 /* How to allocate a 'struct machine_function'. */
11528 static struct machine_function
*
11529 sparc_init_machine_status (void)
11531 return ggc_cleared_alloc
<machine_function
> ();
11534 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11535 We need to emit DTP-relative relocations. */
11538 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11543 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11546 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11549 gcc_unreachable ();
11551 output_addr_const (file
, x
);
11555 /* Do whatever processing is required at the end of a file. */
11558 sparc_file_end (void)
11560 /* If we need to emit the special GOT helper function, do so now. */
11561 if (got_helper_rtx
)
11563 const char *name
= XSTR (got_helper_rtx
, 0);
11564 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11565 #ifdef DWARF2_UNWIND_INFO
11569 if (USE_HIDDEN_LINKONCE
)
11571 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11572 get_identifier (name
),
11573 build_function_type_list (void_type_node
,
11575 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11576 NULL_TREE
, void_type_node
);
11577 TREE_PUBLIC (decl
) = 1;
11578 TREE_STATIC (decl
) = 1;
11579 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11580 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11581 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11582 resolve_unique_section (decl
, 0, flag_function_sections
);
11583 allocate_struct_function (decl
, true);
11584 cfun
->is_thunk
= 1;
11585 current_function_decl
= decl
;
11586 init_varasm_status ();
11587 assemble_start_function (decl
, name
);
11591 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11592 switch_to_section (text_section
);
11594 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11595 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11598 #ifdef DWARF2_UNWIND_INFO
11599 do_cfi
= dwarf2out_do_cfi_asm ();
11601 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11603 if (flag_delayed_branch
)
11604 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11605 reg_name
, reg_name
);
11607 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11608 reg_name
, reg_name
);
11609 #ifdef DWARF2_UNWIND_INFO
11611 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11615 if (NEED_INDICATE_EXEC_STACK
)
11616 file_end_indicate_exec_stack ();
11618 #ifdef TARGET_SOLARIS
11619 solaris_file_end ();
11623 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11624 /* Implement TARGET_MANGLE_TYPE. */
11626 static const char *
11627 sparc_mangle_type (const_tree type
)
11630 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11631 && TARGET_LONG_DOUBLE_128
)
11634 /* For all other types, use normal C++ mangling. */
11639 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11640 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11641 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11644 sparc_emit_membar_for_model (enum memmodel model
,
11645 int load_store
, int before_after
)
11647 /* Bits for the MEMBAR mmask field. */
11648 const int LoadLoad
= 1;
11649 const int StoreLoad
= 2;
11650 const int LoadStore
= 4;
11651 const int StoreStore
= 8;
11653 int mm
= 0, implied
= 0;
11655 switch (sparc_memory_model
)
11658 /* Sequential Consistency. All memory transactions are immediately
11659 visible in sequential execution order. No barriers needed. */
11660 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11664 /* Total Store Ordering: all memory transactions with store semantics
11665 are followed by an implied StoreStore. */
11666 implied
|= StoreStore
;
11668 /* If we're not looking for a raw barrer (before+after), then atomic
11669 operations get the benefit of being both load and store. */
11670 if (load_store
== 3 && before_after
== 1)
11671 implied
|= StoreLoad
;
11675 /* Partial Store Ordering: all memory transactions with load semantics
11676 are followed by an implied LoadLoad | LoadStore. */
11677 implied
|= LoadLoad
| LoadStore
;
11679 /* If we're not looking for a raw barrer (before+after), then atomic
11680 operations get the benefit of being both load and store. */
11681 if (load_store
== 3 && before_after
== 2)
11682 implied
|= StoreLoad
| StoreStore
;
11686 /* Relaxed Memory Ordering: no implicit bits. */
11690 gcc_unreachable ();
11693 if (before_after
& 1)
11695 if (is_mm_release (model
) || is_mm_acq_rel (model
)
11696 || is_mm_seq_cst (model
))
11698 if (load_store
& 1)
11699 mm
|= LoadLoad
| StoreLoad
;
11700 if (load_store
& 2)
11701 mm
|= LoadStore
| StoreStore
;
11704 if (before_after
& 2)
11706 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
11707 || is_mm_seq_cst (model
))
11709 if (load_store
& 1)
11710 mm
|= LoadLoad
| LoadStore
;
11711 if (load_store
& 2)
11712 mm
|= StoreLoad
| StoreStore
;
11716 /* Remove the bits implied by the system memory model. */
11719 /* For raw barriers (before+after), always emit a barrier.
11720 This will become a compile-time barrier if needed. */
11721 if (mm
|| before_after
== 3)
11722 emit_insn (gen_membar (GEN_INT (mm
)));
11725 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11726 compare and swap on the word containing the byte or half-word. */
11729 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11730 rtx oldval
, rtx newval
)
11732 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11733 rtx addr
= gen_reg_rtx (Pmode
);
11734 rtx off
= gen_reg_rtx (SImode
);
11735 rtx oldv
= gen_reg_rtx (SImode
);
11736 rtx newv
= gen_reg_rtx (SImode
);
11737 rtx oldvalue
= gen_reg_rtx (SImode
);
11738 rtx newvalue
= gen_reg_rtx (SImode
);
11739 rtx res
= gen_reg_rtx (SImode
);
11740 rtx resv
= gen_reg_rtx (SImode
);
11741 rtx memsi
, val
, mask
, cc
;
11743 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11745 if (Pmode
!= SImode
)
11746 addr1
= gen_lowpart (SImode
, addr1
);
11747 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11749 memsi
= gen_rtx_MEM (SImode
, addr
);
11750 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11751 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11753 val
= copy_to_reg (memsi
);
11755 emit_insn (gen_rtx_SET (off
,
11756 gen_rtx_XOR (SImode
, off
,
11757 GEN_INT (GET_MODE (mem
) == QImode
11760 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11762 if (GET_MODE (mem
) == QImode
)
11763 mask
= force_reg (SImode
, GEN_INT (0xff));
11765 mask
= force_reg (SImode
, GEN_INT (0xffff));
11767 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
11769 emit_insn (gen_rtx_SET (val
,
11770 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11773 oldval
= gen_lowpart (SImode
, oldval
);
11774 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11776 newval
= gen_lowpart_common (SImode
, newval
);
11777 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
11779 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
11781 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
11783 rtx_code_label
*end_label
= gen_label_rtx ();
11784 rtx_code_label
*loop_label
= gen_label_rtx ();
11785 emit_label (loop_label
);
11787 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
11789 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
11791 emit_move_insn (bool_result
, const1_rtx
);
11793 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11795 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11797 emit_insn (gen_rtx_SET (resv
,
11798 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11801 emit_move_insn (bool_result
, const0_rtx
);
11803 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11804 emit_insn (gen_rtx_SET (val
, resv
));
11806 /* Use cbranchcc4 to separate the compare and branch! */
11807 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11808 cc
, const0_rtx
, loop_label
));
11810 emit_label (end_label
);
11812 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
11814 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11816 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11819 /* Expand code to perform a compare-and-swap. */
11822 sparc_expand_compare_and_swap (rtx operands
[])
11824 rtx bval
, retval
, mem
, oldval
, newval
;
11826 enum memmodel model
;
11828 bval
= operands
[0];
11829 retval
= operands
[1];
11831 oldval
= operands
[3];
11832 newval
= operands
[4];
11833 model
= (enum memmodel
) INTVAL (operands
[6]);
11834 mode
= GET_MODE (mem
);
11836 sparc_emit_membar_for_model (model
, 3, 1);
11838 if (reg_overlap_mentioned_p (retval
, oldval
))
11839 oldval
= copy_to_reg (oldval
);
11841 if (mode
== QImode
|| mode
== HImode
)
11842 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11845 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11848 if (mode
== SImode
)
11849 gen
= gen_atomic_compare_and_swapsi_1
;
11851 gen
= gen_atomic_compare_and_swapdi_1
;
11852 emit_insn (gen (retval
, mem
, oldval
, newval
));
11854 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11856 convert_move (bval
, x
, 1);
11859 sparc_emit_membar_for_model (model
, 3, 2);
11863 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
11867 sel
= gen_lowpart (DImode
, sel
);
11871 /* inp = xxxxxxxAxxxxxxxB */
11872 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11873 NULL_RTX
, 1, OPTAB_DIRECT
);
11874 /* t_1 = ....xxxxxxxAxxx. */
11875 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11876 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11877 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11878 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11879 /* sel = .......B */
11880 /* t_1 = ...A.... */
11881 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11882 /* sel = ...A...B */
11883 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11884 /* sel = AAAABBBB * 4 */
11885 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11886 /* sel = { A*4, A*4+1, A*4+2, ... } */
11890 /* inp = xxxAxxxBxxxCxxxD */
11891 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11892 NULL_RTX
, 1, OPTAB_DIRECT
);
11893 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11894 NULL_RTX
, 1, OPTAB_DIRECT
);
11895 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11896 NULL_RTX
, 1, OPTAB_DIRECT
);
11897 /* t_1 = ..xxxAxxxBxxxCxx */
11898 /* t_2 = ....xxxAxxxBxxxC */
11899 /* t_3 = ......xxxAxxxBxx */
11900 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11902 NULL_RTX
, 1, OPTAB_DIRECT
);
11903 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11905 NULL_RTX
, 1, OPTAB_DIRECT
);
11906 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11907 GEN_INT (0x070000),
11908 NULL_RTX
, 1, OPTAB_DIRECT
);
11909 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11910 GEN_INT (0x07000000),
11911 NULL_RTX
, 1, OPTAB_DIRECT
);
11912 /* sel = .......D */
11913 /* t_1 = .....C.. */
11914 /* t_2 = ...B.... */
11915 /* t_3 = .A...... */
11916 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11917 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11918 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11919 /* sel = .A.B.C.D */
11920 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11921 /* sel = AABBCCDD * 2 */
11922 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11923 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11927 /* input = xAxBxCxDxExFxGxH */
11928 sel
= expand_simple_binop (DImode
, AND
, sel
,
11929 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11931 NULL_RTX
, 1, OPTAB_DIRECT
);
11932 /* sel = .A.B.C.D.E.F.G.H */
11933 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11934 NULL_RTX
, 1, OPTAB_DIRECT
);
11935 /* t_1 = ..A.B.C.D.E.F.G. */
11936 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11937 NULL_RTX
, 1, OPTAB_DIRECT
);
11938 /* sel = .AABBCCDDEEFFGGH */
11939 sel
= expand_simple_binop (DImode
, AND
, sel
,
11940 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11942 NULL_RTX
, 1, OPTAB_DIRECT
);
11943 /* sel = ..AB..CD..EF..GH */
11944 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11945 NULL_RTX
, 1, OPTAB_DIRECT
);
11946 /* t_1 = ....AB..CD..EF.. */
11947 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11948 NULL_RTX
, 1, OPTAB_DIRECT
);
11949 /* sel = ..ABABCDCDEFEFGH */
11950 sel
= expand_simple_binop (DImode
, AND
, sel
,
11951 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11952 NULL_RTX
, 1, OPTAB_DIRECT
);
11953 /* sel = ....ABCD....EFGH */
11954 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11955 NULL_RTX
, 1, OPTAB_DIRECT
);
11956 /* t_1 = ........ABCD.... */
11957 sel
= gen_lowpart (SImode
, sel
);
11958 t_1
= gen_lowpart (SImode
, t_1
);
11962 gcc_unreachable ();
11965 /* Always perform the final addition/merge within the bmask insn. */
11966 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, t_1
));
11969 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11972 sparc_frame_pointer_required (void)
11974 /* If the stack pointer is dynamically modified in the function, it cannot
11975 serve as the frame pointer. */
11976 if (cfun
->calls_alloca
)
11979 /* If the function receives nonlocal gotos, it needs to save the frame
11980 pointer in the nonlocal_goto_save_area object. */
11981 if (cfun
->has_nonlocal_label
)
11984 /* In flat mode, that's it. */
11988 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11989 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11992 /* The way this is structured, we can't eliminate SFP in favor of SP
11993 if the frame pointer is required: we want to use the SFP->HFP elimination
11994 in that case. But the test in update_eliminables doesn't know we are
11995 assuming below that we only do the former elimination. */
11998 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12000 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12003 /* Return the hard frame pointer directly to bypass the stack bias. */
12006 sparc_builtin_setjmp_frame_value (void)
12008 return hard_frame_pointer_rtx
;
12011 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12012 they won't be allocated. */
12015 sparc_conditional_register_usage (void)
12017 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12019 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12020 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12022 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12023 /* then honor it. */
12024 if (TARGET_ARCH32
&& fixed_regs
[5])
12026 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12031 for (regno
= SPARC_FIRST_V9_FP_REG
;
12032 regno
<= SPARC_LAST_V9_FP_REG
;
12034 fixed_regs
[regno
] = 1;
12035 /* %fcc0 is used by v8 and v9. */
12036 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12037 regno
<= SPARC_LAST_V9_FCC_REG
;
12039 fixed_regs
[regno
] = 1;
12044 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12045 fixed_regs
[regno
] = 1;
12047 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12048 /* then honor it. Likewise with g3 and g4. */
12049 if (fixed_regs
[2] == 2)
12050 fixed_regs
[2] = ! TARGET_APP_REGS
;
12051 if (fixed_regs
[3] == 2)
12052 fixed_regs
[3] = ! TARGET_APP_REGS
;
12053 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12054 fixed_regs
[4] = ! TARGET_APP_REGS
;
12055 else if (TARGET_CM_EMBMEDANY
)
12057 else if (fixed_regs
[4] == 2)
12062 /* Disable leaf functions. */
12063 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12064 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12065 leaf_reg_remap
[regno
] = regno
;
12068 global_regs
[SPARC_GSR_REG
] = 1;
12071 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12073 - We can't load constants into FP registers.
12074 - We can't load FP constants into integer registers when soft-float,
12075 because there is no soft-float pattern with a r/F constraint.
12076 - We can't load FP constants into integer registers for TFmode unless
12077 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12078 - Try and reload integer constants (symbolic or otherwise) back into
12079 registers directly, rather than having them dumped to memory. */
12082 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12084 machine_mode mode
= GET_MODE (x
);
12085 if (CONSTANT_P (x
))
12087 if (FP_REG_CLASS_P (rclass
)
12088 || rclass
== GENERAL_OR_FP_REGS
12089 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12090 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12091 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12094 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12095 return GENERAL_REGS
;
12097 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12099 if (! FP_REG_CLASS_P (rclass
)
12100 || !(const_zero_operand (x
, mode
)
12101 || const_all_ones_operand (x
, mode
)))
12108 && (rclass
== EXTRA_FP_REGS
12109 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12111 int regno
= true_regnum (x
);
12113 if (SPARC_INT_REG_P (regno
))
12114 return (rclass
== EXTRA_FP_REGS
12115 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12121 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12122 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12125 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12129 gcc_assert (! TARGET_ARCH64
);
12131 if (sparc_check_64 (operands
[1], insn
) <= 0)
12132 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12133 if (which_alternative
== 1)
12134 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12135 if (GET_CODE (operands
[2]) == CONST_INT
)
12137 if (which_alternative
== 1)
12139 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12140 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12141 output_asm_insn (mulstr
, operands
);
12142 return "srlx\t%L0, 32, %H0";
12146 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12147 output_asm_insn ("or\t%L1, %3, %3", operands
);
12148 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12149 output_asm_insn (mulstr
, operands
);
12150 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12151 return "mov\t%3, %L0";
12154 else if (rtx_equal_p (operands
[1], operands
[2]))
12156 if (which_alternative
== 1)
12158 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12159 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12160 output_asm_insn (mulstr
, operands
);
12161 return "srlx\t%L0, 32, %H0";
12165 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12166 output_asm_insn ("or\t%L1, %3, %3", operands
);
12167 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12168 output_asm_insn (mulstr
, operands
);
12169 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12170 return "mov\t%3, %L0";
12173 if (sparc_check_64 (operands
[2], insn
) <= 0)
12174 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12175 if (which_alternative
== 1)
12177 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12178 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12179 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12180 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12181 output_asm_insn (mulstr
, operands
);
12182 return "srlx\t%L0, 32, %H0";
12186 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12187 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12188 output_asm_insn ("or\t%L1, %3, %3", operands
);
12189 output_asm_insn ("or\t%L2, %4, %4", operands
);
12190 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12191 output_asm_insn (mulstr
, operands
);
12192 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12193 return "mov\t%3, %L0";
12197 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12198 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12199 and INNER_MODE are the modes describing TARGET. */
12202 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
12203 machine_mode inner_mode
)
12205 rtx t1
, final_insn
, sel
;
12208 t1
= gen_reg_rtx (mode
);
12210 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12211 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12216 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12217 bmask
= 0x45674567;
12220 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12221 bmask
= 0x67676767;
12224 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12225 bmask
= 0x77777777;
12228 gcc_unreachable ();
12231 sel
= force_reg (SImode
, GEN_INT (bmask
));
12232 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, const0_rtx
));
12233 emit_insn (final_insn
);
12236 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12237 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12240 vector_init_fpmerge (rtx target
, rtx elt
)
12242 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12244 t1
= gen_reg_rtx (V4QImode
);
12245 elt
= convert_modes (SImode
, QImode
, elt
, true);
12246 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12248 t2
= gen_reg_rtx (V8QImode
);
12249 t2_low
= gen_lowpart (V4QImode
, t2
);
12250 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12252 t3
= gen_reg_rtx (V8QImode
);
12253 t3_low
= gen_lowpart (V4QImode
, t3
);
12254 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12256 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12259 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12260 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12263 vector_init_faligndata (rtx target
, rtx elt
)
12265 rtx t1
= gen_reg_rtx (V4HImode
);
12268 elt
= convert_modes (SImode
, HImode
, elt
, true);
12269 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12271 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12272 force_reg (SImode
, GEN_INT (6)),
12275 for (i
= 0; i
< 4; i
++)
12276 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12279 /* Emit code to initialize TARGET to values for individual fields VALS. */
12282 sparc_expand_vector_init (rtx target
, rtx vals
)
12284 const machine_mode mode
= GET_MODE (target
);
12285 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
12286 const int n_elts
= GET_MODE_NUNITS (mode
);
12292 for (i
= 0; i
< n_elts
; i
++)
12294 rtx x
= XVECEXP (vals
, 0, i
);
12295 if (!CONSTANT_P (x
))
12298 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12304 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12308 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12310 if (GET_MODE_SIZE (inner_mode
) == 4)
12312 emit_move_insn (gen_lowpart (SImode
, target
),
12313 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12316 else if (GET_MODE_SIZE (inner_mode
) == 8)
12318 emit_move_insn (gen_lowpart (DImode
, target
),
12319 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12323 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12324 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12326 emit_move_insn (gen_highpart (word_mode
, target
),
12327 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12328 emit_move_insn (gen_lowpart (word_mode
, target
),
12329 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12333 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12337 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12340 if (mode
== V8QImode
)
12342 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12345 if (mode
== V4HImode
)
12347 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12352 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12353 for (i
= 0; i
< n_elts
; i
++)
12354 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12355 i
* GET_MODE_SIZE (inner_mode
)),
12356 XVECEXP (vals
, 0, i
));
12357 emit_move_insn (target
, mem
);
12360 /* Implement TARGET_SECONDARY_RELOAD. */
12363 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12364 machine_mode mode
, secondary_reload_info
*sri
)
12366 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12368 sri
->icode
= CODE_FOR_nothing
;
12369 sri
->extra_cost
= 0;
12371 /* We need a temporary when loading/storing a HImode/QImode value
12372 between memory and the FPU registers. This can happen when combine puts
12373 a paradoxical subreg in a float/fix conversion insn. */
12374 if (FP_REG_CLASS_P (rclass
)
12375 && (mode
== HImode
|| mode
== QImode
)
12376 && (GET_CODE (x
) == MEM
12377 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12378 && true_regnum (x
) == -1)))
12379 return GENERAL_REGS
;
12381 /* On 32-bit we need a temporary when loading/storing a DFmode value
12382 between unaligned memory and the upper FPU registers. */
12384 && rclass
== EXTRA_FP_REGS
12386 && GET_CODE (x
) == MEM
12387 && ! mem_min_alignment (x
, 8))
12390 if (((TARGET_CM_MEDANY
12391 && symbolic_operand (x
, mode
))
12392 || (TARGET_CM_EMBMEDANY
12393 && text_segment_operand (x
, mode
)))
12397 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12399 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12403 if (TARGET_VIS3
&& TARGET_ARCH32
)
12405 int regno
= true_regnum (x
);
12407 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12408 to move 8-byte values in 4-byte pieces. This only works via
12409 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12410 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12411 an FP_REGS intermediate move. */
12412 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12413 || ((general_or_i64_p (rclass
)
12414 || rclass
== GENERAL_OR_FP_REGS
)
12415 && SPARC_FP_REG_P (regno
)))
12417 sri
->extra_cost
= 2;
12425 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12426 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12429 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
12431 enum rtx_code rc
= GET_CODE (operands
[1]);
12432 machine_mode cmp_mode
;
12433 rtx cc_reg
, dst
, cmp
;
12436 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
12439 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
12440 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
12442 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
12443 rc
= GET_CODE (cmp
);
12446 if (! rtx_equal_p (operands
[2], dst
)
12447 && ! rtx_equal_p (operands
[3], dst
))
12449 if (reg_overlap_mentioned_p (dst
, cmp
))
12450 dst
= gen_reg_rtx (mode
);
12452 emit_move_insn (dst
, operands
[3]);
12454 else if (operands
[2] == dst
)
12456 operands
[2] = operands
[3];
12458 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
12459 rc
= reverse_condition_maybe_unordered (rc
);
12461 rc
= reverse_condition (rc
);
12464 if (XEXP (cmp
, 1) == const0_rtx
12465 && GET_CODE (XEXP (cmp
, 0)) == REG
12466 && cmp_mode
== DImode
12467 && v9_regcmp_p (rc
))
12468 cc_reg
= XEXP (cmp
, 0);
12470 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
12472 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
12474 emit_insn (gen_rtx_SET (dst
,
12475 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
12477 if (dst
!= operands
[0])
12478 emit_move_insn (operands
[0], dst
);
12483 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12484 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12485 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12486 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12487 code to be used for the condition mask. */
12490 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12492 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12493 enum rtx_code code
= GET_CODE (operands
[3]);
12495 mask
= gen_reg_rtx (Pmode
);
12496 cop0
= operands
[4];
12497 cop1
= operands
[5];
12498 if (code
== LT
|| code
== GE
)
12502 code
= swap_condition (code
);
12503 t
= cop0
; cop0
= cop1
; cop1
= t
;
12506 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12508 fcmp
= gen_rtx_UNSPEC (Pmode
,
12509 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12512 cmask
= gen_rtx_UNSPEC (DImode
,
12513 gen_rtvec (2, mask
, gsr
),
12516 bshuf
= gen_rtx_UNSPEC (mode
,
12517 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12520 emit_insn (gen_rtx_SET (mask
, fcmp
));
12521 emit_insn (gen_rtx_SET (gsr
, cmask
));
12523 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
12526 /* On sparc, any mode which naturally allocates into the float
12527 registers should return 4 here. */
12530 sparc_regmode_natural_size (machine_mode mode
)
12532 int size
= UNITS_PER_WORD
;
12536 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12538 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12545 /* Return TRUE if it is a good idea to tie two pseudo registers
12546 when one has mode MODE1 and one has mode MODE2.
12547 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12548 for any hard reg, then this must be FALSE for correct output.
12550 For V9 we have to deal with the fact that only the lower 32 floating
12551 point registers are 32-bit addressable. */
12554 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12556 enum mode_class mclass1
, mclass2
;
12557 unsigned short size1
, size2
;
12559 if (mode1
== mode2
)
12562 mclass1
= GET_MODE_CLASS (mode1
);
12563 mclass2
= GET_MODE_CLASS (mode2
);
12564 if (mclass1
!= mclass2
)
12570 /* Classes are the same and we are V9 so we have to deal with upper
12571 vs. lower floating point registers. If one of the modes is a
12572 4-byte mode, and the other is not, we have to mark them as not
12573 tieable because only the lower 32 floating point register are
12574 addressable 32-bits at a time.
12576 We can't just test explicitly for SFmode, otherwise we won't
12577 cover the vector mode cases properly. */
12579 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12582 size1
= GET_MODE_SIZE (mode1
);
12583 size2
= GET_MODE_SIZE (mode2
);
12584 if ((size1
> 4 && size2
== 4)
12585 || (size2
> 4 && size1
== 4))
12591 /* Implement TARGET_CSTORE_MODE. */
12593 static machine_mode
12594 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
12596 return (TARGET_ARCH64
? DImode
: SImode
);
12599 /* Return the compound expression made of T1 and T2. */
12602 compound_expr (tree t1
, tree t2
)
12604 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
12607 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12610 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12615 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
12616 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
12618 /* We generate the equivalent of feholdexcept (&fenv_var):
12620 unsigned int fenv_var;
12621 __builtin_store_fsr (&fenv_var);
12623 unsigned int tmp1_var;
12624 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12626 __builtin_load_fsr (&tmp1_var); */
12628 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
12629 TREE_ADDRESSABLE (fenv_var
) = 1;
12630 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
12631 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
12633 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
12634 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
12636 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
12637 TREE_ADDRESSABLE (tmp1_var
) = 1;
12638 tree masked_fenv_var
12639 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
12640 build_int_cst (unsigned_type_node
,
12641 ~(accrued_exception_mask
| trap_enable_mask
)));
12643 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
12644 NULL_TREE
, NULL_TREE
);
12646 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
12647 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
12648 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12650 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
12652 /* We reload the value of tmp1_var to clear the exceptions:
12654 __builtin_load_fsr (&tmp1_var); */
12656 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12658 /* We generate the equivalent of feupdateenv (&fenv_var):
12660 unsigned int tmp2_var;
12661 __builtin_store_fsr (&tmp2_var);
12663 __builtin_load_fsr (&fenv_var);
12665 if (SPARC_LOW_FE_EXCEPT_VALUES)
12667 __atomic_feraiseexcept ((int) tmp2_var); */
12669 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
12670 TREE_ADDRESSABLE (tmp2_var
) = 1;
12671 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
12673 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
12674 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
12676 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
12678 tree atomic_feraiseexcept
12679 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12681 = build_call_expr (atomic_feraiseexcept
, 1,
12682 fold_convert (integer_type_node
, tmp2_var
));
12684 if (SPARC_LOW_FE_EXCEPT_VALUES
)
12686 tree shifted_tmp2_var
12687 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
12688 build_int_cst (unsigned_type_node
, 5));
12690 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
12691 update_call
= compound_expr (update_shift
, update_call
);
12695 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
12698 #include "gt-sparc.h"