1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (match_operand 0 "register_operand")
121 if (GET_CODE (op) == SUBREG)
122 op = SUBREG_REG (op);
127 return CA_REGNO_P (REGNO (op));
130 ;; Return 1 if op is a signed 5-bit constant integer.
131 (define_predicate "s5bit_cint_operand"
132 (and (match_code "const_int")
133 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
135 ;; Return 1 if op is a unsigned 3-bit constant integer.
136 (define_predicate "u3bit_cint_operand"
137 (and (match_code "const_int")
138 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
140 ;; Return 1 if op is a unsigned 5-bit constant integer.
141 (define_predicate "u5bit_cint_operand"
142 (and (match_code "const_int")
143 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
145 ;; Return 1 if op is a unsigned 6-bit constant integer.
146 (define_predicate "u6bit_cint_operand"
147 (and (match_code "const_int")
148 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
150 ;; Return 1 if op is an unsigned 7-bit constant integer.
151 (define_predicate "u7bit_cint_operand"
152 (and (match_code "const_int")
153 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
155 ;; Return 1 if op is a signed 8-bit constant integer.
156 ;; Integer multiplication complete more quickly
157 (define_predicate "s8bit_cint_operand"
158 (and (match_code "const_int")
159 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
161 ;; Return 1 if op is a unsigned 10-bit constant integer.
162 (define_predicate "u10bit_cint_operand"
163 (and (match_code "const_int")
164 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
166 ;; Return 1 if op is a constant integer that can fit in a D field.
167 (define_predicate "short_cint_operand"
168 (and (match_code "const_int")
169 (match_test "satisfies_constraint_I (op)")))
171 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
172 (define_predicate "u_short_cint_operand"
173 (and (match_code "const_int")
174 (match_test "satisfies_constraint_K (op)")))
176 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
177 ;; shifted left 16 bits
178 (define_predicate "upper16_cint_operand"
179 (and (match_code "const_int")
180 (match_test "satisfies_constraint_L (op)")))
182 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
183 (define_predicate "non_short_cint_operand"
184 (and (match_code "const_int")
185 (match_test "(unsigned HOST_WIDE_INT)
186 (INTVAL (op) + 0x8000) >= 0x10000")))
188 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
189 (define_predicate "exact_log2_cint_operand"
190 (and (match_code "const_int")
191 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
193 ;; Match op = 0 or op = 1.
194 (define_predicate "const_0_to_1_operand"
195 (and (match_code "const_int")
196 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
199 (define_predicate "const_0_to_3_operand"
200 (and (match_code "const_int")
201 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
203 ;; Match op = 2 or op = 3.
204 (define_predicate "const_2_to_3_operand"
205 (and (match_code "const_int")
206 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
209 (define_predicate "const_0_to_7_operand"
210 (and (match_code "const_int")
211 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
214 (define_predicate "const_0_to_15_operand"
215 (and (match_code "const_int")
216 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
218 ;; Return 1 if op is a register that is not special.
219 (define_predicate "gpc_reg_operand"
220 (match_operand 0 "register_operand")
222 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
225 if (GET_CODE (op) == SUBREG)
226 op = SUBREG_REG (op);
231 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
234 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
237 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
240 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
243 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
244 ;; allow floating point or vector registers.
245 (define_predicate "int_reg_operand"
246 (match_operand 0 "register_operand")
248 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
251 if (GET_CODE (op) == SUBREG)
252 op = SUBREG_REG (op);
257 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
260 return INT_REGNO_P (REGNO (op));
263 ;; Like int_reg_operand, but don't return true for pseudo registers
264 (define_predicate "int_reg_operand_not_pseudo"
265 (match_operand 0 "register_operand")
267 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
270 if (GET_CODE (op) == SUBREG)
271 op = SUBREG_REG (op);
276 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
279 return INT_REGNO_P (REGNO (op));
282 ;; Like int_reg_operand, but only return true for base registers
283 (define_predicate "base_reg_operand"
284 (match_operand 0 "int_reg_operand")
286 if (GET_CODE (op) == SUBREG)
287 op = SUBREG_REG (op);
292 return (REGNO (op) != FIRST_GPR_REGNO);
296 ;; Return true if this is a traditional floating point register
297 (define_predicate "fpr_reg_operand"
298 (match_code "reg,subreg")
302 if (GET_CODE (op) == SUBREG)
303 op = SUBREG_REG (op);
309 if (r >= FIRST_PSEUDO_REGISTER)
312 return FP_REGNO_P (r);
315 ;; Return true if this is a register that can has D-form addressing (GPR and
316 ;; traditional FPR registers for scalars). ISA 3.0 (power9) adds D-form
317 ;; addressing for scalars in Altivec registers.
319 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the
320 ;; power9 fusion allow the floating point types.
321 (define_predicate "toc_fusion_or_p9_reg_operand"
322 (match_code "reg,subreg")
325 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
327 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode)));
328 bool fpr_p = (TARGET_P9_FUSION
329 && (mode == DFmode || mode == SFmode
330 || (TARGET_POWERPC64 && mode == DImode)));
331 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR
332 && (mode == DFmode || mode == SFmode));
334 if (!TARGET_P8_FUSION)
337 if (GET_CODE (op) == SUBREG)
338 op = SUBREG_REG (op);
344 if (r >= FIRST_PSEUDO_REGISTER)
345 return (gpr_p || fpr_p || vmx_p);
353 if (ALTIVEC_REGNO_P (r))
359 ;; Return 1 if op is a HTM specific SPR register.
360 (define_predicate "htm_spr_reg_operand"
361 (match_operand 0 "register_operand")
366 if (GET_CODE (op) == SUBREG)
367 op = SUBREG_REG (op);
386 ;; Return 1 if op is a general purpose register that is an even register
387 ;; which suitable for a load/store quad operation
388 ;; Subregs are not allowed here because when they are combine can
389 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
390 ;; think the innermost reg needs reloading, in TImode instead of
391 ;; PTImode. So reload will choose a reg in TImode which has no
392 ;; requirement that the reg be even.
393 (define_predicate "quad_int_reg_operand"
398 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
402 if (r >= FIRST_PSEUDO_REGISTER)
405 return (INT_REGNO_P (r) && ((r & 1) == 0));
408 ;; Return 1 if op is a register that is a condition register field.
409 (define_predicate "cc_reg_operand"
410 (match_operand 0 "register_operand")
412 if (GET_CODE (op) == SUBREG)
413 op = SUBREG_REG (op);
418 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
421 return CR_REGNO_P (REGNO (op));
424 ;; Return 1 if op is a register that is a condition register field not cr0.
425 (define_predicate "cc_reg_not_cr0_operand"
426 (match_operand 0 "register_operand")
428 if (GET_CODE (op) == SUBREG)
429 op = SUBREG_REG (op);
434 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
437 return CR_REGNO_NOT_CR0_P (REGNO (op));
440 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
441 (define_predicate "cc_reg_not_micro_cr0_operand"
442 (match_operand 0 "register_operand")
444 if (GET_CODE (op) == SUBREG)
445 op = SUBREG_REG (op);
450 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
453 if (rs6000_gen_cell_microcode)
454 return CR_REGNO_NOT_CR0_P (REGNO (op));
456 return CR_REGNO_P (REGNO (op));
459 ;; Return 1 if op is a constant integer valid for D field
460 ;; or non-special register register.
461 (define_predicate "reg_or_short_operand"
462 (if_then_else (match_code "const_int")
463 (match_operand 0 "short_cint_operand")
464 (match_operand 0 "gpc_reg_operand")))
466 ;; Return 1 if op is a constant integer valid for DS field
467 ;; or non-special register.
468 (define_predicate "reg_or_aligned_short_operand"
469 (if_then_else (match_code "const_int")
470 (and (match_operand 0 "short_cint_operand")
471 (match_test "!(INTVAL (op) & 3)"))
472 (match_operand 0 "gpc_reg_operand")))
474 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
475 ;; or non-special register.
476 (define_predicate "reg_or_u_short_operand"
477 (if_then_else (match_code "const_int")
478 (match_operand 0 "u_short_cint_operand")
479 (match_operand 0 "gpc_reg_operand")))
481 ;; Return 1 if op is any constant integer
482 ;; or non-special register.
483 (define_predicate "reg_or_cint_operand"
484 (ior (match_code "const_int")
485 (match_operand 0 "gpc_reg_operand")))
487 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
488 (define_predicate "add_cint_operand"
489 (and (match_code "const_int")
490 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
491 + (mode == SImode ? 0x80000000 : 0x80008000))
492 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
494 ;; Return 1 if op is a constant integer valid for addition
495 ;; or non-special register.
496 (define_predicate "reg_or_add_cint_operand"
497 (if_then_else (match_code "const_int")
498 (match_operand 0 "add_cint_operand")
499 (match_operand 0 "gpc_reg_operand")))
501 ;; Return 1 if op is a constant integer valid for subtraction
502 ;; or non-special register.
503 (define_predicate "reg_or_sub_cint_operand"
504 (if_then_else (match_code "const_int")
505 (match_test "(unsigned HOST_WIDE_INT)
506 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
507 < (unsigned HOST_WIDE_INT) 0x100000000ll")
508 (match_operand 0 "gpc_reg_operand")))
510 ;; Return 1 if op is any 32-bit unsigned constant integer
511 ;; or non-special register.
512 (define_predicate "reg_or_logical_cint_operand"
513 (if_then_else (match_code "const_int")
514 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
516 || ((INTVAL (op) & GET_MODE_MASK (mode)
517 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
518 (match_operand 0 "gpc_reg_operand")))
520 ;; Like reg_or_logical_cint_operand, but allow vsx registers
521 (define_predicate "vsx_reg_or_cint_operand"
522 (ior (match_operand 0 "vsx_register_operand")
523 (match_operand 0 "reg_or_logical_cint_operand")))
525 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
526 ;; with no more than one instruction per word.
527 (define_predicate "easy_fp_constant"
528 (match_code "const_double")
530 if (GET_MODE (op) != mode
531 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
534 /* Consider all constants with -msoft-float to be easy. */
535 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
536 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
540 /* 0.0D is not all zero bits. */
541 if (DECIMAL_FLOAT_MODE_P (mode))
544 /* The constant 0.0 is easy under VSX. */
545 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
548 /* If we are using V.4 style PIC, consider all constants to be hard. */
549 if (flag_pic && DEFAULT_ABI == ABI_V4)
552 /* If we have real FPRs, consider floating point constants hard (other than
553 0.0 under VSX), so that the constant gets pushed to memory during the
554 early RTL phases. This has the advantage that double precision constants
555 that can be represented in single precision without a loss of precision
556 will use single precision loads. */
568 return (num_insns_constant (op, DImode) <= 2);
578 ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
579 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
581 (define_predicate "xxspltib_constant_split"
582 (match_code "const_vector,vec_duplicate,const_int")
587 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
590 return num_insns > 1;
594 ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB
597 (define_predicate "xxspltib_constant_nosplit"
598 (match_code "const_vector,vec_duplicate,const_int")
603 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
606 return num_insns == 1;
609 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
610 ;; vector register without using memory.
611 (define_predicate "easy_vector_constant"
612 (match_code "const_vector")
614 /* As the paired vectors are actually FPRs it seems that there is
615 no easy way to load a CONST_VECTOR without using memory. */
616 if (TARGET_PAIRED_FLOAT)
619 /* Because IEEE 128-bit floating point is considered a vector type
620 in order to pass it in VSX registers, it might use this function
621 instead of easy_fp_constant. */
622 if (FLOAT128_VECTOR_P (mode))
623 return easy_fp_constant (op, mode);
625 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
630 if (zero_constant (op, mode) || all_ones_constant (op, mode))
634 && xxspltib_constant_p (op, mode, &num_insns, &value))
637 return easy_altivec_constant (op, mode);
640 if (SPE_VECTOR_MODE (mode))
643 if (zero_constant (op, mode))
645 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
648 /* Limit SPE vectors to 15 bits signed. These we can generate with:
653 I don't know how efficient it would be to allow bigger constants,
654 considering we'll have an extra 'ori' for every 'li'. I doubt 5
655 instructions is better than a 64-bit memory load, but I don't
656 have the e500 timing specs. */
657 if (mode == V2SImode)
659 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
660 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
661 return cst >= -0x7fff && cst <= 0x7fff
662 && cst2 >= -0x7fff && cst2 <= 0x7fff;
669 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
670 (define_predicate "easy_vector_constant_add_self"
671 (and (match_code "const_vector")
672 (and (match_test "TARGET_ALTIVEC")
673 (match_test "easy_altivec_constant (op, mode)")))
677 if (mode == V2DImode || mode == V2DFmode)
679 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
680 val = const_vector_elt_as_int (op, elt);
681 val = ((val & 0xff) ^ 0x80) - 0x80;
682 return EASY_VECTOR_15_ADD_SELF (val);
685 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
686 (define_predicate "easy_vector_constant_msb"
687 (and (match_code "const_vector")
688 (and (match_test "TARGET_ALTIVEC")
689 (match_test "easy_altivec_constant (op, mode)")))
693 if (mode == V2DImode || mode == V2DFmode)
695 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
696 val = const_vector_elt_as_int (op, elt);
697 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
700 ;; Return true if this is an easy altivec constant that we form
702 (define_predicate "easy_vector_constant_vsldoi"
703 (and (match_code "const_vector")
704 (and (match_test "TARGET_ALTIVEC")
705 (and (match_test "easy_altivec_constant (op, mode)")
706 (match_test "vspltis_shifted (op) != 0")))))
708 ;; Return 1 if operand is constant zero (scalars and vectors).
709 (define_predicate "zero_constant"
710 (and (match_code "const_int,const_double,const_wide_int,const_vector")
711 (match_test "op == CONST0_RTX (mode)")))
713 ;; Return 1 if operand is constant -1 (scalars and vectors).
714 (define_predicate "all_ones_constant"
715 (and (match_code "const_int,const_double,const_wide_int,const_vector")
716 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
718 ;; Return 1 if operand is 0.0.
719 (define_predicate "zero_fp_constant"
720 (and (match_code "const_double")
721 (match_test "SCALAR_FLOAT_MODE_P (mode)
722 && op == CONST0_RTX (mode)")))
724 ;; Return 1 if the operand is in volatile memory. Note that during the
725 ;; RTL generation phase, memory_operand does not return TRUE for volatile
726 ;; memory references. So this function allows us to recognize volatile
727 ;; references where it's safe.
728 (define_predicate "volatile_mem_operand"
729 (and (and (match_code "mem")
730 (match_test "MEM_VOLATILE_P (op)"))
731 (if_then_else (match_test "reload_completed")
732 (match_operand 0 "memory_operand")
733 (if_then_else (match_test "reload_in_progress")
734 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
735 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
737 ;; Return 1 if the operand is an offsettable memory operand.
738 (define_predicate "offsettable_mem_operand"
739 (and (match_operand 0 "memory_operand")
740 (match_test "offsettable_nonstrict_memref_p (op)")))
742 ;; Return 1 if the operand is suitable for load/store quad memory.
743 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
744 (define_predicate "quad_memory_operand"
747 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
750 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
753 return quad_address_p (XEXP (op, 0), mode, false);
756 ;; Return 1 if the operand is suitable for load/store to vector registers with
757 ;; d-form addressing (register+offset), which was added in ISA 3.0.
758 ;; Unlike quad_memory_operand, we do not have to check for alignment.
759 (define_predicate "vsx_quad_dform_memory_operand"
762 if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
765 return quad_address_p (XEXP (op, 0), mode, false);
768 ;; Return 1 if the operand is an indexed or indirect memory operand.
769 (define_predicate "indexed_or_indirect_operand"
773 if (VECTOR_MEM_ALTIVEC_P (mode)
774 && GET_CODE (op) == AND
775 && GET_CODE (XEXP (op, 1)) == CONST_INT
776 && INTVAL (XEXP (op, 1)) == -16)
779 return indexed_or_indirect_address (op, mode);
782 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
783 ;; moves are supported.
784 (define_predicate "reg_or_indexed_operand"
785 (match_code "mem,reg,subreg")
788 return indexed_or_indirect_operand (op, mode);
789 else if (TARGET_DIRECT_MOVE)
790 return register_operand (op, mode);
795 ;; Return 1 if the operand is an indexed or indirect memory operand with an
796 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
797 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
798 ;; while VSX uses the full address and traps)
799 (define_predicate "altivec_indexed_or_indirect_operand"
803 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
804 && GET_CODE (op) == AND
805 && GET_CODE (XEXP (op, 1)) == CONST_INT
806 && INTVAL (XEXP (op, 1)) == -16)
807 return indexed_or_indirect_address (XEXP (op, 0), mode);
812 ;; Return 1 if the operand is an indexed or indirect address.
813 (define_special_predicate "indexed_or_indirect_address"
814 (and (match_test "REG_P (op)
815 || (GET_CODE (op) == PLUS
816 /* Omit testing REG_P (XEXP (op, 0)). */
817 && REG_P (XEXP (op, 1)))")
818 (match_operand 0 "address_operand")))
820 ;; Return 1 if the operand is an index-form address.
821 (define_special_predicate "indexed_address"
822 (match_test "(GET_CODE (op) == PLUS
823 && REG_P (XEXP (op, 0))
824 && REG_P (XEXP (op, 1)))"))
826 ;; Return 1 if the operand is a MEM with an update-form address. This may
827 ;; also include update-indexed form.
828 (define_special_predicate "update_address_mem"
829 (match_test "(MEM_P (op)
830 && (GET_CODE (XEXP (op, 0)) == PRE_INC
831 || GET_CODE (XEXP (op, 0)) == PRE_DEC
832 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
834 ;; Return 1 if the operand is a MEM with an indexed-form address.
835 (define_special_predicate "indexed_address_mem"
836 (match_test "(MEM_P (op)
837 && (indexed_address (XEXP (op, 0), mode)
838 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
839 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
841 ;; Return 1 if the operand is either a non-special register or can be used
842 ;; as the operand of a `mode' add insn.
843 (define_predicate "add_operand"
844 (if_then_else (match_code "const_int")
845 (match_test "satisfies_constraint_I (op)
846 || satisfies_constraint_L (op)")
847 (match_operand 0 "gpc_reg_operand")))
849 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
850 (define_predicate "adde_operand"
851 (if_then_else (match_code "const_int")
852 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
853 (match_operand 0 "gpc_reg_operand")))
855 ;; Return 1 if OP is a constant but not a valid add_operand.
856 (define_predicate "non_add_cint_operand"
857 (and (match_code "const_int")
858 (match_test "!satisfies_constraint_I (op)
859 && !satisfies_constraint_L (op)")))
861 ;; Return 1 if the operand is a constant that can be used as the operand
863 (define_predicate "logical_const_operand"
864 (match_code "const_int")
868 opl = INTVAL (op) & GET_MODE_MASK (mode);
870 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
871 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
874 ;; Return 1 if the operand is a non-special register or a constant that
875 ;; can be used as the operand of an OR or XOR.
876 (define_predicate "logical_operand"
877 (ior (match_operand 0 "gpc_reg_operand")
878 (match_operand 0 "logical_const_operand")))
880 ;; Return 1 if op is a constant that is not a logical operand, but could
881 ;; be split into one.
882 (define_predicate "non_logical_cint_operand"
883 (and (match_code "const_int,const_wide_int")
884 (and (not (match_operand 0 "logical_operand"))
885 (match_operand 0 "reg_or_logical_cint_operand"))))
887 ;; Return 1 if the operand is either a non-special register or a
888 ;; constant that can be used as the operand of a logical AND.
889 (define_predicate "and_operand"
890 (ior (and (match_code "const_int")
891 (match_test "rs6000_is_valid_and_mask (op, mode)"))
892 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
893 (match_operand 0 "gpc_reg_operand")
894 (match_operand 0 "logical_operand"))))
896 ;; Return 1 if the operand is either a logical operand or a short cint operand.
897 (define_predicate "scc_eq_operand"
898 (ior (match_operand 0 "logical_operand")
899 (match_operand 0 "short_cint_operand")))
901 ;; Return 1 if the operand is a general non-special register or memory operand.
902 (define_predicate "reg_or_mem_operand"
903 (ior (match_operand 0 "memory_operand")
904 (ior (and (match_code "mem")
905 (match_test "macho_lo_sum_memory_operand (op, mode)"))
906 (ior (match_operand 0 "volatile_mem_operand")
907 (match_operand 0 "gpc_reg_operand")))))
909 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
910 (define_predicate "reg_or_none500mem_operand"
911 (if_then_else (match_code "mem")
912 (and (match_test "!TARGET_E500_DOUBLE")
913 (ior (match_operand 0 "memory_operand")
914 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
915 (match_operand 0 "volatile_mem_operand"))))
916 (match_operand 0 "gpc_reg_operand")))
918 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
919 (define_predicate "zero_reg_mem_operand"
920 (ior (and (match_test "TARGET_VSX")
921 (match_operand 0 "zero_fp_constant"))
922 (match_operand 0 "reg_or_mem_operand")))
924 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
925 ;; data types inside of a vector that scalar instructions operate on
926 (define_predicate "vsx_scalar_64bit"
927 (match_code "const_int")
929 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
932 ;; Return 1 if the operand is a general register or memory operand without
933 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
935 (define_predicate "lwa_operand"
936 (match_code "reg,subreg,mem")
938 rtx inner, addr, offset;
941 if (reload_completed && GET_CODE (inner) == SUBREG)
942 inner = SUBREG_REG (inner);
944 if (gpc_reg_operand (inner, mode))
946 if (!memory_operand (inner, mode))
948 if (!rs6000_gen_cell_microcode)
951 addr = XEXP (inner, 0);
952 if (GET_CODE (addr) == PRE_INC
953 || GET_CODE (addr) == PRE_DEC
954 || (GET_CODE (addr) == PRE_MODIFY
955 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
957 if (GET_CODE (addr) == LO_SUM
958 && GET_CODE (XEXP (addr, 0)) == REG
959 && GET_CODE (XEXP (addr, 1)) == CONST)
960 addr = XEXP (XEXP (addr, 1), 0);
961 if (GET_CODE (addr) != PLUS)
963 offset = XEXP (addr, 1);
964 if (GET_CODE (offset) != CONST_INT)
966 return INTVAL (offset) % 4 == 0;
969 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
970 (define_predicate "symbol_ref_operand"
971 (and (match_code "symbol_ref")
972 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
973 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
975 ;; Return 1 if op is an operand that can be loaded via the GOT.
976 ;; or non-special register register field no cr0
977 (define_predicate "got_operand"
978 (match_code "symbol_ref,const,label_ref"))
980 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
981 ;; excluding labels involving addition.
982 (define_predicate "got_no_const_operand"
983 (match_code "symbol_ref,label_ref"))
985 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
986 (define_predicate "rs6000_tls_symbol_ref"
987 (and (match_code "symbol_ref")
988 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
990 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
991 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
992 (define_predicate "call_operand"
993 (if_then_else (match_code "reg")
994 (match_test "REGNO (op) == LR_REGNO
995 || REGNO (op) == CTR_REGNO
996 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
997 (match_code "symbol_ref")))
999 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1001 (define_predicate "current_file_function_operand"
1002 (and (match_code "symbol_ref")
1003 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1004 && (SYMBOL_REF_LOCAL_P (op)
1005 || op == XEXP (DECL_RTL (current_function_decl), 0))
1006 && !((DEFAULT_ABI == ABI_AIX
1007 || DEFAULT_ABI == ABI_ELFv2)
1008 && (SYMBOL_REF_EXTERNAL_P (op)
1009 || SYMBOL_REF_WEAK (op)))")))
1011 ;; Return 1 if this operand is a valid input for a move insn.
1012 (define_predicate "input_operand"
1013 (match_code "symbol_ref,const,reg,subreg,mem,
1014 const_double,const_wide_int,const_vector,const_int")
1016 /* Memory is always valid. */
1017 if (memory_operand (op, mode))
1020 /* For floating-point, easy constants are valid. */
1021 if (SCALAR_FLOAT_MODE_P (mode)
1022 && easy_fp_constant (op, mode))
1025 /* Allow any integer constant. */
1026 if (GET_MODE_CLASS (mode) == MODE_INT
1027 && CONST_SCALAR_INT_P (op))
1030 /* Allow easy vector constants. */
1031 if (GET_CODE (op) == CONST_VECTOR
1032 && easy_vector_constant (op, mode))
1035 /* Do not allow invalid E500 subregs. */
1036 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1037 && GET_CODE (op) == SUBREG
1038 && invalid_e500_subreg (op, mode))
1041 /* For floating-point or multi-word mode, the only remaining valid type
1043 if (SCALAR_FLOAT_MODE_P (mode)
1044 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1045 return register_operand (op, mode);
1047 /* We don't allow moving the carry bit around. */
1048 if (ca_operand (op, mode))
1051 /* The only cases left are integral modes one word or smaller (we
1052 do not get called for MODE_CC values). These can be in any
1054 if (register_operand (op, mode))
1057 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1059 if (DEFAULT_ABI == ABI_V4
1060 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1061 && small_data_operand (op, Pmode))
1067 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1068 (define_predicate "splat_input_operand"
1069 (match_code "reg,subreg,mem")
1075 else if (mode == DImode)
1077 else if (mode == SImode && TARGET_P9_VECTOR)
1079 else if (mode == SFmode && TARGET_P9_VECTOR)
1086 rtx addr = XEXP (op, 0);
1088 if (! volatile_ok && MEM_VOLATILE_P (op))
1091 if (reload_in_progress || lra_in_progress || reload_completed)
1092 return indexed_or_indirect_address (addr, vmode);
1094 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1096 return gpc_reg_operand (op, mode);
1099 ;; Return true if OP is a non-immediate operand and not an invalid
1100 ;; SUBREG operation on the e500.
1101 (define_predicate "rs6000_nonimmediate_operand"
1102 (match_code "reg,subreg,mem")
1104 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1105 && GET_CODE (op) == SUBREG
1106 && invalid_e500_subreg (op, mode))
1109 return nonimmediate_operand (op, mode);
1112 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1113 (define_predicate "rotate_mask_operator"
1114 (match_code "rotate,ashift,lshiftrt"))
1116 ;; Return true if operand is boolean operator.
1117 (define_predicate "boolean_operator"
1118 (match_code "and,ior,xor"))
1120 ;; Return true if operand is OR-form of boolean operator.
1121 (define_predicate "boolean_or_operator"
1122 (match_code "ior,xor"))
1124 ;; Return true if operand is an equality operator.
1125 (define_special_predicate "equality_operator"
1126 (match_code "eq,ne"))
1128 ;; Return 1 if OP is a comparison operation that is valid for a branch
1129 ;; instruction. We check the opcode against the mode of the CC value.
1130 ;; validate_condition_mode is an assertion.
1131 (define_predicate "branch_comparison_operator"
1132 (and (match_operand 0 "comparison_operator")
1133 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1134 (match_test "validate_condition_mode (GET_CODE (op),
1135 GET_MODE (XEXP (op, 0))),
1138 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1139 ;; If we're assuming that FP operations cannot generate user-visible traps,
1140 ;; then on e500 we can use the ordered-signaling instructions to implement
1141 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1142 (define_predicate "rs6000_cbranch_operator"
1143 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1144 (if_then_else (match_test "flag_trapping_math")
1145 (match_operand 0 "ordered_comparison_operator")
1146 (ior (match_operand 0 "ordered_comparison_operator")
1147 (match_code ("unlt,unle,ungt,unge"))))
1148 (match_operand 0 "comparison_operator")))
1150 ;; Return 1 if OP is an unsigned comparison operator.
1151 (define_predicate "unsigned_comparison_operator"
1152 (match_code "ltu,gtu,leu,geu"))
1154 ;; Return 1 if OP is a signed comparison operator.
1155 (define_predicate "signed_comparison_operator"
1156 (match_code "lt,gt,le,ge"))
1158 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1159 ;; it must be a positive comparison.
1160 (define_predicate "scc_comparison_operator"
1161 (and (match_operand 0 "branch_comparison_operator")
1162 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1164 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1166 (define_predicate "scc_rev_comparison_operator"
1167 (and (match_operand 0 "branch_comparison_operator")
1168 (match_code "ne,le,ge,leu,geu,ordered")))
1170 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1171 ;; comparisons that generate a -1/0 mask.
1172 (define_predicate "fpmask_comparison_operator"
1173 (match_code "eq,gt,ge"))
1175 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1176 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1177 ;; fpmask_comparison_operator).
1178 (define_predicate "invert_fpmask_comparison_operator"
1179 (match_code "ne,unlt,unle"))
1181 ;; Return 1 if OP is a comparison operation that is valid for a branch
1182 ;; insn, which is true if the corresponding bit in the CC register is set.
1183 (define_predicate "branch_positive_comparison_operator"
1184 (and (match_operand 0 "branch_comparison_operator")
1185 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1187 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1188 (define_predicate "load_multiple_operation"
1189 (match_code "parallel")
1191 int count = XVECLEN (op, 0);
1192 unsigned int dest_regno;
1196 /* Perform a quick check so we don't blow up below. */
1198 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1199 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1200 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1203 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1204 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1206 for (i = 1; i < count; i++)
1208 rtx elt = XVECEXP (op, 0, i);
1210 if (GET_CODE (elt) != SET
1211 || GET_CODE (SET_DEST (elt)) != REG
1212 || GET_MODE (SET_DEST (elt)) != SImode
1213 || REGNO (SET_DEST (elt)) != dest_regno + i
1214 || GET_CODE (SET_SRC (elt)) != MEM
1215 || GET_MODE (SET_SRC (elt)) != SImode
1216 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1217 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1218 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1219 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1226 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1227 ;; The second vector element is a CLOBBER.
1228 (define_predicate "store_multiple_operation"
1229 (match_code "parallel")
1231 int count = XVECLEN (op, 0) - 1;
1232 unsigned int src_regno;
1236 /* Perform a quick check so we don't blow up below. */
1238 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1239 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1240 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1243 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1244 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1246 for (i = 1; i < count; i++)
1248 rtx elt = XVECEXP (op, 0, i + 1);
1250 if (GET_CODE (elt) != SET
1251 || GET_CODE (SET_SRC (elt)) != REG
1252 || GET_MODE (SET_SRC (elt)) != SImode
1253 || REGNO (SET_SRC (elt)) != src_regno + i
1254 || GET_CODE (SET_DEST (elt)) != MEM
1255 || GET_MODE (SET_DEST (elt)) != SImode
1256 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1257 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1258 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1259 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1266 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1268 (define_predicate "save_world_operation"
1269 (match_code "parallel")
1274 int count = XVECLEN (op, 0);
1280 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1281 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1284 for (i=1; i <= 18; i++)
1286 elt = XVECEXP (op, 0, index++);
1287 if (GET_CODE (elt) != SET
1288 || GET_CODE (SET_DEST (elt)) != MEM
1289 || ! memory_operand (SET_DEST (elt), DFmode)
1290 || GET_CODE (SET_SRC (elt)) != REG
1291 || GET_MODE (SET_SRC (elt)) != DFmode)
1295 for (i=1; i <= 12; i++)
1297 elt = XVECEXP (op, 0, index++);
1298 if (GET_CODE (elt) != SET
1299 || GET_CODE (SET_DEST (elt)) != MEM
1300 || GET_CODE (SET_SRC (elt)) != REG
1301 || GET_MODE (SET_SRC (elt)) != V4SImode)
1305 for (i=1; i <= 19; i++)
1307 elt = XVECEXP (op, 0, index++);
1308 if (GET_CODE (elt) != SET
1309 || GET_CODE (SET_DEST (elt)) != MEM
1310 || ! memory_operand (SET_DEST (elt), Pmode)
1311 || GET_CODE (SET_SRC (elt)) != REG
1312 || GET_MODE (SET_SRC (elt)) != Pmode)
1316 elt = XVECEXP (op, 0, index++);
1317 if (GET_CODE (elt) != SET
1318 || GET_CODE (SET_DEST (elt)) != MEM
1319 || ! memory_operand (SET_DEST (elt), Pmode)
1320 || GET_CODE (SET_SRC (elt)) != REG
1321 || REGNO (SET_SRC (elt)) != CR2_REGNO
1322 || GET_MODE (SET_SRC (elt)) != Pmode)
1325 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1326 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1331 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1333 (define_predicate "restore_world_operation"
1334 (match_code "parallel")
1339 int count = XVECLEN (op, 0);
1345 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1346 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1347 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1348 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1351 elt = XVECEXP (op, 0, index++);
1352 if (GET_CODE (elt) != SET
1353 || GET_CODE (SET_SRC (elt)) != MEM
1354 || ! memory_operand (SET_SRC (elt), Pmode)
1355 || GET_CODE (SET_DEST (elt)) != REG
1356 || REGNO (SET_DEST (elt)) != CR2_REGNO
1357 || GET_MODE (SET_DEST (elt)) != Pmode)
1360 for (i=1; i <= 19; i++)
1362 elt = XVECEXP (op, 0, index++);
1363 if (GET_CODE (elt) != SET
1364 || GET_CODE (SET_SRC (elt)) != MEM
1365 || ! memory_operand (SET_SRC (elt), Pmode)
1366 || GET_CODE (SET_DEST (elt)) != REG
1367 || GET_MODE (SET_DEST (elt)) != Pmode)
1371 for (i=1; i <= 12; i++)
1373 elt = XVECEXP (op, 0, index++);
1374 if (GET_CODE (elt) != SET
1375 || GET_CODE (SET_SRC (elt)) != MEM
1376 || GET_CODE (SET_DEST (elt)) != REG
1377 || GET_MODE (SET_DEST (elt)) != V4SImode)
1381 for (i=1; i <= 18; i++)
1383 elt = XVECEXP (op, 0, index++);
1384 if (GET_CODE (elt) != SET
1385 || GET_CODE (SET_SRC (elt)) != MEM
1386 || ! memory_operand (SET_SRC (elt), DFmode)
1387 || GET_CODE (SET_DEST (elt)) != REG
1388 || GET_MODE (SET_DEST (elt)) != DFmode)
1392 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1393 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1394 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1395 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1396 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1401 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1402 (define_predicate "vrsave_operation"
1403 (match_code "parallel")
1405 int count = XVECLEN (op, 0);
1406 unsigned int dest_regno, src_regno;
1410 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1411 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1412 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1413 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1416 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1417 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1419 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1422 for (i = 1; i < count; i++)
1424 rtx elt = XVECEXP (op, 0, i);
1426 if (GET_CODE (elt) != CLOBBER
1427 && GET_CODE (elt) != SET)
1434 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1435 (define_predicate "mfcr_operation"
1436 (match_code "parallel")
1438 int count = XVECLEN (op, 0);
1441 /* Perform a quick check so we don't blow up below. */
1443 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1444 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1445 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1448 for (i = 0; i < count; i++)
1450 rtx exp = XVECEXP (op, 0, i);
1455 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1457 if (GET_CODE (src_reg) != REG
1458 || GET_MODE (src_reg) != CCmode
1459 || ! CR_REGNO_P (REGNO (src_reg)))
1462 if (GET_CODE (exp) != SET
1463 || GET_CODE (SET_DEST (exp)) != REG
1464 || GET_MODE (SET_DEST (exp)) != SImode
1465 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1467 unspec = SET_SRC (exp);
1468 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1470 if (GET_CODE (unspec) != UNSPEC
1471 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1472 || XVECLEN (unspec, 0) != 2
1473 || XVECEXP (unspec, 0, 0) != src_reg
1474 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1475 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1481 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1482 (define_predicate "mtcrf_operation"
1483 (match_code "parallel")
1485 int count = XVECLEN (op, 0);
1489 /* Perform a quick check so we don't blow up below. */
1491 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1492 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1493 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1495 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1497 if (GET_CODE (src_reg) != REG
1498 || GET_MODE (src_reg) != SImode
1499 || ! INT_REGNO_P (REGNO (src_reg)))
1502 for (i = 0; i < count; i++)
1504 rtx exp = XVECEXP (op, 0, i);
1508 if (GET_CODE (exp) != SET
1509 || GET_CODE (SET_DEST (exp)) != REG
1510 || GET_MODE (SET_DEST (exp)) != CCmode
1511 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1513 unspec = SET_SRC (exp);
1514 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1516 if (GET_CODE (unspec) != UNSPEC
1517 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1518 || XVECLEN (unspec, 0) != 2
1519 || XVECEXP (unspec, 0, 0) != src_reg
1520 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1521 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1527 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1528 (define_predicate "crsave_operation"
1529 (match_code "parallel")
1531 int count = XVECLEN (op, 0);
1534 for (i = 1; i < count; i++)
1536 rtx exp = XVECEXP (op, 0, i);
1538 if (GET_CODE (exp) != USE
1539 || GET_CODE (XEXP (exp, 0)) != REG
1540 || GET_MODE (XEXP (exp, 0)) != CCmode
1541 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1547 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1548 (define_predicate "lmw_operation"
1549 (match_code "parallel")
1551 int count = XVECLEN (op, 0);
1552 unsigned int dest_regno;
1554 unsigned int base_regno;
1555 HOST_WIDE_INT offset;
1558 /* Perform a quick check so we don't blow up below. */
1560 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1561 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1562 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1565 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1566 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1569 || count != 32 - (int) dest_regno)
1572 if (legitimate_indirect_address_p (src_addr, 0))
1575 base_regno = REGNO (src_addr);
1576 if (base_regno == 0)
1579 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1581 offset = INTVAL (XEXP (src_addr, 1));
1582 base_regno = REGNO (XEXP (src_addr, 0));
1587 for (i = 0; i < count; i++)
1589 rtx elt = XVECEXP (op, 0, i);
1592 HOST_WIDE_INT newoffset;
1594 if (GET_CODE (elt) != SET
1595 || GET_CODE (SET_DEST (elt)) != REG
1596 || GET_MODE (SET_DEST (elt)) != SImode
1597 || REGNO (SET_DEST (elt)) != dest_regno + i
1598 || GET_CODE (SET_SRC (elt)) != MEM
1599 || GET_MODE (SET_SRC (elt)) != SImode)
1601 newaddr = XEXP (SET_SRC (elt), 0);
1602 if (legitimate_indirect_address_p (newaddr, 0))
1607 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1609 addr_reg = XEXP (newaddr, 0);
1610 newoffset = INTVAL (XEXP (newaddr, 1));
1614 if (REGNO (addr_reg) != base_regno
1615 || newoffset != offset + 4 * i)
1622 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1623 (define_predicate "stmw_operation"
1624 (match_code "parallel")
1626 int count = XVECLEN (op, 0);
1627 unsigned int src_regno;
1629 unsigned int base_regno;
1630 HOST_WIDE_INT offset;
1633 /* Perform a quick check so we don't blow up below. */
1635 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1636 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1637 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1640 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1641 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1644 || count != 32 - (int) src_regno)
1647 if (legitimate_indirect_address_p (dest_addr, 0))
1650 base_regno = REGNO (dest_addr);
1651 if (base_regno == 0)
1654 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1656 offset = INTVAL (XEXP (dest_addr, 1));
1657 base_regno = REGNO (XEXP (dest_addr, 0));
1662 for (i = 0; i < count; i++)
1664 rtx elt = XVECEXP (op, 0, i);
1667 HOST_WIDE_INT newoffset;
1669 if (GET_CODE (elt) != SET
1670 || GET_CODE (SET_SRC (elt)) != REG
1671 || GET_MODE (SET_SRC (elt)) != SImode
1672 || REGNO (SET_SRC (elt)) != src_regno + i
1673 || GET_CODE (SET_DEST (elt)) != MEM
1674 || GET_MODE (SET_DEST (elt)) != SImode)
1676 newaddr = XEXP (SET_DEST (elt), 0);
1677 if (legitimate_indirect_address_p (newaddr, 0))
1682 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1684 addr_reg = XEXP (newaddr, 0);
1685 newoffset = INTVAL (XEXP (newaddr, 1));
1689 if (REGNO (addr_reg) != base_regno
1690 || newoffset != offset + 4 * i)
1697 ;; Return 1 if OP is a stack tie operand.
1698 (define_predicate "tie_operand"
1699 (match_code "parallel")
1701 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1702 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1703 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1704 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1707 ;; Match a small code model toc reference (or medium and large
1708 ;; model toc references before reload).
1709 (define_predicate "small_toc_ref"
1710 (match_code "unspec,plus")
1712 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1715 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1718 ;; Match the TOC memory operand that can be fused with an addis instruction.
1719 ;; This is used in matching a potential fused address before register
1721 (define_predicate "toc_fusion_mem_raw"
1724 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1727 return small_toc_ref (XEXP (op, 0), Pmode);
1730 ;; Match the memory operand that has been fused with an addis instruction and
1731 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1732 (define_predicate "toc_fusion_mem_wrapped"
1737 if (!TARGET_TOC_FUSION_INT)
1743 addr = XEXP (op, 0);
1744 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1747 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1748 ;; GPR registers on power8.
1749 (define_predicate "fusion_gpr_addis"
1750 (match_code "const_int,high,plus")
1752 HOST_WIDE_INT value;
1755 if (GET_CODE (op) == HIGH)
1758 if (CONST_INT_P (op))
1761 else if (GET_CODE (op) == PLUS
1762 && base_reg_operand (XEXP (op, 0), Pmode)
1763 && CONST_INT_P (XEXP (op, 1)))
1764 int_const = XEXP (op, 1);
1769 value = INTVAL (int_const);
1770 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1773 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1776 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1777 value are all 1's or 0's. Ignore this restriction if we are testing
1779 if (TARGET_P9_FUSION)
1782 return (IN_RANGE (value >> 16, -32, 31));
1785 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1786 ;; and loads to GPR registers on power8.
1787 (define_predicate "fusion_gpr_mem_load"
1788 (match_code "mem,sign_extend,zero_extend")
1790 rtx addr, base, offset;
1792 /* Handle sign/zero extend. */
1793 if (GET_CODE (op) == ZERO_EXTEND
1794 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1797 mode = GET_MODE (op);
1811 if (!TARGET_POWERPC64)
1819 addr = XEXP (op, 0);
1820 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1823 base = XEXP (addr, 0);
1824 if (!base_reg_operand (base, GET_MODE (base)))
1827 offset = XEXP (addr, 1);
1829 if (GET_CODE (addr) == PLUS)
1830 return satisfies_constraint_I (offset);
1832 else if (GET_CODE (addr) == LO_SUM)
1834 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1835 return small_toc_ref (offset, GET_MODE (offset));
1837 else if (TARGET_ELF && !TARGET_POWERPC64)
1838 return CONSTANT_P (offset);
1844 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1845 ;; memory field with both the addis and the memory offset. Sign extension
1846 ;; is not handled here, since lha and lwa are not fused.
1847 ;; With extended fusion, also match a FPR load (lfd, lfs) and float_extend
1848 (define_predicate "fusion_addis_mem_combo_load"
1849 (match_code "mem,zero_extend,float_extend")
1851 rtx addr, base, offset;
1853 /* Handle zero/float extend. */
1854 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1857 mode = GET_MODE (op);
1871 if (!TARGET_POWERPC64)
1877 if (!TARGET_P9_FUSION)
1885 addr = XEXP (op, 0);
1886 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1889 base = XEXP (addr, 0);
1890 if (!fusion_gpr_addis (base, GET_MODE (base)))
1893 offset = XEXP (addr, 1);
1894 if (GET_CODE (addr) == PLUS)
1895 return satisfies_constraint_I (offset);
1897 else if (GET_CODE (addr) == LO_SUM)
1899 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1900 return small_toc_ref (offset, GET_MODE (offset));
1902 else if (TARGET_ELF && !TARGET_POWERPC64)
1903 return CONSTANT_P (offset);
1909 ;; Like fusion_addis_mem_combo_load, but for stores
1910 (define_predicate "fusion_addis_mem_combo_store"
1913 rtx addr, base, offset;
1915 if (!MEM_P (op) || !TARGET_P9_FUSION)
1926 if (!TARGET_POWERPC64)
1944 addr = XEXP (op, 0);
1945 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1948 base = XEXP (addr, 0);
1949 if (!fusion_gpr_addis (base, GET_MODE (base)))
1952 offset = XEXP (addr, 1);
1953 if (GET_CODE (addr) == PLUS)
1954 return satisfies_constraint_I (offset);
1956 else if (GET_CODE (addr) == LO_SUM)
1958 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1959 return small_toc_ref (offset, GET_MODE (offset));
1961 else if (TARGET_ELF && !TARGET_POWERPC64)
1962 return CONSTANT_P (offset);
1968 ;; Return true if the operand is a float_extend or zero extend of an
1969 ;; offsettable memory operand suitable for use in fusion
1970 (define_predicate "fusion_offsettable_mem_operand"
1971 (match_code "mem,zero_extend,float_extend")
1973 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1976 mode = GET_MODE (op);
1979 if (!memory_operand (op, mode))
1982 return offsettable_nonstrict_memref_p (op);