riscv: riscv-cores.def: Add T-Head XuanTie C906
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / mcpu-thead-c906.c
bloba71b43a61672cdc2a7827e3234b90cceda6d6159
1 /* { dg-do compile } */
2 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
3 /* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
4 /* T-Head XuanTie C906 => rv64imafdc */
6 #if !((__riscv_xlen == 64) \
7 && !defined(__riscv_32e) \
8 && defined(__riscv_mul) \
9 && defined(__riscv_atomic) \
10 && (__riscv_flen == 64) \
11 && defined(__riscv_compressed) \
12 && defined(__riscv_xtheadba) \
13 && defined(__riscv_xtheadbb) \
14 && defined(__riscv_xtheadbs) \
15 && defined(__riscv_xtheadcmo) \
16 && defined(__riscv_xtheadcondmov) \
17 && defined(__riscv_xtheadfmemidx) \
18 && defined(__riscv_xtheadmac) \
19 && defined(__riscv_xtheadmemidx) \
20 && defined(__riscv_xtheadmempair) \
21 && defined(__riscv_xtheadsync))
22 #error "unexpected arch"
23 #endif
25 int main()
27 return 0;