| blob | b3c55170927c0eb9feb9dba1e271849617302cdb |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
251 #if 0
253 #endif
294 rtx *);
355 {
356 rtx match;
357 rtx replacement;
358 rtx insn;
361 /* Nonzero iff INSN is between START and END, inclusive. */
362 #define INSN_IN_RANGE_P(INSN, START, END) \
363 (INSN_UID (INSN) < max_uid_for_loop \
364 && INSN_LUID (INSN) >= INSN_LUID (START) \
365 && INSN_LUID (INSN) <= INSN_LUID (END))
367 /* Indirect_jump_in_function is computed once per function. */
375 \f
376 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
377 copy the value of the strength reduced giv to its original register. */
380 /* Cost of using a register, to normalize the benefits of a giv. */
383 void
385 {
391 }
392 \f
393 /* Compute the mapping from uids to luids.
394 LUIDs are numbers assigned to insns, like uids,
395 except that luids increase monotonically through the code.
396 Start at insn START and stop just before END. Assign LUIDs
397 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
398 static int
400 {
402 rtx insn;
405 {
408 /* Don't assign luids to line-number NOTEs, so that the distance in
409 luids between two insns is not affected by -g. */
413 else
414 /* Give a line number note the same luid as preceding insn. */
416 }
418 }
419 \f
420 /* Entry point of this file. Perform loop optimization
421 on the current function. F is the first insn of the function
422 and DUMPFILE is a stream for output of a trace of actions taken
423 (or 0 if none should be output). */
425 void
427 {
428 rtx insn;
443 /* Count the number of loops. */
447 {
450 max_loop_num++;
451 }
453 /* Don't waste time if no loops. */
459 /* Get size to use for tables indexed by uids.
460 Leave some space for labels allocated by find_and_verify_loops. */
467 /* Allocate storage for array of loops. */
471 /* Find and process each loop.
472 First, find them, and record them in order of their beginnings. */
475 /* Allocate and initialize auxiliary loop information. */
480 /* Now find all register lifetimes. This must be done after
481 find_and_verify_loops, because it might reorder the insns in the
482 function. */
485 /* This must occur after reg_scan so that registers created by gcse
486 will have entries in the register tables.
488 We could have added a call to reg_scan after gcse_main in toplev.c,
489 but moving this call to init_alias_analysis is more efficient. */
492 /* See if we went too far. Note that get_max_uid already returns
493 one more that the maximum uid of all insn. */
496 /* Now reset it to the actual size we need. See above. */
499 /* find_and_verify_loops has already called compute_luids, but it
500 might have rearranged code afterwards, so we need to recompute
501 the luids now. */
504 /* Don't leave gaps in uid_luid for insns that have been
505 deleted. It is possible that the first or last insn
506 using some register has been deleted by cross-jumping.
507 Make sure that uid_luid for that former insn's uid
508 points to the general area where that insn used to be. */
510 {
514 }
519 /* Determine if the function has indirect jump. On some systems
520 this prevents low overhead loop instructions from being used. */
523 /* Now scan the loops, last ones first, since this means inner ones are done
524 before outer ones. */
526 {
531 }
535 /* Clean up. */
540 }
541 \f
542 /* Returns the next insn, in execution order, after INSN. START and
543 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
544 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
545 insn-stream; it is used with loops that are entered near the
546 bottom. */
548 static rtx
550 {
554 {
556 /* Go to the top of the loop, and continue there. */
558 else
559 /* We're done. */
561 }
564 /* We're done. */
568 }
570 /* Optimize one loop described by LOOP. */
572 /* ??? Could also move memory writes out of loops if the destination address
573 is invariant, the source is invariant, the memory write is not volatile,
574 and if we can prove that no read inside the loop can read this address
575 before the write occurs. If there is a read of this address after the
576 write, then we can also mark the memory read as invariant. */
578 static void
580 {
586 rtx p;
587 /* 1 if we are scanning insns that could be executed zero times. */
589 /* 1 if we are scanning insns that might never be executed
590 due to a subroutine call which might exit before they are reached. */
592 /* Number of insns in the loop. */
596 /* The SET from an insn, if it is the only SET in the insn. */
598 /* Chain describing insns movable in current loop. */
600 /* Ratio of extra register life span we can justify
601 for saving an instruction. More if loop doesn't call subroutines
602 since in that case saving an insn makes more difference
603 and more registers are available. */
605 /* Nonzero if we are scanning instructions in a sub-loop. */
614 /* Determine whether this loop starts with a jump down to a test at
615 the end. This will occur for a small number of loops with a test
616 that is too complex to duplicate in front of the loop.
618 We search for the first insn or label in the loop, skipping NOTEs.
619 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
620 (because we might have a loop executed only once that contains a
621 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
622 (in case we have a degenerate loop).
624 Note that if we mistakenly think that a loop is entered at the top
625 when, in fact, it is entered at the exit test, the only effect will be
626 slightly poorer optimization. Making the opposite error can generate
627 incorrect code. Since very few loops now start with a jump to the
628 exit test, the code here to detect that case is very conservative. */
631 p != loop_end
637 ;
641 /* If loop end is the end of the current function, then emit a
642 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
643 note insn. This is the position we use when sinking insns out of
644 the loop. */
647 else
650 /* Set up variables describing this loop. */
654 /* If loop has a jump before the first label,
655 the true entry is the target of that jump.
656 Start scan from there.
657 But record in LOOP->TOP the place where the end-test jumps
658 back to so we can scan that after the end of the loop. */
660 /* Loop entry must be unconditional jump (and not a RETURN) */
663 /* Check to see whether the jump actually
664 jumps out of the loop (meaning it's no loop).
665 This case can happen for things like
666 do {..} while (0). If this label was generated previously
667 by loop, we can't tell anything about it and have to reject
668 the loop. */
670 {
673 }
675 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
676 as required by loop_reg_used_before_p. So skip such loops. (This
677 test may never be true, but it's best to play it safe.)
679 Also, skip loops where we do not start scanning at a label. This
680 test also rejects loops starting with a JUMP_INSN that failed the
681 test above. */
685 {
690 }
692 /* Allocate extra space for REGs that might be created by load_mems.
693 We allocate a little extra slop as well, in the hopes that we
694 won't have to reallocate the regs array. */
699 {
705 }
707 /* Scan through the loop finding insns that are safe to move.
708 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
709 this reg will be considered invariant for subsequent insns.
710 We consider whether subsequent insns use the reg
711 in deciding whether it is worth actually moving.
713 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
714 and therefore it is possible that the insns we are scanning
715 would never be executed. At such times, we must make sure
716 that it is safe to execute the insn once instead of zero times.
717 When MAYBE_NEVER is 0, all insns will be executed at least once
718 so that is not a problem. */
723 {
725 in_libcall--;
727 {
730 in_libcall++;
734 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
736 #endif
738 {
746 /* Figure out what to use as a source of this insn. If a
747 REG_EQUIV note is given or if a REG_EQUAL note with a
748 constant operand is specified, use it as the source and
749 mark that we should move this insn by calling
750 emit_move_insn rather that duplicating the insn.
752 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
753 note is present. */
757 else
758 {
763 {
765 /* A libcall block can use regs that don't appear in
766 the equivalent expression. To move the libcall,
767 we must move those regs too. */
769 }
770 }
772 /* For parallels, add any possible uses to the dependencies, as
773 we can't move the insn without resolving them first. */
775 {
777 {
780 dependencies
782 dependencies);
783 }
784 }
787 than the one where it is set (meaning that
788 something after this point in the loop might
789 depend on its value before the set). */
791 /* And the set is not guaranteed to be executed once
792 the loop starts, or the value before the set is
793 needed before the set occurs...
795 ??? Note we have quadratic behavior here, mitigated
796 by the fact that the previous test will often fail for
797 large loops. Rather than re-scanning the entire loop
798 each time for register usage, we should build tables
799 of the register usage and use them here instead. */
800 && (maybe_never
802 /* It is unsafe to move the set. However, it may be OK to
803 move the source into a new pseudo, and substitute a
804 reg-to-reg copy for the original insn.
806 This code used to consider it OK to move a set of a variable
807 which was not created by the user and not used in an exit
808 test.
809 That behavior is incorrect and was removed. */
812 /* Don't try to optimize a MODE_CC set with a constant
813 source. It probably will be combined with a conditional
814 jump. */
817 ;
818 /* Don't try to optimize a register that was made
819 by loop-optimization for an inner loop.
820 We don't know its life-span, so we can't compute
821 the benefit. */
823 ;
824 /* Don't move the source and add a reg-to-reg copy:
825 - with -Os (this certainly increases size),
826 - if the mode doesn't support copy operations (obviously),
827 - if the source is already a reg (the motion will gain nothing),
828 - if the source is a legitimate constant (likewise). */
830 && (optimize_size
835 ;
838 || (tem2
841 || (tem1
842 = consec_sets_invariant_p
845 p)))
846 /* If the insn can cause a trap (such as divide by zero),
847 can't move it unless it's guaranteed to be executed
848 once loop is entered. Even a function call might
849 prevent the trap insn from being reached
850 (since it might exit!) */
853 {
857 /* A potential lossage is where we have a case where two insns
858 can be combined as long as they are both in the loop, but
859 we move one of them outside the loop. For large loops,
860 this can lose. The most common case of this is the address
861 of a function being called.
863 Therefore, if this register is marked as being used
864 exactly once if we are in a loop with calls
865 (a "large loop"), see if we can replace the usage of
866 this register with the source of this SET. If we can,
867 delete this insn.
869 Don't do this if P has a REG_RETVAL note or if we have
870 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
882 && (! SMALL_REGISTER_CLASSES
886 /* This test is not redundant; SET_SRC (set) might be
887 a call-clobbered register and the life of REGNO
888 might span a call. */
895 {
896 /* Replace any usage in a REG_EQUAL note. Must copy
897 the new source, so that we don't get rtx sharing
898 between the SET_SOURCE and REG_NOTES of insn p. */
900 = (replace_rtx
906 i++)
909 }
918 m->consec
929 /* Set M->cond if either loop_invariant_p
930 or consec_sets_invariant_p returned 2
931 (only conditionally invariant). */
941 /* Add M to the end of the chain MOVABLES. */
945 {
946 /* It is possible for the first instruction to have a
947 REG_EQUAL note but a non-invariant SET_SRC, so we must
948 remember the status of the first instruction in case
949 the last instruction doesn't have a REG_EQUAL note. */
952 /* Skip this insn, not checking REG_LIBCALL notes. */
954 /* Skip the consecutive insns, if there are any. */
956 /* Back up to the last insn of the consecutive group. */
959 /* We must now reset m->move_insn, m->is_equiv, and
960 possibly m->set_src to correspond to the effects of
961 all the insns. */
965 else
966 {
970 else
973 }
974 m->is_equiv
976 }
977 }
978 /* If this register is always set within a STRICT_LOW_PART
979 or set to zero, then its high bytes are constant.
980 So clear them outside the loop and within the loop
981 just load the low bytes.
982 We must check that the machine has an instruction to do so.
983 Also, if the value loaded into the register
984 depends on the same register, this cannot be done. */
994 {
997 {
1012 /* If the insn may not be executed on some cycles,
1013 we can't clear the whole reg; clear just high part.
1014 Not even if the reg is used only within this loop.
1015 Consider this:
1016 while (1)
1017 while (s != t) {
1018 if (foo ()) x = *s;
1019 use (x);
1020 }
1021 Clearing x before the inner loop could clobber a value
1022 being saved from the last time around the outer loop.
1023 However, if the reg is not used outside this loop
1024 and all uses of the register are in the same
1025 basic block as the store, there is no problem.
1027 If this insn was made by loop, we don't know its
1028 INSN_LUID and hence must make a conservative
1029 assumption. */
1032 || (labels_in_range_p
1036 else
1045 i++)
1047 /* Add M to the end of the chain MOVABLES. */
1049 }
1050 }
1051 }
1052 }
1053 /* Past a call insn, we get to insns which might not be executed
1054 because the call might exit. This matters for insns that trap.
1055 Constant and pure call insns always return, so they don't count. */
1058 /* Past a label or a jump, we get to insns for which we
1059 can't count on whether or how many times they will be
1060 executed during each iteration. Therefore, we can
1061 only move out sets of trivial variables
1062 (those not used after the loop). */
1063 /* Similar code appears twice in strength_reduce. */
1065 /* If we enter the loop in the middle, and scan around to the
1066 beginning, don't set maybe_never for that. This must be an
1067 unconditional jump, otherwise the code at the top of the
1068 loop might never be executed. Unconditional jumps are
1069 followed by a barrier then the loop_end. */
1075 {
1076 /* At the virtual top of a converted loop, insns are again known to
1077 be executed: logically, the loop begins here even though the exit
1078 code has been duplicated. */
1082 loop_depth++;
1084 loop_depth--;
1085 }
1086 }
1088 /* If one movable subsumes another, ignore that other. */
1092 /* For each movable insn, see if the reg that it loads
1093 leads when it dies right into another conditionally movable insn.
1094 If so, record that the second insn "forces" the first one,
1095 since the second can be moved only if the first is. */
1099 /* See if there are multiple movable insns that load the same value.
1100 If there are, make all but the first point at the first one
1101 through the `match' field, and add the priorities of them
1102 all together as the priority of the first. */
1106 /* Now consider each movable insn to decide whether it is worth moving.
1107 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1109 For machines with few registers this increases code size, so do not
1110 move moveables when optimizing for code size on such machines.
1111 (The 18 below is the value for i386.) */
1115 {
1118 /* Recalculate regs->array if move_movables has created new
1119 registers. */
1121 {
1127 ;
1132 }
1133 }
1135 /* Now candidates that still are negative are those not moved.
1136 Change regs->array[I].set_in_loop to indicate that those are not actually
1137 invariant. */
1142 /* Now that we've moved some things out of the loop, we might be able to
1143 hoist even more memory references. */
1146 /* Recalculate regs->array if load_mems has created new registers. */
1154 ;
1161 {
1163 /* Ensure our label doesn't go away. */
1174 }
1177 /* The movable information is required for strength reduction. */
1183 }
1184 \f
1185 /* Add elements to *OUTPUT to record all the pseudo-regs
1186 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1188 void
1190 {
1198 {
1216 }
1220 {
1224 {
1233 }
1234 }
1235 }
1236 \f
1237 /* Check what regs are referred to in the libcall block ending with INSN,
1238 aside from those mentioned in the equivalent value.
1239 If there are none, return 0.
1240 If there are one or more, return an EXPR_LIST containing all of them. */
1242 rtx
1244 {
1249 /* First, find all the regs used in the libcall block
1250 that are not mentioned as inputs to the result. */
1253 {
1258 }
1261 }
1262 \f
1263 /* Return 1 if all uses of REG
1264 are between INSN and the end of the basic block. */
1266 static int
1268 {
1270 rtx p;
1275 /* Search this basic block for the already recorded last use of the reg. */
1277 {
1279 {
1285 /* Ordinary insn: if this is the last use, we win. */
1291 /* Jump insn: if this is the last use, we win. */
1294 /* Otherwise, it's the end of the basic block, so we lose. */
1299 /* It's the end of the basic block, so we lose. */
1304 }
1305 }
1307 /* The "last use" that was recorded can't be found after the first
1308 use. This can happen when the last use was deleted while
1309 processing an inner loop, this inner loop was then completely
1310 unrolled, and the outer loop is always exited after the inner loop,
1311 so that everything after the first use becomes a single basic block. */
1313 }
1314 \f
1315 /* Compute the benefit of eliminating the insns in the block whose
1316 last insn is LAST. This may be a group of insns used to compute a
1317 value directly or can contain a library call. */
1319 static int
1321 {
1322 rtx insn;
1327 {
1330 routine. */
1334 benefit++;
1335 }
1338 }
1339 \f
1340 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1342 static rtx
1344 {
1346 {
1347 rtx temp;
1349 /* If first insn of libcall sequence, skip to end. */
1350 /* Do this at start of loop, since INSN is guaranteed to
1351 be an insn here. */
1356 do
1359 }
1362 }
1364 /* Ignore any movable whose insn falls within a libcall
1365 which is part of another movable.
1366 We make use of the fact that the movable for the libcall value
1367 was made later and so appears later on the chain. */
1369 static void
1371 {
1375 {
1376 /* Is this a movable for the value of a libcall? */
1379 {
1380 rtx insn;
1381 /* Check for earlier movables inside that range,
1382 and mark them invalid. We cannot use LUIDs here because
1383 insns created by loop.c for prior loops don't have LUIDs.
1384 Rather than reject all such insns from movables, we just
1385 explicitly check each insn in the libcall (since invariant
1386 libcalls aren't that common). */
1391 }
1392 }
1393 }
1395 /* For each movable insn, see if the reg that it loads
1396 leads when it dies right into another conditionally movable insn.
1397 If so, record that the second insn "forces" the first one,
1398 since the second can be moved only if the first is. */
1400 static void
1402 {
1406 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1408 {
1411 /* ??? Could this be a bug? What if CSE caused the
1412 register of M1 to be used after this insn?
1413 Since CSE does not update regno_last_uid,
1414 this insn M->insn might not be where it dies.
1415 But very likely this doesn't matter; what matters is
1416 that M's reg is computed from M1's reg. */
1421 /* If m->consec, m->set_src isn't valid. */
1425 /* Increase the priority of the moving the first insn
1426 since it permits the second to be moved as well. */
1428 {
1432 }
1433 }
1434 }
1435 \f
1436 /* Find invariant expressions that are equal and can be combined into
1437 one register. */
1439 static void
1441 {
1446 /* Regs that are set more than once are not allowed to match
1447 or be matched. I'm no longer sure why not. */
1448 /* Only pseudo registers are allowed to match or be matched,
1449 since move_movables does not validate the change. */
1450 /* Perhaps testing m->consec_sets would be more appropriate here? */
1457 {
1464 /* We want later insns to match the first one. Don't make the first
1465 one match any later ones. So start this loop at m->next. */
1471 /* A reg used outside the loop mustn't be eliminated. */
1473 /* A reg used for zero-extending mustn't be eliminated. */
1476 ||
1477 (
1478 /* Can combine regs with different modes loaded from the
1479 same constant only if the modes are the same or
1480 if both are integer modes with M wider or the same
1481 width as M1. The check for integer is redundant, but
1482 safe, since the only case of differing destination
1483 modes with equal sources is when both sources are
1484 VOIDmode, i.e., CONST_INT. */
1490 /* See if the source of M1 says it matches M. */
1497 {
1503 }
1504 }
1506 /* Now combine the regs used for zero-extension.
1507 This can be done for those not marked `global'
1508 provided their lives don't overlap. */
1512 {
1515 /* Combine all the registers for extension from mode MODE.
1516 Don't combine any that are used outside this loop. */
1520 {
1527 {
1528 /* First one: don't check for overlap, just record it. */
1531 }
1533 /* Make sure they extend to the same mode.
1534 (Almost always true.) */
1538 /* We already have one: check for overlap with those
1539 already combined together. */
1546 /* No overlap: we can combine this with the others. */
1552 overlap:
1553 ;
1554 }
1555 }
1557 /* Clean up. */
1559 }
1561 /* Returns the number of movable instructions in LOOP that were not
1562 moved outside the loop. */
1564 static int
1566 {
1575 }
1577 \f
1578 /* Return 1 if regs X and Y will become the same if moved. */
1580 static int
1582 {
1599 }
1601 /* Return 1 if X and Y are identical-looking rtx's.
1602 This is the Lisp function EQUAL for rtx arguments.
1604 If two registers are matching movables or a movable register and an
1605 equivalent constant, consider them equal. */
1607 static int
1610 {
1624 /* If we have a register and a constant, they may sometimes be
1625 equal. */
1628 {
1633 }
1636 {
1641 }
1643 /* Otherwise, rtx's of different codes cannot be equal. */
1647 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1648 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1653 /* These three types of rtx's can be compared nonrecursively. */
1662 /* Compare the elements. If any pair of corresponding elements
1663 fail to match, return 0 for the whole things. */
1667 {
1669 {
1681 /* Two vectors must have the same length. */
1685 /* And the corresponding elements must match. */
1704 /* These are just backpointers, so they don't matter. */
1710 /* It is believed that rtx's at this level will never
1711 contain anything but integers and other rtx's,
1712 except for within LABEL_REFs and SYMBOL_REFs. */
1715 }
1716 }
1718 }
1719 \f
1720 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1721 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1722 references is incremented once for each added note. */
1724 static void
1726 {
1730 rtx insn;
1733 {
1734 /* This code used to ignore labels that referred to dispatch tables to
1735 avoid flow generating (slightly) worse code.
1737 We no longer ignore such label references (see LABEL_REF handling in
1738 mark_jump_label for additional information). */
1741 {
1746 }
1747 }
1751 {
1757 }
1758 }
1759 \f
1760 /* Scan MOVABLES, and move the insns that deserve to be moved.
1761 If two matching movables are combined, replace one reg with the
1762 other throughout. */
1764 static void
1767 {
1772 rtx p;
1775 /* Map of pseudo-register replacements to handle combining
1776 when we move several insns that load the same value
1777 into different pseudo-registers. */
1782 {
1783 /* Describe this movable insn. */
1786 {
1807 }
1809 /* Ignore the insn if it's already done (it matched something else).
1810 Otherwise, see if it is now safe to move. */
1822 {
1824 rtx p;
1827 /* We have an insn that is safe to move.
1828 Compute its desirability. */
1839 /* An insn MUST be moved if we already moved something else
1840 which is safe only if this one is moved too: that is,
1841 if already_moved[REGNO] is nonzero. */
1843 /* An insn is desirable to move if the new lifetime of the
1844 register is no more than THRESHOLD times the old lifetime.
1845 If it's not desirable, it means the loop is so big
1846 that moving won't speed things up much,
1847 and it is liable to make register usage worse. */
1849 /* It is also desirable to move if it can be moved at no
1850 extra cost because something else was already moved. */
1853 || flag_move_all_movables
1858 {
1867 /* Now move the insns that set the reg. */
1870 {
1873 /* Find the end of this chain of matching regs.
1874 Thus, we load each reg in the chain from that one reg.
1875 And that reg is loaded with 0 directly,
1876 since it has ->match == 0. */
1882 /* Mark the moved, invariant reg as being allowed to
1883 share a hard reg with the other matching invariant. */
1887 regs_may_share
1890 regs_may_share));
1898 }
1899 /* If we are to re-generate the item being moved with a
1900 new move insn, first delete what we have and then emit
1901 the move insn before the loop. */
1903 {
1907 {
1908 /* If this is the first insn of a library call sequence,
1909 something is very wrong. */
1914 /* If this is the last insn of a libcall sequence, then
1915 delete every insn in the sequence except the last.
1916 The last insn is handled in the normal manner. */
1919 {
1923 }
1928 /* simplify_giv_expr expects that it can walk the insns
1929 at m->insn forwards and see this old sequence we are
1930 tossing here. delete_insn does preserve the next
1931 pointers, but when we skip over a NOTE we must fix
1932 it up. Otherwise that code walks into the non-deleted
1933 insn stream. */
1938 {
1939 /* Replace the original insn with a move from
1940 our newly created temp. */
1946 }
1947 }
1966 /* The more regs we move, the less we like moving them. */
1968 }
1969 else
1970 {
1972 {
1975 /* If first insn of libcall sequence, skip to end. */
1976 /* Do this at start of loop, since p is guaranteed to
1977 be an insn here. */
1982 /* If last insn of libcall sequence, move all
1983 insns except the last before the loop. The last
1984 insn is handled in the normal manner. */
1987 {
1995 {
1996 rtx body;
1997 rtx n;
1998 rtx next;
2005 /* Find the next insn after TEMP,
2006 not counting USE or NOTE insns. */
2014 /* If that is the call, this may be the insn
2015 that loads the function address.
2017 Extract the function address from the insn
2018 that loads it into a register.
2019 If this insn was cse'd, we get incorrect code.
2021 So emit a new move insn that copies the
2022 function address into the register that the
2023 call insn will use. flow.c will delete any
2024 redundant stores that we have created. */
2029 NULL_RTX)))
2030 {
2036 }
2037 /* We have the call insn.
2038 If it uses the register we suspect it might,
2039 load it with the correct address directly. */
2044 gen_move_insn
2048 {
2050 /* Because the USAGE information potentially
2051 contains objects other than hard registers
2052 we need to copy it. */
2056 }
2057 else
2066 }
2069 }
2071 {
2072 /* P sets REG to zero; but we should clear only
2073 the bits that are not covered by the mode
2074 m->savemode. */
2076 rtx sequence;
2077 rtx tem;
2080 tem = expand_simple_binop
2093 }
2095 {
2097 /* Because the USAGE information potentially
2098 contains objects other than hard registers
2099 we need to copy it. */
2103 }
2105 {
2106 rtx seq;
2107 /* The SET_SRC might not be invariant, so we must
2108 use the REG_EQUAL note. */
2120 }
2122 {
2130 }
2131 else
2135 {
2139 /* If there is a REG_EQUAL note present whose value
2140 is not loop invariant, then delete it, since it
2141 may cause problems with later optimization passes.
2142 It is possible for cse to create such notes
2143 like this as a result of record_jump_cond. */
2148 }
2157 /* If library call, now fix the REG_NOTES that contain
2158 insn pointers, namely REG_LIBCALL on FIRST
2159 and REG_RETVAL on I1. */
2161 {
2165 }
2171 /* simplify_giv_expr expects that it can walk the insns
2172 at m->insn forwards and see this old sequence we are
2173 tossing here. delete_insn does preserve the next
2174 pointers, but when we skip over a NOTE we must fix
2175 it up. Otherwise that code walks into the non-deleted
2176 insn stream. */
2181 {
2182 rtx seq;
2183 /* Replace the original insn with a move from
2184 our newly created temp. */
2190 }
2191 }
2193 /* The more regs we move, the less we like moving them. */
2195 }
2200 {
2201 /* Any other movable that loads the same register
2202 MUST be moved. */
2205 /* This reg has been moved out of one loop. */
2208 /* The reg set here is now invariant. */
2210 {
2214 }
2216 /* Change the length-of-life info for the register
2217 to say it lives at least the full length of this loop.
2218 This will help guide optimizations in outer loops. */
2221 /* This is the old insn before all the moved insns.
2222 We can't use the moved insn because it is out of range
2223 in uid_luid. Only the old insns have luids. */
2227 }
2229 /* Combine with this moved insn any other matching movables. */
2234 {
2235 rtx temp;
2237 /* Schedule the reg loaded by M1
2238 for replacement so that shares the reg of M.
2239 If the modes differ (only possible in restricted
2240 circumstances, make a SUBREG.
2242 Note this assumes that the target dependent files
2243 treat REG and SUBREG equally, including within
2244 GO_IF_LEGITIMATE_ADDRESS and in all the
2245 predicates since we never verify that replacing the
2246 original register with a SUBREG results in a
2247 recognizable insn. */
2250 else
2255 /* Get rid of the matching insn
2256 and prevent further processing of it. */
2259 /* if library call, delete all insns. */
2261 NULL_RTX)))
2263 else
2266 /* Any other movable that loads the same register
2267 MUST be moved. */
2270 /* The reg merged here is now invariant,
2271 if the reg it matches is invariant. */
2273 {
2277 i++)
2279 }
2280 }
2281 }
2284 }
2290 }
2295 /* Go through all the instructions in the loop, making
2296 all the register substitutions scheduled in REG_MAP. */
2300 {
2304 }
2306 /* Clean up. */
2309 }
2312 static void
2314 {
2317 else
2320 }
2323 static void
2325 {
2330 {
2333 }
2334 }
2335 \f
2336 #if 0
2337 /* Scan X and replace the address of any MEM in it with ADDR.
2338 REG is the address that MEM should have before the replacement. */
2340 static void
2342 {
2351 {
2363 /* Short cut for very common case. */
2368 /* Short cut for very common case. */
2373 /* If this MEM uses a reg other than the one we expected,
2374 something is wrong. */
2382 }
2386 {
2390 {
2394 }
2395 }
2396 }
2397 #endif
2398 \f
2399 /* Return the number of memory refs to addresses that vary
2400 in the rtx X. */
2402 static int
2404 {
2415 {
2432 }
2437 {
2441 {
2445 }
2446 }
2448 }
2449 \f
2450 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2451 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2452 `unknown_address_altered', `unknown_constant_address_altered', and
2453 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2454 list `store_mems' in LOOP. */
2456 static void
2458 {
2460 rtx insn;
2464 /* The label after END. Jumping here is just like falling off the
2465 end of the loop. We use next_nonnote_insn instead of next_label
2466 as a hedge against the (pathological) case where some actual insn
2467 might end up between the two. */
2486 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2491 {
2493 {
2496 }
2497 }
2501 {
2503 {
2506 {
2508 /* Count number of loops contained in this one. */
2510 }
2517 {
2520 }
2527 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2528 attached FUNCTION_USAGE expression list, not accounted for by the
2529 code above. We should note these to avoid missing dependencies in
2530 later references. */
2531 {
2532 rtx fusage_entry;
2536 {
2542 {
2547 }
2548 }
2549 }
2554 {
2558 {
2563 {
2566 }
2567 else
2568 {
2571 }
2573 do
2574 {
2576 {
2578 {
2579 /* Something tricky. */
2582 }
2585 {
2586 /* A jump outside the current loop. */
2589 }
2590 }
2594 }
2596 }
2597 else
2598 {
2599 /* A return, or something tricky. */
2601 }
2602 }
2603 /* FALLTHRU */
2624 }
2625 }
2627 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2629 anywhere. */
2631 /* We don't want loads for MEMs moved to a location before the
2632 one at which their stack memory becomes allocated. (Note
2633 that this is not a problem for malloc, etc., since those
2634 require actual function calls. */
2635 && ! current_function_calls_alloca
2636 /* There are ways to leave the loop other than falling off the
2637 end. */
2643 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2644 that loop_invariant_p and load_mems can use true_dependence
2645 to determine what is really clobbered. */
2647 {
2650 loop_info->store_mems
2652 }
2654 {
2658 loop_info->store_mems
2660 }
2661 }
2662 \f
2663 /* Invalidate all loops containing LABEL. */
2665 static void
2667 {
2671 }
2673 /* Scan the function looking for loops. Record the start and end of each loop.
2674 Also mark as invalid loops any loops that contain a setjmp or are branched
2675 to from outside the loop. */
2677 static void
2679 {
2680 rtx insn;
2681 rtx label;
2691 /* If there are jumps to undefined labels,
2692 treat them as jumps out of any/all loops.
2693 This also avoids writing past end of tables when there are no loops. */
2696 /* Find boundaries of loops, mark which loops are contained within
2697 loops, and invalidate loops that have setjmp. */
2702 {
2705 {
2709 num_loops++;
2733 }
2737 {
2738 /* In this case, we must invalidate our current loop and any
2739 enclosing loop. */
2741 {
2747 }
2748 }
2750 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2751 enclosing loop, but this doesn't matter. */
2753 }
2755 /* Any loop containing a label used in an initializer must be invalidated,
2756 because it can be jumped into from anywhere. */
2760 /* Any loop containing a label used for an exception handler must be
2761 invalidated, because it can be jumped into from anywhere. */
2764 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2765 loop that it is not contained within, that loop is marked invalid.
2766 If any INSN or CALL_INSN uses a label's address, then the loop containing
2767 that label is marked invalid, because it could be jumped into from
2768 anywhere.
2770 Also look for blocks of code ending in an unconditional branch that
2771 exits the loop. If such a block is surrounded by a conditional
2772 branch around the block, move the block elsewhere (see below) and
2773 invert the jump to point to the code block. This may eliminate a
2774 label in our loop and will simplify processing by both us and a
2775 possible second cse pass. */
2779 {
2783 {
2787 }
2794 /* See if this is an unconditional branch outside the loop. */
2802 {
2803 rtx p;
2809 /* Go backwards until we reach the start of the loop, a label,
2810 or a JUMP_INSN. */
2817 ;
2819 /* Check for the case where we have a jump to an inner nested
2820 loop, and do not perform the optimization in that case. */
2823 {
2826 {
2831 }
2832 }
2834 /* Make sure that the target of P is within the current loop. */
2840 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2841 we have a block of code to try to move.
2843 We look backward and then forward from the target of INSN
2844 to find a BARRIER at the same loop depth as the target.
2845 If we find such a BARRIER, we make a new label for the start
2846 of the block, invert the jump in P and point it to that label,
2847 and move the block of code to the spot we found. */
2852 /* Just ignore jumps to labels that were never emitted.
2853 These always indicate compilation errors. */
2857 /* If it's not safe to move the sequence, then we
2858 mustn't try. */
2861 {
2862 rtx target
2866 rtx tmp;
2868 /* Search for possible garbage past the conditional jumps
2869 and look for the last barrier. */
2877 /* Don't move things inside a tablejump. */
2890 /* Don't move things inside a tablejump. */
2901 {
2905 /* Ensure our label doesn't go away. */
2908 /* Verify that uid_loop is large enough and that
2909 we can invert P. */
2911 {
2914 /* If no suitable BARRIER was found, create a suitable
2915 one before TARGET. Since TARGET is a fall through
2916 path, we'll need to insert a jump around our block
2917 and add a BARRIER before TARGET.
2919 This creates an extra unconditional jump outside
2920 the loop. However, the benefits of removing rarely
2921 executed instructions from inside the loop usually
2922 outweighs the cost of the extra unconditional jump
2923 outside the loop. */
2925 {
2926 rtx temp;
2933 }
2935 /* Include the BARRIER after INSN and copy the
2936 block after LOC. */
2941 /* All those insns are now in TARGET_LOOP. */
2947 /* The label jumped to by INSN is no longer a loop
2948 exit. Unless INSN does not have a label (e.g.,
2949 it is a RETURN insn), search loop->exit_labels
2950 to find its label_ref, and remove it. Also turn
2951 off LABEL_OUTSIDE_LOOP_P bit. */
2953 {
2955 r;
2958 {
2962 else
2965 }
2971 /* If we didn't find it, then something is
2972 wrong. */
2975 }
2977 /* P is now a jump outside the loop, so it must be put
2978 in loop->exit_labels, and marked as such.
2979 The easiest way to do this is to just call
2980 mark_loop_jump again for P. */
2983 /* If INSN now jumps to the insn after it,
2984 delete INSN. */
2989 }
2991 /* Continue the loop after where the conditional
2992 branch used to jump, since the only branch insn
2993 in the block (if it still remains) is an inter-loop
2994 branch and hence needs no processing. */
3000 /* This loop will be continued with NEXT_INSN (insn). */
3002 }
3003 }
3004 }
3005 }
3006 }
3008 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3009 loops it is contained in, mark the target loop invalid.
3011 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3013 static void
3015 {
3021 {
3033 /* There could be a label reference in here. */
3045 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3057 /* Link together all labels that branch outside the loop. This
3058 is used by final_[bg]iv_value and the loop unrolling code. Also
3059 mark this LABEL_REF so we know that this branch should predict
3060 false. */
3062 /* A check to make sure the label is not in an inner nested loop,
3063 since this does not count as a loop exit. */
3065 {
3070 }
3071 else
3075 {
3084 }
3086 /* If this is inside a loop, but not in the current loop or one enclosed
3087 by it, it invalidates at least one loop. */
3092 /* We must invalidate every nested loop containing the target of this
3093 label, except those that also contain the jump insn. */
3096 {
3097 /* Stop when we reach a loop that also contains the jump insn. */
3102 /* If we get here, we know we need to invalidate a loop. */
3109 }
3113 /* If this is not setting pc, ignore. */
3135 /* Strictly speaking this is not a jump into the loop, only a possible
3136 jump out of the loop. However, we have no way to link the destination
3137 of this jump onto the list of exit labels. To be safe we mark this
3138 loop and any containing loops as invalid. */
3140 {
3142 {
3148 }
3149 }
3151 }
3152 }
3153 \f
3154 /* Return nonzero if there is a label in the range from
3155 insn INSN to and including the insn whose luid is END
3156 INSN must have an assigned luid (i.e., it must not have
3157 been previously created by loop.c). */
3159 static int
3161 {
3163 {
3167 }
3170 }
3172 /* Record that a memory reference X is being set. */
3174 static void
3177 {
3183 /* Count number of memory writes.
3184 This affects heuristics in strength_reduce. */
3187 /* BLKmode MEM means all memory is clobbered. */
3189 {
3192 else
3196 }
3200 }
3202 /* X is a value modified by an INSN that references a biv inside a loop
3203 exit test (ie, X is somehow related to the value of the biv). If X
3204 is a pseudo that is used more than once, then the biv is (effectively)
3205 used more than once. DATA is a pointer to a loop_regs structure. */
3207 static void
3209 {
3224 /* If we do not have usage information, or if we know the register
3225 is used more than once, note that fact for check_dbra_loop. */
3230 }
3231 \f
3232 /* Return nonzero if the rtx X is invariant over the current loop.
3234 The value is 2 if we refer to something only conditionally invariant.
3236 A memory ref is invariant if it is not volatile and does not conflict
3237 with anything stored in `loop_info->store_mems'. */
3239 int
3241 {
3248 rtx mem_list_entry;
3254 {
3262 /* A LABEL_REF is normally invariant, however, if we are unrolling
3263 loops, and this label is inside the loop, then it isn't invariant.
3264 This is because each unrolled copy of the loop body will have
3265 a copy of this label. If this was invariant, then an insn loading
3266 the address of this label into a register might get moved outside
3267 the loop, and then each loop body would end up using the same label.
3269 We don't know the loop bounds here though, so just fail for all
3270 labels. */
3273 else
3282 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3283 since the reg might be set by initialization within the loop. */
3294 /* Out-of-range regs can occur when we are called from unrolling.
3295 These have always been created by the unroller and are set in
3296 the loop, hence are never invariant. */
3307 /* Volatile memory references must be rejected. Do this before
3308 checking for read-only items, so that volatile read-only items
3309 will be rejected also. */
3313 /* See if there is any dependence between a store and this load. */
3316 {
3322 }
3324 /* It's not invalidated by a store in memory
3325 but we must still verify the address is invariant. */
3329 /* Don't mess with insns declared volatile. */
3336 }
3340 {
3342 {
3348 }
3350 {
3353 {
3359 }
3361 }
3362 }
3365 }
3366 \f
3367 /* Return nonzero if all the insns in the loop that set REG
3368 are INSN and the immediately following insns,
3369 and if each of those insns sets REG in an invariant way
3370 (not counting uses of REG in them).
3372 The value is 2 if some of these insns are only conditionally invariant.
3374 We assume that INSN itself is the first set of REG
3375 and that its source is invariant. */
3377 static int
3379 rtx insn)
3380 {
3384 rtx temp;
3385 /* Number of sets we have to insist on finding after INSN. */
3391 /* If N_SETS hit the limit, we can't rely on its value. */
3398 {
3400 rtx set;
3405 /* If library call, skip to end of it. */
3414 {
3419 {
3420 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3421 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3422 notes are OK. */
3428 }
3429 }
3431 count--;
3433 {
3436 }
3437 }
3440 /* If loop_invariant_p ever returned 2, we return 2. */
3442 }
3444 #if 0
3445 /* I don't think this condition is sufficient to allow INSN
3446 to be moved, so we no longer test it. */
3448 /* Return 1 if all insns in the basic block of INSN and following INSN
3449 that set REG are invariant according to TABLE. */
3451 static int
3453 {
3458 {
3467 {
3470 }
3471 }
3472 }
3474 \f
3475 /* Look at all uses (not sets) of registers in X. For each, if it is
3476 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3477 a different insn, set USAGE[REGNO] to const0_rtx. */
3479 static void
3481 {
3493 {
3494 /* Don't count SET_DEST if it is a REG; otherwise count things
3495 in SET_DEST because if a register is partially modified, it won't
3496 show up as a potential movable so we don't care how USAGE is set
3497 for it. */
3501 }
3502 else
3504 {
3510 }
3511 }
3512 \f
3513 /* Count and record any set in X which is contained in INSN. Update
3514 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3515 in X. */
3517 static void
3519 {
3521 /* Don't move a reg that has an explicit clobber.
3522 It's not worth the pain to try to do it correctly. */
3526 {
3534 {
3538 {
3539 /* If this is the first setting of this reg
3540 in current basic block, and it was set before,
3541 it must be set in two basic blocks, so it cannot
3542 be moved out of the loop. */
3546 /* If this is not first setting in current basic block,
3547 see if reg was used in between previous one and this.
3548 If so, neither one can be moved. */
3555 }
3556 }
3557 }
3558 }
3559 \f
3560 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3561 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3562 contained in insn INSN is used by any insn that precedes INSN in
3563 cyclic order starting from the loop entry point.
3565 We don't want to use INSN_LUID here because if we restrict INSN to those
3566 that have a valid INSN_LUID, it means we cannot move an invariant out
3567 from an inner loop past two loops. */
3569 static int
3571 {
3573 rtx p;
3575 /* Scan forward checking for register usage. If we hit INSN, we
3576 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3578 {
3584 }
3587 }
3588 \f
3590 /* Information we collect about arrays that we might want to prefetch. */
3591 struct prefetch_info
3592 {
3596 index. */
3597 HOST_WIDE_INT index;
3599 iteration. */
3601 prefetch area in one iteration. */
3603 This is set only for loops with known
3604 iteration counts and is 0xffffffff
3605 otherwise. */
3609 };
3611 /* Data used by check_store function. */
3612 struct check_store_data
3613 {
3614 rtx mem_address;
3616 };
3622 /* Set mem_write when mem_address is found. Used as callback to
3623 note_stores. */
3624 static void
3626 {
3631 }
3632 \f
3633 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3634 important to get some addresses combined. Later more sophisticated
3635 transformations can be added when necessary.
3637 ??? Same trick with swapping operand is done at several other places.
3638 It can be nice to develop some common way to handle this. */
3640 static int
3642 {
3656 {
3661 }
3662 /* Compare the elements. If any pair of corresponding elements fails to
3663 match, return 0 for the whole thing. */
3667 {
3669 {
3681 /* Two vectors must have the same length. */
3685 /* And the corresponding elements must match. */
3703 /* These are just backpointers, so they don't matter. */
3709 /* It is believed that rtx's at this level will never
3710 contain anything but integers and other rtx's,
3711 except for within LABEL_REFs and SYMBOL_REFs. */
3714 }
3715 }
3717 }
3718 \f
3719 /* Remove constant addition value from the expression X (when present)
3720 and return it. */
3722 static HOST_WIDE_INT
3724 {
3728 /* Avoid clobbering a shared CONST expression. */
3730 {
3734 {
3737 }
3739 }
3742 {
3745 }
3747 /* For plus expression recurse on ourself. */
3749 {
3753 /* In case our parameter was constant, remove extra zero from the
3754 expression. */
3759 }
3762 }
3764 /* Attempt to identify accesses to arrays that are most likely to cause cache
3765 misses, and emit prefetch instructions a few prefetch blocks forward.
3767 To detect the arrays we use the GIV information that was collected by the
3768 strength reduction pass.
3770 The prefetch instructions are generated after the GIV information is done
3771 and before the strength reduction process. The new GIVs are injected into
3772 the strength reduction tables, so the prefetch addresses are optimized as
3773 well.
3775 GIVs are split into base address, stride, and constant addition values.
3776 GIVs with the same address, stride and close addition values are combined
3777 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3778 for write instructions can be used for the block we write to, on machines
3779 that support write prefetches.
3781 Several heuristics are used to determine when to prefetch. They are
3782 controlled by defined symbols that can be overridden for each target. */
3784 static void
3786 {
3802 /* Consider only loops w/o calls. When a call is done, the loop is probably
3803 slow enough to read the memory. */
3805 {
3810 }
3812 /* Don't prefetch in loops known to have few iterations. */
3816 {
3821 }
3823 /* Search all induction variables and pick those interesting for the prefetch
3824 machinery. */
3826 {
3832 /* Expect all BIVs to be executed in each iteration. This makes our
3833 analysis more conservative. */
3835 {
3836 /* Discard non-constant additions that we can't handle well yet, and
3837 BIVs that are executed multiple times; such BIVs ought to be
3838 handled in the nested loop. We accept not_every_iteration BIVs,
3839 since these only result in larger strides and make our
3840 heuristics more conservative. */
3842 {
3844 {
3850 }
3852 }
3855 {
3857 {
3863 }
3865 }
3869 }
3875 {
3876 rtx address;
3877 rtx temp;
3886 /* See whether an induction variable is interesting to us and if
3887 not, report the reason. */
3891 /* We are interested only in constant stride memory references
3892 in order to be able to compute density easily. */
3896 else
3897 {
3900 {
3903 }
3905 /* On some targets, reversed order prefetches are not
3906 worthwhile. */
3910 /* Prefetch of accesses with an extreme stride might not be
3911 worthwhile, either. */
3916 /* Ignore GIVs with varying add values; we can't predict the
3917 value for the next iteration. */
3921 /* Ignore GIVs in the nested loops; they ought to have been
3922 handled already. */
3925 }
3928 {
3934 }
3936 /* Determine the pointer to the basic array we are examining. It is
3937 the sum of the BIV's initial value and the GIV's add_val. */
3947 /* When the GIV is not always executed, we might be better off by
3948 not dirtying the cache pages. */
3951 else
3952 {
3957 }
3959 /* Attempt to find another prefetch to the same array and see if we
3960 can merge this one. */
3964 {
3965 /* In case both access same array (same location
3966 just with small difference in constant indexes), merge
3967 the prefetches. Just do the later and the earlier will
3968 get prefetched from previous iteration.
3969 The artificial threshold should not be too small,
3970 but also not bigger than small portion of memory usually
3971 traversed by single loop. */
3974 {
3983 }
3987 {
3992 }
3993 }
3995 /* Merging failed. */
3997 {
4005 num_prefetches++;
4007 {
4012 }
4013 }
4014 }
4015 }
4018 {
4021 /* Attempt to calculate the total number of bytes fetched by all
4022 iterations of the loop. Avoid overflow. */
4027 else
4032 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4037 {
4042 }
4043 else
4044 {
4050 }
4051 else
4054 /* Find how many prefetch instructions we'll use within the loop. */
4056 {
4062 }
4063 }
4065 /* Determine how many iterations ahead to prefetch within the loop, based
4066 on how many prefetches we currently expect to do within the loop. */
4068 {
4070 {
4076 }
4077 }
4078 /* We'll also use AHEAD to determine how many prefetch instructions to
4079 emit before a loop, so don't leave it zero. */
4084 {
4085 /* Update if we've decided not to prefetch anything within the loop. */
4089 /* Find how many prefetch instructions we'll use before the loop. */
4091 {
4099 }
4102 {
4122 }
4123 }
4126 {
4127 /* Record that this loop uses prefetch instructions. */
4131 {
4136 }
4137 }
4140 {
4144 {
4146 rtx insn;
4150 rtx seq;
4152 /* We can save some effort by offsetting the address on
4153 architectures with offsettable memory references. */
4156 else
4157 {
4163 }
4166 /* Make sure the address operand is valid for prefetch. */
4176 /* Check all insns emitted and record the new GIV
4177 information. */
4180 {
4185 }
4186 }
4189 {
4190 /* Emit insns before the loop to fetch the first cache lines or,
4191 if we're not prefetching within the loop, everything we expect
4192 to need. */
4194 {
4202 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4203 non-constant INIT_VAL to have the same mode as REG, which
4204 in this case we know to be Pmode. */
4206 {
4207 rtx seq;
4214 }
4220 loop_start);
4221 }
4222 }
4223 }
4226 }
4227 \f
4228 /* A "basic induction variable" or biv is a pseudo reg that is set
4229 (within this loop) only by incrementing or decrementing it. */
4230 /* A "general induction variable" or giv is a pseudo reg whose
4231 value is a linear function of a biv. */
4233 /* Bivs are recognized by `basic_induction_var';
4234 Givs by `general_induction_var'. */
4236 /* Communication with routines called via `note_stores'. */
4240 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4244 /* ??? Unfinished optimizations, and possible future optimizations,
4245 for the strength reduction code. */
4247 /* ??? The interaction of biv elimination, and recognition of 'constant'
4248 bivs, may cause problems. */
4250 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4251 performance problems.
4253 Perhaps don't eliminate things that can be combined with an addressing
4254 mode. Find all givs that have the same biv, mult_val, and add_val;
4255 then for each giv, check to see if its only use dies in a following
4256 memory address. If so, generate a new memory address and check to see
4257 if it is valid. If it is valid, then store the modified memory address,
4258 otherwise, mark the giv as not done so that it will get its own iv. */
4260 /* ??? Could try to optimize branches when it is known that a biv is always
4261 positive. */
4263 /* ??? When replace a biv in a compare insn, we should replace with closest
4264 giv so that an optimized branch can still be recognized by the combiner,
4265 e.g. the VAX acb insn. */
4267 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4268 was rerun in loop_optimize whenever a register was added or moved.
4269 Also, some of the optimizations could be a little less conservative. */
4270 \f
4271 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4272 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4273 callback.
4275 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4276 least once for every loop iteration except for the last one.
4278 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4279 loop iteration.
4280 */
4281 void
4283 {
4288 rtx p;
4290 /* If loop_scan_start points to the loop exit test, we have to be wary of
4291 subversive use of gotos inside expression statements. */
4295 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4299 {
4302 /* Past CODE_LABEL, we get to insns that may be executed multiple
4303 times. The only way we can be sure that they can't is if every
4304 jump insn between here and the end of the loop either
4305 returns, exits the loop, is a jump to a location that is still
4306 behind the label, or is a jump to the loop start. */
4309 {
4315 {
4320 {
4323 else
4327 }
4335 {
4338 }
4339 }
4340 }
4342 /* Past a jump, we get to insns for which we can't count
4343 on whether they will be executed during each iteration. */
4344 /* This code appears twice in strength_reduce. There is also similar
4345 code in scan_loop. */
4347 /* If we enter the loop in the middle, and scan around to the
4348 beginning, don't set not_every_iteration for that.
4349 This can be any kind of jump, since we want to know if insns
4350 will be executed if the loop is executed. */
4355 {
4358 /* If this is a jump outside the loop, then it also doesn't
4359 matter. Check to see if the target of this branch is on the
4360 loop->exits_labels list. */
4368 }
4371 {
4372 /* At the virtual top of a converted loop, insns are again known to
4373 be executed each iteration: logically, the loop begins here
4374 even though the exit code has been duplicated.
4376 Insns are also again known to be executed each iteration at
4377 the LOOP_CONT note. */
4383 loop_depth++;
4385 loop_depth--;
4386 }
4388 /* Note if we pass a loop latch. If we do, then we can not clear
4389 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4390 a loop since a jump before the last CODE_LABEL may have started
4391 a new loop iteration.
4393 Note that LOOP_TOP is only set for rotated loops and we need
4394 this check for all loops, so compare against the CODE_LABEL
4395 which immediately follows LOOP_START. */
4400 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4401 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4402 or not an insn is known to be executed each iteration of the
4403 loop, whether or not any iterations are known to occur.
4405 Therefore, if we have just passed a label and have no more labels
4406 between here and the test insn of the loop, and we have not passed
4407 a jump to the top of the loop, then we know these insns will be
4408 executed each iteration. */
4411 && !past_loop_latch
4416 }
4417 }
4418 \f
4419 static void
4421 {
4424 /* Temporary list pointers for traversing ivs->list. */
4431 /* Scan ivs->list to remove all regs that proved not to be bivs.
4432 Make a sanity check against regs->n_times_set. */
4434 {
4436 /* Above happens if register modified by subreg, etc. */
4437 /* Make sure it is not recognized as a basic induction var: */
4439 /* If never incremented, it is invariant that we decided not to
4440 move. So leave it alone. */
4442 {
4453 }
4454 else
4455 {
4460 }
4461 }
4462 }
4465 /* Determine how BIVS are initialized by looking through pre-header
4466 extended basic block. */
4467 static void
4469 {
4471 /* Temporary list pointers for traversing ivs->list. */
4474 rtx p;
4476 /* Find initial value for each biv by searching backwards from loop_start,
4477 halting at first label. Also record any test condition. */
4481 {
4482 rtx test;
4492 /* Record any test of a biv that branches around the loop if no store
4493 between it and the start of loop. We only care about tests with
4494 constants and registers and only certain of those. */
4504 {
4505 /* If an NE test, we have an initial value! */
4507 {
4511 }
4512 else
4514 }
4515 }
4516 }
4519 /* Look at the each biv and see if we can say anything better about its
4520 initial value from any initializing insns set up above. (This is done
4521 in two passes to avoid missing SETs in a PARALLEL.) */
4522 static void
4524 {
4526 /* Temporary list pointers for traversing ivs->list. */
4531 {
4532 rtx src;
4533 rtx note;
4538 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4539 is a constant, use the value of that. */
4545 else
4558 {
4562 {
4565 }
4566 }
4567 /* If we can't make it a giv,
4568 let biv keep initial value of "itself". */
4571 }
4572 }
4575 /* Search the loop for general induction variables. */
4577 static void
4579 {
4581 }
4584 /* For each giv for which we still don't know whether or not it is
4585 replaceable, check to see if it is replaceable because its final value
4586 can be calculated. */
4588 static void
4590 {
4595 {
4601 }
4602 }
4605 /* Return nonzero if it is possible to eliminate the biv BL provided
4606 all givs are reduced. This is possible if either the reg is not
4607 used outside the loop, or we can compute what its final value will
4608 be. */
4610 static int
4613 {
4614 /* For architectures with a decrement_and_branch_until_zero insn,
4615 don't do this if we put a REG_NONNEG note on the endtest for this
4616 biv. */
4618 #ifdef HAVE_decrement_and_branch_until_zero
4620 {
4625 }
4626 #endif
4628 /* Check that biv is used outside loop or if it has a final value.
4629 Compare against bl->init_insn rather than loop->start. We aren't
4630 concerned with any uses of the biv between init_insn and
4631 loop->start since these won't be affected by the value of the biv
4632 elsewhere in the function, so long as init_insn doesn't use the
4633 biv itself. */
4644 {
4652 }
4654 }
4657 /* Reduce each giv of BL that we have decided to reduce. */
4659 static void
4661 {
4665 {
4668 {
4671 /* If the code for derived givs immediately below has already
4672 allocated a new_reg, we must keep it. */
4676 #ifdef AUTO_INC_DEC
4677 /* If the target has auto-increment addressing modes, and
4678 this is an address giv, then try to put the increment
4679 immediately after its use, so that flow can create an
4680 auto-increment addressing mode. */
4683 /* We don't handle reversed biv's because bl->biv->insn
4684 does not have a valid INSN_LUID. */
4688 {
4689 /* If other giv's have been combined with this one, then
4690 this will work only if all uses of the other giv's occur
4691 before this giv's insn. This is difficult to check.
4693 We simplify this by looking for the common case where
4694 there is one DEST_REG giv, and this giv's insn is the
4695 last use of the dest_reg of that DEST_REG giv. If the
4696 increment occurs after the address giv, then we can
4697 perform the optimization. (Otherwise, the increment
4698 would have to go before other_giv, and we would not be
4699 able to combine it with the address giv to get an
4700 auto-inc address.) */
4702 {
4707 {
4710 else
4712 }
4719 }
4720 /* Check for case where increment is before the address
4721 giv. Do this test in "loop order". */
4730 else
4733 #ifdef HAVE_cc0
4734 {
4735 rtx prev;
4737 /* We can't put an insn immediately after one setting
4738 cc0, or immediately before one using cc0. */
4745 }
4746 #endif
4750 }
4751 #endif
4753 /* For each place where the biv is incremented, add an insn
4754 to increment the new, reduced reg for the giv. */
4756 {
4757 rtx insert_before;
4759 /* Skip if location is the same as a previous one. */
4766 else
4774 /* A multiply is acceptable here
4775 since this is presumed to be seldom executed. */
4779 }
4781 /* Add code at loop start to initialize giv's reduced reg. */
4786 }
4787 }
4788 }
4791 /* Check for givs whose first use is their definition and whose
4792 last use is the definition of another giv. If so, it is likely
4793 dead and should not be used to derive another giv nor to
4794 eliminate a biv. */
4796 static void
4798 {
4802 {
4809 {
4815 }
4816 }
4817 }
4820 static void
4822 {
4826 {
4833 /* Update expression if this was combined, in case other giv was
4834 replaced. */
4839 /* See if this register is known to be a pointer to something. If
4840 so, see if we can find the alignment. First see if there is a
4841 destination register that is a pointer. If so, this shares the
4842 alignment too. Next see if we can deduce anything from the
4843 computational information. If not, and this is a DEST_ADDR
4844 giv, at least we know that it's a pointer, though we don't know
4845 the alignment. */
4853 {
4862 }
4866 {
4874 }
4879 /* Store reduced reg as the address in the memref where we found
4880 this giv. */
4883 {
4885 }
4886 else
4887 {
4889 rtx note;
4891 /* Not replaceable; emit an insn to set the original giv reg from
4892 the reduced giv, same as above. */
4897 /* The original insn may have a REG_EQUAL note. This note is
4898 now incorrect and may result in invalid substitutions later.
4899 The original insn is dead, but may be part of a libcall
4900 sequence, which doesn't seem worth the bother of handling. */
4904 }
4906 /* When a loop is reversed, givs which depend on the reversed
4907 biv, and which are live outside the loop, must be set to their
4908 correct final value. This insn is only needed if the giv is
4909 not replaceable. The correct final value is the same as the
4910 value that the giv starts the reversed loop with. */
4921 {
4926 }
4927 }
4928 }
4931 static int
4934 rtx test_reg)
4935 {
4944 /* Reduce benefit if not replaceable, since we will insert a
4945 move-insn to replace the insn that calculates this giv. Don't do
4946 this unless the giv is a user variable, since it will often be
4947 marked non-replaceable because of the duplication of the exit
4948 code outside the loop. In such a case, the copies we insert are
4949 dead and will be deleted. So they don't have a cost. Similar
4950 situations exist. */
4951 /* ??? The new final_[bg]iv_value code does a much better job of
4952 finding replaceable giv's, and hence this code may no longer be
4953 necessary. */
4958 /* Decrease the benefit to count the add-insns that we will insert
4959 to increment the reduced reg for the giv. ??? This can
4960 overestimate the run-time cost of the additional insns, e.g. if
4961 there are multiple basic blocks that increment the biv, but only
4962 one of these blocks is executed during each iteration. There is
4963 no good way to detect cases like this with the current structure
4964 of the loop optimizer. This code is more accurate for
4965 determining code size than run-time benefits. */
4968 /* Decide whether to strength-reduce this giv or to leave the code
4969 unchanged (recompute it from the biv each time it is used). This
4970 decision can be made independently for each giv. */
4972 #ifdef AUTO_INC_DEC
4973 /* Attempt to guess whether autoincrement will handle some of the
4974 new add insns; if so, increase BENEFIT (undo the subtraction of
4975 add_cost that was done above). */
4977 /* Increasing the benefit is risky, since this is only a guess.
4978 Avoid increasing register pressure in cases where there would
4979 be no other benefit from reducing this giv. */
4982 {
4997 }
4998 #endif
5001 }
5004 /* Free IV structures for LOOP. */
5006 static void
5008 {
5015 {
5021 {
5024 }
5026 {
5029 }
5033 }
5034 }
5037 /* Perform strength reduction and induction variable elimination.
5039 Pseudo registers created during this function will be beyond the
5040 last valid index in several tables including
5041 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5042 problem here, because the added registers cannot be givs outside of
5043 their loop, and hence will never be reconsidered. But scan_loop
5044 must check regnos to make sure they are in bounds. */
5046 static void
5048 {
5052 rtx p;
5053 /* Temporary list pointer for traversing ivs->list. */
5055 /* Ratio of extra register life span we can justify
5056 for saving an instruction. More if loop doesn't call subroutines
5057 since in that case saving an insn makes more difference
5058 and more registers are available. */
5059 /* ??? could set this to last value of threshold in move_movables */
5061 /* Map of pseudo-register replacements. */
5073 /* Find all BIVs in loop. */
5076 /* Exit if there are no bivs. */
5078 {
5079 /* Can still unroll the loop anyways, but indicate that there is no
5080 strength reduction info available. */
5086 }
5088 /* Determine how BIVS are initialized by looking through pre-header
5089 extended basic block. */
5092 /* Look at the each biv and see if we can say anything better about its
5093 initial value from any initializing insns set up above. */
5096 /* Search the loop for general induction variables. */
5099 /* Try to calculate and save the number of loop iterations. This is
5100 set to zero if the actual number can not be calculated. This must
5101 be called after all giv's have been identified, since otherwise it may
5102 fail if the iteration variable is a giv. */
5105 #ifdef HAVE_prefetch
5108 #endif
5110 /* Now for each giv for which we still don't know whether or not it is
5111 replaceable, check to see if it is replaceable because its final value
5112 can be calculated. This must be done after loop_iterations is called,
5113 so that final_giv_value will work correctly. */
5116 /* Try to prove that the loop counter variable (if any) is always
5117 nonnegative; if so, record that fact with a REG_NONNEG note
5118 so that "decrement and branch until zero" insn can be used. */
5121 /* Create reg_map to hold substitutions for replaceable giv regs.
5122 Some givs might have been made from biv increments, so look at
5123 ivs->reg_iv_type for a suitable size. */
5127 /* Examine each iv class for feasibility of strength reduction/induction
5128 variable elimination. */
5131 {
5135 /* Test whether it will be possible to eliminate this biv
5136 provided all givs are reduced. */
5139 /* This will be true at the end, if all givs which depend on this
5140 biv have been strength reduced.
5141 We can't (currently) eliminate the biv unless this is so. */
5144 /* Check each extension dependent giv in this class to see if its
5145 root biv is safe from wrapping in the interior mode. */
5148 /* Combine all giv's for this iv_class. */
5152 {
5160 /* If an insn is not to be strength reduced, then set its ignore
5161 flag, and clear bl->all_reduced. */
5163 /* A giv that depends on a reversed biv must be reduced if it is
5164 used after the loop exit, otherwise, it would have the wrong
5165 value after the loop exit. To make it simple, just reduce all
5166 of such giv's whether or not we know they are used after the loop
5167 exit. */
5172 {
5180 }
5181 else
5182 {
5183 /* Check that we can increment the reduced giv without a
5184 multiply insn. If not, reject it. */
5189 {
5197 }
5198 }
5199 }
5201 /* Check for givs whose first use is their definition and whose
5202 last use is the definition of another giv. If so, it is likely
5203 dead and should not be used to derive another giv nor to
5204 eliminate a biv. */
5207 /* Reduce each giv that we decided to reduce. */
5210 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5211 as not reduced.
5213 For each giv register that can be reduced now: if replaceable,
5214 substitute reduced reg wherever the old giv occurs;
5215 else add new move insn "giv_reg = reduced_reg". */
5218 /* All the givs based on the biv bl have been reduced if they
5219 merit it. */
5221 /* For each giv not marked as maybe dead that has been combined with a
5222 second giv, clear any "maybe dead" mark on that second giv.
5223 v->new_reg will either be or refer to the register of the giv it
5224 combined with.
5226 Doing this clearing avoids problems in biv elimination where
5227 a giv's new_reg is a complex value that can't be put in the
5228 insn but the giv combined with (with a reg as new_reg) is
5229 marked maybe_dead. Since the register will be used in either
5230 case, we'd prefer it be used from the simpler giv. */
5236 /* Try to eliminate the biv, if it is a candidate.
5237 This won't work if ! bl->all_reduced,
5238 since the givs we planned to use might not have been reduced.
5240 We have to be careful that we didn't initially think we could
5241 eliminate this biv because of a giv that we now think may be
5242 dead and shouldn't be used as a biv replacement.
5244 Also, there is the possibility that we may have a giv that looks
5245 like it can be used to eliminate a biv, but the resulting insn
5246 isn't valid. This can happen, for example, on the 88k, where a
5247 JUMP_INSN can compare a register only with zero. Attempts to
5248 replace it with a compare with a constant will fail.
5250 Note that in cases where this call fails, we may have replaced some
5251 of the occurrences of the biv with a giv, but no harm was done in
5252 doing so in the rare cases where it can occur. */
5256 {
5257 /* ?? If we created a new test to bypass the loop entirely,
5258 or otherwise drop straight in, based on this test, then
5259 we might want to rewrite it also. This way some later
5260 pass has more hope of removing the initialization of this
5261 biv entirely. */
5263 /* If final_value != 0, then the biv may be used after loop end
5264 and we must emit an insn to set it just in case.
5266 Reversed bivs already have an insn after the loop setting their
5267 value, so we don't need another one. We can't calculate the
5268 proper final value for such a biv here anyways. */
5277 }
5278 /* See above note wrt final_value. But since we couldn't eliminate
5279 the biv, we must set the value after the loop instead of before. */
5283 }
5285 /* Go through all the instructions in the loop, making all the
5286 register substitutions scheduled in REG_MAP. */
5291 {
5295 }
5298 {
5299 /* When we completely unroll a loop we will likely not need the increment
5300 of the loop BIV and we will not need the conditional branch at the
5301 end of the loop. */
5304 #ifdef HAVE_cc0
5305 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5306 need the comparison before the conditional branch at the end of the
5307 loop. */
5309 #endif
5311 /* We'll need one copy for each loop iteration. */
5314 /* A little slop to account for the ability to remove initialization
5315 code, better CSE, and other secondary benefits of completely
5316 unrolling some loops. */
5319 /* Clamp the value. */
5322 }
5324 /* Unroll loops from within strength reduction so that we can use the
5325 induction variable information that strength_reduce has already
5326 collected. Always unroll loops that would be as small or smaller
5327 unrolled than when rolled. */
5334 #ifdef HAVE_doloop_end
5339 /* In case number of iterations is known, drop branch prediction note
5340 in the branch. Do that only in second loop pass, as loop unrolling
5341 may change the number of iterations performed. */
5343 {
5344 unsigned HOST_WIDE_INT n
5349 }
5357 }
5358 \f
5359 /*Record all basic induction variables calculated in the insn. */
5360 static rtx
5363 {
5365 rtx set;
5366 rtx dest_reg;
5367 rtx inc_val;
5368 rtx mult_val;
5374 {
5379 {
5384 {
5385 /* It is a possible basic induction variable.
5386 Create and initialize an induction structure for it. */
5394 }
5397 }
5398 }
5400 }
5401 \f
5402 /* Record all givs calculated in the insn.
5403 A register is a giv if: it is only set once, it is a function of a
5404 biv and a constant (or invariant), and it is not a biv. */
5405 static rtx
5408 {
5411 rtx set;
5412 /* Look for a general induction variable in a register. */
5417 {
5418 rtx src_reg;
5419 rtx dest_reg;
5420 rtx add_val;
5421 rtx mult_val;
5422 rtx ext_val;
5425 rtx last_consec_insn;
5434 /* Equivalent expression is a giv. */
5439 /* Don't try to handle any regs made by loop optimization.
5440 We have nothing on them in regno_first_uid, etc. */
5442 /* Don't recognize a BASIC_INDUCT_VAR here. */
5444 /* This must be the only place where the register is set. */
5446 /* or all sets must be consecutive and make a giv. */
5451 {
5455 /* If this is a library call, increase benefit. */
5459 /* Skip the consecutive insns, if there are any. */
5467 }
5468 }
5470 /* Look for givs which are memory addresses. */
5473 maybe_multiple);
5475 /* Update the status of whether giv can derive other givs. This can
5476 change when we pass a label or an insn that updates a biv. */
5481 }
5482 \f
5483 /* Return 1 if X is a valid source for an initial value (or as value being
5484 compared against in an initial test).
5486 X must be either a register or constant and must not be clobbered between
5487 the current insn and the start of the loop.
5489 INSN is the insn containing X. */
5491 static int
5493 {
5497 /* Only consider pseudos we know about initialized in insns whose luids
5498 we know. */
5503 /* Don't use call-clobbered registers across a call which clobbers it. On
5504 some machines, don't use any hard registers at all. */
5506 && (SMALL_REGISTER_CLASSES
5510 /* Don't use registers that have been clobbered before the start of the
5511 loop. */
5516 }
5517 \f
5518 /* Scan X for memory refs and check each memory address
5519 as a possible giv. INSN is the insn whose pattern X comes from.
5520 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5521 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5522 more than once in each loop iteration. */
5524 static void
5527 {
5537 {
5553 {
5554 rtx src_reg;
5555 rtx add_val;
5556 rtx mult_val;
5557 rtx ext_val;
5560 /* This code used to disable creating GIVs with mult_val == 1 and
5561 add_val == 0. However, this leads to lost optimizations when
5562 it comes time to combine a set of related DEST_ADDR GIVs, since
5563 this one would not be seen. */
5568 {
5569 /* Found one; record it. */
5578 }
5579 }
5584 }
5586 /* Recursively scan the subexpressions for other mem refs. */
5592 maybe_multiple);
5596 maybe_multiple);
5597 }
5598 \f
5599 /* Fill in the data about one biv update.
5600 V is the `struct induction' in which we record the biv. (It is
5601 allocated by the caller, with alloca.)
5602 INSN is the insn that sets it.
5603 DEST_REG is the biv's reg.
5605 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5606 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5607 being set to INC_VAL.
5609 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5610 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5611 can be executed more than once per iteration. If MAYBE_MULTIPLE
5612 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5613 executed exactly once per iteration. */
5615 static void
5619 {
5636 /* Add this to the reg's iv_class, creating a class
5637 if this is the first incrementation of the reg. */
5641 {
5642 /* Create and initialize new iv_class. */
5652 /* Set initial value to the reg itself. */
5655 /* We haven't seen the initializing insn yet */
5665 /* Add this class to ivs->list. */
5669 /* Put it in the array of biv register classes. */
5671 }
5672 else
5673 {
5674 /* Check if location is the same as a previous one. */
5678 {
5681 }
5682 }
5684 /* Update IV_CLASS entry for this biv. */
5693 }
5694 \f
5695 /* Fill in the data about one giv.
5696 V is the `struct induction' in which we record the giv. (It is
5697 allocated by the caller, with alloca.)
5698 INSN is the insn that sets it.
5699 BENEFIT estimates the savings from deleting this insn.
5700 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5701 into a register or is used as a memory address.
5703 SRC_REG is the biv reg which the giv is computed from.
5704 DEST_REG is the giv's reg (if the giv is stored in a reg).
5705 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5706 LOCATION points to the place where this giv's value appears in INSN. */
5708 static void
5713 {
5718 rtx temp;
5720 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5721 undo the MULT canonicalization that we performed earlier. */
5751 /* The v->always_computable field is used in update_giv_derive, to
5752 determine whether a giv can be used to derive another giv. For a
5753 DEST_REG giv, INSN computes a new value for the giv, so its value
5754 isn't computable if INSN insn't executed every iteration.
5755 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5756 it does not compute a new value. Hence the value is always computable
5757 regardless of whether INSN is executed each iteration. */
5761 else
5767 {
5770 }
5772 {
5777 /* If the lifetime is zero, it means that this register is
5778 really a dead store. So mark this as a giv that can be
5779 ignored. This will not prevent the biv from being eliminated. */
5785 }
5787 /* Add the giv to the class of givs computed from one biv. */
5791 {
5794 /* Don't count DEST_ADDR. This is supposed to count the number of
5795 insns that calculate givs. */
5799 }
5800 else
5801 /* Fatal error, biv missing for this giv? */
5805 {
5808 }
5809 else
5810 {
5811 /* The giv can be replaced outright by the reduced register only if all
5812 of the following conditions are true:
5813 - the insn that sets the giv is always executed on any iteration
5814 on which the giv is used at all
5815 (there are two ways to deduce this:
5816 either the insn is executed on every iteration,
5817 or all uses follow that insn in the same basic block),
5818 - the giv is not used outside the loop
5819 - no assignments to the biv occur during the giv's lifetime. */
5822 /* Previous line always fails if INSN was moved by loop opt. */
5825 && (! not_every_iteration
5827 {
5828 /* Now check that there are no assignments to the biv within the
5829 giv's lifetime. This requires two separate checks. */
5831 /* Check each biv update, and fail if any are between the first
5832 and last use of the giv.
5834 If this loop contains an inner loop that was unrolled, then
5835 the insn modifying the biv may have been emitted by the loop
5836 unrolling code, and hence does not have a valid luid. Just
5837 mark the biv as not replaceable in this case. It is not very
5838 useful as a biv, because it is used in two different loops.
5839 It is very unlikely that we would be able to optimize the giv
5840 using this biv anyways. */
5845 {
5851 {
5855 }
5856 }
5858 /* If there are any backwards branches that go from after the
5859 biv update to before it, then this giv is not replaceable. */
5863 {
5867 }
5868 }
5869 else
5870 {
5871 /* May still be replaceable, we don't have enough info here to
5872 decide. */
5875 }
5876 }
5878 /* Record whether the add_val contains a const_int, for later use by
5879 combine_givs. */
5880 {
5885 ;
5889 {
5891 {
5896 else
5898 }
5901 }
5902 }
5906 }
5908 /* All this does is determine whether a giv can be made replaceable because
5909 its final value can be calculated. This code can not be part of record_giv
5910 above, because final_giv_value requires that the number of loop iterations
5911 be known, and that can not be accurately calculated until after all givs
5912 have been identified. */
5914 static void
5916 {
5919 /* DEST_ADDR givs will never reach here, because they are always marked
5920 replaceable above in record_giv. */
5922 /* The giv can be replaced outright by the reduced register only if all
5923 of the following conditions are true:
5924 - the insn that sets the giv is always executed on any iteration
5925 on which the giv is used at all
5926 (there are two ways to deduce this:
5927 either the insn is executed on every iteration,
5928 or all uses follow that insn in the same basic block),
5929 - its final value can be calculated (this condition is different
5930 than the one above in record_giv)
5931 - it's not used before the it's set
5932 - no assignments to the biv occur during the giv's lifetime. */
5934 #if 0
5935 /* This is only called now when replaceable is known to be false. */
5936 /* Clear replaceable, so that it won't confuse final_giv_value. */
5938 #endif
5943 {
5946 rtx last_giv_use;
5951 /* When trying to determine whether or not a biv increment occurs
5952 during the lifetime of the giv, we can ignore uses of the variable
5953 outside the loop because final_value is true. Hence we can not
5954 use regno_last_uid and regno_first_uid as above in record_giv. */
5956 /* Search the loop to determine whether any assignments to the
5957 biv occur during the giv's lifetime. Start with the insn
5958 that sets the giv, and search around the loop until we come
5959 back to that insn again.
5961 Also fail if there is a jump within the giv's lifetime that jumps
5962 to somewhere outside the lifetime but still within the loop. This
5963 catches spaghetti code where the execution order is not linear, and
5964 hence the above test fails. Here we assume that the giv lifetime
5965 does not extend from one iteration of the loop to the next, so as
5966 to make the test easier. Since the lifetime isn't known yet,
5967 this requires two loops. See also record_giv above. */
5972 {
5975 {
5978 }
5984 {
5985 /* It is possible for the BIV increment to use the GIV if we
5986 have a cycle. Thus we must be sure to check each insn for
5987 both BIV and GIV uses, and we must check for BIV uses
5988 first. */
5995 {
5997 {
6001 }
6003 }
6004 }
6005 }
6007 /* Now that the lifetime of the giv is known, check for branches
6008 from within the lifetime to outside the lifetime if it is still
6009 replaceable. */
6012 {
6015 {
6028 {
6037 }
6038 }
6039 }
6041 /* If it is replaceable, then save the final value. */
6044 }
6049 }
6050 \f
6051 /* Update the status of whether a giv can derive other givs.
6053 We need to do something special if there is or may be an update to the biv
6054 between the time the giv is defined and the time it is used to derive
6055 another giv.
6057 In addition, a giv that is only conditionally set is not allowed to
6058 derive another giv once a label has been passed.
6060 The cases we look at are when a label or an update to a biv is passed. */
6062 static void
6064 {
6068 rtx tem;
6071 /* Search all IV classes, then all bivs, and finally all givs.
6073 There are three cases we are concerned with. First we have the situation
6074 of a giv that is only updated conditionally. In that case, it may not
6075 derive any givs after a label is passed.
6077 The second case is when a biv update occurs, or may occur, after the
6078 definition of a giv. For certain biv updates (see below) that are
6079 known to occur between the giv definition and use, we can adjust the
6080 giv definition. For others, or when the biv update is conditional,
6081 we must prevent the giv from deriving any other givs. There are two
6082 sub-cases within this case.
6084 If this is a label, we are concerned with any biv update that is done
6085 conditionally, since it may be done after the giv is defined followed by
6086 a branch here (actually, we need to pass both a jump and a label, but
6087 this extra tracking doesn't seem worth it).
6089 If this is a jump, we are concerned about any biv update that may be
6090 executed multiple times. We are actually only concerned about
6091 backward jumps, but it is probably not worth performing the test
6092 on the jump again here.
6094 If this is a biv update, we must adjust the giv status to show that a
6095 subsequent biv update was performed. If this adjustment cannot be done,
6096 the giv cannot derive further givs. */
6102 {
6104 {
6105 /* If cant_derive is already true, there is no point in
6106 checking all of these conditions again. */
6110 /* If this giv is conditionally set and we have passed a label,
6111 it cannot derive anything. */
6115 /* Skip givs that have mult_val == 0, since
6116 they are really invariants. Also skip those that are
6117 replaceable, since we know their lifetime doesn't contain
6118 any biv update. */
6122 /* The only way we can allow this giv to derive another
6123 is if this is a biv increment and we can form the product
6124 of biv->add_val and giv->mult_val. In this case, we will
6125 be able to compute a compensation. */
6127 {
6128 rtx ext_val_dummy;
6139 tem = simplify_giv_expr
6146 else
6148 }
6152 }
6153 }
6154 }
6155 \f
6156 /* Check whether an insn is an increment legitimate for a basic induction var.
6157 X is the source of insn P, or a part of it.
6158 MODE is the mode in which X should be interpreted.
6160 DEST_REG is the putative biv, also the destination of the insn.
6161 We accept patterns of these forms:
6162 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6163 REG = INVARIANT + REG
6165 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6166 store the additive term into *INC_VAL, and store the place where
6167 we found the additive term into *LOCATION.
6169 If X is an assignment of an invariant into DEST_REG, we set
6170 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6172 We also want to detect a BIV when it corresponds to a variable
6173 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6174 of the variable may be a PLUS that adds a SUBREG of that variable to
6175 an invariant and then sign- or zero-extends the result of the PLUS
6176 into the variable.
6178 Most GIVs in such cases will be in the promoted mode, since that is the
6179 probably the natural computation mode (and almost certainly the mode
6180 used for addresses) on the machine. So we view the pseudo-reg containing
6181 the variable as the BIV, as if it were simply incremented.
6183 Note that treating the entire pseudo as a BIV will result in making
6184 simple increments to any GIVs based on it. However, if the variable
6185 overflows in its declared mode but not its promoted mode, the result will
6186 be incorrect. This is acceptable if the variable is signed, since
6187 overflows in such cases are undefined, but not if it is unsigned, since
6188 those overflows are defined. So we only check for SIGN_EXTEND and
6189 not ZERO_EXTEND.
6191 If we cannot find a biv, we return 0. */
6193 static int
6197 {
6205 {
6211 {
6213 }
6218 {
6220 }
6221 else
6234 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6235 handle addition of promoted variables.
6236 ??? The comment at the start of this function is wrong: promoted
6237 variable increments don't look like it says they do. */
6243 /* If this register is assigned in a previous insn, look at its
6244 source, but don't go outside the loop or past a label. */
6246 /* If this sets a register to itself, we would repeat any previous
6247 biv increment if we applied this strategy blindly. */
6253 {
6254 rtx dest;
6255 do
6256 {
6258 }
6287 }
6288 /* Fall through. */
6290 /* Can accept constant setting of biv only when inside inner most loop.
6291 Otherwise, a biv of an inner loop may be incorrectly recognized
6292 as a biv of the outer loop,
6293 causing code to be moved INTO the inner loop. */
6300 /* convert_modes aborts if we try to convert to or from CCmode, so just
6301 exclude that case. It is very unlikely that a condition code value
6302 would be a useful iterator anyways. convert_modes aborts if we try to
6303 convert a float mode to non-float or vice versa too. */
6307 {
6308 /* Possible bug here? Perhaps we don't know the mode of X. */
6312 }
6313 else
6317 /* Ignore this BIV if signed arithmetic overflow is defined. */
6324 /* Similar, since this can be a sign extension. */
6329 ;
6343 location);
6348 }
6349 }
6350 \f
6351 /* A general induction variable (giv) is any quantity that is a linear
6352 function of a basic induction variable,
6353 i.e. giv = biv * mult_val + add_val.
6354 The coefficients can be any loop invariant quantity.
6355 A giv need not be computed directly from the biv;
6356 it can be computed by way of other givs. */
6358 /* Determine whether X computes a giv.
6359 If it does, return a nonzero value
6360 which is the benefit from eliminating the computation of X;
6361 set *SRC_REG to the register of the biv that it is computed from;
6362 set *ADD_VAL and *MULT_VAL to the coefficients,
6363 such that the value of X is biv * mult + add; */
6365 static int
6370 {
6374 /* If this is an invariant, forget it, it isn't a giv. */
6385 {
6388 /* Since this is now an invariant and wasn't before, it must be a giv
6389 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6390 with. */
6397 /* This is equivalent to a BIV. */
6404 /* Either (plus (biv) (invar)) or
6405 (plus (mult (biv) (invar_1)) (invar_2)). */
6407 {
6410 }
6411 else
6412 {
6415 }
6420 /* ADD_VAL is zero. */
6428 }
6430 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6431 unless they are CONST_INT). */
6439 else
6442 /* Always return true if this is a giv so it will be detected as such,
6443 even if the benefit is zero or negative. This allows elimination
6444 of bivs that might otherwise not be eliminated. */
6446 }
6447 \f
6448 /* Given an expression, X, try to form it as a linear function of a biv.
6449 We will canonicalize it to be of the form
6450 (plus (mult (BIV) (invar_1))
6451 (invar_2))
6452 with possible degeneracies.
6454 The invariant expressions must each be of a form that can be used as a
6455 machine operand. We surround then with a USE rtx (a hack, but localized
6456 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6457 routine; it is the caller's responsibility to strip them.
6459 If no such canonicalization is possible (i.e., two biv's are used or an
6460 expression that is neither invariant nor a biv or giv), this routine
6461 returns 0.
6463 For a nonzero return, the result will have a code of CONST_INT, USE,
6464 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6466 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6471 static rtx
6473 {
6478 rtx tem;
6480 /* If this is not an integer mode, or if we cannot do arithmetic in this
6481 mode, this can't be a giv. */
6488 {
6495 /* Put constant last, CONST_INT last if both constant. */
6503 /* Handle addition of zero, then addition of an invariant. */
6508 {
6511 /* Adding two invariants must result in an invariant, so enclose
6512 addition operation inside a USE and return it. */
6522 else
6531 /* biv + invar or mult + invar. Return sum. */
6535 /* (a + invar_1) + invar_2. Associate. */
6536 return
6542 arg1)),
6547 }
6549 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6550 MULT to reduce cases. */
6556 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6557 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6558 Recurse to associate the second PLUS. */
6563 return
6571 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6587 /* Handle "a - b" as "a + b * (-1)". */
6593 constm1_rtx)),
6602 /* Put constant last, CONST_INT last if both constant. */
6607 /* If second argument is not now constant, not giv. */
6611 /* Handle multiply by 0 or 1. */
6619 {
6621 /* biv * invar. Done. */
6625 /* Product of two constants. */
6629 /* invar * invar is a giv, but attempt to simplify it somehow. */
6635 {
6636 /* (invar_0 * invar_1) * invar_2. Associate. */
6643 arg1)),
6645 }
6646 /* Propagate the MULT expressions to the intermost nodes. */
6648 {
6649 /* (invar_0 + invar_1) * invar_2. Distribute. */
6655 arg1),
6659 arg1)),
6661 }
6665 /* (a * invar_1) * invar_2. Associate. */
6671 arg1)),
6675 /* (a + invar_1) * invar_2. Distribute. */
6680 arg1),
6683 arg1)),
6688 }
6691 /* Shift by constant is multiply by power of two. */
6695 return
6704 /* "-a" is "a * (-1)" */
6710 /* "~a" is "-a - 1". Silly, but easy. */
6714 const1_rtx),
6718 /* Already in proper form for invariant. */
6724 /* Conditionally recognize extensions of simple IVs. After we've
6725 computed loop traversal counts and verified the range of the
6726 source IV, we'll reevaluate this as a GIV. */
6728 {
6731 {
6734 }
6735 }
6739 /* If this is a new register, we can't deal with it. */
6743 /* Check for biv or giv. */
6745 {
6749 {
6752 /* Form expression from giv and add benefit. Ensure this giv
6753 can derive another and subtract any needed adjustment if so. */
6755 /* Increasing the benefit here is risky. The only case in which it
6756 is arguably correct is if this is the only use of V. In other
6757 cases, this will artificially inflate the benefit of the current
6758 giv, and lead to suboptimal code. Thus, it is disabled, since
6759 potentially not reducing an only marginally beneficial giv is
6760 less harmful than reducing many givs that are not really
6761 beneficial. */
6762 {
6766 }
6779 {
6782 }
6783 else
6784 {
6787 }
6789 }
6792 do_default:
6793 /* If it isn't an induction variable, and it is invariant, we
6794 may be able to simplify things further by looking through
6795 the bits we just moved outside the loop. */
6797 {
6803 {
6804 /* Ok, we found a match. Substitute and simplify. */
6806 /* If we match another movable, we must use that, as
6807 this one is going away. */
6812 /* If consec is nonzero, this is a member of a group of
6813 instructions that were moved together. We handle this
6814 case only to the point of seeking to the last insn and
6815 looking for a REG_EQUAL. Fail if we don't find one. */
6817 {
6820 do
6821 {
6823 }
6829 }
6830 else
6831 {
6835 }
6838 {
6839 /* What we are most interested in is pointer
6840 arithmetic on invariants -- only take
6841 patterns we may be able to do something with. */
6847 {
6849 benefit);
6852 }
6857 {
6862 }
6863 }
6865 }
6866 }
6868 }
6870 /* Fall through to general case. */
6872 /* If invariant, return as USE (unless CONST_INT).
6873 Otherwise, not giv. */
6878 {
6887 }
6888 else
6890 }
6891 }
6893 /* This routine folds invariants such that there is only ever one
6894 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6896 static rtx
6898 {
6904 {
6907 }
6910 {
6913 }
6914 else
6915 {
6918 }
6919 }
6921 static rtx
6923 {
6925 {
6929 else
6932 }
6935 else
6938 }
6939 \f
6940 /* Help detect a giv that is calculated by several consecutive insns;
6941 for example,
6942 giv = biv * M
6943 giv = giv + A
6944 The caller has already identified the first insn P as having a giv as dest;
6945 we check that all other insns that set the same register follow
6946 immediately after P, that they alter nothing else,
6947 and that the result of the last is still a giv.
6949 The value is 0 if the reg set in P is not really a giv.
6950 Otherwise, the value is the amount gained by eliminating
6951 all the consecutive insns that compute the value.
6953 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6954 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6956 The coefficients of the ultimate giv value are stored in
6957 *MULT_VAL and *ADD_VAL. */
6959 static int
6963 {
6969 rtx temp;
6970 rtx set;
6972 /* Indicate that this is a giv so that we can update the value produced in
6973 each insn of the multi-insn sequence.
6975 This induction structure will be used only by the call to
6976 general_induction_var below, so we can allocate it on our stack.
6977 If this is a giv, our caller will replace the induct var entry with
6978 a new induction structure. */
6999 {
7003 /* If libcall, skip to end of call sequence. */
7014 /* Giv created by equivalent expression. */
7020 {
7024 count--;
7028 }
7030 {
7031 /* Allow insns that set something other than this giv to a
7032 constant. Such insns are needed on machines which cannot
7033 include long constants and should not disqualify a giv. */
7042 }
7043 }
7048 }
7049 \f
7050 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7051 represented by G1. If no such expression can be found, or it is clear that
7052 it cannot possibly be a valid address, 0 is returned.
7054 To perform the computation, we note that
7055 G1 = x * v + a and
7056 G2 = y * v + b
7057 where `v' is the biv.
7059 So G2 = (y/b) * G1 + (b - a*y/x).
7061 Note that MULT = y/x.
7063 Update: A and B are now allowed to be additive expressions such that
7064 B contains all variables in A. That is, computing B-A will not require
7065 subtracting variables. */
7067 static rtx
7069 {
7070 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7075 /* If MULT is not 1, we cannot handle A with non-constants, since we
7076 would then be required to subtract multiples of the registers in A.
7077 This is theoretically possible, and may even apply to some Fortran
7078 constructs, but it is a lot of work and we do not attempt it here. */
7083 /* In general these structures are sorted top to bottom (down the PLUS
7084 chain), but not left to right across the PLUS. If B is a higher
7085 order giv than A, we can strip one level and recurse. If A is higher
7086 order, we'll eventually bail out, but won't know that until the end.
7087 If they are the same, we'll strip one level around this loop. */
7090 {
7102 /* We matched: remove one reg completely. */
7105 /* An alternate match. */
7108 /* An alternate match. */
7110 else
7111 {
7112 /* Indicates an extra register in B. Strip one level from B and
7113 recurse, hoping B was the higher order expression. */
7118 }
7119 }
7121 /* Here we are at the last level of A, go through the cases hoping to
7122 get rid of everything but a constant. */
7125 {
7138 }
7140 {
7142 }
7144 {
7149 }
7151 {
7156 else
7158 }
7163 }
7165 rtx
7167 {
7170 /* The value that G1 will be multiplied by must be a constant integer. Also,
7171 the only chance we have of getting a valid address is if b*c/a (see above
7172 for notation) is also an integer. */
7175 {
7180 }
7183 else
7184 {
7185 /* ??? Find out if the one is a multiple of the other? */
7187 }
7191 {
7192 /* Failed. If we've got a multiplication factor between G1 and G2,
7193 scale G1's addend and try again. */
7195 {
7199 {
7200 HOST_WIDE_INT m;
7204 }
7205 else
7206 {
7208 mult);
7209 }
7212 }
7213 }
7217 /* Form simplified final result. */
7222 else
7227 else
7228 {
7231 {
7235 }
7238 }
7239 }
7240 \f
7241 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7242 represented by G1. This indicates that G2 should be combined with G1 and
7243 that G2 can use (either directly or via an address expression) a register
7244 used to represent G1. */
7246 static rtx
7248 {
7251 /* With the introduction of ext dependent givs, we must care for modes.
7252 G2 must not use a wider mode than G1. */
7262 /* If these givs are identical, they can be combined. We use the results
7263 of express_from because the addends are not in a canonical form, so
7264 rtx_equal_p is a weaker test. */
7265 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7266 combination to be the other way round. */
7269 {
7271 }
7273 /* If G2 can be expressed as a function of G1 and that function is valid
7274 as an address and no more expensive than using a register for G2,
7275 the expression of G2 in terms of G1 can be used. */
7282 }
7283 \f
7284 /* Check each extension dependent giv in this class to see if its
7285 root biv is safe from wrapping in the interior mode, which would
7286 make the giv illegal. */
7288 static void
7290 {
7293 HOST_WIDE_INT start_val;
7299 /* Make sure the iteration data is available. We must have
7300 constants in order to be certain of no overflow. */
7301 /* ??? An unknown iteration count with an increment of +-1
7302 combined with friendly exit tests of against an invariant
7303 value is also amenable to optimization. Not implemented. */
7309 /* Make sure the host can represent the arithmetic. */
7311 {
7313 HOST_WIDE_INT s_end_val;
7325 /* Check for host arithmetic overflow. */
7327 {
7329 HOST_WIDE_INT s_max;
7336 /* Check zero extension of biv ok. */
7338 /* Check for host arithmetic overflow. */
7339 && (neg_incr
7342 /* Check for target arithmetic overflow. */
7343 && (neg_incr
7346 {
7348 }
7350 /* Check sign extension of biv ok. */
7351 /* ??? While it is true that overflow with signed and pointer
7352 arithmetic is undefined, I fear too many programmers don't
7353 keep this fact in mind -- myself included on occasion.
7354 So leave alone with the signed overflow optimizations. */
7356 /* Check for host arithmetic overflow. */
7357 && (neg_incr
7360 /* Check for target arithmetic overflow. */
7361 && (neg_incr
7364 {
7366 }
7367 }
7368 }
7370 /* Invalidate givs that fail the tests. */
7373 {
7378 {
7387 /* We don't know whether this value is being used as either
7388 signed or unsigned, so to safely truncate we must satisfy
7389 both. The initial check here verifies the BIV itself;
7390 once that is successful we may check its range wrt the
7391 derived GIV. */
7393 {
7397 /* We know from the above that both endpoints are nonnegative,
7398 and that there is no wrapping. Verify that both endpoints
7399 are within the (signed) range of the outer mode. */
7402 }
7407 }
7410 {
7412 {
7416 }
7417 }
7418 else
7419 {
7421 {
7426 else
7427 {
7432 else
7434 }
7439 }
7442 }
7443 }
7444 }
7446 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7448 rtx
7450 {
7456 /* Recall that check_ext_dependent_givs verified that the known bounds
7457 of a biv did not overflow or wrap with respect to the extension for
7458 the giv. Therefore, constants need no additional adjustment. */
7462 /* Otherwise, we must adjust the value to compensate for the
7463 differing modes of the biv and the giv. */
7465 }
7466 \f
7467 struct combine_givs_stats
7468 {
7471 };
7473 static int
7475 {
7482 /* Stabilize the sort. */
7486 }
7488 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7489 any other. If so, point SAME to the giv combined with and set NEW_REG to
7490 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7491 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7493 static void
7495 {
7496 /* Additional benefit to add for being combined multiple times. */
7504 /* Count givs, because bl->giv_count is incorrect here. */
7508 giv_count++;
7510 giv_array
7521 {
7523 rtx single_use;
7528 /* If a DEST_REG GIV is used only once, do not allow it to combine
7529 with anything, for in doing so we will gain nothing that cannot
7530 be had by simply letting the GIV with which we would have combined
7531 to be reduced on its own. The losage shows up in particular with
7532 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7533 be seen elsewhere as well. */
7540 /* Add an additional weight for zero addends. */
7545 {
7546 rtx this_combine;
7551 {
7554 }
7555 }
7557 }
7559 /* Iterate, combining until we can't. */
7560 restart:
7564 {
7567 {
7573 }
7575 }
7578 {
7584 /* If it has already been combined, skip. */
7589 {
7592 /* If it has already been combined, skip. */
7594 {
7599 /* For destination, we now may replace by mem expression instead
7600 of register. This changes the costs considerably, so add the
7601 compensation. */
7611 /* ??? The new final_[bg]iv_value code does a much better job
7612 of finding replaceable giv's, and hence this code may no
7613 longer be necessary. */
7617 /* To help optimize the next set of combinations, remove
7618 this giv from the benefits of other potential mates. */
7620 {
7624 }
7631 }
7632 }
7634 /* To help optimize the next set of combinations, remove
7635 this giv from the benefits of other potential mates. */
7637 {
7639 {
7643 }
7647 /* We've finished with this giv, and everything it touched.
7648 Restart the combination so that proper weights for the
7649 rest of the givs are properly taken into account. */
7650 /* ??? Ideally we would compact the arrays at this point, so
7651 as to not cover old ground. But sanely compacting
7652 can_combine is tricky. */
7654 }
7655 }
7657 /* Clean up. */
7660 }
7661 \f
7662 /* Generate sequence for REG = B * M + A. B is the initial value of
7663 the basic induction variable, M a multiplicative constant, A an
7664 additive constant and REG the destination register. */
7666 static rtx
7668 {
7669 rtx seq;
7670 rtx result;
7673 /* Use unsigned arithmetic. */
7681 }
7684 /* Update registers created in insn sequence SEQ. */
7686 static void
7688 {
7689 rtx insn;
7691 /* Update register info for alias analysis. */
7697 {
7700 {
7707 }
7708 }
7712 }
7715 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7716 is the initial value of the basic induction variable, M a
7717 multiplicative constant, A an additive constant and REG the
7718 destination register. */
7720 void
7723 {
7724 rtx seq;
7727 {
7730 }
7732 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7735 /* Increase the lifetime of any invariants moved further in code. */
7742 /* It is possible that the expansion created lots of new registers.
7743 Iterate over the sequence we just created and record them all. */
7745 }
7748 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7749 initial value of the basic induction variable, M a multiplicative
7750 constant, A an additive constant and REG the destination
7751 register. */
7753 void
7755 {
7756 rtx seq;
7758 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7761 /* Increase the lifetime of any invariants moved further in code.
7762 ???? Is this really necessary? */
7769 /* It is possible that the expansion created lots of new registers.
7770 Iterate over the sequence we just created and record them all. */
7772 }
7775 /* Emit insns after loop to set REG = B * M + A. B is the initial
7776 value of the basic induction variable, M a multiplicative constant,
7777 A an additive constant and REG the destination register. */
7779 void
7781 {
7782 rtx seq;
7784 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7789 /* It is possible that the expansion created lots of new registers.
7790 Iterate over the sequence we just created and record them all. */
7792 }
7796 /* Similar to gen_add_mult, but compute cost rather than generating
7797 sequence. */
7799 static int
7801 {
7811 {
7816 }
7819 }
7820 \f
7821 /* Test whether A * B can be computed without
7822 an actual multiply insn. Value is 1 if so.
7824 ??? This function stinks because it generates a ton of wasted RTL
7825 ??? and as a result fragments GC memory to no end. There are other
7826 ??? places in the compiler which are invoked a lot and do the same
7827 ??? thing, generate wasted RTL just to see if something is possible. */
7829 static int
7831 {
7832 rtx tmp;
7835 /* If only one is constant, make it B. */
7839 /* If first constant, both constant, so don't need multiply. */
7843 /* If second not constant, neither is constant, so would need multiply. */
7847 /* One operand is constant, so might not need multiply insn. Generate the
7848 code for the multiply and see if a call or multiply, or long sequence
7849 of insns is generated. */
7858 {
7861 {
7871 {
7874 }
7877 }
7878 }
7888 }
7889 \f
7890 /* Check to see if loop can be terminated by a "decrement and branch until
7891 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7892 Also try reversing an increment loop to a decrement loop
7893 to see if the optimization can be performed.
7894 Value is nonzero if optimization was performed. */
7896 /* This is useful even if the architecture doesn't have such an insn,
7897 because it might change a loops which increments from 0 to n to a loop
7898 which decrements from n to 0. A loop that decrements to zero is usually
7899 faster than one that increments from zero. */
7901 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7902 such as approx_final_value, biv_total_increment, loop_iterations, and
7903 final_[bg]iv_value. */
7905 static int
7907 {
7912 rtx reg;
7913 rtx jump_label;
7914 rtx final_value;
7915 rtx start_value;
7916 rtx new_add_val;
7917 rtx comparison;
7918 rtx before_comparison;
7919 rtx p;
7920 rtx jump;
7921 rtx first_compare;
7926 /* If last insn is a conditional branch, and the insn before tests a
7927 register value, try to optimize it. Otherwise, we can't do anything. */
7936 /* Try to compute whether the compare/branch at the loop end is one or
7937 two instructions. */
7943 else
7946 {
7947 /* If more than one condition is present to control the loop, then
7948 do not proceed, as this function does not know how to rewrite
7949 loop tests with more than one condition.
7951 Look backwards from the first insn in the last comparison
7952 sequence and see if we've got another comparison sequence. */
7954 rtx jump1;
7958 }
7960 /* Check all of the bivs to see if the compare uses one of them.
7961 Skip biv's set more than once because we can't guarantee that
7962 it will be zero on the last iteration. Also skip if the biv is
7963 used between its update and the test insn. */
7966 {
7971 first_compare))
7973 }
7978 /* Look for the case where the basic induction variable is always
7979 nonnegative, and equals zero on the last iteration.
7980 In this case, add a reg_note REG_NONNEG, which allows the
7981 m68k DBRA instruction to be used. */
7989 {
7990 /* Initial value must be greater than 0,
7991 init_val % -dec_value == 0 to ensure that it equals zero on
7992 the last iteration */
7998 {
7999 /* register always nonnegative, add REG_NOTE to branch */
8007 }
8009 /* If the decrement is 1 and the value was tested as >= 0 before
8010 the loop, then we can safely optimize. */
8012 {
8025 {
8033 }
8034 }
8035 }
8038 {
8039 /* Try to change inc to dec, so can apply above optimization. */
8040 /* Can do this if:
8041 all registers modified are induction variables or invariant,
8042 all memory references have non-overlapping addresses
8043 (obviously true if only one write)
8044 allow 2 insns for the compare/jump at the end of the loop. */
8045 /* Also, we must avoid any instructions which use both the reversed
8046 biv and another biv. Such instructions will fail if the loop is
8047 reversed. We meet this condition by requiring that either
8048 no_use_except_counting is true, or else that there is only
8049 one biv. */
8051 /* 1 if the iteration var is used only to count iterations. */
8053 /* 1 if the loop has no memory store, or it has a single memory store
8054 which is reversible. */
8060 {
8064 /* If there are no givs for this biv, and the only exit is the
8065 fall through at the end of the loop, then
8066 see if perhaps there are no uses except to count. */
8070 {
8075 /* An insn that sets the biv is okay. */
8076 ;
8078 /* An insn that doesn't mention the biv is okay. */
8079 ;
8082 {
8083 /* If either of these insns uses the biv and sets a pseudo
8084 that has more than one usage, then the biv has uses
8085 other than counting since it's used to derive a value
8086 that is used more than one time. */
8088 regs);
8090 {
8093 }
8094 }
8095 else
8096 {
8099 }
8100 }
8102 /* A biv has uses besides counting if it is used to set
8103 another biv. */
8107 {
8110 }
8111 }
8114 /* No need to worry about MEMs. */
8115 ;
8117 {
8122 /* If the loop has a single store, and the destination address is
8123 invariant, then we can't reverse the loop, because this address
8124 might then have the wrong value at loop exit.
8125 This would work if the source was invariant also, however, in that
8126 case, the insn should have been moved out of the loop. */
8129 {
8132 /* If we could prove that each of the memory locations
8133 written to was different, then we could reverse the
8134 store -- but we don't presently have any way of
8135 knowing that. */
8138 /* If the store depends on a register that is set after the
8139 store, it depends on the initial value, and is thus not
8140 reversible. */
8142 {
8149 }
8150 }
8151 }
8152 else
8155 /* This code only acts for innermost loops. Also it simplifies
8156 the memory address check by only reversing loops with
8157 zero or one memory access.
8158 Two memory accesses could involve parts of the same array,
8159 and that can't be reversed.
8160 If the biv is used only for counting, than we don't need to worry
8161 about all these things. */
8167 && reversible_mem_store
8172 {
8173 rtx tem;
8175 /* Loop can be reversed. */
8179 /* Now check other conditions:
8181 The increment must be a constant, as must the initial value,
8182 and the comparison code must be LT.
8184 This test can probably be improved since +/- 1 in the constant
8185 can be obtained by changing LT to LE and vice versa; this is
8186 confusing. */
8189 /* for constants, LE gets turned into LT */
8193 {
8204 comparison_const_width
8206 else
8207 comparison_const_width
8211 comparison_sign_mask
8214 /* If the comparison value is not a loop invariant, then we
8215 can not reverse this loop.
8217 ??? If the insns which initialize the comparison value as
8218 a whole compute an invariant result, then we could move
8219 them out of the loop and proceed with loop reversal. */
8227 /* Normalize the initial value if it is an integer and
8228 has no other use except as a counter. This will allow
8229 a few more loops to be reversed. */
8233 {
8235 /* The code below requires comparison_val to be a multiple
8236 of add_val in order to do the loop reversal, so
8237 round up comparison_val to a multiple of add_val.
8238 Since comparison_value is constant, we know that the
8239 current comparison code is LT. */
8241 comparison_val
8243 /* We postpone overflow checks for COMPARISON_VAL here;
8244 even if there is an overflow, we might still be able to
8245 reverse the loop, if converting the loop exit test to
8246 NE is possible. */
8248 }
8250 /* First check if we can do a vanilla loop reversal. */
8252 /* If we have a decrement_and_branch_on_count,
8253 prefer the NE test, since this will allow that
8254 instruction to be generated. Note that we must
8255 use a vanilla loop reversal if the biv is used to
8256 calculate a giv or has a non-counting use. */
8257 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8258 && defined (HAVE_decrement_and_branch_on_count)
8262 #endif
8264 /* Now do postponed overflow checks on COMPARISON_VAL. */
8267 {
8268 /* Register will always be nonnegative, with value
8269 0 on last iteration */
8273 }
8277 {
8280 }
8281 else
8287 /* If the initial value is not zero, or if the comparison
8288 value is not an exact multiple of the increment, then we
8289 can not reverse this loop. */
8292 {
8295 }
8296 else
8297 {
8300 }
8304 /* Reset these in case we normalized the initial value
8305 and comparison value above. */
8308 {
8310 final_value
8312 }
8315 /* Save some info needed to produce the new insns. */
8320 /* Set start_value; if this is not a CONST_INT, we need
8321 to generate a SUB.
8322 Initialize biv to start_value before loop start.
8323 The old initializing insn will be deleted as a
8324 dead store by flow.c. */
8327 {
8330 }
8332 {
8340 start_value
8346 }
8348 {
8351 initial_value);
8355 start_value
8358 }
8359 else
8360 /* We could handle the other cases too, but it'll be
8361 better to have a testcase first. */
8364 /* We may not have a single insn which can increment a reg, so
8365 create a sequence to hold all the insns from expand_inc. */
8374 /* Update biv info to reflect its new status. */
8379 /* Update loop info. */
8388 /* Inc LABEL_NUSES so that delete_insn will
8389 not delete the label. */
8392 /* Emit an insn after the end of the loop to set the biv's
8393 proper exit value if it is used anywhere outside the loop. */
8399 /* Delete compare/branch at end of loop. */
8404 /* Add new compare/branch insn at end of loop. */
8416 ;
8422 {
8424 {
8425 /* Increment of LABEL_NUSES done above. */
8426 /* Register is now always nonnegative,
8427 so add REG_NONNEG note to the branch. */
8430 }
8432 }
8434 /* No insn may reference both the reversed and another biv or it
8435 will fail (see comment near the top of the loop reversal
8436 code).
8437 Earlier on, we have verified that the biv has no use except
8438 counting, or it is the only biv in this function.
8439 However, the code that computes no_use_except_counting does
8440 not verify reg notes. It's possible to have an insn that
8441 references another biv, and has a REG_EQUAL note with an
8442 expression based on the reversed biv. To avoid this case,
8443 remove all REG_EQUAL notes based on the reversed biv
8444 here. */
8447 {
8450 /* If this is a set of a GIV based on the reversed biv, any
8451 REG_EQUAL notes should still be correct. */
8458 {
8463 else
8465 }
8466 }
8468 /* Mark that this biv has been reversed. Each giv which depends
8469 on this biv, and which is also live past the end of the loop
8470 will have to be fixed up. */
8475 {
8479 else
8481 }
8484 }
8485 }
8486 }
8489 }
8490 \f
8491 /* Verify whether the biv BL appears to be eliminable,
8492 based on the insns in the loop that refer to it.
8494 If ELIMINATE_P is nonzero, actually do the elimination.
8496 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8497 determine whether invariant insns should be placed inside or at the
8498 start of the loop. */
8500 static int
8503 {
8506 rtx p;
8508 /* Scan all insns in the loop, stopping if we find one that uses the
8509 biv in a way that we cannot eliminate. */
8512 {
8516 rtx note;
8518 /* If this is a libcall that sets a giv, skip ahead to its end. */
8520 {
8524 {
8529 {
8536 }
8537 }
8538 }
8540 /* Closely examine the insn if the biv is mentioned. */
8545 {
8551 }
8553 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8558 }
8561 {
8566 }
8569 }
8570 \f
8571 /* INSN and REFERENCE are instructions in the same insn chain.
8572 Return nonzero if INSN is first. */
8574 int
8576 {
8580 {
8581 /* Start with test for not first so that INSN == REFERENCE yields not
8582 first. */
8588 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8589 previous insn, hence the <= comparison below does not work if
8590 P is a note. */
8601 }
8602 }
8604 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8605 the offset that we have to take into account due to auto-increment /
8606 div derivation is zero. */
8607 static int
8610 {
8611 /* If the giv V had the auto-inc address optimization applied
8612 to it, and INSN occurs between the giv insn and the biv
8613 insn, then we'd have to adjust the value used here.
8614 This is rare, so we don't bother to make this possible. */
8623 }
8625 /* If BL appears in X (part of the pattern of INSN), see if we can
8626 eliminate its use. If so, return 1. If not, return 0.
8628 If BIV does not appear in X, return 1.
8630 If ELIMINATE_P is nonzero, actually do the elimination.
8631 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8632 Depending on how many items have been moved out of the loop, it
8633 will either be before INSN (when WHERE_INSN is nonzero) or at the
8634 start of the loop (when WHERE_INSN is zero). */
8636 static int
8640 {
8646 #ifdef HAVE_cc0
8648 #endif
8654 {
8656 /* If we haven't already been able to do something with this BIV,
8657 we can't eliminate it. */
8663 /* If this sets the BIV, it is not a problem. */
8667 /* If this is an insn that defines a giv, it is also ok because
8668 it will go away when the giv is reduced. */
8673 #ifdef HAVE_cc0
8675 {
8676 /* Can replace with any giv that was reduced and
8677 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8678 Require a constant for MULT_VAL, so we know it's nonzero.
8679 ??? We disable this optimization to avoid potential
8680 overflows. */
8688 {
8695 /* If the giv has the opposite direction of change,
8696 then reverse the comparison. */
8700 else
8703 /* We can probably test that giv's reduced reg. */
8706 }
8708 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8709 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8710 Require a constant for MULT_VAL, so we know it's nonzero.
8711 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8712 overflow problem. */
8724 {
8731 /* If the giv has the opposite direction of change,
8732 then reverse the comparison. */
8736 else
8740 /* Replace biv with the giv's reduced register. */
8745 /* Insn doesn't support that constant or invariant. Copy it
8746 into a register (it will be a loop invariant.) */
8753 /* Substitute the new register for its invariant value in
8754 the compare expression. */
8758 }
8759 }
8760 #endif
8767 /* See if either argument is the biv. */
8772 else
8776 {
8777 /* First try to replace with any giv that has constant positive
8778 mult_val and constant add_val. We might be able to support
8779 negative mult_val, but it seems complex to do it in general. */
8791 {
8795 /* Don't eliminate if the linear combination that makes up
8796 the giv overflows when it is applied to ARG. */
8798 {
8799 rtx add_val;
8803 else
8809 }
8814 /* Replace biv with the giv's reduced reg. */
8817 /* If all constants are actually constant integers and
8818 the derived constant can be directly placed in the COMPARE,
8819 do so. */
8822 {
8825 }
8826 else
8827 {
8828 /* Otherwise, load it into a register. */
8833 }
8839 }
8841 /* Look for giv with positive constant mult_val and nonconst add_val.
8842 Insert insns to calculate new compare value.
8843 ??? Turn this off due to possible overflow. */
8851 {
8852 rtx tem;
8862 /* Replace biv with giv's reduced register. */
8866 /* Compute value to compare against. */
8870 /* Use it in this insn. */
8874 }
8875 }
8877 {
8879 {
8880 /* Look for giv with constant positive mult_val and nonconst
8881 add_val. Insert insns to compute new compare value.
8882 ??? Turn this off due to possible overflow. */
8889 {
8890 rtx tem;
8900 /* Replace biv with giv's reduced register. */
8904 /* Compute value to compare against. */
8911 }
8912 }
8914 /* This code has problems. Basically, you can't know when
8915 seeing if we will eliminate BL, whether a particular giv
8916 of ARG will be reduced. If it isn't going to be reduced,
8917 we can't eliminate BL. We can try forcing it to be reduced,
8918 but that can generate poor code.
8920 The problem is that the benefit of reducing TV, below should
8921 be increased if BL can actually be eliminated, but this means
8922 we might have to do a topological sort of the order in which
8923 we try to process biv. It doesn't seem worthwhile to do
8924 this sort of thing now. */
8926 #if 0
8927 /* Otherwise the reg compared with had better be a biv. */
8932 /* Look for a pair of givs, one for each biv,
8933 with identical coefficients. */
8935 {
8947 {
8954 /* Replace biv with its giv's reduced reg. */
8956 /* Replace other operand with the other giv's
8957 reduced reg. */
8960 }
8961 }
8962 #endif
8963 }
8965 /* If we get here, the biv can't be eliminated. */
8969 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8970 biv is used in it, since it will be replaced. */
8978 }
8980 /* See if any subexpression fails elimination. */
8983 {
8985 {
8998 }
8999 }
9002 }
9003 \f
9004 /* Return nonzero if the last use of REG
9005 is in an insn following INSN in the same basic block. */
9007 static int
9009 {
9010 rtx n;
9014 {
9017 }
9019 }
9020 \f
9021 /* Called via `note_stores' to record the initial value of a biv. Here we
9022 just record the location of the set and process it later. */
9024 static void
9026 {
9037 /* If this is the first set found, record it. */
9039 {
9042 }
9043 }
9044 \f
9045 /* If any of the registers in X are "old" and currently have a last use earlier
9046 than INSN, update them to have a last use of INSN. Their actual last use
9047 will be the previous insn but it will not have a valid uid_luid so we can't
9048 use it. X must be a source expression only. */
9050 static void
9052 {
9053 /* Check for the case where INSN does not have a valid luid. In this case,
9054 there is no need to modify the regno_last_uid, as this can only happen
9055 when code is inserted after the loop_end to set a pseudo's final value,
9056 and hence this insn will never be the last use of x.
9057 ???? This comment is not correct. See for example loop_givs_reduce.
9058 This may insert an insn before another new insn. */
9062 {
9064 }
9065 else
9066 {
9070 {
9076 }
9077 }
9078 }
9079 \f
9080 /* Given an insn INSN and condition COND, return the condition in a
9081 canonical form to simplify testing by callers. Specifically:
9083 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9084 (2) Both operands will be machine operands; (cc0) will have been replaced.
9085 (3) If an operand is a constant, it will be the second operand.
9086 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9087 for GE, GEU, and LEU.
9089 If the condition cannot be understood, or is an inequality floating-point
9090 comparison which needs to be reversed, 0 will be returned.
9092 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9094 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9095 insn used in locating the condition was found. If a replacement test
9096 of the condition is desired, it should be placed in front of that
9097 insn and we will be sure that the inputs are still valid.
9099 If WANT_REG is nonzero, we wish the condition to be relative to that
9100 register, if possible. Therefore, do not canonicalize the condition
9101 further. */
9103 rtx
9105 rtx want_reg)
9106 {
9109 rtx set;
9110 rtx tem;
9128 /* If we are comparing a register with zero, see if the register is set
9129 in the previous insn to a COMPARE or a comparison operation. Perform
9130 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9131 in cse.c */
9136 {
9137 /* Set nonzero when we find something of interest. */
9140 #ifdef HAVE_cc0
9141 /* If comparison with cc0, import actual comparison from compare
9142 insn. */
9144 {
9155 }
9156 #endif
9158 /* If this is a COMPARE, pick up the two things being compared. */
9160 {
9164 }
9168 /* Go back to the previous insn. Stop if it is not an INSN. We also
9169 stop if it isn't a single set or if it has a REG_INC note because
9170 we don't want to bother dealing with it. */
9184 /* If this is setting OP0, get what it sets it to if it looks
9185 relevant. */
9187 {
9189 #ifdef FLOAT_STORE_FLAG_VALUE
9190 REAL_VALUE_TYPE fsfv;
9191 #endif
9193 /* ??? We may not combine comparisons done in a CCmode with
9194 comparisons not done in a CCmode. This is to aid targets
9195 like Alpha that have an IEEE compliant EQ instruction, and
9196 a non-IEEE compliant BEQ instruction. The use of CCmode is
9197 actually artificial, simply to prevent the combination, but
9198 should not affect other platforms.
9200 However, we must allow VOIDmode comparisons to match either
9201 CCmode or non-CCmode comparison, because some ports have
9202 modeless comparisons inside branch patterns.
9204 ??? This mode check should perhaps look more like the mode check
9205 in simplify_comparison in combine. */
9213 && (STORE_FLAG_VALUE
9216 #ifdef FLOAT_STORE_FLAG_VALUE
9221 #endif
9222 ))
9233 && (STORE_FLAG_VALUE
9236 #ifdef FLOAT_STORE_FLAG_VALUE
9241 #endif
9242 ))
9248 {
9251 }
9252 else
9254 }
9257 /* If this sets OP0, but not directly, we have to give up. */
9261 {
9265 {
9270 }
9275 }
9276 }
9278 /* If constant is first, put it last. */
9282 /* If OP0 is the result of a comparison, we weren't able to find what
9283 was really being compared, so fail. */
9287 /* Canonicalize any ordered comparison with integers involving equality
9288 if we can do computations in the relevant mode and we do not
9289 overflow. */
9294 {
9297 unsigned HOST_WIDE_INT max_val
9301 {
9307 /* When cross-compiling, const_val might be sign-extended from
9308 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9328 }
9329 }
9331 /* Never return CC0; return zero instead. */
9336 }
9338 /* Given a jump insn JUMP, return the condition that will cause it to branch
9339 to its JUMP_LABEL. If the condition cannot be understood, or is an
9340 inequality floating-point comparison which needs to be reversed, 0 will
9341 be returned.
9343 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9344 insn used in locating the condition was found. If a replacement test
9345 of the condition is desired, it should be placed in front of that
9346 insn and we will be sure that the inputs are still valid. */
9348 rtx
9350 {
9351 rtx cond;
9353 rtx set;
9355 /* If this is not a standard conditional jump, we can't parse it. */
9363 /* If this branches to JUMP_LABEL when the condition is false, reverse
9364 the condition. */
9365 reverse
9370 }
9372 /* Similar to above routine, except that we also put an invariant last
9373 unless both operands are invariants. */
9375 rtx
9377 {
9387 }
9389 /* Scan the function and determine whether it has indirect (computed) jumps.
9391 This is taken mostly from flow.c; similar code exists elsewhere
9392 in the compiler. It may be useful to put this into rtlanal.c. */
9393 static int
9395 {
9396 rtx insn;
9403 }
9405 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9406 documentation for LOOP_MEMS for the definition of `appropriate'.
9407 This function is called from prescan_loop via for_each_rtx. */
9409 static int
9411 {
9420 {
9425 /* We're not interested in MEMs that are only clobbered. */
9429 /* We're not interested in the MEM associated with a
9430 CONST_DOUBLE, so there's no need to traverse into this. */
9434 /* We're not interested in any MEMs that only appear in notes. */
9438 /* This is not a MEM. */
9440 }
9442 /* See if we've already seen this MEM. */
9445 {
9447 /* The modes of the two memory accesses are different. If
9448 this happens, something tricky is going on, and we just
9449 don't optimize accesses to this MEM. */
9453 }
9455 /* Resize the array, if necessary. */
9457 {
9460 else
9466 }
9468 /* Actually insert the MEM. */
9470 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9471 because we can't put it in a register. We still store it in the
9472 table, though, so that if we see the same address later, but in a
9473 non-BLK mode, we'll not think we can optimize it at that point. */
9479 }
9482 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9484 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9485 register that is modified by an insn between FROM and TO. If the
9486 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9487 more, stop incrementing it, to avoid overflow.
9489 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9490 register I is used, if it is only used once. Otherwise, it is set
9491 to 0 (for no uses) or const0_rtx for more than one use. This
9492 parameter may be zero, in which case this processing is not done.
9494 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9495 optimize register I. */
9497 static void
9499 {
9502 /* last_set[n] is nonzero iff reg n has been set in the current
9503 basic block. In that case, it is the insn that last set reg n. */
9505 rtx insn;
9511 /* Grow the regs array if not allocated or too small. */
9513 {
9519 /* Zero the new elements. */
9522 }
9524 /* Clear previously scanned fields but do not clear n_times_set. */
9526 {
9530 }
9534 /* Scan the loop, recording register usage. */
9537 {
9539 {
9540 /* Record registers that have exactly one use. */
9543 /* Include uses in REG_EQUAL notes. */
9551 {
9555 last_set);
9556 }
9557 }
9562 /* Invalidate all registers used for function argument passing.
9563 We check rtx_varies_p for the same reason as below, to allow
9564 optimizing PIC calculations. */
9566 {
9567 rtx link;
9569 link;
9571 {
9578 }
9579 }
9580 }
9582 /* Invalidate all hard registers clobbered by calls. With one exception:
9583 a call-clobbered PIC register is still function-invariant for our
9584 purposes, since we can hoist any PIC calculations out of the loop.
9585 Thus the call to rtx_varies_p. */
9590 {
9593 }
9595 #ifdef AVOID_CCMODE_COPIES
9596 /* Don't try to move insns which set CC registers if we should not
9597 create CCmode register copies. */
9601 #endif
9603 /* Set regs->array[I].n_times_set for the new registers. */
9608 }
9610 /* Returns the number of real INSNs in the LOOP. */
9612 static int
9614 {
9616 rtx insn;
9624 }
9626 /* Move MEMs into registers for the duration of the loop. */
9628 static void
9630 {
9637 rtx end_label;
9638 /* Nonzero if the next instruction may never be executed. */
9645 /* We cannot use next_label here because it skips over normal insns. */
9650 /* Check to see if it's possible that some instructions in the loop are
9651 never executed. Also check if there is a goto out of the loop other
9652 than right after the end of the loop. */
9656 {
9660 /* If we enter the loop in the middle, and scan
9661 around to the beginning, don't set maybe_never
9662 for that. This must be an unconditional jump,
9663 otherwise the code at the top of the loop might
9664 never be executed. Unconditional jumps are
9665 followed a by barrier then loop end. */
9670 {
9671 /* If this is a jump outside of the loop but not right
9672 after the end of the loop, we would have to emit new fixup
9673 sequences for each such label. */
9675 JUMP_INSN is executed, we must be conservative. */
9684 /* Something complicated. */
9686 else
9687 /* If there are any more instructions in the loop, they
9688 might not be reached. */
9690 }
9693 }
9695 /* Find start of the extended basic block that enters the loop. */
9699 ;
9704 /* Build table of mems that get set to constant values before the
9705 loop. */
9709 /* Actually move the MEMs. */
9711 {
9712 regset_head load_copies;
9713 regset_head store_copies;
9715 rtx reg;
9717 rtx mem_list_entry;
9721 /* There's no telling whether or not MEM is modified. */
9724 /* Go through the MEMs written to in the loop to see if this
9725 one is aliased by one of them. */
9728 {
9733 {
9734 /* MEM is indeed aliased by this store. */
9737 }
9739 }
9745 /* If this MEM is written to, we must be sure that there
9746 are no reads from another MEM that aliases this one. */
9748 {
9752 {
9756 VOIDmode,
9758 rtx_varies_p))
9759 {
9760 /* It's not safe to hoist loop_info->mems[i] out of
9761 the loop because writes to it might not be
9762 seen by reads from loop_info->mems[j]. */
9765 }
9766 }
9767 }
9770 /* We can't access the MEM outside the loop; it might
9771 cause a trap that wouldn't have happened otherwise. */
9775 /* We thought we were going to lift this MEM out of the
9776 loop, but later discovered that we could not. */
9782 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9783 order to keep scan_loop from moving stores to this MEM
9784 out of the loop just because this REG is neither a
9785 user-variable nor used in the loop test. */
9790 /* Now, replace all references to the MEM with the
9791 corresponding pseudos. */
9796 {
9798 {
9799 rtx set;
9803 /* See if this copies the mem into a register that isn't
9804 modified afterwards. We'll try to do copy propagation
9805 a little further on. */
9807 /* @@@ This test is _way_ too conservative. */
9808 && ! maybe_never
9816 /* See if this copies the mem from a register that isn't
9817 modified afterwards. We'll try to remove the
9818 redundant copy later on by doing a little register
9819 renaming and copy propagation. This will help
9820 to untangle things for the BIV detection code. */
9822 && ! maybe_never
9830 /* If this is a call which uses / clobbers this memory
9831 location, we must not change the interface here. */
9835 {
9839 }
9840 else
9841 /* Replace the memory reference with the shadow register. */
9844 }
9849 }
9854 /* We couldn't replace all occurrences of the MEM. */
9856 else
9857 {
9858 /* Load the memory immediately before LOOP->START, which is
9859 the NOTE_LOOP_BEG. */
9861 rtx set;
9867 {
9871 {
9875 /* Extending hard register lifetimes causes crash
9876 on SRC targets. Doing so on non-SRC is
9877 probably also not good idea, since we most
9878 probably have pseudoregister equivalence as
9879 well. */
9882 }
9883 /* Use the constant equivalence if that is cheap enough. */
9889 {
9892 }
9894 /* If best_equiv is nonzero, we know that MEM is set to a
9895 constant or register before the loop. We will use this
9896 knowledge to initialize the shadow register with that
9897 constant or reg rather than by loading from MEM. */
9900 }
9905 {
9908 {
9911 }
9912 }
9918 {
9920 {
9923 }
9925 /* Store the memory immediately after END, which is
9926 the NOTE_LOOP_END. */
9929 }
9932 {
9937 }
9939 /* Attempt a bit of copy propagation. This helps untangle the
9940 data flow, and enables {basic,general}_induction_var to find
9941 more bivs/givs. */
9942 EXECUTE_IF_SET_IN_REG_SET
9944 {
9946 });
9949 EXECUTE_IF_SET_IN_REG_SET
9951 {
9953 });
9955 }
9956 }
9959 {
9960 /* Now, we need to replace all references to the previous exit
9961 label with the new one. */
9962 replace_label_data rr;
9968 {
9970 }
9971 }
9974 }
9976 /* For communication between note_reg_stored and its caller. */
9977 struct note_reg_stored_arg
9978 {
9980 rtx reg;
9981 };
9983 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9984 is equal to ARG. */
9985 static void
9987 {
9991 }
9993 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9994 There must be exactly one insn that sets this pseudo; it will be
9995 deleted if all replacements succeed and we can prove that the register
9996 is not used after the loop. */
9998 static void
10000 {
10001 /* This is the reg that we are copying from. */
10004 rtx insn;
10005 /* These help keep track of whether we replaced all uses of the reg. */
10012 {
10013 rtx set;
10015 /* Only substitute within one extended basic block from the initializing
10016 insn. */
10023 /* Is this the initializing insn? */
10028 {
10035 }
10037 /* Only substitute after seeing the initializing insn. */
10039 {
10046 /* Stop replacing when REPLACEMENT is modified. */
10051 {
10054 /* It is possible that we've turned previously valid REG_EQUAL to
10055 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10056 REPLACEMENT is modified, we get different meaning. */
10060 }
10061 }
10062 }
10066 {
10070 {
10071 rtx first;
10072 rtx retval_note;
10074 /* Assume we're just deleting INIT_INSN. */
10076 /* Look for REG_RETVAL note. If we're deleting the end of
10077 the libcall sequence, the whole sequence can go. */
10079 /* If we found a REG_RETVAL note, find the first instruction
10080 in the sequence. */
10084 /* Delete the instructions. */
10086 }
10089 }
10090 }
10092 /* Replace all the instructions from FIRST up to and including LAST
10093 with NOTE_INSN_DELETED notes. */
10095 static void
10097 {
10099 {
10105 /* If this was the LAST instructions we're supposed to delete,
10106 we're done. */
10111 }
10112 }
10114 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10115 loop LOOP if the order of the sets of these registers can be
10116 swapped. There must be exactly one insn within the loop that sets
10117 this pseudo followed immediately by a move insn that sets
10118 REPLACEMENT with REGNO. */
10119 static void
10122 {
10123 rtx insn;
10132 {
10133 /* Search for the insn that copies REGNO to NEW_REGNO? */
10141 }
10144 {
10145 rtx prev_insn;
10146 rtx prev_set;
10148 /* Some DEF-USE info would come in handy here to make this
10149 function more general. For now, just check the previous insn
10150 which is the most likely candidate for setting REGNO. */
10158 {
10159 /* We have:
10160 (set (reg regno) (expr))
10161 (set (reg new_regno) (reg regno))
10163 so try converting this to:
10164 (set (reg new_regno) (expr))
10165 (set (reg regno) (reg new_regno))
10167 The former construct is often generated when a global
10168 variable used for an induction variable is shadowed by a
10169 register (NEW_REGNO). The latter construct improves the
10170 chances of GIV replacement and BIV elimination. */
10180 {
10187 /* Update first use of REGNO. */
10191 /* Now perform copy propagation to hopefully
10192 remove all uses of REGNO within the loop. */
10194 }
10195 }
10196 }
10197 }
10199 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10201 static int
10203 {
10205 {
10209 }
10211 }
10213 /* Returns the first MEM found in NOTE by depth-first search. */
10215 static rtx
10217 {
10221 }
10223 /* Replace MEM with its associated pseudo register. This function is
10224 called from load_mems via for_each_rtx. DATA is actually a pointer
10225 to a structure describing the instruction currently being scanned
10226 and the MEM we are currently replacing. */
10228 static int
10230 {
10238 {
10243 /* We're not interested in the MEM associated with a
10244 CONST_DOUBLE, so there's no need to traverse into one. */
10248 /* This is not a MEM. */
10250 }
10253 /* This is not the MEM we are currently replacing. */
10256 /* Actually replace the MEM. */
10260 }
10262 static void
10264 {
10265 loop_replace_args args;
10273 /* If we hoist a mem write out of the loop, then REG_EQUAL
10274 notes referring to the mem are no longer valid. */
10276 {
10281 {
10285 {
10286 /* Remove the note. */
10289 }
10290 }
10291 }
10292 }
10294 /* Replace one register with another. Called through for_each_rtx; PX points
10295 to the rtx being scanned. DATA is actually a pointer to
10296 a structure of arguments. */
10298 static int
10300 {
10311 }
10313 static void
10315 {
10316 loop_replace_args args;
10323 }
10324 \f
10325 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10326 (ignored in the interim). */
10328 static rtx
10331 rtx pattern)
10332 {
10334 }
10337 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10338 in basic block WHERE_BB (ignored in the interim) within the loop
10339 otherwise hoist PATTERN into the loop pre-header. */
10341 rtx
10343 basic_block where_bb ATTRIBUTE_UNUSED,
10345 {
10349 }
10352 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10353 WHERE_BB (ignored in the interim) within the loop. */
10355 static rtx
10357 basic_block where_bb ATTRIBUTE_UNUSED,
10359 {
10361 }
10364 /* Hoist insn for PATTERN into the loop pre-header. */
10366 rtx
10368 {
10370 }
10373 /* Hoist call insn for PATTERN into the loop pre-header. */
10375 static rtx
10377 {
10379 }
10382 /* Sink insn for PATTERN after the loop end. */
10384 rtx
10386 {
10388 }
10390 /* bl->final_value can be either general_operand or PLUS of general_operand
10391 and constant. Emit sequence of instructions to load it into REG. */
10392 static rtx
10394 {
10395 rtx seq;
10403 }
10405 /* If the loop has multiple exits, emit insn for PATTERN before the
10406 loop to ensure that it will always be executed no matter how the
10407 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10408 since this is slightly more efficient. */
10410 static rtx
10412 {
10415 else
10417 }
10418 \f
10419 static void
10421 {
10429 iv_num++;
10434 {
10437 }
10438 }
10441 static void
10444 {
10446 rtx incr;
10457 {
10460 }
10462 {
10465 }
10469 {
10473 }
10476 {
10480 }
10482 /* List the increments. */
10484 {
10488 }
10490 /* List the givs. */
10492 {
10497 else
10500 }
10501 }
10504 static void
10506 {
10517 {
10521 }
10524 }
10527 static void
10529 {
10536 else
10552 {
10554 {
10566 }
10567 }
10578 {
10582 }
10585 }
10588 void
10590 {
10592 }
10595 void
10597 {
10599 }
10602 void
10604 {
10606 }
10609 void
10611 {
10613 }
10616 #define LOOP_BLOCK_NUM_1(INSN) \
10617 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10619 /* The notes do not have an assigned block, so look at the next insn. */
10620 #define LOOP_BLOCK_NUM(INSN) \
10621 ((INSN) ? (GET_CODE (INSN) == NOTE \
10622 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10623 : LOOP_BLOCK_NUM_1 (INSN)) \
10624 : -1)
10626 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10628 static void
10631 {
10632 rtx label;
10637 /* Print diagnostics to compare our concept of a loop with
10638 what the loop notes say. */
10653 {
10673 {
10676 {
10679 }
10680 }
10683 /* This can happen when a marked loop appears as two nested loops,
10684 say from while (a || b) {}. The inner loop won't match
10685 the loop markers but the outer one will. */
10688 }
10689 }
10691 /* Call this function from the debugger to dump LOOP. */
10693 void
10695 {
10697 }
10699 /* Call this function from the debugger to dump LOOPS. */
10701 void
10703 {
10705 }