| blob | 8dab1909cc470e837a0ef6007261e0cef63ede68 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
89 #ifndef CHECK_STACK_LIMIT
90 #define CHECK_STACK_LIMIT (-1)
91 #endif
93 /* Return index of given mode in mult and division cost tables. */
94 #define MODE_INDEX(mode) \
95 ((mode) == QImode ? 0 \
96 : (mode) == HImode ? 1 \
97 : (mode) == SImode ? 2 \
98 : (mode) == DImode ? 3 \
99 : 4)
101 /* Processor costs (relative to an add) */
102 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
103 #define COSTS_N_BYTES(N) ((N) * 2)
105 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
114 const
137 in QImode, HImode and SImode.
138 Relative to reg-reg move (2). */
142 in SFmode, DFmode and XFmode */
144 in SFmode, DFmode and XFmode */
147 in SImode and DImode */
149 in SImode and DImode */
152 in SImode, DImode and TImode */
154 in SImode, DImode and TImode */
167 ix86_size_memcpy,
168 ix86_size_memset,
180 };
182 /* Processor costs (relative to an add) */
185 DUMMY_STRINGOP_ALGS};
188 DUMMY_STRINGOP_ALGS};
190 static const
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
218 in SFmode, DFmode and XFmode */
220 in SFmode, DFmode and XFmode */
223 in SImode and DImode */
225 in SImode and DImode */
228 in SImode, DImode and TImode */
230 in SImode, DImode and TImode */
243 i386_memcpy,
244 i386_memset,
256 };
260 DUMMY_STRINGOP_ALGS};
263 DUMMY_STRINGOP_ALGS};
265 static const
288 in QImode, HImode and SImode.
289 Relative to reg-reg move (2). */
293 in SFmode, DFmode and XFmode */
295 in SFmode, DFmode and XFmode */
298 in SImode and DImode */
300 in SImode and DImode */
303 in SImode, DImode and TImode */
305 in SImode, DImode and TImode */
308 shared for code and data, so 4kB is
309 not really precise. */
320 i486_memcpy,
321 i486_memset,
333 };
337 DUMMY_STRINGOP_ALGS};
340 DUMMY_STRINGOP_ALGS};
342 static const
365 in QImode, HImode and SImode.
366 Relative to reg-reg move (2). */
370 in SFmode, DFmode and XFmode */
372 in SFmode, DFmode and XFmode */
375 in SImode and DImode */
377 in SImode and DImode */
380 in SImode, DImode and TImode */
382 in SImode, DImode and TImode */
395 pentium_memcpy,
396 pentium_memset,
408 };
410 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
411 (we ensure the alignment). For small blocks inline loop is still a
412 noticeable win, for bigger blocks either rep movsl or rep movsb is
413 way to go. Rep movsb has apparently more expensive startup time in CPU,
414 but after 4K the difference is down in the noise. */
419 DUMMY_STRINGOP_ALGS};
424 DUMMY_STRINGOP_ALGS};
425 static const
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
453 in SFmode, DFmode and XFmode */
455 in SFmode, DFmode and XFmode */
458 in SImode and DImode */
460 in SImode and DImode */
463 in SImode, DImode and TImode */
465 in SImode, DImode and TImode */
478 pentiumpro_memcpy,
479 pentiumpro_memset,
491 };
495 DUMMY_STRINGOP_ALGS};
498 DUMMY_STRINGOP_ALGS};
499 static const
522 in QImode, HImode and SImode.
523 Relative to reg-reg move (2). */
527 in SFmode, DFmode and XFmode */
529 in SFmode, DFmode and XFmode */
533 in SImode and DImode */
535 in SImode and DImode */
538 in SImode, DImode and TImode */
540 in SImode, DImode and TImode */
553 geode_memcpy,
554 geode_memset,
566 };
570 DUMMY_STRINGOP_ALGS};
573 DUMMY_STRINGOP_ALGS};
574 static const
597 in QImode, HImode and SImode.
598 Relative to reg-reg move (2). */
602 in SFmode, DFmode and XFmode */
604 in SFmode, DFmode and XFmode */
607 in SImode and DImode */
609 in SImode and DImode */
612 in SImode, DImode and TImode */
614 in SImode, DImode and TImode */
618 have integrated l2 cache, but
619 optimizing for k6 is not important
620 enough to worry about that. */
630 k6_memcpy,
631 k6_memset,
643 };
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
650 DUMMY_STRINGOP_ALGS};
653 DUMMY_STRINGOP_ALGS};
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
707 athlon_memcpy,
708 athlon_memset,
720 };
722 /* K8 has optimized REP instruction for medium sized blocks, but for very
723 small blocks it is better to use loop. For large blocks, libcall can
724 do nontemporary accesses and beat inline considerably. */
735 static const
758 in QImode, HImode and SImode.
759 Relative to reg-reg move (2). */
763 in SFmode, DFmode and XFmode */
765 in SFmode, DFmode and XFmode */
768 in SImode and DImode */
770 in SImode and DImode */
773 in SImode, DImode and TImode */
775 in SImode, DImode and TImode */
780 /* New AMD processors never drop prefetches; if they cannot be performed
781 immediately, they are queued. We set number of simultaneous prefetches
782 to a large constant to reflect this (it probably is not a good idea not
783 to limit number of prefetches at all, as their execution also takes some
784 time). */
794 k8_memcpy,
795 k8_memset,
807 };
809 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
810 very small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
863 /* On K8:
864 MOVD reg64, xmmreg Double FSTORE 4
865 MOVD reg32, xmmreg Double FSTORE 4
866 On AMDFAM10:
867 MOVD reg64, xmmreg Double FADD 3
868 1/1 1/1
869 MOVD reg32, xmmreg Double FADD 3
870 1/1 1/1 */
874 /* New AMD processors never drop prefetches; if they cannot be performed
875 immediately, they are queued. We set number of simultaneous prefetches
876 to a large constant to reflect this (it probably is not a good idea not
877 to limit number of prefetches at all, as their execution also takes some
878 time). */
888 amdfam10_memcpy,
889 amdfam10_memset,
901 };
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
939 in QImode, HImode and SImode.
940 Relative to reg-reg move (2). */
944 in SFmode, DFmode and XFmode */
946 in SFmode, DFmode and XFmode */
949 in SImode and DImode */
951 in SImode and DImode */
954 in SImode, DImode and TImode */
956 in SImode, DImode and TImode */
958 /* On K8:
959 MOVD reg64, xmmreg Double FSTORE 4
960 MOVD reg32, xmmreg Double FSTORE 4
961 On AMDFAM10:
962 MOVD reg64, xmmreg Double FADD 3
963 1/1 1/1
964 MOVD reg32, xmmreg Double FADD 3
965 1/1 1/1 */
969 /* New AMD processors never drop prefetches; if they cannot be performed
970 immediately, they are queued. We set number of simultaneous prefetches
971 to a large constant to reflect this (it probably is not a good idea not
972 to limit number of prefetches at all, as their execution also takes some
973 time). */
983 bdver1_memcpy,
984 bdver1_memset,
996 };
998 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
999 very small blocks it is better to use loop. For large blocks, libcall
1000 can do nontemporary accesses and beat inline considerably. */
1035 in QImode, HImode and SImode.
1036 Relative to reg-reg move (2). */
1040 in SFmode, DFmode and XFmode */
1042 in SFmode, DFmode and XFmode */
1045 in SImode and DImode */
1047 in SImode and DImode */
1050 in SImode, DImode and TImode */
1052 in SImode, DImode and TImode */
1054 /* On K8:
1055 MOVD reg64, xmmreg Double FSTORE 4
1056 MOVD reg32, xmmreg Double FSTORE 4
1057 On AMDFAM10:
1058 MOVD reg64, xmmreg Double FADD 3
1059 1/1 1/1
1060 MOVD reg32, xmmreg Double FADD 3
1061 1/1 1/1 */
1065 /* New AMD processors never drop prefetches; if they cannot be performed
1066 immediately, they are queued. We set number of simultaneous prefetches
1067 to a large constant to reflect this (it probably is not a good idea not
1068 to limit number of prefetches at all, as their execution also takes some
1069 time). */
1079 bdver2_memcpy,
1080 bdver2_memset,
1092 };
1095 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1096 very small blocks it is better to use loop. For large blocks, libcall
1097 can do nontemporary accesses and beat inline considerably. */
1130 in QImode, HImode and SImode.
1131 Relative to reg-reg move (2). */
1135 in SFmode, DFmode and XFmode */
1137 in SFmode, DFmode and XFmode */
1140 in SImode and DImode */
1142 in SImode and DImode */
1145 in SImode, DImode and TImode */
1147 in SImode, DImode and TImode */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver3_memcpy,
1167 bdver3_memset,
1179 };
1181 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1182 very small blocks it is better to use loop. For large blocks, libcall
1183 can do nontemporary accesses and beat inline considerably. */
1216 in QImode, HImode and SImode.
1217 Relative to reg-reg move (2). */
1221 in SFmode, DFmode and XFmode */
1223 in SFmode, DFmode and XFmode */
1226 in SImode and DImode */
1228 in SImode and DImode */
1231 in SImode, DImode and TImode */
1233 in SImode, DImode and TImode */
1238 /* New AMD processors never drop prefetches; if they cannot be performed
1239 immediately, they are queued. We set number of simultaneous prefetches
1240 to a large constant to reflect this (it probably is not a good idea not
1241 to limit number of prefetches at all, as their execution also takes some
1242 time). */
1252 bdver4_memcpy,
1253 bdver4_memset,
1265 };
1267 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1268 very small blocks it is better to use loop. For large blocks, libcall can
1269 do nontemporary accesses and beat inline considerably. */
1302 in QImode, HImode and SImode.
1303 Relative to reg-reg move (2). */
1307 in SFmode, DFmode and XFmode */
1309 in SFmode, DFmode and XFmode */
1312 in SImode and DImode */
1314 in SImode and DImode */
1317 in SImode, DImode and TImode */
1319 in SImode, DImode and TImode */
1321 /* On K8:
1322 MOVD reg64, xmmreg Double FSTORE 4
1323 MOVD reg32, xmmreg Double FSTORE 4
1324 On AMDFAM10:
1325 MOVD reg64, xmmreg Double FADD 3
1326 1/1 1/1
1327 MOVD reg32, xmmreg Double FADD 3
1328 1/1 1/1 */
1341 btver1_memcpy,
1342 btver1_memset,
1354 };
1388 in QImode, HImode and SImode.
1389 Relative to reg-reg move (2). */
1393 in SFmode, DFmode and XFmode */
1395 in SFmode, DFmode and XFmode */
1398 in SImode and DImode */
1400 in SImode and DImode */
1403 in SImode, DImode and TImode */
1405 in SImode, DImode and TImode */
1407 /* On K8:
1408 MOVD reg64, xmmreg Double FSTORE 4
1409 MOVD reg32, xmmreg Double FSTORE 4
1410 On AMDFAM10:
1411 MOVD reg64, xmmreg Double FADD 3
1412 1/1 1/1
1413 MOVD reg32, xmmreg Double FADD 3
1414 1/1 1/1 */
1426 btver2_memcpy,
1427 btver2_memset,
1439 };
1443 DUMMY_STRINGOP_ALGS};
1447 DUMMY_STRINGOP_ALGS};
1449 static const
1472 in QImode, HImode and SImode.
1473 Relative to reg-reg move (2). */
1477 in SFmode, DFmode and XFmode */
1479 in SFmode, DFmode and XFmode */
1482 in SImode and DImode */
1484 in SImode and DImode */
1487 in SImode, DImode and TImode */
1489 in SImode, DImode and TImode */
1502 pentium4_memcpy,
1503 pentium4_memset,
1515 };
1528 static const
1551 in QImode, HImode and SImode.
1552 Relative to reg-reg move (2). */
1556 in SFmode, DFmode and XFmode */
1558 in SFmode, DFmode and XFmode */
1561 in SImode and DImode */
1563 in SImode and DImode */
1566 in SImode, DImode and TImode */
1568 in SImode, DImode and TImode */
1581 nocona_memcpy,
1582 nocona_memset,
1594 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 atom_memcpy,
1659 atom_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 slm_memcpy,
1736 slm_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 intel_memcpy,
1813 intel_memset,
1825 };
1827 /* Generic should produce code tuned for Core-i7 (and newer chips)
1828 and btver1 (and newer chips). */
1840 static const
1843 /* On all chips taken into consideration lea is 2 cycles and more. With
1844 this cost however our current implementation of synth_mult results in
1845 use of unnecessary temporary registers causing regression on several
1846 SPECfp benchmarks. */
1867 in QImode, HImode and SImode.
1868 Relative to reg-reg move (2). */
1872 in SFmode, DFmode and XFmode */
1874 in SFmode, DFmode and XFmode */
1877 in SImode and DImode */
1879 in SImode and DImode */
1882 in SImode, DImode and TImode */
1884 in SImode, DImode and TImode */
1890 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1891 value is increased to perhaps more appropriate value of 5. */
1899 generic_memcpy,
1900 generic_memset,
1912 };
1914 /* core_cost should produce code tuned for Core familly of CPUs. */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* FIXME perhaps more appropriate value is 5. */
1985 core_memcpy,
1986 core_memset,
1998 };
2001 /* Set by -mtune. */
2004 /* Set by -mtune or -Os. */
2007 /* Processor feature/optimization bitmasks. */
2008 #define m_386 (1<<PROCESSOR_I386)
2009 #define m_486 (1<<PROCESSOR_I486)
2010 #define m_PENT (1<<PROCESSOR_PENTIUM)
2011 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2012 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2013 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2014 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2015 #define m_CORE2 (1<<PROCESSOR_CORE2)
2016 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2017 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2018 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2019 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2020 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2021 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2022 #define m_INTEL (1<<PROCESSOR_INTEL)
2024 #define m_GEODE (1<<PROCESSOR_GEODE)
2025 #define m_K6 (1<<PROCESSOR_K6)
2026 #define m_K6_GEODE (m_K6 | m_GEODE)
2027 #define m_K8 (1<<PROCESSOR_K8)
2028 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2029 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2030 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2031 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2032 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2033 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2034 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2035 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2036 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2037 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2038 #define m_BTVER (m_BTVER1 | m_BTVER2)
2039 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2041 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2044 #undef DEF_TUNE
2045 #define DEF_TUNE(tune, name, selector) name,
2047 #undef DEF_TUNE
2048 };
2050 /* Feature tests against the various tunings. */
2053 /* Feature tests against the various tunings used to create ix86_tune_features
2054 based on the processor mask. */
2056 #undef DEF_TUNE
2057 #define DEF_TUNE(tune, name, selector) selector,
2059 #undef DEF_TUNE
2060 };
2062 /* Feature tests against the various architecture variations. */
2065 /* Feature tests against the various architecture variations, used to create
2066 ix86_arch_features based on the processor mask. */
2068 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2071 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2074 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2077 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2080 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2082 };
2084 /* In case the average insn count for single function invocation is
2085 lower than this constant, emit fast (but longer) prologue and
2086 epilogue code. */
2087 #define FAST_PROLOGUE_INSN_COUNT 20
2089 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2094 /* Array of the smallest class containing reg number REGNO, indexed by
2095 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2098 {
2099 /* ax, dx, cx, bx */
2101 /* si, di, bp, sp */
2103 /* FP registers */
2106 /* arg pointer */
2107 NON_Q_REGS,
2108 /* flags, fpsr, fpcr, frame */
2110 /* SSE registers */
2113 /* MMX registers */
2116 /* REX registers */
2119 /* SSE REX registers */
2122 /* AVX-512 SSE registers */
2127 /* Mask registers. */
2130 };
2132 /* The "default" register map used in 32bit mode. */
2135 {
2146 };
2148 /* The "default" register map used in 64bit mode. */
2151 {
2162 };
2164 /* Define the register numbers to be used in Dwarf debugging information.
2165 The SVR4 reference port C compiler uses the following register numbers
2166 in its Dwarf output code:
2167 0 for %eax (gcc regno = 0)
2168 1 for %ecx (gcc regno = 2)
2169 2 for %edx (gcc regno = 1)
2170 3 for %ebx (gcc regno = 3)
2171 4 for %esp (gcc regno = 7)
2172 5 for %ebp (gcc regno = 6)
2173 6 for %esi (gcc regno = 4)
2174 7 for %edi (gcc regno = 5)
2175 The following three DWARF register numbers are never generated by
2176 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2177 believes these numbers have these meanings.
2178 8 for %eip (no gcc equivalent)
2179 9 for %eflags (gcc regno = 17)
2180 10 for %trapno (no gcc equivalent)
2181 It is not at all clear how we should number the FP stack registers
2182 for the x86 architecture. If the version of SDB on x86/svr4 were
2183 a bit less brain dead with respect to floating-point then we would
2184 have a precedent to follow with respect to DWARF register numbers
2185 for x86 FP registers, but the SDB on x86/svr4 is so completely
2186 broken with respect to FP registers that it is hardly worth thinking
2187 of it as something to strive for compatibility with.
2188 The version of x86/svr4 SDB I have at the moment does (partially)
2189 seem to believe that DWARF register number 11 is associated with
2190 the x86 register %st(0), but that's about all. Higher DWARF
2191 register numbers don't seem to be associated with anything in
2192 particular, and even for DWARF regno 11, SDB only seems to under-
2193 stand that it should say that a variable lives in %st(0) (when
2194 asked via an `=' command) if we said it was in DWARF regno 11,
2195 but SDB still prints garbage when asked for the value of the
2196 variable in question (via a `/' command).
2197 (Also note that the labels SDB prints for various FP stack regs
2198 when doing an `x' command are all wrong.)
2199 Note that these problems generally don't affect the native SVR4
2200 C compiler because it doesn't allow the use of -O with -g and
2201 because when it is *not* optimizing, it allocates a memory
2202 location for each floating-point variable, and the memory
2203 location is what gets described in the DWARF AT_location
2204 attribute for the variable in question.
2205 Regardless of the severe mental illness of the x86/svr4 SDB, we
2206 do something sensible here and we use the following DWARF
2207 register numbers. Note that these are all stack-top-relative
2208 numbers.
2209 11 for %st(0) (gcc regno = 8)
2210 12 for %st(1) (gcc regno = 9)
2211 13 for %st(2) (gcc regno = 10)
2212 14 for %st(3) (gcc regno = 11)
2213 15 for %st(4) (gcc regno = 12)
2214 16 for %st(5) (gcc regno = 13)
2215 17 for %st(6) (gcc regno = 14)
2216 18 for %st(7) (gcc regno = 15)
2217 */
2219 {
2230 };
2232 /* Define parameter passing and return registers. */
2235 {
2237 };
2240 {
2242 };
2245 {
2247 };
2249 /* Additional registers that are clobbered by SYSV calls. */
2252 {
2257 };
2259 /* Define the structure for the machine field in struct function. */
2264 rtx rtl;
2266 };
2268 /* Structure describing stack frame layout.
2269 Stack grows downward:
2271 [arguments]
2272 <- ARG_POINTER
2273 saved pc
2275 saved static chain if ix86_static_chain_on_stack
2277 saved frame pointer if frame_pointer_needed
2278 <- HARD_FRAME_POINTER
2279 [saved regs]
2280 <- regs_save_offset
2281 [padding0]
2283 [saved SSE regs]
2284 <- sse_regs_save_offset
2285 [padding1] |
2286 | <- FRAME_POINTER
2287 [va_arg registers] |
2288 |
2289 [frame] |
2290 |
2291 [padding2] | = to_allocate
2292 <- STACK_POINTER
2293 */
2294 struct ix86_frame
2295 {
2302 /* The offsets relative to ARG_POINTER. */
2303 HOST_WIDE_INT frame_pointer_offset;
2304 HOST_WIDE_INT hard_frame_pointer_offset;
2305 HOST_WIDE_INT stack_pointer_offset;
2306 HOST_WIDE_INT hfp_save_offset;
2307 HOST_WIDE_INT reg_save_offset;
2308 HOST_WIDE_INT sse_reg_save_offset;
2310 /* When save_regs_using_mov is set, emit prologue using
2311 move instead of push instructions. */
2313 };
2315 /* Which cpu are we scheduling for. */
2318 /* Which cpu are we optimizing for. */
2321 /* Which instruction set architecture to use. */
2324 /* True if processor has SSE prefetch instruction. */
2327 /* -mstackrealign option */
2344 /* Preferred alignment for stack boundary in bits. */
2347 /* Alignment for incoming stack boundary in bits specified at
2348 command line. */
2351 /* Default alignment for incoming stack boundary in bits. */
2354 /* Alignment for incoming stack boundary in bits. */
2357 /* Calling abi specific va_list type nodes. */
2361 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2365 /* Fence to use after loop using movnt. */
2366 tree x86_mfence;
2368 /* Register class used for passing given 64bit part of the argument.
2369 These represent classes as documented by the PS ABI, with the exception
2370 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2371 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2373 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2374 whenever possible (upper half does contain padding). */
2375 enum x86_64_reg_class
2376 {
2377 X86_64_NO_CLASS,
2378 X86_64_INTEGER_CLASS,
2379 X86_64_INTEGERSI_CLASS,
2380 X86_64_SSE_CLASS,
2381 X86_64_SSESF_CLASS,
2382 X86_64_SSEDF_CLASS,
2383 X86_64_SSEUP_CLASS,
2384 X86_64_X87_CLASS,
2385 X86_64_X87UP_CLASS,
2386 X86_64_COMPLEX_X87_CLASS,
2387 X86_64_MEMORY_CLASS
2388 };
2390 #define MAX_CLASSES 8
2392 /* Table of constants used by fldpi, fldln2, etc.... */
2396 \f
2401 const_tree);
2413 enum ix86_function_specific_strings
2414 {
2415 IX86_FUNCTION_SPECIFIC_ARCH,
2416 IX86_FUNCTION_SPECIFIC_TUNE,
2417 IX86_FUNCTION_SPECIFIC_MAX
2418 };
2439 \f
2440 #ifndef SUBTARGET32_DEFAULT_CPU
2442 #endif
2444 /* Whether -mtune= or -march= were specified */
2448 /* Vectorization library interface and handlers. */
2454 /* Processor target table, indexed by processor number */
2455 struct ptt
2456 {
2464 };
2466 /* This table must be in sync with enum processor_type in i386.h. */
2468 {
2494 };
2495 \f
2496 static bool
2498 {
2500 }
2502 static unsigned int
2504 {
2507 /* vzeroupper instructions are inserted immediately after reload to
2508 account for possible spills from 256bit registers. The pass
2509 reuses mode switching infrastructure by re-running mode insertion
2510 pass, so disable entities that have already been processed. */
2516 /* Call optimize_mode_switching. */
2519 }
2524 {
2536 };
2539 {
2543 {}
2545 /* opt_pass methods: */
2553 rtl_opt_pass *
2555 {
2557 }
2559 /* Return true if a red-zone is in use. */
2563 {
2565 }
2566 \f
2567 /* Return a string that documents the current -m options. The caller is
2568 responsible for freeing the string. */
2574 {
2575 struct ix86_target_opts
2576 {
2579 };
2581 /* This table is ordered so that options like -msse4.2 that imply
2582 preceding options while match those first. */
2584 {
2626 };
2628 /* Flag options. */
2630 {
2659 };
2676 /* Add -march= option. */
2678 {
2681 }
2683 /* Add -mtune= option. */
2685 {
2688 }
2690 /* Add -m32/-m64/-mx32. */
2692 {
2695 else
2697 isa &= ~ (OPTION_MASK_ISA_64BIT
2698 | OPTION_MASK_ABI_64
2700 }
2701 else
2705 /* Pick out the options in isa options. */
2707 {
2709 {
2712 }
2713 }
2716 {
2719 isa);
2720 }
2722 /* Add flag options. */
2724 {
2726 {
2729 }
2730 }
2733 {
2736 }
2738 /* Add -fpmath= option. */
2740 {
2743 {
2758 }
2759 }
2761 /* Any options? */
2767 /* Size the string. */
2771 {
2776 }
2778 /* Build the string. */
2783 {
2790 {
2792 line_len++;
2795 {
2799 }
2800 }
2804 {
2808 }
2809 }
2815 }
2817 /* Return true, if profiling code should be emitted before
2818 prologue. Otherwise it returns false.
2819 Note: For x86 with "hotfix" it is sorried. */
2820 static bool
2822 {
2824 }
2826 /* Function that is callable from the debugger to print the current
2827 options. */
2828 void ATTRIBUTE_UNUSED
2830 {
2836 {
2839 }
2840 else
2844 }
2847 #define DEF_ENUM
2848 #define DEF_ALG(alg, name) #name,
2850 #undef DEF_ENUM
2851 #undef DEF_ALG
2852 };
2854 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2855 The string is of the following form (or comma separated list of it):
2857 strategy_alg:max_size:[align|noalign]
2859 where the full size range for the strategy is either [0, max_size] or
2860 [min_size, max_size], in which min_size is the max_size + 1 of the
2861 preceding range. The last size range must have max_size == -1.
2863 Examples:
2865 1.
2866 -mmemcpy-strategy=libcall:-1:noalign
2868 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2871 2.
2872 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2874 This is to tell the compiler to use the following strategy for memset
2875 1) when the expected size is between [1, 16], use rep_8byte strategy;
2876 2) when the size is between [17, 2048], use vector_loop;
2877 3) when the size is > 2048, use libcall. */
2879 struct stringop_size_range
2880 {
2882 stringop_alg alg;
2884 };
2886 static void
2888 {
2896 else
2901 do
2902 {
2912 {
2916 }
2919 {
2923 }
2930 {
2932 alg_name,
2935 }
2939 {
2940 /* rep; movq isn't available in 32-bit code. */
2943 alg_name,
2946 }
2954 else
2955 {
2959 }
2960 n++;
2962 }
2966 {
2971 }
2974 {
2978 }
2980 /* Now override the default algs array. */
2982 {
2988 }
2989 }
2991 \f
2992 /* parse -mtune-ctrl= option. When DUMP is true,
2993 print the features that are explicitly set. */
2995 static void
2997 {
3005 do
3006 {
3013 {
3014 curr_feature_string++;
3016 }
3018 {
3020 {
3026 }
3027 }
3032 }
3035 }
3037 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3038 processor type. */
3040 static void
3042 {
3047 {
3050 else
3052 }
3055 {
3060 }
3063 }
3066 /* Override various settings based on options. If MAIN_ARGS_P, the
3067 options are from the command line, otherwise they are from
3068 attributes. */
3070 static void
3074 {
3082 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3083 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3084 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3085 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3086 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3087 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3088 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3089 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3090 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3091 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3092 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3093 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3094 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3095 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3096 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3097 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3098 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3099 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3100 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3101 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3102 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3103 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3104 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3105 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3106 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3107 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3108 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3109 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3110 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3111 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3112 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3113 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3114 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3115 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3116 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3117 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3118 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3119 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3120 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3121 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3122 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3123 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3124 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3125 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3126 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3127 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3129 #define PTA_CORE2 \
3130 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3131 | PTA_CX16 | PTA_FXSR)
3132 #define PTA_NEHALEM \
3133 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3134 #define PTA_WESTMERE \
3135 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3136 #define PTA_SANDYBRIDGE \
3137 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3138 #define PTA_IVYBRIDGE \
3139 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3140 #define PTA_HASWELL \
3141 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3142 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3143 #define PTA_BROADWELL \
3144 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3145 #define PTA_BONNELL \
3146 (PTA_CORE2 | PTA_MOVBE)
3147 #define PTA_SILVERMONT \
3148 (PTA_WESTMERE | PTA_MOVBE)
3150 /* if this reaches 64, need to widen struct pta flags below */
3152 static struct pta
3153 {
3158 }
3160 {
3194 PTA_SANDYBRIDGE},
3196 PTA_SANDYBRIDGE},
3198 PTA_IVYBRIDGE},
3200 PTA_IVYBRIDGE},
3291 PTA_64BIT
3293 };
3295 /* -mrecip options. */
3296 static struct
3297 {
3300 }
3302 {
3309 };
3313 /* Set up prefix/suffix so the error messages refer to either the command
3314 line argument, or the attribute(target). */
3316 {
3320 }
3321 else
3322 {
3326 }
3328 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3329 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3332 #ifdef TARGET_BI_ARCH
3333 else
3334 {
3335 #if TARGET_BI_ARCH == 1
3336 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3337 is on and OPTION_MASK_ABI_X32 is off. We turn off
3338 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3339 -mx32. */
3342 #else
3343 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3344 on and OPTION_MASK_ABI_64 is off. We turn off
3345 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3346 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3350 #endif
3351 }
3352 #endif
3355 {
3356 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3357 OPTION_MASK_ABI_64 for TARGET_X32. */
3360 }
3363 | OPTION_MASK_ABI_X32
3366 {
3367 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3368 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3371 }
3373 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3374 SUBTARGET_OVERRIDE_OPTIONS;
3375 #endif
3377 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3378 SUBSUBTARGET_OVERRIDE_OPTIONS;
3379 #endif
3381 /* -fPIC is the default for x86_64. */
3385 /* Need to check -mtune=generic first. */
3387 {
3388 /* As special support for cross compilers we read -mtune=native
3389 as -mtune=generic. With native compilers we won't see the
3390 -mtune=native, as it was changed by the driver. */
3392 {
3394 }
3399 }
3400 else
3401 {
3405 {
3406 opts->x_ix86_tune_string
3409 }
3411 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3412 or defaulted. We need to use a sensible tune option. */
3414 {
3416 }
3417 }
3421 {
3422 /* rep; movq isn't available in 32-bit code. */
3425 }
3428 opts->x_ix86_arch_string
3431 else
3435 {
3443 }
3444 else
3451 /* For targets using ms ABI enable ms-extensions, if not
3452 explicit turned off. For non-ms ABI we turn off this
3453 option. */
3458 {
3460 {
3504 {
3507 }
3515 }
3516 }
3517 else
3518 {
3519 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3520 use of rip-relative addressing. This eliminates fixups that
3521 would otherwise be needed if this object is to be placed in a
3522 DLL, and is essentially just as efficient as direct addressing. */
3528 else
3530 }
3532 {
3535 }
3543 {
3546 /* Default cpu tuning to the architecture. */
3691 }
3709 {
3713 {
3715 {
3717 {
3725 }
3726 else
3729 }
3730 }
3731 /* Intel CPUs have always interpreted SSE prefetch instructions as
3732 NOPs; so, we can enable SSE prefetch instructions even when
3733 -mtune (rather than -march) points us to a processor that has them.
3734 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3735 higher processors. */
3740 }
3748 #ifndef USE_IX86_FRAME_POINTER
3749 #define USE_IX86_FRAME_POINTER 0
3750 #endif
3752 #ifndef USE_X86_64_FRAME_POINTER
3753 #define USE_X86_64_FRAME_POINTER 0
3754 #endif
3756 /* Set the default values for switches whose default depends on TARGET_64BIT
3757 in case they weren't overwritten by command line options. */
3759 {
3767 opts->x_flag_unwind_tables
3771 }
3772 else
3773 {
3775 opts->x_flag_omit_frame_pointer
3781 }
3786 else
3789 /* Arrange to set up i386_stack_locals for all functions. */
3792 /* Validate -mregparm= value. */
3794 {
3798 {
3802 }
3803 }
3807 /* Default align_* from the processor table. */
3809 {
3812 }
3814 {
3817 }
3819 {
3821 }
3823 /* Provide default for -mbranch-cost= value. */
3828 {
3829 opts->x_target_flags
3832 /* Enable by default the SSE and MMX builtins. Do allow the user to
3833 explicitly disable any of these. In particular, disabling SSE and
3834 MMX for kernel code is extremely useful. */
3836 opts->x_ix86_isa_flags
3843 }
3844 else
3845 {
3846 opts->x_target_flags
3850 opts->x_ix86_isa_flags
3853 /* i386 ABI does not specify red zone. It still makes sense to use it
3854 when programmer takes care to stack from being destroyed. */
3857 }
3859 /* Keep nonleaf frame pointers. */
3865 /* If we're doing fast math, we don't care about comparison order
3866 wrt NaNs. This lets us use a shorter comparison sequence. */
3870 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3871 since the insns won't need emulation. */
3875 /* Likewise, if the target doesn't have a 387, or we've specified
3876 software floating point, don't use 387 inline intrinsics. */
3880 /* Turn on MMX builtins for -msse. */
3882 opts->x_ix86_isa_flags
3885 /* Enable SSE prefetch. */
3890 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3893 opts->x_ix86_isa_flags
3896 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3899 opts->x_ix86_isa_flags
3902 /* Enable lzcnt instruction for -mabm. */
3904 opts->x_ix86_isa_flags
3907 /* Validate -mpreferred-stack-boundary= value or default it to
3908 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3911 {
3918 {
3922 else
3925 }
3926 else
3927 ix86_preferred_stack_boundary
3929 }
3931 /* Set the default value for -mstackrealign. */
3937 /* Validate -mincoming-stack-boundary= value or default it to
3938 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3941 {
3948 else
3949 {
3950 ix86_user_incoming_stack_boundary
3952 ix86_incoming_stack_boundary
3954 }
3955 }
3957 /* Accept -msseregparm only if at least SSE support is enabled. */
3963 {
3965 {
3967 {
3970 }
3973 {
3976 }
3977 }
3978 }
3979 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3980 fpmath=387. The second is however default at many targets since the
3981 extra 80bit precision of temporaries is considered to be part of ABI.
3982 Overwrite the default at least for -ffast-math.
3983 TODO: -mfpmath=both seems to produce same performing code with bit
3984 smaller binaries. It is however not clear if register allocation is
3985 ready for this setting.
3986 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3987 codegen. We may switch to 387 with -ffast-math for size optimized
3988 functions. */
3992 else
3995 /* If the i387 is disabled, then do not return values in it. */
3999 /* Use external vectorized library in vectorizing intrinsics. */
4002 {
4013 }
4020 /* If stack probes are required, the space used for large function
4021 arguments on the stack must also be probed, so enable
4022 -maccumulate-outgoing-args so this happens in the prologue. */
4025 {
4030 }
4032 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4033 {
4039 }
4041 /* When scheduling description is not available, disable scheduler pass
4042 so it won't slow down the compilation and make x87 code slower. */
4063 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4065 && HAVE_prefetch
4070 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4071 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4076 {
4079 {
4081 ix86_gen_tls_local_dynamic_base_64
4083 }
4084 else
4085 {
4087 ix86_gen_tls_local_dynamic_base_64
4089 }
4090 }
4091 else
4095 {
4105 }
4106 else
4107 {
4117 }
4119 #ifdef USE_IX86_CLD
4120 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4123 #endif
4126 {
4131 }
4133 {
4137 }
4139 {
4140 #if defined(PROFILE_BEFORE_PROLOGUE)
4142 #else
4144 #endif
4145 }
4147 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4148 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4149 AVX unaligned load/store. */
4151 {
4161 /* Enable 128-bit AVX instruction generation
4162 for the auto-vectorizer. */
4166 }
4169 {
4176 {
4179 {
4181 q++;
4182 }
4183 else
4188 else
4189 {
4192 {
4195 }
4198 {
4202 }
4203 }
4208 else
4210 }
4211 }
4218 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4219 for 64-bit Bionic. */
4224 ? MASK_LONG_DOUBLE_128
4227 /* Only one of them can be active. */
4231 /* Save the initial options in case the user does function specific
4232 options. */
4234 target_option_default_node = target_option_current_node
4237 /* Handle stack protector */
4239 opts->x_ix86_stack_protector_guard
4242 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4244 {
4248 }
4251 {
4255 }
4256 }
4258 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4260 static void
4262 {
4264 static struct register_pass_info insert_vzeroupper_info
4267 };
4272 /* This needs to be done at start up. It's convenient to do it here. */
4274 }
4276 /* Update register usage after having seen the compiler flags. */
4278 static void
4280 {
4284 /* The PIC register, if it exists, is fixed. */
4289 /* For 32-bit targets, squash the REX registers. */
4291 {
4298 }
4300 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4308 {
4309 /* Set/reset conditionally defined registers from
4310 CALL_USED_REGISTERS initializer. */
4314 /* Calculate registers of CLOBBERED_REGS register set
4315 as call used registers from GENERAL_REGS register set. */
4319 }
4321 /* If MMX is disabled, squash the registers. */
4327 /* If SSE is disabled, squash the registers. */
4333 /* If the FPU is disabled, squash the registers. */
4339 /* If AVX512F is disabled, squash the registers. */
4341 {
4347 }
4348 }
4350 \f
4351 /* Save the current options */
4353 static void
4356 {
4391 /* The fields are char but the variables are not; make sure the
4392 values fit in the fields. */
4397 }
4399 /* Restore the current options */
4401 static void
4404 {
4410 /* We don't change -fPIC. */
4447 /* Recreate the arch feature tests if the arch changed */
4449 {
4454 }
4456 /* Recreate the tune optimization tests */
4459 }
4461 /* Print the current options */
4463 static void
4466 {
4484 {
4487 }
4488 }
4490 \f
4491 /* Inner function to process the attribute((target(...))), take an argument and
4492 set the current options from the argument. If we have a list, recursively go
4493 over the list. */
4495 static bool
4500 {
4504 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4505 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4506 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4507 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4508 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4510 enum ix86_opt_type
4511 {
4512 ix86_opt_unknown,
4513 ix86_opt_yes,
4514 ix86_opt_no,
4515 ix86_opt_str,
4516 ix86_opt_enum,
4517 ix86_opt_isa
4518 };
4520 static const struct
4521 {
4528 /* isa options */
4571 /* enum options */
4574 /* string options */
4578 /* flag options */
4580 OPT_mcld,
4581 MASK_CLD),
4584 OPT_mfancy_math_387,
4585 MASK_NO_FANCY_MATH_387),
4588 OPT_mieee_fp,
4589 MASK_IEEE_FP),
4592 OPT_minline_all_stringops,
4593 MASK_INLINE_ALL_STRINGOPS),
4596 OPT_minline_stringops_dynamically,
4597 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4600 OPT_mno_align_stringops,
4601 MASK_NO_ALIGN_STRINGOPS),
4604 OPT_mrecip,
4605 MASK_RECIP),
4607 };
4609 /* If this is a list, recurse to get the options. */
4611 {
4618 enum_opts_set))
4622 }
4625 {
4628 }
4630 /* Handle multiple arguments separated by commas. */
4634 {
4648 {
4652 }
4653 else
4654 {
4657 }
4659 /* Recognize no-xxx. */
4661 {
4665 }
4666 else
4669 /* Find the option. */
4673 {
4681 {
4686 }
4687 }
4689 /* Process the option. */
4691 {
4694 }
4697 {
4703 }
4706 {
4712 else
4714 }
4717 {
4719 {
4722 }
4723 else
4725 }
4728 {
4736 global_dc);
4737 else
4738 {
4741 }
4742 }
4744 else
4746 }
4749 }
4751 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4753 tree
4757 {
4772 /* Process each of the options on the chain. */
4777 /* If the changed options are different from the default, rerun
4778 ix86_option_override_internal, and then save the options away.
4779 The string options are are attribute options, and will be undone
4780 when we copy the save structure. */
4786 {
4787 /* If we are using the default tune= or arch=, undo the string assigned,
4788 and use the default. */
4799 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4804 {
4807 }
4809 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4812 /* Add any builtin functions with the new isa if any. */
4815 /* Save the current options unless we are validating options for
4816 #pragma. */
4823 /* Free up memory allocated to hold the strings */
4826 }
4829 }
4831 /* Hook to validate attribute((target("string"))). */
4833 static bool
4836 tree args,
4838 {
4843 /* attribute((target("default"))) does nothing, beyond
4844 affecting multi-versioning. */
4853 /* Get the optimization options of the current function. */
4859 /* Init func_options. */
4867 /* Initialize func_options to the default before its target options can
4868 be set. */
4881 {
4886 }
4889 }
4891 \f
4892 /* Hook to determine if one function can safely inline another. */
4894 static bool
4896 {
4901 /* If callee has no option attributes, then it is ok to inline. */
4905 /* If caller has no option attributes, but callee does then it is not ok to
4906 inline. */
4910 else
4911 {
4915 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4916 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4917 function. */
4922 /* See if we have the same non-isa options. */
4926 /* See if arch, tune, etc. are the same. */
4939 else
4941 }
4944 }
4946 \f
4947 /* Remember the last target of ix86_set_current_function. */
4950 /* Invalidate ix86_previous_fndecl cache. */
4951 void
4953 {
4955 }
4957 /* Establish appropriate back-end context for processing the function
4958 FNDECL. The argument might be NULL to indicate processing at top
4959 level, outside of any function scope. */
4960 static void
4962 {
4963 /* Only change the context if the function changes. This hook is called
4964 several times in the course of compiling a function, and we don't want to
4965 slow things down too much or call target_reinit when it isn't safe. */
4967 {
4968 tree old_tree = (ix86_previous_fndecl
4972 tree new_tree = (fndecl
4978 ;
4981 {
4986 else
4989 }
4992 {
5000 else
5003 }
5004 }
5005 }
5007 \f
5008 /* Return true if this goes in large data/bss. */
5010 static bool
5012 {
5016 /* Functions are never large data. */
5020 /* Automatic variables are never large data. */
5025 {
5031 }
5032 else
5033 {
5036 /* If this is an incomplete type with size 0, then we can't put it
5037 in data because it might be too big when completed. */
5040 }
5043 }
5045 /* Switch to the appropriate section for output of DECL.
5046 DECL is either a `VAR_DECL' node or a constant of some sort.
5047 RELOC indicates whether forming the initial value of DECL requires
5048 link-time relocations. */
5053 {
5055 {
5059 {
5093 /* We don't split these for medium model. Place them into
5094 default sections and hope for best. */
5096 }
5098 {
5099 /* We might get called with string constants, but get_named_section
5100 doesn't like them as they are not DECLs. Also, we need to set
5101 flags in that case. */
5105 }
5106 }
5108 }
5110 /* Select a set of attributes for section NAME based on the properties
5111 of DECL and whether or not RELOC indicates that DECL's initializer
5112 might contain runtime relocations. */
5114 static unsigned int ATTRIBUTE_UNUSED
5116 {
5130 }
5132 /* Build up a unique section name, expressed as a
5133 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5134 RELOC indicates whether the initial value of EXP requires
5135 link-time relocations. */
5137 static void ATTRIBUTE_UNUSED
5139 {
5141 {
5143 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5147 {
5171 /* We don't split these for medium model. Place them into
5172 default sections and hope for best. */
5174 }
5176 {
5183 /* If we're using one_only, then there needs to be a .gnu.linkonce
5184 prefix to the section name. */
5191 }
5192 }
5194 }
5196 #ifdef COMMON_ASM_OP
5197 /* This says how to output assembler code to declare an
5198 uninitialized external linkage data object.
5200 For medium model x86-64 we need to use .largecomm opcode for
5201 large objects. */
5202 void
5206 {
5210 else
5215 }
5216 #endif
5218 /* Utility function for targets to use in implementing
5219 ASM_OUTPUT_ALIGNED_BSS. */
5221 void
5225 {
5229 else
5232 #ifdef ASM_DECLARE_OBJECT_NAME
5235 #else
5236 /* Standard thing is just output label for the object. */
5240 }
5241 \f
5242 /* Decide whether we must probe the stack before any space allocation
5243 on this target. It's essentially TARGET_STACK_PROBE except when
5244 -fstack-check causes the stack to be already probed differently. */
5246 bool
5248 {
5249 /* Do not probe the stack twice if static stack checking is enabled. */
5254 }
5255 \f
5256 /* Decide whether we can make a sibling call to a function. DECL is the
5257 declaration of the function being targeted by the call and EXP is the
5258 CALL_EXPR representing the call. */
5260 static bool
5262 {
5266 /* If we are generating position-independent code, we cannot sibcall
5267 optimize any indirect call, or a direct call to a global function,
5268 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5270 && !TARGET_64BIT
5271 && flag_pic
5275 /* If we need to align the outgoing stack, then sibcalling would
5276 unalign the stack, which may break the called function. */
5282 {
5285 }
5286 else
5287 {
5288 /* We're looking at the CALL_EXPR, we need the type of the function. */
5293 }
5295 /* Check that the return value locations are the same. Like
5296 if we are returning floats on the 80387 register stack, we cannot
5297 make a sibcall from a function that doesn't return a float to a
5298 function that does or, conversely, from a function that does return
5299 a float to a function that doesn't; the necessary stack adjustment
5300 would not be executed. This is also the place we notice
5301 differences in the return value ABI. Note that it is ok for one
5302 of the functions to have void return type as long as the return
5303 value of the other is passed in a register. */
5308 {
5311 }
5313 ;
5318 {
5319 /* The SYSV ABI has more call-clobbered registers;
5320 disallow sibcalls from MS to SYSV. */
5324 }
5325 else
5326 {
5327 /* If this call is indirect, we'll need to be able to use a
5328 call-clobbered register for the address of the target function.
5329 Make sure that all such registers are not used for passing
5330 parameters. Note that DLLIMPORT functions are indirect. */
5333 {
5335 {
5336 /* ??? Need to count the actual number of registers to be used,
5337 not the possible number of registers. Fix later. */
5339 }
5340 }
5341 }
5343 /* Otherwise okay. That also includes certain types of indirect calls. */
5345 }
5347 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5348 and "sseregparm" calling convention attributes;
5349 arguments as in struct attribute_spec.handler. */
5351 static tree
5353 tree args,
5356 {
5361 {
5363 name);
5366 }
5368 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5370 {
5371 tree cst;
5374 {
5376 }
5379 {
5381 }
5385 {
5388 name);
5390 }
5392 {
5396 }
5399 }
5402 {
5403 /* Do not warn when emulating the MS ABI. */
5408 name);
5411 }
5413 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5415 {
5417 {
5419 }
5421 {
5423 }
5425 {
5427 }
5429 {
5431 }
5432 }
5434 /* Can combine stdcall with fastcall (redundant), regparm and
5435 sseregparm. */
5437 {
5439 {
5441 }
5443 {
5445 }
5447 {
5449 }
5450 }
5452 /* Can combine cdecl with regparm and sseregparm. */
5454 {
5456 {
5458 }
5460 {
5462 }
5464 {
5466 }
5467 }
5469 {
5472 name);
5474 {
5476 }
5478 {
5480 }
5482 {
5484 }
5485 }
5487 /* Can combine sseregparm with all attributes. */
5490 }
5492 /* The transactional memory builtins are implicitly regparm or fastcall
5493 depending on the ABI. Override the generic do-nothing attribute that
5494 these builtins were declared with, and replace it with one of the two
5495 attributes that we expect elsewhere. */
5497 static tree
5499 tree args ATTRIBUTE_UNUSED,
5501 {
5502 tree alt;
5504 /* In no case do we want to add the placeholder attribute. */
5507 /* The 64-bit ABI is unchanged for transactional memory. */
5511 /* ??? Is there a better way to validate 32-bit windows? We have
5512 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5515 else
5516 {
5519 }
5523 }
5525 /* This function determines from TYPE the calling-convention. */
5527 unsigned int
5529 {
5532 tree attrs;
5539 {
5549 /* Regparam isn't allowed for thiscall and fastcall. */
5551 {
5556 }
5560 }
5567 || is_stdarg
5573 }
5575 /* Return 0 if the attributes for two types are incompatible, 1 if they
5576 are compatible, and 2 if they are nearly compatible (which causes a
5577 warning to be generated). */
5579 static int
5581 {
5597 }
5598 \f
5599 /* Return the regparm value for a function with the indicated TYPE and DECL.
5600 DECL may be NULL when calling function indirectly
5601 or considering a libcall. */
5603 static int
5605 {
5606 tree attr;
5617 {
5620 {
5623 }
5624 }
5630 /* Use register calling convention for local functions when possible. */
5633 /* Caller and callee must agree on the calling convention, so
5634 checking here just optimize means that with
5635 __attribute__((optimize (...))) caller could use regparm convention
5636 and callee not, or vice versa. Instead look at whether the callee
5637 is optimized or not. */
5640 {
5641 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5644 {
5647 /* Make sure no regparm register is taken by a
5648 fixed register variable. */
5653 /* We don't want to use regparm(3) for nested functions as
5654 these use a static chain pointer in the third argument. */
5658 /* In 32-bit mode save a register for the split stack. */
5662 /* Each fixed register usage increases register pressure,
5663 so less registers should be used for argument passing.
5664 This functionality can be overriden by an explicit
5665 regparm value. */
5668 globals++;
5670 local_regparm
5675 }
5676 }
5679 }
5681 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5682 DFmode (2) arguments in SSE registers for a function with the
5683 indicated TYPE and DECL. DECL may be NULL when calling function
5684 indirectly or considering a libcall. Otherwise return 0. */
5686 static int
5688 {
5691 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5692 by the sseregparm attribute. */
5695 {
5697 {
5699 {
5703 else
5706 }
5708 }
5711 }
5713 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5714 (and DFmode for SSE2) arguments in SSE registers. */
5717 {
5718 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5722 }
5725 }
5727 /* Return true if EAX is live at the start of the function. Used by
5728 ix86_expand_prologue to determine if we need special help before
5729 calling allocate_stack_worker. */
5731 static bool
5733 {
5734 /* Cheat. Don't bother working forward from ix86_function_regparm
5735 to the function type to whether an actual argument is located in
5736 eax. Instead just look at cfg info, which is still close enough
5737 to correct at this point. This gives false positives for broken
5738 functions that might use uninitialized data that happens to be
5739 allocated in eax, but who cares? */
5741 }
5743 static bool
5745 {
5746 tree attr;
5749 {
5755 /* For 32-bit MS-ABI the default is to keep aggregate
5756 return pointer. */
5759 }
5761 }
5763 /* Value is the number of bytes of arguments automatically
5764 popped when returning from a subroutine call.
5765 FUNDECL is the declaration node of the function (as a tree),
5766 FUNTYPE is the data type of the function (as a tree),
5767 or for a library call it is an identifier node for the subroutine name.
5768 SIZE is the number of bytes of arguments passed on the stack.
5770 On the 80386, the RTD insn may be used to pop them if the number
5771 of args is fixed, but if the number is variable then the caller
5772 must pop them all. RTD can't be used for library calls now
5773 because the library is compiled with the Unix compiler.
5774 Use of RTD is a selectable option, since it is incompatible with
5775 standard Unix calling sequences. If the option is not selected,
5776 the caller must always pop the args.
5778 The attribute stdcall is equivalent to RTD on a per module basis. */
5780 static int
5782 {
5785 /* None of the 64-bit ABIs pop arguments. */
5796 /* Lose any fake structure return argument if it is passed on the stack. */
5799 {
5803 }
5806 }
5808 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5810 static bool
5812 {
5813 /* Check operand constraints in case hard registers were propagated
5814 into insn pattern. This check prevents combine pass from
5815 generating insn patterns with invalid hard register operands.
5816 These invalid insns can eventually confuse reload to error out
5817 with a spill failure. See also PRs 46829 and 46843. */
5819 {
5826 {
5834 /* For pre-AVX disallow unaligned loads/stores where the
5835 instructions don't support it. */
5839 {
5843 }
5845 /* A unary operator may be accepted by the predicate, but it
5846 is irrelevant for matching constraints. */
5851 {
5859 }
5866 /* Operand has no constraints, anything is OK. */
5870 {
5873 && operands_match_p
5877 {
5880 }
5881 }
5885 }
5886 }
5889 }
5890 \f
5891 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5893 static unsigned HOST_WIDE_INT
5895 {
5899 }
5900 \f
5901 /* Argument support functions. */
5903 /* Return true when register may be used to pass function parameters. */
5904 bool
5906 {
5912 {
5916 else
5922 }
5928 /* TODO: The function should depend on current function ABI but
5929 builtins.c would need updating then. Therefore we use the
5930 default ABI. */
5933 /* RAX is used as hidden argument to va_arg functions. */
5939 else
5947 }
5949 /* Return if we do not know how to pass TYPE solely in registers. */
5951 static bool
5953 {
5957 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5958 The layout_type routine is crafty and tries to trick us into passing
5959 currently unsupported vector types on the stack by using TImode. */
5962 }
5964 /* It returns the size, in bytes, of the area reserved for arguments passed
5965 in registers for the function represented by fndecl dependent to the used
5966 abi format. */
5967 int
5969 {
5973 else
5978 }
5980 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5981 call abi used. */
5982 enum calling_abi
5984 {
5986 {
5989 {
5991 {
5993 {
5996 {
5999 }
6000 }
6002 }
6003 }
6007 }
6009 }
6011 /* We add this as a workaround in order to use libc_has_function
6012 hook in i386.md. */
6013 bool
6015 {
6017 }
6019 static bool
6021 {
6023 {
6027 else
6029 }
6031 }
6033 static enum calling_abi
6035 {
6039 }
6041 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6042 call abi used. */
6043 enum calling_abi
6045 {
6049 }
6051 /* Write the extra assembler code needed to declare a function properly. */
6053 void
6055 tree decl)
6056 {
6060 {
6066 }
6068 #ifdef SUBTARGET_ASM_UNWIND_INIT
6070 #endif
6074 /* Output magic byte marker, if hot-patch attribute is set. */
6076 {
6078 {
6079 /* leaq [%rsp + 0], %rsp */
6082 }
6083 else
6084 {
6085 /* movl.s %edi, %edi
6086 push %ebp
6087 movl.s %esp, %ebp */
6090 }
6091 }
6092 }
6094 /* regclass.c */
6097 /* Implementation of call abi switching target hook. Specific to FNDECL
6098 the specific call register sets are set. See also
6099 ix86_conditional_register_usage for more details. */
6100 void
6102 {
6105 else
6107 }
6109 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6110 expensive re-initialization of init_regs each time we switch function context
6111 since this is needed only during RTL expansion. */
6112 static void
6114 {
6118 }
6120 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6121 for a call to a function whose data type is FNTYPE.
6122 For a library call, FNTYPE is 0. */
6124 void
6128 tree fndecl,
6130 {
6136 {
6139 }
6140 else
6141 {
6144 }
6148 /* Set up the number of registers to use for passing arguments. */
6151 {
6153 ? X86_64_REGPARM_MAX
6155 }
6157 {
6160 {
6162 ? X86_64_SSE_REGPARM_MAX
6164 }
6165 }
6173 /* Because type might mismatch in between caller and callee, we need to
6174 use actual type of function for local calls.
6175 FIXME: cgraph_analyze can be told to actually record if function uses
6176 va_start so for local functions maybe_vaarg can be made aggressive
6177 helping K&R code.
6178 FIXME: once typesytem is fixed, we won't need this code anymore. */
6186 {
6187 /* If there are variable arguments, then we won't pass anything
6188 in registers in 32-bit mode. */
6190 {
6199 }
6201 /* Use ecx and edx registers if function has fastcall attribute,
6202 else look for regparm information. */
6204 {
6207 {
6210 }
6212 {
6215 }
6216 else
6218 }
6220 /* Set up the number of SSE registers used for passing SFmode
6221 and DFmode arguments. Warn for mismatching ABI. */
6223 }
6224 }
6226 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6227 But in the case of vector types, it is some vector mode.
6229 When we have only some of our vector isa extensions enabled, then there
6230 are some modes for which vector_mode_supported_p is false. For these
6231 modes, the generic vector support in gcc will choose some non-vector mode
6232 in order to implement the type. By computing the natural mode, we'll
6233 select the proper ABI location for the operand and not depend on whatever
6234 the middle-end decides to do with these vector types.
6236 The midde-end can't deal with the vector types > 16 bytes. In this
6237 case, we return the original mode and warn ABI change if CUM isn't
6238 NULL.
6240 If INT_RETURN is true, warn ABI change if the vector mode isn't
6241 available for function return value. */
6243 static enum machine_mode
6246 {
6250 {
6253 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6255 {
6260 else
6263 /* Get the mode which has this inner mode and number of units. */
6267 {
6269 {
6274 {
6278 }
6280 {
6284 }
6287 }
6289 {
6294 {
6298 }
6300 {
6304 }
6307 }
6310 {
6315 {
6319 }
6321 {
6325 }
6326 }
6328 {
6333 {
6337 }
6339 {
6343 }
6344 }
6346 }
6349 }
6350 }
6353 }
6355 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6356 this may not agree with the mode that the type system has chosen for the
6357 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6358 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6360 static rtx
6363 {
6364 rtx tmp;
6368 else
6369 {
6373 }
6376 }
6378 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6379 of this code is to classify each 8bytes of incoming argument by the register
6380 class and assign registers accordingly. */
6382 /* Return the union class of CLASS1 and CLASS2.
6383 See the x86-64 PS ABI for details. */
6385 static enum x86_64_reg_class
6387 {
6388 /* Rule #1: If both classes are equal, this is the resulting class. */
6392 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6393 the other class. */
6399 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6403 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6411 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6412 MEMORY is used. */
6421 /* Rule #6: Otherwise class SSE is used. */
6423 }
6425 /* Classify the argument of type TYPE and mode MODE.
6426 CLASSES will be filled by the register class used to pass each word
6427 of the operand. The number of words is returned. In case the parameter
6428 should be passed in memory, 0 is returned. As a special case for zero
6429 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6431 BIT_OFFSET is used internally for handling records and specifies offset
6432 of the offset in bits modulo 512 to avoid overflow cases.
6434 See the x86-64 PS ABI for details.
6435 */
6437 static int
6440 {
6441 HOST_WIDE_INT bytes =
6443 int words
6446 /* Variable sized entities are always passed/returned in memory. */
6455 {
6457 tree field;
6460 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6467 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6468 signalize memory class, so handle it as special case. */
6470 {
6473 }
6475 /* Classify each field of record and merge classes. */
6477 {
6479 /* And now merge the fields of structure. */
6481 {
6483 {
6489 /* Bitfields are always classified as integer. Handle them
6490 early, since later code would consider them to be
6491 misaligned integers. */
6493 {
6502 }
6503 else
6504 {
6509 /* Flexible array member is ignored. */
6516 {
6520 {
6523 "the ABI of passing struct with"
6524 " a flexible array member has"
6526 }
6528 }
6530 subclasses,
6540 }
6541 }
6542 }
6546 /* Arrays are handled as small records. */
6547 {
6554 /* The partial classes are now full classes. */
6565 }
6568 /* Unions are similar to RECORD_TYPE but offset is always 0.
6569 */
6571 {
6573 {
6581 bit_offset);
6586 }
6587 }
6592 }
6595 {
6596 /* When size > 16 bytes, if the first one isn't
6597 X86_64_SSE_CLASS or any other ones aren't
6598 X86_64_SSEUP_CLASS, everything should be passed in
6599 memory. */
6606 }
6608 /* Final merger cleanup. */
6610 {
6611 /* If one class is MEMORY, everything should be passed in
6612 memory. */
6616 /* The X86_64_SSEUP_CLASS should be always preceded by
6617 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6621 {
6622 /* The first one should never be X86_64_SSEUP_CLASS. */
6625 }
6627 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6628 everything should be passed in memory. */
6631 {
6634 /* The first one should never be X86_64_X87UP_CLASS. */
6637 {
6640 "the ABI of passing union with long double"
6642 }
6644 }
6645 }
6647 }
6649 /* Compute alignment needed. We align all types to natural boundaries with
6650 exception of XFmode that is aligned to 64bits. */
6652 {
6661 /* Misaligned fields are always returned in memory. */
6664 }
6666 /* for V1xx modes, just use the base mode */
6671 /* Classification of atomic types. */
6673 {
6689 {
6692 /* Analyze last 128 bits only. */
6696 {
6699 }
6701 {
6704 }
6706 {
6710 }
6712 {
6715 }
6716 else
6718 }
6725 /* OImode shouldn't be used directly. */
6732 else
6750 else
6751 {
6755 {
6758 "the ABI of passing structure with complex float"
6760 }
6763 }
6772 /* This modes is larger than 16 bytes. */
6830 else
6834 }
6835 }
6837 /* Examine the argument and return set number of register required in each
6838 class. Return 0 iff parameter should be passed in memory. */
6839 static int
6842 {
6852 {
6874 }
6876 }
6878 /* Construct container for the argument used by GCC interface. See
6879 FUNCTION_ARG for the detailed description. */
6881 static rtx
6885 {
6886 /* The following variables hold the static issued_error state. */
6900 rtx ret;
6911 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6912 some less clueful developer tries to use floating-point anyway. */
6914 {
6916 {
6918 {
6921 }
6922 }
6924 {
6927 }
6929 }
6931 /* Likewise, error if the ABI requires us to return values in the
6932 x87 registers and the user specified -mno-80387. */
6938 {
6940 {
6943 }
6945 }
6947 /* First construct simple cases. Avoid SCmode, since we want to use
6948 single register to pass this type. */
6951 {
6966 /* Zero sized array, struct or class. */
6970 }
7009 /* Otherwise figure out the entries of the PARALLEL. */
7011 {
7015 {
7020 /* Merge TImodes on aligned occasions here too. */
7022 tmpmode
7026 else
7028 /* We've requested 24 bytes we
7029 don't have mode for. Use DImode. */
7036 intreg++;
7044 sse_regno++;
7052 sse_regno++;
7057 {
7063 {
7065 i++;
7066 }
7067 else
7092 }
7098 sse_regno++;
7102 }
7103 }
7105 /* Empty aligned struct, union or class. */
7113 }
7115 /* Update the data in CUM to advance over an argument of mode MODE
7116 and data type TYPE. (TYPE is null for libcalls where that information
7117 may not be available.) */
7119 static void
7122 HOST_WIDE_INT words)
7123 {
7125 {
7132 /* FALLTHRU */
7143 {
7146 }
7150 /* OImode shouldn't be used directly. */
7159 /* FALLTHRU */
7181 {
7186 {
7189 }
7190 }
7200 {
7205 {
7208 }
7209 }
7211 }
7212 }
7214 static void
7217 {
7220 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7227 {
7232 }
7233 else
7234 {
7238 }
7239 }
7241 static void
7243 HOST_WIDE_INT words)
7244 {
7245 /* Otherwise, this should be passed indirect. */
7250 {
7253 }
7254 }
7256 /* Update the data in CUM to advance over an argument of mode MODE and
7257 data type TYPE. (TYPE is null for libcalls where that information
7258 may not be available.) */
7260 static void
7263 {
7269 else
7280 else
7282 }
7284 /* Define where to put the arguments to a function.
7285 Value is zero to push the argument on the stack,
7286 or a hard register in which to store the argument.
7288 MODE is the argument's machine mode.
7289 TYPE is the data type of the argument (as a tree).
7290 This is null for libcalls where that information may
7291 not be available.
7292 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7293 the preceding args and about the function being called.
7294 NAMED is nonzero if this argument is a named parameter
7295 (otherwise it is an extra parameter matching an ellipsis). */
7297 static rtx
7301 {
7302 /* Avoid the AL settings for the Unix64 ABI. */
7307 {
7314 /* FALLTHRU */
7320 {
7323 /* Fastcall allocates the first two DWORD (SImode) or
7324 smaller arguments to ECX and EDX if it isn't an
7325 aggregate type . */
7327 {
7333 /* ECX not EAX is the first allocated register. */
7336 }
7338 }
7347 /* FALLTHRU */
7349 /* In 32bit, we pass TImode in xmm registers. */
7357 {
7361 }
7366 /* OImode and XImode shouldn't be used directly. */
7382 {
7386 }
7396 {
7400 }
7402 }
7405 }
7407 static rtx
7410 {
7411 /* Handle a hidden AL argument containing number of registers
7412 for varargs x86-64 functions. */
7416 ? X86_64_SSE_REGPARM_MAX
7421 {
7437 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7441 }
7447 }
7449 static rtx
7452 HOST_WIDE_INT bytes)
7453 {
7456 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7457 We use value of -2 to specify that current function call is MSABI. */
7461 /* If we've run out of registers, it goes on the stack. */
7467 /* Only floating point modes are passed in anything but integer regs. */
7469 {
7472 else
7473 {
7476 /* Unnamed floating parameters are passed in both the
7477 SSE and integer registers. */
7483 }
7484 }
7485 /* Handle aggregated types passed in register. */
7487 {
7492 }
7495 }
7497 /* Return where to put the arguments to a function.
7498 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7500 MODE is the argument's machine mode. TYPE is the data type of the
7501 argument. It is null for libcalls where that information may not be
7502 available. CUM gives information about the preceding args and about
7503 the function being called. NAMED is nonzero if this argument is a
7504 named parameter (otherwise it is an extra parameter matching an
7505 ellipsis). */
7507 static rtx
7510 {
7514 rtx arg;
7518 else
7522 /* To simplify the code below, represent vector types with a vector mode
7523 even if MMX/SSE are not active. */
7531 else
7535 }
7537 /* A C expression that indicates when an argument must be passed by
7538 reference. If nonzero for an argument, a copy of that argument is
7539 made in memory and a pointer to the argument is passed instead of
7540 the argument itself. The pointer is passed in whatever way is
7541 appropriate for passing a pointer to that type. */
7543 static bool
7546 {
7549 /* See Windows x64 Software Convention. */
7551 {
7554 {
7555 /* Arrays are passed by reference. */
7560 {
7561 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7562 are passed by reference. */
7564 }
7565 }
7567 /* __m128 is passed by reference. */
7573 }
7574 }
7579 }
7581 /* Return true when TYPE should be 128bit aligned for 32bit argument
7582 passing ABI. XXX: This function is obsolete and is only used for
7583 checking psABI compatibility with previous versions of GCC. */
7585 static bool
7587 {
7599 {
7600 /* Walk the aggregates recursively. */
7602 {
7606 {
7607 tree field;
7609 /* Walk all the structure fields. */
7611 {
7615 }
7617 }
7620 /* Just for use if some languages passes arrays by value. */
7627 }
7628 }
7630 }
7632 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7633 XXX: This function is obsolete and is only used for checking psABI
7634 compatibility with previous versions of GCC. */
7636 static unsigned int
7639 {
7640 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7641 natural boundaries. */
7643 {
7644 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7645 make an exception for SSE modes since these require 128bit
7646 alignment.
7648 The handling here differs from field_alignment. ICC aligns MMX
7649 arguments to 4 byte boundaries, while structure fields are aligned
7650 to 8 byte boundaries. */
7652 {
7655 }
7656 else
7657 {
7660 }
7661 }
7665 }
7667 /* Return true when TYPE should be 128bit aligned for 32bit argument
7668 passing ABI. */
7670 static bool
7672 {
7682 {
7683 /* Walk the aggregates recursively. */
7685 {
7689 {
7690 tree field;
7692 /* Walk all the structure fields. */
7694 field;
7696 {
7700 }
7702 }
7705 /* Just for use if some languages passes arrays by value. */
7712 }
7713 }
7714 else
7718 }
7720 /* Gives the alignment boundary, in bits, of an argument with the
7721 specified mode and type. */
7723 static unsigned int
7725 {
7728 {
7729 /* Since the main variant type is used for call, we convert it to
7730 the main variant type. */
7733 }
7734 else
7738 else
7739 {
7744 {
7745 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7747 {
7750 }
7756 }
7759 && !warned
7761 saved_align))
7762 {
7765 "The ABI for passing parameters with %d-byte"
7768 }
7769 }
7772 }
7774 /* Return true if N is a possible register number of function value. */
7776 static bool
7778 {
7780 {
7788 /* Complex values are returned in %st(0)/%st(1) pair. */
7791 /* TODO: The function should depend on current function ABI but
7792 builtins.c would need updating then. Therefore we use the
7793 default ABI. */
7798 /* Complex values are returned in %xmm0/%xmm1 pair. */
7807 }
7810 }
7812 /* Define how to find the value returned by a function.
7813 VALTYPE is the data type of the value (as a tree).
7814 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7815 otherwise, FUNC is 0. */
7817 static rtx
7820 {
7823 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7824 we normally prevent this case when mmx is not available. However
7825 some ABIs may require the result to be returned like DImode. */
7829 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7830 we prevent this case when sse is not available. However some ABIs
7831 may require the result to be returned like integer TImode. */
7836 /* 32-byte vector modes in %ymm0. */
7840 /* 64-byte vector modes in %zmm0. */
7844 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7847 else
7848 /* Most things go in %eax. */
7851 /* Override FP return register with %xmm0 for local functions when
7852 SSE math is enabled or for functions with sseregparm attribute. */
7854 {
7859 }
7861 /* OImode shouldn't be used directly. */
7865 }
7867 static rtx
7869 const_tree valtype)
7870 {
7871 rtx ret;
7873 /* Handle libcalls, which don't provide a type node. */
7875 {
7879 {
7898 }
7901 }
7903 {
7904 /* Pointers are always returned in word_mode. */
7906 }
7912 /* For zero sized structures, construct_container returns NULL, but we
7913 need to keep rest of compiler happy by returning meaningful value. */
7918 }
7920 static rtx
7922 const_tree valtype)
7923 {
7927 {
7929 {
7948 }
7949 }
7951 }
7953 static rtx
7956 {
7968 else
7970 }
7972 static rtx
7975 {
7981 }
7983 /* Pointer function arguments and return values are promoted to
7984 word_mode. */
7986 static enum machine_mode
7990 {
7992 {
7995 }
7997 for_return);
7998 }
8000 /* Return true if a structure, union or array with MODE containing FIELD
8001 should be accessed using BLKmode. */
8003 static bool
8005 {
8006 /* Union with XFmode must be in BLKmode. */
8010 }
8012 rtx
8014 {
8016 }
8018 /* Return true iff type is returned in memory. */
8020 static bool ATTRIBUTE_UNUSED
8022 {
8023 HOST_WIDE_INT size;
8034 {
8035 /* User-created vectors small enough to fit in EAX. */
8039 /* MMX/3dNow values are returned in MM0,
8040 except when it doesn't exits or the ABI prescribes otherwise. */
8044 /* SSE values are returned in XMM0, except when it doesn't exist. */
8048 /* AVX values are returned in YMM0, except when it doesn't exist. */
8052 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8055 }
8063 /* OImode shouldn't be used directly. */
8067 }
8069 static bool ATTRIBUTE_UNUSED
8071 {
8074 }
8076 static bool ATTRIBUTE_UNUSED
8078 {
8081 /* __m128 is returned in xmm0. */
8088 /* Otherwise, the size must be exactly in [1248]. */
8090 }
8092 static bool
8094 {
8095 #ifdef SUBTARGET_RETURN_IN_MEMORY
8097 #else
8101 {
8104 else
8106 }
8107 else
8109 #endif
8110 }
8112 \f
8113 /* Create the va_list data type. */
8115 /* Returns the calling convention specific va_list date type.
8116 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8118 static tree
8120 {
8123 /* For i386 we use plain pointer to argument area. */
8133 unsigned_type_node);
8136 unsigned_type_node);
8139 ptr_type_node);
8142 ptr_type_node);
8161 /* The correct type is an array type of one element. */
8163 }
8165 /* Setup the builtin va_list data type and for 64-bit the additional
8166 calling convention specific va_list data types. */
8168 static tree
8170 {
8173 /* Initialize abi specific va_list builtin types. */
8175 {
8176 tree t;
8178 {
8183 }
8184 else
8185 {
8190 }
8192 {
8197 }
8198 else
8199 {
8204 }
8205 }
8208 }
8210 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8212 static void
8214 {
8216 alias_set_type set;
8219 /* GPR size of varargs save area. */
8222 else
8225 /* FPR size of varargs save area. We don't need it if we don't pass
8226 anything in SSE registers. */
8229 else
8243 {
8251 }
8254 {
8258 /* Now emit code to save SSE registers. The AX parameter contains number
8259 of SSE parameter registers used to call this function, though all we
8260 actually check here is the zero/non-zero status. */
8265 label));
8267 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8268 we used movdqa (i.e. TImode) instead? Perhaps even better would
8269 be if we could determine the real mode of the data, via a hook
8270 into pass_stdarg. Ignore all that for now. */
8280 {
8289 }
8292 }
8293 }
8295 static void
8297 {
8301 /* Reset to zero, as there might be a sysv vaarg used
8302 before. */
8307 {
8318 }
8319 }
8321 static void
8325 {
8327 CUMULATIVE_ARGS next_cum;
8328 tree fntype;
8330 /* This argument doesn't appear to be used anymore. Which is good,
8331 because the old code here didn't suppress rtl generation. */
8339 /* For varargs, we do not want to skip the dummy va_dcl argument.
8340 For stdargs, we do want to skip the last named argument. */
8348 else
8350 }
8352 /* Checks if TYPE is of kind va_list char *. */
8354 static bool
8356 {
8357 tree canonic;
8359 /* For 32-bit it is always true. */
8365 }
8367 /* Implement va_start. */
8369 static void
8371 {
8375 tree type;
8376 rtx ovf_rtx;
8380 {
8383 /* When we are splitting the stack, we can't refer to the stack
8384 arguments using internal_arg_pointer, because they may be on
8385 the old stack. The split stack prologue will arrange to
8386 leave a pointer to the old stack arguments in a scratch
8387 register, which we here copy to a pseudo-register. The split
8388 stack prologue can't set the pseudo-register directly because
8389 it (the prologue) runs before any registers have been saved. */
8393 {
8407 }
8408 }
8410 /* Only 64bit target needs something special. */
8412 {
8415 else
8416 {
8425 }
8427 }
8436 /* The following should be folded into the MEM_REF offset. */
8446 /* Count number of gp and fp argument registers used. */
8452 {
8458 }
8461 {
8467 }
8469 /* Find the overflow area. */
8473 else
8483 {
8484 /* Find the register save area.
8485 Prologue of the function save it right above stack frame. */
8493 }
8494 }
8496 /* Implement va_arg. */
8498 static tree
8501 {
8508 rtx container;
8510 tree ptrtype;
8514 /* Only 64bit target needs something special. */
8538 {
8551 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8553 {
8556 }
8564 }
8566 /* Pull the value out of the saved registers. */
8571 {
8585 /* In case we are passing structure, verify that it is consecutive block
8586 on the register save area. If not we need to do moves. */
8588 {
8589 /* Verify that all registers are strictly consecutive */
8591 {
8595 {
8600 }
8601 }
8602 else
8603 {
8607 {
8612 }
8613 }
8614 }
8616 {
8619 }
8620 else
8621 {
8624 }
8626 /* First ensure that we fit completely in registers. */
8628 {
8635 }
8637 {
8645 }
8647 /* Compute index to start of area used for integer regs. */
8649 {
8650 /* int_addr = gpr + sav; */
8653 }
8655 {
8656 /* sse_addr = fpr + sav; */
8659 }
8661 {
8665 /* addr = &temp; */
8670 {
8674 tree piece_type;
8675 tree addr_type;
8676 tree daddr_type;
8685 {
8690 }
8694 else
8701 {
8704 }
8705 else
8706 {
8709 }
8716 {
8721 }
8722 else
8723 {
8724 tree copy
8729 }
8731 }
8732 }
8735 {
8739 }
8742 {
8746 }
8751 }
8753 /* ... otherwise out of the overflow area. */
8755 /* When we align parameter on stack for caller, if the parameter
8756 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8757 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8758 here with caller. */
8763 /* Care for on-stack alignment if needed. */
8766 else
8767 {
8772 }
8789 }
8790 \f
8791 /* Return true if OPNUM's MEM should be matched
8792 in movabs* patterns. */
8794 bool
8796 {
8808 }
8809 \f
8810 /* Initialize the table of extra 80387 mathematical constants. */
8812 static void
8814 {
8816 {
8822 };
8826 {
8828 /* Ensure each constant is rounded to XFmode precision. */
8831 }
8834 }
8836 /* Return non-zero if the constant is something that
8837 can be loaded with a special instruction. */
8839 int
8841 {
8844 REAL_VALUE_TYPE r;
8856 /* For XFmode constants, try to find a special 80387 instruction when
8857 optimizing for size or on those CPUs that benefit from them. */
8860 {
8869 }
8871 /* Load of the constant -0.0 or -1.0 will be split as
8872 fldz;fchs or fld1;fchs sequence. */
8879 }
8881 /* Return the opcode of the special instruction to be used to load
8882 the constant X. */
8886 {
8888 {
8908 }
8909 }
8911 /* Return the CONST_DOUBLE representing the 80387 constant that is
8912 loaded by the specified special instruction. The argument IDX
8913 matches the return value from standard_80387_constant_p. */
8915 rtx
8917 {
8924 {
8935 }
8938 XFmode);
8939 }
8941 /* Return 1 if X is all 0s and 2 if x is all 1s
8942 in supported SSE/AVX vector mode. */
8944 int
8946 {
8953 {
8974 }
8977 }
8979 /* Return the opcode of the special instruction to be used to load
8980 the constant X. */
8984 {
8986 {
8989 {
9011 }
9020 else
9025 }
9027 }
9029 /* Returns true if OP contains a symbol reference */
9031 bool
9033 {
9042 {
9044 {
9050 }
9054 }
9057 }
9059 /* Return true if it is appropriate to emit `ret' instructions in the
9060 body of a function. Do this only if the epilogue is simple, needing a
9061 couple of insns. Prior to reloading, we can't tell how many registers
9062 must be saved, so return false then. Return false if there is no frame
9063 marker to de-allocate. */
9065 bool
9067 {
9073 /* Don't allow more than 32k pop, since that's all we can do
9074 with one instruction. */
9081 }
9082 \f
9083 /* Value should be nonzero if functions must have frame pointers.
9084 Zero means the frame pointer need not be set up (and parms may
9085 be accessed via the stack pointer) in functions that seem suitable. */
9087 static bool
9089 {
9090 /* If we accessed previous frames, then the generated code expects
9091 to be able to access the saved ebp value in our frame. */
9095 /* Several x86 os'es need a frame pointer for other reasons,
9096 usually pertaining to setjmp. */
9100 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9104 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9105 allocation is 4GB. */
9109 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9110 turns off the frame pointer by default. Turn it back on now if
9111 we've not got a leaf function. */
9121 }
9123 /* Record that the current function accesses previous call frames. */
9125 void
9127 {
9129 }
9130 \f
9131 #ifndef USE_HIDDEN_LINKONCE
9132 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9133 # define USE_HIDDEN_LINKONCE 1
9134 # else
9135 # define USE_HIDDEN_LINKONCE 0
9136 # endif
9137 #endif
9141 /* Fills in the label name that should be used for a pc thunk for
9142 the given register. */
9144 static void
9146 {
9151 else
9153 }
9156 /* This function generates code for -fpic that loads %ebx with
9157 the return address of the caller and then returns. */
9159 static void
9161 {
9166 {
9168 tree decl;
9184 #if TARGET_MACHO
9186 {
9195 }
9196 else
9197 #endif
9199 {
9210 }
9211 else
9212 {
9215 }
9221 /* Make sure unwind info is emitted for the thunk if needed. */
9224 /* Pad stack IP move with 4 instructions (two NOPs count
9225 as one instruction). */
9227 {
9232 }
9243 }
9247 }
9249 /* Emit code for the SET_GOT patterns. */
9253 {
9259 {
9260 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9265 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9266 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9267 an unadorned address. */
9272 }
9277 {
9279 /* We don't need a pic base, we're not producing pic. */
9286 }
9287 else
9288 {
9297 #if TARGET_MACHO
9298 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9299 This is what will be referenced by the Mach-O PIC subsystem. */
9303 /* When we are restoring the pic base at the site of a nonlocal label,
9304 and we decided to emit the pic base above, we will still output a
9305 local label used for calculating the correction offset (even though
9306 the offset will be 0 in that case). */
9310 #endif
9311 }
9317 }
9319 /* Generate an "push" pattern for input ARG. */
9321 static rtx
9323 {
9336 stack_pointer_rtx)),
9337 arg);
9338 }
9340 /* Generate an "pop" pattern for input ARG. */
9342 static rtx
9344 {
9349 arg,
9352 stack_pointer_rtx)));
9353 }
9355 /* Return >= 0 if there is an unused call-clobbered register available
9356 for the entire function. */
9358 static unsigned int
9360 {
9364 {
9366 /* Can't use the same register for both PIC and DRAP. */
9369 else
9374 }
9377 }
9379 /* Return TRUE if we need to save REGNO. */
9381 static bool
9383 {
9394 {
9397 {
9403 }
9404 }
9415 }
9417 /* Return number of saved general prupose registers. */
9419 static int
9421 {
9427 nregs ++;
9429 }
9431 /* Return number of saved SSE registrers. */
9433 static int
9435 {
9443 nregs ++;
9445 }
9447 /* Given FROM and TO register numbers, say whether this elimination is
9448 allowed. If stack alignment is needed, we can only replace argument
9449 pointer with hard frame pointer, or replace frame pointer with stack
9450 pointer. Otherwise, frame pointer elimination is automatically
9451 handled and all other eliminations are valid. */
9453 static bool
9455 {
9461 else
9463 }
9465 /* Return the offset between two registers, one to be eliminated, and the other
9466 its replacement, at the start of a routine. */
9468 HOST_WIDE_INT
9470 {
9479 else
9480 {
9488 }
9489 }
9491 /* In a dynamically-aligned function, we can't know the offset from
9492 stack pointer to frame pointer, so we must ensure that setjmp
9493 eliminates fp against the hard fp (%ebp) rather than trying to
9494 index from %esp up to the top of the frame across a gap that is
9495 of unknown (at compile-time) size. */
9496 static rtx
9498 {
9500 }
9502 /* When using -fsplit-stack, the allocation routines set a field in
9503 the TCB to the bottom of the stack plus this much space, measured
9504 in bytes. */
9506 #define SPLIT_STACK_AVAILABLE 256
9508 /* Fill structure ix86_frame about frame of currently computed function. */
9510 static void
9512 {
9514 HOST_WIDE_INT offset;
9517 HOST_WIDE_INT to_allocate;
9525 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9526 function prologues and leaf. */
9530 {
9535 }
9541 /* For SEH we have to limit the amount of code movement into the prologue.
9542 At present we do this via a BLOCKAGE, at which point there's very little
9543 scheduling that can be done, which means that there's very little point
9544 in doing anything except PUSHs. */
9548 /* During reload iteration the amount of registers saved can change.
9549 Recompute the value as needed. Do not recompute when amount of registers
9550 didn't change as reload does multiple calls to the function and does not
9551 expect the decision to change within single iteration. */
9554 {
9560 /* The fast prologue uses move instead of push to save registers. This
9561 is significantly longer, but also executes faster as modern hardware
9562 can execute the moves in parallel, but can't do that for push/pop.
9564 Be careful about choosing what prologue to emit: When function takes
9565 many instructions to execute we may use slow version as well as in
9566 case function is known to be outside hot spot (this is known with
9567 feedback only). Weight the size of function by number of registers
9568 to save as it is cheap to use one or two push instructions but very
9569 slow to use many of them. */
9573 || (flag_branch_probabilities
9576 else
9579 }
9581 frame->save_regs_using_mov
9583 /* If static stack checking is enabled and done with probes,
9584 the registers need to be saved before allocating the frame. */
9587 /* Skip return address. */
9590 /* Skip pushed static chain. */
9594 /* Skip saved base pointer. */
9599 /* The traditional frame pointer location is at the top of the frame. */
9602 /* Register save area */
9606 /* On SEH target, registers are pushed just before the frame pointer
9607 location. */
9611 /* Align and set SSE register save area. */
9613 {
9614 /* The only ABI that has saved SSE registers (Win64) also has a
9615 16-byte aligned default stack, and thus we don't need to be
9616 within the re-aligned local stack frame to save them. */
9620 }
9623 /* The re-aligned stack starts here. Values before this point are not
9624 directly comparable with values below this point. In order to make
9625 sure that no value happens to be the same before and after, force
9626 the alignment computation below to add a non-zero value. */
9630 /* Va-arg area */
9634 /* Align start of frame for local function. */
9643 /* Frame pointer points here. */
9648 /* Add outgoing arguments area. Can be skipped if we eliminated
9649 all the function calls as dead code.
9650 Skipping is however impossible when function calls alloca. Alloca
9651 expander assumes that last crtl->outgoing_args_size
9652 of stack frame are unused. */
9656 {
9659 }
9660 else
9663 /* Align stack boundary. Only needed if we're calling another function
9664 or using alloca. */
9669 /* We've reached end of stack frame. */
9672 /* Size prologue needs to allocate. */
9683 {
9689 }
9690 else
9694 /* The SEH frame pointer location is near the bottom of the frame.
9695 This is enforced by the fact that the difference between the
9696 stack pointer and the frame pointer is limited to 240 bytes in
9697 the unwind data structure. */
9699 {
9700 HOST_WIDE_INT diff;
9702 /* If we can leave the frame pointer where it is, do so. Also, returns
9703 the establisher frame for __builtin_frame_address (0). */
9708 {
9709 /* Ideally we'd determine what portion of the local stack frame
9710 (within the constraint of the lowest 240) is most heavily used.
9711 But without that complication, simply bias the frame pointer
9712 by 128 bytes so as to maximize the amount of the local stack
9713 frame that is addressable with 8-bit offsets. */
9715 }
9716 }
9717 }
9719 /* This is semi-inlined memory_address_length, but simplified
9720 since we know that we're always dealing with reg+offset, and
9721 to avoid having to create and discard all that rtl. */
9725 {
9729 {
9730 /* EBP and R13 cannot be encoded without an offset. */
9732 }
9736 /* ESP and R12 must be encoded with a SIB byte. */
9738 len++;
9741 }
9743 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9744 The valid base registers are taken from CFUN->MACHINE->FS. */
9746 static rtx
9748 {
9754 {
9755 /* Choose the base register most likely to allow the most scheduling
9756 opportunities. Generally FP is valid throughout the function,
9757 while DRAP must be reloaded within the epilogue. But choose either
9758 over the SP due to increased encoding size. */
9761 {
9764 }
9766 {
9769 }
9771 {
9774 }
9775 }
9776 else
9777 {
9778 HOST_WIDE_INT toffset;
9781 /* Choose the base register with the smallest address encoding.
9782 With a tie, choose FP > DRAP > SP. */
9784 {
9788 }
9790 {
9794 {
9798 }
9799 }
9801 {
9805 {
9809 }
9810 }
9811 }
9815 }
9817 /* Emit code to save registers in the prologue. */
9819 static void
9821 {
9823 rtx insn;
9827 {
9830 }
9831 }
9833 /* Emit a single register save at CFA - CFA_OFFSET. */
9835 static void
9837 HOST_WIDE_INT cfa_offset)
9838 {
9846 /* For SSE saves, we need to indicate the 128-bit alignment. */
9857 /* When saving registers into a re-aligned local stack frame, avoid
9858 any tricky guessing by dwarf2out. */
9860 {
9864 {
9865 /* A bit of a hack. We force the DRAP register to be saved in
9866 the re-aligned stack frame, which provides us with a copy
9867 of the CFA that will last past the prologue. Install it. */
9873 }
9874 else
9875 {
9876 /* The frame pointer is a stable reference within the
9877 aligned frame. Use it. */
9884 }
9885 }
9887 /* The memory may not be relative to the current CFA register,
9888 which means that we may need to generate a new pattern for
9889 use by the unwind info. */
9891 {
9896 }
9897 }
9899 /* Emit code to save registers using MOV insns.
9900 First register is stored at CFA - CFA_OFFSET. */
9901 static void
9903 {
9908 {
9911 }
9912 }
9914 /* Emit code to save SSE registers using MOV insns.
9915 First register is stored at CFA - CFA_OFFSET. */
9916 static void
9918 {
9923 {
9926 }
9927 }
9931 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9932 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9933 Don't add the note if the previously saved value will be left untouched
9934 within stack red-zone till return, as unwinders can find the same value
9935 in the register and on the stack. */
9937 static void
9939 {
9945 {
9948 }
9949 else
9950 queued_cfa_restores
9952 }
9954 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9956 static void
9958 {
9959 rtx last;
9963 ;
9968 }
9970 /* Expand prologue or epilogue stack adjustment.
9971 The pattern exist to put a dependency on all ebp-based memory accesses.
9972 STYLE should be negative if instructions should be marked as frame related,
9973 zero if %r11 register is live and cannot be freely used and positive
9974 otherwise. */
9976 static void
9979 {
9981 rtx insn;
9988 else
9989 {
9990 rtx tmp;
9991 /* r11 is used by indirect sibcall return as well, set before the
9992 epilogue and used after the epilogue. */
9995 else
9996 {
10000 }
10006 }
10013 {
10014 rtx r;
10024 }
10026 {
10029 {
10033 }
10034 }
10037 {
10042 {
10045 }
10047 {
10050 }
10051 else
10052 {
10053 /* Else there are two possibilities: SP itself, which we set
10054 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10055 taken care of this by hand along the eh_return path. */
10058 }
10062 }
10063 }
10065 /* Find an available register to be used as dynamic realign argument
10066 pointer regsiter. Such a register will be written in prologue and
10067 used in begin of body, so it must not be
10068 1. parameter passing register.
10069 2. GOT pointer.
10070 We reuse static-chain register if it is available. Otherwise, we
10071 use DI for i386 and R13 for x86-64. We chose R13 since it has
10072 shorter encoding.
10074 Return: the regno of chosen register. */
10076 static unsigned int
10078 {
10082 {
10083 /* Use R13 for nested function or function need static chain.
10084 Since function with tail call may use any caller-saved
10085 registers in epilogue, DRAP must not use caller-saved
10086 register in such case. */
10091 }
10092 else
10093 {
10094 /* Use DI for nested function or function need static chain.
10095 Since function with tail call may use any caller-saved
10096 registers in epilogue, DRAP must not use caller-saved
10097 register in such case. */
10101 /* Reuse static chain register if it isn't used for parameter
10102 passing. */
10104 {
10108 }
10110 }
10111 }
10113 /* Return minimum incoming stack alignment. */
10115 static unsigned int
10117 {
10120 /* Prefer the one specified at command line. */
10123 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10124 if -mstackrealign is used, it isn't used for sibcall check and
10125 estimated stack alignment is 128bit. */
10127 && !TARGET_64BIT
10128 && ix86_force_align_arg_pointer
10131 else
10134 /* Incoming stack alignment can be changed on individual functions
10135 via force_align_arg_pointer attribute. We use the smallest
10136 incoming stack boundary. */
10142 /* The incoming stack frame has to be aligned at least at
10143 parm_stack_boundary. */
10147 /* Stack at entrance of main is aligned by runtime. We use the
10148 smallest incoming stack boundary. */
10156 }
10158 /* Update incoming stack boundary and estimated stack alignment. */
10160 static void
10162 {
10163 ix86_incoming_stack_boundary
10166 /* x86_64 vararg needs 16byte stack alignment for register save
10167 area. */
10172 }
10174 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10175 needed or an rtx for DRAP otherwise. */
10177 static rtx
10179 {
10184 {
10185 /* Assign DRAP to vDRAP and returns vDRAP */
10187 rtx drap_vreg;
10188 rtx arg_ptr;
10201 {
10204 }
10206 }
10207 else
10209 }
10211 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10213 static rtx
10215 {
10217 }
10220 rtx reg;
10222 };
10224 /* Return a short-lived scratch register for use on function entry.
10225 In 32-bit mode, it is valid only after the registers are saved
10226 in the prologue. This register must be released by means of
10227 release_scratch_register_on_entry once it is dead. */
10229 static void
10231 {
10237 {
10238 /* We always use R11 in 64-bit mode. */
10240 }
10241 else
10242 {
10244 bool fastcall_p
10246 bool thiscall_p
10250 int drap_regno
10253 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10254 for the static chain register. */
10258 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10259 for the static chain register. */
10264 /* ecx is the static chain register. */
10266 && !static_chain_p
10271 /* esi is the static chain register. */
10277 else
10278 {
10281 }
10282 }
10286 {
10289 }
10290 }
10292 /* Release a scratch register obtained from the preceding function. */
10294 static void
10296 {
10298 {
10302 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10308 }
10309 }
10311 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10313 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10315 static void
10317 {
10318 /* We skip the probe for the first interval + a small dope of 4 words and
10319 probe that many bytes past the specified size to maintain a protection
10320 area at the botton of the stack. */
10324 /* See if we have a constant small number of probes to generate. If so,
10325 that's the easy case. The run-time loop is made up of 11 insns in the
10326 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10327 for n # of intervals. */
10329 {
10333 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10334 values of N from 1 until it exceeds SIZE. If only one probe is
10335 needed, this will not generate any code. Then adjust and probe
10336 to PROBE_INTERVAL + SIZE. */
10338 {
10340 {
10343 }
10344 else
10351 }
10355 else
10363 /* Adjust back to account for the additional first interval. */
10367 }
10369 /* Otherwise, do the same as above, but in a loop. Note that we must be
10370 extra careful with variables wrapping around because we might be at
10371 the very top (or the very bottom) of the address space and we have
10372 to be able to handle this case properly; in particular, we use an
10373 equality test for the loop condition. */
10374 else
10375 {
10376 HOST_WIDE_INT rounded_size;
10382 /* Step 1: round SIZE to the previous multiple of the interval. */
10387 /* Step 2: compute initial and final value of the loop counter. */
10389 /* SP = SP_0 + PROBE_INTERVAL. */
10394 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10398 stack_pointer_rtx)));
10401 /* Step 3: the loop
10403 while (SP != LAST_ADDR)
10404 {
10405 SP = SP + PROBE_INTERVAL
10406 probe at SP
10407 }
10409 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10410 values of N from 1 until it is equal to ROUNDED_SIZE. */
10415 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10416 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10419 {
10424 }
10426 /* Adjust back to account for the additional first interval. */
10432 }
10436 /* Even if the stack pointer isn't the CFA register, we need to correctly
10437 describe the adjustments made to it, in particular differentiate the
10438 frame-related ones from the frame-unrelated ones. */
10440 {
10453 }
10455 /* Make sure nothing is scheduled before we are done. */
10457 }
10459 /* Adjust the stack pointer up to REG while probing it. */
10463 {
10473 /* Jump to END_LAB if SP == LAST_ADDR. */
10481 /* SP = SP + PROBE_INTERVAL. */
10485 /* Probe at SP. */
10496 }
10498 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10499 inclusive. These are offsets from the current stack pointer. */
10501 static void
10503 {
10504 /* See if we have a constant small number of probes to generate. If so,
10505 that's the easy case. The run-time loop is made up of 7 insns in the
10506 generic case while the compile-time loop is made up of n insns for n #
10507 of intervals. */
10509 {
10510 HOST_WIDE_INT i;
10512 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10513 it exceeds SIZE. If only one probe is needed, this will not
10514 generate any code. Then probe at FIRST + SIZE. */
10521 }
10523 /* Otherwise, do the same as above, but in a loop. Note that we must be
10524 extra careful with variables wrapping around because we might be at
10525 the very top (or the very bottom) of the address space and we have
10526 to be able to handle this case properly; in particular, we use an
10527 equality test for the loop condition. */
10528 else
10529 {
10536 /* Step 1: round SIZE to the previous multiple of the interval. */
10541 /* Step 2: compute initial and final value of the loop counter. */
10543 /* TEST_OFFSET = FIRST. */
10546 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10550 /* Step 3: the loop
10552 while (TEST_ADDR != LAST_ADDR)
10553 {
10554 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10555 probe at TEST_ADDR
10556 }
10558 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10559 until it is equal to ROUNDED_SIZE. */
10564 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10565 that SIZE is equal to ROUNDED_SIZE. */
10570 stack_pointer_rtx,
10575 }
10577 /* Make sure nothing is scheduled before we are done. */
10579 }
10581 /* Probe a range of stack addresses from REG to END, inclusive. These are
10582 offsets from the current stack pointer. */
10586 {
10596 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10604 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10608 /* Probe at TEST_ADDR. */
10621 }
10623 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10624 to be generated in correct form. */
10625 static void
10627 {
10628 /* Check if stack realign is really needed after reload, and
10629 stores result in cfun */
10630 unsigned int incoming_stack_boundary
10639 {
10640 /* After stack_realign_needed is finalized, we can't no longer
10641 change it. */
10644 }
10646 /* If the only reason for frame_pointer_needed is that we conservatively
10647 assumed stack realignment might be needed, but in the end nothing that
10648 needed the stack alignment had been spilled, clear frame_pointer_needed
10649 and say we don't need stack realignment. */
10651 && frame_pointer_needed
10653 && flag_omit_frame_pointer
10655 && !ix86_current_function_calls_tls_descriptor
10664 {
10666 basic_block bb;
10673 HARD_FRAME_POINTER_REGNUM);
10675 {
10676 rtx insn;
10680 set_up_by_prologue))
10681 {
10685 }
10686 }
10688 /* If drap has been set, but it actually isn't live at the start
10689 of the function, there is no reason to set it up. */
10691 {
10694 {
10697 }
10698 }
10699 else
10714 }
10718 }
10720 /* Expand the prologue into a bunch of separate insns. */
10722 void
10724 {
10729 HOST_WIDE_INT allocate;
10735 /* DRAP should not coexist with stack_realign_fp */
10740 /* Initialize CFA state for before the prologue. */
10744 /* Track SP offset to the CFA. We continue tracking this after we've
10745 swapped the CFA register away from SP. In the case of re-alignment
10746 this is fudged; we're interested to offsets within the local frame. */
10753 {
10754 /* We should have already generated an error for any use of
10755 ms_hook on a nested function. */
10758 /* Check if profiling is active and we shall use profiling before
10759 prologue variant. If so sorry. */
10764 /* In ix86_asm_output_function_label we emitted:
10765 8b ff movl.s %edi,%edi
10766 55 push %ebp
10767 8b ec movl.s %esp,%ebp
10769 This matches the hookable function prologue in Win32 API
10770 functions in Microsoft Windows XP Service Pack 2 and newer.
10771 Wine uses this to enable Windows apps to hook the Win32 API
10772 functions provided by Wine.
10774 What that means is that we've already set up the frame pointer. */
10778 {
10781 /* We've decided to use the frame pointer already set up.
10782 Describe this to the unwinder by pretending that both
10783 push and mov insns happen right here.
10785 Putting the unwind info here at the end of the ms_hook
10786 is done so that we can make absolutely certain we get
10787 the required byte sequence at the start of the function,
10788 rather than relying on an assembler that can produce
10789 the exact encoding required.
10791 However it does mean (in the unpatched case) that we have
10792 a 1 insn window where the asynchronous unwind info is
10793 incorrect. However, if we placed the unwind info at
10794 its correct location we would have incorrect unwind info
10795 in the patched case. Which is probably all moot since
10796 I don't expect Wine generates dwarf2 unwind info for the
10797 system libraries that use this feature. */
10803 stack_pointer_rtx);
10811 /* Note that gen_push incremented m->fs.cfa_offset, even
10812 though we didn't emit the push insn here. */
10816 }
10817 else
10818 {
10819 /* The frame pointer is not needed so pop %ebp again.
10820 This leaves us with a pristine state. */
10822 }
10823 }
10825 /* The first insn of a function that accepts its static chain on the
10826 stack is to push the register that would be filled in by a direct
10827 call. This insn will be skipped by the trampoline. */
10829 {
10833 /* We don't want to interpret this push insn as a register save,
10834 only as a stack adjustment. The real copy of the register as
10835 a save will be done later, if needed. */
10840 }
10842 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10843 of DRAP is needed and stack realignment is really needed after reload */
10845 {
10848 /* Only need to push parameter pointer reg if it is caller saved. */
10850 {
10851 /* Push arg pointer reg */
10854 }
10856 /* Grab the argument pointer. */
10863 /* Align the stack. */
10865 stack_pointer_rtx,
10869 /* Replicate the return address on the stack so that return
10870 address can be reached via (argp - 1) slot. This is needed
10871 to implement macro RETURN_ADDR_RTX and intrinsic function
10872 expand_builtin_return_addr etc. */
10878 /* For the purposes of frame and register save area addressing,
10879 we've started over with a new frame. */
10882 }
10888 {
10889 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10890 slower on all targets. Also sdb doesn't like it. */
10894 /* Push registers now, before setting the frame pointer
10895 on SEH target. */
10897 && TARGET_SEH
10899 {
10903 }
10906 {
10914 }
10915 }
10918 {
10919 /* If saving registers via PUSH, do so now. */
10921 {
10925 }
10927 /* When using red zone we may start register saving before allocating
10928 the stack frame saving one cycle of the prologue. However, avoid
10929 doing this if we have to probe the stack; at least on x86_64 the
10930 stack probe can turn into a call that clobbers a red zone location. */
10932 && (! TARGET_STACK_PROBE
10934 {
10937 }
10938 }
10941 {
10945 /* The computation of the size of the re-aligned stack frame means
10946 that we must allocate the size of the register save area before
10947 performing the actual alignment. Otherwise we cannot guarantee
10948 that there's enough storage above the realignment point. */
10955 /* Align the stack. */
10957 stack_pointer_rtx,
10960 /* For the purposes of register save area addressing, the stack
10961 pointer is no longer valid. As for the value of sp_offset,
10962 see ix86_compute_frame_layout, which we need to match in order
10963 to pass verification of stack_pointer_offset at the end. */
10966 }
10971 {
10972 /* We start to count from ARG_POINTER. */
10975 /* If it was realigned, take into account the fake frame. */
10977 {
10984 /* This over-estimates by 1 minimal-stack-alignment-unit but
10985 mitigates that by counting in the new return address slot. */
10986 current_function_dynamic_stack_size
10988 }
10991 }
10993 /* On SEH target with very large frame size, allocate an area to save
10994 SSE registers (as the very large allocation won't be described). */
10998 {
10999 HOST_WIDE_INT sse_size =
11004 /* No need to do stack checking as the area will be immediately
11005 written. */
11012 }
11014 /* The stack has already been decremented by the instruction calling us
11015 so probe if the size is non-negative to preserve the protection area. */
11017 {
11018 /* We expect the registers to be saved when probes are used. */
11022 {
11025 {
11028 }
11029 }
11030 else
11031 {
11038 {
11040 {
11043 }
11044 else
11046 }
11047 else
11048 {
11050 {
11054 }
11055 else
11057 }
11058 }
11059 }
11062 ;
11065 {
11069 }
11070 else
11071 {
11083 {
11086 /* Note that SEH directives need to continue tracking the stack
11087 pointer even after the frame pointer has been set up. */
11089 {
11097 }
11098 }
11101 {
11106 {
11114 }
11115 }
11120 /* Use the fact that AX still contains ALLOCATE. */
11122 ? gen_pro_epilogue_adjust_stack_di_sub
11129 {
11137 }
11140 /* Use stack_pointer_rtx for relative addressing so that code
11141 works for realigned stack, too. */
11143 {
11150 }
11152 {
11157 }
11158 }
11161 /* If we havn't already set up the frame pointer, do so now. */
11163 {
11175 }
11183 /* We don't use pic-register for pe-coff target. */
11185 && !TARGET_PECOFF
11188 {
11195 }
11198 {
11200 {
11202 {
11212 label));
11216 }
11217 else
11219 }
11220 else
11221 {
11225 }
11226 }
11228 /* In the pic_reg_used case, make sure that the got load isn't deleted
11229 when mcount needs it. Blockage to avoid call movement across mcount
11230 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11231 note. */
11236 {
11237 /* vDRAP is setup but after reload it turns out stack realign
11238 isn't necessary, here we will emit prologue to setup DRAP
11239 without stack realign adjustment */
11242 }
11244 /* Prevent instructions from being scheduled into register save push
11245 sequence when access to the redzone area is done through frame pointer.
11246 The offset between the frame pointer and the stack pointer is calculated
11247 relative to the value of the stack pointer at the end of the function
11248 prologue, and moving instructions that access redzone area via frame
11249 pointer inside push sequence violates this assumption. */
11253 /* Emit cld instruction if stringops are used in the function. */
11257 /* SEH requires that the prologue end within 256 bytes of the start of
11258 the function. Prevent instruction schedules that would extend that.
11259 Further, prevent alloca modifications to the stack pointer from being
11260 combined with prologue modifications. */
11263 }
11265 /* Emit code to restore REG using a POP insn. */
11267 static void
11269 {
11278 {
11279 /* Previously we'd represented the CFA as an expression
11280 like *(%ebp - 8). We've just popped that value from
11281 the stack, which means we need to reset the CFA to
11282 the drap register. This will remain until we restore
11283 the stack pointer. */
11287 /* This means that the DRAP register is valid for addressing too. */
11290 }
11293 {
11300 }
11302 /* When the frame pointer is the CFA, and we pop it, we are
11303 swapping back to the stack pointer as the CFA. This happens
11304 for stack frames that don't allocate other data, so we assume
11305 the stack pointer is now pointing at the return address, i.e.
11306 the function entry state, which makes the offset be 1 word. */
11308 {
11311 {
11319 }
11320 }
11321 }
11323 /* Emit code to restore saved registers using POP insns. */
11325 static void
11327 {
11333 }
11335 /* Emit code and notes for the LEAVE instruction. */
11337 static void
11339 {
11351 {
11359 }
11362 }
11364 /* Emit code to restore saved registers using MOV insns.
11365 First register is restored from CFA - CFA_OFFSET. */
11366 static void
11369 {
11375 {
11384 {
11385 /* Previously we'd represented the CFA as an expression
11386 like *(%ebp - 8). We've just popped that value from
11387 the stack, which means we need to reset the CFA to
11388 the drap register. This will remain until we restore
11389 the stack pointer. */
11393 /* This means that the DRAP register is valid for addressing. */
11395 }
11396 else
11400 }
11401 }
11403 /* Emit code to restore saved registers using MOV insns.
11404 First register is restored from CFA - CFA_OFFSET. */
11405 static void
11408 {
11413 {
11415 rtx mem;
11425 }
11426 }
11428 /* Restore function stack, frame, and registers. */
11430 void
11432 {
11448 /* The FP must be valid if the frame pointer is present. */
11453 /* We must have *some* valid pointer to the stack frame. */
11456 /* The DRAP is never valid at this point. */
11459 /* See the comment about red zone and frame
11460 pointer usage in ix86_expand_prologue. */
11467 /* Determine the CFA offset of the end of the red-zone. */
11470 {
11471 /* The red-zone begins below the return address. */
11474 /* When the register save area is in the aligned portion of
11475 the stack, determine the maximum runtime displacement that
11476 matches up with the aligned frame. */
11480 }
11482 /* Special care must be taken for the normal return case of a function
11483 using eh_return: the eax and edx registers are marked as saved, but
11484 not restored along this path. Adjust the save location to match. */
11488 /* EH_RETURN requires the use of moves to function properly. */
11491 /* SEH requires the use of pops to identify the epilogue. */
11494 /* If we're only restoring one register and sp is not valid then
11495 using a move instruction to restore the register since it's
11496 less work than reloading sp and popping the register. */
11509 && TARGET_USE_LEAVE
11513 else
11517 {
11518 /* Ensure that the entire register save area is addressable via
11519 the stack pointer, if we will restore via sp. */
11524 {
11528 style,
11530 }
11531 }
11533 /* If there are any SSE registers to restore, then we have to do it
11534 via moves, since there's obviously no pop for SSE regs. */
11540 {
11541 rtx t;
11546 /* eh_return epilogues need %ecx added to the stack pointer. */
11548 {
11551 /* Stack align doesn't work with eh_return. */
11553 /* Neither does regparm nested functions. */
11557 {
11565 /* Note that we use SA as a temporary CFA, as the return
11566 address is at the proper place relative to it. We
11567 pretend this happens at the FP restore insn because
11568 prior to this insn the FP would be stored at the wrong
11569 offset relative to SA, and after this insn we have no
11570 other reasonable register to use for the CFA. We don't
11571 bother resetting the CFA to the SP for the duration of
11572 the return insn. */
11585 }
11586 else
11587 {
11595 {
11599 UNITS_PER_WORD));
11601 }
11602 }
11605 }
11606 }
11607 else
11608 {
11609 /* SEH requires that the function end with (1) a stack adjustment
11610 if necessary, (2) a sequence of pops, and (3) a return or
11611 jump instruction. Prevent insns from the function body from
11612 being scheduled into this sequence. */
11614 {
11615 /* Prevent a catch region from being adjacent to the standard
11616 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11617 several other flags that would be interesting to test are
11618 not yet set up. */
11621 else
11623 }
11625 /* First step is to deallocate the stack frame so that we can
11626 pop the registers. Also do it on SEH target for very large
11627 frame as the emitted instructions aren't allowed by the ABI in
11628 epilogues. */
11630 || (TARGET_SEH
11633 {
11638 }
11640 {
11644 style,
11646 }
11649 }
11651 /* If we used a stack pointer and haven't already got rid of it,
11652 then do so now. */
11654 {
11655 /* If the stack pointer is valid and pointing at the frame
11656 pointer store address, then we only need a pop. */
11659 /* Leave results in shorter dependency chains on CPUs that are
11660 able to grok it fast. */
11665 else
11666 {
11668 hard_frame_pointer_rtx,
11671 }
11672 }
11675 {
11677 rtx insn;
11703 }
11705 /* At this point the stack pointer must be valid, and we must have
11706 restored all of the registers. We may not have deallocated the
11707 entire stack frame. We've delayed this until now because it may
11708 be possible to merge the local stack deallocation with the
11709 deallocation forced by ix86_static_chain_on_stack. */
11714 {
11718 }
11719 else
11722 /* Sibcall epilogues don't want a return instruction. */
11724 {
11727 }
11730 {
11733 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11734 address, do explicit add, and jump indirectly to the caller. */
11737 {
11739 rtx insn;
11741 /* There is no "pascal" calling convention in any 64bit ABI. */
11758 }
11759 else
11761 }
11762 else
11765 /* Restore the state back to the state from the prologue,
11766 so that it's correct for the next epilogue. */
11768 }
11770 /* Reset from the function's potential modifications. */
11772 static void
11774 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11775 {
11778 #if TARGET_MACHO
11779 /* Mach-O doesn't support labels at the end of objects, so if
11780 it looks like we might want one, insert a NOP. */
11781 {
11787 {
11788 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11789 notes only, instead set their CODE_LABEL_NUMBER to -1,
11790 otherwise there would be code generation differences
11791 in between -g and -g0. */
11795 }
11805 }
11806 #endif
11808 }
11810 /* Return a scratch register to use in the split stack prologue. The
11811 split stack prologue is used for -fsplit-stack. It is the first
11812 instructions in the function, even before the regular prologue.
11813 The scratch register can be any caller-saved register which is not
11814 used for parameters or for the static chain. */
11816 static unsigned int
11818 {
11821 else
11822 {
11835 {
11837 {
11841 }
11843 }
11845 {
11849 }
11851 {
11854 else
11855 {
11857 {
11861 }
11863 }
11864 }
11865 else
11866 {
11867 /* FIXME: We could make this work by pushing a register
11868 around the addition and comparison. */
11871 }
11872 }
11873 }
11875 /* A SYMBOL_REF for the function which allocates new stackspace for
11876 -fsplit-stack. */
11880 /* A SYMBOL_REF for the more stack function when using the large
11881 model. */
11885 /* Handle -fsplit-stack. These are the first instructions in the
11886 function, even before the regular prologue. */
11888 void
11890 {
11892 HOST_WIDE_INT allocate;
11897 rtx fn;
11905 /* This is the label we will branch to if we have enough stack
11906 space. We expect the basic block reordering pass to reverse this
11907 branch if optimizing, so that we branch in the unlikely case. */
11910 /* We need to compare the stack pointer minus the frame size with
11911 the stack boundary in the TCB. The stack boundary always gives
11912 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11913 can compare directly. Otherwise we need to do an addition. */
11916 UNSPEC_STACK_CHECK);
11921 else
11922 {
11924 rtx offset;
11926 /* We need a scratch register to hold the stack pointer minus
11927 the required frame size. Since this is the very start of the
11928 function, the scratch register can be any caller-saved
11929 register which is not used for parameters. */
11936 {
11937 /* We don't use ix86_gen_add3 in this case because it will
11938 want to split to lea, but when not optimizing the insn
11939 will not be split after this point. */
11942 offset)));
11943 }
11944 else
11945 {
11948 stack_pointer_rtx));
11949 }
11951 }
11957 /* Mark the jump as very likely to be taken. */
11965 /* Get more stack space. We pass in the desired stack space and the
11966 size of the arguments to copy to the new stack. In 32-bit mode
11967 we push the parameters; __morestack will return on a new stack
11968 anyhow. In 64-bit mode we pass the parameters in r10 and
11969 r11. */
11974 {
11980 /* If this function uses a static chain, it will be in %r10.
11981 Preserve it across the call to __morestack. */
11983 {
11984 rtx rax;
11989 }
11993 {
11994 HOST_WIDE_INT argval;
11997 /* When using the large model we need to load the address
11998 into a register, and we've run out of registers. So we
11999 switch to a different calling convention, and we call a
12000 different function: __morestack_large. We pass the
12001 argument size in the upper 32 bits of r10 and pass the
12002 frame size in the lower 32 bits. */
12007 split_stack_fn_large =
12011 {
12021 UNSPEC_GOT);
12027 }
12028 else
12035 }
12036 else
12037 {
12041 }
12044 }
12045 else
12046 {
12049 }
12055 /* In order to make call/return prediction work right, we now need
12056 to execute a return instruction. See
12057 libgcc/config/i386/morestack.S for the details on how this works.
12059 For flow purposes gcc must not see this as a return
12060 instruction--we need control flow to continue at the subsequent
12061 label. Therefore, we use an unspec. */
12065 /* If we are in 64-bit mode and this function uses a static chain,
12066 we saved %r10 in %rax before calling _morestack. */
12071 /* If this function calls va_start, we need to store a pointer to
12072 the arguments on the old stack, because they may not have been
12073 all copied to the new stack. At this point the old stack can be
12074 found at the frame pointer value used by __morestack, because
12075 __morestack has set that up before calling back to us. Here we
12076 store that pointer in a scratch register, and in
12077 ix86_expand_prologue we store the scratch register in a stack
12078 slot. */
12080 {
12082 rtx frame_reg;
12089 /* 64-bit:
12090 fp -> old fp value
12091 return address within this function
12092 return address of caller of this function
12093 stack arguments
12094 So we add three words to get to the stack arguments.
12096 32-bit:
12097 fp -> old fp value
12098 return address within this function
12099 first argument to __morestack
12100 second argument to __morestack
12101 return address of caller of this function
12102 stack arguments
12103 So we add five words to get to the stack arguments.
12104 */
12115 }
12120 /* If this function calls va_start, we now have to set the scratch
12121 register for the case where we do not call __morestack. In this
12122 case we need to set it based on the stack pointer. */
12124 {
12131 }
12132 }
12134 /* We may have to tell the dataflow pass that the split stack prologue
12135 is initializing a scratch register. */
12137 static void
12139 {
12141 {
12144 }
12145 }
12146 \f
12147 /* Extract the parts of an RTL expression that is a valid memory address
12148 for an instruction. Return 0 if the structure of the address is
12149 grossly off. Return -1 if the address contains ASHIFT, so it is not
12150 strictly valid, but still used for computing length of lea instruction. */
12152 int
12154 {
12159 rtx tmp;
12163 /* Allow zero-extended SImode addresses,
12164 they will be emitted with addr32 prefix. */
12166 {
12169 {
12173 }
12176 {
12183 }
12184 }
12186 /* Allow SImode subregs of DImode addresses,
12187 they will be emitted with addr32 prefix. */
12189 {
12192 {
12196 }
12197 }
12202 {
12205 else
12207 }
12209 {
12214 do
12215 {
12220 }
12227 {
12230 {
12255 /* FALLTHRU */
12259 && TARGET_TLS_DIRECT_SEG_REFS
12262 else
12269 /* FALLTHRU */
12276 else
12291 }
12292 }
12293 }
12295 {
12298 }
12300 {
12301 /* We're called for lea too, which implements ashift on occasion. */
12311 }
12312 else
12316 {
12318 ;
12321 ;
12322 else
12324 }
12326 /* Extract the integral value of scale. */
12328 {
12332 }
12337 /* Avoid useless 0 displacement. */
12341 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12346 {
12347 rtx tmp;
12350 }
12352 /* Special case: %ebp cannot be encoded as a base without a displacement.
12353 Similarly %r13. */
12355 && base_reg
12364 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12365 Avoid this by transforming to [%esi+0].
12366 Reload calls address legitimization without cfun defined, so we need
12367 to test cfun for being non-NULL. */
12373 /* Special case: encode reg+reg instead of reg*2. */
12377 /* Special case: scaling cannot be encoded without base or displacement. */
12388 }
12389 \f
12390 /* Return cost of the memory address x.
12391 For i386, it is better to use a complex address than let gcc copy
12392 the address into a reg and make a new pseudo. But not if the address
12393 requires to two regs - that would mean more pseudos with longer
12394 lifetimes. */
12395 static int
12397 addr_space_t as ATTRIBUTE_UNUSED,
12399 {
12411 /* Attempt to minimize number of registers in the address. */
12417 cost++;
12424 cost++;
12426 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12427 since it's predecode logic can't detect the length of instructions
12428 and it degenerates to vector decoded. Increase cost of such
12429 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12430 to split such addresses or even refuse such addresses at all.
12432 Following addressing modes are affected:
12433 [base+scale*index]
12434 [scale*index+disp]
12435 [base+index]
12437 The first and last case may be avoidable by explicitly coding the zero in
12438 memory address, but I don't have AMD-K6 machine handy to check this
12439 theory. */
12448 }
12449 \f
12450 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12451 this is used for to form addresses to local data when -fPIC is in
12452 use. */
12454 static bool
12456 {
12459 }
12461 /* Determine if a given RTX is a valid constant. We already know this
12462 satisfies CONSTANT_P. */
12464 static bool
12466 {
12468 {
12473 {
12477 }
12482 /* Only some unspecs are valid as "constants". */
12485 {
12501 }
12503 /* We must have drilled down to a symbol. */
12508 /* FALLTHRU */
12511 /* TLS symbols are never valid. */
12515 /* DLLIMPORT symbols are never valid. */
12520 #if TARGET_MACHO
12521 /* mdynamic-no-pic */
12524 #endif
12540 }
12542 /* Otherwise we handle everything else in the move patterns. */
12544 }
12546 /* Determine if it's legal to put X into the constant pool. This
12547 is not possible for the address of thread-local symbols, which
12548 is checked above. */
12550 static bool
12552 {
12553 /* We can always put integral constants and vectors in memory. */
12555 {
12563 }
12565 }
12567 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12568 otherwise zero. */
12570 static bool
12572 {
12578 }
12581 /* Nonzero if the constant value X is a legitimate general operand
12582 when generating PIC code. It is given that flag_pic is on and
12583 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12585 bool
12587 {
12588 rtx inner;
12591 {
12598 /* Only some unspecs are valid as "constants". */
12601 {
12614 }
12615 /* FALLTHRU */
12623 }
12624 }
12626 /* Determine if a given CONST RTX is a valid memory displacement
12627 in PIC mode. */
12629 bool
12631 {
12634 /* In 64bit mode we can allow direct addresses of symbols and labels
12635 when they are not dynamic symbols. */
12637 {
12641 {
12665 /* FALLTHRU */
12668 /* TLS references should always be enclosed in UNSPEC.
12669 The dllimported symbol needs always to be resolved. */
12675 {
12683 /* Function-symbols need to be resolved only for
12684 large-model.
12685 For the small-model we don't need to resolve anything
12686 here. */
12691 /* Non-external symbols don't need to be resolved for
12692 large, and medium-model. */
12697 }
12706 }
12707 }
12713 {
12714 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12715 of GOT tables. We should not need these anyway. */
12727 }
12731 {
12736 }
12745 {
12749 /* We need to check for both symbols and labels because VxWorks loads
12750 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12751 details. */
12755 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12756 While ABI specify also 32bit relocation but we don't produce it in
12757 small PIC model at all. */
12779 }
12782 }
12784 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12785 replace the input X, or the original X if no replacement is called for.
12786 The output parameter *WIN is 1 if the calling macro should goto WIN,
12787 0 if it should not. */
12789 bool
12794 {
12795 /* Reload can generate:
12797 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12798 (reg:DI 97))
12799 (reg:DI 2 cx))
12801 This RTX is rejected from ix86_legitimate_address_p due to
12802 non-strictness of base register 97. Following this rejection,
12803 reload pushes all three components into separate registers,
12804 creating invalid memory address RTX.
12806 Following code reloads only the invalid part of the
12807 memory address RTX. */
12813 {
12819 {
12824 }
12828 {
12833 }
12837 }
12840 }
12842 /* Determine if op is suitable RTX for an address register.
12843 Return naked register if a register or a register subreg is
12844 found, otherwise return NULL_RTX. */
12846 static rtx
12848 {
12851 /* Only SImode or DImode registers can form the address. */
12858 {
12866 /* Don't allow SUBREGs that span more than a word. It can
12867 lead to spill failures when the register is one word out
12868 of a two word structure. */
12872 /* Allow only SUBREGs of non-eliminable hard registers. */
12875 }
12877 /* Op is not a register. */
12879 }
12881 /* Recognizes RTL expressions that are valid memory addresses for an
12882 instruction. The MODE argument is the machine mode for the MEM
12883 expression that wants to use this address.
12885 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12886 convert common non-canonical forms to canonical form so that they will
12887 be recognized. */
12889 static bool
12892 {
12895 HOST_WIDE_INT scale;
12899 /* Decomposition failed. */
12908 /* Validate base register. */
12910 {
12918 /* Base is not valid. */
12920 }
12922 /* Validate index register. */
12924 {
12932 /* Index is not valid. */
12934 }
12936 /* Index and base should have the same mode. */
12941 /* Address override works only on the (%reg) part of %fs:(%reg). */
12947 /* Validate scale factor. */
12949 {
12951 /* Scale without index. */
12955 /* Scale is not a valid multiplier. */
12957 }
12959 /* Validate displacement. */
12961 {
12966 {
12967 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12968 used. While ABI specify also 32bit relocations, we don't produce
12969 them at all and use IP relative instead. */
12976 /* 64bit address unspec. */
12996 /* Invalid address unspec. */
12998 }
13001 && (flag_pic
13002 || (TARGET_MACHO
13003 #if TARGET_MACHO
13004 && MACHOPIC_INDIRECT
13006 #endif
13007 )))
13008 {
13010 is_legitimate_pic:
13012 {
13013 /* foo@dtpoff(%rX) is ok. */
13020 /* Non-constant pic memory reference. */
13022 }
13025 /* Displacement is an invalid pic construct. */
13027 #if TARGET_MACHO
13030 /* displacment must be referenced via non_lazy_pointer */
13032 #endif
13034 /* This code used to verify that a symbolic pic displacement
13035 includes the pic_offset_table_rtx register.
13037 While this is good idea, unfortunately these constructs may
13038 be created by "adds using lea" optimization for incorrect
13039 code like:
13041 int a;
13042 int foo(int i)
13043 {
13044 return *(&a+i);
13045 }
13047 This code is nonsensical, but results in addressing
13048 GOT table with pic_offset_table_rtx base. We can't
13049 just refuse it easily, since it gets matched by
13050 "addsi3" pattern, that later gets split to lea in the
13051 case output register differs from input. While this
13052 can be handled by separate addsi pattern for this case
13053 that never results in lea, this seems to be easier and
13054 correct fix for crash to disable this test. */
13055 }
13062 /* Displacement is not constant. */
13066 /* Displacement is out of range. */
13068 /* In x32 mode, constant addresses are sign extended to 64bit, so
13069 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13074 }
13076 /* Everything looks valid. */
13078 }
13080 /* Determine if a given RTX is a valid constant address. */
13082 bool
13084 {
13086 }
13087 \f
13088 /* Return a unique alias set for the GOT. */
13090 static alias_set_type
13092 {
13097 }
13099 /* Return a legitimate reference for ORIG (an address) using the
13100 register REG. If REG is 0, a new pseudo is generated.
13102 There are two types of references that must be handled:
13104 1. Global data references must load the address from the GOT, via
13105 the PIC reg. An insn is emitted to do this load, and the reg is
13106 returned.
13108 2. Static data references, constant pool addresses, and code labels
13109 compute the address as an offset from the GOT, whose base is in
13110 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13111 differentiate them from global data objects. The returned
13112 address is the PIC reg + an unspec constant.
13114 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13115 reg also appears in the address. */
13117 static rtx
13119 {
13123 #if TARGET_MACHO
13125 {
13128 /* Use the generic Mach-O PIC machinery. */
13130 }
13131 #endif
13134 {
13138 }
13144 {
13145 rtx tmpreg;
13146 /* This symbol may be referenced via a displacement from the PIC
13147 base address (@GOTOFF). */
13154 {
13156 UNSPEC_GOTOFF);
13158 }
13159 else
13164 else
13169 {
13173 }
13174 else
13176 }
13178 {
13179 /* This symbol may be referenced via a displacement from the PIC
13180 base address (@GOTOFF). */
13187 {
13189 UNSPEC_GOTOFF);
13191 }
13192 else
13198 {
13201 }
13202 }
13204 /* We can't use @GOTOFF for text labels on VxWorks;
13205 see gotoff_operand. */
13207 {
13212 /* For x64 PE-COFF there is no GOT table. So we use address
13213 directly. */
13215 {
13223 }
13225 {
13233 /* Use directly gen_movsi, otherwise the address is loaded
13234 into register for CSE. We don't want to CSE this addresses,
13235 instead we CSE addresses from the GOT table, so skip this. */
13238 }
13239 else
13240 {
13241 /* This symbol must be referenced via a load from the
13242 Global Offset Table (@GOT). */
13258 }
13259 }
13260 else
13261 {
13264 {
13266 {
13269 }
13270 else
13272 }
13274 {
13277 /* We must match stuff we generate before. Assume the only
13278 unspecs that can get here are ours. Not that we could do
13279 anything with them anyway.... */
13285 }
13287 {
13290 /* Check first to see if this is a constant offset from a @GOTOFF
13291 symbol reference. */
13294 {
13296 {
13300 UNSPEC_GOTOFF);
13306 {
13309 }
13310 }
13311 else
13312 {
13315 {
13319 }
13320 }
13321 }
13322 else
13323 {
13326 new_rtx
13330 {
13333 {
13336 new_rtx
13338 }
13339 else
13341 }
13342 else
13343 {
13346 {
13349 }
13351 }
13352 }
13353 }
13354 }
13356 }
13357 \f
13358 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13360 static rtx
13362 {
13366 {
13371 }
13377 }
13379 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13383 static rtx
13385 {
13387 {
13393 }
13396 {
13398 UNSPEC_PLTOFF);
13401 }
13404 }
13406 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13410 rtx
13412 {
13414 {
13415 ix86_tls_module_base_symbol
13420 }
13423 }
13425 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13426 false if we expect this to be used for a memory address and true if
13427 we expect to load the address into a register. */
13429 static rtx
13431 {
13437 /* Fall back to global dynamic model if tool chain cannot support local
13438 dynamic. */
13445 {
13450 {
13453 else
13454 {
13457 }
13458 }
13461 {
13464 else
13474 }
13475 else
13476 {
13480 {
13482 rtx insns;
13485 emit_call_insn
13495 }
13496 else
13498 }
13505 {
13508 else
13509 {
13512 }
13513 }
13516 {
13521 else
13527 }
13528 else
13529 {
13533 {
13538 emit_call_insn
13543 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13544 share the LD_BASE result with other LD model accesses. */
13546 UNSPEC_TLS_LD_BASE);
13550 }
13551 else
13553 }
13561 {
13568 }
13573 {
13575 {
13576 /* The Sun linker took the AMD64 TLS spec literally
13577 and can only handle %rax as destination of the
13578 initial executable code sequence. */
13583 }
13585 /* Generate DImode references to avoid %fs:(%reg32)
13586 problems and linker IE->LE relaxation bug. */
13590 }
13592 {
13597 }
13599 {
13603 }
13604 else
13605 {
13608 }
13618 {
13623 }
13624 else
13625 {
13629 }
13639 {
13643 }
13644 else
13645 {
13649 }
13654 }
13657 }
13659 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13660 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13661 unique refptr-DECL symbol corresponding to symbol DECL. */
13664 htab_t dllimport_map;
13666 static tree
13668 {
13675 tree to;
13676 rtx rtl;
13703 else
13716 {
13718 #ifdef SUB_TARGET_RECORD_STUB
13720 #endif
13721 }
13730 }
13732 /* Expand SYMBOL into its corresponding far-addresse symbol.
13733 WANT_REG is true if we require the result be a register. */
13735 static rtx
13737 {
13738 tree imp_decl;
13739 rtx x;
13748 }
13750 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13751 true if we require the result be a register. */
13753 static rtx
13755 {
13756 tree imp_decl;
13757 rtx x;
13766 }
13768 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13769 is true if we require the result be a register. */
13771 static rtx
13773 {
13778 {
13785 {
13788 }
13789 }
13805 {
13808 }
13810 }
13812 /* Try machine-dependent ways of modifying an illegitimate address
13813 to be legitimate. If we find one, return the new, valid address.
13814 This macro is used in only one place: `memory_address' in explow.c.
13816 OLDX is the address as it was before break_out_memory_refs was called.
13817 In some cases it is useful to look at this to decide what needs to be done.
13819 It is always safe for this macro to do nothing. It exists to recognize
13820 opportunities to optimize the output.
13822 For the 80386, we handle X+REG by loading X into a register R and
13823 using R+REG. R will go in a general reg and indexing will be used.
13824 However, if REG is a broken-out memory address or multiplication,
13825 nothing needs to be done because REG can certainly go in a general reg.
13827 When -fpic is used, special handling is needed for symbolic references.
13828 See comments by legitimize_pic_address in i386.c for details. */
13830 static rtx
13833 {
13844 {
13848 }
13851 {
13855 }
13860 #if TARGET_MACHO
13863 #endif
13865 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13869 {
13874 }
13877 {
13878 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13883 {
13889 }
13894 {
13900 }
13902 /* Put multiply first if it isn't already. */
13904 {
13909 }
13911 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13912 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13913 created by virtual register instantiation, register elimination, and
13914 similar optimizations. */
13916 {
13922 }
13924 /* Canonicalize
13925 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13926 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13931 {
13932 rtx constant;
13936 {
13939 }
13941 {
13944 }
13945 else
13949 {
13956 }
13957 }
13963 {
13966 }
13969 {
13972 }
13980 {
13983 }
13989 {
13993 {
13996 }
14000 }
14003 {
14007 {
14010 }
14014 }
14015 }
14018 }
14019 \f
14020 /* Print an integer constant expression in assembler syntax. Addition
14021 and subtraction are the only arithmetic that may appear in these
14022 expressions. FILE is the stdio stream to write to, X is the rtx, and
14023 CODE is the operand print code from the output string. */
14025 static void
14027 {
14031 {
14040 else
14041 {
14044 /* Mark the decl as referenced so that cgraph will
14045 output the function. */
14049 #if TARGET_MACHO
14053 #endif
14055 }
14063 /* FALLTHRU */
14074 /* This used to output parentheses around the expression,
14075 but that does not work on the 386 (either ATT or BSD assembler). */
14081 {
14082 /* We can use %d if the number is <32 bits and positive. */
14087 else
14089 }
14090 else
14091 /* We can't handle floating point constants;
14092 TARGET_PRINT_OPERAND must handle them. */
14097 /* Some assemblers need integer constants to appear first. */
14099 {
14103 }
14104 else
14105 {
14110 }
14125 {
14129 }
14134 {
14153 /* FIXME: This might be @TPOFF in Sun ld too. */
14162 else
14172 else
14178 #if TARGET_MACHO
14183 #endif
14187 }
14192 }
14193 }
14195 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14196 We need to emit DTP-relative relocations. */
14198 static void ATTRIBUTE_UNUSED
14200 {
14205 {
14213 }
14214 }
14216 /* Return true if X is a representation of the PIC register. This copes
14217 with calls from ix86_find_base_term, where the register might have
14218 been replaced by a cselib value. */
14220 static bool
14222 {
14226 else
14228 }
14230 /* Helper function for ix86_delegitimize_address.
14231 Attempt to delegitimize TLS local-exec accesses. */
14233 static rtx
14235 {
14260 {
14265 }
14271 }
14273 /* In the name of slightly smaller debug output, and to cater to
14274 general assembler lossage, recognize PIC+GOTOFF and turn it back
14275 into a direct symbol reference.
14277 On Darwin, this is necessary to avoid a crash, because Darwin
14278 has a different PIC label for each routine but the DWARF debugging
14279 information is not associated with any particular routine, so it's
14280 necessary to remove references to the PIC label from RTL stored by
14281 the DWARF output code. */
14283 static rtx
14285 {
14287 /* addend is NULL or some rtx if x is something+GOTOFF where
14288 something doesn't include the PIC register. */
14290 /* reg_addend is NULL or a multiple of some register. */
14292 /* const_addend is NULL or a const_int. */
14294 /* This is the result, or NULL. */
14303 {
14310 {
14316 }
14323 {
14326 {
14331 }
14333 }
14338 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14339 and -mcmodel=medium -fpic. */
14340 }
14347 /* %ebx + GOT/GOTOFF */
14348 ;
14350 {
14351 /* %ebx + %reg * scale + GOT/GOTOFF */
14357 else
14358 {
14361 }
14362 }
14363 else
14369 {
14372 }
14393 {
14394 /* If the rest of original X doesn't involve the PIC register, add
14395 addend and subtract pic_offset_table_rtx. This can happen e.g.
14396 for code like:
14397 leal (%ebx, %ecx, 4), %ecx
14398 ...
14399 movl foo@GOTOFF(%ecx), %edx
14400 in which case we return (%ecx - %ebx) + foo. */
14403 pic_offset_table_rtx),
14404 result);
14405 else
14407 }
14409 {
14413 }
14415 }
14417 /* If X is a machine specific address (i.e. a symbol or label being
14418 referenced as a displacement from the GOT implemented using an
14419 UNSPEC), then return the base term. Otherwise return X. */
14421 rtx
14423 {
14424 rtx term;
14427 {
14441 }
14444 }
14445 \f
14446 static void
14449 {
14453 {
14456 }
14461 {
14464 {
14483 }
14487 {
14506 }
14513 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14514 Those same assemblers have the same but opposite lossage on cmov. */
14517 else
14522 {
14535 }
14542 else
14547 {
14560 }
14567 else
14577 else
14588 }
14590 }
14592 /* Print the name of register X to FILE based on its machine mode and number.
14593 If CODE is 'w', pretend the mode is HImode.
14594 If CODE is 'b', pretend the mode is QImode.
14595 If CODE is 'k', pretend the mode is SImode.
14596 If CODE is 'q', pretend the mode is DImode.
14597 If CODE is 'x', pretend the mode is V4SFmode.
14598 If CODE is 't', pretend the mode is V8SFmode.
14599 If CODE is 'g', pretend the mode is V16SFmode.
14600 If CODE is 'h', pretend the reg is the 'high' byte register.
14601 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14602 If CODE is 'd', duplicate the operand for AVX instruction.
14603 */
14605 void
14607 {
14616 {
14620 }
14647 else
14650 /* Irritatingly, AMD extended registers use different naming convention
14651 from the normal registers: "r%d[bwd]" */
14653 {
14658 {
14672 /* no suffix */
14677 }
14679 }
14683 {
14686 {
14689 }
14690 /* FALLTHRU */
14696 /* FALLTHRU */
14699 normal:
14714 {
14719 }
14722 {
14727 }
14731 }
14735 {
14738 else
14740 }
14741 }
14743 /* Locate some local-dynamic symbol still in use by this function
14744 so that we can print its name in some tls_local_dynamic_base
14745 pattern. */
14747 static int
14749 {
14754 {
14757 }
14760 }
14764 {
14765 rtx insn;
14776 }
14778 /* Meaning of CODE:
14779 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14780 C -- print opcode suffix for set/cmov insn.
14781 c -- like C, but print reversed condition
14782 F,f -- likewise, but for floating-point.
14783 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14784 otherwise nothing
14785 R -- print embeded rounding and sae.
14786 r -- print only sae.
14787 z -- print the opcode suffix for the size of the current operand.
14788 Z -- likewise, with special suffixes for x87 instructions.
14789 * -- print a star (in certain assembler syntax)
14790 A -- print an absolute memory reference.
14791 E -- print address with DImode register names if TARGET_64BIT.
14792 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14793 s -- print a shift double count, followed by the assemblers argument
14794 delimiter.
14795 b -- print the QImode name of the register for the indicated operand.
14796 %b0 would print %al if operands[0] is reg 0.
14797 w -- likewise, print the HImode name of the register.
14798 k -- likewise, print the SImode name of the register.
14799 q -- likewise, print the DImode name of the register.
14800 x -- likewise, print the V4SFmode name of the register.
14801 t -- likewise, print the V8SFmode name of the register.
14802 g -- likewise, print the V16SFmode name of the register.
14803 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14804 y -- print "st(0)" instead of "st" as a register.
14805 d -- print duplicated register operand for AVX instruction.
14806 D -- print condition for SSE cmp instruction.
14807 P -- if PIC, print an @PLT suffix.
14808 p -- print raw symbol name.
14809 X -- don't print any sort of PIC '@' suffix for a symbol.
14810 & -- print some in-use local-dynamic symbol name.
14811 H -- print a memory address offset by 8; used for sse high-parts
14812 Y -- print condition for XOP pcom* instruction.
14813 + -- print a branch hint as 'cs' or 'ds' prefix
14814 ; -- print a semicolon (after prefixes due to bug in older gas).
14815 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14816 @ -- print a segment register of thread base pointer load
14817 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14818 */
14820 void
14822 {
14824 {
14826 {
14829 {
14835 /* Intel syntax. For absolute addresses, registers should not
14836 be surrounded by braces. */
14838 {
14843 }
14848 }
14854 /* Wrap address in an UNSPEC to declare special handling. */
14892 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14897 {
14911 output_operand_lossage
14914 }
14917 #endif
14922 {
14923 /* Opcodes don't get size suffixes if using Intel opcodes. */
14928 {
14946 output_operand_lossage
14949 }
14950 }
14953 warning
14955 /* FALLTHRU */
14958 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14963 {
14965 {
14967 #ifdef HAVE_AS_IX86_FILDS
14969 #endif
14977 #ifdef HAVE_AS_IX86_FILDQ
14979 #else
14981 #endif
14986 }
14987 }
14989 {
14990 /* 387 opcodes don't get size suffixes
14991 if the operands are registers. */
14996 {
15012 }
15013 }
15014 else
15015 {
15016 output_operand_lossage
15019 }
15021 output_operand_lossage
15042 {
15045 }
15050 {
15101 }
15105 /* Little bit of braindamage here. The SSE compare instructions
15106 does use completely different names for the comparisons that the
15107 fp conditional moves. */
15109 {
15112 {
15115 }
15121 {
15124 }
15130 {
15133 }
15142 {
15145 }
15151 {
15154 }
15160 {
15163 }
15174 }
15179 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15182 #endif
15187 {
15191 }
15195 file);
15200 {
15204 }
15205 /* It doesn't actually matter what mode we use here, as we're
15206 only going to use this for printing. */
15208 /* Output 'qword ptr' for intel assembler dialect. */
15217 #ifdef HAVE_AS_IX86_HLE
15219 #else
15221 #endif
15223 #ifdef HAVE_AS_IX86_HLE
15225 #else
15227 #endif
15228 /* We do not want to print value of the operand. */
15257 {
15272 }
15285 {
15290 else
15293 }
15296 {
15297 rtx x;
15306 {
15311 {
15313 bool cputaken
15316 /* Emit hints only in the case default branch prediction
15317 heuristics would fail. */
15319 {
15320 /* We use 3e (DS) prefix for taken branches and
15321 2e (CS) prefix for not taken branches. */
15324 else
15326 }
15327 }
15328 }
15330 }
15333 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15335 #endif
15342 /* The kernel uses a different segment register for performance
15343 reasons; a system call would not have to trash the userspace
15344 segment register, which would be expensive. */
15347 else
15362 }
15363 }
15369 {
15370 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15373 {
15376 {
15385 else
15392 }
15394 /* Check for explicit size override (codes 'b', 'w', 'k',
15395 'q' and 'x') */
15409 }
15412 /* Avoid (%rip) for call operands. */
15418 else
15420 }
15423 {
15424 REAL_VALUE_TYPE r;
15432 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15436 else
15438 }
15441 {
15442 REAL_VALUE_TYPE r;
15451 }
15453 /* These float cases don't actually occur as immediate operands. */
15455 {
15460 }
15462 else
15463 {
15464 /* We have patterns that allow zero sets of memory, for instance.
15465 In 64-bit mode, we should probably support all 8-byte vectors,
15466 since we can in fact encode that into an immediate. */
15468 {
15471 }
15474 {
15476 {
15479 }
15482 {
15485 else
15487 }
15488 }
15493 else
15495 }
15496 }
15498 static bool
15500 {
15503 }
15504 \f
15505 /* Print a memory operand whose address is ADDR. */
15507 static void
15509 {
15518 {
15525 }
15527 {
15531 }
15532 else
15543 {
15554 }
15556 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15558 {
15570 }
15572 {
15573 /* Displacement only requires special attention. */
15576 {
15580 }
15583 else
15585 }
15586 else
15587 {
15588 /* Print SImode register names to force addr32 prefix. */
15590 {
15591 #ifdef ENABLE_CHECKING
15594 {
15605 }
15606 #endif
15609 }
15611 && TARGET_X32
15612 && disp
15615 {
15616 /* X32 runs in 64-bit mode, where displacement, DISP, in
15617 address DISP(%r64), is encoded as 32-bit immediate sign-
15618 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15619 address is %r64 + 0xffffffffbffffd00. When %r64 <
15620 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15621 which is invalid for x32. The correct address is %r64
15622 - 0x40000300 == 0xf7ffdd64. To properly encode
15623 -0x40000300(%r64) for x32, we zero-extend negative
15624 displacement by forcing addr32 prefix which truncates
15625 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15626 zero-extend all negative displacements, including -1(%rsp).
15627 However, for small negative displacements, sign-extension
15628 won't cause overflow. We only zero-extend negative
15629 displacements if they < -16*1024*1024, which is also used
15630 to check legitimate address displacements for PIC. */
15632 }
15635 {
15637 {
15642 else
15644 }
15650 {
15655 }
15657 }
15658 else
15659 {
15663 {
15664 /* Pull out the offset of a symbol; print any symbol itself. */
15668 {
15672 }
15680 else
15682 }
15686 {
15689 {
15693 }
15694 }
15697 else
15701 {
15706 }
15708 }
15709 }
15710 }
15712 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15714 static bool
15716 {
15717 rtx op;
15724 {
15727 /* FIXME: This might be @TPOFF in Sun ld. */
15738 else
15750 else
15757 #if TARGET_MACHO
15763 #endif
15766 {
15771 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15773 #else
15775 #endif
15778 }
15783 }
15786 }
15787 \f
15788 /* Split one or more double-mode RTL references into pairs of half-mode
15789 references. The RTL can be REG, offsettable MEM, integer constant, or
15790 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15791 split and "num" is its length. lo_half and hi_half are output arrays
15792 that parallel "operands". */
15794 void
15797 {
15802 {
15811 }
15816 {
15819 /* simplify_subreg refuse to split volatile memory addresses,
15820 but we still have to handle it. */
15822 {
15825 }
15826 else
15827 {
15834 }
15835 }
15836 }
15837 \f
15838 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15839 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15840 is the expression of the binary operation. The output may either be
15841 emitted here, or returned to the caller, like all output_* functions.
15843 There is no guarantee that the operands are the same mode, as they
15844 might be within FLOAT or FLOAT_EXTEND expressions. */
15846 #ifndef SYSV386_COMPAT
15847 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15848 wants to fix the assemblers because that causes incompatibility
15849 with gcc. No-one wants to fix gcc because that causes
15850 incompatibility with assemblers... You can use the option of
15851 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15852 #define SYSV386_COMPAT 1
15853 #endif
15857 {
15863 #ifdef ENABLE_CHECKING
15864 /* Even if we do not want to check the inputs, this documents input
15865 constraints. Which helps in understanding the following code. */
15875 else
15877 #endif
15880 {
15885 else
15894 else
15903 else
15912 else
15919 }
15922 {
15924 {
15928 else
15930 }
15931 else
15932 {
15936 else
15938 }
15940 }
15944 {
15948 {
15952 }
15954 /* know operands[0] == operands[1]. */
15957 {
15960 }
15963 {
15965 /* How is it that we are storing to a dead operand[2]?
15966 Well, presumably operands[1] is dead too. We can't
15967 store the result to st(0) as st(0) gets popped on this
15968 instruction. Instead store to operands[2] (which I
15969 think has to be st(1)). st(1) will be popped later.
15970 gcc <= 2.8.1 didn't have this check and generated
15971 assembly code that the Unixware assembler rejected. */
15973 else
15976 }
15980 else
15987 {
15990 }
15993 {
15996 }
15999 {
16000 #if SYSV386_COMPAT
16001 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16002 derived assemblers, confusingly reverse the direction of
16003 the operation for fsub{r} and fdiv{r} when the
16004 destination register is not st(0). The Intel assembler
16005 doesn't have this brain damage. Read !SYSV386_COMPAT to
16006 figure out what the hardware really does. */
16009 else
16011 #else
16013 /* As above for fmul/fadd, we can't store to st(0). */
16015 else
16017 #endif
16019 }
16022 {
16023 #if SYSV386_COMPAT
16026 else
16028 #else
16031 else
16033 #endif
16035 }
16038 {
16041 else
16044 }
16046 {
16047 #if SYSV386_COMPAT
16049 #else
16051 #endif
16052 }
16053 else
16054 {
16055 #if SYSV386_COMPAT
16057 #else
16059 #endif
16060 }
16065 }
16069 }
16071 /* Check if a 256bit AVX register is referenced inside of EXP. */
16073 static int
16075 {
16086 }
16088 /* Return needed mode for entity in optimize_mode_switching pass. */
16090 static int
16092 {
16094 {
16095 rtx link;
16097 /* Needed mode is set to AVX_U128_CLEAN if there are
16098 no 256bit modes used in function arguments. */
16100 link;
16102 {
16104 {
16109 }
16110 }
16113 }
16115 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16116 changes state only when a 256bit register is written to, but we need
16117 to prevent the compiler from moving optimal insertion point above
16118 eventual read from 256bit register. */
16123 }
16125 /* Return mode that i387 must be switched into
16126 prior to the execution of insn. */
16128 static int
16130 {
16133 /* The mode UNINITIALIZED is used to store control word after a
16134 function call or ASM pattern. The mode ANY specify that function
16135 has no requirements on the control word and make no changes in the
16136 bits we are interested in. */
16150 {
16173 }
16176 }
16178 /* Return mode that entity must be switched into
16179 prior to the execution of insn. */
16181 int
16183 {
16185 {
16195 }
16197 }
16199 /* Check if a 256bit AVX register is referenced in stores. */
16201 static void
16203 {
16205 {
16208 }
16209 }
16211 /* Calculate mode of upper 128bit AVX registers after the insn. */
16213 static int
16215 {
16222 /* We know that state is clean after CALL insn if there are no
16223 256bit registers used in the function return register. */
16225 {
16230 }
16232 /* Otherwise, return current mode. Remember that if insn
16233 references AVX 256bit registers, the mode was already changed
16234 to DIRTY from MODE_NEEDED. */
16236 }
16238 /* Return the mode that an insn results in. */
16240 int
16242 {
16244 {
16254 }
16255 }
16257 static int
16259 {
16260 tree arg;
16262 /* Entry mode is set to AVX_U128_DIRTY if there are
16263 256bit modes used in function arguments. */
16266 {
16271 }
16274 }
16276 /* Return a mode that ENTITY is assumed to be
16277 switched to at function entry. */
16279 int
16281 {
16283 {
16293 }
16294 }
16296 static int
16298 {
16301 /* Exit mode is set to AVX_U128_DIRTY if there are
16302 256bit modes used in the function return register. */
16307 }
16309 /* Return a mode that ENTITY is assumed to be
16310 switched to at function exit. */
16312 int
16314 {
16316 {
16326 }
16327 }
16329 /* Output code to initialize control word copies used by trunc?f?i and
16330 rounding patterns. CURRENT_MODE is set to current control word,
16331 while NEW_MODE is set to new control word. */
16333 static void
16335 {
16337 rtx new_mode;
16348 {
16350 {
16352 /* round toward zero (truncate) */
16358 /* round down toward -oo */
16365 /* round up toward +oo */
16372 /* mask precision exception for nearbyint() */
16379 }
16380 }
16381 else
16382 {
16384 {
16386 /* round toward zero (truncate) */
16392 /* round down toward -oo */
16398 /* round up toward +oo */
16404 /* mask precision exception for nearbyint() */
16411 }
16412 }
16418 }
16420 /* Emit vzeroupper. */
16422 void
16424 {
16427 /* Cancel automatic vzeroupper insertion if there are
16428 live call-saved SSE registers at the insertion point. */
16440 }
16442 /* Generate one or more insns to set ENTITY to MODE. */
16444 void
16446 {
16448 {
16463 }
16464 }
16466 /* Output code for INSN to convert a float to a signed int. OPERANDS
16467 are the insn operands. The output may be [HSD]Imode and the input
16468 operand may be [SDX]Fmode. */
16472 {
16477 /* Jump through a hoop or two for DImode, since the hardware has no
16478 non-popping instruction. We used to do this a different way, but
16479 that was somewhat fragile and broke with post-reload splitters. */
16489 else
16490 {
16495 else
16499 }
16502 }
16504 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16505 have the values zero or one, indicates the ffreep insn's operand
16506 from the OPERANDS array. */
16510 {
16512 #ifdef HAVE_AS_IX86_FFREEP
16514 #else
16515 {
16525 }
16526 #endif
16529 }
16532 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16533 should be used. UNORDERED_P is true when fucom should be used. */
16537 {
16543 {
16546 }
16547 else
16548 {
16551 }
16554 {
16558 else
16560 else
16563 else
16565 }
16572 {
16574 {
16577 }
16578 else
16580 }
16583 && stack_top_dies
16586 {
16587 /* If both the top of the 387 stack dies, and the other operand
16588 is also a stack register that dies, then this must be a
16589 `fcompp' float compare */
16592 {
16593 /* There is no double popping fcomi variant. Fortunately,
16594 eflags is immune from the fstp's cc clobbering. */
16597 else
16600 }
16601 else
16602 {
16605 else
16607 }
16608 }
16609 else
16610 {
16611 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16614 {
16622 NULL,
16623 NULL,
16630 NULL,
16631 NULL,
16632 NULL,
16633 NULL
16634 };
16649 }
16650 }
16652 void
16654 {
16657 #ifdef ASM_QUAD
16660 #else
16662 #endif
16665 }
16667 void
16669 {
16672 #ifdef ASM_QUAD
16675 #else
16677 #endif
16678 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16684 #if TARGET_MACHO
16686 {
16690 }
16691 #endif
16692 else
16695 }
16696 \f
16697 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16698 for the target. */
16700 void
16702 {
16703 rtx tmp;
16705 /* We play register width games, which are only valid after reload. */
16708 /* Avoid HImode and its attendant prefix byte. */
16713 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16715 {
16718 }
16721 }
16723 /* X is an unchanging MEM. If it is a constant pool reference, return
16724 the constant pool rtx, else NULL. */
16726 rtx
16728 {
16735 }
16737 void
16739 {
16747 {
16748 rtx tmp;
16752 {
16758 }
16761 }
16765 {
16768 rtx tmp;
16773 else
16777 {
16784 }
16785 }
16789 {
16791 {
16792 #if TARGET_MACHO
16793 /* dynamic-no-pic */
16795 {
16796 rtx temp = ((reload_in_progress
16804 }
16806 {
16810 }
16813 else
16814 {
16822 }
16823 /* dynamic-no-pic */
16824 #endif
16825 }
16826 else
16827 {
16831 {
16837 }
16838 }
16839 }
16840 else
16841 {
16852 /* Force large constants in 64bit compilation into register
16853 to get them CSEed. */
16865 {
16866 /* If we are loading a floating point constant to a register,
16867 force the value to memory now, since we'll get better code
16868 out the back end. */
16872 {
16877 }
16878 }
16879 }
16882 }
16884 void
16886 {
16893 /* Force constants other than zero into memory. We do not know how
16894 the instructions used to build constants modify the upper 64 bits
16895 of the register, once we have that information we may be able
16896 to handle some of them more efficiently. */
16905 /* We need to check memory alignment for SSE mode since attribute
16906 can make operands unaligned. */
16911 {
16914 /* ix86_expand_vector_move_misalign() does not like constants ... */
16920 /* ... nor both arguments in memory. */
16928 }
16930 /* Make operand1 a register if it isn't already. */
16934 {
16937 }
16940 }
16942 /* Split 32-byte AVX unaligned load and store if needed. */
16944 static void
16946 {
16947 rtx m;
16954 {
16975 }
16978 {
16980 {
16987 }
16988 /* Normal *mov<mode>_internal pattern will handle
16989 unaligned loads just fine if misaligned_operand
16990 is true, and without the UNSPEC it can be combined
16991 with arithmetic instructions. */
16994 else
16996 }
16998 {
17000 {
17005 }
17006 else
17008 }
17009 else
17011 }
17013 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17014 straight to ix86_expand_vector_move. */
17015 /* Code generation for scalar reg-reg moves of single and double precision data:
17016 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17017 movaps reg, reg
17018 else
17019 movss reg, reg
17020 if (x86_sse_partial_reg_dependency == true)
17021 movapd reg, reg
17022 else
17023 movsd reg, reg
17025 Code generation for scalar loads of double precision data:
17026 if (x86_sse_split_regs == true)
17027 movlpd mem, reg (gas syntax)
17028 else
17029 movsd mem, reg
17031 Code generation for unaligned packed loads of single precision data
17032 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17033 if (x86_sse_unaligned_move_optimal)
17034 movups mem, reg
17036 if (x86_sse_partial_reg_dependency == true)
17037 {
17038 xorps reg, reg
17039 movlps mem, reg
17040 movhps mem+8, reg
17041 }
17042 else
17043 {
17044 movlps mem, reg
17045 movhps mem+8, reg
17046 }
17048 Code generation for unaligned packed loads of double precision data
17049 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17050 if (x86_sse_unaligned_move_optimal)
17051 movupd mem, reg
17053 if (x86_sse_split_regs == true)
17054 {
17055 movlpd mem, reg
17056 movhpd mem+8, reg
17057 }
17058 else
17059 {
17060 movsd mem, reg
17061 movhpd mem+8, reg
17062 }
17063 */
17065 void
17067 {
17076 {
17078 {
17082 {
17084 {
17087 }
17088 else
17090 }
17092 /* FALLTHRU */
17096 {
17111 }
17117 else
17125 }
17128 }
17132 {
17134 {
17138 {
17140 {
17143 }
17144 else
17146 }
17148 /* FALLTHRU */
17158 }
17161 }
17164 {
17165 /* Normal *mov<mode>_internal pattern will handle
17166 unaligned loads just fine if misaligned_operand
17167 is true, and without the UNSPEC it can be combined
17168 with arithmetic instructions. */
17174 /* ??? If we have typed data, then it would appear that using
17175 movdqu is the only way to get unaligned data loaded with
17176 integer type. */
17178 {
17180 {
17183 }
17185 /* We will eventually emit movups based on insn attributes. */
17189 }
17191 {
17192 rtx zero;
17195 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17196 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17198 {
17199 /* We will eventually emit movups based on insn attributes. */
17202 }
17204 /* When SSE registers are split into halves, we can avoid
17205 writing to the top half twice. */
17207 {
17210 }
17211 else
17212 {
17213 /* ??? Not sure about the best option for the Intel chips.
17214 The following would seem to satisfy; the register is
17215 entirely cleared, breaking the dependency chain. We
17216 then store to the upper half, with a dependency depth
17217 of one. A rumor has it that Intel recommends two movsd
17218 followed by an unpacklpd, but this is unconfirmed. And
17219 given that the dependency depth of the unpacklpd would
17220 still be one, I'm not sure why this would be better. */
17222 }
17228 }
17229 else
17230 {
17231 rtx t;
17234 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17235 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17237 {
17239 {
17242 }
17249 }
17253 else
17258 else
17267 }
17268 }
17270 {
17272 {
17275 /* We will eventually emit movups based on insn attributes. */
17277 }
17279 {
17281 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17282 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17284 /* We will eventually emit movups based on insn attributes. */
17286 else
17287 {
17292 }
17293 }
17294 else
17295 {
17300 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17301 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17303 {
17306 }
17307 else
17308 {
17313 }
17314 }
17315 }
17316 else
17318 }
17320 /* Helper function of ix86_fixup_binary_operands to canonicalize
17321 operand order. Returns true if the operands should be swapped. */
17323 static bool
17325 rtx operands[])
17326 {
17331 /* If the operation is not commutative, we can't do anything. */
17335 /* Highest priority is that src1 should match dst. */
17341 /* Next highest priority is that immediate constants come second. */
17347 /* Lowest priority is that memory references should come second. */
17354 }
17357 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17358 destination to use for the operation. If different from the true
17359 destination in operands[0], a copy operation will be required. */
17361 rtx
17363 rtx operands[])
17364 {
17369 /* Canonicalize operand order. */
17371 {
17372 rtx temp;
17374 /* It is invalid to swap operands of different modes. */
17380 }
17382 /* Both source operands cannot be in memory. */
17384 {
17385 /* Optimization: Only read from memory once. */
17387 {
17390 }
17393 else
17395 }
17397 /* If the destination is memory, and we do not have matching source
17398 operands, do things in registers. */
17402 /* Source 1 cannot be a constant. */
17406 /* Source 1 cannot be a non-matching memory. */
17410 /* Improve address combine. */
17419 }
17421 /* Similarly, but assume that the destination has already been
17422 set up properly. */
17424 void
17427 {
17430 }
17432 /* Attempt to expand a binary operator. Make the expansion closer to the
17433 actual machine, then just general_operand, which will allow 3 separate
17434 memory references (one output, two input) in a single insn. */
17436 void
17438 rtx operands[])
17439 {
17446 /* Emit the instruction. */
17450 {
17451 /* Reload doesn't know about the flags register, and doesn't know that
17452 it doesn't want to clobber it. We can only do this with PLUS. */
17455 }
17459 {
17460 /* This is going to be an LEA; avoid splitting it later. */
17462 }
17463 else
17464 {
17467 }
17469 /* Fix up the destination if needed. */
17472 }
17474 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17475 the given OPERANDS. */
17477 void
17479 rtx operands[])
17480 {
17483 {
17486 }
17488 {
17491 }
17492 /* Optimize (__m128i) d | (__m128i) e and similar code
17493 when d and e are float vectors into float vector logical
17494 insn. In C/C++ without using intrinsics there is no other way
17495 to express vector logical operation on float vectors than
17496 to cast them temporarily to integer vectors. */
17498 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17507 {
17508 rtx dst;
17510 {
17517 {
17520 }
17521 else
17522 {
17527 }
17538 }
17539 }
17548 }
17550 /* Return TRUE or FALSE depending on whether the binary operator meets the
17551 appropriate constraints. */
17553 bool
17556 {
17561 /* Both source operands cannot be in memory. */
17565 /* Canonicalize operand order for commutative operators. */
17567 {
17571 }
17573 /* If the destination is memory, we must have a matching source operand. */
17577 /* Source 1 cannot be a constant. */
17581 /* Source 1 cannot be a non-matching memory. */
17583 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17591 }
17593 /* Attempt to expand a unary operator. Make the expansion closer to the
17594 actual machine, then just general_operand, which will allow 2 separate
17595 memory references (one output, one input) in a single insn. */
17597 void
17599 rtx operands[])
17600 {
17607 /* If the destination is memory, and we do not have matching source
17608 operands, do things in registers. */
17611 {
17614 else
17616 }
17618 /* When source operand is memory, destination must match. */
17622 /* Emit the instruction. */
17626 {
17627 /* Reload doesn't know about the flags register, and doesn't know that
17628 it doesn't want to clobber it. */
17631 }
17632 else
17633 {
17636 }
17638 /* Fix up the destination if needed. */
17641 }
17643 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17644 divisor are within the range [0-255]. */
17646 void
17649 {
17658 {
17671 }
17678 /* Use 8bit unsigned divimod if dividend and divisor are within
17679 the range [0-255]. */
17688 pc_rtx);
17693 /* Generate original signed/unsigned divimod. */
17698 /* Branch to the end. */
17702 /* Generate 8bit unsigned divide. */
17704 /* Don't use operands[0] for result of 8bit divide since not all
17705 registers support QImode ZERO_EXTRACT. */
17712 {
17715 }
17716 else
17717 {
17720 }
17722 /* Extract remainder from AH. */
17726 else
17727 {
17728 /* Need a new scratch register since the old one has result
17729 of 8bit divide. */
17733 }
17736 /* Zero extend quotient from AL. */
17742 }
17744 /* Whether it is OK to emit CFI directives when emitting asm code. */
17746 bool
17748 {
17750 }
17752 #define LEA_MAX_STALL (3)
17753 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17755 /* Increase given DISTANCE in half-cycles according to
17756 dependencies between PREV and NEXT instructions.
17757 Add 1 half-cycle if there is no dependency and
17758 go to next cycle if there is some dependecy. */
17760 static unsigned int
17762 {
17779 }
17781 /* Function checks if instruction INSN defines register number
17782 REGNO1 or REGNO2. */
17784 static bool
17786 rtx insn)
17787 {
17795 {
17797 }
17800 }
17802 /* Function checks if instruction INSN uses register number
17803 REGNO as a part of address expression. */
17805 static bool
17807 {
17815 }
17817 /* Search backward for non-agu definition of register number REGNO1
17818 or register number REGNO2 in basic block starting from instruction
17819 START up to head of basic block or instruction INSN.
17821 Function puts true value into *FOUND var if definition was found
17822 and false otherwise.
17824 Distance in half-cycles between START and found instruction or head
17825 of BB is added to DISTANCE and returned. */
17827 static int
17831 {
17841 {
17843 {
17846 {
17849 {
17852 }
17853 }
17856 }
17861 }
17864 }
17866 /* Search backward for non-agu definition of register number REGNO1
17867 or register number REGNO2 in INSN's basic block until
17868 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17869 2. Reach neighbour BBs boundary, or
17870 3. Reach agu definition.
17871 Returns the distance between the non-agu definition point and INSN.
17872 If no definition point, returns -1. */
17874 static int
17876 rtx insn)
17877 {
17888 {
17889 edge e;
17890 edge_iterator ei;
17895 {
17898 }
17904 else
17905 {
17910 {
17911 int bb_dist
17917 {
17924 }
17925 }
17928 }
17929 }
17931 /* get_attr_type may modify recog data. We want to make sure
17932 that recog data is valid for instruction INSN, on which
17933 distance_non_agu_define is called. INSN is unchanged here. */
17940 }
17942 /* Return the distance in half-cycles between INSN and the next
17943 insn that uses register number REGNO in memory address added
17944 to DISTANCE. Return -1 if REGNO0 is set.
17946 Put true value into *FOUND if register usage was found and
17947 false otherwise.
17948 Put true value into *REDEFINED if register redefinition was
17949 found and false otherwise. */
17951 static int
17955 {
17964 {
17967 /* If insn and start belong to the same bb, set prev to insn,
17968 so the call to increase_distance will increase the distance
17969 between insns by 1. */
17971 }
17976 {
17978 {
17981 {
17982 /* Return DISTANCE if OP0 is used in memory
17983 address in NEXT. */
17986 }
17989 {
17990 /* Return -1 if OP0 is set in NEXT. */
17993 }
17996 }
18002 }
18005 }
18007 /* Return the distance between INSN and the next insn that uses
18008 register number REGNO0 in memory address. Return -1 if no such
18009 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18011 static int
18013 {
18025 {
18026 edge e;
18027 edge_iterator ei;
18032 {
18035 }
18041 else
18042 {
18048 {
18049 int bb_dist
18054 {
18061 }
18062 }
18065 }
18066 }
18072 }
18074 /* Define this macro to tune LEA priority vs ADD, it take effect when
18075 there is a dilemma of choicing LEA or ADD
18076 Negative value: ADD is more preferred than LEA
18077 Zero: Netrual
18078 Positive value: LEA is more preferred than ADD*/
18079 #define IX86_LEA_PRIORITY 0
18081 /* Return true if usage of lea INSN has performance advantage
18082 over a sequence of instructions. Instructions sequence has
18083 SPLIT_COST cycles higher latency than lea latency. */
18085 static bool
18088 {
18091 /* For Silvermont if using a 2-source or 3-source LEA for
18092 non-destructive destination purposes, or due to wanting
18093 ability to use SCALE, the use of LEA is justified. */
18095 {
18103 }
18109 {
18110 /* If there is no non AGU operand definition, no AGU
18111 operand usage and split cost is 0 then both lea
18112 and non lea variants have same priority. Currently
18113 we prefer lea for 64 bit code and non lea on 32 bit
18114 code. */
18117 else
18119 }
18121 /* With longer definitions distance lea is more preferable.
18122 Here we change it to take into account splitting cost and
18123 lea priority. */
18126 /* If there is no use in memory addess then we just check
18127 that split cost exceeds AGU stall. */
18131 /* If this insn has both backward non-agu dependence and forward
18132 agu dependence, the one with short distance takes effect. */
18134 }
18136 /* Return true if it is legal to clobber flags by INSN and
18137 false otherwise. */
18139 static bool
18141 {
18144 bitmap live;
18147 {
18149 {
18156 }
18162 }
18166 }
18168 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18169 move and add to avoid AGU stalls. */
18171 bool
18173 {
18176 /* Check if we need to optimize. */
18180 /* Check it is correct to split here. */
18188 /* We need to split only adds with non destructive
18189 destination operand. */
18192 else
18194 }
18196 /* Return true if we should emit lea instruction instead of mov
18197 instruction. */
18199 bool
18201 {
18204 /* Check if we need to optimize. */
18208 /* Use lea for reg to reg moves only. */
18216 }
18218 /* Return true if we need to split lea into a sequence of
18219 instructions to avoid AGU stalls. */
18221 bool
18223 {
18229 /* Check we need to optimize. */
18233 /* The "at least two components" test below might not catch simple
18234 move or zero extension insns if parts.base is non-NULL and parts.disp
18235 is const0_rtx as the only components in the address, e.g. if the
18236 register is %rbp or %r13. As this test is much cheaper and moves or
18237 zero extensions are the common case, do this check first. */
18243 /* Check if it is OK to split here. */
18250 /* There should be at least two components in the address. */
18255 /* We should not split into add if non legitimate pic
18256 operand is used as displacement. */
18271 /* Compute how many cycles we will add to execution time
18272 if split lea into a sequence of instructions. */
18274 {
18275 /* Have to use mov instruction if non desctructive
18276 destination form is used. */
18280 /* Have to add index to base if both exist. */
18284 /* Have to use shift and adds if scale is 2 or greater. */
18286 {
18291 else
18293 }
18295 /* Have to use add instruction with immediate if
18296 disp is non zero. */
18300 /* Subtract the price of lea. */
18302 }
18306 }
18308 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18309 matches destination. RTX includes clobber of FLAGS_REG. */
18311 static void
18314 {
18321 }
18323 /* Return true if regno1 def is nearest to the insn. */
18325 static bool
18327 {
18334 {
18336 {
18339 }
18345 }
18347 /* None of the regs is defined in the bb. */
18349 }
18351 /* Split lea instructions into a sequence of instructions
18352 which are executed on ALU to avoid AGU stalls.
18353 It is assumed that it is allowed to clobber flags register
18354 at lea position. */
18356 void
18358 {
18374 {
18377 }
18380 {
18383 }
18389 {
18390 /* Case r1 = r1 + ... */
18392 {
18393 /* If we have a case r1 = r1 + C * r2 then we
18394 should use multiplication which is very
18395 expensive. Assume cost model is wrong if we
18396 have such case here. */
18401 }
18402 else
18403 {
18404 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18408 /* Use shift for scaling. */
18417 }
18418 }
18420 {
18423 }
18424 else
18425 {
18427 {
18430 }
18432 {
18435 }
18436 else
18437 {
18442 else
18443 {
18444 rtx tmp1;
18446 /* Find better operand for SET instruction, depending
18447 on which definition is farther from the insn. */
18450 else
18460 }
18463 }
18467 }
18468 }
18470 /* Return true if it is ok to optimize an ADD operation to LEA
18471 operation to avoid flag register consumation. For most processors,
18472 ADD is faster than LEA. For the processors like BONNELL, if the
18473 destination register of LEA holds an actual address which will be
18474 used soon, LEA is better and otherwise ADD is better. */
18476 bool
18478 {
18483 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18491 }
18493 /* Return true if destination reg of SET_BODY is shift count of
18494 USE_BODY. */
18496 static bool
18498 {
18499 rtx set_dest;
18500 rtx shift_rtx;
18503 /* Retrieve destination of SET_BODY. */
18505 {
18514 use_body))
18519 }
18521 /* Retrieve shift count of USE_BODY. */
18523 {
18535 }
18543 {
18546 /* Return true if shift count is dest of SET_BODY. */
18548 {
18549 /* Add check since it can be invoked before register
18550 allocation in pre-reload schedule. */
18556 }
18557 }
18560 }
18562 /* Return true if destination reg of SET_INSN is shift count of
18563 USE_INSN. */
18565 bool
18567 {
18570 }
18572 /* Return TRUE or FALSE depending on whether the unary operator meets the
18573 appropriate constraints. */
18575 bool
18579 {
18580 /* If one of operands is memory, source and destination must match. */
18586 }
18588 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18589 are ok, keeping in mind the possible movddup alternative. */
18591 bool
18593 {
18599 }
18601 /* Post-reload splitter for converting an SF or DFmode value in an
18602 SSE register into an unsigned SImode. */
18604 void
18606 {
18617 /* Load up the value into the low element. We must ensure that the other
18618 elements are valid floats -- zero is the easiest such value. */
18620 {
18623 else
18625 }
18626 else
18627 {
18632 else
18634 }
18654 else
18659 }
18661 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18662 Expects the 64-bit DImode to be supplied in a pair of integral
18663 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18664 -mfpmath=sse, !optimize_size only. */
18666 void
18668 {
18672 rtx x;
18678 {
18681 }
18682 else
18683 {
18687 }
18695 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18698 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18699 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18700 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18701 (0x1.0p84 + double(fp_value_hi_xmm)).
18702 Note these exponents differ by 32. */
18706 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18707 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18716 /* Add the upper and lower DFmode values together. */
18719 else
18720 {
18724 }
18727 }
18729 /* Not used, but eases macroization of patterns. */
18730 void
18732 rtx input ATTRIBUTE_UNUSED)
18733 {
18735 }
18737 /* Convert an unsigned SImode value into a DFmode. Only currently used
18738 for SSE, but applicable anywhere. */
18740 void
18742 {
18743 REAL_VALUE_TYPE TWO31r;
18758 }
18760 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18761 32-bit mode; otherwise we have a direct convert instruction. */
18763 void
18765 {
18766 REAL_VALUE_TYPE TWO32r;
18784 }
18786 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18787 For x86_32, -mfpmath=sse, !optimize_size only. */
18788 void
18790 {
18791 REAL_VALUE_TYPE ONE16r;
18810 }
18812 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18813 a vector of unsigned ints VAL to vector of floats TARGET. */
18815 void
18817 {
18819 REAL_VALUE_TYPE TWO16r;
18826 else
18831 OPTAB_DIRECT);
18842 OPTAB_DIRECT);
18844 OPTAB_DIRECT);
18847 }
18849 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18850 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18851 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18852 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18854 rtx
18856 {
18857 REAL_VALUE_TYPE TWO31r;
18872 {
18878 }
18887 OPTAB_DIRECT);
18888 else
18889 {
18895 OPTAB_DIRECT);
18896 }
18899 }
18901 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18902 then replicate the value for all elements of the vector
18903 register. */
18905 rtx
18907 {
18909 rtvec v;
18913 {
18946 }
18947 }
18949 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18950 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18951 for an SSE register. If VECT is true, then replicate the mask for
18952 all elements of the vector register. If INVERT is true, then create
18953 a mask excluding the sign bit. */
18955 rtx
18957 {
18961 rtx v;
18962 rtx mask;
18964 /* Find the sign bit, sign extended to 2*HWI. */
18966 {
18990 else
18998 {
19001 }
19002 else
19003 {
19004 rtvec vec;
19010 {
19013 }
19014 else
19024 }
19029 }
19034 /* Force this value into the low part of a fp vector constant. */
19043 }
19045 /* Generate code for floating point ABS or NEG. */
19047 void
19049 rtx operands[])
19050 {
19061 {
19067 }
19069 /* NEG and ABS performed with SSE use bitwise mask operations.
19070 Create the appropriate mask now. */
19073 else
19083 {
19085 rtvec par;
19090 else
19091 {
19094 }
19096 }
19097 else
19099 }
19101 /* Expand a copysign operation. Special case operand 0 being a constant. */
19103 void
19105 {
19119 else
19123 {
19130 {
19133 else
19134 {
19138 }
19139 }
19149 else
19153 }
19154 else
19155 {
19165 else
19169 }
19170 }
19172 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19173 be a constant, and so has already been expanded into a vector constant. */
19175 void
19177 {
19193 {
19196 }
19197 }
19199 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19200 so we have to do two masks. */
19202 void
19204 {
19219 {
19220 /* Shouldn't happen often (it's useless, obviously), but when it does
19221 we'd generate incorrect code if we continue below. */
19224 }
19227 {
19238 }
19239 else
19240 {
19242 {
19244 }
19246 {
19250 }
19254 {
19257 }
19259 {
19264 }
19266 }
19270 }
19272 /* Return TRUE or FALSE depending on whether the first SET in INSN
19273 has source and destination with matching CC modes, and that the
19274 CC mode is at least as constrained as REQ_MODE. */
19276 bool
19278 {
19279 rtx set;
19290 {
19300 /* FALLTHRU */
19304 /* FALLTHRU */
19308 /* FALLTHRU */
19322 }
19325 }
19327 /* Generate insn patterns to do an integer compare of OPERANDS. */
19329 static rtx
19331 {
19338 /* This is very simple, but making the interface the same as in the
19339 FP case makes the rest of the code easier. */
19343 /* Return the test that should be put into the flags user, i.e.
19344 the bcc, scc, or cmov instruction. */
19346 }
19348 /* Figure out whether to use ordered or unordered fp comparisons.
19349 Return the appropriate mode to use. */
19351 enum machine_mode
19353 {
19354 /* ??? In order to make all comparisons reversible, we do all comparisons
19355 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19356 all forms trapping and nontrapping comparisons, we can make inequality
19357 comparisons trapping again, since it results in better code when using
19358 FCOM based compares. */
19360 }
19362 enum machine_mode
19364 {
19368 {
19371 }
19374 {
19375 /* Only zero flag is needed. */
19379 /* Codes needing carry flag. */
19382 /* Detect overflow checks. They need just the carry flag. */
19386 else
19391 /* Codes possibly doable only with sign flag when
19392 comparing against zero. */
19397 else
19398 /* For other cases Carry flag is not required. */
19400 /* Codes doable only with sign flag when comparing
19401 against zero, but we miss jump instruction for it
19402 so we need to use relational tests against overflow
19403 that thus needs to be zero. */
19408 else
19410 /* strcmp pattern do (use flags) and combine may ask us for proper
19411 mode. */
19416 }
19417 }
19419 /* Return the fixed registers used for condition codes. */
19421 static bool
19423 {
19427 }
19429 /* If two condition code modes are compatible, return a condition code
19430 mode which is compatible with both. Otherwise, return
19431 VOIDmode. */
19433 static enum machine_mode
19435 {
19452 {
19466 {
19480 }
19484 /* These are only compatible with themselves, which we already
19485 checked above. */
19487 }
19488 }
19491 /* Return a comparison we can do and that it is equivalent to
19492 swap_condition (code) apart possibly from orderedness.
19493 But, never change orderedness if TARGET_IEEE_FP, returning
19494 UNKNOWN in that case if necessary. */
19496 static enum rtx_code
19498 {
19500 {
19511 }
19512 }
19514 /* Return cost of comparison CODE using the best strategy for performance.
19515 All following functions do use number of instructions as a cost metrics.
19516 In future this should be tweaked to compute bytes for optimize_size and
19517 take into account performance of various instructions on various CPUs. */
19519 static int
19521 {
19524 /* The cost of code using bit-twiddling on %ah. */
19526 {
19549 }
19552 {
19559 }
19560 }
19562 /* Return strategy to use for floating-point. We assume that fcomi is always
19563 preferrable where available, since that is also true when looking at size
19564 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19566 enum ix86_fpcmp_strategy
19568 {
19569 /* Do fcomi/sahf based test when profitable. */
19578 }
19580 /* Swap, force into registers, or otherwise massage the two operands
19581 to a fp comparison. The operands are updated in place; the new
19582 comparison code is returned. */
19584 static enum rtx_code
19586 {
19592 /* All of the unordered compare instructions only work on registers.
19593 The same is true of the fcomi compare instructions. The XFmode
19594 compare instructions require registers except when comparing
19595 against zero or when converting operand 1 from fixed point to
19596 floating point. */
19605 {
19608 }
19609 else
19610 {
19611 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19612 things around if they appear profitable, otherwise force op0
19613 into a register. */
19619 {
19622 {
19623 rtx tmp;
19626 }
19627 }
19633 {
19638 {
19641 }
19642 else
19644 }
19645 }
19647 /* Try to rearrange the comparison to make it cheaper. */
19651 {
19652 rtx tmp;
19657 }
19662 }
19664 /* Convert comparison codes we use to represent FP comparison to integer
19665 code that will result in proper branch. Return UNKNOWN if no such code
19666 is available. */
19668 enum rtx_code
19670 {
19672 {
19695 }
19696 }
19698 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19700 static rtx
19702 {
19709 /* Do fcomi/sahf based test when profitable. */
19711 {
19716 tmp);
19724 tmp);
19733 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19740 /* In the unordered case, we have to check C2 for NaN's, which
19741 doesn't happen to work out to anything nice combination-wise.
19742 So do some bit twiddling on the value we've got in AH to come
19743 up with an appropriate set of condition codes. */
19747 {
19751 {
19754 }
19755 else
19756 {
19762 }
19767 {
19772 }
19773 else
19774 {
19777 }
19782 {
19785 }
19786 else
19787 {
19791 }
19796 {
19802 }
19803 else
19804 {
19807 }
19812 {
19817 }
19818 else
19819 {
19822 }
19827 {
19832 }
19833 else
19834 {
19837 }
19851 }
19856 }
19858 /* Return the test that should be put into the flags user, i.e.
19859 the bcc, scc, or cmov instruction. */
19862 const0_rtx);
19863 }
19865 static rtx
19867 {
19868 rtx ret;
19874 {
19877 }
19878 else
19882 }
19884 void
19886 {
19888 rtx tmp;
19891 {
19898 simple:
19902 pc_rtx);
19910 /* Expand DImode branch into multiple compare+branch. */
19911 {
19917 {
19920 }
19927 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19928 avoid two branches. This costs one extra insn, so disable when
19929 optimizing for size. */
19934 {
19952 }
19954 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19955 op1 is a constant and the low word is zero, then we can just
19956 examine the high word. Similarly for low word -1 and
19957 less-or-equal-than or greater-than. */
19961 {
19964 {
19967 }
19971 {
19974 }
19978 }
19980 /* Otherwise, we need two or three jumps. */
19989 {
20003 }
20005 /*
20006 * a < b =>
20007 * if (hi(a) < hi(b)) goto true;
20008 * if (hi(a) > hi(b)) goto false;
20009 * if (lo(a) < lo(b)) goto true;
20010 * false:
20011 */
20023 }
20028 }
20029 }
20031 /* Split branch based on floating point condition. */
20032 void
20035 {
20036 rtx condition;
20037 rtx i;
20040 {
20045 }
20048 tmp);
20056 }
20058 void
20060 {
20061 rtx ret;
20068 }
20070 /* Expand comparison setting or clearing carry flag. Return true when
20071 successful and set pop for the operation. */
20072 static bool
20074 {
20078 /* Do not handle double-mode compares that go through special path. */
20083 {
20088 /* Shortcut: following common codes never translate
20089 into carry flag compares. */
20094 /* These comparisons require zero flag; swap operands so they won't. */
20097 {
20102 }
20104 /* Try to expand the comparison and verify that we end up with
20105 carry flag based comparison. This fails to be true only when
20106 we decide to expand comparison using arithmetic that is not
20107 too common scenario. */
20116 else
20125 }
20131 {
20136 /* Convert a==0 into (unsigned)a<1. */
20145 /* Convert a>b into b<a or a>=b-1. */
20149 {
20151 /* Bail out on overflow. We still can swap operands but that
20152 would force loading of the constant into register. */
20157 }
20158 else
20159 {
20164 }
20167 /* Convert a>=0 into (unsigned)a<0x80000000. */
20185 }
20186 /* Swapping operands may cause constant to appear as first operand. */
20188 {
20192 }
20196 }
20198 bool
20200 {
20224 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20225 HImode insns, we'd be swallowed in word prefix ops. */
20231 {
20235 HOST_WIDE_INT diff;
20238 /* Sign bit compares are better done using shifts than we do by using
20239 sbb. */
20242 {
20243 /* Detect overlap between destination and compare sources. */
20247 {
20248 rtx flags;
20257 {
20259 compare_code
20261 }
20263 /* To simplify rest of code, restrict to the GEU case. */
20265 {
20271 }
20272 else
20273 {
20276 reverse_condition_maybe_unordered
20278 else
20281 }
20290 else
20293 }
20294 else
20295 {
20298 else
20299 {
20304 }
20306 }
20309 {
20310 /*
20311 * cmpl op0,op1
20312 * sbbl dest,dest
20313 * [addl dest, ct]
20314 *
20315 * Size 5 - 8.
20316 */
20321 }
20323 {
20324 /*
20325 * cmpl op0,op1
20326 * sbbl dest,dest
20327 * orl $ct, dest
20328 *
20329 * Size 8.
20330 */
20334 }
20336 {
20337 /*
20338 * cmpl op0,op1
20339 * sbbl dest,dest
20340 * notl dest
20341 * [addl dest, cf]
20342 *
20343 * Size 8 - 11.
20344 */
20350 }
20351 else
20352 {
20353 /*
20354 * cmpl op0,op1
20355 * sbbl dest,dest
20356 * [notl dest]
20357 * andl cf - ct, dest
20358 * [addl dest, ct]
20359 *
20360 * Size 8 - 11.
20361 */
20364 {
20368 }
20378 }
20384 }
20387 {
20390 HOST_WIDE_INT tmp;
20395 {
20398 /* We may be reversing unordered compare to normal compare, that
20399 is not valid in general (we may convert non-trapping condition
20400 to trapping one), however on i386 we currently emit all
20401 comparisons unordered. */
20404 }
20405 else
20406 {
20409 }
20410 }
20415 {
20420 {
20425 }
20426 }
20428 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20432 {
20433 /* If lea code below could be used, only optimize
20434 if it results in a 2 insn sequence. */
20440 {
20441 /*
20442 * notl op1 (if necessary)
20443 * sarl $31, op1
20444 * orl cf, op1
20445 */
20447 {
20451 }
20462 }
20463 }
20471 {
20472 /*
20473 * xorl dest,dest
20474 * cmpl op1,op2
20475 * setcc dest
20476 * lea cf(dest*(ct-cf)),dest
20477 *
20478 * Size 14.
20479 *
20480 * This also catches the degenerate setcc-only case.
20481 */
20483 rtx tmp;
20489 /* On x86_64 the lea instruction operates on Pmode, so we need
20490 to get arithmetics done in proper mode to match. */
20493 else
20494 {
20495 rtx out1;
20498 nops++;
20500 {
20502 nops++;
20503 }
20504 }
20506 {
20508 nops++;
20509 }
20511 {
20514 else
20516 }
20521 }
20523 /*
20524 * General case: Jumpful:
20525 * xorl dest,dest cmpl op1, op2
20526 * cmpl op1, op2 movl ct, dest
20527 * setcc dest jcc 1f
20528 * decl dest movl cf, dest
20529 * andl (cf-ct),dest 1:
20530 * addl ct,dest
20531 *
20532 * Size 20. Size 14.
20533 *
20534 * This is reasonably steep, but branch mispredict costs are
20535 * high on modern cpus, so consider failing only if optimizing
20536 * for space.
20537 */
20542 {
20544 {
20551 {
20554 /* We may be reversing unordered compare to normal compare,
20555 that is not valid in general (we may convert non-trapping
20556 condition to trapping one), however on i386 we currently
20557 emit all comparisons unordered. */
20559 }
20560 else
20561 {
20565 }
20566 }
20569 {
20570 /* notl op1 (if needed)
20571 sarl $31, op1
20572 andl (cf-ct), op1
20573 addl ct, op1
20575 For x < 0 (resp. x <= -1) there will be no notl,
20576 so if possible swap the constants to get rid of the
20577 complement.
20578 True/false will be -1/0 while code below (store flag
20579 followed by decrement) is 0/-1, so the constants need
20580 to be exchanged once more. */
20583 {
20586 }
20587 else
20588 {
20592 }
20595 }
20596 else
20597 {
20601 constm1_rtx,
20603 }
20615 }
20616 }
20619 {
20620 /* Try a few things more with specific constants and a variable. */
20622 optab op;
20628 /* If one of the two operands is an interesting constant, load a
20629 constant with the above and mask it in with a logical operation. */
20632 {
20638 else
20640 }
20642 {
20648 else
20650 }
20651 else
20658 /* Recurse to get the constant loaded. */
20662 /* Mask in the interesting variable. */
20664 OPTAB_WIDEN);
20669 }
20671 /*
20672 * For comparison with above,
20673 *
20674 * movl cf,dest
20675 * movl ct,tmp
20676 * cmpl op1,op2
20677 * cmovcc tmp,dest
20678 *
20679 * Size 15.
20680 */
20702 }
20704 /* Swap, force into registers, or otherwise massage the two operands
20705 to an sse comparison with a mask result. Thus we differ a bit from
20706 ix86_prepare_fp_compare_args which expects to produce a flags result.
20708 The DEST operand exists to help determine whether to commute commutative
20709 operators. The POP0/POP1 operands are updated in place. The new
20710 comparison code is returned, or UNKNOWN if not implementable. */
20712 static enum rtx_code
20715 {
20716 rtx tmp;
20719 {
20722 /* AVX supports all the needed comparisons. */
20725 /* We have no LTGT as an operator. We could implement it with
20726 NE & ORDERED, but this requires an extra temporary. It's
20727 not clear that it's worth it. */
20734 /* These are supported directly. */
20741 /* AVX has 3 operand comparisons, no need to swap anything. */
20744 /* For commutative operators, try to canonicalize the destination
20745 operand to be first in the comparison - this helps reload to
20746 avoid extra moves. */
20749 /* FALLTHRU */
20755 /* These are not supported directly before AVX, and furthermore
20756 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20757 comparison operands to transform into something that is
20758 supported. */
20767 }
20770 }
20772 /* Detect conditional moves that exactly match min/max operational
20773 semantics. Note that this is IEEE safe, as long as we don't
20774 interchange the operands.
20776 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20777 and TRUE if the operation is successful and instructions are emitted. */
20779 static bool
20782 {
20785 rtx tmp;
20788 ;
20790 {
20794 }
20795 else
20802 else
20807 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20808 but MODE may be a vector mode and thus not appropriate. */
20810 {
20812 rtvec v;
20817 }
20818 else
20819 {
20822 }
20826 }
20828 /* Expand an sse vector comparison. Return the register with the result. */
20830 static rtx
20833 {
20837 /* In general case result of comparison can differ from operands' type. */
20840 /* In AVX512F the result of comparison is an integer mask. */
20842 rtx x;
20845 {
20850 }
20851 else
20864 /* Compare patterns for int modes are unspec in AVX512F only. */
20866 {
20870 {
20879 }
20882 {
20885 }
20886 }
20890 {
20893 }
20894 else
20898 }
20900 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20901 operations. This is used for both scalar and vector conditional moves. */
20903 static void
20905 {
20909 /* In AVX512F the result of comparison is an integer mask. */
20917 {
20919 }
20922 {
20926 }
20929 {
20934 }
20937 {
20941 }
20944 {
20952 op_true,
20953 op_false)));
20954 }
20955 else
20956 {
20966 {
20980 {
20987 }
21002 {
21009 }
21027 }
21030 {
21034 }
21035 else
21036 {
21042 else
21054 }
21055 }
21056 }
21058 /* Expand a floating-point conditional move. Return true if successful. */
21060 bool
21062 {
21070 {
21073 /* Since we've no cmove for sse registers, don't force bad register
21074 allocation just to gain access to it. Deny movcc when the
21075 comparison mode doesn't match the move mode. */
21094 }
21101 /* The floating point conditional move instructions don't directly
21102 support conditions resulting from a signed integer comparison. */
21106 {
21111 }
21118 }
21120 /* Expand a floating-point vector conditional move; a vcond operation
21121 rather than a movcc operation. */
21123 bool
21125 {
21127 rtx cmp;
21132 {
21133 rtx temp;
21135 {
21152 }
21154 OPTAB_DIRECT);
21157 }
21167 }
21169 /* Expand a signed/unsigned integral vector conditional move. */
21171 bool
21173 {
21183 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21184 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21193 {
21197 {
21203 }
21206 {
21212 }
21213 }
21222 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21226 ;
21227 else
21228 {
21229 /* Canonicalize the comparison to EQ, GT, GTU. */
21231 {
21248 /* FALLTHRU */
21258 }
21260 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21262 {
21264 {
21266 /* SSE4.1 supports EQ. */
21273 /* SSE4.2 supports GT/GTU. */
21280 }
21281 }
21283 /* Unsigned parallel compare is not supported by the hardware.
21284 Play some tricks to turn this into a signed comparison
21285 against 0. */
21287 {
21291 {
21298 {
21303 {
21312 }
21313 /* Subtract (-(INT MAX) - 1) from both operands to make
21314 them signed. */
21325 }
21332 /* Perform a parallel unsigned saturating subtraction. */
21345 }
21346 }
21347 }
21349 /* Allow the comparison to be done in one mode, but the movcc to
21350 happen in another mode. */
21352 {
21355 }
21356 else
21357 {
21363 }
21368 }
21370 static bool
21372 {
21375 {
21379 op1));
21384 op1));
21396 }
21397 }
21399 /* Expand a variable vector permutation. */
21401 void
21403 {
21414 /* Number of elements in the vector. */
21423 {
21425 {
21426 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21427 an constant shuffle operand. With a tiny bit of effort we can
21428 use VPERMD instead. A re-interpretation stall for V4DFmode is
21429 unfortunate but there's no avoiding it.
21430 Similarly for V16HImode we don't have instructions for variable
21431 shuffling, while for V32QImode we can use after preparing suitable
21432 masks vpshufb; vpshufb; vpermq; vpor. */
21435 {
21439 }
21440 else
21441 {
21445 }
21448 /* Replicate the low bits of the V4DImode mask into V8SImode:
21449 mask = { A B C D }
21450 t1 = { A A B B C C D D }. */
21458 else
21461 /* Multiply the shuffle indicies by two. */
21463 OPTAB_DIRECT);
21465 /* Add one to the odd shuffle indicies:
21466 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21468 {
21471 }
21475 OPTAB_DIRECT);
21477 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21482 }
21485 {
21487 /* The VPERMD and VPERMPS instructions already properly ignore
21488 the high bits of the shuffle elements. No need for us to
21489 perform an AND ourselves. */
21491 {
21496 }
21497 else
21498 {
21504 }
21511 else
21512 {
21518 }
21522 /* By combining the two 128-bit input vectors into one 256-bit
21523 input vector, we can use VPERMD and VPERMPS for the full
21524 two-operand shuffle. */
21556 /* From mask create two adjusted masks, which contain the same
21557 bits as mask in the low 7 bits of each vector element.
21558 The first mask will have the most significant bit clear
21559 if it requests element from the same 128-bit lane
21560 and MSB set if it requests element from the other 128-bit lane.
21561 The second mask will have the opposite values of the MSB,
21562 and additionally will have its 128-bit lanes swapped.
21563 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21564 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21565 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21566 stands for other 12 bytes. */
21567 /* The bit whether element is from the same lane or the other
21568 lane is bit 4, so shift it up by 3 to the MSB position. */
21572 /* Clear MSB bits from the mask just in case it had them set. */
21574 /* After this t1 will have MSB set for elements from other lane. */
21576 /* Clear bits other than MSB. */
21578 /* Or in the lower bits from mask into t3. */
21580 /* And invert MSB bits in t1, so MSB is set for elements from the same
21581 lane. */
21583 /* Swap 128-bit lanes in t3. */
21588 /* And or in the lower bits from mask into t1. */
21591 {
21592 /* Each of these shuffles will put 0s in places where
21593 element from the other 128-bit lane is needed, otherwise
21594 will shuffle in the requested value. */
21598 /* For t3 the 128-bit lanes are swapped again. */
21603 /* And oring both together leads to the result. */
21610 }
21613 /* Similarly to the above one_operand_shuffle code,
21614 just for repeated twice for each operand. merge_two:
21615 code will merge the two results together. */
21639 }
21640 }
21643 {
21644 /* The XOP VPPERM insn supports three inputs. By ignoring the
21645 one_operand_shuffle special case, we avoid creating another
21646 set of constant vectors in memory. */
21649 /* mask = mask & {2*w-1, ...} */
21651 }
21652 else
21653 {
21654 /* mask = mask & {w-1, ...} */
21656 }
21664 /* For non-QImode operations, convert the word permutation control
21665 into a byte permutation control. */
21667 {
21672 /* Convert mask to vector of chars. */
21675 /* Replicate each of the input bytes into byte positions:
21676 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21677 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21678 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21685 else
21688 /* Convert it into the byte positions by doing
21689 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21695 }
21697 /* The actual shuffle operations all operate on V16QImode. */
21702 {
21709 }
21711 {
21718 }
21719 else
21720 {
21724 /* Shuffle the two input vectors independently. */
21730 merge_two:
21731 /* Then merge them together. The key is whether any given control
21732 element contained a bit set that indicates the second word. */
21736 {
21737 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21738 more shuffle to convert the V2DI input mask into a V4SI
21739 input mask. At which point the masking that expand_int_vcond
21740 will work as desired. */
21748 }
21770 }
21771 }
21773 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21774 true if we should do zero extension, else sign extension. HIGH_P is
21775 true if we want the N/2 high elements, else the low elements. */
21777 void
21779 {
21781 rtx tmp;
21784 {
21790 {
21794 else
21797 extract
21803 else
21806 extract
21812 else
21815 extract
21821 else
21824 extract
21830 else
21833 extract
21839 else
21845 else
21851 else
21856 }
21859 {
21862 }
21864 {
21865 /* Shift higher 8 bytes to lower 8 bytes. */
21870 }
21871 else
21875 }
21876 else
21877 {
21881 {
21885 else
21891 else
21897 else
21902 }
21906 else
21913 }
21914 }
21916 /* Expand conditional increment or decrement using adb/sbb instructions.
21917 The default case using setcc followed by the conditional move can be
21918 done by generic code. */
21919 bool
21921 {
21923 rtx flags;
21925 rtx compare_op;
21943 {
21946 }
21949 {
21953 reverse_condition_maybe_unordered
21955 else
21957 }
21961 /* Construct either adc or sbb insn. */
21963 {
21965 {
21980 }
21981 }
21982 else
21983 {
21985 {
22000 }
22001 }
22005 }
22008 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22009 but works for floating pointer parameters and nonoffsetable memories.
22010 For pushes, it returns just stack offsets; the values will be saved
22011 in the right order. Maximally three parts are generated. */
22013 static int
22015 {
22020 else
22026 /* Optimize constant pool reference to immediates. This is used by fp
22027 moves, that force all constants to memory to allow combining. */
22029 {
22033 }
22036 {
22037 /* The only non-offsetable memories we handle are pushes. */
22046 }
22049 {
22051 /* Caution: if we looked through a constant pool memory above,
22052 the operand may actually have a different mode now. That's
22053 ok, since we want to pun this all the way back to an integer. */
22057 }
22060 {
22063 else
22064 {
22068 {
22072 }
22074 {
22079 }
22081 {
22082 REAL_VALUE_TYPE r;
22087 {
22094 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22095 long double may not be 80-bit. */
22104 }
22107 }
22108 else
22110 }
22111 }
22112 else
22113 {
22117 {
22120 {
22124 }
22126 {
22130 }
22132 {
22133 REAL_VALUE_TYPE r;
22139 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22142 = gen_int_mode
22145 DImode);
22146 else
22153 = gen_int_mode
22156 DImode);
22157 else
22159 }
22160 else
22162 }
22163 }
22166 }
22168 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22169 Return false when normal moves are needed; true when all required
22170 insns have been emitted. Operands 2-4 contain the input values
22171 int the correct order; operands 5-7 contain the output values. */
22173 void
22175 {
22183 /* The DFmode expanders may ask us to move double.
22184 For 64bit target this is single move. By hiding the fact
22185 here we simplify i386.md splitters. */
22187 {
22188 /* Optimize constant pool reference to immediates. This is used by
22189 fp moves, that force all constants to memory to allow combining. */
22196 {
22199 }
22200 else
22205 }
22207 /* The only non-offsettable memory we handle is push. */
22210 else
22217 /* When emitting push, take care for source operands on the stack. */
22220 {
22223 /* Compensate for the stack decrement by 4. */
22228 /* src_base refers to the stack pointer and is
22229 automatically decreased by emitted push. */
22233 }
22235 /* We need to do copy in the right order in case an address register
22236 of the source overlaps the destination. */
22238 {
22239 rtx tmp;
22242 {
22246 collisions++;
22247 }
22249 /* Collision in the middle part can be handled by reordering. */
22251 {
22254 }
22258 {
22260 {
22263 }
22264 else
22265 {
22268 }
22269 }
22271 /* If there are more collisions, we can't handle it by reordering.
22272 Do an lea to the last part and use only one colliding move. */
22274 {
22281 /* Handle the case when the last part isn't valid for lea.
22282 Happens in 64-bit mode storing the 12-byte XFmode. */
22288 {
22293 {
22294 /* It is not valid to use %gs: or %fs: in
22295 lea though, so we need to remove it from the
22296 address used for lea and add it to each individual
22297 memory loads instead. */
22301 {
22303 {
22309 {
22313 }
22314 }
22318 }
22320 }
22321 }
22327 {
22332 }
22333 }
22334 }
22337 {
22339 {
22341 {
22346 }
22348 {
22351 }
22352 }
22353 else
22354 {
22355 /* In 64bit mode we don't have 32bit push available. In case this is
22356 register, it is OK - we will just use larger counterpart. We also
22357 retype memory - these comes from attempt to avoid REX prefix on
22358 moving of second half of TFmode value. */
22360 {
22362 {
22373 }
22377 }
22378 }
22382 }
22384 /* Choose correct order to not overwrite the source before it is copied. */
22394 {
22396 {
22399 }
22400 }
22401 else
22402 {
22404 {
22407 }
22408 }
22410 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22412 {
22421 }
22427 }
22429 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22430 left shift by a constant, either using a single shift or
22431 a sequence of add instructions. */
22433 static void
22435 {
22441 {
22445 }
22446 else
22447 {
22450 }
22451 }
22453 void
22455 {
22464 {
22469 {
22475 }
22476 else
22477 {
22485 }
22487 }
22494 {
22495 /* Assuming we've chosen a QImode capable registers, then 1 << N
22496 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22498 {
22514 }
22516 /* Otherwise, we can get the same results by manually performing
22517 a bit extract operation on bit 5/6, and then performing the two
22518 shifts. The two methods of getting 0/1 into low/high are exactly
22519 the same size. Avoiding the shift in the bit extract case helps
22520 pentium4 a bit; no one else seems to care much either way. */
22521 else
22522 {
22527 HOST_WIDE_INT bits;
22528 rtx x;
22531 {
22537 }
22538 else
22539 {
22545 }
22549 else
22557 }
22562 }
22565 {
22566 /* For -1 << N, we can avoid the shld instruction, because we
22567 know that we're shifting 0...31/63 ones into a -1. */
22571 else
22573 }
22574 else
22575 {
22583 }
22588 {
22594 }
22595 else
22596 {
22601 }
22602 }
22604 void
22606 {
22616 {
22621 {
22627 }
22629 {
22638 }
22639 else
22640 {
22648 }
22649 }
22650 else
22651 {
22663 {
22671 scratch));
22672 }
22673 else
22674 {
22679 }
22680 }
22681 }
22683 void
22685 {
22695 {
22700 {
22707 }
22708 else
22709 {
22717 }
22718 }
22719 else
22720 {
22732 {
22738 scratch));
22739 }
22740 else
22741 {
22746 }
22747 }
22748 }
22750 /* Predict just emitted jump instruction to be taken with probability PROB. */
22751 static void
22753 {
22757 }
22759 /* Helper function for the string operations below. Dest VARIABLE whether
22760 it is aligned to VALUE bytes. If true, jump to the label. */
22761 static rtx
22763 {
22768 else
22774 else
22777 }
22779 /* Adjust COUNTER by the VALUE. */
22780 static void
22782 {
22787 }
22789 /* Zero extend possibly SImode EXP to Pmode register. */
22790 rtx
22792 {
22794 }
22796 /* Divide COUNTREG by SCALE. */
22797 static rtx
22799 {
22800 rtx sc;
22812 }
22814 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22815 DImode for constant loop counts. */
22817 static enum machine_mode
22819 {
22827 }
22829 /* Copy the address to a Pmode register. This is used for x32 to
22830 truncate DImode TLS address to a SImode register. */
22832 static rtx
22834 {
22835 rtx reg;
22837 {
22841 }
22842 else
22843 {
22848 }
22849 }
22851 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22852 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22853 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22854 memory by VALUE (supposed to be in MODE).
22856 The size is rounded down to whole number of chunk size moved at once.
22857 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22860 static void
22865 {
22871 rtx size;
22880 /* Those two should combine. */
22882 {
22886 }
22893 /* This assert could be relaxed - in this case we'll need to compute
22894 smallest power of two, containing in PIECE_SIZE_N and pass it to
22895 offset_address. */
22901 {
22905 /* When unrolling for chips that reorder memory reads and writes,
22906 we can save registers by using single temporary.
22907 Also using 4 temporaries is overkill in 32bit mode. */
22909 {
22911 {
22913 {
22914 destmem =
22916 srcmem =
22918 }
22920 }
22921 }
22922 else
22923 {
22927 {
22930 {
22931 srcmem =
22933 }
22935 }
22937 {
22939 {
22940 destmem =
22942 }
22944 }
22945 }
22946 }
22947 else
22949 {
22951 destmem =
22954 }
22964 {
22970 else
22972 }
22973 else
22981 {
22986 }
22988 }
22990 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22991 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22992 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22993 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22994 ORIG_VALUE is the original value passed to memset to fill the memory with.
22995 Other arguments have same meaning as for previous function. */
22997 static void
23000 rtx count,
23002 {
23003 rtx destexp;
23004 rtx srcexp;
23005 rtx countreg;
23006 HOST_WIDE_INT rounded_count;
23008 /* If possible, it is shorter to use rep movs.
23009 TODO: Maybe it is better to move this logic to decide_alg. */
23020 {
23024 }
23025 else
23028 {
23033 }
23038 {
23041 }
23042 else
23043 {
23047 {
23051 }
23052 else
23055 {
23060 }
23061 else
23062 {
23065 }
23068 }
23069 }
23071 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23072 DESTMEM.
23073 SRC is passed by pointer to be updated on return.
23074 Return value is updated DST. */
23075 static rtx
23077 HOST_WIDE_INT size_to_move)
23078 {
23084 /* Find the widest mode in which we could perform moves.
23085 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23086 it until move of such size is supported. */
23091 {
23095 }
23097 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23098 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23100 {
23105 {
23109 }
23110 }
23116 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23120 {
23121 /* We move from memory to memory, so we'll need to do it via
23122 a temporary register. */
23133 piece_size);
23135 piece_size);
23136 }
23138 /* Update DST and SRC rtx. */
23141 }
23143 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23144 static void
23147 {
23150 {
23155 /* For now MAX_SIZE should be a power of 2. This assert could be
23156 relaxed, but it'll require a bit more complicated epilogue
23157 expanding. */
23160 {
23163 }
23165 }
23167 {
23173 }
23175 /* When there are stringops, we can cheaply increase dest and src pointers.
23176 Otherwise we save code size by maintaining offset (zero is readily
23177 available from preceding rep operation) and using x86 addressing modes.
23178 */
23180 {
23182 {
23189 }
23191 {
23198 }
23200 {
23207 }
23208 }
23209 else
23210 {
23212 rtx tmp;
23215 {
23226 }
23228 {
23241 }
23243 {
23252 }
23253 }
23254 }
23256 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23257 with value PROMOTED_VAL.
23258 SRC is passed by pointer to be updated on return.
23259 Return value is updated DST. */
23260 static rtx
23262 HOST_WIDE_INT size_to_move)
23263 {
23269 /* Find the widest mode in which we could perform moves.
23270 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23271 it until move of such size is supported. */
23276 {
23279 }
23286 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23290 {
23292 {
23295 piece_size);
23297 }
23305 piece_size);
23306 }
23308 /* Update DST rtx. */
23310 }
23311 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23312 static void
23315 {
23316 count =
23322 }
23324 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23325 static void
23328 {
23329 rtx dest;
23332 {
23337 /* For now MAX_SIZE should be a power of 2. This assert could be
23338 relaxed, but it'll require a bit more complicated epilogue
23339 expanding. */
23342 {
23344 {
23347 else
23349 }
23350 }
23352 }
23354 {
23357 }
23359 {
23362 {
23367 }
23368 else
23369 {
23378 }
23381 }
23383 {
23386 {
23389 }
23390 else
23391 {
23396 }
23399 }
23401 {
23407 }
23409 {
23415 }
23417 {
23423 }
23424 }
23426 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23427 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23428 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23429 ignored.
23430 Return value is updated DESTMEM. */
23431 static rtx
23436 {
23439 {
23441 {
23444 {
23447 else
23449 }
23450 else
23456 }
23457 }
23459 }
23461 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23462 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23463 and jump to DONE_LABEL. */
23464 static void
23470 {
23473 rtx modesize;
23476 /* If we do not have vector value to copy, we must reduce size. */
23478 {
23480 {
23485 }
23486 else
23488 }
23489 else
23490 {
23491 /* Choose appropriate vector mode. */
23497 }
23502 {
23505 else
23506 {
23509 }
23511 }
23517 {
23521 }
23523 {
23526 else
23527 {
23530 }
23532 }
23538 }
23540 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23541 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23542 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23543 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23544 DONE_LABEL is a label after the whole copying sequence. The label is created
23545 on demand if *DONE_LABEL is NULL.
23546 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23547 bounds after the initial copies.
23549 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23550 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23551 we will dispatch to a library call for large blocks.
23553 In pseudocode we do:
23555 if (COUNT < SIZE)
23556 {
23557 Assume that SIZE is 4. Bigger sizes are handled analogously
23558 if (COUNT & 4)
23559 {
23560 copy 4 bytes from SRCPTR to DESTPTR
23561 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23562 goto done_label
23563 }
23564 if (!COUNT)
23565 goto done_label;
23566 copy 1 byte from SRCPTR to DESTPTR
23567 if (COUNT & 2)
23568 {
23569 copy 2 bytes from SRCPTR to DESTPTR
23570 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23571 }
23572 }
23573 else
23574 {
23575 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23576 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23578 OLD_DESPTR = DESTPTR;
23579 Align DESTPTR up to DESIRED_ALIGN
23580 SRCPTR += DESTPTR - OLD_DESTPTR
23581 COUNT -= DEST_PTR - OLD_DESTPTR
23582 if (DYNAMIC_CHECK)
23583 Round COUNT down to multiple of SIZE
23584 << optional caller supplied zero size guard is here >>
23585 << optional caller suppplied dynamic check is here >>
23586 << caller supplied main copy loop is here >>
23587 }
23588 done_label:
23589 */
23590 static void
23603 {
23606 rtx modesize;
23608 rtx mode_value;
23610 /* Chose proper value to copy. */
23613 else
23617 /* See if block is big or small, handle small blocks. */
23619 {
23630 /* Handle sizes > 3. */
23637 /* Nothing to copy? Jump to DONE_LABEL if so */
23641 /* Do a byte copy. */
23645 else
23646 {
23649 }
23651 /* Handle sizes 2 and 3. */
23658 else
23659 {
23664 }
23670 }
23671 else
23675 /* Start memcpy for COUNT >= SIZE. */
23677 {
23680 }
23682 /* Copy first desired_align bytes. */
23688 {
23691 else
23692 {
23695 }
23698 }
23701 /* Copy last SIZE bytes. */
23708 else
23709 {
23715 }
23717 {
23721 else
23722 {
23725 }
23726 }
23728 /* Align destination. */
23730 {
23734 /* Align destptr up, place it to new register. */
23743 /* See how many bytes we skipped. */
23747 /* Adjust srcptr and count. */
23753 /* We copied at most size + prolog_size. */
23756 else
23759 /* Our loops always round down the bock size, but for dispatch to library
23760 we need precise value. */
23764 }
23765 else
23766 {
23768 /* Decrease count, so we won't end up copying last word twice. */
23772 else
23776 }
23777 }
23780 /* This function is like the previous one, except here we know how many bytes
23781 need to be copied. That allows us to update alignment not only of DST, which
23782 is returned, but also of SRC, which is passed as a pointer for that
23783 reason. */
23784 static rtx
23789 {
23797 {
23801 }
23806 {
23808 {
23810 {
23813 else
23815 }
23816 else
23819 }
23820 }
23827 {
23833 {
23836 {
23840 }
23845 }
23849 }
23852 }
23854 /* Return true if ALG can be used in current context.
23855 Assume we expand memset if MEMSET is true. */
23856 static bool
23858 {
23863 /* Algorithms using the rep prefix want at least edi and ecx;
23864 additionally, memset wants eax and memcpy wants esi. Don't
23865 consider such algorithms if the user has appropriated those
23866 registers for their own purposes. */
23873 }
23875 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23876 static enum stringop_alg
23880 {
23891 /* Even if the string operation call is cold, we still might spend a lot
23892 of time processing large blocks. */
23898 else
23904 else
23907 /* See maximal size for user defined algorithm. */
23909 {
23916 }
23918 /* If expected size is not known but max size is small enough
23919 so inline version is a win, set expected size into
23920 the range. */
23925 /* If user specified the algorithm, honnor it if possible. */
23929 /* rep; movq or rep; movl is the smallest variant. */
23931 {
23936 else
23939 }
23940 /* Very tiny blocks are best handled via the loop, REP is expensive to
23941 setup. */
23945 {
23949 {
23950 /* We get here if the algorithms that were not libcall-based
23951 were rep-prefix based and we are unable to use rep prefixes
23952 based on global register usage. Break out of the loop and
23953 use the heuristic below. */
23957 {
23961 {
23964 }
23965 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23966 last non-libcall inline algorithm. */
23968 {
23969 /* When the current size is best to be copied by a libcall,
23970 but we are still forced to inline, run the heuristic below
23971 that will pick code for medium sized blocks. */
23973 {
23976 }
23979 }
23981 {
23984 }
23985 }
23986 }
23987 }
23988 /* When asked to inline the call anyway, try to pick meaningful choice.
23989 We look for maximal size of block that is faster to copy by hand and
23990 take blocks of at most of that size guessing that average size will
23991 be roughly half of the block.
23993 If this turns out to be bad, we might simply specify the preferred
23994 choice in ix86_costs. */
23998 {
24001 /* If there aren't any usable algorithms, then recursing on
24002 smaller sizes isn't going to find anything. Just return the
24003 simple byte-at-a-time copy loop. */
24005 {
24006 /* Pick something reasonable. */
24010 }
24018 else
24021 }
24024 }
24026 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24027 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24028 static int
24033 {
24044 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24045 copying whole cacheline at once. */
24058 }
24061 /* Helper function for memcpy. For QImode value 0xXY produce
24062 0xXYXYXYXY of wide specified by MODE. This is essentially
24063 a * 0x10101010, but we can do slightly better than
24064 synth_mult by unwinding the sequence by hand on CPUs with
24065 slow multiply. */
24066 static rtx
24068 {
24070 rtx tmp;
24077 {
24085 }
24094 nops--;
24099 {
24103 OPTAB_DIRECT);
24104 }
24105 else
24106 {
24112 else
24114 else
24115 {
24118 reg =
24120 }
24130 }
24131 }
24133 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24134 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24135 alignment from ALIGN to DESIRED_ALIGN. */
24136 static rtx
24139 {
24140 rtx promoted_val;
24149 else
24153 }
24155 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24156 operations when profitable. The code depends upon architecture, block size
24157 and alignment, but always has one of the following overall structures:
24159 Aligned move sequence:
24161 1) Prologue guard: Conditional that jumps up to epilogues for small
24162 blocks that can be handled by epilogue alone. This is faster
24163 but also needed for correctness, since prologue assume the block
24164 is larger than the desired alignment.
24166 Optional dynamic check for size and libcall for large
24167 blocks is emitted here too, with -minline-stringops-dynamically.
24169 2) Prologue: copy first few bytes in order to get destination
24170 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24171 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24172 copied. We emit either a jump tree on power of two sized
24173 blocks, or a byte loop.
24175 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24176 with specified algorithm.
24178 4) Epilogue: code copying tail of the block that is too small to be
24179 handled by main body (or up to size guarded by prologue guard).
24181 Misaligned move sequence
24183 1) missaligned move prologue/epilogue containing:
24184 a) Prologue handling small memory blocks and jumping to done_label
24185 (skipped if blocks are known to be large enough)
24186 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24187 needed by single possibly misaligned move
24188 (skipped if alignment is not needed)
24189 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24191 2) Zero size guard dispatching to done_label, if needed
24193 3) dispatch to library call, if needed,
24195 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24196 with specified algorithm. */
24197 bool
24203 {
24204 rtx destreg;
24207 rtx tmp;
24223 /* TODO: Once value ranges are available, fill in proper data. */
24231 /* i386 can do misaligned access on reasonably increased cost. */
24235 /* ALIGN is the minimum of destination and source alignment, but we care here
24236 just about destination alignment. */
24242 {
24245 /* When COUNT is 0, there is nothing to do. */
24248 }
24249 else
24250 {
24259 }
24261 /* Make sure we don't need to care about overflow later on. */
24265 /* Step 0: Decide on preferred algorithm, desired alignment and
24266 size of chunks to be copied by main loop. */
24268 issetmem,
24275 /* For now vector-version of memset is generated only for memory zeroing, as
24276 creating of promoted vector value is very cheap in this case. */
24289 {
24308 /* Find the widest supported mode. */
24314 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24315 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24317 {
24322 }
24334 }
24342 /* Step 1: Prologue guard. */
24344 /* Alignment code needs count to be in register. */
24346 {
24349 {
24350 align_bytes
24354 else
24356 }
24359 }
24362 /* Misaligned move sequences handle both prologue and epilogue at once.
24363 Default code generation results in a smaller code for large alignments
24364 and also avoids redundant job when sizes are known precisely. */
24365 misaligned_prologue_used
24366 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24372 /* Do the cheap promotion to allow better CSE across the
24373 main loop and epilogue (ie one load of the big constant in the
24374 front of all code.
24375 For now the misaligned move sequences do not have fast path
24376 without broadcasting. */
24378 {
24380 {
24386 }
24387 else
24388 {
24391 }
24392 }
24393 /* Misaligned move sequences handles both prologues and epilogues at once.
24394 Default code generation results in smaller code for large alignments and
24395 also avoids redundant job when sizes are known precisely. */
24397 {
24398 /* Misaligned move prologue handled small blocks by itself. */
24399 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24404 desired_align < align
24413 {
24414 /* It is possible that we copied enough so the main loop will not
24415 execute. */
24425 else
24427 }
24428 }
24429 /* Ensure that alignment prologue won't copy past end of block. */
24431 {
24433 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24434 Make sure it is power of 2. */
24437 /* To improve performance of small blocks, we jump around the VAL
24438 promoting mode. This mean that if the promoted VAL is not constant,
24439 we might not use it in the epilogue and have to use byte
24440 loop variant. */
24445 {
24446 /* If main algorithm works on QImode, no epilogue is needed.
24447 For small sizes just don't align anything. */
24450 else
24452 }
24455 {
24462 else
24464 }
24465 }
24467 /* Emit code to decide on runtime whether library call or inline should be
24468 used. */
24470 {
24472 {
24474 {
24478 }
24479 }
24480 else
24481 {
24491 else
24495 }
24496 }
24498 /* Step 2: Alignment prologue. */
24499 /* Do the expensive promotion once we branched off the small blocks. */
24505 {
24507 {
24508 /* Except for the first move in prologue, we no longer know
24509 constant offset in aliasing info. It don't seems to worth
24510 the pain to maintain it for the first move, so throw away
24511 the info early. */
24518 issetmem);
24519 /* At most desired_align - align bytes are copied. */
24522 else
24524 }
24525 else
24526 {
24527 /* If we know how many bytes need to be stored before dst is
24528 sufficiently aligned, maintain aliasing info accurately. */
24530 srcreg,
24531 promoted_val,
24532 vec_promoted_val,
24533 desired_align,
24534 align_bytes,
24535 issetmem);
24542 }
24544 && !min_size
24549 {
24550 /* It is possible that we copied enough so the main loop will not
24551 execute. */
24561 else
24563 }
24564 }
24566 {
24573 }
24577 /* Step 3: Main loop. */
24580 {
24603 }
24604 /* Adjust properly the offset of src and dest memory for aliasing. */
24606 {
24612 }
24613 else
24614 {
24618 }
24620 /* Step 4: Epilogue to copy the remaining bytes. */
24621 epilogue:
24623 {
24624 /* When the main loop is done, COUNT_EXP might hold original count,
24625 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24626 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24627 bytes. Compensate if needed. */
24630 {
24631 tmp =
24634 OPTAB_DIRECT);
24637 }
24640 }
24643 {
24646 epilogue_size_needed);
24647 else
24648 {
24652 epilogue_size_needed);
24653 else
24655 epilogue_size_needed);
24656 }
24657 }
24661 }
24664 /* Expand the appropriate insns for doing strlen if not just doing
24665 repnz; scasb
24667 out = result, initialized with the start address
24668 align_rtx = alignment of the address.
24669 scratch = scratch register, initialized with the startaddress when
24670 not aligned, otherwise undefined
24672 This is just the body. It needs the initializations mentioned above and
24673 some address computing at the end. These things are done in i386.md. */
24675 static void
24677 {
24679 rtx tmp;
24684 rtx mem;
24687 rtx cmp;
24693 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24695 /* Is there a known alignment and is it less than 4? */
24697 {
24700 /* Is there a known alignment and is it not 2? */
24702 {
24706 /* Leave just the 3 lower bits. */
24716 }
24717 else
24718 {
24719 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24720 check if is aligned to 4 - byte. */
24727 }
24731 /* Now compare the bytes. */
24733 /* Compare the first n unaligned byte on a byte per byte basis. */
24737 /* Increment the address. */
24740 /* Not needed with an alignment of 2 */
24742 {
24746 end_0_label);
24751 }
24754 end_0_label);
24757 }
24759 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24760 align this loop. It gives only huge programs, but does not help to
24761 speed up. */
24768 /* This formula yields a nonzero result iff one of the bytes is zero.
24769 This saves three branches inside loop and many cycles. */
24777 align_4_label);
24780 {
24786 /* If zero is not in the first two bytes, move two bytes forward. */
24792 reg,
24793 tmpreg)));
24794 /* Emit lea manually to avoid clobbering of flags. */
24802 reg2,
24803 out)));
24804 }
24805 else
24806 {
24808 /* Is zero in the first two bytes? */
24815 pc_rtx);
24819 /* Not in the first two. Move two bytes forward. */
24825 }
24827 /* Avoid branch in fixing the byte. */
24835 }
24837 /* Expand strlen. */
24839 bool
24841 {
24844 /* The generic case of strlen expander is long. Avoid it's
24845 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24848 && !TARGET_INLINE_ALL_STRINGOPS
24858 {
24859 /* Well it seems that some optimizer does not combine a call like
24860 foo(strlen(bar), strlen(bar));
24861 when the move and the subtraction is done here. It does calculate
24862 the length just once when these instructions are done inside of
24863 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24864 often used and I use one fewer register for the lifetime of
24865 output_strlen_unroll() this is better. */
24871 /* strlensi_unroll_1 returns the address of the zero at the end of
24872 the string, like memchr(), so compute the length by subtracting
24873 the start address. */
24875 }
24876 else
24877 {
24878 rtx unspec;
24880 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24893 /* If .md starts supporting :P, this can be done in .md. */
24899 }
24901 }
24903 /* For given symbol (function) construct code to compute address of it's PLT
24904 entry in large x86-64 PIC model. */
24905 static rtx
24907 {
24920 }
24922 rtx
24924 rtx callarg2,
24926 {
24927 unsigned int const cregs_size
24938 {
24939 #if TARGET_MACHO
24942 #endif
24943 }
24944 else
24945 {
24946 /* Static functions and indirect calls don't need the pic register. */
24948 && (!TARGET_64BIT
24954 }
24957 {
24961 }
24964 && !TARGET_PECOFF
24972 {
24975 }
24983 {
24987 }
24991 {
24995 UNSPEC_MS_TO_SYSV_CALL);
24998 {
25004 }
25005 }
25014 }
25016 /* Output the assembly for a call instruction. */
25020 {
25026 {
25029 /* SEH epilogue detection requires the indirect branch case
25030 to include REX.W. */
25033 else
25038 }
25040 /* SEH unwinding can require an extra nop to be emitted in several
25041 circumstances. Determine if we have one of those. */
25043 {
25044 rtx i;
25047 {
25048 /* If we get to another real insn, we don't need the nop. */
25052 /* If we get to the epilogue note, prevent a catch region from
25053 being adjacent to the standard epilogue sequence. If non-
25054 call-exceptions, we'll have done this during epilogue emission. */
25056 && !flag_non_call_exceptions
25058 {
25061 }
25062 }
25064 /* If we didn't find a real insn following the call, prevent the
25065 unwinder from looking into the next function. */
25068 }
25072 else
25081 }
25082 \f
25083 /* Clear stack slot assignments remembered from previous functions.
25084 This is called from INIT_EXPANDERS once before RTL is emitted for each
25085 function. */
25089 {
25097 }
25099 /* Return a MEM corresponding to a stack slot with mode MODE.
25100 Allocate a new slot if necessary.
25102 The RTL for a function can have several slots available: N is
25103 which slot to use. */
25105 rtx
25107 {
25124 }
25126 static void
25128 {
25134 }
25135 \f
25136 /* Check whether x86 address PARTS is a pc-relative address. */
25138 static bool
25140 {
25148 {
25150 {
25167 }
25168 }
25170 }
25172 /* Calculate the length of the memory address in the instruction encoding.
25173 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25174 or other prefixes. We never generate addr32 prefix for LEA insn. */
25176 int
25178 {
25195 /* If this is not LEA instruction, add the length of addr32 prefix. */
25200 len++;
25214 /* Rule of thumb:
25215 - esp as the base always wants an index,
25216 - ebp as the base always wants a displacement,
25217 - r12 as the base always wants an index,
25218 - r13 as the base always wants a displacement. */
25220 /* Register Indirect. */
25222 {
25223 /* esp (for its index) and ebp (for its displacement) need
25224 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25225 code. */
25232 len++;
25233 }
25235 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25236 is not disp32, but disp32(%rip), so for disp32
25237 SIB byte is needed, unless print_operand_address
25238 optimizes it into disp32(%rip) or (%rip) is implied
25239 by UNSPEC. */
25241 {
25244 len++;
25245 }
25246 else
25247 {
25248 /* Find the length of the displacement constant. */
25250 {
25253 else
25255 }
25256 /* ebp always wants a displacement. Similarly r13. */
25258 len++;
25260 /* An index requires the two-byte modrm form.... */
25262 /* ...like esp (or r12), which always wants an index. */
25266 len++;
25267 }
25270 }
25272 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25273 is set, expect that insn have 8bit immediate alternative. */
25274 int
25276 {
25282 {
25287 {
25290 {
25302 }
25304 {
25307 }
25308 }
25310 {
25320 /* Immediates for DImode instructions are encoded
25321 as 32bit sign extended values. */
25327 }
25328 }
25330 }
25332 /* Compute default value for "length_address" attribute. */
25333 int
25335 {
25339 {
25350 }
25355 {
25358 {
25363 constraints++;
25366 ;
25367 /* Skip ignored operands. */
25370 }
25372 }
25374 }
25376 /* Compute default value for "length_vex" attribute. It includes
25377 2 or 3 byte VEX prefix and 1 opcode byte. */
25379 int
25381 {
25384 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25385 byte VEX prefix. */
25389 /* We can always use 2 byte VEX prefix in 32bit. */
25397 {
25398 /* REX.W bit uses 3 byte VEX prefix. */
25402 }
25403 else
25404 {
25405 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25409 }
25412 }
25413 \f
25414 /* Return the maximum number of instructions a cpu can issue. */
25416 static int
25418 {
25420 {
25451 }
25452 }
25454 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25455 by DEP_INSN and nothing set by DEP_INSN. */
25457 static bool
25459 {
25462 /* Simplify the test for uninteresting insns. */
25470 {
25473 }
25478 {
25481 }
25482 else
25488 /* This test is true if the dependent insn reads the flags but
25489 not any other potentially set register. */
25497 }
25499 /* Return true iff USE_INSN has a memory address with operands set by
25500 SET_INSN. */
25502 bool
25504 {
25509 {
25512 }
25514 }
25516 /* Helper function for exact_store_load_dependency.
25517 Return true if addr is found in insn. */
25518 static bool
25520 {
25527 {
25533 CASE_CONST_ANY:
25542 }
25546 {
25548 {
25558 }
25559 }
25561 }
25563 /* Return true if there exists exact dependency for store & load, i.e.
25564 the same memory address is used in them. */
25565 static bool
25567 {
25581 }
25583 static int
25585 {
25591 /* Anti and output dependencies have zero cost on all CPUs. */
25597 /* If we can't recognize the insns, we can't really do anything. */
25605 {
25607 /* Address Generation Interlock adds a cycle of latency. */
25609 {
25620 }
25624 /* ??? Compares pair with jump/setcc. */
25628 /* Floating point stores require value to be ready one cycle earlier. */
25636 /* INT->FP conversion is expensive. */
25640 /* There is one cycle extra latency between an FP op and a store. */
25650 /* Show ability of reorder buffer to hide latency of load by executing
25651 in parallel with previous instruction in case
25652 previous instruction is not needed to compute the address. */
25655 {
25656 /* Claim moves to take one cycle, as core can issue one load
25657 at time and the next load can start cycle later. */
25662 cost--;
25663 }
25667 /* The esp dependency is resolved before
25668 the instruction is really finished. */
25673 /* INT->FP conversion is expensive. */
25679 /* Show ability of reorder buffer to hide latency of load by executing
25680 in parallel with previous instruction in case
25681 previous instruction is not needed to compute the address. */
25684 {
25685 /* Claim moves to take one cycle, as core can issue one load
25686 at time and the next load can start cycle later. */
25692 else
25694 }
25705 /* Stack engine allows to execute push&pop instructions in parall. */
25709 /* FALLTHRU */
25715 /* Show ability of reorder buffer to hide latency of load by executing
25716 in parallel with previous instruction in case
25717 previous instruction is not needed to compute the address. */
25720 {
25724 /* Because of the difference between the length of integer and
25725 floating unit pipeline preparation stages, the memory operands
25726 for floating point are cheaper.
25728 ??? For Athlon it the difference is most probably 2. */
25731 else
25736 else
25738 }
25745 /* Stack engine allows to execute push&pop instructions in parall. */
25752 /* Show ability of reorder buffer to hide latency of load by executing
25753 in parallel with previous instruction in case
25754 previous instruction is not needed to compute the address. */
25757 {
25760 else
25762 }
25770 /* Increase cost of integer loads. */
25773 {
25776 {
25779 else
25780 {
25781 /* Increase cost of ld/st for short int types only
25782 because of store forwarding issue. */
25786 {
25787 /* Increase cost of store/load insn if exact
25788 dependence exists and it is load insn. */
25793 }
25794 }
25795 }
25796 }
25800 }
25803 }
25805 /* How many alternative schedules to try. This should be as wide as the
25806 scheduling freedom in the DFA, but no wider. Making this value too
25807 large results extra work for the scheduler. */
25809 static int
25811 {
25813 {
25825 /* We use lookahead value 4 for BD both before and after reload
25826 schedules. Plan is to have value 8 included for O3. */
25836 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25837 as many instructions can be executed on a cycle, i.e.,
25838 issue_rate. I wonder why tuning for many CPUs does not do this. */
25841 /* Don't use lookahead for pre-reload schedule to save compile time. */
25846 }
25847 }
25849 /* Return true if target platform supports macro-fusion. */
25851 static bool
25853 {
25855 }
25857 /* Check whether current microarchitecture support macro fusion
25858 for insn pair "CONDGEN + CONDJMP". Refer to
25859 "Intel Architectures Optimization Reference Manual". */
25861 static bool
25863 {
25885 else
25886 {
25891 {
25895 else
25897 }
25898 }
25905 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25906 supported. */
25913 /* No fusion for RIP-relative address. */
25920 ix86_address parts;
25926 }
25931 /* Check whether conditional jump use Sign or Overflow Flags. */
25939 /* Return true for TYPE_TEST and TYPE_ICMP. */
25944 /* The following is the case that macro-fusion for alu + jmp. */
25948 /* No fusion for alu op with memory destination operand. */
25953 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25954 supported. */
25963 }
25965 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25966 execution. It is applied if
25967 (1) IMUL instruction is on the top of list;
25968 (2) There exists the only producer of independent IMUL instruction in
25969 ready list.
25970 Return index of IMUL producer if it was found and -1 otherwise. */
25971 static int
25973 {
25975 sd_iterator_def sd_it;
25976 dep_t dep;
25983 /* Check that IMUL instruction is on the top of ready list. */
25992 /* Search for producer of independent IMUL instruction. */
25994 {
25998 /* Skip IMUL instruction. */
26008 {
26009 rtx con;
26020 {
26021 sd_iterator_def sd_it1;
26022 dep_t dep1;
26023 /* Check if there is no other dependee for IMUL. */
26026 {
26027 rtx pro;
26033 }
26036 }
26037 }
26040 }
26042 }
26044 /* Try to find the best candidate on the top of ready list if two insns
26045 have the same priority - candidate is best if its dependees were
26046 scheduled earlier. Applied for Silvermont only.
26047 Return true if top 2 insns must be interchanged. */
26048 static bool
26050 {
26053 rtx set;
26054 sd_iterator_def sd_it;
26055 dep_t dep;
26058 #define INSN_TICK(INSN) (HID (INSN)->tick)
26079 {
26082 /* Determine winner more precise. */
26084 {
26085 rtx pro;
26091 }
26093 {
26094 rtx pro;
26100 }
26103 {
26104 /* Determine winner - load must win. */
26110 }
26112 }
26114 #undef INSN_TICK
26115 }
26117 /* Perform possible reodering of ready list for Atom/Silvermont only.
26118 Return issue rate. */
26119 static int
26122 {
26126 rtx insn;
26129 /* Set up issue rate. */
26132 /* Do reodering for BONNELL/SILVERMONT only. */
26136 /* Nothing to do if ready list contains only 1 instruction. */
26140 /* Do reodering for post-reload scheduler only. */
26145 {
26150 /* Put IMUL producer (ready[index]) at the top of ready list. */
26156 }
26158 {
26162 /* Swap 2 top elements of ready list. */
26166 }
26168 }
26170 static bool
26173 /* Returns true if lhs of insn is HW function argument register and set up
26174 is_spilled to true if it is likely spilled HW register. */
26175 static bool
26177 {
26178 rtx dst;
26182 /* Call instructions are not movable, ignore it. */
26193 {
26194 /* Is it likely spilled HW register? */
26199 }
26201 }
26203 /* Add output dependencies for chain of function adjacent arguments if only
26204 there is a move to likely spilled HW register. Return first argument
26205 if at least one dependence was added or NULL otherwise. */
26206 static rtx
26208 {
26209 rtx insn;
26216 /* Find nearest to call argument passing instruction. */
26218 {
26227 }
26231 {
26238 {
26241 }
26243 {
26244 /* Add output depdendence between two function arguments if chain
26245 of output arguments contains likely spilled HW registers. */
26249 }
26250 else
26252 }
26256 }
26258 /* Add output or anti dependency from insn to first_arg to restrict its code
26259 motion. */
26260 static void
26262 {
26263 rtx set;
26264 rtx tmp;
26271 {
26272 /* Add output dependency to the first function argument. */
26275 }
26276 /* Add anti dependency. */
26278 }
26280 /* Avoid cross block motion of function argument through adding dependency
26281 from the first non-jump instruction in bb. */
26282 static void
26284 {
26288 {
26290 {
26293 {
26296 }
26297 }
26301 }
26302 }
26304 /* Hook for pre-reload schedule - avoid motion of function arguments
26305 passed in likely spilled HW registers. */
26306 static void
26308 {
26309 rtx insn;
26317 {
26320 {
26321 /* Add dependee for first argument to predecessors if only
26322 region contains more than one block. */
26326 /* Skip trivial regions and region head blocks that can have
26327 predecessors outside of region. */
26329 {
26330 edge e;
26331 edge_iterator ei;
26333 /* Regions are SCCs with the exception of selective
26334 scheduling with pipelining of outer blocks enabled.
26335 So also check that immediate predecessors of a non-head
26336 block are in the same region. */
26338 {
26339 /* Avoid creating of loop-carried dependencies through
26340 using topological ordering in the region. */
26344 }
26345 }
26349 }
26350 }
26353 }
26355 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26356 HW registers to maximum, to schedule them at soon as possible. These are
26357 moves from function argument registers at the top of the function entry
26358 and moves from function return value registers after call. */
26359 static int
26361 {
26362 rtx set;
26372 {
26379 }
26382 }
26384 /* Model decoder of Core 2/i7.
26385 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26386 track the instruction fetch block boundaries and make sure that long
26387 (9+ bytes) instructions are assigned to D0. */
26389 /* Maximum length of an insn that can be handled by
26390 a secondary decoder unit. '8' for Core 2/i7. */
26393 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26394 '16' for Core 2/i7. */
26397 /* Maximum number of instructions decoder can handle per cycle.
26398 '6' for Core 2/i7. */
26402 ix86_first_cycle_multipass_data_t;
26404 const_ix86_first_cycle_multipass_data_t;
26406 /* A variable to store target state across calls to max_issue within
26407 one cycle. */
26411 /* Initialize DATA. */
26412 static void
26414 {
26415 ix86_first_cycle_multipass_data_t data
26422 }
26424 /* Advancing the cycle; reset ifetch block counts. */
26425 static void
26427 {
26434 }
26438 /* Filter out insns from ready_try that the core will not be able to issue
26439 on current cycle due to decoder. */
26440 static void
26441 core2i7_first_cycle_multipass_filter_ready_try
26444 {
26446 {
26447 rtx insn;
26457 (!first_cycle_insn_p
26459 /* ... or it would not fit into the ifetch block ... */
26461 /* ... or the decoder is full already ... */
26463 /* ... mask the insn out. */
26464 {
26469 }
26470 }
26471 }
26473 /* Prepare for a new round of multipass lookahead scheduling. */
26474 static void
26478 {
26479 ix86_first_cycle_multipass_data_t data
26481 const_ix86_first_cycle_multipass_data_t prev_data
26484 /* Restore the state from the end of the previous round. */
26488 /* Filter instructions that cannot be issued on current cycle due to
26489 decoder restrictions. */
26491 first_cycle_insn_p);
26492 }
26494 /* INSN is being issued in current solution. Account for its impact on
26495 the decoder model. */
26496 static void
26500 {
26501 ix86_first_cycle_multipass_data_t data
26503 const_ix86_first_cycle_multipass_data_t prev_data
26513 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26515 {
26518 }
26520 {
26524 }
26527 /* Filter out insns from ready_try that the core will not be able to issue
26528 on current cycle due to decoder. */
26531 }
26533 /* Revert the effect on ready_try. */
26534 static void
26538 {
26539 const_ix86_first_cycle_multipass_data_t data
26542 sbitmap_iterator sbi;
26546 {
26548 }
26549 }
26551 /* Save the result of multipass lookahead scheduling for the next round. */
26552 static void
26554 {
26555 const_ix86_first_cycle_multipass_data_t data
26557 ix86_first_cycle_multipass_data_t next_data
26561 {
26564 }
26565 }
26567 /* Deallocate target data. */
26568 static void
26570 {
26571 ix86_first_cycle_multipass_data_t data
26575 {
26579 }
26580 }
26582 /* Prepare for scheduling pass. */
26583 static void
26587 {
26588 /* Install scheduling hooks for current CPU. Some of these hooks are used
26589 in time-critical parts of the scheduler, so we only set them up when
26590 they are actually used. */
26592 {
26597 /* Do not perform multipass scheduling for pre-reload schedule
26598 to save compile time. */
26600 {
26616 /* Set decoder parameters. */
26621 }
26622 /* ... Fall through ... */
26632 }
26633 }
26635 \f
26636 /* Compute the alignment given to a constant that is being placed in memory.
26637 EXP is the constant and ALIGN is the alignment that the object would
26638 ordinarily have.
26639 The value of this function is used instead of that alignment to align
26640 the object. */
26642 int
26644 {
26647 {
26652 }
26658 }
26660 /* Compute the alignment for a static variable.
26661 TYPE is the data type, and ALIGN is the alignment that
26662 the object would ordinarily have. The value of this function is used
26663 instead of that alignment to align the object. */
26665 int
26667 {
26668 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26669 for symbols from other compilation units or symbols that don't need
26670 to bind locally. In order to preserve some ABI compatibility with
26671 those compilers, ensure we don't decrease alignment from what we
26672 used to assume. */
26674 int max_align_compat
26677 /* A data structure, equal or greater than the size of a cache line
26678 (64 bytes in the Pentium 4 and other recent Intel processors, including
26679 processors based on Intel Core microarchitecture) should be aligned
26680 so that its base address is a multiple of a cache line size. */
26682 int max_align
26692 {
26701 }
26703 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26704 to 16byte boundary. */
26706 {
26713 }
26719 {
26724 }
26726 {
26733 }
26738 {
26743 }
26746 {
26751 }
26754 }
26756 /* Compute the alignment for a local variable or a stack slot. EXP is
26757 the data type or decl itself, MODE is the widest mode available and
26758 ALIGN is the alignment that the object would ordinarily have. The
26759 value of this macro is used instead of that alignment to align the
26760 object. */
26762 unsigned int
26765 {
26769 {
26772 }
26773 else
26774 {
26777 }
26779 /* Don't do dynamic stack realignment for long long objects with
26780 -mpreferred-stack-boundary=2. */
26789 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26790 register in MODE. We will return the largest alignment of XF
26791 and DF. */
26793 {
26797 }
26799 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26800 to 16byte boundary. Exact wording is:
26802 An array uses the same alignment as its elements, except that a local or
26803 global array variable of length at least 16 bytes or
26804 a C99 variable-length array variable always has alignment of at least 16 bytes.
26806 This was added to allow use of aligned SSE instructions at arrays. This
26807 rule is meant for static storage (where compiler can not do the analysis
26808 by itself). We follow it for automatic variables only when convenient.
26809 We fully control everything in the function compiled and functions from
26810 other unit can not rely on the alignment.
26812 Exclude va_list type. It is the common case of local array where
26813 we can not benefit from the alignment.
26815 TODO: Probably one should optimize for size only when var is not escaping. */
26818 {
26828 }
26830 {
26835 }
26837 {
26843 }
26848 {
26853 }
26856 {
26862 }
26864 }
26866 /* Compute the minimum required alignment for dynamic stack realignment
26867 purposes for a local variable, parameter or a stack slot. EXP is
26868 the data type or decl itself, MODE is its mode and ALIGN is the
26869 alignment that the object would ordinarily have. */
26871 unsigned int
26874 {
26878 {
26881 }
26882 else
26883 {
26886 }
26891 /* Don't do dynamic stack realignment for long long objects with
26892 -mpreferred-stack-boundary=2. */
26899 }
26900 \f
26901 /* Find a location for the static chain incoming to a nested function.
26902 This is a register, unless all free registers are used by arguments. */
26904 static rtx
26906 {
26913 {
26914 /* We always use R10 in 64-bit mode. */
26916 }
26917 else
26918 {
26919 tree fntype;
26922 /* By default in 32-bit mode we use ECX to pass the static chain. */
26928 {
26929 /* Fastcall functions use ecx/edx for arguments, which leaves
26930 us with EAX for the static chain.
26931 Thiscall functions use ecx for arguments, which also
26932 leaves us with EAX for the static chain. */
26934 }
26936 {
26937 /* Thiscall functions use ecx for arguments, which leaves
26938 us with EAX and EDX for the static chain.
26939 We are using for abi-compatibility EAX. */
26941 }
26943 {
26944 /* For regparm 3, we have no free call-clobbered registers in
26945 which to store the static chain. In order to implement this,
26946 we have the trampoline push the static chain to the stack.
26947 However, we can't push a value below the return address when
26948 we call the nested function directly, so we have to use an
26949 alternate entry point. For this we use ESI, and have the
26950 alternate entry point push ESI, so that things appear the
26951 same once we're executing the nested function. */
26953 {
26959 }
26961 }
26962 }
26965 }
26967 /* Emit RTL insns to initialize the variable parts of a trampoline.
26968 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26969 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26970 to be passed to the target function. */
26972 static void
26974 {
26982 {
26985 /* Load the function address to r11. Try to load address using
26986 the shorter movl instead of movabs. We may want to support
26987 movq for kernel mode, but kernel does not use trampolines at
26988 the moment. FNADDR is a 32bit address and may not be in
26989 DImode when ptr_mode == SImode. Always use movl in this
26990 case. */
26993 {
27002 }
27003 else
27004 {
27011 }
27013 /* Load static chain using movabs to r10. Use the shorter movl
27014 instead of movabs when ptr_mode == SImode. */
27016 {
27019 }
27020 else
27021 {
27024 }
27033 /* Jump to r11; the last (unused) byte is a nop, only there to
27034 pad the write out to a single 32-bit store. */
27038 }
27039 else
27040 {
27043 /* Depending on the static chain location, either load a register
27044 with a constant, or push the constant to the stack. All of the
27045 instructions are the same size. */
27048 {
27050 {
27057 }
27058 }
27059 else
27074 /* Compute offset from the end of the jmp to the target function.
27075 In the case in which the trampoline stores the static chain on
27076 the stack, we need to skip the first insn which pushes the
27077 (call-saved) register static chain; this push is 1 byte. */
27084 }
27088 #ifdef HAVE_ENABLE_EXECUTE_STACK
27089 #ifdef CHECK_EXECUTE_STACK_ENABLED
27091 #endif
27094 #endif
27095 }
27096 \f
27097 /* The following file contains several enumerations and data structures
27098 built from the definitions in i386-builtin-types.def. */
27102 /* Table for the ix86 builtin non-function types. */
27105 /* Retrieve an element from the above table, building some of
27106 the types lazily. */
27108 static tree
27110 {
27122 {
27130 }
27131 else
27132 {
27138 else
27146 }
27150 }
27152 /* Table for the ix86 builtin function types. */
27155 /* Retrieve an element from the above table, building some of
27156 the types lazily. */
27158 static tree
27160 {
27161 tree type;
27170 {
27178 {
27181 }
27184 }
27185 else
27186 {
27192 }
27196 }
27199 /* Codes for all the SSE/MMX builtins. */
27200 enum ix86_builtins
27201 {
27202 IX86_BUILTIN_ADDPS,
27203 IX86_BUILTIN_ADDSS,
27204 IX86_BUILTIN_DIVPS,
27205 IX86_BUILTIN_DIVSS,
27206 IX86_BUILTIN_MULPS,
27207 IX86_BUILTIN_MULSS,
27208 IX86_BUILTIN_SUBPS,
27209 IX86_BUILTIN_SUBSS,
27211 IX86_BUILTIN_CMPEQPS,
27212 IX86_BUILTIN_CMPLTPS,
27213 IX86_BUILTIN_CMPLEPS,
27214 IX86_BUILTIN_CMPGTPS,
27215 IX86_BUILTIN_CMPGEPS,
27216 IX86_BUILTIN_CMPNEQPS,
27217 IX86_BUILTIN_CMPNLTPS,
27218 IX86_BUILTIN_CMPNLEPS,
27219 IX86_BUILTIN_CMPNGTPS,
27220 IX86_BUILTIN_CMPNGEPS,
27221 IX86_BUILTIN_CMPORDPS,
27222 IX86_BUILTIN_CMPUNORDPS,
27223 IX86_BUILTIN_CMPEQSS,
27224 IX86_BUILTIN_CMPLTSS,
27225 IX86_BUILTIN_CMPLESS,
27226 IX86_BUILTIN_CMPNEQSS,
27227 IX86_BUILTIN_CMPNLTSS,
27228 IX86_BUILTIN_CMPNLESS,
27229 IX86_BUILTIN_CMPORDSS,
27230 IX86_BUILTIN_CMPUNORDSS,
27232 IX86_BUILTIN_COMIEQSS,
27233 IX86_BUILTIN_COMILTSS,
27234 IX86_BUILTIN_COMILESS,
27235 IX86_BUILTIN_COMIGTSS,
27236 IX86_BUILTIN_COMIGESS,
27237 IX86_BUILTIN_COMINEQSS,
27238 IX86_BUILTIN_UCOMIEQSS,
27239 IX86_BUILTIN_UCOMILTSS,
27240 IX86_BUILTIN_UCOMILESS,
27241 IX86_BUILTIN_UCOMIGTSS,
27242 IX86_BUILTIN_UCOMIGESS,
27243 IX86_BUILTIN_UCOMINEQSS,
27245 IX86_BUILTIN_CVTPI2PS,
27246 IX86_BUILTIN_CVTPS2PI,
27247 IX86_BUILTIN_CVTSI2SS,
27248 IX86_BUILTIN_CVTSI642SS,
27249 IX86_BUILTIN_CVTSS2SI,
27250 IX86_BUILTIN_CVTSS2SI64,
27251 IX86_BUILTIN_CVTTPS2PI,
27252 IX86_BUILTIN_CVTTSS2SI,
27253 IX86_BUILTIN_CVTTSS2SI64,
27255 IX86_BUILTIN_MAXPS,
27256 IX86_BUILTIN_MAXSS,
27257 IX86_BUILTIN_MINPS,
27258 IX86_BUILTIN_MINSS,
27260 IX86_BUILTIN_LOADUPS,
27261 IX86_BUILTIN_STOREUPS,
27262 IX86_BUILTIN_MOVSS,
27264 IX86_BUILTIN_MOVHLPS,
27265 IX86_BUILTIN_MOVLHPS,
27266 IX86_BUILTIN_LOADHPS,
27267 IX86_BUILTIN_LOADLPS,
27268 IX86_BUILTIN_STOREHPS,
27269 IX86_BUILTIN_STORELPS,
27271 IX86_BUILTIN_MASKMOVQ,
27272 IX86_BUILTIN_MOVMSKPS,
27273 IX86_BUILTIN_PMOVMSKB,
27275 IX86_BUILTIN_MOVNTPS,
27276 IX86_BUILTIN_MOVNTQ,
27278 IX86_BUILTIN_LOADDQU,
27279 IX86_BUILTIN_STOREDQU,
27281 IX86_BUILTIN_PACKSSWB,
27282 IX86_BUILTIN_PACKSSDW,
27283 IX86_BUILTIN_PACKUSWB,
27285 IX86_BUILTIN_PADDB,
27286 IX86_BUILTIN_PADDW,
27287 IX86_BUILTIN_PADDD,
27288 IX86_BUILTIN_PADDQ,
27289 IX86_BUILTIN_PADDSB,
27290 IX86_BUILTIN_PADDSW,
27291 IX86_BUILTIN_PADDUSB,
27292 IX86_BUILTIN_PADDUSW,
27293 IX86_BUILTIN_PSUBB,
27294 IX86_BUILTIN_PSUBW,
27295 IX86_BUILTIN_PSUBD,
27296 IX86_BUILTIN_PSUBQ,
27297 IX86_BUILTIN_PSUBSB,
27298 IX86_BUILTIN_PSUBSW,
27299 IX86_BUILTIN_PSUBUSB,
27300 IX86_BUILTIN_PSUBUSW,
27302 IX86_BUILTIN_PAND,
27303 IX86_BUILTIN_PANDN,
27304 IX86_BUILTIN_POR,
27305 IX86_BUILTIN_PXOR,
27307 IX86_BUILTIN_PAVGB,
27308 IX86_BUILTIN_PAVGW,
27310 IX86_BUILTIN_PCMPEQB,
27311 IX86_BUILTIN_PCMPEQW,
27312 IX86_BUILTIN_PCMPEQD,
27313 IX86_BUILTIN_PCMPGTB,
27314 IX86_BUILTIN_PCMPGTW,
27315 IX86_BUILTIN_PCMPGTD,
27317 IX86_BUILTIN_PMADDWD,
27319 IX86_BUILTIN_PMAXSW,
27320 IX86_BUILTIN_PMAXUB,
27321 IX86_BUILTIN_PMINSW,
27322 IX86_BUILTIN_PMINUB,
27324 IX86_BUILTIN_PMULHUW,
27325 IX86_BUILTIN_PMULHW,
27326 IX86_BUILTIN_PMULLW,
27328 IX86_BUILTIN_PSADBW,
27329 IX86_BUILTIN_PSHUFW,
27331 IX86_BUILTIN_PSLLW,
27332 IX86_BUILTIN_PSLLD,
27333 IX86_BUILTIN_PSLLQ,
27334 IX86_BUILTIN_PSRAW,
27335 IX86_BUILTIN_PSRAD,
27336 IX86_BUILTIN_PSRLW,
27337 IX86_BUILTIN_PSRLD,
27338 IX86_BUILTIN_PSRLQ,
27339 IX86_BUILTIN_PSLLWI,
27340 IX86_BUILTIN_PSLLDI,
27341 IX86_BUILTIN_PSLLQI,
27342 IX86_BUILTIN_PSRAWI,
27343 IX86_BUILTIN_PSRADI,
27344 IX86_BUILTIN_PSRLWI,
27345 IX86_BUILTIN_PSRLDI,
27346 IX86_BUILTIN_PSRLQI,
27348 IX86_BUILTIN_PUNPCKHBW,
27349 IX86_BUILTIN_PUNPCKHWD,
27350 IX86_BUILTIN_PUNPCKHDQ,
27351 IX86_BUILTIN_PUNPCKLBW,
27352 IX86_BUILTIN_PUNPCKLWD,
27353 IX86_BUILTIN_PUNPCKLDQ,
27355 IX86_BUILTIN_SHUFPS,
27357 IX86_BUILTIN_RCPPS,
27358 IX86_BUILTIN_RCPSS,
27359 IX86_BUILTIN_RSQRTPS,
27360 IX86_BUILTIN_RSQRTPS_NR,
27361 IX86_BUILTIN_RSQRTSS,
27362 IX86_BUILTIN_RSQRTF,
27363 IX86_BUILTIN_SQRTPS,
27364 IX86_BUILTIN_SQRTPS_NR,
27365 IX86_BUILTIN_SQRTSS,
27367 IX86_BUILTIN_UNPCKHPS,
27368 IX86_BUILTIN_UNPCKLPS,
27370 IX86_BUILTIN_ANDPS,
27371 IX86_BUILTIN_ANDNPS,
27372 IX86_BUILTIN_ORPS,
27373 IX86_BUILTIN_XORPS,
27375 IX86_BUILTIN_EMMS,
27376 IX86_BUILTIN_LDMXCSR,
27377 IX86_BUILTIN_STMXCSR,
27378 IX86_BUILTIN_SFENCE,
27380 IX86_BUILTIN_FXSAVE,
27381 IX86_BUILTIN_FXRSTOR,
27382 IX86_BUILTIN_FXSAVE64,
27383 IX86_BUILTIN_FXRSTOR64,
27385 IX86_BUILTIN_XSAVE,
27386 IX86_BUILTIN_XRSTOR,
27387 IX86_BUILTIN_XSAVE64,
27388 IX86_BUILTIN_XRSTOR64,
27390 IX86_BUILTIN_XSAVEOPT,
27391 IX86_BUILTIN_XSAVEOPT64,
27393 /* 3DNow! Original */
27394 IX86_BUILTIN_FEMMS,
27395 IX86_BUILTIN_PAVGUSB,
27396 IX86_BUILTIN_PF2ID,
27397 IX86_BUILTIN_PFACC,
27398 IX86_BUILTIN_PFADD,
27399 IX86_BUILTIN_PFCMPEQ,
27400 IX86_BUILTIN_PFCMPGE,
27401 IX86_BUILTIN_PFCMPGT,
27402 IX86_BUILTIN_PFMAX,
27403 IX86_BUILTIN_PFMIN,
27404 IX86_BUILTIN_PFMUL,
27405 IX86_BUILTIN_PFRCP,
27406 IX86_BUILTIN_PFRCPIT1,
27407 IX86_BUILTIN_PFRCPIT2,
27408 IX86_BUILTIN_PFRSQIT1,
27409 IX86_BUILTIN_PFRSQRT,
27410 IX86_BUILTIN_PFSUB,
27411 IX86_BUILTIN_PFSUBR,
27412 IX86_BUILTIN_PI2FD,
27413 IX86_BUILTIN_PMULHRW,
27415 /* 3DNow! Athlon Extensions */
27416 IX86_BUILTIN_PF2IW,
27417 IX86_BUILTIN_PFNACC,
27418 IX86_BUILTIN_PFPNACC,
27419 IX86_BUILTIN_PI2FW,
27420 IX86_BUILTIN_PSWAPDSI,
27421 IX86_BUILTIN_PSWAPDSF,
27423 /* SSE2 */
27424 IX86_BUILTIN_ADDPD,
27425 IX86_BUILTIN_ADDSD,
27426 IX86_BUILTIN_DIVPD,
27427 IX86_BUILTIN_DIVSD,
27428 IX86_BUILTIN_MULPD,
27429 IX86_BUILTIN_MULSD,
27430 IX86_BUILTIN_SUBPD,
27431 IX86_BUILTIN_SUBSD,
27433 IX86_BUILTIN_CMPEQPD,
27434 IX86_BUILTIN_CMPLTPD,
27435 IX86_BUILTIN_CMPLEPD,
27436 IX86_BUILTIN_CMPGTPD,
27437 IX86_BUILTIN_CMPGEPD,
27438 IX86_BUILTIN_CMPNEQPD,
27439 IX86_BUILTIN_CMPNLTPD,
27440 IX86_BUILTIN_CMPNLEPD,
27441 IX86_BUILTIN_CMPNGTPD,
27442 IX86_BUILTIN_CMPNGEPD,
27443 IX86_BUILTIN_CMPORDPD,
27444 IX86_BUILTIN_CMPUNORDPD,
27445 IX86_BUILTIN_CMPEQSD,
27446 IX86_BUILTIN_CMPLTSD,
27447 IX86_BUILTIN_CMPLESD,
27448 IX86_BUILTIN_CMPNEQSD,
27449 IX86_BUILTIN_CMPNLTSD,
27450 IX86_BUILTIN_CMPNLESD,
27451 IX86_BUILTIN_CMPORDSD,
27452 IX86_BUILTIN_CMPUNORDSD,
27454 IX86_BUILTIN_COMIEQSD,
27455 IX86_BUILTIN_COMILTSD,
27456 IX86_BUILTIN_COMILESD,
27457 IX86_BUILTIN_COMIGTSD,
27458 IX86_BUILTIN_COMIGESD,
27459 IX86_BUILTIN_COMINEQSD,
27460 IX86_BUILTIN_UCOMIEQSD,
27461 IX86_BUILTIN_UCOMILTSD,
27462 IX86_BUILTIN_UCOMILESD,
27463 IX86_BUILTIN_UCOMIGTSD,
27464 IX86_BUILTIN_UCOMIGESD,
27465 IX86_BUILTIN_UCOMINEQSD,
27467 IX86_BUILTIN_MAXPD,
27468 IX86_BUILTIN_MAXSD,
27469 IX86_BUILTIN_MINPD,
27470 IX86_BUILTIN_MINSD,
27472 IX86_BUILTIN_ANDPD,
27473 IX86_BUILTIN_ANDNPD,
27474 IX86_BUILTIN_ORPD,
27475 IX86_BUILTIN_XORPD,
27477 IX86_BUILTIN_SQRTPD,
27478 IX86_BUILTIN_SQRTSD,
27480 IX86_BUILTIN_UNPCKHPD,
27481 IX86_BUILTIN_UNPCKLPD,
27483 IX86_BUILTIN_SHUFPD,
27485 IX86_BUILTIN_LOADUPD,
27486 IX86_BUILTIN_STOREUPD,
27487 IX86_BUILTIN_MOVSD,
27489 IX86_BUILTIN_LOADHPD,
27490 IX86_BUILTIN_LOADLPD,
27492 IX86_BUILTIN_CVTDQ2PD,
27493 IX86_BUILTIN_CVTDQ2PS,
27495 IX86_BUILTIN_CVTPD2DQ,
27496 IX86_BUILTIN_CVTPD2PI,
27497 IX86_BUILTIN_CVTPD2PS,
27498 IX86_BUILTIN_CVTTPD2DQ,
27499 IX86_BUILTIN_CVTTPD2PI,
27501 IX86_BUILTIN_CVTPI2PD,
27502 IX86_BUILTIN_CVTSI2SD,
27503 IX86_BUILTIN_CVTSI642SD,
27505 IX86_BUILTIN_CVTSD2SI,
27506 IX86_BUILTIN_CVTSD2SI64,
27507 IX86_BUILTIN_CVTSD2SS,
27508 IX86_BUILTIN_CVTSS2SD,
27509 IX86_BUILTIN_CVTTSD2SI,
27510 IX86_BUILTIN_CVTTSD2SI64,
27512 IX86_BUILTIN_CVTPS2DQ,
27513 IX86_BUILTIN_CVTPS2PD,
27514 IX86_BUILTIN_CVTTPS2DQ,
27516 IX86_BUILTIN_MOVNTI,
27517 IX86_BUILTIN_MOVNTI64,
27518 IX86_BUILTIN_MOVNTPD,
27519 IX86_BUILTIN_MOVNTDQ,
27521 IX86_BUILTIN_MOVQ128,
27523 /* SSE2 MMX */
27524 IX86_BUILTIN_MASKMOVDQU,
27525 IX86_BUILTIN_MOVMSKPD,
27526 IX86_BUILTIN_PMOVMSKB128,
27528 IX86_BUILTIN_PACKSSWB128,
27529 IX86_BUILTIN_PACKSSDW128,
27530 IX86_BUILTIN_PACKUSWB128,
27532 IX86_BUILTIN_PADDB128,
27533 IX86_BUILTIN_PADDW128,
27534 IX86_BUILTIN_PADDD128,
27535 IX86_BUILTIN_PADDQ128,
27536 IX86_BUILTIN_PADDSB128,
27537 IX86_BUILTIN_PADDSW128,
27538 IX86_BUILTIN_PADDUSB128,
27539 IX86_BUILTIN_PADDUSW128,
27540 IX86_BUILTIN_PSUBB128,
27541 IX86_BUILTIN_PSUBW128,
27542 IX86_BUILTIN_PSUBD128,
27543 IX86_BUILTIN_PSUBQ128,
27544 IX86_BUILTIN_PSUBSB128,
27545 IX86_BUILTIN_PSUBSW128,
27546 IX86_BUILTIN_PSUBUSB128,
27547 IX86_BUILTIN_PSUBUSW128,
27549 IX86_BUILTIN_PAND128,
27550 IX86_BUILTIN_PANDN128,
27551 IX86_BUILTIN_POR128,
27552 IX86_BUILTIN_PXOR128,
27554 IX86_BUILTIN_PAVGB128,
27555 IX86_BUILTIN_PAVGW128,
27557 IX86_BUILTIN_PCMPEQB128,
27558 IX86_BUILTIN_PCMPEQW128,
27559 IX86_BUILTIN_PCMPEQD128,
27560 IX86_BUILTIN_PCMPGTB128,
27561 IX86_BUILTIN_PCMPGTW128,
27562 IX86_BUILTIN_PCMPGTD128,
27564 IX86_BUILTIN_PMADDWD128,
27566 IX86_BUILTIN_PMAXSW128,
27567 IX86_BUILTIN_PMAXUB128,
27568 IX86_BUILTIN_PMINSW128,
27569 IX86_BUILTIN_PMINUB128,
27571 IX86_BUILTIN_PMULUDQ,
27572 IX86_BUILTIN_PMULUDQ128,
27573 IX86_BUILTIN_PMULHUW128,
27574 IX86_BUILTIN_PMULHW128,
27575 IX86_BUILTIN_PMULLW128,
27577 IX86_BUILTIN_PSADBW128,
27578 IX86_BUILTIN_PSHUFHW,
27579 IX86_BUILTIN_PSHUFLW,
27580 IX86_BUILTIN_PSHUFD,
27582 IX86_BUILTIN_PSLLDQI128,
27583 IX86_BUILTIN_PSLLWI128,
27584 IX86_BUILTIN_PSLLDI128,
27585 IX86_BUILTIN_PSLLQI128,
27586 IX86_BUILTIN_PSRAWI128,
27587 IX86_BUILTIN_PSRADI128,
27588 IX86_BUILTIN_PSRLDQI128,
27589 IX86_BUILTIN_PSRLWI128,
27590 IX86_BUILTIN_PSRLDI128,
27591 IX86_BUILTIN_PSRLQI128,
27593 IX86_BUILTIN_PSLLDQ128,
27594 IX86_BUILTIN_PSLLW128,
27595 IX86_BUILTIN_PSLLD128,
27596 IX86_BUILTIN_PSLLQ128,
27597 IX86_BUILTIN_PSRAW128,
27598 IX86_BUILTIN_PSRAD128,
27599 IX86_BUILTIN_PSRLW128,
27600 IX86_BUILTIN_PSRLD128,
27601 IX86_BUILTIN_PSRLQ128,
27603 IX86_BUILTIN_PUNPCKHBW128,
27604 IX86_BUILTIN_PUNPCKHWD128,
27605 IX86_BUILTIN_PUNPCKHDQ128,
27606 IX86_BUILTIN_PUNPCKHQDQ128,
27607 IX86_BUILTIN_PUNPCKLBW128,
27608 IX86_BUILTIN_PUNPCKLWD128,
27609 IX86_BUILTIN_PUNPCKLDQ128,
27610 IX86_BUILTIN_PUNPCKLQDQ128,
27612 IX86_BUILTIN_CLFLUSH,
27613 IX86_BUILTIN_MFENCE,
27614 IX86_BUILTIN_LFENCE,
27615 IX86_BUILTIN_PAUSE,
27617 IX86_BUILTIN_FNSTENV,
27618 IX86_BUILTIN_FLDENV,
27619 IX86_BUILTIN_FNSTSW,
27620 IX86_BUILTIN_FNCLEX,
27622 IX86_BUILTIN_BSRSI,
27623 IX86_BUILTIN_BSRDI,
27624 IX86_BUILTIN_RDPMC,
27625 IX86_BUILTIN_RDTSC,
27626 IX86_BUILTIN_RDTSCP,
27627 IX86_BUILTIN_ROLQI,
27628 IX86_BUILTIN_ROLHI,
27629 IX86_BUILTIN_RORQI,
27630 IX86_BUILTIN_RORHI,
27632 /* SSE3. */
27633 IX86_BUILTIN_ADDSUBPS,
27634 IX86_BUILTIN_HADDPS,
27635 IX86_BUILTIN_HSUBPS,
27636 IX86_BUILTIN_MOVSHDUP,
27637 IX86_BUILTIN_MOVSLDUP,
27638 IX86_BUILTIN_ADDSUBPD,
27639 IX86_BUILTIN_HADDPD,
27640 IX86_BUILTIN_HSUBPD,
27641 IX86_BUILTIN_LDDQU,
27643 IX86_BUILTIN_MONITOR,
27644 IX86_BUILTIN_MWAIT,
27646 /* SSSE3. */
27647 IX86_BUILTIN_PHADDW,
27648 IX86_BUILTIN_PHADDD,
27649 IX86_BUILTIN_PHADDSW,
27650 IX86_BUILTIN_PHSUBW,
27651 IX86_BUILTIN_PHSUBD,
27652 IX86_BUILTIN_PHSUBSW,
27653 IX86_BUILTIN_PMADDUBSW,
27654 IX86_BUILTIN_PMULHRSW,
27655 IX86_BUILTIN_PSHUFB,
27656 IX86_BUILTIN_PSIGNB,
27657 IX86_BUILTIN_PSIGNW,
27658 IX86_BUILTIN_PSIGND,
27659 IX86_BUILTIN_PALIGNR,
27660 IX86_BUILTIN_PABSB,
27661 IX86_BUILTIN_PABSW,
27662 IX86_BUILTIN_PABSD,
27664 IX86_BUILTIN_PHADDW128,
27665 IX86_BUILTIN_PHADDD128,
27666 IX86_BUILTIN_PHADDSW128,
27667 IX86_BUILTIN_PHSUBW128,
27668 IX86_BUILTIN_PHSUBD128,
27669 IX86_BUILTIN_PHSUBSW128,
27670 IX86_BUILTIN_PMADDUBSW128,
27671 IX86_BUILTIN_PMULHRSW128,
27672 IX86_BUILTIN_PSHUFB128,
27673 IX86_BUILTIN_PSIGNB128,
27674 IX86_BUILTIN_PSIGNW128,
27675 IX86_BUILTIN_PSIGND128,
27676 IX86_BUILTIN_PALIGNR128,
27677 IX86_BUILTIN_PABSB128,
27678 IX86_BUILTIN_PABSW128,
27679 IX86_BUILTIN_PABSD128,
27681 /* AMDFAM10 - SSE4A New Instructions. */
27682 IX86_BUILTIN_MOVNTSD,
27683 IX86_BUILTIN_MOVNTSS,
27684 IX86_BUILTIN_EXTRQI,
27685 IX86_BUILTIN_EXTRQ,
27686 IX86_BUILTIN_INSERTQI,
27687 IX86_BUILTIN_INSERTQ,
27689 /* SSE4.1. */
27690 IX86_BUILTIN_BLENDPD,
27691 IX86_BUILTIN_BLENDPS,
27692 IX86_BUILTIN_BLENDVPD,
27693 IX86_BUILTIN_BLENDVPS,
27694 IX86_BUILTIN_PBLENDVB128,
27695 IX86_BUILTIN_PBLENDW128,
27697 IX86_BUILTIN_DPPD,
27698 IX86_BUILTIN_DPPS,
27700 IX86_BUILTIN_INSERTPS128,
27702 IX86_BUILTIN_MOVNTDQA,
27703 IX86_BUILTIN_MPSADBW128,
27704 IX86_BUILTIN_PACKUSDW128,
27705 IX86_BUILTIN_PCMPEQQ,
27706 IX86_BUILTIN_PHMINPOSUW128,
27708 IX86_BUILTIN_PMAXSB128,
27709 IX86_BUILTIN_PMAXSD128,
27710 IX86_BUILTIN_PMAXUD128,
27711 IX86_BUILTIN_PMAXUW128,
27713 IX86_BUILTIN_PMINSB128,
27714 IX86_BUILTIN_PMINSD128,
27715 IX86_BUILTIN_PMINUD128,
27716 IX86_BUILTIN_PMINUW128,
27718 IX86_BUILTIN_PMOVSXBW128,
27719 IX86_BUILTIN_PMOVSXBD128,
27720 IX86_BUILTIN_PMOVSXBQ128,
27721 IX86_BUILTIN_PMOVSXWD128,
27722 IX86_BUILTIN_PMOVSXWQ128,
27723 IX86_BUILTIN_PMOVSXDQ128,
27725 IX86_BUILTIN_PMOVZXBW128,
27726 IX86_BUILTIN_PMOVZXBD128,
27727 IX86_BUILTIN_PMOVZXBQ128,
27728 IX86_BUILTIN_PMOVZXWD128,
27729 IX86_BUILTIN_PMOVZXWQ128,
27730 IX86_BUILTIN_PMOVZXDQ128,
27732 IX86_BUILTIN_PMULDQ128,
27733 IX86_BUILTIN_PMULLD128,
27735 IX86_BUILTIN_ROUNDSD,
27736 IX86_BUILTIN_ROUNDSS,
27738 IX86_BUILTIN_ROUNDPD,
27739 IX86_BUILTIN_ROUNDPS,
27741 IX86_BUILTIN_FLOORPD,
27742 IX86_BUILTIN_CEILPD,
27743 IX86_BUILTIN_TRUNCPD,
27744 IX86_BUILTIN_RINTPD,
27745 IX86_BUILTIN_ROUNDPD_AZ,
27747 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27748 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27749 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27751 IX86_BUILTIN_FLOORPS,
27752 IX86_BUILTIN_CEILPS,
27753 IX86_BUILTIN_TRUNCPS,
27754 IX86_BUILTIN_RINTPS,
27755 IX86_BUILTIN_ROUNDPS_AZ,
27757 IX86_BUILTIN_FLOORPS_SFIX,
27758 IX86_BUILTIN_CEILPS_SFIX,
27759 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27761 IX86_BUILTIN_PTESTZ,
27762 IX86_BUILTIN_PTESTC,
27763 IX86_BUILTIN_PTESTNZC,
27765 IX86_BUILTIN_VEC_INIT_V2SI,
27766 IX86_BUILTIN_VEC_INIT_V4HI,
27767 IX86_BUILTIN_VEC_INIT_V8QI,
27768 IX86_BUILTIN_VEC_EXT_V2DF,
27769 IX86_BUILTIN_VEC_EXT_V2DI,
27770 IX86_BUILTIN_VEC_EXT_V4SF,
27771 IX86_BUILTIN_VEC_EXT_V4SI,
27772 IX86_BUILTIN_VEC_EXT_V8HI,
27773 IX86_BUILTIN_VEC_EXT_V2SI,
27774 IX86_BUILTIN_VEC_EXT_V4HI,
27775 IX86_BUILTIN_VEC_EXT_V16QI,
27776 IX86_BUILTIN_VEC_SET_V2DI,
27777 IX86_BUILTIN_VEC_SET_V4SF,
27778 IX86_BUILTIN_VEC_SET_V4SI,
27779 IX86_BUILTIN_VEC_SET_V8HI,
27780 IX86_BUILTIN_VEC_SET_V4HI,
27781 IX86_BUILTIN_VEC_SET_V16QI,
27783 IX86_BUILTIN_VEC_PACK_SFIX,
27784 IX86_BUILTIN_VEC_PACK_SFIX256,
27786 /* SSE4.2. */
27787 IX86_BUILTIN_CRC32QI,
27788 IX86_BUILTIN_CRC32HI,
27789 IX86_BUILTIN_CRC32SI,
27790 IX86_BUILTIN_CRC32DI,
27792 IX86_BUILTIN_PCMPESTRI128,
27793 IX86_BUILTIN_PCMPESTRM128,
27794 IX86_BUILTIN_PCMPESTRA128,
27795 IX86_BUILTIN_PCMPESTRC128,
27796 IX86_BUILTIN_PCMPESTRO128,
27797 IX86_BUILTIN_PCMPESTRS128,
27798 IX86_BUILTIN_PCMPESTRZ128,
27799 IX86_BUILTIN_PCMPISTRI128,
27800 IX86_BUILTIN_PCMPISTRM128,
27801 IX86_BUILTIN_PCMPISTRA128,
27802 IX86_BUILTIN_PCMPISTRC128,
27803 IX86_BUILTIN_PCMPISTRO128,
27804 IX86_BUILTIN_PCMPISTRS128,
27805 IX86_BUILTIN_PCMPISTRZ128,
27807 IX86_BUILTIN_PCMPGTQ,
27809 /* AES instructions */
27810 IX86_BUILTIN_AESENC128,
27811 IX86_BUILTIN_AESENCLAST128,
27812 IX86_BUILTIN_AESDEC128,
27813 IX86_BUILTIN_AESDECLAST128,
27814 IX86_BUILTIN_AESIMC128,
27815 IX86_BUILTIN_AESKEYGENASSIST128,
27817 /* PCLMUL instruction */
27818 IX86_BUILTIN_PCLMULQDQ128,
27820 /* AVX */
27821 IX86_BUILTIN_ADDPD256,
27822 IX86_BUILTIN_ADDPS256,
27823 IX86_BUILTIN_ADDSUBPD256,
27824 IX86_BUILTIN_ADDSUBPS256,
27825 IX86_BUILTIN_ANDPD256,
27826 IX86_BUILTIN_ANDPS256,
27827 IX86_BUILTIN_ANDNPD256,
27828 IX86_BUILTIN_ANDNPS256,
27829 IX86_BUILTIN_BLENDPD256,
27830 IX86_BUILTIN_BLENDPS256,
27831 IX86_BUILTIN_BLENDVPD256,
27832 IX86_BUILTIN_BLENDVPS256,
27833 IX86_BUILTIN_DIVPD256,
27834 IX86_BUILTIN_DIVPS256,
27835 IX86_BUILTIN_DPPS256,
27836 IX86_BUILTIN_HADDPD256,
27837 IX86_BUILTIN_HADDPS256,
27838 IX86_BUILTIN_HSUBPD256,
27839 IX86_BUILTIN_HSUBPS256,
27840 IX86_BUILTIN_MAXPD256,
27841 IX86_BUILTIN_MAXPS256,
27842 IX86_BUILTIN_MINPD256,
27843 IX86_BUILTIN_MINPS256,
27844 IX86_BUILTIN_MULPD256,
27845 IX86_BUILTIN_MULPS256,
27846 IX86_BUILTIN_ORPD256,
27847 IX86_BUILTIN_ORPS256,
27848 IX86_BUILTIN_SHUFPD256,
27849 IX86_BUILTIN_SHUFPS256,
27850 IX86_BUILTIN_SUBPD256,
27851 IX86_BUILTIN_SUBPS256,
27852 IX86_BUILTIN_XORPD256,
27853 IX86_BUILTIN_XORPS256,
27854 IX86_BUILTIN_CMPSD,
27855 IX86_BUILTIN_CMPSS,
27856 IX86_BUILTIN_CMPPD,
27857 IX86_BUILTIN_CMPPS,
27858 IX86_BUILTIN_CMPPD256,
27859 IX86_BUILTIN_CMPPS256,
27860 IX86_BUILTIN_CVTDQ2PD256,
27861 IX86_BUILTIN_CVTDQ2PS256,
27862 IX86_BUILTIN_CVTPD2PS256,
27863 IX86_BUILTIN_CVTPS2DQ256,
27864 IX86_BUILTIN_CVTPS2PD256,
27865 IX86_BUILTIN_CVTTPD2DQ256,
27866 IX86_BUILTIN_CVTPD2DQ256,
27867 IX86_BUILTIN_CVTTPS2DQ256,
27868 IX86_BUILTIN_EXTRACTF128PD256,
27869 IX86_BUILTIN_EXTRACTF128PS256,
27870 IX86_BUILTIN_EXTRACTF128SI256,
27871 IX86_BUILTIN_VZEROALL,
27872 IX86_BUILTIN_VZEROUPPER,
27873 IX86_BUILTIN_VPERMILVARPD,
27874 IX86_BUILTIN_VPERMILVARPS,
27875 IX86_BUILTIN_VPERMILVARPD256,
27876 IX86_BUILTIN_VPERMILVARPS256,
27877 IX86_BUILTIN_VPERMILPD,
27878 IX86_BUILTIN_VPERMILPS,
27879 IX86_BUILTIN_VPERMILPD256,
27880 IX86_BUILTIN_VPERMILPS256,
27881 IX86_BUILTIN_VPERMIL2PD,
27882 IX86_BUILTIN_VPERMIL2PS,
27883 IX86_BUILTIN_VPERMIL2PD256,
27884 IX86_BUILTIN_VPERMIL2PS256,
27885 IX86_BUILTIN_VPERM2F128PD256,
27886 IX86_BUILTIN_VPERM2F128PS256,
27887 IX86_BUILTIN_VPERM2F128SI256,
27888 IX86_BUILTIN_VBROADCASTSS,
27889 IX86_BUILTIN_VBROADCASTSD256,
27890 IX86_BUILTIN_VBROADCASTSS256,
27891 IX86_BUILTIN_VBROADCASTPD256,
27892 IX86_BUILTIN_VBROADCASTPS256,
27893 IX86_BUILTIN_VINSERTF128PD256,
27894 IX86_BUILTIN_VINSERTF128PS256,
27895 IX86_BUILTIN_VINSERTF128SI256,
27896 IX86_BUILTIN_LOADUPD256,
27897 IX86_BUILTIN_LOADUPS256,
27898 IX86_BUILTIN_STOREUPD256,
27899 IX86_BUILTIN_STOREUPS256,
27900 IX86_BUILTIN_LDDQU256,
27901 IX86_BUILTIN_MOVNTDQ256,
27902 IX86_BUILTIN_MOVNTPD256,
27903 IX86_BUILTIN_MOVNTPS256,
27904 IX86_BUILTIN_LOADDQU256,
27905 IX86_BUILTIN_STOREDQU256,
27906 IX86_BUILTIN_MASKLOADPD,
27907 IX86_BUILTIN_MASKLOADPS,
27908 IX86_BUILTIN_MASKSTOREPD,
27909 IX86_BUILTIN_MASKSTOREPS,
27910 IX86_BUILTIN_MASKLOADPD256,
27911 IX86_BUILTIN_MASKLOADPS256,
27912 IX86_BUILTIN_MASKSTOREPD256,
27913 IX86_BUILTIN_MASKSTOREPS256,
27914 IX86_BUILTIN_MOVSHDUP256,
27915 IX86_BUILTIN_MOVSLDUP256,
27916 IX86_BUILTIN_MOVDDUP256,
27918 IX86_BUILTIN_SQRTPD256,
27919 IX86_BUILTIN_SQRTPS256,
27920 IX86_BUILTIN_SQRTPS_NR256,
27921 IX86_BUILTIN_RSQRTPS256,
27922 IX86_BUILTIN_RSQRTPS_NR256,
27924 IX86_BUILTIN_RCPPS256,
27926 IX86_BUILTIN_ROUNDPD256,
27927 IX86_BUILTIN_ROUNDPS256,
27929 IX86_BUILTIN_FLOORPD256,
27930 IX86_BUILTIN_CEILPD256,
27931 IX86_BUILTIN_TRUNCPD256,
27932 IX86_BUILTIN_RINTPD256,
27933 IX86_BUILTIN_ROUNDPD_AZ256,
27935 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27936 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27937 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27939 IX86_BUILTIN_FLOORPS256,
27940 IX86_BUILTIN_CEILPS256,
27941 IX86_BUILTIN_TRUNCPS256,
27942 IX86_BUILTIN_RINTPS256,
27943 IX86_BUILTIN_ROUNDPS_AZ256,
27945 IX86_BUILTIN_FLOORPS_SFIX256,
27946 IX86_BUILTIN_CEILPS_SFIX256,
27947 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27949 IX86_BUILTIN_UNPCKHPD256,
27950 IX86_BUILTIN_UNPCKLPD256,
27951 IX86_BUILTIN_UNPCKHPS256,
27952 IX86_BUILTIN_UNPCKLPS256,
27954 IX86_BUILTIN_SI256_SI,
27955 IX86_BUILTIN_PS256_PS,
27956 IX86_BUILTIN_PD256_PD,
27957 IX86_BUILTIN_SI_SI256,
27958 IX86_BUILTIN_PS_PS256,
27959 IX86_BUILTIN_PD_PD256,
27961 IX86_BUILTIN_VTESTZPD,
27962 IX86_BUILTIN_VTESTCPD,
27963 IX86_BUILTIN_VTESTNZCPD,
27964 IX86_BUILTIN_VTESTZPS,
27965 IX86_BUILTIN_VTESTCPS,
27966 IX86_BUILTIN_VTESTNZCPS,
27967 IX86_BUILTIN_VTESTZPD256,
27968 IX86_BUILTIN_VTESTCPD256,
27969 IX86_BUILTIN_VTESTNZCPD256,
27970 IX86_BUILTIN_VTESTZPS256,
27971 IX86_BUILTIN_VTESTCPS256,
27972 IX86_BUILTIN_VTESTNZCPS256,
27973 IX86_BUILTIN_PTESTZ256,
27974 IX86_BUILTIN_PTESTC256,
27975 IX86_BUILTIN_PTESTNZC256,
27977 IX86_BUILTIN_MOVMSKPD256,
27978 IX86_BUILTIN_MOVMSKPS256,
27980 /* AVX2 */
27981 IX86_BUILTIN_MPSADBW256,
27982 IX86_BUILTIN_PABSB256,
27983 IX86_BUILTIN_PABSW256,
27984 IX86_BUILTIN_PABSD256,
27985 IX86_BUILTIN_PACKSSDW256,
27986 IX86_BUILTIN_PACKSSWB256,
27987 IX86_BUILTIN_PACKUSDW256,
27988 IX86_BUILTIN_PACKUSWB256,
27989 IX86_BUILTIN_PADDB256,
27990 IX86_BUILTIN_PADDW256,
27991 IX86_BUILTIN_PADDD256,
27992 IX86_BUILTIN_PADDQ256,
27993 IX86_BUILTIN_PADDSB256,
27994 IX86_BUILTIN_PADDSW256,
27995 IX86_BUILTIN_PADDUSB256,
27996 IX86_BUILTIN_PADDUSW256,
27997 IX86_BUILTIN_PALIGNR256,
27998 IX86_BUILTIN_AND256I,
27999 IX86_BUILTIN_ANDNOT256I,
28000 IX86_BUILTIN_PAVGB256,
28001 IX86_BUILTIN_PAVGW256,
28002 IX86_BUILTIN_PBLENDVB256,
28003 IX86_BUILTIN_PBLENDVW256,
28004 IX86_BUILTIN_PCMPEQB256,
28005 IX86_BUILTIN_PCMPEQW256,
28006 IX86_BUILTIN_PCMPEQD256,
28007 IX86_BUILTIN_PCMPEQQ256,
28008 IX86_BUILTIN_PCMPGTB256,
28009 IX86_BUILTIN_PCMPGTW256,
28010 IX86_BUILTIN_PCMPGTD256,
28011 IX86_BUILTIN_PCMPGTQ256,
28012 IX86_BUILTIN_PHADDW256,
28013 IX86_BUILTIN_PHADDD256,
28014 IX86_BUILTIN_PHADDSW256,
28015 IX86_BUILTIN_PHSUBW256,
28016 IX86_BUILTIN_PHSUBD256,
28017 IX86_BUILTIN_PHSUBSW256,
28018 IX86_BUILTIN_PMADDUBSW256,
28019 IX86_BUILTIN_PMADDWD256,
28020 IX86_BUILTIN_PMAXSB256,
28021 IX86_BUILTIN_PMAXSW256,
28022 IX86_BUILTIN_PMAXSD256,
28023 IX86_BUILTIN_PMAXUB256,
28024 IX86_BUILTIN_PMAXUW256,
28025 IX86_BUILTIN_PMAXUD256,
28026 IX86_BUILTIN_PMINSB256,
28027 IX86_BUILTIN_PMINSW256,
28028 IX86_BUILTIN_PMINSD256,
28029 IX86_BUILTIN_PMINUB256,
28030 IX86_BUILTIN_PMINUW256,
28031 IX86_BUILTIN_PMINUD256,
28032 IX86_BUILTIN_PMOVMSKB256,
28033 IX86_BUILTIN_PMOVSXBW256,
28034 IX86_BUILTIN_PMOVSXBD256,
28035 IX86_BUILTIN_PMOVSXBQ256,
28036 IX86_BUILTIN_PMOVSXWD256,
28037 IX86_BUILTIN_PMOVSXWQ256,
28038 IX86_BUILTIN_PMOVSXDQ256,
28039 IX86_BUILTIN_PMOVZXBW256,
28040 IX86_BUILTIN_PMOVZXBD256,
28041 IX86_BUILTIN_PMOVZXBQ256,
28042 IX86_BUILTIN_PMOVZXWD256,
28043 IX86_BUILTIN_PMOVZXWQ256,
28044 IX86_BUILTIN_PMOVZXDQ256,
28045 IX86_BUILTIN_PMULDQ256,
28046 IX86_BUILTIN_PMULHRSW256,
28047 IX86_BUILTIN_PMULHUW256,
28048 IX86_BUILTIN_PMULHW256,
28049 IX86_BUILTIN_PMULLW256,
28050 IX86_BUILTIN_PMULLD256,
28051 IX86_BUILTIN_PMULUDQ256,
28052 IX86_BUILTIN_POR256,
28053 IX86_BUILTIN_PSADBW256,
28054 IX86_BUILTIN_PSHUFB256,
28055 IX86_BUILTIN_PSHUFD256,
28056 IX86_BUILTIN_PSHUFHW256,
28057 IX86_BUILTIN_PSHUFLW256,
28058 IX86_BUILTIN_PSIGNB256,
28059 IX86_BUILTIN_PSIGNW256,
28060 IX86_BUILTIN_PSIGND256,
28061 IX86_BUILTIN_PSLLDQI256,
28062 IX86_BUILTIN_PSLLWI256,
28063 IX86_BUILTIN_PSLLW256,
28064 IX86_BUILTIN_PSLLDI256,
28065 IX86_BUILTIN_PSLLD256,
28066 IX86_BUILTIN_PSLLQI256,
28067 IX86_BUILTIN_PSLLQ256,
28068 IX86_BUILTIN_PSRAWI256,
28069 IX86_BUILTIN_PSRAW256,
28070 IX86_BUILTIN_PSRADI256,
28071 IX86_BUILTIN_PSRAD256,
28072 IX86_BUILTIN_PSRLDQI256,
28073 IX86_BUILTIN_PSRLWI256,
28074 IX86_BUILTIN_PSRLW256,
28075 IX86_BUILTIN_PSRLDI256,
28076 IX86_BUILTIN_PSRLD256,
28077 IX86_BUILTIN_PSRLQI256,
28078 IX86_BUILTIN_PSRLQ256,
28079 IX86_BUILTIN_PSUBB256,
28080 IX86_BUILTIN_PSUBW256,
28081 IX86_BUILTIN_PSUBD256,
28082 IX86_BUILTIN_PSUBQ256,
28083 IX86_BUILTIN_PSUBSB256,
28084 IX86_BUILTIN_PSUBSW256,
28085 IX86_BUILTIN_PSUBUSB256,
28086 IX86_BUILTIN_PSUBUSW256,
28087 IX86_BUILTIN_PUNPCKHBW256,
28088 IX86_BUILTIN_PUNPCKHWD256,
28089 IX86_BUILTIN_PUNPCKHDQ256,
28090 IX86_BUILTIN_PUNPCKHQDQ256,
28091 IX86_BUILTIN_PUNPCKLBW256,
28092 IX86_BUILTIN_PUNPCKLWD256,
28093 IX86_BUILTIN_PUNPCKLDQ256,
28094 IX86_BUILTIN_PUNPCKLQDQ256,
28095 IX86_BUILTIN_PXOR256,
28096 IX86_BUILTIN_MOVNTDQA256,
28097 IX86_BUILTIN_VBROADCASTSS_PS,
28098 IX86_BUILTIN_VBROADCASTSS_PS256,
28099 IX86_BUILTIN_VBROADCASTSD_PD256,
28100 IX86_BUILTIN_VBROADCASTSI256,
28101 IX86_BUILTIN_PBLENDD256,
28102 IX86_BUILTIN_PBLENDD128,
28103 IX86_BUILTIN_PBROADCASTB256,
28104 IX86_BUILTIN_PBROADCASTW256,
28105 IX86_BUILTIN_PBROADCASTD256,
28106 IX86_BUILTIN_PBROADCASTQ256,
28107 IX86_BUILTIN_PBROADCASTB128,
28108 IX86_BUILTIN_PBROADCASTW128,
28109 IX86_BUILTIN_PBROADCASTD128,
28110 IX86_BUILTIN_PBROADCASTQ128,
28111 IX86_BUILTIN_VPERMVARSI256,
28112 IX86_BUILTIN_VPERMDF256,
28113 IX86_BUILTIN_VPERMVARSF256,
28114 IX86_BUILTIN_VPERMDI256,
28115 IX86_BUILTIN_VPERMTI256,
28116 IX86_BUILTIN_VEXTRACT128I256,
28117 IX86_BUILTIN_VINSERT128I256,
28118 IX86_BUILTIN_MASKLOADD,
28119 IX86_BUILTIN_MASKLOADQ,
28120 IX86_BUILTIN_MASKLOADD256,
28121 IX86_BUILTIN_MASKLOADQ256,
28122 IX86_BUILTIN_MASKSTORED,
28123 IX86_BUILTIN_MASKSTOREQ,
28124 IX86_BUILTIN_MASKSTORED256,
28125 IX86_BUILTIN_MASKSTOREQ256,
28126 IX86_BUILTIN_PSLLVV4DI,
28127 IX86_BUILTIN_PSLLVV2DI,
28128 IX86_BUILTIN_PSLLVV8SI,
28129 IX86_BUILTIN_PSLLVV4SI,
28130 IX86_BUILTIN_PSRAVV8SI,
28131 IX86_BUILTIN_PSRAVV4SI,
28132 IX86_BUILTIN_PSRLVV4DI,
28133 IX86_BUILTIN_PSRLVV2DI,
28134 IX86_BUILTIN_PSRLVV8SI,
28135 IX86_BUILTIN_PSRLVV4SI,
28137 IX86_BUILTIN_GATHERSIV2DF,
28138 IX86_BUILTIN_GATHERSIV4DF,
28139 IX86_BUILTIN_GATHERDIV2DF,
28140 IX86_BUILTIN_GATHERDIV4DF,
28141 IX86_BUILTIN_GATHERSIV4SF,
28142 IX86_BUILTIN_GATHERSIV8SF,
28143 IX86_BUILTIN_GATHERDIV4SF,
28144 IX86_BUILTIN_GATHERDIV8SF,
28145 IX86_BUILTIN_GATHERSIV2DI,
28146 IX86_BUILTIN_GATHERSIV4DI,
28147 IX86_BUILTIN_GATHERDIV2DI,
28148 IX86_BUILTIN_GATHERDIV4DI,
28149 IX86_BUILTIN_GATHERSIV4SI,
28150 IX86_BUILTIN_GATHERSIV8SI,
28151 IX86_BUILTIN_GATHERDIV4SI,
28152 IX86_BUILTIN_GATHERDIV8SI,
28154 /* AVX512F */
28155 IX86_BUILTIN_ADDPD512,
28156 IX86_BUILTIN_ADDPS512,
28157 IX86_BUILTIN_ADDSD_ROUND,
28158 IX86_BUILTIN_ADDSS_ROUND,
28159 IX86_BUILTIN_ALIGND512,
28160 IX86_BUILTIN_ALIGNQ512,
28161 IX86_BUILTIN_BLENDMD512,
28162 IX86_BUILTIN_BLENDMPD512,
28163 IX86_BUILTIN_BLENDMPS512,
28164 IX86_BUILTIN_BLENDMQ512,
28165 IX86_BUILTIN_BROADCASTF32X4_512,
28166 IX86_BUILTIN_BROADCASTF64X4_512,
28167 IX86_BUILTIN_BROADCASTI32X4_512,
28168 IX86_BUILTIN_BROADCASTI64X4_512,
28169 IX86_BUILTIN_BROADCASTSD512,
28170 IX86_BUILTIN_BROADCASTSS512,
28171 IX86_BUILTIN_CMPD512,
28172 IX86_BUILTIN_CMPPD512,
28173 IX86_BUILTIN_CMPPS512,
28174 IX86_BUILTIN_CMPQ512,
28175 IX86_BUILTIN_CMPSD_MASK,
28176 IX86_BUILTIN_CMPSS_MASK,
28177 IX86_BUILTIN_COMIDF,
28178 IX86_BUILTIN_COMISF,
28179 IX86_BUILTIN_COMPRESSPD512,
28180 IX86_BUILTIN_COMPRESSPDSTORE512,
28181 IX86_BUILTIN_COMPRESSPS512,
28182 IX86_BUILTIN_COMPRESSPSSTORE512,
28183 IX86_BUILTIN_CVTDQ2PD512,
28184 IX86_BUILTIN_CVTDQ2PS512,
28185 IX86_BUILTIN_CVTPD2DQ512,
28186 IX86_BUILTIN_CVTPD2PS512,
28187 IX86_BUILTIN_CVTPD2UDQ512,
28188 IX86_BUILTIN_CVTPH2PS512,
28189 IX86_BUILTIN_CVTPS2DQ512,
28190 IX86_BUILTIN_CVTPS2PD512,
28191 IX86_BUILTIN_CVTPS2PH512,
28192 IX86_BUILTIN_CVTPS2UDQ512,
28193 IX86_BUILTIN_CVTSD2SS_ROUND,
28194 IX86_BUILTIN_CVTSI2SD64,
28195 IX86_BUILTIN_CVTSI2SS32,
28196 IX86_BUILTIN_CVTSI2SS64,
28197 IX86_BUILTIN_CVTSS2SD_ROUND,
28198 IX86_BUILTIN_CVTTPD2DQ512,
28199 IX86_BUILTIN_CVTTPD2UDQ512,
28200 IX86_BUILTIN_CVTTPS2DQ512,
28201 IX86_BUILTIN_CVTTPS2UDQ512,
28202 IX86_BUILTIN_CVTUDQ2PD512,
28203 IX86_BUILTIN_CVTUDQ2PS512,
28204 IX86_BUILTIN_CVTUSI2SD32,
28205 IX86_BUILTIN_CVTUSI2SD64,
28206 IX86_BUILTIN_CVTUSI2SS32,
28207 IX86_BUILTIN_CVTUSI2SS64,
28208 IX86_BUILTIN_DIVPD512,
28209 IX86_BUILTIN_DIVPS512,
28210 IX86_BUILTIN_DIVSD_ROUND,
28211 IX86_BUILTIN_DIVSS_ROUND,
28212 IX86_BUILTIN_EXPANDPD512,
28213 IX86_BUILTIN_EXPANDPD512Z,
28214 IX86_BUILTIN_EXPANDPDLOAD512,
28215 IX86_BUILTIN_EXPANDPDLOAD512Z,
28216 IX86_BUILTIN_EXPANDPS512,
28217 IX86_BUILTIN_EXPANDPS512Z,
28218 IX86_BUILTIN_EXPANDPSLOAD512,
28219 IX86_BUILTIN_EXPANDPSLOAD512Z,
28220 IX86_BUILTIN_EXTRACTF32X4,
28221 IX86_BUILTIN_EXTRACTF64X4,
28222 IX86_BUILTIN_EXTRACTI32X4,
28223 IX86_BUILTIN_EXTRACTI64X4,
28224 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28225 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28226 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28227 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28228 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28229 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28230 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28231 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28232 IX86_BUILTIN_GETEXPPD512,
28233 IX86_BUILTIN_GETEXPPS512,
28234 IX86_BUILTIN_GETEXPSD128,
28235 IX86_BUILTIN_GETEXPSS128,
28236 IX86_BUILTIN_GETMANTPD512,
28237 IX86_BUILTIN_GETMANTPS512,
28238 IX86_BUILTIN_GETMANTSD128,
28239 IX86_BUILTIN_GETMANTSS128,
28240 IX86_BUILTIN_INSERTF32X4,
28241 IX86_BUILTIN_INSERTF64X4,
28242 IX86_BUILTIN_INSERTI32X4,
28243 IX86_BUILTIN_INSERTI64X4,
28244 IX86_BUILTIN_LOADAPD512,
28245 IX86_BUILTIN_LOADAPS512,
28246 IX86_BUILTIN_LOADDQUDI512,
28247 IX86_BUILTIN_LOADDQUSI512,
28248 IX86_BUILTIN_LOADUPD512,
28249 IX86_BUILTIN_LOADUPS512,
28250 IX86_BUILTIN_MAXPD512,
28251 IX86_BUILTIN_MAXPS512,
28252 IX86_BUILTIN_MAXSD_ROUND,
28253 IX86_BUILTIN_MAXSS_ROUND,
28254 IX86_BUILTIN_MINPD512,
28255 IX86_BUILTIN_MINPS512,
28256 IX86_BUILTIN_MINSD_ROUND,
28257 IX86_BUILTIN_MINSS_ROUND,
28258 IX86_BUILTIN_MOVAPD512,
28259 IX86_BUILTIN_MOVAPS512,
28260 IX86_BUILTIN_MOVDDUP512,
28261 IX86_BUILTIN_MOVDQA32LOAD512,
28262 IX86_BUILTIN_MOVDQA32STORE512,
28263 IX86_BUILTIN_MOVDQA32_512,
28264 IX86_BUILTIN_MOVDQA64LOAD512,
28265 IX86_BUILTIN_MOVDQA64STORE512,
28266 IX86_BUILTIN_MOVDQA64_512,
28267 IX86_BUILTIN_MOVNTDQ512,
28268 IX86_BUILTIN_MOVNTDQA512,
28269 IX86_BUILTIN_MOVNTPD512,
28270 IX86_BUILTIN_MOVNTPS512,
28271 IX86_BUILTIN_MOVSHDUP512,
28272 IX86_BUILTIN_MOVSLDUP512,
28273 IX86_BUILTIN_MULPD512,
28274 IX86_BUILTIN_MULPS512,
28275 IX86_BUILTIN_MULSD_ROUND,
28276 IX86_BUILTIN_MULSS_ROUND,
28277 IX86_BUILTIN_PABSD512,
28278 IX86_BUILTIN_PABSQ512,
28279 IX86_BUILTIN_PADDD512,
28280 IX86_BUILTIN_PADDQ512,
28281 IX86_BUILTIN_PANDD512,
28282 IX86_BUILTIN_PANDND512,
28283 IX86_BUILTIN_PANDNQ512,
28284 IX86_BUILTIN_PANDQ512,
28285 IX86_BUILTIN_PBROADCASTD512,
28286 IX86_BUILTIN_PBROADCASTD512_GPR,
28287 IX86_BUILTIN_PBROADCASTMB512,
28288 IX86_BUILTIN_PBROADCASTMW512,
28289 IX86_BUILTIN_PBROADCASTQ512,
28290 IX86_BUILTIN_PBROADCASTQ512_GPR,
28291 IX86_BUILTIN_PBROADCASTQ512_MEM,
28292 IX86_BUILTIN_PCMPEQD512_MASK,
28293 IX86_BUILTIN_PCMPEQQ512_MASK,
28294 IX86_BUILTIN_PCMPGTD512_MASK,
28295 IX86_BUILTIN_PCMPGTQ512_MASK,
28296 IX86_BUILTIN_PCOMPRESSD512,
28297 IX86_BUILTIN_PCOMPRESSDSTORE512,
28298 IX86_BUILTIN_PCOMPRESSQ512,
28299 IX86_BUILTIN_PCOMPRESSQSTORE512,
28300 IX86_BUILTIN_PEXPANDD512,
28301 IX86_BUILTIN_PEXPANDD512Z,
28302 IX86_BUILTIN_PEXPANDDLOAD512,
28303 IX86_BUILTIN_PEXPANDDLOAD512Z,
28304 IX86_BUILTIN_PEXPANDQ512,
28305 IX86_BUILTIN_PEXPANDQ512Z,
28306 IX86_BUILTIN_PEXPANDQLOAD512,
28307 IX86_BUILTIN_PEXPANDQLOAD512Z,
28308 IX86_BUILTIN_PMAXSD512,
28309 IX86_BUILTIN_PMAXSQ512,
28310 IX86_BUILTIN_PMAXUD512,
28311 IX86_BUILTIN_PMAXUQ512,
28312 IX86_BUILTIN_PMINSD512,
28313 IX86_BUILTIN_PMINSQ512,
28314 IX86_BUILTIN_PMINUD512,
28315 IX86_BUILTIN_PMINUQ512,
28316 IX86_BUILTIN_PMOVDB512,
28317 IX86_BUILTIN_PMOVDB512_MEM,
28318 IX86_BUILTIN_PMOVDW512,
28319 IX86_BUILTIN_PMOVDW512_MEM,
28320 IX86_BUILTIN_PMOVQB512,
28321 IX86_BUILTIN_PMOVQB512_MEM,
28322 IX86_BUILTIN_PMOVQD512,
28323 IX86_BUILTIN_PMOVQD512_MEM,
28324 IX86_BUILTIN_PMOVQW512,
28325 IX86_BUILTIN_PMOVQW512_MEM,
28326 IX86_BUILTIN_PMOVSDB512,
28327 IX86_BUILTIN_PMOVSDB512_MEM,
28328 IX86_BUILTIN_PMOVSDW512,
28329 IX86_BUILTIN_PMOVSDW512_MEM,
28330 IX86_BUILTIN_PMOVSQB512,
28331 IX86_BUILTIN_PMOVSQB512_MEM,
28332 IX86_BUILTIN_PMOVSQD512,
28333 IX86_BUILTIN_PMOVSQD512_MEM,
28334 IX86_BUILTIN_PMOVSQW512,
28335 IX86_BUILTIN_PMOVSQW512_MEM,
28336 IX86_BUILTIN_PMOVSXBD512,
28337 IX86_BUILTIN_PMOVSXBQ512,
28338 IX86_BUILTIN_PMOVSXDQ512,
28339 IX86_BUILTIN_PMOVSXWD512,
28340 IX86_BUILTIN_PMOVSXWQ512,
28341 IX86_BUILTIN_PMOVUSDB512,
28342 IX86_BUILTIN_PMOVUSDB512_MEM,
28343 IX86_BUILTIN_PMOVUSDW512,
28344 IX86_BUILTIN_PMOVUSDW512_MEM,
28345 IX86_BUILTIN_PMOVUSQB512,
28346 IX86_BUILTIN_PMOVUSQB512_MEM,
28347 IX86_BUILTIN_PMOVUSQD512,
28348 IX86_BUILTIN_PMOVUSQD512_MEM,
28349 IX86_BUILTIN_PMOVUSQW512,
28350 IX86_BUILTIN_PMOVUSQW512_MEM,
28351 IX86_BUILTIN_PMOVZXBD512,
28352 IX86_BUILTIN_PMOVZXBQ512,
28353 IX86_BUILTIN_PMOVZXDQ512,
28354 IX86_BUILTIN_PMOVZXWD512,
28355 IX86_BUILTIN_PMOVZXWQ512,
28356 IX86_BUILTIN_PMULDQ512,
28357 IX86_BUILTIN_PMULLD512,
28358 IX86_BUILTIN_PMULUDQ512,
28359 IX86_BUILTIN_PORD512,
28360 IX86_BUILTIN_PORQ512,
28361 IX86_BUILTIN_PROLD512,
28362 IX86_BUILTIN_PROLQ512,
28363 IX86_BUILTIN_PROLVD512,
28364 IX86_BUILTIN_PROLVQ512,
28365 IX86_BUILTIN_PRORD512,
28366 IX86_BUILTIN_PRORQ512,
28367 IX86_BUILTIN_PRORVD512,
28368 IX86_BUILTIN_PRORVQ512,
28369 IX86_BUILTIN_PSHUFD512,
28370 IX86_BUILTIN_PSLLD512,
28371 IX86_BUILTIN_PSLLDI512,
28372 IX86_BUILTIN_PSLLQ512,
28373 IX86_BUILTIN_PSLLQI512,
28374 IX86_BUILTIN_PSLLVV16SI,
28375 IX86_BUILTIN_PSLLVV8DI,
28376 IX86_BUILTIN_PSRAD512,
28377 IX86_BUILTIN_PSRADI512,
28378 IX86_BUILTIN_PSRAQ512,
28379 IX86_BUILTIN_PSRAQI512,
28380 IX86_BUILTIN_PSRAVV16SI,
28381 IX86_BUILTIN_PSRAVV8DI,
28382 IX86_BUILTIN_PSRLD512,
28383 IX86_BUILTIN_PSRLDI512,
28384 IX86_BUILTIN_PSRLQ512,
28385 IX86_BUILTIN_PSRLQI512,
28386 IX86_BUILTIN_PSRLVV16SI,
28387 IX86_BUILTIN_PSRLVV8DI,
28388 IX86_BUILTIN_PSUBD512,
28389 IX86_BUILTIN_PSUBQ512,
28390 IX86_BUILTIN_PTESTMD512,
28391 IX86_BUILTIN_PTESTMQ512,
28392 IX86_BUILTIN_PTESTNMD512,
28393 IX86_BUILTIN_PTESTNMQ512,
28394 IX86_BUILTIN_PUNPCKHDQ512,
28395 IX86_BUILTIN_PUNPCKHQDQ512,
28396 IX86_BUILTIN_PUNPCKLDQ512,
28397 IX86_BUILTIN_PUNPCKLQDQ512,
28398 IX86_BUILTIN_PXORD512,
28399 IX86_BUILTIN_PXORQ512,
28400 IX86_BUILTIN_RCP14PD512,
28401 IX86_BUILTIN_RCP14PS512,
28402 IX86_BUILTIN_RCP14SD,
28403 IX86_BUILTIN_RCP14SS,
28404 IX86_BUILTIN_RNDSCALEPD,
28405 IX86_BUILTIN_RNDSCALEPS,
28406 IX86_BUILTIN_RNDSCALESD,
28407 IX86_BUILTIN_RNDSCALESS,
28408 IX86_BUILTIN_RSQRT14PD512,
28409 IX86_BUILTIN_RSQRT14PS512,
28410 IX86_BUILTIN_RSQRT14SD,
28411 IX86_BUILTIN_RSQRT14SS,
28412 IX86_BUILTIN_SCALEFPD512,
28413 IX86_BUILTIN_SCALEFPS512,
28414 IX86_BUILTIN_SCALEFSD,
28415 IX86_BUILTIN_SCALEFSS,
28416 IX86_BUILTIN_SHUFPD512,
28417 IX86_BUILTIN_SHUFPS512,
28418 IX86_BUILTIN_SHUF_F32x4,
28419 IX86_BUILTIN_SHUF_F64x2,
28420 IX86_BUILTIN_SHUF_I32x4,
28421 IX86_BUILTIN_SHUF_I64x2,
28422 IX86_BUILTIN_SQRTPD512,
28423 IX86_BUILTIN_SQRTPD512_MASK,
28424 IX86_BUILTIN_SQRTPS512_MASK,
28425 IX86_BUILTIN_SQRTPS_NR512,
28426 IX86_BUILTIN_SQRTSD_ROUND,
28427 IX86_BUILTIN_SQRTSS_ROUND,
28428 IX86_BUILTIN_STOREAPD512,
28429 IX86_BUILTIN_STOREAPS512,
28430 IX86_BUILTIN_STOREDQUDI512,
28431 IX86_BUILTIN_STOREDQUSI512,
28432 IX86_BUILTIN_STOREUPD512,
28433 IX86_BUILTIN_STOREUPS512,
28434 IX86_BUILTIN_SUBPD512,
28435 IX86_BUILTIN_SUBPS512,
28436 IX86_BUILTIN_SUBSD_ROUND,
28437 IX86_BUILTIN_SUBSS_ROUND,
28438 IX86_BUILTIN_UCMPD512,
28439 IX86_BUILTIN_UCMPQ512,
28440 IX86_BUILTIN_UNPCKHPD512,
28441 IX86_BUILTIN_UNPCKHPS512,
28442 IX86_BUILTIN_UNPCKLPD512,
28443 IX86_BUILTIN_UNPCKLPS512,
28444 IX86_BUILTIN_VCVTSD2SI32,
28445 IX86_BUILTIN_VCVTSD2SI64,
28446 IX86_BUILTIN_VCVTSD2USI32,
28447 IX86_BUILTIN_VCVTSD2USI64,
28448 IX86_BUILTIN_VCVTSS2SI32,
28449 IX86_BUILTIN_VCVTSS2SI64,
28450 IX86_BUILTIN_VCVTSS2USI32,
28451 IX86_BUILTIN_VCVTSS2USI64,
28452 IX86_BUILTIN_VCVTTSD2SI32,
28453 IX86_BUILTIN_VCVTTSD2SI64,
28454 IX86_BUILTIN_VCVTTSD2USI32,
28455 IX86_BUILTIN_VCVTTSD2USI64,
28456 IX86_BUILTIN_VCVTTSS2SI32,
28457 IX86_BUILTIN_VCVTTSS2SI64,
28458 IX86_BUILTIN_VCVTTSS2USI32,
28459 IX86_BUILTIN_VCVTTSS2USI64,
28460 IX86_BUILTIN_VFMADDPD512_MASK,
28461 IX86_BUILTIN_VFMADDPD512_MASK3,
28462 IX86_BUILTIN_VFMADDPD512_MASKZ,
28463 IX86_BUILTIN_VFMADDPS512_MASK,
28464 IX86_BUILTIN_VFMADDPS512_MASK3,
28465 IX86_BUILTIN_VFMADDPS512_MASKZ,
28466 IX86_BUILTIN_VFMADDSD3_ROUND,
28467 IX86_BUILTIN_VFMADDSS3_ROUND,
28468 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28469 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28470 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28471 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28472 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28473 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28474 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28475 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28476 IX86_BUILTIN_VFMSUBPD512_MASK3,
28477 IX86_BUILTIN_VFMSUBPS512_MASK3,
28478 IX86_BUILTIN_VFMSUBSD3_MASK3,
28479 IX86_BUILTIN_VFMSUBSS3_MASK3,
28480 IX86_BUILTIN_VFNMADDPD512_MASK,
28481 IX86_BUILTIN_VFNMADDPS512_MASK,
28482 IX86_BUILTIN_VFNMSUBPD512_MASK,
28483 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28484 IX86_BUILTIN_VFNMSUBPS512_MASK,
28485 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28486 IX86_BUILTIN_VPCLZCNTD512,
28487 IX86_BUILTIN_VPCLZCNTQ512,
28488 IX86_BUILTIN_VPCONFLICTD512,
28489 IX86_BUILTIN_VPCONFLICTQ512,
28490 IX86_BUILTIN_VPERMDF512,
28491 IX86_BUILTIN_VPERMDI512,
28492 IX86_BUILTIN_VPERMI2VARD512,
28493 IX86_BUILTIN_VPERMI2VARPD512,
28494 IX86_BUILTIN_VPERMI2VARPS512,
28495 IX86_BUILTIN_VPERMI2VARQ512,
28496 IX86_BUILTIN_VPERMILPD512,
28497 IX86_BUILTIN_VPERMILPS512,
28498 IX86_BUILTIN_VPERMILVARPD512,
28499 IX86_BUILTIN_VPERMILVARPS512,
28500 IX86_BUILTIN_VPERMT2VARD512,
28501 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28502 IX86_BUILTIN_VPERMT2VARPD512,
28503 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28504 IX86_BUILTIN_VPERMT2VARPS512,
28505 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28506 IX86_BUILTIN_VPERMT2VARQ512,
28507 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28508 IX86_BUILTIN_VPERMVARDF512,
28509 IX86_BUILTIN_VPERMVARDI512,
28510 IX86_BUILTIN_VPERMVARSF512,
28511 IX86_BUILTIN_VPERMVARSI512,
28512 IX86_BUILTIN_VTERNLOGD512_MASK,
28513 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28514 IX86_BUILTIN_VTERNLOGQ512_MASK,
28515 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28517 /* Mask arithmetic operations */
28518 IX86_BUILTIN_KAND16,
28519 IX86_BUILTIN_KANDN16,
28520 IX86_BUILTIN_KNOT16,
28521 IX86_BUILTIN_KOR16,
28522 IX86_BUILTIN_KORTESTC16,
28523 IX86_BUILTIN_KORTESTZ16,
28524 IX86_BUILTIN_KUNPCKBW,
28525 IX86_BUILTIN_KXNOR16,
28526 IX86_BUILTIN_KXOR16,
28527 IX86_BUILTIN_KMOV16,
28529 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28530 where all operands are 32-byte or 64-byte wide respectively. */
28531 IX86_BUILTIN_GATHERALTSIV4DF,
28532 IX86_BUILTIN_GATHERALTDIV8SF,
28533 IX86_BUILTIN_GATHERALTSIV4DI,
28534 IX86_BUILTIN_GATHERALTDIV8SI,
28535 IX86_BUILTIN_GATHER3ALTDIV16SF,
28536 IX86_BUILTIN_GATHER3ALTDIV16SI,
28537 IX86_BUILTIN_GATHER3ALTSIV8DF,
28538 IX86_BUILTIN_GATHER3ALTSIV8DI,
28539 IX86_BUILTIN_GATHER3DIV16SF,
28540 IX86_BUILTIN_GATHER3DIV16SI,
28541 IX86_BUILTIN_GATHER3DIV8DF,
28542 IX86_BUILTIN_GATHER3DIV8DI,
28543 IX86_BUILTIN_GATHER3SIV16SF,
28544 IX86_BUILTIN_GATHER3SIV16SI,
28545 IX86_BUILTIN_GATHER3SIV8DF,
28546 IX86_BUILTIN_GATHER3SIV8DI,
28547 IX86_BUILTIN_SCATTERDIV16SF,
28548 IX86_BUILTIN_SCATTERDIV16SI,
28549 IX86_BUILTIN_SCATTERDIV8DF,
28550 IX86_BUILTIN_SCATTERDIV8DI,
28551 IX86_BUILTIN_SCATTERSIV16SF,
28552 IX86_BUILTIN_SCATTERSIV16SI,
28553 IX86_BUILTIN_SCATTERSIV8DF,
28554 IX86_BUILTIN_SCATTERSIV8DI,
28556 /* AVX512PF */
28557 IX86_BUILTIN_GATHERPFQPD,
28558 IX86_BUILTIN_GATHERPFDPS,
28559 IX86_BUILTIN_GATHERPFDPD,
28560 IX86_BUILTIN_GATHERPFQPS,
28561 IX86_BUILTIN_SCATTERPFDPD,
28562 IX86_BUILTIN_SCATTERPFDPS,
28563 IX86_BUILTIN_SCATTERPFQPD,
28564 IX86_BUILTIN_SCATTERPFQPS,
28566 /* AVX-512ER */
28567 IX86_BUILTIN_EXP2PD_MASK,
28568 IX86_BUILTIN_EXP2PS_MASK,
28569 IX86_BUILTIN_EXP2PS,
28570 IX86_BUILTIN_RCP28PD,
28571 IX86_BUILTIN_RCP28PS,
28572 IX86_BUILTIN_RCP28SD,
28573 IX86_BUILTIN_RCP28SS,
28574 IX86_BUILTIN_RSQRT28PD,
28575 IX86_BUILTIN_RSQRT28PS,
28576 IX86_BUILTIN_RSQRT28SD,
28577 IX86_BUILTIN_RSQRT28SS,
28579 /* SHA builtins. */
28580 IX86_BUILTIN_SHA1MSG1,
28581 IX86_BUILTIN_SHA1MSG2,
28582 IX86_BUILTIN_SHA1NEXTE,
28583 IX86_BUILTIN_SHA1RNDS4,
28584 IX86_BUILTIN_SHA256MSG1,
28585 IX86_BUILTIN_SHA256MSG2,
28586 IX86_BUILTIN_SHA256RNDS2,
28588 /* TFmode support builtins. */
28589 IX86_BUILTIN_INFQ,
28590 IX86_BUILTIN_HUGE_VALQ,
28591 IX86_BUILTIN_FABSQ,
28592 IX86_BUILTIN_COPYSIGNQ,
28594 /* Vectorizer support builtins. */
28595 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28596 IX86_BUILTIN_CPYSGNPS,
28597 IX86_BUILTIN_CPYSGNPD,
28598 IX86_BUILTIN_CPYSGNPS256,
28599 IX86_BUILTIN_CPYSGNPS512,
28600 IX86_BUILTIN_CPYSGNPD256,
28601 IX86_BUILTIN_CPYSGNPD512,
28602 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28603 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28606 /* FMA4 instructions. */
28607 IX86_BUILTIN_VFMADDSS,
28608 IX86_BUILTIN_VFMADDSD,
28609 IX86_BUILTIN_VFMADDPS,
28610 IX86_BUILTIN_VFMADDPD,
28611 IX86_BUILTIN_VFMADDPS256,
28612 IX86_BUILTIN_VFMADDPD256,
28613 IX86_BUILTIN_VFMADDSUBPS,
28614 IX86_BUILTIN_VFMADDSUBPD,
28615 IX86_BUILTIN_VFMADDSUBPS256,
28616 IX86_BUILTIN_VFMADDSUBPD256,
28618 /* FMA3 instructions. */
28619 IX86_BUILTIN_VFMADDSS3,
28620 IX86_BUILTIN_VFMADDSD3,
28622 /* XOP instructions. */
28623 IX86_BUILTIN_VPCMOV,
28624 IX86_BUILTIN_VPCMOV_V2DI,
28625 IX86_BUILTIN_VPCMOV_V4SI,
28626 IX86_BUILTIN_VPCMOV_V8HI,
28627 IX86_BUILTIN_VPCMOV_V16QI,
28628 IX86_BUILTIN_VPCMOV_V4SF,
28629 IX86_BUILTIN_VPCMOV_V2DF,
28630 IX86_BUILTIN_VPCMOV256,
28631 IX86_BUILTIN_VPCMOV_V4DI256,
28632 IX86_BUILTIN_VPCMOV_V8SI256,
28633 IX86_BUILTIN_VPCMOV_V16HI256,
28634 IX86_BUILTIN_VPCMOV_V32QI256,
28635 IX86_BUILTIN_VPCMOV_V8SF256,
28636 IX86_BUILTIN_VPCMOV_V4DF256,
28638 IX86_BUILTIN_VPPERM,
28640 IX86_BUILTIN_VPMACSSWW,
28641 IX86_BUILTIN_VPMACSWW,
28642 IX86_BUILTIN_VPMACSSWD,
28643 IX86_BUILTIN_VPMACSWD,
28644 IX86_BUILTIN_VPMACSSDD,
28645 IX86_BUILTIN_VPMACSDD,
28646 IX86_BUILTIN_VPMACSSDQL,
28647 IX86_BUILTIN_VPMACSSDQH,
28648 IX86_BUILTIN_VPMACSDQL,
28649 IX86_BUILTIN_VPMACSDQH,
28650 IX86_BUILTIN_VPMADCSSWD,
28651 IX86_BUILTIN_VPMADCSWD,
28653 IX86_BUILTIN_VPHADDBW,
28654 IX86_BUILTIN_VPHADDBD,
28655 IX86_BUILTIN_VPHADDBQ,
28656 IX86_BUILTIN_VPHADDWD,
28657 IX86_BUILTIN_VPHADDWQ,
28658 IX86_BUILTIN_VPHADDDQ,
28659 IX86_BUILTIN_VPHADDUBW,
28660 IX86_BUILTIN_VPHADDUBD,
28661 IX86_BUILTIN_VPHADDUBQ,
28662 IX86_BUILTIN_VPHADDUWD,
28663 IX86_BUILTIN_VPHADDUWQ,
28664 IX86_BUILTIN_VPHADDUDQ,
28665 IX86_BUILTIN_VPHSUBBW,
28666 IX86_BUILTIN_VPHSUBWD,
28667 IX86_BUILTIN_VPHSUBDQ,
28669 IX86_BUILTIN_VPROTB,
28670 IX86_BUILTIN_VPROTW,
28671 IX86_BUILTIN_VPROTD,
28672 IX86_BUILTIN_VPROTQ,
28673 IX86_BUILTIN_VPROTB_IMM,
28674 IX86_BUILTIN_VPROTW_IMM,
28675 IX86_BUILTIN_VPROTD_IMM,
28676 IX86_BUILTIN_VPROTQ_IMM,
28678 IX86_BUILTIN_VPSHLB,
28679 IX86_BUILTIN_VPSHLW,
28680 IX86_BUILTIN_VPSHLD,
28681 IX86_BUILTIN_VPSHLQ,
28682 IX86_BUILTIN_VPSHAB,
28683 IX86_BUILTIN_VPSHAW,
28684 IX86_BUILTIN_VPSHAD,
28685 IX86_BUILTIN_VPSHAQ,
28687 IX86_BUILTIN_VFRCZSS,
28688 IX86_BUILTIN_VFRCZSD,
28689 IX86_BUILTIN_VFRCZPS,
28690 IX86_BUILTIN_VFRCZPD,
28691 IX86_BUILTIN_VFRCZPS256,
28692 IX86_BUILTIN_VFRCZPD256,
28694 IX86_BUILTIN_VPCOMEQUB,
28695 IX86_BUILTIN_VPCOMNEUB,
28696 IX86_BUILTIN_VPCOMLTUB,
28697 IX86_BUILTIN_VPCOMLEUB,
28698 IX86_BUILTIN_VPCOMGTUB,
28699 IX86_BUILTIN_VPCOMGEUB,
28700 IX86_BUILTIN_VPCOMFALSEUB,
28701 IX86_BUILTIN_VPCOMTRUEUB,
28703 IX86_BUILTIN_VPCOMEQUW,
28704 IX86_BUILTIN_VPCOMNEUW,
28705 IX86_BUILTIN_VPCOMLTUW,
28706 IX86_BUILTIN_VPCOMLEUW,
28707 IX86_BUILTIN_VPCOMGTUW,
28708 IX86_BUILTIN_VPCOMGEUW,
28709 IX86_BUILTIN_VPCOMFALSEUW,
28710 IX86_BUILTIN_VPCOMTRUEUW,
28712 IX86_BUILTIN_VPCOMEQUD,
28713 IX86_BUILTIN_VPCOMNEUD,
28714 IX86_BUILTIN_VPCOMLTUD,
28715 IX86_BUILTIN_VPCOMLEUD,
28716 IX86_BUILTIN_VPCOMGTUD,
28717 IX86_BUILTIN_VPCOMGEUD,
28718 IX86_BUILTIN_VPCOMFALSEUD,
28719 IX86_BUILTIN_VPCOMTRUEUD,
28721 IX86_BUILTIN_VPCOMEQUQ,
28722 IX86_BUILTIN_VPCOMNEUQ,
28723 IX86_BUILTIN_VPCOMLTUQ,
28724 IX86_BUILTIN_VPCOMLEUQ,
28725 IX86_BUILTIN_VPCOMGTUQ,
28726 IX86_BUILTIN_VPCOMGEUQ,
28727 IX86_BUILTIN_VPCOMFALSEUQ,
28728 IX86_BUILTIN_VPCOMTRUEUQ,
28730 IX86_BUILTIN_VPCOMEQB,
28731 IX86_BUILTIN_VPCOMNEB,
28732 IX86_BUILTIN_VPCOMLTB,
28733 IX86_BUILTIN_VPCOMLEB,
28734 IX86_BUILTIN_VPCOMGTB,
28735 IX86_BUILTIN_VPCOMGEB,
28736 IX86_BUILTIN_VPCOMFALSEB,
28737 IX86_BUILTIN_VPCOMTRUEB,
28739 IX86_BUILTIN_VPCOMEQW,
28740 IX86_BUILTIN_VPCOMNEW,
28741 IX86_BUILTIN_VPCOMLTW,
28742 IX86_BUILTIN_VPCOMLEW,
28743 IX86_BUILTIN_VPCOMGTW,
28744 IX86_BUILTIN_VPCOMGEW,
28745 IX86_BUILTIN_VPCOMFALSEW,
28746 IX86_BUILTIN_VPCOMTRUEW,
28748 IX86_BUILTIN_VPCOMEQD,
28749 IX86_BUILTIN_VPCOMNED,
28750 IX86_BUILTIN_VPCOMLTD,
28751 IX86_BUILTIN_VPCOMLED,
28752 IX86_BUILTIN_VPCOMGTD,
28753 IX86_BUILTIN_VPCOMGED,
28754 IX86_BUILTIN_VPCOMFALSED,
28755 IX86_BUILTIN_VPCOMTRUED,
28757 IX86_BUILTIN_VPCOMEQQ,
28758 IX86_BUILTIN_VPCOMNEQ,
28759 IX86_BUILTIN_VPCOMLTQ,
28760 IX86_BUILTIN_VPCOMLEQ,
28761 IX86_BUILTIN_VPCOMGTQ,
28762 IX86_BUILTIN_VPCOMGEQ,
28763 IX86_BUILTIN_VPCOMFALSEQ,
28764 IX86_BUILTIN_VPCOMTRUEQ,
28766 /* LWP instructions. */
28767 IX86_BUILTIN_LLWPCB,
28768 IX86_BUILTIN_SLWPCB,
28769 IX86_BUILTIN_LWPVAL32,
28770 IX86_BUILTIN_LWPVAL64,
28771 IX86_BUILTIN_LWPINS32,
28772 IX86_BUILTIN_LWPINS64,
28774 IX86_BUILTIN_CLZS,
28776 /* RTM */
28777 IX86_BUILTIN_XBEGIN,
28778 IX86_BUILTIN_XEND,
28779 IX86_BUILTIN_XABORT,
28780 IX86_BUILTIN_XTEST,
28782 /* BMI instructions. */
28783 IX86_BUILTIN_BEXTR32,
28784 IX86_BUILTIN_BEXTR64,
28785 IX86_BUILTIN_CTZS,
28787 /* TBM instructions. */
28788 IX86_BUILTIN_BEXTRI32,
28789 IX86_BUILTIN_BEXTRI64,
28791 /* BMI2 instructions. */
28792 IX86_BUILTIN_BZHI32,
28793 IX86_BUILTIN_BZHI64,
28794 IX86_BUILTIN_PDEP32,
28795 IX86_BUILTIN_PDEP64,
28796 IX86_BUILTIN_PEXT32,
28797 IX86_BUILTIN_PEXT64,
28799 /* ADX instructions. */
28800 IX86_BUILTIN_ADDCARRYX32,
28801 IX86_BUILTIN_ADDCARRYX64,
28803 /* FSGSBASE instructions. */
28804 IX86_BUILTIN_RDFSBASE32,
28805 IX86_BUILTIN_RDFSBASE64,
28806 IX86_BUILTIN_RDGSBASE32,
28807 IX86_BUILTIN_RDGSBASE64,
28808 IX86_BUILTIN_WRFSBASE32,
28809 IX86_BUILTIN_WRFSBASE64,
28810 IX86_BUILTIN_WRGSBASE32,
28811 IX86_BUILTIN_WRGSBASE64,
28813 /* RDRND instructions. */
28814 IX86_BUILTIN_RDRAND16_STEP,
28815 IX86_BUILTIN_RDRAND32_STEP,
28816 IX86_BUILTIN_RDRAND64_STEP,
28818 /* RDSEED instructions. */
28819 IX86_BUILTIN_RDSEED16_STEP,
28820 IX86_BUILTIN_RDSEED32_STEP,
28821 IX86_BUILTIN_RDSEED64_STEP,
28823 /* F16C instructions. */
28824 IX86_BUILTIN_CVTPH2PS,
28825 IX86_BUILTIN_CVTPH2PS256,
28826 IX86_BUILTIN_CVTPS2PH,
28827 IX86_BUILTIN_CVTPS2PH256,
28829 /* CFString built-in for darwin */
28830 IX86_BUILTIN_CFSTRING,
28832 /* Builtins to get CPU type and supported features. */
28833 IX86_BUILTIN_CPU_INIT,
28834 IX86_BUILTIN_CPU_IS,
28835 IX86_BUILTIN_CPU_SUPPORTS,
28837 /* Read/write FLAGS register built-ins. */
28838 IX86_BUILTIN_READ_FLAGS,
28839 IX86_BUILTIN_WRITE_FLAGS,
28841 IX86_BUILTIN_MAX
28842 };
28844 /* Table for the ix86 builtin decls. */
28847 /* Table of all of the builtin functions that are possible with different ISA's
28848 but are waiting to be built until a function is declared to use that
28849 ISA. */
28856 };
28861 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28862 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28863 function decl in the ix86_builtins array. Returns the function decl or
28864 NULL_TREE, if the builtin was not added.
28866 If the front end has a special hook for builtin functions, delay adding
28867 builtin functions that aren't in the current ISA until the ISA is changed
28868 with function specific optimization. Doing so, can save about 300K for the
28869 default compiler. When the builtin is expanded, check at that time whether
28870 it is valid.
28872 If the front end doesn't have a special hook, record all builtins, even if
28873 it isn't an instruction set in the current ISA in case the user uses
28874 function specific options for a different ISA, so that we don't get scope
28875 errors if a builtin is added in the middle of a function scope. */
28881 {
28885 {
28894 {
28900 }
28901 else
28902 {
28908 }
28909 }
28912 }
28914 /* Like def_builtin, but also marks the function decl "const". */
28919 {
28923 else
28927 }
28929 /* Add any new builtin functions for a given ISA that may not have been
28930 declared. This saves a bit of space compared to adding all of the
28931 declarations to the tree, even if we didn't use them. */
28933 static void
28935 {
28939 {
28942 {
28945 /* Don't define the builtin again. */
28951 NULL_TREE);
28956 }
28957 }
28958 }
28960 /* Bits for builtin_description.flag. */
28962 /* Set when we don't support the comparison natively, and should
28963 swap_comparison in order to support it. */
28964 #define BUILTIN_DESC_SWAP_OPERANDS 1
28966 struct builtin_description
28967 {
28974 };
28977 {
28978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28986 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28987 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
29000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
29001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
29002 };
29005 {
29006 /* SSE4.2 */
29007 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
29008 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
29009 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
29010 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
29011 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
29012 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
29013 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
29014 };
29017 {
29018 /* SSE4.2 */
29019 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
29020 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
29021 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
29022 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
29023 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
29024 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
29025 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
29026 };
29028 /* Special builtins with variable number of arguments. */
29030 {
29031 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
29032 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
29033 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
29035 /* 80387 (for use internally for atomic compound assignment). */
29036 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
29037 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
29038 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
29039 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
29041 /* MMX */
29042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29044 /* 3DNow! */
29045 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29047 /* FXSR, XSAVE and XSAVEOPT */
29048 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29049 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29050 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29051 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29052 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29054 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29055 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29056 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29057 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29058 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29060 /* SSE */
29061 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29062 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29065 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29070 /* SSE or 3DNow!A */
29071 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29072 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29074 /* SSE2 */
29075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29082 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29089 /* SSE3 */
29090 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29092 /* SSE4.1 */
29093 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29095 /* SSE4A */
29096 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29097 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29099 /* AVX */
29100 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29101 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29103 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29104 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29105 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29109 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29112 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29114 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29115 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29117 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29118 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29121 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29123 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29124 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29130 /* AVX2 */
29131 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29132 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29133 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29134 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29135 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29136 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29137 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29138 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29139 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29141 /* AVX512F */
29142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29190 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29191 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29192 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29193 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29194 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29195 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29197 /* FSGSBASE */
29198 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29199 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29200 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29201 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29202 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29203 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29204 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29205 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29207 /* RTM */
29208 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29209 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29210 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29211 };
29213 /* Builtins with variable number of arguments. */
29215 {
29216 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29217 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29218 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29219 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29220 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29221 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29222 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29224 /* MMX */
29225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29249 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29250 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29251 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29252 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29253 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29254 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29256 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29258 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29260 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29263 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29276 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29277 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29278 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29279 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29288 /* 3DNow! */
29289 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29290 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29291 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29292 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29294 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29295 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29296 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29297 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29298 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29299 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29300 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29301 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29302 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29303 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29304 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29305 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29306 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29307 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29308 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29310 /* 3DNow!A */
29311 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29312 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29313 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29314 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29315 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29316 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29318 /* SSE */
29319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29321 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29323 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29326 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29327 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29330 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29334 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29335 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29336 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29337 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29343 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29352 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29353 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29354 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29356 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29357 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29358 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29359 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29360 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29361 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29362 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29364 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29365 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29366 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29369 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29371 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29372 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29374 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29378 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29379 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29380 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29384 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29386 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29392 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29393 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29395 /* SSE MMX or 3Dnow!A */
29396 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29397 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29398 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29400 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29401 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29402 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29403 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29405 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29406 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29408 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29410 /* SSE2 */
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29429 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29430 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29434 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29436 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29437 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29439 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29471 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29473 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29474 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29476 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29479 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29480 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29482 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29484 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29485 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29486 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29487 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29488 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29489 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29490 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29491 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29502 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29503 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29505 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29507 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29508 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29520 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29521 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29522 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29525 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29526 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29527 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29528 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29529 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29530 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29531 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29532 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29538 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29542 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29547 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29552 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29553 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29554 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29555 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29556 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29557 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29560 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29561 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29562 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29563 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29564 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29565 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29567 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29568 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29569 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29570 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29578 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29580 /* SSE2 MMX */
29581 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29582 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29584 /* SSE3 */
29585 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29586 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29588 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29589 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29590 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29591 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29592 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29593 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29595 /* SSSE3 */
29596 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29597 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29598 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29599 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29600 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29601 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29603 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29604 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29605 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29606 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29607 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29608 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29609 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29610 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29611 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29612 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29613 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29614 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29615 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29616 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29617 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29618 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29619 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29620 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29621 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29622 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29623 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29624 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29625 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29626 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29628 /* SSSE3. */
29629 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29630 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29632 /* SSE4.1 */
29633 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29634 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29635 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29636 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29637 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29638 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29639 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29640 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29641 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29642 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29645 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29646 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29647 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29648 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29649 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29650 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29651 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29652 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29653 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29654 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29655 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29656 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29658 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29659 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29660 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29661 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29662 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29663 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29664 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29665 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29666 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29667 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29668 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29669 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29671 /* SSE4.1 */
29672 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29673 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29674 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29675 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29677 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29678 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29679 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29680 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29682 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29683 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29685 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29686 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29688 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29689 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29690 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29691 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29693 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29694 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29696 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29697 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29699 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29700 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29701 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29703 /* SSE4.2 */
29704 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29705 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29706 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29707 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29708 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29710 /* SSE4A */
29711 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29712 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29713 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29714 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29716 /* AES */
29717 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29718 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29720 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29721 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29722 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29723 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29725 /* PCLMUL */
29726 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29728 /* AVX */
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29730 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29777 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29778 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29782 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29784 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29800 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29802 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29804 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29816 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29817 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29830 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29831 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29841 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29842 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29843 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29864 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29865 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29867 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29869 /* AVX2 */
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29909 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29910 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29911 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29912 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29913 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29914 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29915 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29916 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29917 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29918 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29919 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29920 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29934 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29936 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29937 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29938 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29939 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29940 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29941 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29951 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29952 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29953 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29954 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29955 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29956 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29957 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29958 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29959 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29960 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29962 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29963 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29964 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29965 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29966 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29967 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29968 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29969 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29970 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29971 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29973 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29974 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29975 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29976 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29977 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29978 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29979 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29980 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29981 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29984 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29991 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29992 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29993 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29994 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29995 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29996 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29997 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29998 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29999 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30001 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30002 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
30003 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
30004 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
30005 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
30006 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30007 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30008 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30009 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30010 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30011 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30012 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30013 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30014 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30015 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30017 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30019 /* BMI */
30020 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30021 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30022 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30024 /* TBM */
30025 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30026 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30028 /* F16C */
30029 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
30030 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
30031 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
30032 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
30034 /* BMI2 */
30035 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30036 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30037 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30038 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30039 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30040 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30042 /* AVX512F */
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30092 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30093 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30095 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30096 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30204 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30205 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30206 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30207 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30239 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30244 /* Mask arithmetic operations */
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30256 /* SHA */
30257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30264 };
30266 /* Builtins with rounding support. */
30268 {
30269 /* AVX512F */
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30289 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30291 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30298 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30300 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30320 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30322 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30326 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30350 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30352 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30354 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30356 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30358 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30360 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30362 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30364 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30378 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30380 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30390 /* AVX512ER */
30391 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30392 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30393 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30394 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30395 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30396 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30397 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30398 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30399 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30400 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30401 };
30403 /* FMA4 and XOP. */
30404 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30405 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30406 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30407 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30408 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30409 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30410 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30411 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30412 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30413 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30414 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30415 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30416 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30417 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30418 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30419 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30420 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30421 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30422 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30423 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30424 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30425 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30426 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30427 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30428 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30429 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30430 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30431 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30432 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30433 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30434 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30435 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30436 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30437 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30438 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30439 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30440 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30441 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30442 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30443 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30444 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30445 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30446 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30447 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30448 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30449 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30450 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30451 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30452 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30453 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30454 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30455 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30458 {
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30646 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30654 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30657 };
30658 \f
30659 /* TM vector builtins. */
30661 /* Reuse the existing x86-specific `struct builtin_description' cause
30662 we're lazy. Add casts to make them fit. */
30664 {
30665 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30666 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30667 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30668 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30669 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30670 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30671 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30673 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30674 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30675 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30676 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30677 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30678 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30679 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30681 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30682 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30683 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30684 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30685 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30686 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30687 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30689 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30690 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30691 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30692 };
30694 /* TM callbacks. */
30696 /* Return the builtin decl needed to load a vector of TYPE. */
30698 static tree
30700 {
30702 {
30704 {
30711 }
30712 }
30714 }
30716 /* Return the builtin decl needed to store a vector of TYPE. */
30718 static tree
30720 {
30722 {
30724 {
30731 }
30732 }
30734 }
30735 \f
30736 /* Initialize the transactional memory vector load/store builtins. */
30738 static void
30740 {
30744 tree decl;
30751 /* If there are no builtins defined, we must be compiling in a
30752 language without trans-mem support. */
30756 /* Use whatever attributes a normal TM load has. */
30760 /* Use whatever attributes a normal TM store has. */
30764 /* Use whatever attributes a normal TM log has. */
30772 {
30776 {
30784 {
30787 }
30789 {
30792 }
30793 else
30794 {
30797 }
30799 /* The builtin without the prefix for
30800 calling it directly. */
30802 attrs);
30803 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30804 set the TYPE_ATTRIBUTES. */
30808 }
30809 }
30810 }
30812 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30813 in the current target ISA to allow the user to compile particular modules
30814 with different target specific options that differ from the command line
30815 options. */
30816 static void
30818 {
30823 /* Add all special builtins with variable number of operands. */
30827 {
30833 }
30835 /* Add all builtins with variable number of operands. */
30839 {
30845 }
30847 /* Add all builtins with rounding. */
30851 {
30857 }
30859 /* pcmpestr[im] insns. */
30863 {
30866 else
30869 }
30871 /* pcmpistr[im] insns. */
30875 {
30878 else
30881 }
30883 /* comi/ucomi insns. */
30885 {
30888 else
30891 }
30893 /* SSE */
30899 /* SSE or 3DNow!A */
30902 IX86_BUILTIN_MASKMOVQ);
30904 /* SSE2 */
30913 /* SSE3. */
30919 /* AES */
30933 /* PCLMUL */
30937 /* RDRND */
30944 IX86_BUILTIN_RDRAND64_STEP);
30946 /* AVX2 */
30948 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30949 IX86_BUILTIN_GATHERSIV2DF);
30952 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30953 IX86_BUILTIN_GATHERSIV4DF);
30956 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30957 IX86_BUILTIN_GATHERDIV2DF);
30960 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30961 IX86_BUILTIN_GATHERDIV4DF);
30964 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30965 IX86_BUILTIN_GATHERSIV4SF);
30968 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30969 IX86_BUILTIN_GATHERSIV8SF);
30972 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30973 IX86_BUILTIN_GATHERDIV4SF);
30976 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30977 IX86_BUILTIN_GATHERDIV8SF);
30980 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30981 IX86_BUILTIN_GATHERSIV2DI);
30984 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30985 IX86_BUILTIN_GATHERSIV4DI);
30988 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30989 IX86_BUILTIN_GATHERDIV2DI);
30992 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30993 IX86_BUILTIN_GATHERDIV4DI);
30996 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30997 IX86_BUILTIN_GATHERSIV4SI);
31000 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
31001 IX86_BUILTIN_GATHERSIV8SI);
31004 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
31005 IX86_BUILTIN_GATHERDIV4SI);
31008 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
31009 IX86_BUILTIN_GATHERDIV8SI);
31012 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
31013 IX86_BUILTIN_GATHERALTSIV4DF);
31016 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
31017 IX86_BUILTIN_GATHERALTDIV8SF);
31020 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
31021 IX86_BUILTIN_GATHERALTSIV4DI);
31024 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
31025 IX86_BUILTIN_GATHERALTDIV8SI);
31027 /* AVX512F */
31029 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
31030 IX86_BUILTIN_GATHER3SIV16SF);
31033 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
31034 IX86_BUILTIN_GATHER3SIV8DF);
31037 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
31038 IX86_BUILTIN_GATHER3DIV16SF);
31041 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31042 IX86_BUILTIN_GATHER3DIV8DF);
31045 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31046 IX86_BUILTIN_GATHER3SIV16SI);
31049 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31050 IX86_BUILTIN_GATHER3SIV8DI);
31053 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31054 IX86_BUILTIN_GATHER3DIV16SI);
31057 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31058 IX86_BUILTIN_GATHER3DIV8DI);
31061 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31062 IX86_BUILTIN_GATHER3ALTSIV8DF);
31065 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31066 IX86_BUILTIN_GATHER3ALTDIV16SF);
31069 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31070 IX86_BUILTIN_GATHER3ALTSIV8DI);
31073 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31074 IX86_BUILTIN_GATHER3ALTDIV16SI);
31077 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31078 IX86_BUILTIN_SCATTERSIV16SF);
31081 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31082 IX86_BUILTIN_SCATTERSIV8DF);
31085 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31086 IX86_BUILTIN_SCATTERDIV16SF);
31089 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31090 IX86_BUILTIN_SCATTERDIV8DF);
31093 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31094 IX86_BUILTIN_SCATTERSIV16SI);
31097 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31098 IX86_BUILTIN_SCATTERSIV8DI);
31101 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31102 IX86_BUILTIN_SCATTERDIV16SI);
31105 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31106 IX86_BUILTIN_SCATTERDIV8DI);
31108 /* AVX512PF */
31110 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31111 IX86_BUILTIN_GATHERPFDPD);
31113 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31114 IX86_BUILTIN_GATHERPFDPS);
31116 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31117 IX86_BUILTIN_GATHERPFQPD);
31119 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31120 IX86_BUILTIN_GATHERPFQPS);
31122 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31123 IX86_BUILTIN_SCATTERPFDPD);
31125 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31126 IX86_BUILTIN_SCATTERPFDPS);
31128 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31129 IX86_BUILTIN_SCATTERPFQPD);
31131 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31132 IX86_BUILTIN_SCATTERPFQPS);
31134 /* SHA */
31150 /* RTM. */
31154 /* MMX access to the vec_init patterns. */
31159 V4HI_FTYPE_HI_HI_HI_HI,
31160 IX86_BUILTIN_VEC_INIT_V4HI);
31163 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31164 IX86_BUILTIN_VEC_INIT_V8QI);
31166 /* Access to the vec_extract patterns. */
31188 /* Access to the vec_set patterns. */
31209 /* RDSEED */
31218 /* ADCX */
31223 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31224 IX86_BUILTIN_ADDCARRYX64);
31226 /* Read/write FLAGS. */
31237 /* Add FMA4 multi-arg argument instructions */
31239 {
31245 }
31246 }
31248 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31249 to return a pointer to VERSION_DECL if the outcome of the expression
31250 formed by PREDICATE_CHAIN is true. This function will be called during
31251 version dispatch to decide which function version to execute. It returns
31252 the basic block at the end, to which more conditions can be added. */
31254 static basic_block
31257 {
31258 gimple return_stmt;
31260 gimple convert_stmt;
31261 gimple call_cond_stmt;
31262 gimple if_else_stmt;
31268 gimple_seq gseq;
31285 {
31293 }
31296 {
31311 else
31312 {
31313 gimple assign_stmt;
31314 /* Use MIN_EXPR to check if any integer is zero?.
31315 and_expr_var = min_expr <cond_var, and_expr_var> */
31323 }
31324 }
31327 integer_zero_node,
31357 }
31359 /* This parses the attribute arguments to target in DECL and determines
31360 the right builtin to use to match the platform specification.
31361 It returns the priority value for this version decl. If PREDICATE_LIST
31362 is not NULL, it stores the list of cpu features that need to be checked
31363 before dispatching this function. */
31365 static unsigned int
31367 {
31368 tree attrs;
31370 tree target_node;
31377 /* Priority of i386 features, greater value is higher priority. This is
31378 used to decide the order in which function dispatch must happen. For
31379 instance, a version specialized for SSE4.2 should be checked for dispatch
31380 before a version for SSE3, as SSE4.2 implies SSE3. */
31381 enum feature_priority
31382 {
31384 P_MMX,
31385 P_SSE,
31386 P_SSE2,
31387 P_SSE3,
31388 P_SSSE3,
31389 P_PROC_SSSE3,
31390 P_SSE4_A,
31391 P_PROC_SSE4_A,
31392 P_SSE4_1,
31393 P_SSE4_2,
31394 P_PROC_SSE4_2,
31395 P_POPCNT,
31396 P_AVX,
31397 P_PROC_AVX,
31398 P_FMA4,
31399 P_XOP,
31400 P_PROC_XOP,
31401 P_FMA,
31402 P_PROC_FMA,
31403 P_AVX2,
31404 P_PROC_AVX2
31405 };
31409 /* These are the target attribute strings for which a dispatcher is
31410 available, from fold_builtin_cpu. */
31412 static struct _feature_list
31413 {
31416 }
31418 {
31433 };
31436 static unsigned int NUM_FEATURES
31452 /* Return priority zero for default function. */
31456 /* Handle arch= if specified. For priority, set it to be 1 more than
31457 the best instruction set the processor can handle. For instance, if
31458 there is a version for atom and a version for ssse3 (the highest ISA
31459 priority for atom), the atom version must be checked for dispatch
31460 before the ssse3 version. */
31462 {
31472 {
31474 {
31482 else
31483 /* We translate "arch=corei7" and "arch=nehalem" to
31484 "corei7" so that it will be mapped to M_INTEL_COREI7
31485 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31492 else
31499 else
31539 }
31540 }
31545 {
31549 }
31552 {
31554 /* For a C string literal the length includes the trailing NULL. */
31557 predicate_chain);
31558 }
31559 }
31561 /* Process feature name. */
31568 {
31569 /* Do not process "arch=" */
31571 {
31574 }
31576 {
31578 {
31580 {
31585 predicate_chain);
31586 }
31587 /* Find the maximum priority feature. */
31592 }
31593 }
31595 {
31599 }
31601 }
31605 {
31608 attrs_str);
31610 }
31612 {
31615 }
31618 }
31620 /* This compares the priority of target features in function DECL1
31621 and DECL2. It returns positive value if DECL1 is higher priority,
31622 negative value if DECL2 is higher priority and 0 if they are the
31623 same. */
31625 static int
31627 {
31632 }
31634 /* V1 and V2 point to function versions with different priorities
31635 based on the target ISA. This function compares their priorities. */
31637 static int
31639 {
31641 {
31642 tree version_decl;
31643 tree predicate_chain;
31650 }
31652 /* This function generates the dispatch function for
31653 multi-versioned functions. DISPATCH_DECL is the function which will
31654 contain the dispatch logic. FNDECLS are the function choices for
31655 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31656 in DISPATCH_DECL in which the dispatch code is generated. */
31658 static int
31662 {
31663 tree default_decl;
31664 gimple ifunc_cpu_init_stmt;
31665 gimple_seq gseq;
31667 tree ele;
31673 struct _function_version_info
31674 {
31675 tree version_decl;
31676 tree predicate_chain;
31684 /*fndecls_p is actually a vector. */
31687 /* At least one more version other than the default. */
31694 /* The first version in the vector is the default decl. */
31700 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31701 constructors, so explicity call __builtin_cpu_init here. */
31712 {
31716 /* Get attribute string, parse it and find the right predicate decl.
31717 The predicate function could be a lengthy combination of many
31718 features, like arch-type and various isa-variants. */
31729 actual_versions++;
31730 }
31732 /* Sort the versions according to descending order of dispatch priority. The
31733 priority is based on the ISA. This is not a perfect solution. There
31734 could still be ambiguity. If more than one function version is suitable
31735 to execute, which one should be dispatched? In future, allow the user
31736 to specify a dispatch priority next to the version. */
31746 /* dispatch default version at the end. */
31752 }
31754 /* Comparator function to be used in qsort routine to sort attribute
31755 specification strings to "target". */
31757 static int
31759 {
31763 }
31765 /* ARGLIST is the argument to target attribute. This function tokenizes
31766 the comma separated arguments, sorts them and returns a string which
31767 is a unique identifier for the comma separated arguments. It also
31768 replaces non-identifier characters "=,-" with "_". */
31772 {
31773 tree arg;
31782 {
31787 argnum++;
31790 argnum++;
31791 }
31796 {
31802 }
31804 /* Replace "=,-" with "_". */
31817 {
31819 i++;
31821 }
31828 {
31833 }
31838 }
31840 /* This function changes the assembler name for functions that are
31841 versions. If DECL is a function version and has a "target"
31842 attribute, it appends the attribute string to its assembler name. */
31844 static tree
31846 {
31847 tree version_attr;
31855 "Function versions cannot be marked as gnu_inline,"
31864 /* target attribute string cannot be NULL. */
31868 version_string
31879 /* Allow assembler name to be modified if already set. */
31887 }
31889 /* This function returns true if FN1 and FN2 are versions of the same function,
31890 that is, the target strings of the function decls are different. This assumes
31891 that FN1 and FN2 have the same signature. */
31893 static bool
31895 {
31907 /* At least one function decl should have the target attribute specified. */
31911 /* Diagnose missing target attribute if one of the decls is already
31912 multi-versioned. */
31914 {
31916 {
31918 {
31923 }
31926 fn2);
31929 /* Prevent diagnosing of the same error multiple times. */
31934 }
31936 }
31941 /* The sorted target strings must be different for fn1 and fn2
31942 to be versions. */
31945 else
31952 }
31954 static tree
31956 {
31957 /* For function version, add the target suffix to the assembler name. */
31961 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31963 #endif
31966 }
31968 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31969 is true, append the full path name of the source file. */
31973 {
31981 /* Get a unique name that can be used globally without any chances
31982 of collision at link time. */
31992 /* Use '.' to concatenate names as it is demangler friendly. */
31995 suffix);
31996 else
32000 }
32002 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32004 /* Make a dispatcher declaration for the multi-versioned function DECL.
32005 Calls to DECL function will be replaced with calls to the dispatcher
32006 by the front-end. Return the decl created. */
32008 static tree
32010 {
32011 tree func_decl;
32031 /* Mark this func as external, the resolver will flip it again if
32032 it gets generated. */
32034 /* This will be of type IFUNCs have to be externally visible. */
32038 }
32040 #endif
32042 /* Returns true if decl is multi-versioned and DECL is the default function,
32043 that is it is not tagged with target specific optimization. */
32045 static bool
32047 {
32056 }
32058 /* Make a dispatcher declaration for the multi-versioned function DECL.
32059 Calls to DECL function will be replaced with calls to the dispatcher
32060 by the front-end. Returns the decl of the dispatcher function. */
32062 static tree
32064 {
32086 /* Find the default version and make it the first node. */
32088 /* Go to the beginning of the chain. */
32093 {
32098 }
32100 /* If there is no default node, just return NULL. */
32104 /* Make default info the first node. */
32106 {
32113 }
32117 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32119 {
32124 /* Right now, the dispatching is done via ifunc. */
32130 dispatcher_version_info
32135 /* Set the dispatcher for all the versions. */
32138 {
32141 }
32142 }
32143 else
32144 #endif
32145 {
32147 "multiversioning needs ifunc which is not supported "
32149 }
32152 }
32154 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32155 it to CHAIN. */
32157 static tree
32159 {
32160 tree attr_name;
32161 tree attr_arg_name;
32162 tree attr_args;
32163 tree attr;
32170 }
32172 /* Make the resolver function decl to dispatch the versions of
32173 a multi-versioned function, DEFAULT_DECL. Create an
32174 empty basic block in the resolver and store the pointer in
32175 EMPTY_BB. Return the decl of the resolver function. */
32177 static tree
32181 {
32186 /* IFUNC's have to be globally visible. So, if the default_decl is
32187 not, then the name of the IFUNC should be made unique. */
32191 /* Append the filename to the resolver function if the versions are
32192 not externally visible. This is because the resolver function has
32193 to be externally visible for the loader to find it. So, appending
32194 the filename will prevent conflicts with a resolver function from
32195 another module which is based on the same version name. */
32198 /* The resolver function should return a (void *). */
32209 /* IFUNC resolvers have to be externally visible. */
32213 /* Resolver is not external, body is generated. */
32223 {
32224 /* In this case, each translation unit with a call to this
32225 versioned function will put out a resolver. Ensure it
32226 is comdat to keep just one copy. */
32229 }
32230 /* Build result decl and add to function_decl. */
32246 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32250 /* Create the alias for dispatch to resolver here. */
32251 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32255 }
32257 /* Generate the dispatching code body to dispatch multi-versioned function
32258 DECL. The target hook is called to process the "target" attributes and
32259 provide the code to dispatch the right function at run-time. NODE points
32260 to the dispatcher decl whose body will be created. */
32262 static tree
32264 {
32265 tree resolver_decl;
32266 basic_block empty_bb;
32267 tree default_ver_decl;
32283 /* The first version in the chain corresponds to the default version. */
32286 /* node is going to be an alias, so remove the finalized bit. */
32300 {
32302 /* Check for virtual functions here again, as by this time it should
32303 have been determined if this function needs a vtable index or
32304 not. This happens for methods in derived classes that override
32305 virtual methods in base classes but are not explicitly marked as
32306 virtual. */
32311 }
32317 }
32318 /* This builds the processor_model struct type defined in
32319 libgcc/config/i386/cpuinfo.c */
32321 static tree
32323 {
32330 /* The first 3 fields are unsigned int. */
32332 {
32338 }
32340 /* The last field is an array of unsigned integers of size one. */
32351 }
32353 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32355 static tree
32357 {
32358 tree new_decl;
32361 VAR_DECL,
32363 type);
32376 }
32378 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32379 into an integer defined in libgcc/config/i386/cpuinfo.c */
32381 static tree
32383 {
32389 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32390 enum processor_features
32391 {
32393 F_MMX,
32394 F_POPCNT,
32395 F_SSE,
32396 F_SSE2,
32397 F_SSE3,
32398 F_SSSE3,
32399 F_SSE4_1,
32400 F_SSE4_2,
32401 F_AVX,
32402 F_AVX2,
32403 F_SSE4_A,
32404 F_FMA4,
32405 F_XOP,
32406 F_FMA,
32407 F_MAX
32408 };
32410 /* These are the values for vendor types and cpu types and subtypes
32411 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32412 the corresponding start value. */
32413 enum processor_model
32414 {
32416 M_AMD,
32417 M_CPU_TYPE_START,
32418 M_INTEL_BONNELL,
32419 M_INTEL_CORE2,
32420 M_INTEL_COREI7,
32421 M_AMDFAM10H,
32422 M_AMDFAM15H,
32423 M_INTEL_SILVERMONT,
32424 M_AMD_BTVER1,
32425 M_AMD_BTVER2,
32426 M_CPU_SUBTYPE_START,
32427 M_INTEL_COREI7_NEHALEM,
32428 M_INTEL_COREI7_WESTMERE,
32429 M_INTEL_COREI7_SANDYBRIDGE,
32430 M_AMDFAM10H_BARCELONA,
32431 M_AMDFAM10H_SHANGHAI,
32432 M_AMDFAM10H_ISTANBUL,
32433 M_AMDFAM15H_BDVER1,
32434 M_AMDFAM15H_BDVER2,
32435 M_AMDFAM15H_BDVER3,
32436 M_AMDFAM15H_BDVER4,
32437 M_INTEL_COREI7_IVYBRIDGE,
32438 M_INTEL_COREI7_HASWELL,
32439 M_INTEL_COREI7_BROADWELL
32440 };
32442 static struct _arch_names_table
32443 {
32446 }
32448 {
32474 };
32476 static struct _isa_names_table
32477 {
32480 }
32482 {
32498 };
32512 {
32513 /* *args must be a expr that can contain other EXPRS leading to a
32514 STRING_CST. */
32516 {
32519 }
32521 }
32526 {
32527 tree ref;
32528 tree field;
32529 tree final;
32532 unsigned int NUM_ARCH_NAMES
32541 {
32545 }
32550 /* CPU types are stored in the next field. */
32553 {
32556 }
32558 /* CPU subtypes are stored in the next field. */
32560 {
32563 }
32565 /* Get the appropriate field in __cpu_model. */
32569 /* Check the value. */
32573 }
32575 {
32576 tree ref;
32577 tree array_elt;
32578 tree field;
32579 tree final;
32582 unsigned int NUM_ISA_NAMES
32591 {
32595 }
32598 /* Get the last field, which is __cpu_features. */
32602 /* Get the appropriate field: __cpu_model.__cpu_features */
32606 /* Access the 0th element of __cpu_features array. */
32611 /* Return __cpu_model.__cpu_features[0] & field_val */
32615 }
32617 }
32619 static tree
32622 {
32624 {
32629 {
32632 }
32633 }
32635 #ifdef SUBTARGET_FOLD_BUILTIN
32637 #endif
32640 }
32642 /* Make builtins to detect cpu type and features supported. NAME is
32643 the builtin name, CODE is the builtin code, and FTYPE is the function
32644 type of the builtin. */
32646 static void
32649 {
32650 tree decl;
32651 tree type;
32659 }
32661 /* Make builtins to get CPU type and features supported. The created
32662 builtins are :
32664 __builtin_cpu_init (), to detect cpu type and features,
32665 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32666 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32667 */
32669 static void
32671 {
32678 }
32680 /* Internal method for ix86_init_builtins. */
32682 static void
32684 {
32696 sysv_va_ref =
32699 fnvoid_va_end_ms =
32701 fnvoid_va_start_ms =
32703 fnvoid_va_end_sysv =
32705 fnvoid_va_start_sysv =
32707 NULL_TREE);
32708 fnvoid_va_copy_ms =
32710 NULL_TREE);
32711 fnvoid_va_copy_sysv =
32727 }
32729 static void
32731 {
32734 /* The __float80 type. */
32737 {
32738 /* The __float80 type. */
32743 }
32746 /* The __float128 type. */
32752 /* This macro is built by i386-builtin-types.awk. */
32753 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32754 }
32756 static void
32758 {
32759 tree t;
32763 /* Builtins to get CPU type and features. */
32766 /* TFmode support builtins. */
32772 /* We will expand them to normal call if SSE isn't available since
32773 they are used by libgcc. */
32792 #ifdef SUBTARGET_INIT_BUILTINS
32793 SUBTARGET_INIT_BUILTINS;
32794 #endif
32795 }
32797 /* Return the ix86 builtin for CODE. */
32799 static tree
32801 {
32806 }
32808 /* Errors in the source file can cause expand_expr to return const0_rtx
32809 where we expect a vector. To avoid crashing, use one of the vector
32810 clear instructions. */
32811 static rtx
32813 {
32817 }
32819 /* Fixup modeless constants to fit required mode. */
32820 static rtx
32822 {
32826 }
32828 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32830 static rtx
32832 {
32833 rtx pat;
32853 {
32857 }
32871 }
32873 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32875 static rtx
32879 {
32880 rtx pat;
32888 rtx op;
32895 {
32975 }
32985 {
32992 {
32994 {
32997 {
33015 xop_rotl:
33017 {
33020 gcc_checking_assert
33022 }
33023 else
33024 {
33025 gcc_checking_assert
33036 }
33040 }
33041 }
33042 }
33043 else
33044 {
33045 non_constant:
33049 /* If we aren't optimizing, only allow one memory operand to be
33050 generated. */
33052 num_memory++;
33060 }
33064 }
33067 {
33078 else
33079 {
33085 }
33098 }
33105 }
33107 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33108 insns with vec_merge. */
33110 static rtx
33112 rtx target)
33113 {
33114 rtx pat;
33141 }
33143 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33145 static rtx
33148 {
33149 rtx pat;
33154 rtx op2;
33165 /* Swap operands if we have a comparison that isn't available in
33166 hardware. */
33168 {
33173 }
33193 }
33195 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33197 static rtx
33199 rtx target)
33200 {
33201 rtx pat;
33215 /* Swap operands if we have a comparison that isn't available in
33216 hardware. */
33218 {
33222 }
33243 const0_rtx)));
33246 }
33248 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33250 static rtx
33252 rtx target)
33253 {
33254 rtx pat;
33279 }
33281 static rtx
33284 {
33285 rtx pat;
33290 rtx op2;
33317 }
33319 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33321 static rtx
33323 rtx target)
33324 {
33325 rtx pat;
33358 const0_rtx)));
33361 }
33363 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33365 static rtx
33368 {
33369 rtx pat;
33407 {
33410 }
33413 {
33422 }
33424 {
33433 }
33434 else
33435 {
33442 }
33450 {
33455 emit_insn
33459 FLAGS_REG),
33460 const0_rtx)));
33462 }
33463 else
33465 }
33468 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33470 static rtx
33473 {
33474 rtx pat;
33502 {
33505 }
33508 {
33517 }
33519 {
33528 }
33529 else
33530 {
33537 }
33545 {
33550 emit_insn
33554 FLAGS_REG),
33555 const0_rtx)));
33557 }
33558 else
33560 }
33562 /* Subroutine of ix86_expand_builtin to take care of insns with
33563 variable number of operands. */
33565 static rtx
33568 {
33574 struct
33575 {
33576 rtx op;
33588 {
34036 }
34041 {
34044 }
34047 {
34054 }
34055 else
34056 {
34059 }
34062 {
34069 {
34070 /* SIMD shift insns take either an 8-bit immediate or
34071 register as count. But builtin functions take int as
34072 count. If count doesn't match, we put it in register. */
34074 {
34078 }
34079 }
34082 {
34085 {
34161 {
34165 {
34168 }
34174 }
34176 }
34177 }
34178 else
34179 {
34183 /* If we aren't optimizing, only allow one memory operand to
34184 be generated. */
34186 num_memory++;
34191 {
34194 }
34195 else
34196 {
34199 }
34200 }
34204 }
34207 {
34232 }
34239 }
34241 /* Transform pattern of following layout:
34242 (parallel [
34243 set (A B)
34244 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34245 ])
34246 into:
34247 (set (A B))
34249 Or:
34250 (parallel [ A B
34251 ...
34252 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34253 ...
34254 ])
34255 into:
34256 (parallel [ A B ... ]) */
34258 static rtx
34260 {
34267 {
34276 }
34277 else
34278 {
34284 {
34289 }
34291 /* No more than 1 occurence was removed. */
34295 }
34296 }
34298 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34299 with rounding. */
34300 static rtx
34303 {
34320 /* See avxintrin.h for values. */
34322 {
34326 };
34328 {
34333 };
34336 {
34339 }
34341 {
34344 }
34347 {
34350 }
34373 ? CODE_FOR_sse_ucomi_round
34380 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34382 {
34388 }
34389 else
34390 {
34393 }
34399 set_dst,
34400 const0_rtx)));
34403 }
34405 static rtx
34408 {
34409 rtx pat;
34411 struct
34412 {
34413 rtx op;
34423 {
34500 }
34510 {
34517 {
34519 {
34521 {
34537 }
34538 }
34539 }
34541 {
34543 {
34546 }
34548 /* If there is no rounding use normal version of the pattern. */
34551 }
34552 else
34553 {
34560 {
34563 }
34564 else
34565 {
34568 }
34569 }
34573 }
34576 {
34601 }
34611 }
34613 /* Subroutine of ix86_expand_builtin to take care of special insns
34614 with variable number of operands. */
34616 static rtx
34619 {
34620 tree arg;
34624 struct
34625 {
34626 rtx op;
34636 {
34675 {
34683 }
34702 /* Reserve memory operand for target. */
34705 {
34706 /* These builtins and instructions require the memory
34707 to be properly aligned. */
34726 }
34751 {
34752 /* These builtins and instructions require the memory
34753 to be properly aligned. */
34762 }
34763 /* FALLTHRU */
34781 /* Reserve memory operand for target. */
34794 {
34795 /* These builtins and instructions require the memory
34796 to be properly aligned. */
34805 }
34818 }
34823 {
34828 {
34831 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34832 on it. Try to improve it using get_pointer_alignment,
34833 and if the special builtin is one that requires strict
34834 mode alignment, also from it's GET_MODE_ALIGNMENT.
34835 Failure to do so could lead to ix86_legitimate_combined_insn
34836 rejecting all changes to such insns. */
34842 }
34843 else
34846 }
34847 else
34848 {
34855 }
34858 {
34867 {
34869 {
34875 else
34878 }
34879 }
34880 else
34881 {
34883 {
34884 /* This must be the memory operand. */
34887 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34888 on it. Try to improve it using get_pointer_alignment,
34889 and if the special builtin is one that requires strict
34890 mode alignment, also from it's GET_MODE_ALIGNMENT.
34891 Failure to do so could lead to ix86_legitimate_combined_insn
34892 rejecting all changes to such insns. */
34898 }
34899 else
34900 {
34901 /* This must be register. */
34909 else
34910 {
34913 }
34914 }
34915 }
34919 }
34922 {
34937 }
34943 }
34945 /* Return the integer constant in ARG. Constrain it to be in the range
34946 of the subparts of VEC_TYPE; issue an error if not. */
34948 static int
34950 {
34955 {
34958 }
34961 }
34963 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34964 ix86_expand_vector_init. We DO have language-level syntax for this, in
34965 the form of (type){ init-list }. Except that since we can't place emms
34966 instructions from inside the compiler, we can't allow the use of MMX
34967 registers unless the user explicitly asks for it. So we do *not* define
34968 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34969 we have builtins invoked by mmintrin.h that gives us license to emit
34970 these sorts of instructions. */
34972 static rtx
34974 {
34984 {
34987 }
34994 }
34996 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34997 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34998 had a language-level syntax for referencing vector elements. */
35000 static rtx
35002 {
35006 rtx op0;
35026 }
35028 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35029 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
35030 a language-level syntax for referencing vector elements. */
35032 static rtx
35034 {
35058 /* OP0 is the source of these builtin functions and shouldn't be
35059 modified. Create a copy, use it and return it as target. */
35065 }
35067 /* Expand an expression EXP that calls a built-in function,
35068 with result going to TARGET if that's convenient
35069 (and in mode MODE if that's convenient).
35070 SUBTARGET may be used as the target for computing one of EXP's operands.
35071 IGNORE is nonzero if the value is to be ignored. */
35073 static rtx
35076 {
35086 /* For CPU builtins that can be folded, fold first and expand the fold. */
35088 {
35090 {
35091 /* Make it call __cpu_indicator_init in libgcc. */
35097 }
35100 {
35105 }
35106 }
35108 /* Determine whether the builtin function is available under the current ISA.
35109 Originally the builtin was not created if it wasn't applicable to the
35110 current ISA based on the command line switches. With function specific
35111 options, we need to check in the context of the function making the call
35112 whether it is supported. */
35115 {
35121 else
35122 {
35126 }
35128 }
35131 {
35135 ? CODE_FOR_mmx_maskmovq
35137 /* Note the arg order is different from the operand order. */
35238 {
35239 REAL_VALUE_TYPE inf;
35240 rtx tmp;
35252 }
35262 {
35268 insn = (TARGET_64BIT
35272 }
35274 {
35275 insn = (TARGET_64BIT
35279 }
35280 else
35281 {
35284 insn = (TARGET_64BIT
35292 {
35295 }
35297 }
35300 {
35301 /* mode is VOIDmode if __builtin_rd* has been called
35302 without lhs. */
35306 }
35309 {
35314 }
35328 {
35353 }
35359 {
35362 }
35382 {
35385 }
35391 {
35395 {
35416 }
35421 }
35422 else
35423 {
35425 {
35437 }
35439 }
35469 ? CODE_FOR_tbm_bextri_si
35472 {
35475 }
35476 else
35477 {
35486 }
35502 rdrand_step:
35509 {
35512 }
35518 /* Emit SImode conditional move. */
35520 {
35523 }
35526 else
35534 const0_rtx);
35553 rdseed_step:
35560 {
35563 }
35569 const0_rtx);
35588 addcarryx:
35596 /* Generate CF from input operand. */
35601 /* Gen ADCX instruction to compute X+Y+CF. */
35616 /* Store the result. */
35619 {
35622 }
35625 /* Return current CF value. */
35667 kortest:
35681 /* Emit kortest. */
35683 /* And use setcc to return result from flags. */
35834 gather_gen:
35835 rtx half;
35848 /* Note the arg order is different from the operand order. */
35859 else
35863 {
35885 else
35892 {
35897 }
35904 else
35911 {
35916 }
35920 }
35922 /* Force memory operand only with base register here. But we
35923 don't want to do it on memory operand for other builtin
35924 functions. */
35937 {
35940 }
35941 else
35942 {
35945 }
35947 {
35950 }
35952 /* Optimize. If mask is known to have all high bits set,
35953 replace op0 with pc_rtx to signal that the instruction
35954 overwrites the whole destination and doesn't use its
35955 previous contents. */
35957 {
35959 {
35962 }
35964 {
35967 {
35971 negative++;
35974 negative++;
35975 }
35978 }
35981 {
35982 /* Recognize also when mask is like:
35983 __v2df src = _mm_setzero_pd ();
35984 __v2df mask = _mm_cmpeq_pd (src, src);
35985 or
35986 __v8sf src = _mm256_setzero_ps ();
35987 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35988 as that is a cheaper way to load all ones into
35989 a register than having to load a constant from
35990 memory. */
35993 {
35998 {
36005 /* FALLTHRU */
36015 }
36016 }
36017 }
36018 }
36026 {
36050 }
36053 scatter_gen:
36069 /* Force memory operand only with base register here. But we
36070 don't want to do it on memory operand for other builtin
36071 functions. */
36080 {
36083 }
36084 else
36085 {
36088 }
36097 {
36100 }
36109 vec_prefetch_gen:
36129 {
36132 }
36134 {
36137 }
36142 /* Force memory operand only with base register here. But we
36143 don't want to do it on memory operand for other builtin
36144 functions. */
36151 {
36154 }
36157 {
36160 }
36176 {
36179 }
36185 }
36198 {
36202 /* Emit a normal call if SSE isn't available. */
36206 }
36235 }
36237 /* This returns the target-specific builtin with code CODE if
36238 current_function_decl has visibility on this builtin, which is checked
36239 using isa flags. Returns NULL_TREE otherwise. */
36242 {
36246 /* Determine the isa flags of current_function_decl. */
36258 else
36260 }
36262 /* Returns a function decl for a vectorized version of the builtin function
36263 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36264 if it is not available. */
36266 static tree
36268 tree type_in)
36269 {
36285 {
36288 {
36295 }
36300 {
36303 }
36308 {
36315 }
36321 /* The round insn does not trap on denormals. */
36326 {
36333 }
36339 /* The round insn does not trap on denormals. */
36344 {
36349 }
36355 /* The round insn does not trap on denormals. */
36360 {
36367 }
36373 /* The round insn does not trap on denormals. */
36378 {
36383 }
36390 {
36395 }
36402 {
36407 }
36413 /* The round insn does not trap on denormals. */
36418 {
36425 }
36431 /* The round insn does not trap on denormals. */
36436 {
36441 }
36446 {
36453 }
36458 {
36465 }
36469 /* The round insn does not trap on denormals. */
36474 {
36479 }
36483 /* The round insn does not trap on denormals. */
36488 {
36493 }
36497 /* The round insn does not trap on denormals. */
36502 {
36507 }
36511 /* The round insn does not trap on denormals. */
36516 {
36521 }
36525 /* The round insn does not trap on denormals. */
36530 {
36535 }
36539 /* The round insn does not trap on denormals. */
36544 {
36549 }
36553 /* The round insn does not trap on denormals. */
36558 {
36563 }
36567 /* The round insn does not trap on denormals. */
36572 {
36577 }
36581 /* The round insn does not trap on denormals. */
36586 {
36591 }
36595 /* The round insn does not trap on denormals. */
36600 {
36605 }
36610 {
36615 }
36620 {
36625 }
36630 }
36632 /* Dispatch to a handler for a vectorization library. */
36635 type_in);
36638 }
36640 /* Handler for an SVML-style interface to
36641 a library with vectorized intrinsics. */
36643 static tree
36645 {
36653 /* The SVML is suitable for unsafe math only. */
36666 {
36713 }
36722 {
36725 }
36726 else
36729 /* Convert to uppercase. */
36734 args;
36736 arity++;
36740 else
36743 /* Build a function declaration for the vectorized function. */
36752 }
36754 /* Handler for an ACML-style interface to
36755 a library with vectorized intrinsics. */
36757 static tree
36759 {
36767 /* The ACML is 64bits only and suitable for unsafe math only as
36768 it does not correctly support parts of IEEE with the required
36769 precision such as denormals. */
36783 {
36813 }
36820 args;
36822 arity++;
36826 else
36829 /* Build a function declaration for the vectorized function. */
36838 }
36840 /* Returns a decl of a function that implements gather load with
36841 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36842 Return NULL_TREE if it is not available. */
36844 static tree
36847 {
36863 /* v*gather* insn sign extends index to pointer mode. */
36875 {
36903 else
36909 else
36915 else
36921 else
36926 }
36929 }
36931 /* Returns a code for a target-specific builtin that implements
36932 reciprocal of the function, or NULL_TREE if not available. */
36934 static tree
36937 {
36944 /* Machine dependent builtins. */
36946 {
36947 /* Vectorized version of sqrt to rsqrt conversion. */
36956 }
36957 else
36958 /* Normal builtins. */
36960 {
36961 /* Sqrt to rsqrt conversion. */
36967 }
36968 }
36969 \f
36970 /* Helper for avx_vpermilps256_operand et al. This is also used by
36971 the expansion functions to turn the parallel back into a mask.
36972 The return value is 0 for no match and the imm8+1 for a match. */
36974 int
36976 {
36984 /* Validate that all of the elements are constants, and not totally
36985 out of range. Copy the data into an integral array to make the
36986 subsequent checks easier. */
36988 {
36998 }
37001 {
37003 /* In the 512-bit DFmode case, we can only move elements within
37004 a 128-bit lane. First fill the second part of the mask,
37005 then fallthru. */
37007 {
37011 }
37013 {
37017 }
37018 /* FALLTHRU */
37021 /* In the 256-bit DFmode case, we can only move elements within
37022 a 128-bit lane. */
37024 {
37028 }
37030 {
37034 }
37038 /* In 512 bit SFmode case, permutation in the upper 256 bits
37039 must mirror the permutation in the lower 256-bits. */
37043 /* FALLTHRU */
37046 /* In 256 bit SFmode case, we have full freedom of
37047 movement within the low 128-bit lane, but the high 128-bit
37048 lane must mirror the exact same pattern. */
37053 /* FALLTHRU */
37057 /* In the 128-bit case, we've full freedom in the placement of
37058 the elements from the source operand. */
37065 }
37067 /* Make sure success has a non-zero value by adding one. */
37069 }
37071 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37072 the expansion functions to turn the parallel back into a mask.
37073 The return value is 0 for no match and the imm8+1 for a match. */
37075 int
37077 {
37085 /* Validate that all of the elements are constants, and not totally
37086 out of range. Copy the data into an integral array to make the
37087 subsequent checks easier. */
37089 {
37099 }
37101 /* Validate that the halves of the permute are halves. */
37109 /* Reconstruct the mask. */
37111 {
37117 }
37119 /* Make sure success has a non-zero value by adding one. */
37121 }
37122 \f
37123 /* Return a register priority for hard reg REGNO. */
37124 static int
37126 {
37127 /* ebp and r13 as the base always wants a displacement, r12 as the
37128 base always wants an index. So discourage their usage in an
37129 address. */
37134 /* New x86-64 int registers result in bigger code size. Discourage
37135 them. */
37138 /* New x86-64 SSE registers result in bigger code size. Discourage
37139 them. */
37142 /* Usage of AX register results in smaller code. Prefer it. */
37146 }
37148 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37150 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37151 QImode must go into class Q_REGS.
37152 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37153 movdf to do mem-to-mem moves through integer regs. */
37155 static reg_class_t
37157 {
37160 /* We're only allowed to return a subclass of CLASS. Many of the
37161 following checks fail for NO_REGS, so eliminate that early. */
37165 /* All classes can load zeros. */
37169 /* Force constants into memory if we are loading a (nonzero) constant into
37170 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37171 instructions to load from a constant. */
37178 /* Prefer SSE regs only, if we can use them for math. */
37182 /* Floating-point constants need more complex checks. */
37184 {
37185 /* General regs can load everything. */
37189 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37190 zero above. We only want to wind up preferring 80387 registers if
37191 we plan on doing computation with them. */
37194 {
37195 /* Limit class to non-sse. */
37204 }
37207 }
37209 /* Generally when we see PLUS here, it's the function invariant
37210 (plus soft-fp const_int). Which can only be computed into general
37211 regs. */
37215 /* QImode constants are easy to load, but non-constant QImode data
37216 must go into Q_REGS. */
37218 {
37224 }
37227 }
37229 /* Discourage putting floating-point values in SSE registers unless
37230 SSE math is being used, and likewise for the 387 registers. */
37231 static reg_class_t
37233 {
37236 /* Restrict the output reload class to the register bank that we are doing
37237 math on. If we would like not to return a subset of CLASS, reject this
37238 alternative: if reload cannot do this, it will still use its choice. */
37244 {
37249 else
37251 }
37254 }
37256 static reg_class_t
37259 {
37260 /* Double-word spills from general registers to non-offsettable memory
37261 references (zero-extended addresses) require special handling. */
37267 {
37269 ? CODE_FOR_reload_noff_load
37271 /* Add the cost of moving address to a temporary. */
37275 }
37277 /* QImode spills from non-QI registers require
37278 intermediate register on 32bit targets. */
37284 {
37289 else
37295 /* Return Q_REGS if the operand is in memory. */
37298 }
37300 /* This condition handles corner case where an expression involving
37301 pointers gets vectorized. We're trying to use the address of a
37302 stack slot as a vector initializer.
37304 (set (reg:V2DI 74 [ vect_cst_.2 ])
37305 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37307 Eventually frame gets turned into sp+offset like this:
37309 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37310 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37311 (const_int 392 [0x188]))))
37313 That later gets turned into:
37315 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37316 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37317 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37319 We'll have the following reload recorded:
37321 Reload 0: reload_in (DI) =
37322 (plus:DI (reg/f:DI 7 sp)
37323 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37324 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37325 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37326 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37327 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37328 reload_reg_rtx: (reg:V2DI 22 xmm1)
37330 Which isn't going to work since SSE instructions can't handle scalar
37331 additions. Returning GENERAL_REGS forces the addition into integer
37332 register and reload can handle subsequent reloads without problems. */
37340 }
37342 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37344 static bool
37346 {
37348 {
37363 }
37366 }
37368 /* If we are copying between general and FP registers, we need a memory
37369 location. The same is true for SSE and MMX registers.
37371 To optimize register_move_cost performance, allow inline variant.
37373 The macro can't work reliably when one of the CLASSES is class containing
37374 registers from multiple units (SSE, MMX, integer). We avoid this by never
37375 combining those units in single alternative in the machine description.
37376 Ensure that this constraint holds to avoid unexpected surprises.
37378 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37379 enforce these sanity checks. */
37384 {
37393 {
37396 }
37401 /* ??? This is a lie. We do have moves between mmx/general, and for
37402 mmx/sse2. But by saying we need secondary memory we discourage the
37403 register allocator from using the mmx registers unless needed. */
37408 {
37409 /* SSE1 doesn't have any direct moves from other classes. */
37413 /* If the target says that inter-unit moves are more expensive
37414 than moving through memory, then don't generate them. */
37419 /* Between SSE and general, we have moves no larger than word size. */
37422 }
37425 }
37427 bool
37430 {
37432 }
37434 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37436 On the 80386, this is the size of MODE in words,
37437 except in the FP regs, where a single reg is always enough. */
37439 static unsigned char
37441 {
37443 {
37448 else
37450 }
37451 else
37452 {
37455 else
37457 }
37458 }
37460 /* Return true if the registers in CLASS cannot represent the change from
37461 modes FROM to TO. */
37463 bool
37466 {
37470 /* x87 registers can't do subreg at all, as all values are reformatted
37471 to extended precision. */
37476 {
37477 /* Vector registers do not support QI or HImode loads. If we don't
37478 disallow a change to these modes, reload will assume it's ok to
37479 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37480 the vec_dupv4hi pattern. */
37484 /* Vector registers do not support subreg with nonzero offsets, which
37485 are otherwise valid for integer registers. Since we can't see
37486 whether we have a nonzero offset from here, prohibit all
37487 nonparadoxical subregs changing size. */
37490 }
37493 }
37495 /* Return the cost of moving data of mode M between a
37496 register and memory. A value of 2 is the default; this cost is
37497 relative to those in `REGISTER_MOVE_COST'.
37499 This function is used extensively by register_move_cost that is used to
37500 build tables at startup. Make it inline in this case.
37501 When IN is 2, return maximum of in and out move cost.
37503 If moving between registers and memory is more expensive than
37504 between two registers, you should define this macro to express the
37505 relative cost.
37507 Model also increased moving costs of QImode registers in non
37508 Q_REGS classes.
37509 */
37513 {
37516 {
37519 {
37531 }
37535 }
37537 {
37540 {
37552 }
37556 }
37558 {
37561 {
37570 }
37574 }
37576 {
37579 {
37585 else
37590 }
37591 else
37592 {
37597 else
37599 }
37606 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37613 else
37617 }
37618 }
37620 static int
37623 {
37625 }
37628 /* Return the cost of moving data from a register in class CLASS1 to
37629 one in class CLASS2.
37631 It is not required that the cost always equal 2 when FROM is the same as TO;
37632 on some machines it is expensive to move between registers if they are not
37633 general registers. */
37635 static int
37637 reg_class_t class2_i)
37638 {
37642 /* In case we require secondary memory, compute cost of the store followed
37643 by load. In order to avoid bad register allocation choices, we need
37644 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37647 {
37653 /* In case of copying from general_purpose_register we may emit multiple
37654 stores followed by single load causing memory size mismatch stall.
37655 Count this as arbitrarily high cost of 20. */
37660 /* In the case of FP/MMX moves, the registers actually overlap, and we
37661 have to switch modes in order to treat them differently. */
37667 }
37669 /* Moves between SSE/MMX and integer unit are expensive. */
37673 /* ??? By keeping returned value relatively high, we limit the number
37674 of moves between integer and MMX/SSE registers for all targets.
37675 Additionally, high value prevents problem with x86_modes_tieable_p(),
37676 where integer modes in MMX/SSE registers are not tieable
37677 because of missing QImode and HImode moves to, from or between
37678 MMX/SSE registers. */
37688 }
37690 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37691 MODE. */
37693 bool
37695 {
37696 /* Flags and only flags can only hold CCmode values. */
37708 {
37709 /* We implement the move patterns for all vector modes into and
37710 out of SSE registers, even when no operation instructions
37711 are available. */
37713 /* For AVX-512 we allow, regardless of regno:
37714 - XI mode
37715 - any of 512-bit wide vector mode
37716 - any scalar mode. */
37723 /* xmm16-xmm31 are only available for AVX-512. */
37727 /* OImode and AVX modes are available only when AVX is enabled. */
37734 }
37736 {
37737 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37738 so if the register is available at all, then we can move data of
37739 the given mode into or out of it. */
37742 }
37745 {
37746 /* Take care for QImode values - they can be in non-QI regs,
37747 but then they do cause partial register stalls. */
37752 /* LRA checks if the hard register is OK for the given mode.
37753 QImode values can live in non-QI regs, so we allow all
37754 registers here. */
37758 }
37759 /* We handle both integer and floats in the general purpose registers. */
37766 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37767 on to use that value in smaller contexts, this can easily force a
37768 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37769 supporting DImode, allow it. */
37774 }
37776 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37777 tieable integer mode. */
37779 static bool
37781 {
37783 {
37796 }
37797 }
37799 /* Return true if MODE1 is accessible in a register that can hold MODE2
37800 without copying. That is, all register classes that can hold MODE2
37801 can also hold MODE1. */
37803 bool
37805 {
37813 /* MODE2 being XFmode implies fp stack or general regs, which means we
37814 can tie any smaller floating point modes to it. Note that we do not
37815 tie this with TFmode. */
37819 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37820 that we can tie it with SFmode. */
37824 /* If MODE2 is only appropriate for an SSE register, then tie with
37825 any other mode acceptable to SSE registers. */
37835 /* If MODE2 is appropriate for an MMX register, then tie
37836 with any other mode acceptable to MMX registers. */
37843 }
37845 /* Return the cost of moving between two registers of mode MODE. */
37847 static int
37849 {
37853 {
37885 }
37887 /* Return the cost of moving between two registers of mode MODE,
37888 assuming that the move will be in pieces of at most UNITS bytes. */
37890 }
37892 /* Compute a (partial) cost for rtx X. Return true if the complete
37893 cost has been computed, and false if subexpressions should be
37894 scanned. In either case, *TOTAL contains the cost result. */
37896 static bool
37899 {
37900 rtx mask;
37907 {
37911 {
37914 }
37926 && !(TARGET_64BIT
37931 else
37937 {
37940 }
37942 {
37952 }
37954 {
37957 {
37966 }
37967 }
37968 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37969 it'll probably end up. Add a penalty for size. */
37976 /* The zero extensions is often completely free on x86_64, so make
37977 it as cheap as possible. */
37983 else
37995 {
37998 {
38001 }
38004 {
38007 }
38008 }
38009 /* FALLTHRU */
38016 {
38017 /* ??? Should be SSE vector operation cost. */
38018 /* At least for published AMD latencies, this really is the same
38019 as the latency for a simple fpu operation like fabs. */
38020 /* V*QImode is emulated with 1-11 insns. */
38022 {
38025 {
38026 /* For XOP we use vpshab, which requires a broadcast of the
38027 value to the variable shift insn. For constants this
38028 means a V16Q const in mem; even when we can perform the
38029 shift with one insn set the cost to prefer paddb. */
38031 {
38036 }
38038 }
38042 }
38043 else
38045 }
38047 {
38049 {
38052 else
38054 }
38055 else
38056 {
38059 else
38061 }
38062 }
38063 else
38064 {
38069 {
38070 /* Return the cost after shift-and truncation. */
38073 }
38074 else
38076 }
38080 {
38081 rtx sub;
38086 /* ??? SSE scalar/vector cost should be used here. */
38087 /* ??? Bald assumption that fma has the same cost as fmul. */
38091 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38102 }
38106 {
38107 /* ??? SSE scalar cost should be used here. */
38110 }
38112 {
38115 }
38117 {
38118 /* ??? SSE vector cost should be used here. */
38121 }
38123 {
38124 /* V*QImode is emulated with 7-13 insns. */
38126 {
38133 }
38134 /* V*DImode is emulated with 5-8 insns. */
38136 {
38139 else
38141 }
38142 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38143 insns, including two PMULUDQ. */
38146 else
38149 }
38150 else
38151 {
38156 {
38159 nbits++;
38160 }
38161 else
38162 /* This is arbitrary. */
38165 /* Compute costs correctly for widening multiplication. */
38169 {
38176 {
38180 else
38182 }
38186 }
38194 }
38201 /* ??? SSE cost should be used here. */
38206 /* ??? SSE vector cost should be used here. */
38208 else
38215 {
38220 {
38223 {
38231 }
38232 }
38235 {
38238 {
38244 }
38245 }
38247 {
38255 }
38256 }
38257 /* FALLTHRU */
38261 {
38262 /* ??? SSE cost should be used here. */
38265 }
38267 {
38270 }
38272 {
38273 /* ??? SSE vector cost should be used here. */
38276 }
38277 /* FALLTHRU */
38284 {
38291 }
38292 /* FALLTHRU */
38296 {
38297 /* ??? SSE cost should be used here. */
38300 }
38302 {
38305 }
38307 {
38308 /* ??? SSE vector cost should be used here. */
38311 }
38312 /* FALLTHRU */
38316 {
38317 /* ??? Should be SSE vector operation cost. */
38318 /* At least for published AMD latencies, this really is the same
38319 as the latency for a simple fpu operation like fabs. */
38321 }
38324 else
38333 {
38334 /* This kind of construct is implemented using test[bwl].
38335 Treat it as if we had an AND. */
38340 }
38350 /* ??? SSE cost should be used here. */
38355 /* ??? SSE vector cost should be used here. */
38361 /* ??? SSE cost should be used here. */
38366 /* ??? SSE vector cost should be used here. */
38378 /* ??? Assume all of these vector manipulation patterns are
38379 recognizable. In which case they all pretty much have the
38380 same cost. */
38385 /* This is masked instruction, assume the same cost,
38386 as nonmasked variant. */
38389 else
38395 }
38396 }
38398 #if TARGET_MACHO
38402 /* Given a symbol name and its associated stub, write out the
38403 definition of the stub. */
38405 void
38407 {
38412 /* For 64-bit we shouldn't get here. */
38415 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38432 else
38439 {
38441 }
38443 {
38444 /* PIC stub. */
38445 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38451 }
38452 else
38455 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38456 it needs no stub-binding-helper. */
38463 {
38466 }
38467 else
38472 /* N.B. Keep the correspondence of these
38473 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38474 old-pic/new-pic/non-pic stubs; altering this will break
38475 compatibility with existing dylibs. */
38477 {
38478 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38480 }
38481 else
38482 /* 16-byte -mdynamic-no-pic stub. */
38488 }
38491 /* Order the registers for register allocator. */
38493 void
38495 {
38499 /* First allocate the local general purpose registers. */
38504 /* Global general purpose registers. */
38509 /* x87 registers come first in case we are doing FP math
38510 using them. */
38515 /* SSE registers. */
38521 /* Extended REX SSE registers. */
38525 /* Mask register. */
38529 /* x87 registers. */
38537 /* Initialize the rest of array as we do not allocate some registers
38538 at all. */
38541 }
38543 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38544 in struct attribute_spec handler. */
38545 static tree
38547 tree args,
38550 {
38555 {
38557 name);
38560 }
38562 {
38564 name);
38567 }
38569 {
38570 tree cst;
38574 {
38577 name);
38579 }
38582 {
38585 name);
38587 }
38590 }
38593 }
38595 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38596 struct attribute_spec.handler. */
38597 static tree
38599 tree args ATTRIBUTE_UNUSED,
38601 {
38606 {
38608 name);
38611 }
38613 /* Can combine regparm with all attributes but fastcall. */
38615 {
38617 {
38619 }
38622 }
38624 {
38626 {
38628 }
38631 }
38634 }
38636 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38637 struct attribute_spec.handler. */
38638 static tree
38640 tree args ATTRIBUTE_UNUSED,
38642 {
38645 {
38648 }
38649 else
38653 {
38655 name);
38657 }
38663 {
38665 name);
38667 }
38670 }
38672 static tree
38674 tree args ATTRIBUTE_UNUSED,
38676 {
38678 {
38680 name);
38682 }
38684 }
38686 static bool
38688 {
38692 }
38694 /* Returns an expression indicating where the this parameter is
38695 located on entry to the FUNCTION. */
38697 static rtx
38699 {
38705 {
38710 else
38713 }
38718 {
38725 {
38730 }
38731 else
38732 {
38735 {
38741 }
38742 }
38744 }
38748 }
38750 /* Determine whether x86_output_mi_thunk can succeed. */
38752 static bool
38754 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38756 {
38757 /* 64-bit can handle anything. */
38761 /* For 32-bit, everything's fine if we have one free register. */
38765 /* Need a free register for vcall_offset. */
38769 /* Need a free register for GOT references. */
38773 /* Otherwise ok. */
38775 }
38777 /* Output the assembler code for a thunk function. THUNK_DECL is the
38778 declaration for the thunk function itself, FUNCTION is the decl for
38779 the target function. DELTA is an immediate constant offset to be
38780 added to THIS. If VCALL_OFFSET is nonzero, the word at
38781 *(*this + vcall_offset) should be added to THIS. */
38783 static void
38787 {
38794 else
38795 {
38801 else
38803 }
38807 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38808 pull it in now and let DELTA benefit. */
38812 {
38813 /* Put the this parameter into %eax. */
38816 }
38817 else
38820 /* Adjust the this parameter by a fixed constant. */
38822 {
38827 {
38829 {
38833 }
38834 }
38837 }
38839 /* Adjust the this parameter by a value stored in the vtable. */
38841 {
38851 /* Adjust the this parameter. */
38855 {
38859 }
38866 vcall_mem));
38867 else
38869 }
38871 /* If necessary, drop THIS back to its stack slot. */
38877 {
38880 ;
38881 else
38882 {
38886 }
38887 }
38888 else
38889 {
38891 ;
38892 #if TARGET_MACHO
38894 {
38897 }
38899 else
38900 {
38908 }
38909 }
38911 /* Our sibling call patterns do not allow memories, because we have no
38912 predicate that can distinguish between frame and non-frame memory.
38913 For our purposes here, we can get away with (ab)using a jump pattern,
38914 because we're going to do no optimization. */
38917 else
38918 {
38924 {
38930 }
38936 }
38939 /* Emit just enough of rest_of_compilation to get the insns emitted.
38940 Note that use_thunk calls assemble_start_function et al. */
38946 }
38948 static void
38950 {
38954 #if TARGET_MACHO
38956 #endif
38963 }
38965 int
38967 {
38979 }
38981 /* Output assembler code to FILE to increment profiler label # LABELNO
38982 for profiling a function entry. */
38983 void
38985 {
38990 {
38991 #ifndef NO_PROFILE_COUNTERS
38993 #endif
38997 else
38999 }
39001 {
39002 #ifndef NO_PROFILE_COUNTERS
39005 #endif
39007 }
39008 else
39009 {
39010 #ifndef NO_PROFILE_COUNTERS
39013 #endif
39015 }
39016 }
39018 /* We don't have exact information about the insn sizes, but we may assume
39019 quite safely that we are informed about all 1 byte insns and memory
39020 address sizes. This is enough to eliminate unnecessary padding in
39021 99% of cases. */
39023 static int
39025 {
39031 /* Discard alignments we've emit and jump instructions. */
39036 /* Important case - calls are always 5 bytes.
39037 It is common to have many calls in the row. */
39046 /* For normal instructions we rely on get_attr_length being exact,
39047 with a few exceptions. */
39049 {
39053 {
39063 /* Otherwise trust get_attr_length. */
39065 }
39070 }
39073 else
39075 }
39077 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39079 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39080 window. */
39082 static void
39084 {
39089 /* Look for all minimal intervals of instructions containing 4 jumps.
39090 The intervals are bounded by START and INSN. NBYTES is the total
39091 size of instructions in the interval including INSN and not including
39092 START. When the NBYTES is smaller than 16 bytes, it is possible
39093 that the end of START and INSN ends up in the same 16byte page.
39095 The smallest offset in the page INSN can start is the case where START
39096 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39097 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39099 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39100 have to, control transfer to label(s) can be performed through other
39101 means, and also we estimate minimum length of all asm stmts as 0. */
39103 {
39107 {
39113 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39114 already in the current 16 byte page, because otherwise
39115 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39116 bytes to reach 16 byte boundary. */
39124 {
39126 {
39131 else
39134 }
39135 }
39137 }
39146 njumps++;
39147 else
39151 {
39156 else
39159 }
39166 {
39173 }
39174 }
39175 }
39176 #endif
39178 /* AMD Athlon works faster
39179 when RET is not destination of conditional jump or directly preceded
39180 by other jump instruction. We avoid the penalty by inserting NOP just
39181 before the RET instructions in such cases. */
39182 static void
39184 {
39185 edge e;
39186 edge_iterator ei;
39189 {
39192 rtx prev;
39202 {
39203 edge e;
39204 edge_iterator ei;
39209 {
39212 }
39213 }
39215 {
39221 /* Empty functions get branch mispredict even when
39222 the jump destination is not visible to us. */
39225 }
39227 {
39230 }
39231 }
39232 }
39234 /* Count the minimum number of instructions in BB. Return 4 if the
39235 number of instructions >= 4. */
39237 static int
39239 {
39240 rtx insn;
39243 /* Count number of instructions in this block. Return 4 if the number
39244 of instructions >= 4. */
39246 {
39247 /* Only happen in exit blocks. */
39255 {
39256 insn_count++;
39259 }
39260 }
39263 }
39266 /* Count the minimum number of instructions in code path in BB.
39267 Return 4 if the number of instructions >= 4. */
39269 static int
39271 {
39272 edge e;
39273 edge_iterator ei;
39276 /* Only bother counting instructions along paths with no
39277 more than 2 basic blocks between entry and exit. Given
39278 that BB has an edge to exit, determine if a predecessor
39279 of BB has an edge from entry. If so, compute the number
39280 of instructions in the predecessor block. If there
39281 happen to be multiple such blocks, compute the minimum. */
39284 {
39285 edge prev_e;
39286 edge_iterator prev_ei;
39289 {
39292 }
39294 {
39296 {
39301 }
39302 }
39303 }
39309 }
39311 /* Pad short function to 4 instructions. */
39313 static void
39315 {
39316 edge e;
39317 edge_iterator ei;
39320 {
39323 {
39326 /* Pad short function. */
39328 {
39331 /* Find epilogue. */
39340 /* Two NOPs count as one instruction. */
39343 }
39344 }
39345 }
39346 }
39348 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39349 the epilogue, the Windows system unwinder will apply epilogue logic and
39350 produce incorrect offsets. This can be avoided by adding a nop between
39351 the last insn that can throw and the first insn of the epilogue. */
39353 static void
39355 {
39356 edge e;
39357 edge_iterator ei;
39360 {
39363 /* Find the beginning of the epilogue. */
39370 /* We only care about preceding insns that can throw. */
39375 /* Do not separate calls from their debug information. */
39381 else
39385 }
39386 }
39388 /* Implement machine specific optimizations. We implement padding of returns
39389 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39390 static void
39392 {
39393 /* We are freeing block_for_insn in the toplev to keep compatibility
39394 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39401 {
39406 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39409 #endif
39410 }
39411 }
39413 /* Return nonzero when QImode register that must be represented via REX prefix
39414 is used. */
39415 bool
39417 {
39425 }
39427 /* Return nonzero when P points to register encoded via REX prefix.
39428 Called via for_each_rtx. */
39429 static int
39431 {
39437 }
39439 /* Return true when INSN mentions register that must be encoded using REX
39440 prefix. */
39441 bool
39443 {
39446 }
39448 /* If profitable, negate (without causing overflow) integer constant
39449 of mode MODE at location LOC. Return true in this case. */
39450 bool
39452 {
39453 HOST_WIDE_INT val;
39459 {
39461 /* DImode x86_64 constants must fit in 32 bits. */
39474 }
39476 /* Avoid overflows. */
39482 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39483 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39486 {
39489 }
39492 }
39494 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39495 optabs would emit if we didn't have TFmode patterns. */
39497 void
39499 {
39533 }
39534 \f
39535 /* AVX512F does support 64-byte integer vector operations,
39536 thus the longest vector we are faced with is V64QImode. */
39537 #define MAX_VECT_LEN 64
39539 struct expand_vec_perm_d
39540 {
39547 };
39553 /* Get a vector mode of the same size as the original but with elements
39554 twice as wide. This is only guaranteed to apply to integral vectors. */
39558 {
39559 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39564 }
39566 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39567 fill target with val via vec_duplicate. */
39569 static bool
39571 {
39575 /* First attempt to recognize VAL as-is. */
39579 {
39580 rtx seq;
39581 /* If that fails, force VAL into a register. */
39592 }
39594 }
39596 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39597 with all elements equal to VAR. Return true if successful. */
39599 static bool
39602 {
39606 {
39611 /* FALLTHRU */
39631 {
39632 rtx x;
39639 }
39649 {
39653 permute:
39661 /* Extend to SImode using a paradoxical SUBREG. */
39665 /* Insert the SImode value as low element of a V4SImode vector. */
39674 }
39682 widen:
39683 /* Replicate the value once into the next wider mode and recurse. */
39684 {
39686 rtx x;
39703 }
39707 {
39716 }
39721 }
39722 }
39724 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39725 whose ONE_VAR element is VAR, and other elements are zero. Return true
39726 if successful. */
39728 static bool
39731 {
39733 rtx new_target;
39738 {
39740 /* For SSE4.1, we normally use vector set. But if the second
39741 element is zero and inter-unit moves are OK, we use movq
39742 instead. */
39744 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39766 /* Use ix86_expand_vector_set in 64bit mode only. */
39771 }
39774 {
39779 }
39782 {
39787 /* FALLTHRU */
39802 else
39809 {
39810 /* We need to shuffle the value to the correct position, so
39811 create a new pseudo to store the intermediate result. */
39813 /* With SSE2, we can use the integer shuffle insns. */
39815 {
39817 const1_rtx,
39824 }
39826 /* Otherwise convert the intermediate result to V4SFmode and
39827 use the SSE1 shuffle instructions. */
39829 {
39832 }
39833 else
39837 const1_rtx,
39846 }
39861 widen:
39865 /* Zero extend the variable element to SImode and recurse. */
39878 }
39879 }
39881 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39882 consisting of the values in VALS. It is known that all elements
39883 except ONE_VAR are constants. Return true if successful. */
39885 static bool
39888 {
39898 {
39903 /* For the two element vectors, it's just as easy to use
39904 the general case. */
39908 /* Use ix86_expand_vector_set in 64bit mode only. */
39930 widen:
39931 /* There's no way to set one QImode entry easily. Combine
39932 the variable value with its adjacent constant value, and
39933 promote to an HImode set. */
39936 {
39941 }
39942 else
39943 {
39946 }
39960 }
39965 }
39967 /* A subroutine of ix86_expand_vector_init_general. Use vector
39968 concatenate to handle the most general case: all values variable,
39969 and none identical. */
39971 static void
39974 {
39977 rtvec v;
39981 {
39984 {
40029 }
40042 {
40057 }
40062 {
40081 }
40086 {
40099 }
40102 half:
40103 /* FIXME: We process inputs backward to help RA. PR 36222. */
40107 {
40112 }
40116 {
40120 {
40124 }
40127 {
40131 }
40134 }
40136 {
40139 {
40143 }
40146 }
40147 else
40153 }
40154 }
40156 /* A subroutine of ix86_expand_vector_init_general. Use vector
40157 interleave to handle the most general case: all values variable,
40158 and none identical. */
40160 static void
40163 {
40172 {
40193 }
40196 {
40197 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40201 /* Insert the SImode value as low element of V4SImode vector. */
40205 op0),
40207 const1_rtx);
40210 /* Cast the V4SImode vector back to a vector in orignal mode. */
40214 /* Load even elements into the second position. */
40218 const1_rtx));
40220 /* Cast vector to FIRST_IMODE vector. */
40223 }
40225 /* Interleave low FIRST_IMODE vectors. */
40227 {
40231 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40234 }
40236 /* Interleave low SECOND_IMODE vectors. */
40238 {
40241 {
40246 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40247 vector. */
40250 }
40253 /* FALLTHRU */
40260 /* Cast the SECOND_IMODE vector back to a vector on original
40261 mode. */
40268 }
40269 }
40271 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40272 all values variable, and none identical. */
40274 static void
40277 {
40283 {
40288 /* FALLTHRU */
40316 half:
40333 /* FALLTHRU */
40339 /* Don't use ix86_expand_vector_init_interleave if we can't
40340 move from GPR to SSE register directly. */
40356 }
40358 {
40370 {
40374 {
40380 else
40381 {
40386 }
40387 }
40390 }
40395 {
40401 }
40403 {
40409 }
40410 else
40412 }
40413 }
40415 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40416 instructions unless MMX_OK is true. */
40418 void
40420 {
40427 rtx x;
40430 {
40440 }
40442 /* Constants are best loaded from the constant pool. */
40444 {
40447 }
40449 /* If all values are identical, broadcast the value. */
40455 /* Values where only one field is non-constant are best loaded from
40456 the pool and overwritten via move later. */
40458 {
40462 one_var))
40467 }
40470 }
40472 void
40474 {
40479 rtx tmp;
40481 = {
40488 };
40490 = {
40497 };
40501 {
40505 {
40510 else
40514 }
40526 else
40532 {
40535 /* For the two element vectors, we implement a VEC_CONCAT with
40536 the extraction of the other element. */
40543 else
40548 }
40557 {
40563 /* tmp = target = A B C D */
40565 /* target = A A B B */
40567 /* target = X A B B */
40569 /* target = A X C D */
40576 /* tmp = target = A B C D */
40578 /* tmp = X B C D */
40580 /* target = A B X D */
40587 /* tmp = target = A B C D */
40589 /* tmp = X B C D */
40591 /* target = A B X D */
40599 }
40607 /* Element 0 handled by vec_merge below. */
40609 {
40612 }
40615 {
40616 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40617 store into element 0, then shuffle them back. */
40634 }
40635 else
40636 {
40637 /* For SSE1, we have to reuse the V4SF code. */
40641 }
40694 half:
40695 /* Compute offset. */
40701 /* Extract the half. */
40705 /* Put val in tmp at elt. */
40708 /* Put it back. */
40714 }
40717 {
40721 }
40722 else
40723 {
40732 }
40733 }
40735 void
40737 {
40741 rtx tmp;
40744 {
40749 /* FALLTHRU */
40762 {
40782 }
40794 {
40796 {
40816 }
40820 }
40821 else
40822 {
40823 /* For SSE1, we have to reuse the V4SF code. */
40827 }
40843 {
40847 else
40851 }
40856 {
40860 else
40864 }
40869 {
40873 else
40877 }
40882 {
40886 else
40890 }
40895 {
40899 else
40903 }
40908 {
40912 else
40916 }
40923 else
40932 else
40941 else
40950 else
40956 /* ??? Could extract the appropriate HImode element and shift. */
40959 }
40962 {
40966 /* Let the rtl optimizers know about the zero extension performed. */
40968 {
40971 }
40974 }
40975 else
40976 {
40983 }
40984 }
40986 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40987 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40988 The upper bits of DEST are undefined, though they shouldn't cause
40989 exceptions (some bits from src or all zeros are ok). */
40991 static void
40993 {
40996 {
41000 else
41018 else
41025 else
41033 {
41038 const1_rtx);
41039 }
41040 else
41041 {
41045 }
41065 else
41087 }
41091 }
41093 /* Expand a vector reduction. FN is the binary pattern to reduce;
41094 DEST is the destination; IN is the input vector. */
41096 void
41098 {
41103 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41107 {
41110 }
41115 {
41120 else
41124 }
41125 }
41126 \f
41127 /* Target hook for scalar_mode_supported_p. */
41128 static bool
41130 {
41135 else
41137 }
41139 /* Implements target hook vector_mode_supported_p. */
41140 static bool
41142 {
41156 }
41158 /* Target hook for c_mode_for_suffix. */
41159 static enum machine_mode
41161 {
41168 }
41170 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41172 We do this in the new i386 backend to maintain source compatibility
41173 with the old cc0-based compiler. */
41175 static tree
41177 tree inputs ATTRIBUTE_UNUSED,
41178 tree clobbers)
41179 {
41181 clobbers);
41183 clobbers);
41185 }
41187 /* Implements target vector targetm.asm.encode_section_info. */
41189 static void ATTRIBUTE_UNUSED
41191 {
41196 }
41198 /* Worker function for REVERSE_CONDITION. */
41200 enum rtx_code
41202 {
41206 }
41208 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41209 to OPERANDS[0]. */
41213 {
41215 {
41218 {
41222 }
41226 }
41228 {
41232 else
41233 {
41234 /* There is no non-popping store to memory for XFmode.
41235 So if we need one, follow the store with a load. */
41238 else
41240 }
41241 }
41242 else
41244 }
41246 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41247 FP status register is set. */
41249 void
41251 {
41253 rtx temp;
41258 {
41263 }
41264 else
41265 {
41270 }
41274 pc_rtx);
41279 }
41281 /* Output code to perform a log1p XFmode calculation. */
41284 {
41290 rtx test;
41296 XFmode));
41310 }
41312 /* Emit code for round calculation. */
41314 {
41321 rtx insn;
41326 {
41338 }
41341 {
41362 }
41370 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41372 /* scratch = fxam(op1) */
41375 UNSPEC_FXAM)));
41376 /* e1 = fabs(op1) */
41379 /* e2 = e1 + 0.5 */
41384 /* res = floor(e2) */
41386 {
41391 }
41392 else
41396 {
41399 {
41406 UNSPEC_TRUNC_NOOP)));
41407 }
41423 }
41425 /* flags = signbit(a) */
41428 /* if (flags) then res = -res */
41432 pc_rtx);
41443 }
41445 /* Output code to perform a Newton-Rhapson approximation of a single precision
41446 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41449 {
41457 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41461 /* x0 = rcp(b) estimate */
41465 UNSPEC_RCP14)));
41466 else
41469 UNSPEC_RCP)));
41471 /* e0 = x0 * b */
41475 /* e0 = x0 * e0 */
41479 /* e1 = x0 + x0 */
41483 /* x1 = e1 - e0 */
41487 /* res = a * x1 */
41490 }
41492 /* Output code to perform a Newton-Rhapson approximation of a
41493 single precision floating point [reciprocal] square root. */
41497 {
41499 REAL_VALUE_TYPE r;
41516 {
41519 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41522 }
41524 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41525 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41529 /* x0 = rsqrt(a) estimate */
41532 unspec)));
41534 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41536 {
41544 /* Handle masked compare. */
41546 {
41548 /* Imm value 0x4 corresponds to not-equal comparison. */
41551 }
41552 else
41553 {
41559 }
41560 }
41562 /* e0 = x0 * a */
41565 /* e1 = e0 * x0 */
41569 /* e2 = e1 - 3. */
41576 /* e3 = -.5 * x0 */
41579 else
41580 /* e3 = -.5 * e0 */
41583 /* ret = e2 * e3 */
41586 }
41588 #ifdef TARGET_SOLARIS
41589 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41591 static void
41593 tree decl)
41594 {
41595 /* With Binutils 2.15, the "@unwind" marker must be specified on
41596 every occurrence of the ".eh_frame" section, not just the first
41597 one. */
41600 {
41604 }
41606 #ifndef USE_GAS
41608 {
41611 }
41612 #endif
41615 }
41618 /* Return the mangling of TYPE if it is an extended fundamental type. */
41622 {
41630 {
41632 /* __float128 is "g". */
41635 /* "long double" or __float80 is "e". */
41639 }
41640 }
41642 /* For 32-bit code we can save PIC register setup by using
41643 __stack_chk_fail_local hidden function instead of calling
41644 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41645 register, so it is better to call __stack_chk_fail directly. */
41647 static tree ATTRIBUTE_UNUSED
41649 {
41650 return TARGET_64BIT
41653 }
41655 /* Select a format to encode pointers in exception handling data. CODE
41656 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41657 true if the symbol may be affected by dynamic relocations.
41659 ??? All x86 object file formats are capable of representing this.
41660 After all, the relocation needed is the same as for the call insn.
41661 Whether or not a particular assembler allows us to enter such, I
41662 guess we'll have to see. */
41663 int
41665 {
41667 {
41674 }
41679 }
41680 \f
41681 /* Expand copysign from SIGN to the positive value ABS_VALUE
41682 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41683 the sign-bit. */
41684 static void
41686 {
41690 {
41697 else
41702 {
41703 /* We need to generate a scalar mode mask in this case. */
41708 }
41709 }
41710 else
41716 }
41718 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41719 mask for masking out the sign-bit is stored in *SMASK, if that is
41720 non-null. */
41721 static rtx
41723 {
41732 else
41736 {
41737 /* We need to generate a scalar mode mask in this case. */
41742 }
41750 }
41752 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41753 swapping the operands if SWAP_OPERANDS is true. The expanded
41754 code is a forward jump to a newly created label in case the
41755 comparison is true. The generated label rtx is returned. */
41756 static rtx
41759 {
41764 {
41768 }
41781 }
41783 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41784 using comparison code CODE. Operands are swapped for the comparison if
41785 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41786 static rtx
41789 {
41795 {
41799 }
41806 }
41808 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41809 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41810 static rtx
41812 {
41813 REAL_VALUE_TYPE TWO52r;
41814 rtx TWO52;
41821 }
41823 /* Expand SSE sequence for computing lround from OP1 storing
41824 into OP0. */
41825 void
41827 {
41828 /* C code for the stuff we're doing below:
41829 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41830 return (long)tmp;
41831 */
41835 rtx adj;
41837 /* load nextafter (0.5, 0.0) */
41842 /* adj = copysign (0.5, op1) */
41846 /* adj = op1 + adj */
41849 /* op0 = (imode)adj */
41851 }
41853 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41854 into OPERAND0. */
41855 void
41857 {
41858 /* C code for the stuff we're doing below (for do_floor):
41859 xi = (long)op1;
41860 xi -= (double)xi > op1 ? 1 : 0;
41861 return xi;
41862 */
41867 /* reg = (long)op1 */
41871 /* freg = (double)reg */
41875 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41886 }
41888 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41889 result in OPERAND0. */
41890 void
41892 {
41893 /* C code for the stuff we're doing below:
41894 xa = fabs (operand1);
41895 if (!isless (xa, 2**52))
41896 return operand1;
41897 xa = xa + 2**52 - 2**52;
41898 return copysign (xa, operand1);
41899 */
41906 /* xa = abs (operand1) */
41909 /* if (!isless (xa, TWO52)) goto label; */
41922 }
41924 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41925 into OPERAND0. */
41926 void
41928 {
41929 /* C code for the stuff we expand below.
41930 double xa = fabs (x), x2;
41931 if (!isless (xa, TWO52))
41932 return x;
41933 xa = xa + TWO52 - TWO52;
41934 x2 = copysign (xa, x);
41935 Compensate. Floor:
41936 if (x2 > x)
41937 x2 -= 1;
41938 Compensate. Ceil:
41939 if (x2 < x)
41940 x2 -= -1;
41941 return x2;
41942 */
41948 /* Temporary for holding the result, initialized to the input
41949 operand to ease control flow. */
41953 /* xa = abs (operand1) */
41956 /* if (!isless (xa, TWO52)) goto label; */
41959 /* xa = xa + TWO52 - TWO52; */
41963 /* xa = copysign (xa, operand1) */
41966 /* generate 1.0 or -1.0 */
41971 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41975 /* We always need to subtract here to preserve signed zero. */
41984 }
41986 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41987 into OPERAND0. */
41988 void
41990 {
41991 /* C code for the stuff we expand below.
41992 double xa = fabs (x), x2;
41993 if (!isless (xa, TWO52))
41994 return x;
41995 x2 = (double)(long)x;
41996 Compensate. Floor:
41997 if (x2 > x)
41998 x2 -= 1;
41999 Compensate. Ceil:
42000 if (x2 < x)
42001 x2 += 1;
42002 if (HONOR_SIGNED_ZEROS (mode))
42003 return copysign (x2, x);
42004 return x2;
42005 */
42011 /* Temporary for holding the result, initialized to the input
42012 operand to ease control flow. */
42016 /* xa = abs (operand1) */
42019 /* if (!isless (xa, TWO52)) goto label; */
42022 /* xa = (double)(long)x */
42027 /* generate 1.0 */
42030 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42045 }
42047 /* Expand SSE sequence for computing round from OPERAND1 storing
42048 into OPERAND0. Sequence that works without relying on DImode truncation
42049 via cvttsd2siq that is only available on 64bit targets. */
42050 void
42052 {
42053 /* C code for the stuff we expand below.
42054 double xa = fabs (x), xa2, x2;
42055 if (!isless (xa, TWO52))
42056 return x;
42057 Using the absolute value and copying back sign makes
42058 -0.0 -> -0.0 correct.
42059 xa2 = xa + TWO52 - TWO52;
42060 Compensate.
42061 dxa = xa2 - xa;
42062 if (dxa <= -0.5)
42063 xa2 += 1;
42064 else if (dxa > 0.5)
42065 xa2 -= 1;
42066 x2 = copysign (xa2, x);
42067 return x2;
42068 */
42074 /* Temporary for holding the result, initialized to the input
42075 operand to ease control flow. */
42079 /* xa = abs (operand1) */
42082 /* if (!isless (xa, TWO52)) goto label; */
42085 /* xa2 = xa + TWO52 - TWO52; */
42089 /* dxa = xa2 - xa; */
42092 /* generate 0.5, 1.0 and -0.5 */
42098 /* Compensate. */
42100 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42105 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42111 /* res = copysign (xa2, operand1) */
42118 }
42120 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42121 into OPERAND0. */
42122 void
42124 {
42125 /* C code for SSE variant we expand below.
42126 double xa = fabs (x), x2;
42127 if (!isless (xa, TWO52))
42128 return x;
42129 x2 = (double)(long)x;
42130 if (HONOR_SIGNED_ZEROS (mode))
42131 return copysign (x2, x);
42132 return x2;
42133 */
42139 /* Temporary for holding the result, initialized to the input
42140 operand to ease control flow. */
42144 /* xa = abs (operand1) */
42147 /* if (!isless (xa, TWO52)) goto label; */
42150 /* x = (double)(long)x */
42162 }
42164 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42165 into OPERAND0. */
42166 void
42168 {
42172 /* C code for SSE variant we expand below.
42173 double xa = fabs (x), x2;
42174 if (!isless (xa, TWO52))
42175 return x;
42176 xa2 = xa + TWO52 - TWO52;
42177 Compensate:
42178 if (xa2 > xa)
42179 xa2 -= 1.0;
42180 x2 = copysign (xa2, x);
42181 return x2;
42182 */
42186 /* Temporary for holding the result, initialized to the input
42187 operand to ease control flow. */
42191 /* xa = abs (operand1) */
42194 /* if (!isless (xa, TWO52)) goto label; */
42197 /* res = xa + TWO52 - TWO52; */
42202 /* generate 1.0 */
42205 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42213 /* res = copysign (res, operand1) */
42220 }
42222 /* Expand SSE sequence for computing round from OPERAND1 storing
42223 into OPERAND0. */
42224 void
42226 {
42227 /* C code for the stuff we're doing below:
42228 double xa = fabs (x);
42229 if (!isless (xa, TWO52))
42230 return x;
42231 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42232 return copysign (xa, x);
42233 */
42239 /* Temporary for holding the result, initialized to the input
42240 operand to ease control flow. */
42248 /* load nextafter (0.5, 0.0) */
42253 /* xa = xa + 0.5 */
42257 /* xa = (double)(int64_t)xa */
42262 /* res = copysign (xa, operand1) */
42269 }
42271 /* Expand SSE sequence for computing round
42272 from OP1 storing into OP0 using sse4 round insn. */
42273 void
42275 {
42284 {
42295 }
42297 /* round (a) = trunc (a + copysign (0.5, a)) */
42299 /* load nextafter (0.5, 0.0) */
42305 /* e1 = copysign (0.5, op1) */
42309 /* e2 = op1 + e1 */
42312 /* res = trunc (e2) */
42317 }
42318 \f
42320 /* Table of valid machine attributes. */
42322 {
42323 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42324 affects_type_identity } */
42325 /* Stdcall attribute says callee is responsible for popping arguments
42326 if they are not variable. */
42329 /* Fastcall attribute says callee is responsible for popping arguments
42330 if they are not variable. */
42333 /* Thiscall attribute says callee is responsible for popping arguments
42334 if they are not variable. */
42337 /* Cdecl attribute says the callee is a normal C declaration */
42340 /* Regparm attribute specifies how many integer arguments are to be
42341 passed in registers. */
42344 /* Sseregparm attribute says we are using x86_64 calling conventions
42345 for FP arguments. */
42348 /* The transactional memory builtins are implicitly regparm or fastcall
42349 depending on the ABI. Override the generic do-nothing attribute that
42350 these builtins were declared with. */
42353 /* force_align_arg_pointer says this function realigns the stack at entry. */
42356 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42361 #endif
42366 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42367 SUBTARGET_ATTRIBUTE_TABLE,
42368 #endif
42369 /* ms_abi and sysv_abi calling convention function attributes. */
42376 /* End element. */
42378 };
42380 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42381 static int
42383 tree vectype,
42385 {
42389 {
42434 }
42435 }
42437 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42438 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42439 insn every time. */
42443 /* Initialize vselect_insn. */
42445 static void
42447 {
42449 rtx x;
42460 }
42462 /* Construct (set target (vec_select op0 (parallel perm))) and
42463 return true if that's a valid instruction in the active ISA. */
42465 static bool
42468 {
42494 }
42496 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42498 static bool
42502 {
42504 rtx x;
42519 }
42521 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42522 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42524 static bool
42526 {
42535 ;
42537 ;
42539 ;
42540 else
42543 /* This is a blend, not a permute. Elements must stay in their
42544 respective lanes. */
42546 {
42550 }
42555 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42556 decision should be extracted elsewhere, so that we only try that
42557 sequence once all budget==3 options have been tried. */
42564 {
42588 /* See if bytes move in pairs so we can use pblendw with
42589 an immediate argument, rather than pblendvb with a vector
42590 argument. */
42593 {
42594 use_pblendvb:
42598 finish_pblendvb:
42604 else
42609 }
42614 /* FALLTHRU */
42616 do_subreg:
42623 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42627 /* See if bytes move in quadruplets. If yes, vpblendd
42628 with immediate can be used. */
42633 {
42634 /* See if bytes move the same in both lanes. If yes,
42635 vpblendw with immediate can be used. */
42640 /* Use vpblendw. */
42645 }
42647 /* Use vpblendd. */
42654 /* See if words move in pairs. If yes, vpblendd can be used. */
42659 {
42660 /* See if words move the same in both lanes. If not,
42661 vpblendvb must be used. */
42664 {
42665 /* Use vpblendvb. */
42675 }
42677 /* Use vpblendw. */
42681 }
42683 /* Use vpblendd. */
42690 /* Use vpblendd. */
42698 }
42700 /* This matches five different patterns with the different modes. */
42708 }
42710 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42711 in terms of the variable form of vpermilps.
42713 Note that we will have already failed the immediate input vpermilps,
42714 which requires that the high and low part shuffle be identical; the
42715 variable form doesn't require that. */
42717 static bool
42719 {
42726 /* We can only permute within the 128-bit lane. */
42728 {
42732 }
42738 {
42741 /* Within each 128-bit lane, the elements of op0 are numbered
42742 from 0 and the elements of op1 are numbered from 4. */
42749 }
42756 }
42758 /* Return true if permutation D can be performed as VMODE permutation
42759 instead. */
42761 static bool
42763 {
42778 else
42784 }
42786 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42787 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42789 static bool
42791 {
42800 {
42802 {
42805 {
42809 /* Use vperm2i128 insn. The pattern uses
42810 V4DImode instead of V2TImode. */
42823 }
42825 }
42826 }
42827 else
42828 {
42830 {
42833 }
42835 {
42839 /* V4DImode should be already handled through
42840 expand_vselect by vpermq instruction. */
42847 {
42848 /* First see if vpermq can be used for
42849 V8SImode/V16HImode/V32QImode. */
42851 {
42859 {
42863 }
42865 }
42867 /* Next see if vpermd can be used. */
42870 }
42871 /* Or if vpermps can be used. */
42876 {
42877 /* vpshufb only works intra lanes, it is not
42878 possible to shuffle bytes in between the lanes. */
42882 }
42883 }
42884 else
42886 }
42894 else
42895 {
42901 else
42905 {
42909 }
42910 }
42921 {
42928 else
42930 }
42931 else
42932 {
42935 }
42940 }
42942 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42943 in a single instruction. */
42945 static bool
42947 {
42951 /* Check plain VEC_SELECT first, because AVX has instructions that could
42952 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42953 input where SEL+CONCAT may not. */
42955 {
42961 {
42967 }
42970 {
42974 }
42976 {
42977 /* Use vpbroadcast{b,w,d}. */
42980 {
42999 /* For other modes prefer other shuffles this function creates. */
43001 }
43003 {
43007 }
43008 }
43013 /* There are plenty of patterns in sse.md that are written for
43014 SEL+CONCAT and are not replicated for a single op. Perhaps
43015 that should be changed, to avoid the nastiness here. */
43017 /* Recognize interleave style patterns, which means incrementing
43018 every other permutation operand. */
43020 {
43023 }
43028 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43030 {
43032 {
43037 }
43042 }
43043 }
43045 /* Finally, try the fully general two operand permute. */
43050 /* Recognize interleave style patterns with reversed operands. */
43052 {
43054 {
43058 else
43061 }
43066 }
43068 /* Try the SSE4.1 blend variable merge instructions. */
43072 /* Try one of the AVX vpermil variable permutations. */
43076 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43077 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43081 /* Try the AVX512F vpermi2 instructions. */
43095 }
43097 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43098 in terms of a pair of pshuflw + pshufhw instructions. */
43100 static bool
43102 {
43110 /* The two permutations only operate in 64-bit lanes. */
43121 /* Emit the pshuflw. */
43128 /* Emit the pshufhw. */
43136 }
43138 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43139 the permutation using the SSSE3 palignr instruction. This succeeds
43140 when all of the elements in PERM fit within one vector and we merely
43141 need to shift them down so that a single vector permutation has a
43142 chance to succeed. */
43144 static bool
43146 {
43153 /* Even with AVX, palignr only operates on 128-bit vectors. */
43159 {
43165 }
43169 /* Given that we have SSSE3, we know we'll be able to implement the
43170 single operand permutation after the palignr with pshufb. */
43185 {
43190 }
43192 /* Test for the degenerate case where the alignment by itself
43193 produces the desired permutation. */
43195 {
43198 }
43204 }
43208 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43209 a two vector permutation into a single vector permutation by using
43210 an interleave operation to merge the vectors. */
43212 static bool
43214 {
43219 rtx seq;
43223 {
43226 }
43228 {
43231 /* For 32-byte modes allow even d->one_operand_p.
43232 The lack of cross-lane shuffling in some instructions
43233 might prevent a single insn shuffle. */
43236 /* If expand_vec_perm_interleave3 can expand this into
43237 a 3 insn sequence, give up and let it be expanded as
43238 3 insn sequence. While that is one insn longer,
43239 it doesn't need a memory operand and in the common
43240 case that both interleave low and high permutations
43241 with the same operands are adjacent needs 4 insns
43242 for both after CSE. */
43245 }
43246 else
43249 /* Examine from whence the elements come. */
43258 {
43261 /* Split the two input vectors into 4 halves. */
43267 /* If the elements from the low halves use interleave low, and similarly
43268 for interleave high. If the elements are from mis-matched halves, we
43269 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43271 {
43272 /* punpckl* */
43274 {
43279 }
43282 }
43284 {
43285 /* punpckh* */
43287 {
43292 }
43295 }
43297 {
43298 /* shufps */
43300 {
43305 }
43307 {
43308 /* shufpd */
43313 }
43314 }
43316 {
43317 /* shufps */
43319 {
43324 }
43326 {
43327 /* shufpd */
43332 }
43333 }
43334 else
43336 }
43337 else
43338 {
43343 /* Split the two input vectors into 8 quarters. */
43349 {
43352 }
43355 {
43359 }
43361 {
43364 }
43367 {
43369 {
43370 /* Attempt to increase the likelihood that dfinal
43371 shuffle will be intra-lane. */
43375 }
43377 /* vperm2f128 or vperm2i128. */
43379 {
43384 }
43389 {
43393 {
43396 }
43397 }
43398 }
43403 {
43404 /* vpunpckl* */
43406 {
43415 }
43416 }
43419 {
43420 /* vpunpckh* */
43422 {
43431 }
43432 }
43433 else
43435 }
43437 /* Use the remapping array set up above to move the elements from their
43438 swizzled locations into their final destinations. */
43441 {
43444 /* If same_halves is true, both halves of the remapped vector are the
43445 same. Avoid cross-lane accesses if possible. */
43447 {
43450 }
43451 else
43453 }
43455 {
43458 }
43462 /* Test if the final remap can be done with a single insn. For V4SFmode or
43463 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43476 {
43479 }
43486 }
43488 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43489 a single vector cross-lane permutation into vpermq followed
43490 by any of the single insn permutations. */
43492 static bool
43494 {
43508 {
43511 }
43514 {
43519 }
43532 {
43539 }
43546 {
43551 ;
43554 else
43556 }
43565 }
43567 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43568 a vector permutation using two instructions, vperm2f128 resp.
43569 vperm2i128 followed by any single in-lane permutation. */
43571 static bool
43573 {
43587 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43588 immediate. For perm < 16 the second permutation uses
43589 d->op0 as first operand, for perm >= 16 it uses d->op1
43590 as first operand. The second operand is the result of
43591 vperm2[fi]128. */
43593 {
43594 /* Ignore permutations which do not move anything cross-lane. */
43596 {
43597 /* The second shuffle for e.g. V4DFmode has
43598 0123 and ABCD operands.
43599 Ignore AB23, as 23 is already in the second lane
43600 of the first operand. */
43602 /* And 01CD, as 01 is in the first lane of the first
43603 operand. */
43605 /* And 4567, as then the vperm2[fi]128 doesn't change
43606 anything on the original 4567 second operand. */
43608 }
43609 else
43610 {
43611 /* The second shuffle for e.g. V4DFmode has
43612 4567 and ABCD operands.
43613 Ignore AB67, as 67 is already in the second lane
43614 of the first operand. */
43616 /* And 45CD, as 45 is in the first lane of the first
43617 operand. */
43619 /* And 0123, as then the vperm2[fi]128 doesn't change
43620 anything on the original 0123 first operand. */
43622 }
43625 {
43631 else
43633 }
43636 {
43640 }
43641 else
43645 {
43649 /* Found a usable second shuffle. dfirst will be
43650 vperm2f128 on d->op0 and d->op1. */
43661 /* And dsecond is some single insn shuffle, taking
43662 d->op0 and result of vperm2f128 (if perm < 16) or
43663 d->op1 and result of vperm2f128 (otherwise). */
43672 }
43674 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43677 }
43680 }
43682 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43683 a two vector permutation using 2 intra-lane interleave insns
43684 and cross-lane shuffle for 32-byte vectors. */
43686 static bool
43688 {
43695 ;
43697 ;
43698 else
43713 {
43717 else
43723 else
43729 else
43735 else
43741 else
43747 else
43752 }
43756 }
43758 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43759 a single vector permutation using a single intra-lane vector
43760 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43761 the non-swapped and swapped vectors together. */
43763 static bool
43765 {
43768 rtx seq;
43773 || TARGET_AVX2
43782 {
43789 }
43824 }
43826 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43827 permutation using two vperm2f128, followed by a vshufpd insn blending
43828 the two vectors together. */
43830 static bool
43832 {
43875 }
43877 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43878 permutation with two pshufb insns and an ior. We should have already
43879 failed all two instruction sequences. */
43881 static bool
43883 {
43897 /* Generate two permutation masks. If the required element is within
43898 the given vector it is shuffled into the proper lane. If the required
43899 element is in the other vector, force a zero into the lane by setting
43900 bit 7 in the permutation mask. */
43903 {
43910 {
43913 }
43914 }
43938 }
43940 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
43941 with two vpshufb insns, vpermq and vpor. We should have already failed
43942 all two or three instruction sequences. */
43944 static bool
43946 {
43961 /* Generate two permutation masks. If the required element is within
43962 the same lane, it is shuffled in. If the required element from the
43963 other lane, force a zero by setting bit 7 in the permutation mask.
43964 In the other mask the mask has non-negative elements if element
43965 is requested from the other lane, but also moved to the other lane,
43966 so that the result of vpshufb can have the two V2TImode halves
43967 swapped. */
43970 {
43975 {
43978 }
43979 }
43988 /* Swap the 128-byte lanes of h into hp. */
43992 const1_rtx));
44009 }
44011 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44012 and extract-odd permutations of two V32QImode and V16QImode operand
44013 with two vpshufb insns, vpor and vpermq. We should have already
44014 failed all two or three instruction sequences. */
44016 static bool
44018 {
44037 /* Generate two permutation masks. In the first permutation mask
44038 the first quarter will contain indexes for the first half
44039 of the op0, the second quarter will contain bit 7 set, third quarter
44040 will contain indexes for the second half of the op0 and the
44041 last quarter bit 7 set. In the second permutation mask
44042 the first quarter will contain bit 7 set, the second quarter
44043 indexes for the first half of the op1, the third quarter bit 7 set
44044 and last quarter indexes for the second half of the op1.
44045 I.e. the first mask e.g. for V32QImode extract even will be:
44046 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44047 (all values masked with 0xf except for -128) and second mask
44048 for extract even will be
44049 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44052 {
44058 {
44061 }
44062 }
44081 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44089 }
44091 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44092 and extract-odd permutations. */
44094 static bool
44096 {
44100 {
44107 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44111 /* Now an unpck[lh]pd will produce the result required. */
44114 else
44120 {
44129 /* Shuffle within the 128-bit lanes to produce:
44130 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44134 /* Shuffle the lanes around to produce:
44135 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44139 /* Shuffle within the 128-bit lanes to produce:
44140 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44143 /* Shuffle within the 128-bit lanes to produce:
44144 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44147 /* Shuffle the lanes around to produce:
44148 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44151 }
44158 /* These are always directly implementable by expand_vec_perm_1. */
44164 else
44165 {
44168 /* We need 2*log2(N)-1 operations to achieve odd/even
44169 with interleave. */
44178 else
44181 }
44187 else
44188 {
44202 else
44205 }
44214 {
44219 else
44224 {
44229 }
44231 }
44239 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44243 /* Now an vpunpck[lh]qdq will produce the result required. */
44246 else
44253 {
44258 else
44263 {
44268 }
44270 }
44281 /* Shuffle the lanes around into
44282 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44290 /* Swap the 2nd and 3rd position in each lane into
44291 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44297 /* Now an vpunpck[lh]qdq will produce
44298 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44302 else
44311 }
44314 }
44316 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44317 extract-even and extract-odd permutations. */
44319 static bool
44321 {
44333 }
44335 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44336 permutations. We assume that expand_vec_perm_1 has already failed. */
44338 static bool
44340 {
44348 {
44351 /* These are special-cased in sse.md so that we can optionally
44352 use the vbroadcast instruction. They expand to two insns
44353 if the input happens to be in a register. */
44360 /* These are always implementable using standard shuffle patterns. */
44365 /* These can be implemented via interleave. We save one insn by
44366 stopping once we have promoted to V4SImode and then use pshufd. */
44369 do
44370 {
44371 rtx dest;
44377 {
44381 }
44388 }
44403 /* For AVX2 broadcasts of the first element vpbroadcast* or
44404 vpermq should be used by expand_vec_perm_1. */
44410 }
44411 }
44413 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44414 broadcast permutations. */
44416 static bool
44418 {
44430 }
44432 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44433 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44434 all the shorter instruction sequences. */
44436 static bool
44438 {
44454 /* Generate 4 permutation masks. If the required element is within
44455 the same lane, it is shuffled in. If the required element from the
44456 other lane, force a zero by setting bit 7 in the permutation mask.
44457 In the other mask the mask has non-negative elements if element
44458 is requested from the other lane, but also moved to the other lane,
44459 so that the result of vpshufb can have the two V2TImode halves
44460 swapped. */
44463 {
44468 }
44474 {
44482 }
44485 {
44487 {
44490 }
44497 }
44499 /* Swap the 128-byte lanes of h[X]. */
44501 {
44507 const1_rtx));
44509 }
44512 {
44514 {
44517 }
44523 }
44526 {
44528 {
44532 }
44535 }
44545 }
44547 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44548 With all of the interface bits taken care of, perform the expansion
44549 in D and return true on success. */
44551 static bool
44553 {
44554 /* Try a single instruction expansion. */
44558 /* Try sequences of two instructions. */
44578 /* Try sequences of three instructions. */
44592 /* Try sequences of four instructions. */
44600 /* ??? Look for narrow permutations whose element orderings would
44601 allow the promotion to a wider mode. */
44603 /* ??? Look for sequences of interleave or a wider permute that place
44604 the data into the correct lanes for a half-vector shuffle like
44605 pshuf[lh]w or vpermilps. */
44607 /* ??? Look for sequences of interleave that produce the desired results.
44608 The combinatorics of punpck[lh] get pretty ugly... */
44613 /* Even longer sequences. */
44618 }
44620 /* If a permutation only uses one operand, make it clear. Returns true
44621 if the permutation references both operands. */
44623 static bool
44625 {
44633 {
44639 {
44642 }
44643 /* The elements of PERM do not suggest that only the first operand
44644 is used, but both operands are identical. Allow easier matching
44645 of the permutation by folding the permutation into the single
44646 input vector. */
44647 /* FALLTHRU */
44658 }
44661 }
44663 bool
44665 {
44670 rtx sel;
44687 {
44692 }
44699 /* If the selector says both arguments are needed, but the operands are the
44700 same, the above tried to expand with one_operand_p and flattened selector.
44701 If that didn't work, retry without one_operand_p; we succeeded with that
44702 during testing. */
44704 {
44708 }
44711 }
44713 /* Implement targetm.vectorize.vec_perm_const_ok. */
44715 static bool
44718 {
44727 /* Given sufficient ISA support we can just return true here
44728 for selected vector modes. */
44731 /* All implementable with a single vpermi2 insn. */
44734 {
44735 /* All implementable with a single vpperm insn. */
44738 /* All implementable with 2 pshufb + 1 ior. */
44741 /* All implementable with shufpd or unpck[lh]pd. */
44744 }
44746 /* Extract the values from the vector CST into the permutation
44747 array in D. */
44750 {
44754 }
44756 /* For all elements from second vector, fold the elements to first. */
44761 /* Check whether the mask can be applied to the vector type. */
44764 /* Implementable with shufps or pshufd. */
44768 /* Otherwise we have to go through the motions and see if we can
44769 figure out how to generate the requested permutation. */
44780 }
44782 void
44784 {
44799 /* We'll either be able to implement the permutation directly... */
44803 /* ... or we use the special-case patterns. */
44805 }
44807 static void
44809 {
44824 {
44827 }
44829 /* Note that for AVX this isn't one instruction. */
44832 }
44835 /* Expand a vector operation CODE for a V*QImode in terms of the
44836 same operation on V*HImode. */
44838 void
44840 {
44852 {
44865 }
44869 {
44871 /* Unpack data such that we've got a source byte in each low byte of
44872 each word. We don't care what goes into the high byte of each word.
44873 Rather than trying to get zero in there, most convenient is to let
44874 it be a copy of the low byte. */
44879 /* FALLTHRU */
44891 /* FALLTHRU */
44901 }
44903 /* Perform the operation. */
44910 /* Merge the data back into the right place. */
44920 {
44921 /* For SSE2, we used an full interleave, so the desired
44922 results are in the even elements. */
44925 }
44926 else
44927 {
44928 /* For AVX, the interleave used above was not cross-lane. So the
44929 extraction is evens but with the second and third quarter swapped.
44930 Happily, that is even one insn shorter than even extraction. */
44933 }
44940 }
44942 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
44943 if op is CONST_VECTOR with all odd elements equal to their
44944 preceding element. */
44946 static bool
44948 {
44958 }
44960 void
44963 {
44966 rtx x;
44974 /* We only play even/odd games with vectors of SImode. */
44977 /* If we're looking for the odd results, shift those members down to
44978 the even slots. For some cpus this is faster than a PSHUFD. */
44980 {
44981 /* For XOP use vpmacsdqh, but only for smult, as it is only
44982 signed. */
44984 {
44988 }
44999 }
45002 {
45005 else
45007 }
45009 {
45012 else
45014 }
45019 else
45020 {
45023 /* The easiest way to implement this without PMULDQ is to go through
45024 the motions as if we are performing a full 64-bit multiply. With
45025 the exception that we need to do less shuffling of the elements. */
45027 /* Compute the sign-extension, aka highparts, of the two operands. */
45033 /* Multiply LO(A) * HI(B), and vice-versa. */
45039 /* Multiply LO(A) * LO(B). */
45043 /* Combine and shift the highparts into place. */
45048 /* Combine high and low parts. */
45051 }
45053 }
45055 void
45058 {
45064 {
45069 {
45070 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45071 shuffle the elements once so that all elements are in the right
45072 place for immediate use: { A C B D }. */
45077 }
45078 else
45079 {
45080 /* Put the elements into place for the multiply. */
45084 }
45089 /* Shuffle the elements between the lanes. After this we
45090 have { A B E F | C D G H } for each operand. */
45100 /* Shuffle the elements within the lanes. After this we
45101 have { A A B B | C C D D } or { E E F F | G G H H }. */
45139 }
45140 }
45142 void
45144 {
45154 /* Move the results in element 2 down to element 1; we don't care
45155 what goes in elements 2 and 3. Then we can merge the parts
45156 back together with an interleave.
45158 Note that two other sequences were tried:
45159 (1) Use interleaves at the start instead of psrldq, which allows
45160 us to use a single shufps to merge things back at the end.
45161 (2) Use shufps here to combine the two vectors, then pshufd to
45162 put the elements in the correct order.
45163 In both cases the cost of the reformatting stall was too high
45164 and the overall sequence slower. */
45175 }
45177 void
45179 {
45184 {
45185 /* op1: A,B,C,D, op2: E,F,G,H */
45194 /* t1: B,A,D,C */
45201 /* t2: (B*E),(A*F),(D*G),(C*H) */
45204 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45207 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45210 /* Multiply lower parts and add all */
45212 emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2)));
45214 }
45215 else
45216 {
45221 {
45224 }
45226 {
45229 }
45231 {
45234 }
45235 else
45239 /* Multiply low parts. */
45243 /* Shift input vectors right 32 bits so we can multiply high parts. */
45248 /* Multiply high parts by low parts. */
45254 /* Combine and shift the highparts back. */
45258 /* Combine high and low parts. */
45260 }
45264 }
45266 /* Calculate integer abs() using only SSE2 instructions. */
45268 void
45270 {
45275 {
45276 /* For 32-bit signed integer X, the best way to calculate the absolute
45277 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45289 /* For 16-bit signed integer X, the best way to calculate the absolute
45290 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45298 /* For 8-bit signed integer X, the best way to calculate the absolute
45299 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45300 as SSE2 provides the PMINUB insn. */
45310 }
45314 }
45316 /* Expand an insert into a vector register through pinsr insn.
45317 Return true if successful. */
45319 bool
45321 {
45329 {
45332 }
45338 {
45343 {
45350 {
45382 }
45396 }
45400 }
45401 }
45402 \f
45403 /* This function returns the calling abi specific va_list type node.
45404 It returns the FNDECL specific va_list type. */
45406 static tree
45408 {
45415 else
45417 }
45419 /* Returns the canonical va_list type specified by TYPE. If there
45420 is no valid TYPE provided, it return NULL_TREE. */
45422 static tree
45424 {
45427 /* Resolve references and pointers to va_list type. */
45436 {
45441 {
45442 /* If va_list is an array type, the argument may have decayed
45443 to a pointer type, e.g. by being passed to another function.
45444 In that case, unwrap both types so that we can compare the
45445 underlying records. */
45448 {
45451 }
45452 }
45459 {
45460 /* If va_list is an array type, the argument may have decayed
45461 to a pointer type, e.g. by being passed to another function.
45462 In that case, unwrap both types so that we can compare the
45463 underlying records. */
45466 {
45469 }
45470 }
45477 {
45478 /* If va_list is an array type, the argument may have decayed
45479 to a pointer type, e.g. by being passed to another function.
45480 In that case, unwrap both types so that we can compare the
45481 underlying records. */
45484 {
45487 }
45488 }
45492 }
45494 }
45496 /* Iterate through the target-specific builtin types for va_list.
45497 IDX denotes the iterator, *PTREE is set to the result type of
45498 the va_list builtin, and *PNAME to its internal type.
45499 Returns zero if there is no element for this index, otherwise
45500 IDX should be increased upon the next call.
45501 Note, do not iterate a base builtin's name like __builtin_va_list.
45502 Used from c_common_nodes_and_builtins. */
45504 static int
45506 {
45508 {
45510 {
45523 }
45524 }
45527 }
45529 #undef TARGET_SCHED_DISPATCH
45530 #define TARGET_SCHED_DISPATCH has_dispatch
45531 #undef TARGET_SCHED_DISPATCH_DO
45532 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45533 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45534 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45535 #undef TARGET_SCHED_REORDER
45536 #define TARGET_SCHED_REORDER ix86_sched_reorder
45537 #undef TARGET_SCHED_ADJUST_PRIORITY
45538 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45539 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45540 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45541 ix86_dependencies_evaluation_hook
45543 /* The size of the dispatch window is the total number of bytes of
45544 object code allowed in a window. */
45545 #define DISPATCH_WINDOW_SIZE 16
45547 /* Number of dispatch windows considered for scheduling. */
45548 #define MAX_DISPATCH_WINDOWS 3
45550 /* Maximum number of instructions in a window. */
45551 #define MAX_INSN 4
45553 /* Maximum number of immediate operands in a window. */
45554 #define MAX_IMM 4
45556 /* Maximum number of immediate bits allowed in a window. */
45557 #define MAX_IMM_SIZE 128
45559 /* Maximum number of 32 bit immediates allowed in a window. */
45560 #define MAX_IMM_32 4
45562 /* Maximum number of 64 bit immediates allowed in a window. */
45563 #define MAX_IMM_64 2
45565 /* Maximum total of loads or prefetches allowed in a window. */
45566 #define MAX_LOAD 2
45568 /* Maximum total of stores allowed in a window. */
45569 #define MAX_STORE 1
45571 #undef BIG
45572 #define BIG 100
45575 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45578 disp_load,
45579 disp_store,
45580 disp_load_store,
45581 disp_prefetch,
45582 disp_imm,
45583 disp_imm_32,
45584 disp_imm_64,
45585 disp_branch,
45586 disp_cmp,
45587 disp_jcc,
45588 disp_last
45589 };
45591 /* Number of allowable groups in a dispatch window. It is an array
45592 indexed by dispatch_group enum. 100 is used as a big number,
45593 because the number of these kind of operations does not have any
45594 effect in dispatch window, but we need them for other reasons in
45595 the table. */
45598 };
45604 };
45606 /* Instruction path. */
45612 last_path
45613 };
45615 /* sched_insn_info defines a window to the instructions scheduled in
45616 the basic block. It contains a pointer to the insn_info table and
45617 the instruction scheduled.
45619 Windows are allocated for each basic block and are linked
45620 together. */
45622 rtx insn;
45629 /* Linked list of dispatch windows. This is a two way list of
45630 dispatch windows of a basic block. It contains information about
45631 the number of uops in the window and the total number of
45632 instructions and of bytes in the object code for this dispatch
45633 window. */
45651 /* Immediate valuse used in an insn. */
45653 {
45662 /* Get dispatch group of insn. */
45664 static enum dispatch_group
45666 {
45682 }
45684 /* Return true if insn is a compare instruction. */
45686 static bool
45688 {
45696 }
45698 /* Return true if a dispatch violation encountered. */
45700 static bool
45702 {
45706 }
45708 /* Return true if insn is a branch instruction. */
45710 static bool
45712 {
45714 }
45716 /* Return true if insn is a prefetch instruction. */
45718 static bool
45720 {
45722 }
45724 /* This function initializes a dispatch window and the list container holding a
45725 pointer to the window. */
45727 static void
45729 {
45735 else
45753 {
45759 }
45761 }
45763 /* This function allocates and initializes a dispatch window and the
45764 list container holding a pointer to the window. */
45768 {
45773 }
45775 /* This routine initializes the dispatch scheduling information. It
45776 initiates building dispatch scheduler tables and constructs the
45777 first dispatch window. */
45779 static void
45781 {
45782 /* Allocate a dispatch list and a window. */
45787 }
45789 /* This function returns true if a branch is detected. End of a basic block
45790 does not have to be a branch, but here we assume only branches end a
45791 window. */
45793 static bool
45795 {
45797 }
45799 /* This function is called when the end of a window processing is reached. */
45801 static void
45803 {
45806 {
45811 }
45813 }
45815 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45816 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45817 for 48 bytes of instructions. Note that these windows are not dispatch
45818 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45822 {
45824 {
45829 }
45835 }
45837 /* Increment the number of immediate operands of an instruction. */
45839 static int
45841 {
45846 {
45853 else
45864 {
45867 }
45872 }
45875 }
45877 /* Compute number of immediate operands of an instruction. */
45879 static void
45881 {
45884 }
45886 /* Return total size of immediate operands of an instruction along with number
45887 of corresponding immediate-operands. It initializes its parameters to zero
45888 befor calling FIND_CONSTANT.
45889 INSN is the input instruction. IMM is the total of immediates.
45890 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45891 bit immediates. */
45893 static int
45895 {
45903 }
45905 /* This function indicates if an operand of an instruction is an
45906 immediate. */
45908 static bool
45910 {
45919 }
45921 /* Return single or double path for instructions. */
45923 static enum insn_path
45925 {
45935 }
45937 /* Return insn dispatch group. */
45939 static enum dispatch_group
45941 {
45959 }
45961 /* Count number of GROUP restricted instructions in a dispatch
45962 window WINDOW_LIST. */
45964 static int
45966 {
45977 {
45996 }
46009 }
46011 /* This function returns true if insn satisfies dispatch rules on the
46012 last window scheduled. */
46014 static bool
46016 {
46024 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46025 instructions should be given the lowest priority in the
46026 scheduling process in Haifa scheduler to make sure they will be
46027 scheduled in the same dispatch window as the reference to them. */
46031 /* Check nonrestricted. */
46035 /* Get last dispatch window. */
46040 {
46045 /* Window 1 is full. Go for next window. */
46047 }
46054 /* See if it fits in the first window. */
46056 {
46057 /* The first widow should have only single and double path
46058 uops. */
46064 }
46066 }
46068 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46069 dispatch window WINDOW_LIST. */
46071 static void
46073 {
46091 /* Initialize window with new instruction. */
46112 {
46115 }
46116 }
46118 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46119 If the total bytes of instructions or the number of instructions in
46120 the window exceed allowable, it allocates a new window. */
46122 static void
46124 {
46147 /* Get the last dispatch window. */
46155 else
46158 /* If current window is full, get a new window.
46159 Window number zero is full, if MAX_INSN uops are scheduled in it.
46160 Window number one is full, if window zero's bytes plus window
46161 one's bytes is 32, or if the bytes of the new instruction added
46162 to the total makes it greater than 48, or it has already MAX_INSN
46163 instructions in it. */
46172 {
46175 }
46178 {
46182 {
46185 }
46186 }
46188 {
46193 {
46196 }
46199 }
46200 else
46204 {
46205 /* End of basic block is reached do end-basic-block process. */
46208 }
46209 }
46211 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46213 DEBUG_FUNCTION static void
46215 {
46221 else
46235 {
46238 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46244 }
46245 }
46247 /* Print to stdout a dispatch window. */
46249 DEBUG_FUNCTION void
46251 {
46253 }
46255 /* Print INSN dispatch information to FILE. */
46257 DEBUG_FUNCTION static void
46259 {
46282 }
46284 /* Print to STDERR the status of the ready list with respect to
46285 dispatch windows. */
46287 DEBUG_FUNCTION void
46289 {
46297 }
46299 /* This routine is the driver of the dispatch scheduler. */
46301 static void
46303 {
46308 }
46310 /* Return TRUE if Dispatch Scheduling is supported. */
46312 static bool
46314 {
46318 {
46334 }
46337 }
46339 /* Implementation of reassociation_width target hook used by
46340 reassoc phase to identify parallelism level in reassociated
46341 tree. Statements tree_code is passed in OPC. Arguments type
46342 is passed in MODE.
46344 Currently parallel reassociation is enabled for Atom
46345 processors only and we set reassociation width to be 2
46346 because Atom may issue up to 2 instructions per cycle.
46348 Return value should be fixed if parallel reassociation is
46349 enabled for other processors. */
46351 static int
46354 {
46363 }
46365 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46366 place emms and femms instructions. */
46368 static enum machine_mode
46370 {
46375 {
46392 else
46404 /* FALLTHRU */
46408 }
46409 }
46411 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46412 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46413 256bit and 128bit vectors. */
46415 static unsigned int
46417 {
46420 }
46422 \f
46424 /* Return class of registers which could be used for pseudo of MODE
46425 and of class RCLASS for spilling instead of memory. Return NO_REGS
46426 if it is not possible or non-profitable. */
46427 static reg_class_t
46429 {
46435 }
46437 /* Implement targetm.vectorize.init_cost. */
46441 {
46445 }
46447 /* Implement targetm.vectorize.add_stmt_cost. */
46449 static unsigned
46453 {
46460 /* Statements in an inner loop relative to the loop being
46461 vectorized are weighted more heavily. The value here is
46462 arbitrary and could potentially be improved with analysis. */
46470 }
46472 /* Implement targetm.vectorize.finish_cost. */
46474 static void
46477 {
46482 }
46484 /* Implement targetm.vectorize.destroy_cost_data. */
46486 static void
46488 {
46490 }
46492 /* Validate target specific memory model bits in VAL. */
46494 static unsigned HOST_WIDE_INT
46496 {
46503 {
46507 }
46510 {
46514 }
46516 {
46520 }
46522 }
46524 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46525 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46526 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46527 or number of vecsize_mangle variants that should be emitted. */
46529 static int
46533 {
46540 {
46544 }
46549 {
46556 /* case SCmode: */
46557 /* case DCmode: */
46563 }
46565 tree t;
46569 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46571 {
46578 /* case SCmode: */
46579 /* case DCmode: */
46585 }
46588 {
46589 /* Parse here processor clause. If not present, default to 'b'. */
46591 }
46593 {
46594 /* If the function isn't exported, we can pick up just one ISA
46595 for the clones. */
46600 else
46603 }
46604 else
46605 {
46608 }
46610 {
46623 }
46625 {
46628 else
46633 }
46635 }
46637 /* Add target attribute to SIMD clone NODE if needed. */
46639 static void
46641 {
46645 {
46660 }
46670 }
46672 /* If SIMD clone NODE can't be used in a vectorized loop
46673 in current function, return -1, otherwise return a badness of using it
46674 (0 if it is most desirable from vecsize_mangle point of view, 1
46675 slightly less desirable, etc.). */
46677 static int
46679 {
46681 {
46699 }
46700 }
46702 /* This function gives out the number of memory references.
46703 This value determines the unrolling factor for
46704 bdver3 and bdver4 architectures. */
46706 static int
46708 {
46710 {
46719 else
46721 }
46723 }
46725 /* This function adjusts the unroll factor based on
46726 the hardware capabilities. For ex, bdver3 has
46727 a loop buffer which makes unrolling of smaller
46728 loops less important. This function decides the
46729 unroll factor using number of memory references
46730 (value 32 is used) as a heuristic. */
46732 static unsigned
46734 {
46736 rtx insn;
46743 /* Count the number of memory references within the loop body. */
46746 {
46750 }
46757 }
46760 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46762 static bool
46764 {
46765 /* For x87 floating point with standard excess precision handling,
46766 there is no adddf3 pattern (since x87 floating point only has
46767 XFmode operations) so the default hook implementation gets this
46768 wrong. */
46770 }
46772 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46774 static void
46776 {
46781 {
46796 hold_fnclex);
46810 }
46812 {
46821 mxcsr_orig_var,
46831 ldmxcsr_hold_call);
46834 else
46839 ldmxcsr_clear_call);
46840 else
46844 stxmcsr_update_call);
46846 {
46852 exceptions_assign);
46853 }
46854 else
46859 ldmxcsr_update_call);
46860 }
46861 tree atomic_feraiseexcept
46866 atomic_feraiseexcept_call);
46867 }
46869 /* Initialize the GCC target structure. */
46870 #undef TARGET_RETURN_IN_MEMORY
46871 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46873 #undef TARGET_LEGITIMIZE_ADDRESS
46874 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46876 #undef TARGET_ATTRIBUTE_TABLE
46877 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46878 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46879 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46880 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46881 # undef TARGET_MERGE_DECL_ATTRIBUTES
46882 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46883 #endif
46885 #undef TARGET_COMP_TYPE_ATTRIBUTES
46886 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46888 #undef TARGET_INIT_BUILTINS
46889 #define TARGET_INIT_BUILTINS ix86_init_builtins
46890 #undef TARGET_BUILTIN_DECL
46891 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46892 #undef TARGET_EXPAND_BUILTIN
46893 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46895 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46896 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46897 ix86_builtin_vectorized_function
46899 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46900 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46902 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46903 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46905 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46906 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46908 #undef TARGET_BUILTIN_RECIPROCAL
46909 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46911 #undef TARGET_ASM_FUNCTION_EPILOGUE
46912 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
46914 #undef TARGET_ENCODE_SECTION_INFO
46915 #ifndef SUBTARGET_ENCODE_SECTION_INFO
46916 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
46917 #else
46918 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
46919 #endif
46921 #undef TARGET_ASM_OPEN_PAREN
46923 #undef TARGET_ASM_CLOSE_PAREN
46926 #undef TARGET_ASM_BYTE_OP
46927 #define TARGET_ASM_BYTE_OP ASM_BYTE
46929 #undef TARGET_ASM_ALIGNED_HI_OP
46930 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
46931 #undef TARGET_ASM_ALIGNED_SI_OP
46932 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
46933 #ifdef ASM_QUAD
46934 #undef TARGET_ASM_ALIGNED_DI_OP
46935 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
46936 #endif
46938 #undef TARGET_PROFILE_BEFORE_PROLOGUE
46939 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
46941 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
46942 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
46944 #undef TARGET_ASM_UNALIGNED_HI_OP
46945 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
46946 #undef TARGET_ASM_UNALIGNED_SI_OP
46947 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
46948 #undef TARGET_ASM_UNALIGNED_DI_OP
46949 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
46951 #undef TARGET_PRINT_OPERAND
46952 #define TARGET_PRINT_OPERAND ix86_print_operand
46953 #undef TARGET_PRINT_OPERAND_ADDRESS
46954 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
46955 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
46956 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
46957 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
46958 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
46960 #undef TARGET_SCHED_INIT_GLOBAL
46961 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
46962 #undef TARGET_SCHED_ADJUST_COST
46963 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
46964 #undef TARGET_SCHED_ISSUE_RATE
46965 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
46966 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
46967 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
46968 ia32_multipass_dfa_lookahead
46969 #undef TARGET_SCHED_MACRO_FUSION_P
46970 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
46971 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
46972 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
46974 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
46975 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
46977 #undef TARGET_MEMMODEL_CHECK
46978 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
46980 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
46981 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
46983 #ifdef HAVE_AS_TLS
46984 #undef TARGET_HAVE_TLS
46985 #define TARGET_HAVE_TLS true
46986 #endif
46987 #undef TARGET_CANNOT_FORCE_CONST_MEM
46988 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
46989 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
46990 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
46992 #undef TARGET_DELEGITIMIZE_ADDRESS
46993 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
46995 #undef TARGET_MS_BITFIELD_LAYOUT_P
46996 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
46998 #if TARGET_MACHO
46999 #undef TARGET_BINDS_LOCAL_P
47000 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
47001 #endif
47002 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47003 #undef TARGET_BINDS_LOCAL_P
47004 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
47005 #endif
47007 #undef TARGET_ASM_OUTPUT_MI_THUNK
47008 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47009 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47010 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47012 #undef TARGET_ASM_FILE_START
47013 #define TARGET_ASM_FILE_START x86_file_start
47015 #undef TARGET_OPTION_OVERRIDE
47016 #define TARGET_OPTION_OVERRIDE ix86_option_override
47018 #undef TARGET_REGISTER_MOVE_COST
47019 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47020 #undef TARGET_MEMORY_MOVE_COST
47021 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47022 #undef TARGET_RTX_COSTS
47023 #define TARGET_RTX_COSTS ix86_rtx_costs
47024 #undef TARGET_ADDRESS_COST
47025 #define TARGET_ADDRESS_COST ix86_address_cost
47027 #undef TARGET_FIXED_CONDITION_CODE_REGS
47028 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47029 #undef TARGET_CC_MODES_COMPATIBLE
47030 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47032 #undef TARGET_MACHINE_DEPENDENT_REORG
47033 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47035 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47036 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47038 #undef TARGET_BUILD_BUILTIN_VA_LIST
47039 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47041 #undef TARGET_FOLD_BUILTIN
47042 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47044 #undef TARGET_COMPARE_VERSION_PRIORITY
47045 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47047 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47048 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47049 ix86_generate_version_dispatcher_body
47051 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47052 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47053 ix86_get_function_versions_dispatcher
47055 #undef TARGET_ENUM_VA_LIST_P
47056 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47058 #undef TARGET_FN_ABI_VA_LIST
47059 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47061 #undef TARGET_CANONICAL_VA_LIST_TYPE
47062 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47064 #undef TARGET_EXPAND_BUILTIN_VA_START
47065 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47067 #undef TARGET_MD_ASM_CLOBBERS
47068 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47070 #undef TARGET_PROMOTE_PROTOTYPES
47071 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47072 #undef TARGET_SETUP_INCOMING_VARARGS
47073 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47074 #undef TARGET_MUST_PASS_IN_STACK
47075 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47076 #undef TARGET_FUNCTION_ARG_ADVANCE
47077 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47078 #undef TARGET_FUNCTION_ARG
47079 #define TARGET_FUNCTION_ARG ix86_function_arg
47080 #undef TARGET_FUNCTION_ARG_BOUNDARY
47081 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47082 #undef TARGET_PASS_BY_REFERENCE
47083 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47084 #undef TARGET_INTERNAL_ARG_POINTER
47085 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47086 #undef TARGET_UPDATE_STACK_BOUNDARY
47087 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47088 #undef TARGET_GET_DRAP_RTX
47089 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47090 #undef TARGET_STRICT_ARGUMENT_NAMING
47091 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47092 #undef TARGET_STATIC_CHAIN
47093 #define TARGET_STATIC_CHAIN ix86_static_chain
47094 #undef TARGET_TRAMPOLINE_INIT
47095 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47096 #undef TARGET_RETURN_POPS_ARGS
47097 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47099 #undef TARGET_LEGITIMATE_COMBINED_INSN
47100 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47102 #undef TARGET_ASAN_SHADOW_OFFSET
47103 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47105 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47106 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47108 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47109 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47111 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47112 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47114 #undef TARGET_C_MODE_FOR_SUFFIX
47115 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47117 #ifdef HAVE_AS_TLS
47118 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47119 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47120 #endif
47122 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47123 #undef TARGET_INSERT_ATTRIBUTES
47124 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47125 #endif
47127 #undef TARGET_MANGLE_TYPE
47128 #define TARGET_MANGLE_TYPE ix86_mangle_type
47130 #if !TARGET_MACHO
47131 #undef TARGET_STACK_PROTECT_FAIL
47132 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47133 #endif
47135 #undef TARGET_FUNCTION_VALUE
47136 #define TARGET_FUNCTION_VALUE ix86_function_value
47138 #undef TARGET_FUNCTION_VALUE_REGNO_P
47139 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47141 #undef TARGET_PROMOTE_FUNCTION_MODE
47142 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47144 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47145 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47147 #undef TARGET_INSTANTIATE_DECLS
47148 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47150 #undef TARGET_SECONDARY_RELOAD
47151 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47153 #undef TARGET_CLASS_MAX_NREGS
47154 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47156 #undef TARGET_PREFERRED_RELOAD_CLASS
47157 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47158 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47159 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47160 #undef TARGET_CLASS_LIKELY_SPILLED_P
47161 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47163 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47164 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47165 ix86_builtin_vectorization_cost
47166 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47167 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47168 ix86_vectorize_vec_perm_const_ok
47169 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47170 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47171 ix86_preferred_simd_mode
47172 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47173 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47174 ix86_autovectorize_vector_sizes
47175 #undef TARGET_VECTORIZE_INIT_COST
47176 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47177 #undef TARGET_VECTORIZE_ADD_STMT_COST
47178 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47179 #undef TARGET_VECTORIZE_FINISH_COST
47180 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47181 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47182 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47184 #undef TARGET_SET_CURRENT_FUNCTION
47185 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47187 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47188 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47190 #undef TARGET_OPTION_SAVE
47191 #define TARGET_OPTION_SAVE ix86_function_specific_save
47193 #undef TARGET_OPTION_RESTORE
47194 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47196 #undef TARGET_OPTION_PRINT
47197 #define TARGET_OPTION_PRINT ix86_function_specific_print
47199 #undef TARGET_OPTION_FUNCTION_VERSIONS
47200 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47202 #undef TARGET_CAN_INLINE_P
47203 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47205 #undef TARGET_EXPAND_TO_RTL_HOOK
47206 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47208 #undef TARGET_LEGITIMATE_ADDRESS_P
47209 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47211 #undef TARGET_LRA_P
47212 #define TARGET_LRA_P hook_bool_void_true
47214 #undef TARGET_REGISTER_PRIORITY
47215 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47217 #undef TARGET_REGISTER_USAGE_LEVELING_P
47218 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47220 #undef TARGET_LEGITIMATE_CONSTANT_P
47221 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47223 #undef TARGET_FRAME_POINTER_REQUIRED
47224 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47226 #undef TARGET_CAN_ELIMINATE
47227 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47229 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47230 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47232 #undef TARGET_ASM_CODE_END
47233 #define TARGET_ASM_CODE_END ix86_code_end
47235 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47236 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47238 #if TARGET_MACHO
47239 #undef TARGET_INIT_LIBFUNCS
47240 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47241 #endif
47243 #undef TARGET_LOOP_UNROLL_ADJUST
47244 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47246 #undef TARGET_SPILL_CLASS
47247 #define TARGET_SPILL_CLASS ix86_spill_class
47249 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47250 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47251 ix86_simd_clone_compute_vecsize_and_simdlen
47253 #undef TARGET_SIMD_CLONE_ADJUST
47254 #define TARGET_SIMD_CLONE_ADJUST \
47255 ix86_simd_clone_adjust
47257 #undef TARGET_SIMD_CLONE_USABLE
47258 #define TARGET_SIMD_CLONE_USABLE \
47259 ix86_simd_clone_usable
47261 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47262 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47263 ix86_float_exceptions_rounding_supported_p
47266 \f