| blob | 1b488fe5dbc27a1bede64d646271861022ececa8 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
306 rtx *);
367 {
368 rtx match;
369 rtx replacement;
370 rtx insn;
373 /* Nonzero iff INSN is between START and END, inclusive. */
374 #define INSN_IN_RANGE_P(INSN, START, END) \
375 (INSN_UID (INSN) < max_uid_for_loop \
376 && INSN_LUID (INSN) >= INSN_LUID (START) \
377 && INSN_LUID (INSN) <= INSN_LUID (END))
379 /* Indirect_jump_in_function is computed once per function. */
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
412 {
414 rtx insn;
417 {
420 /* Don't assign luids to line-number NOTEs, so that the distance in
421 luids between two insns is not affected by -g. */
425 else
426 /* Give a line number note the same luid as preceding insn. */
428 }
430 }
431 \f
432 /* Entry point of this file. Perform loop optimization
433 on the current function. F is the first insn of the function
434 and DUMPFILE is a stream for output of a trace of actions taken
435 (or 0 if none should be output). */
437 void
439 {
440 rtx insn;
455 /* Count the number of loops. */
459 {
462 max_loop_num++;
463 }
465 /* Don't waste time if no loops. */
471 /* Get size to use for tables indexed by uids.
472 Leave some space for labels allocated by find_and_verify_loops. */
478 /* Allocate storage for array of loops. */
481 /* Find and process each loop.
482 First, find them, and record them in order of their beginnings. */
485 /* Allocate and initialize auxiliary loop information. */
490 /* Now find all register lifetimes. This must be done after
491 find_and_verify_loops, because it might reorder the insns in the
492 function. */
495 /* This must occur after reg_scan so that registers created by gcse
496 will have entries in the register tables.
498 We could have added a call to reg_scan after gcse_main in toplev.c,
499 but moving this call to init_alias_analysis is more efficient. */
502 /* See if we went too far. Note that get_max_uid already returns
503 one more that the maximum uid of all insn. */
506 /* Now reset it to the actual size we need. See above. */
509 /* find_and_verify_loops has already called compute_luids, but it
510 might have rearranged code afterwards, so we need to recompute
511 the luids now. */
514 /* Don't leave gaps in uid_luid for insns that have been
515 deleted. It is possible that the first or last insn
516 using some register has been deleted by cross-jumping.
517 Make sure that uid_luid for that former insn's uid
518 points to the general area where that insn used to be. */
520 {
524 }
529 /* Determine if the function has indirect jump. On some systems
530 this prevents low overhead loop instructions from being used. */
533 /* Now scan the loops, last ones first, since this means inner ones are done
534 before outer ones. */
536 {
540 {
543 }
544 }
548 /* Clean up. */
556 }
557 \f
558 /* Returns the next insn, in execution order, after INSN. START and
559 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
560 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
561 insn-stream; it is used with loops that are entered near the
562 bottom. */
564 static rtx
566 {
570 {
572 /* Go to the top of the loop, and continue there. */
574 else
575 /* We're done. */
577 }
580 /* We're done. */
584 }
586 /* Find any register references hidden inside X and add them to
587 the dependency list DEPS. This is used to look inside CLOBBER (MEM
588 when checking whether a PARALLEL can be pulled out of a loop. */
590 static rtx
592 {
596 else
597 {
601 {
607 }
608 }
610 }
612 /* Optimize one loop described by LOOP. */
614 /* ??? Could also move memory writes out of loops if the destination address
615 is invariant, the source is invariant, the memory write is not volatile,
616 and if we can prove that no read inside the loop can read this address
617 before the write occurs. If there is a read of this address after the
618 write, then we can also mark the memory read as invariant. */
620 static void
622 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
647 /* Nonzero if we are scanning instructions in a sub-loop. */
656 /* Determine whether this loop starts with a jump down to a test at
657 the end. This will occur for a small number of loops with a test
658 that is too complex to duplicate in front of the loop.
660 We search for the first insn or label in the loop, skipping NOTEs.
661 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
662 (because we might have a loop executed only once that contains a
663 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
664 (in case we have a degenerate loop).
666 Note that if we mistakenly think that a loop is entered at the top
667 when, in fact, it is entered at the exit test, the only effect will be
668 slightly poorer optimization. Making the opposite error can generate
669 incorrect code. Since very few loops now start with a jump to the
670 exit test, the code here to detect that case is very conservative. */
673 p != loop_end
679 ;
683 /* If loop end is the end of the current function, then emit a
684 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
685 note insn. This is the position we use when sinking insns out of
686 the loop. */
689 else
692 /* Set up variables describing this loop. */
696 /* If loop has a jump before the first label,
697 the true entry is the target of that jump.
698 Start scan from there.
699 But record in LOOP->TOP the place where the end-test jumps
700 back to so we can scan that after the end of the loop. */
702 /* Loop entry must be unconditional jump (and not a RETURN) */
705 /* Check to see whether the jump actually
706 jumps out of the loop (meaning it's no loop).
707 This case can happen for things like
708 do {..} while (0). If this label was generated previously
709 by loop, we can't tell anything about it and have to reject
710 the loop. */
712 {
715 }
717 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
718 as required by loop_reg_used_before_p. So skip such loops. (This
719 test may never be true, but it's best to play it safe.)
721 Also, skip loops where we do not start scanning at a label. This
722 test also rejects loops starting with a JUMP_INSN that failed the
723 test above. */
727 {
732 }
734 /* Allocate extra space for REGs that might be created by load_mems.
735 We allocate a little extra slop as well, in the hopes that we
736 won't have to reallocate the regs array. */
741 {
747 }
749 /* Scan through the loop finding insns that are safe to move.
750 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
751 this reg will be considered invariant for subsequent insns.
752 We consider whether subsequent insns use the reg
753 in deciding whether it is worth actually moving.
755 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
756 and therefore it is possible that the insns we are scanning
757 would never be executed. At such times, we must make sure
758 that it is safe to execute the insn once instead of zero times.
759 When MAYBE_NEVER is 0, all insns will be executed at least once
760 so that is not a problem. */
765 {
767 in_libcall--;
769 {
772 in_libcall++;
776 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
778 #endif
780 {
788 /* Figure out what to use as a source of this insn. If a
789 REG_EQUIV note is given or if a REG_EQUAL note with a
790 constant operand is specified, use it as the source and
791 mark that we should move this insn by calling
792 emit_move_insn rather that duplicating the insn.
794 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
795 note is present. */
799 else
800 {
805 {
807 /* A libcall block can use regs that don't appear in
808 the equivalent expression. To move the libcall,
809 we must move those regs too. */
811 }
812 }
814 /* For parallels, add any possible uses to the dependencies, as
815 we can't move the insn without resolving them first.
816 MEMs inside CLOBBERs may also reference registers; these
817 count as implicit uses. */
819 {
821 {
824 dependencies
826 dependencies);
831 }
832 }
835 than the one where it is set (meaning that
836 something after this point in the loop might
837 depend on its value before the set). */
839 /* And the set is not guaranteed to be executed once
840 the loop starts, or the value before the set is
841 needed before the set occurs...
843 ??? Note we have quadratic behavior here, mitigated
844 by the fact that the previous test will often fail for
845 large loops. Rather than re-scanning the entire loop
846 each time for register usage, we should build tables
847 of the register usage and use them here instead. */
848 && (maybe_never
850 /* It is unsafe to move the set. However, it may be OK to
851 move the source into a new pseudo, and substitute a
852 reg-to-reg copy for the original insn.
854 This code used to consider it OK to move a set of a variable
855 which was not created by the user and not used in an exit
856 test.
857 That behavior is incorrect and was removed. */
860 /* Don't try to optimize a MODE_CC set with a constant
861 source. It probably will be combined with a conditional
862 jump. */
865 ;
866 /* Don't try to optimize a register that was made
867 by loop-optimization for an inner loop.
868 We don't know its life-span, so we can't compute
869 the benefit. */
871 ;
872 /* Don't move the source and add a reg-to-reg copy:
873 - with -Os (this certainly increases size),
874 - if the mode doesn't support copy operations (obviously),
875 - if the source is already a reg (the motion will gain nothing),
876 - if the source is a legitimate constant (likewise). */
878 && (optimize_size
883 ;
886 || (tem2
889 || (tem1
890 = consec_sets_invariant_p
893 p)))
894 /* If the insn can cause a trap (such as divide by zero),
895 can't move it unless it's guaranteed to be executed
896 once loop is entered. Even a function call might
897 prevent the trap insn from being reached
898 (since it might exit!) */
901 {
905 /* A potential lossage is where we have a case where two insns
906 can be combined as long as they are both in the loop, but
907 we move one of them outside the loop. For large loops,
908 this can lose. The most common case of this is the address
909 of a function being called.
911 Therefore, if this register is marked as being used
912 exactly once if we are in a loop with calls
913 (a "large loop"), see if we can replace the usage of
914 this register with the source of this SET. If we can,
915 delete this insn.
917 Don't do this if P has a REG_RETVAL note or if we have
918 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
930 && (! SMALL_REGISTER_CLASSES
934 /* This test is not redundant; SET_SRC (set) might be
935 a call-clobbered register and the life of REGNO
936 might span a call. */
943 {
944 /* Replace any usage in a REG_EQUAL note. Must copy
945 the new source, so that we don't get rtx sharing
946 between the SET_SOURCE and REG_NOTES of insn p. */
948 = (replace_rtx
954 i++)
957 }
966 m->consec
977 /* Set M->cond if either loop_invariant_p
978 or consec_sets_invariant_p returned 2
979 (only conditionally invariant). */
989 /* Add M to the end of the chain MOVABLES. */
993 {
994 /* It is possible for the first instruction to have a
995 REG_EQUAL note but a non-invariant SET_SRC, so we must
996 remember the status of the first instruction in case
997 the last instruction doesn't have a REG_EQUAL note. */
1000 /* Skip this insn, not checking REG_LIBCALL notes. */
1002 /* Skip the consecutive insns, if there are any. */
1004 /* Back up to the last insn of the consecutive group. */
1007 /* We must now reset m->move_insn, m->is_equiv, and
1008 possibly m->set_src to correspond to the effects of
1009 all the insns. */
1013 else
1014 {
1018 else
1021 }
1022 m->is_equiv
1024 }
1025 }
1026 /* If this register is always set within a STRICT_LOW_PART
1027 or set to zero, then its high bytes are constant.
1028 So clear them outside the loop and within the loop
1029 just load the low bytes.
1030 We must check that the machine has an instruction to do so.
1031 Also, if the value loaded into the register
1032 depends on the same register, this cannot be done. */
1042 {
1045 {
1060 /* If the insn may not be executed on some cycles,
1061 we can't clear the whole reg; clear just high part.
1062 Not even if the reg is used only within this loop.
1063 Consider this:
1064 while (1)
1065 while (s != t) {
1066 if (foo ()) x = *s;
1067 use (x);
1068 }
1069 Clearing x before the inner loop could clobber a value
1070 being saved from the last time around the outer loop.
1071 However, if the reg is not used outside this loop
1072 and all uses of the register are in the same
1073 basic block as the store, there is no problem.
1075 If this insn was made by loop, we don't know its
1076 INSN_LUID and hence must make a conservative
1077 assumption. */
1080 || (labels_in_range_p
1084 else
1093 i++)
1095 /* Add M to the end of the chain MOVABLES. */
1097 }
1098 }
1099 }
1100 }
1101 /* Past a call insn, we get to insns which might not be executed
1102 because the call might exit. This matters for insns that trap.
1103 Constant and pure call insns always return, so they don't count. */
1106 /* Past a label or a jump, we get to insns for which we
1107 can't count on whether or how many times they will be
1108 executed during each iteration. Therefore, we can
1109 only move out sets of trivial variables
1110 (those not used after the loop). */
1111 /* Similar code appears twice in strength_reduce. */
1113 /* If we enter the loop in the middle, and scan around to the
1114 beginning, don't set maybe_never for that. This must be an
1115 unconditional jump, otherwise the code at the top of the
1116 loop might never be executed. Unconditional jumps are
1117 followed by a barrier then the loop_end. */
1123 {
1124 /* At the virtual top of a converted loop, insns are again known to
1125 be executed: logically, the loop begins here even though the exit
1126 code has been duplicated. */
1130 loop_depth++;
1132 loop_depth--;
1133 }
1134 }
1136 /* If one movable subsumes another, ignore that other. */
1140 /* For each movable insn, see if the reg that it loads
1141 leads when it dies right into another conditionally movable insn.
1142 If so, record that the second insn "forces" the first one,
1143 since the second can be moved only if the first is. */
1147 /* See if there are multiple movable insns that load the same value.
1148 If there are, make all but the first point at the first one
1149 through the `match' field, and add the priorities of them
1150 all together as the priority of the first. */
1154 /* Now consider each movable insn to decide whether it is worth moving.
1155 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1157 For machines with few registers this increases code size, so do not
1158 move moveables when optimizing for code size on such machines.
1159 (The 18 below is the value for i386.) */
1163 {
1166 /* Recalculate regs->array if move_movables has created new
1167 registers. */
1169 {
1175 ;
1180 }
1181 }
1183 /* Now candidates that still are negative are those not moved.
1184 Change regs->array[I].set_in_loop to indicate that those are not actually
1185 invariant. */
1190 /* Now that we've moved some things out of the loop, we might be able to
1191 hoist even more memory references. */
1194 /* Recalculate regs->array if load_mems has created new registers. */
1202 ;
1209 {
1211 /* Ensure our label doesn't go away. */
1222 }
1225 /* The movable information is required for strength reduction. */
1231 }
1232 \f
1233 /* Add elements to *OUTPUT to record all the pseudo-regs
1234 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1236 static void
1238 {
1246 {
1264 }
1268 {
1272 {
1281 }
1282 }
1283 }
1284 \f
1285 /* Check what regs are referred to in the libcall block ending with INSN,
1286 aside from those mentioned in the equivalent value.
1287 If there are none, return 0.
1288 If there are one or more, return an EXPR_LIST containing all of them. */
1290 static rtx
1292 {
1297 /* First, find all the regs used in the libcall block
1298 that are not mentioned as inputs to the result. */
1301 {
1306 }
1309 }
1310 \f
1311 /* Return 1 if all uses of REG
1312 are between INSN and the end of the basic block. */
1314 static int
1316 {
1318 rtx p;
1323 /* Search this basic block for the already recorded last use of the reg. */
1325 {
1327 {
1333 /* Ordinary insn: if this is the last use, we win. */
1339 /* Jump insn: if this is the last use, we win. */
1342 /* Otherwise, it's the end of the basic block, so we lose. */
1347 /* It's the end of the basic block, so we lose. */
1352 }
1353 }
1355 /* The "last use" that was recorded can't be found after the first
1356 use. This can happen when the last use was deleted while
1357 processing an inner loop, this inner loop was then completely
1358 unrolled, and the outer loop is always exited after the inner loop,
1359 so that everything after the first use becomes a single basic block. */
1361 }
1362 \f
1363 /* Compute the benefit of eliminating the insns in the block whose
1364 last insn is LAST. This may be a group of insns used to compute a
1365 value directly or can contain a library call. */
1367 static int
1369 {
1370 rtx insn;
1375 {
1378 routine. */
1382 benefit++;
1383 }
1386 }
1387 \f
1388 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1390 static rtx
1392 {
1394 {
1395 rtx temp;
1397 /* If first insn of libcall sequence, skip to end. */
1398 /* Do this at start of loop, since INSN is guaranteed to
1399 be an insn here. */
1404 do
1407 }
1410 }
1412 /* Ignore any movable whose insn falls within a libcall
1413 which is part of another movable.
1414 We make use of the fact that the movable for the libcall value
1415 was made later and so appears later on the chain. */
1417 static void
1419 {
1423 {
1424 /* Is this a movable for the value of a libcall? */
1427 {
1428 rtx insn;
1429 /* Check for earlier movables inside that range,
1430 and mark them invalid. We cannot use LUIDs here because
1431 insns created by loop.c for prior loops don't have LUIDs.
1432 Rather than reject all such insns from movables, we just
1433 explicitly check each insn in the libcall (since invariant
1434 libcalls aren't that common). */
1439 }
1440 }
1441 }
1443 /* For each movable insn, see if the reg that it loads
1444 leads when it dies right into another conditionally movable insn.
1445 If so, record that the second insn "forces" the first one,
1446 since the second can be moved only if the first is. */
1448 static void
1450 {
1454 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1456 {
1459 /* ??? Could this be a bug? What if CSE caused the
1460 register of M1 to be used after this insn?
1461 Since CSE does not update regno_last_uid,
1462 this insn M->insn might not be where it dies.
1463 But very likely this doesn't matter; what matters is
1464 that M's reg is computed from M1's reg. */
1469 /* If m->consec, m->set_src isn't valid. */
1473 /* Increase the priority of the moving the first insn
1474 since it permits the second to be moved as well.
1475 Likewise for insns already forced by the first insn. */
1477 {
1482 {
1485 }
1486 }
1487 }
1488 }
1489 \f
1490 /* Find invariant expressions that are equal and can be combined into
1491 one register. */
1493 static void
1495 {
1500 /* Regs that are set more than once are not allowed to match
1501 or be matched. I'm no longer sure why not. */
1502 /* Only pseudo registers are allowed to match or be matched,
1503 since move_movables does not validate the change. */
1504 /* Perhaps testing m->consec_sets would be more appropriate here? */
1511 {
1518 /* We want later insns to match the first one. Don't make the first
1519 one match any later ones. So start this loop at m->next. */
1525 /* A reg used outside the loop mustn't be eliminated. */
1527 /* A reg used for zero-extending mustn't be eliminated. */
1530 ||
1531 (
1532 /* Can combine regs with different modes loaded from the
1533 same constant only if the modes are the same or
1534 if both are integer modes with M wider or the same
1535 width as M1. The check for integer is redundant, but
1536 safe, since the only case of differing destination
1537 modes with equal sources is when both sources are
1538 VOIDmode, i.e., CONST_INT. */
1544 /* See if the source of M1 says it matches M. */
1551 {
1557 }
1558 }
1560 /* Now combine the regs used for zero-extension.
1561 This can be done for those not marked `global'
1562 provided their lives don't overlap. */
1566 {
1569 /* Combine all the registers for extension from mode MODE.
1570 Don't combine any that are used outside this loop. */
1574 {
1581 {
1582 /* First one: don't check for overlap, just record it. */
1585 }
1587 /* Make sure they extend to the same mode.
1588 (Almost always true.) */
1592 /* We already have one: check for overlap with those
1593 already combined together. */
1600 /* No overlap: we can combine this with the others. */
1606 overlap:
1607 ;
1608 }
1609 }
1611 /* Clean up. */
1613 }
1615 /* Returns the number of movable instructions in LOOP that were not
1616 moved outside the loop. */
1618 static int
1620 {
1629 }
1631 \f
1632 /* Return 1 if regs X and Y will become the same if moved. */
1634 static int
1636 {
1653 }
1655 /* Return 1 if X and Y are identical-looking rtx's.
1656 This is the Lisp function EQUAL for rtx arguments.
1658 If two registers are matching movables or a movable register and an
1659 equivalent constant, consider them equal. */
1661 static int
1664 {
1678 /* If we have a register and a constant, they may sometimes be
1679 equal. */
1682 {
1687 }
1690 {
1695 }
1697 /* Otherwise, rtx's of different codes cannot be equal. */
1701 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1702 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1707 /* These three types of rtx's can be compared nonrecursively. */
1716 /* Compare the elements. If any pair of corresponding elements
1717 fail to match, return 0 for the whole things. */
1721 {
1723 {
1735 /* Two vectors must have the same length. */
1739 /* And the corresponding elements must match. */
1758 /* These are just backpointers, so they don't matter. */
1764 /* It is believed that rtx's at this level will never
1765 contain anything but integers and other rtx's,
1766 except for within LABEL_REFs and SYMBOL_REFs. */
1769 }
1770 }
1772 }
1773 \f
1774 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1775 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1776 references is incremented once for each added note. */
1778 static void
1780 {
1784 rtx insn;
1787 {
1788 /* This code used to ignore labels that referred to dispatch tables to
1789 avoid flow generating (slightly) worse code.
1791 We no longer ignore such label references (see LABEL_REF handling in
1792 mark_jump_label for additional information). */
1795 {
1800 }
1801 }
1805 {
1811 }
1812 }
1813 \f
1814 /* Scan MOVABLES, and move the insns that deserve to be moved.
1815 If two matching movables are combined, replace one reg with the
1816 other throughout. */
1818 static void
1821 {
1826 rtx p;
1829 /* Map of pseudo-register replacements to handle combining
1830 when we move several insns that load the same value
1831 into different pseudo-registers. */
1836 {
1837 /* Describe this movable insn. */
1840 {
1861 }
1863 /* Ignore the insn if it's already done (it matched something else).
1864 Otherwise, see if it is now safe to move. */
1876 {
1878 rtx p;
1881 /* We have an insn that is safe to move.
1882 Compute its desirability. */
1893 /* An insn MUST be moved if we already moved something else
1894 which is safe only if this one is moved too: that is,
1895 if already_moved[REGNO] is nonzero. */
1897 /* An insn is desirable to move if the new lifetime of the
1898 register is no more than THRESHOLD times the old lifetime.
1899 If it's not desirable, it means the loop is so big
1900 that moving won't speed things up much,
1901 and it is liable to make register usage worse. */
1903 /* It is also desirable to move if it can be moved at no
1904 extra cost because something else was already moved. */
1907 || flag_move_all_movables
1912 {
1921 /* Now move the insns that set the reg. */
1924 {
1927 /* Find the end of this chain of matching regs.
1928 Thus, we load each reg in the chain from that one reg.
1929 And that reg is loaded with 0 directly,
1930 since it has ->match == 0. */
1936 /* Mark the moved, invariant reg as being allowed to
1937 share a hard reg with the other matching invariant. */
1941 regs_may_share
1944 regs_may_share));
1952 }
1953 /* If we are to re-generate the item being moved with a
1954 new move insn, first delete what we have and then emit
1955 the move insn before the loop. */
1957 {
1961 {
1962 /* If this is the first insn of a library call sequence,
1963 something is very wrong. */
1968 /* If this is the last insn of a libcall sequence, then
1969 delete every insn in the sequence except the last.
1970 The last insn is handled in the normal manner. */
1973 {
1977 }
1982 /* simplify_giv_expr expects that it can walk the insns
1983 at m->insn forwards and see this old sequence we are
1984 tossing here. delete_insn does preserve the next
1985 pointers, but when we skip over a NOTE we must fix
1986 it up. Otherwise that code walks into the non-deleted
1987 insn stream. */
1992 {
1993 /* Replace the original insn with a move from
1994 our newly created temp. */
2000 }
2001 }
2020 /* The more regs we move, the less we like moving them. */
2022 }
2023 else
2024 {
2026 {
2029 /* If first insn of libcall sequence, skip to end. */
2030 /* Do this at start of loop, since p is guaranteed to
2031 be an insn here. */
2036 /* If last insn of libcall sequence, move all
2037 insns except the last before the loop. The last
2038 insn is handled in the normal manner. */
2041 {
2049 {
2050 rtx body;
2051 rtx n;
2052 rtx next;
2059 /* Find the next insn after TEMP,
2060 not counting USE or NOTE insns. */
2068 /* If that is the call, this may be the insn
2069 that loads the function address.
2071 Extract the function address from the insn
2072 that loads it into a register.
2073 If this insn was cse'd, we get incorrect code.
2075 So emit a new move insn that copies the
2076 function address into the register that the
2077 call insn will use. flow.c will delete any
2078 redundant stores that we have created. */
2083 NULL_RTX)))
2084 {
2090 }
2091 /* We have the call insn.
2092 If it uses the register we suspect it might,
2093 load it with the correct address directly. */
2098 gen_move_insn
2102 {
2104 /* Because the USAGE information potentially
2105 contains objects other than hard registers
2106 we need to copy it. */
2110 }
2111 else
2120 }
2123 }
2125 {
2126 /* P sets REG to zero; but we should clear only
2127 the bits that are not covered by the mode
2128 m->savemode. */
2130 rtx sequence;
2131 rtx tem;
2134 tem = expand_simple_binop
2147 }
2149 {
2151 /* Because the USAGE information potentially
2152 contains objects other than hard registers
2153 we need to copy it. */
2157 }
2159 {
2160 rtx seq;
2161 /* The SET_SRC might not be invariant, so we must
2162 use the REG_EQUAL note. */
2175 }
2177 {
2185 }
2186 else
2190 {
2194 /* If there is a REG_EQUAL note present whose value
2195 is not loop invariant, then delete it, since it
2196 may cause problems with later optimization passes.
2197 It is possible for cse to create such notes
2198 like this as a result of record_jump_cond. */
2203 }
2212 /* If library call, now fix the REG_NOTES that contain
2213 insn pointers, namely REG_LIBCALL on FIRST
2214 and REG_RETVAL on I1. */
2216 {
2220 }
2226 /* simplify_giv_expr expects that it can walk the insns
2227 at m->insn forwards and see this old sequence we are
2228 tossing here. delete_insn does preserve the next
2229 pointers, but when we skip over a NOTE we must fix
2230 it up. Otherwise that code walks into the non-deleted
2231 insn stream. */
2236 {
2237 rtx seq;
2238 /* Replace the original insn with a move from
2239 our newly created temp. */
2245 }
2246 }
2248 /* The more regs we move, the less we like moving them. */
2250 }
2255 {
2256 /* Any other movable that loads the same register
2257 MUST be moved. */
2260 /* This reg has been moved out of one loop. */
2263 /* The reg set here is now invariant. */
2265 {
2269 }
2271 /* Change the length-of-life info for the register
2272 to say it lives at least the full length of this loop.
2273 This will help guide optimizations in outer loops. */
2276 /* This is the old insn before all the moved insns.
2277 We can't use the moved insn because it is out of range
2278 in uid_luid. Only the old insns have luids. */
2282 }
2284 /* Combine with this moved insn any other matching movables. */
2289 {
2290 rtx temp;
2292 /* Schedule the reg loaded by M1
2293 for replacement so that shares the reg of M.
2294 If the modes differ (only possible in restricted
2295 circumstances, make a SUBREG.
2297 Note this assumes that the target dependent files
2298 treat REG and SUBREG equally, including within
2299 GO_IF_LEGITIMATE_ADDRESS and in all the
2300 predicates since we never verify that replacing the
2301 original register with a SUBREG results in a
2302 recognizable insn. */
2305 else
2310 /* Get rid of the matching insn
2311 and prevent further processing of it. */
2314 /* If library call, delete all insns. */
2316 NULL_RTX)))
2318 else
2321 /* Any other movable that loads the same register
2322 MUST be moved. */
2325 /* The reg merged here is now invariant,
2326 if the reg it matches is invariant. */
2328 {
2332 i++)
2334 }
2335 }
2336 }
2339 }
2345 }
2350 /* Go through all the instructions in the loop, making
2351 all the register substitutions scheduled in REG_MAP. */
2355 {
2359 }
2361 /* Clean up. */
2364 }
2367 static void
2369 {
2372 else
2375 }
2378 static void
2380 {
2385 {
2388 }
2389 }
2390 \f
2391 #if 0
2392 /* Scan X and replace the address of any MEM in it with ADDR.
2393 REG is the address that MEM should have before the replacement. */
2395 static void
2397 {
2406 {
2418 /* Short cut for very common case. */
2423 /* Short cut for very common case. */
2428 /* If this MEM uses a reg other than the one we expected,
2429 something is wrong. */
2437 }
2441 {
2445 {
2449 }
2450 }
2451 }
2452 #endif
2453 \f
2454 /* Return the number of memory refs to addresses that vary
2455 in the rtx X. */
2457 static int
2459 {
2470 {
2487 }
2492 {
2496 {
2500 }
2501 }
2503 }
2504 \f
2505 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2506 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2507 `unknown_address_altered', `unknown_constant_address_altered', and
2508 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2509 list `store_mems' in LOOP. */
2511 static void
2513 {
2515 rtx insn;
2519 /* The label after END. Jumping here is just like falling off the
2520 end of the loop. We use next_nonnote_insn instead of next_label
2521 as a hedge against the (pathological) case where some actual insn
2522 might end up between the two. */
2541 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2546 {
2548 {
2551 }
2552 }
2556 {
2558 {
2561 {
2563 /* Count number of loops contained in this one. */
2565 }
2572 {
2575 }
2582 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2583 attached FUNCTION_USAGE expression list, not accounted for by the
2584 code above. We should note these to avoid missing dependencies in
2585 later references. */
2586 {
2587 rtx fusage_entry;
2591 {
2597 {
2602 }
2603 }
2604 }
2609 {
2613 {
2618 {
2621 }
2622 else
2623 {
2626 }
2628 do
2629 {
2631 {
2633 {
2634 /* Something tricky. */
2637 }
2640 {
2641 /* A jump outside the current loop. */
2644 }
2645 }
2649 }
2651 }
2652 else
2653 {
2654 /* A return, or something tricky. */
2656 }
2657 }
2658 /* Fall through. */
2679 }
2680 }
2682 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2684 anywhere. */
2686 /* We don't want loads for MEMs moved to a location before the
2687 one at which their stack memory becomes allocated. (Note
2688 that this is not a problem for malloc, etc., since those
2689 require actual function calls. */
2690 && ! current_function_calls_alloca
2691 /* There are ways to leave the loop other than falling off the
2692 end. */
2698 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2699 that loop_invariant_p and load_mems can use true_dependence
2700 to determine what is really clobbered. */
2702 {
2705 loop_info->store_mems
2707 }
2709 {
2713 loop_info->store_mems
2715 }
2716 }
2717 \f
2718 /* Invalidate all loops containing LABEL. */
2720 static void
2722 {
2726 }
2728 /* Scan the function looking for loops. Record the start and end of each loop.
2729 Also mark as invalid loops any loops that contain a setjmp or are branched
2730 to from outside the loop. */
2732 static void
2734 {
2735 rtx insn;
2736 rtx label;
2746 /* If there are jumps to undefined labels,
2747 treat them as jumps out of any/all loops.
2748 This also avoids writing past end of tables when there are no loops. */
2751 /* Find boundaries of loops, mark which loops are contained within
2752 loops, and invalidate loops that have setjmp. */
2757 {
2760 {
2764 num_loops++;
2788 }
2792 {
2793 /* In this case, we must invalidate our current loop and any
2794 enclosing loop. */
2796 {
2802 }
2803 }
2805 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2806 enclosing loop, but this doesn't matter. */
2808 }
2810 /* Any loop containing a label used in an initializer must be invalidated,
2811 because it can be jumped into from anywhere. */
2815 /* Any loop containing a label used for an exception handler must be
2816 invalidated, because it can be jumped into from anywhere. */
2819 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2820 loop that it is not contained within, that loop is marked invalid.
2821 If any INSN or CALL_INSN uses a label's address, then the loop containing
2822 that label is marked invalid, because it could be jumped into from
2823 anywhere.
2825 Also look for blocks of code ending in an unconditional branch that
2826 exits the loop. If such a block is surrounded by a conditional
2827 branch around the block, move the block elsewhere (see below) and
2828 invert the jump to point to the code block. This may eliminate a
2829 label in our loop and will simplify processing by both us and a
2830 possible second cse pass. */
2834 {
2838 {
2842 }
2849 /* See if this is an unconditional branch outside the loop. */
2857 {
2858 rtx p;
2864 /* Go backwards until we reach the start of the loop, a label,
2865 or a JUMP_INSN. */
2872 ;
2874 /* Check for the case where we have a jump to an inner nested
2875 loop, and do not perform the optimization in that case. */
2878 {
2881 {
2886 }
2887 }
2889 /* Make sure that the target of P is within the current loop. */
2895 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2896 we have a block of code to try to move.
2898 We look backward and then forward from the target of INSN
2899 to find a BARRIER at the same loop depth as the target.
2900 If we find such a BARRIER, we make a new label for the start
2901 of the block, invert the jump in P and point it to that label,
2902 and move the block of code to the spot we found. */
2907 /* Just ignore jumps to labels that were never emitted.
2908 These always indicate compilation errors. */
2912 /* If it's not safe to move the sequence, then we
2913 mustn't try. */
2916 {
2917 rtx target
2921 rtx tmp;
2923 /* Search for possible garbage past the conditional jumps
2924 and look for the last barrier. */
2932 /* Don't move things inside a tablejump. */
2945 /* Don't move things inside a tablejump. */
2956 {
2960 /* Ensure our label doesn't go away. */
2963 /* Verify that uid_loop is large enough and that
2964 we can invert P. */
2966 {
2969 /* If no suitable BARRIER was found, create a suitable
2970 one before TARGET. Since TARGET is a fall through
2971 path, we'll need to insert a jump around our block
2972 and add a BARRIER before TARGET.
2974 This creates an extra unconditional jump outside
2975 the loop. However, the benefits of removing rarely
2976 executed instructions from inside the loop usually
2977 outweighs the cost of the extra unconditional jump
2978 outside the loop. */
2980 {
2981 rtx temp;
2988 }
2990 /* Include the BARRIER after INSN and copy the
2991 block after LOC. */
2996 /* All those insns are now in TARGET_LOOP. */
3002 /* The label jumped to by INSN is no longer a loop
3003 exit. Unless INSN does not have a label (e.g.,
3004 it is a RETURN insn), search loop->exit_labels
3005 to find its label_ref, and remove it. Also turn
3006 off LABEL_OUTSIDE_LOOP_P bit. */
3008 {
3010 r;
3013 {
3017 else
3020 }
3026 /* If we didn't find it, then something is
3027 wrong. */
3030 }
3032 /* P is now a jump outside the loop, so it must be put
3033 in loop->exit_labels, and marked as such.
3034 The easiest way to do this is to just call
3035 mark_loop_jump again for P. */
3038 /* If INSN now jumps to the insn after it,
3039 delete INSN. */
3044 }
3046 /* Continue the loop after where the conditional
3047 branch used to jump, since the only branch insn
3048 in the block (if it still remains) is an inter-loop
3049 branch and hence needs no processing. */
3055 /* This loop will be continued with NEXT_INSN (insn). */
3057 }
3058 }
3059 }
3060 }
3061 }
3063 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3064 loops it is contained in, mark the target loop invalid.
3066 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3068 static void
3070 {
3076 {
3088 /* There could be a label reference in here. */
3100 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3112 /* Link together all labels that branch outside the loop. This
3113 is used by final_[bg]iv_value and the loop unrolling code. Also
3114 mark this LABEL_REF so we know that this branch should predict
3115 false. */
3117 /* A check to make sure the label is not in an inner nested loop,
3118 since this does not count as a loop exit. */
3120 {
3125 }
3126 else
3130 {
3139 }
3141 /* If this is inside a loop, but not in the current loop or one enclosed
3142 by it, it invalidates at least one loop. */
3147 /* We must invalidate every nested loop containing the target of this
3148 label, except those that also contain the jump insn. */
3151 {
3152 /* Stop when we reach a loop that also contains the jump insn. */
3157 /* If we get here, we know we need to invalidate a loop. */
3164 }
3168 /* If this is not setting pc, ignore. */
3190 /* Strictly speaking this is not a jump into the loop, only a possible
3191 jump out of the loop. However, we have no way to link the destination
3192 of this jump onto the list of exit labels. To be safe we mark this
3193 loop and any containing loops as invalid. */
3195 {
3197 {
3203 }
3204 }
3206 }
3207 }
3208 \f
3209 /* Return nonzero if there is a label in the range from
3210 insn INSN to and including the insn whose luid is END
3211 INSN must have an assigned luid (i.e., it must not have
3212 been previously created by loop.c). */
3214 static int
3216 {
3218 {
3222 }
3225 }
3227 /* Record that a memory reference X is being set. */
3229 static void
3232 {
3238 /* Count number of memory writes.
3239 This affects heuristics in strength_reduce. */
3242 /* BLKmode MEM means all memory is clobbered. */
3244 {
3247 else
3251 }
3255 }
3257 /* X is a value modified by an INSN that references a biv inside a loop
3258 exit test (ie, X is somehow related to the value of the biv). If X
3259 is a pseudo that is used more than once, then the biv is (effectively)
3260 used more than once. DATA is a pointer to a loop_regs structure. */
3262 static void
3264 {
3279 /* If we do not have usage information, or if we know the register
3280 is used more than once, note that fact for check_dbra_loop. */
3285 }
3286 \f
3287 /* Return nonzero if the rtx X is invariant over the current loop.
3289 The value is 2 if we refer to something only conditionally invariant.
3291 A memory ref is invariant if it is not volatile and does not conflict
3292 with anything stored in `loop_info->store_mems'. */
3294 int
3296 {
3303 rtx mem_list_entry;
3309 {
3317 /* A LABEL_REF is normally invariant, however, if we are unrolling
3318 loops, and this label is inside the loop, then it isn't invariant.
3319 This is because each unrolled copy of the loop body will have
3320 a copy of this label. If this was invariant, then an insn loading
3321 the address of this label into a register might get moved outside
3322 the loop, and then each loop body would end up using the same label.
3324 We don't know the loop bounds here though, so just fail for all
3325 labels. */
3328 else
3337 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3338 since the reg might be set by initialization within the loop. */
3349 /* Out-of-range regs can occur when we are called from unrolling.
3350 These registers created by the unroller are set in the loop,
3351 hence are never invariant.
3352 Other out-of-range regs can be generated by load_mems; those that
3353 are written to in the loop are not invariant, while those that are
3354 not written to are invariant. It would be easy for load_mems
3355 to set n_times_set correctly for these registers, however, there
3356 is no easy way to distinguish them from registers created by the
3357 unroller. */
3368 /* Volatile memory references must be rejected. Do this before
3369 checking for read-only items, so that volatile read-only items
3370 will be rejected also. */
3374 /* See if there is any dependence between a store and this load. */
3377 {
3383 }
3385 /* It's not invalidated by a store in memory
3386 but we must still verify the address is invariant. */
3390 /* Don't mess with insns declared volatile. */
3397 }
3401 {
3403 {
3409 }
3411 {
3414 {
3420 }
3422 }
3423 }
3426 }
3427 \f
3428 /* Return nonzero if all the insns in the loop that set REG
3429 are INSN and the immediately following insns,
3430 and if each of those insns sets REG in an invariant way
3431 (not counting uses of REG in them).
3433 The value is 2 if some of these insns are only conditionally invariant.
3435 We assume that INSN itself is the first set of REG
3436 and that its source is invariant. */
3438 static int
3440 rtx insn)
3441 {
3445 rtx temp;
3446 /* Number of sets we have to insist on finding after INSN. */
3452 /* If N_SETS hit the limit, we can't rely on its value. */
3459 {
3461 rtx set;
3466 /* If library call, skip to end of it. */
3475 {
3480 {
3481 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3482 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3483 notes are OK. */
3489 }
3490 }
3492 count--;
3494 {
3497 }
3498 }
3501 /* If loop_invariant_p ever returned 2, we return 2. */
3503 }
3504 \f
3505 /* Look at all uses (not sets) of registers in X. For each, if it is
3506 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3507 a different insn, set USAGE[REGNO] to const0_rtx. */
3509 static void
3511 {
3523 {
3524 /* Don't count SET_DEST if it is a REG; otherwise count things
3525 in SET_DEST because if a register is partially modified, it won't
3526 show up as a potential movable so we don't care how USAGE is set
3527 for it. */
3531 }
3532 else
3534 {
3540 }
3541 }
3542 \f
3543 /* Count and record any set in X which is contained in INSN. Update
3544 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3545 in X. */
3547 static void
3549 {
3551 /* Don't move a reg that has an explicit clobber.
3552 It's not worth the pain to try to do it correctly. */
3556 {
3564 {
3568 {
3569 /* If this is the first setting of this reg
3570 in current basic block, and it was set before,
3571 it must be set in two basic blocks, so it cannot
3572 be moved out of the loop. */
3576 /* If this is not first setting in current basic block,
3577 see if reg was used in between previous one and this.
3578 If so, neither one can be moved. */
3585 }
3586 }
3587 }
3588 }
3589 \f
3590 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3591 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3592 contained in insn INSN is used by any insn that precedes INSN in
3593 cyclic order starting from the loop entry point.
3595 We don't want to use INSN_LUID here because if we restrict INSN to those
3596 that have a valid INSN_LUID, it means we cannot move an invariant out
3597 from an inner loop past two loops. */
3599 static int
3601 {
3603 rtx p;
3605 /* Scan forward checking for register usage. If we hit INSN, we
3606 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3608 {
3614 }
3617 }
3618 \f
3620 /* Information we collect about arrays that we might want to prefetch. */
3621 struct prefetch_info
3622 {
3626 index. */
3627 HOST_WIDE_INT index;
3629 iteration. */
3631 prefetch area in one iteration. */
3633 This is set only for loops with known
3634 iteration counts and is 0xffffffff
3635 otherwise. */
3639 };
3641 /* Data used by check_store function. */
3642 struct check_store_data
3643 {
3644 rtx mem_address;
3646 };
3652 /* Set mem_write when mem_address is found. Used as callback to
3653 note_stores. */
3654 static void
3656 {
3661 }
3662 \f
3663 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3664 important to get some addresses combined. Later more sophisticated
3665 transformations can be added when necessary.
3667 ??? Same trick with swapping operand is done at several other places.
3668 It can be nice to develop some common way to handle this. */
3670 static int
3672 {
3684 {
3689 }
3691 /* Compare the elements. If any pair of corresponding elements fails to
3692 match, return 0 for the whole thing. */
3696 {
3698 {
3710 /* Two vectors must have the same length. */
3714 /* And the corresponding elements must match. */
3732 /* These are just backpointers, so they don't matter. */
3738 /* It is believed that rtx's at this level will never
3739 contain anything but integers and other rtx's,
3740 except for within LABEL_REFs and SYMBOL_REFs. */
3743 }
3744 }
3746 }
3747 \f
3748 /* Remove constant addition value from the expression X (when present)
3749 and return it. */
3751 static HOST_WIDE_INT
3753 {
3757 /* Avoid clobbering a shared CONST expression. */
3759 {
3763 {
3766 }
3768 }
3771 {
3774 }
3776 /* For plus expression recurse on ourself. */
3778 {
3782 /* In case our parameter was constant, remove extra zero from the
3783 expression. */
3788 }
3791 }
3793 /* Attempt to identify accesses to arrays that are most likely to cause cache
3794 misses, and emit prefetch instructions a few prefetch blocks forward.
3796 To detect the arrays we use the GIV information that was collected by the
3797 strength reduction pass.
3799 The prefetch instructions are generated after the GIV information is done
3800 and before the strength reduction process. The new GIVs are injected into
3801 the strength reduction tables, so the prefetch addresses are optimized as
3802 well.
3804 GIVs are split into base address, stride, and constant addition values.
3805 GIVs with the same address, stride and close addition values are combined
3806 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3807 for write instructions can be used for the block we write to, on machines
3808 that support write prefetches.
3810 Several heuristics are used to determine when to prefetch. They are
3811 controlled by defined symbols that can be overridden for each target. */
3813 static void
3815 {
3831 /* Consider only loops w/o calls. When a call is done, the loop is probably
3832 slow enough to read the memory. */
3834 {
3839 }
3841 /* Don't prefetch in loops known to have few iterations. */
3845 {
3850 }
3852 /* Search all induction variables and pick those interesting for the prefetch
3853 machinery. */
3855 {
3861 /* Expect all BIVs to be executed in each iteration. This makes our
3862 analysis more conservative. */
3864 {
3865 /* Discard non-constant additions that we can't handle well yet, and
3866 BIVs that are executed multiple times; such BIVs ought to be
3867 handled in the nested loop. We accept not_every_iteration BIVs,
3868 since these only result in larger strides and make our
3869 heuristics more conservative. */
3871 {
3873 {
3879 }
3881 }
3884 {
3886 {
3892 }
3894 }
3898 }
3904 {
3905 rtx address;
3906 rtx temp;
3915 /* See whether an induction variable is interesting to us and if
3916 not, report the reason. */
3920 /* We are interested only in constant stride memory references
3921 in order to be able to compute density easily. */
3925 else
3926 {
3929 {
3932 }
3934 /* On some targets, reversed order prefetches are not
3935 worthwhile. */
3939 /* Prefetch of accesses with an extreme stride might not be
3940 worthwhile, either. */
3945 /* Ignore GIVs with varying add values; we can't predict the
3946 value for the next iteration. */
3950 /* Ignore GIVs in the nested loops; they ought to have been
3951 handled already. */
3954 }
3957 {
3963 }
3965 /* Determine the pointer to the basic array we are examining. It is
3966 the sum of the BIV's initial value and the GIV's add_val. */
3976 /* When the GIV is not always executed, we might be better off by
3977 not dirtying the cache pages. */
3980 else
3981 {
3986 }
3988 /* Attempt to find another prefetch to the same array and see if we
3989 can merge this one. */
3993 {
3994 /* In case both access same array (same location
3995 just with small difference in constant indexes), merge
3996 the prefetches. Just do the later and the earlier will
3997 get prefetched from previous iteration.
3998 The artificial threshold should not be too small,
3999 but also not bigger than small portion of memory usually
4000 traversed by single loop. */
4003 {
4012 }
4016 {
4021 }
4022 }
4024 /* Merging failed. */
4026 {
4034 num_prefetches++;
4036 {
4041 }
4042 }
4043 }
4044 }
4047 {
4050 /* Attempt to calculate the total number of bytes fetched by all
4051 iterations of the loop. Avoid overflow. */
4056 else
4061 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4066 {
4071 }
4072 else
4073 {
4079 }
4080 else
4083 /* Find how many prefetch instructions we'll use within the loop. */
4085 {
4091 }
4092 }
4094 /* Determine how many iterations ahead to prefetch within the loop, based
4095 on how many prefetches we currently expect to do within the loop. */
4097 {
4099 {
4105 }
4106 }
4107 /* We'll also use AHEAD to determine how many prefetch instructions to
4108 emit before a loop, so don't leave it zero. */
4113 {
4114 /* Update if we've decided not to prefetch anything within the loop. */
4118 /* Find how many prefetch instructions we'll use before the loop. */
4120 {
4128 }
4131 {
4151 }
4152 }
4155 {
4156 /* Record that this loop uses prefetch instructions. */
4160 {
4165 }
4166 }
4169 {
4173 {
4175 rtx insn;
4179 rtx seq;
4181 /* We can save some effort by offsetting the address on
4182 architectures with offsettable memory references. */
4185 else
4186 {
4192 }
4195 /* Make sure the address operand is valid for prefetch. */
4205 /* Check all insns emitted and record the new GIV
4206 information. */
4209 {
4214 }
4215 }
4218 {
4219 /* Emit insns before the loop to fetch the first cache lines or,
4220 if we're not prefetching within the loop, everything we expect
4221 to need. */
4223 {
4231 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4232 non-constant INIT_VAL to have the same mode as REG, which
4233 in this case we know to be Pmode. */
4235 {
4236 rtx seq;
4243 }
4249 loop_start);
4250 }
4251 }
4252 }
4255 }
4256 \f
4257 /* Communication with routines called via `note_stores'. */
4261 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4265 /* ??? Unfinished optimizations, and possible future optimizations,
4266 for the strength reduction code. */
4268 /* ??? The interaction of biv elimination, and recognition of 'constant'
4269 bivs, may cause problems. */
4271 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4272 performance problems.
4274 Perhaps don't eliminate things that can be combined with an addressing
4275 mode. Find all givs that have the same biv, mult_val, and add_val;
4276 then for each giv, check to see if its only use dies in a following
4277 memory address. If so, generate a new memory address and check to see
4278 if it is valid. If it is valid, then store the modified memory address,
4279 otherwise, mark the giv as not done so that it will get its own iv. */
4281 /* ??? Could try to optimize branches when it is known that a biv is always
4282 positive. */
4284 /* ??? When replace a biv in a compare insn, we should replace with closest
4285 giv so that an optimized branch can still be recognized by the combiner,
4286 e.g. the VAX acb insn. */
4288 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4289 was rerun in loop_optimize whenever a register was added or moved.
4290 Also, some of the optimizations could be a little less conservative. */
4291 \f
4292 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4293 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4294 callback.
4296 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4297 least once for every loop iteration except for the last one.
4299 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4300 loop iteration.
4301 */
4302 void
4304 {
4309 rtx p;
4311 /* If loop_scan_start points to the loop exit test, we have to be wary of
4312 subversive use of gotos inside expression statements. */
4316 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4320 {
4323 /* Past CODE_LABEL, we get to insns that may be executed multiple
4324 times. The only way we can be sure that they can't is if every
4325 jump insn between here and the end of the loop either
4326 returns, exits the loop, is a jump to a location that is still
4327 behind the label, or is a jump to the loop start. */
4330 {
4336 {
4341 {
4344 else
4348 }
4356 {
4359 }
4360 }
4361 }
4363 /* Past a jump, we get to insns for which we can't count
4364 on whether they will be executed during each iteration. */
4365 /* This code appears twice in strength_reduce. There is also similar
4366 code in scan_loop. */
4368 /* If we enter the loop in the middle, and scan around to the
4369 beginning, don't set not_every_iteration for that.
4370 This can be any kind of jump, since we want to know if insns
4371 will be executed if the loop is executed. */
4376 {
4379 /* If this is a jump outside the loop, then it also doesn't
4380 matter. Check to see if the target of this branch is on the
4381 loop->exits_labels list. */
4389 }
4392 {
4393 /* At the virtual top of a converted loop, insns are again known to
4394 be executed each iteration: logically, the loop begins here
4395 even though the exit code has been duplicated.
4397 Insns are also again known to be executed each iteration at
4398 the LOOP_CONT note. */
4404 loop_depth++;
4406 loop_depth--;
4407 }
4409 /* Note if we pass a loop latch. If we do, then we can not clear
4410 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4411 a loop since a jump before the last CODE_LABEL may have started
4412 a new loop iteration.
4414 Note that LOOP_TOP is only set for rotated loops and we need
4415 this check for all loops, so compare against the CODE_LABEL
4416 which immediately follows LOOP_START. */
4421 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4422 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4423 or not an insn is known to be executed each iteration of the
4424 loop, whether or not any iterations are known to occur.
4426 Therefore, if we have just passed a label and have no more labels
4427 between here and the test insn of the loop, and we have not passed
4428 a jump to the top of the loop, then we know these insns will be
4429 executed each iteration. */
4432 && !past_loop_latch
4437 }
4438 }
4439 \f
4440 static void
4442 {
4445 /* Temporary list pointers for traversing ivs->list. */
4452 /* Scan ivs->list to remove all regs that proved not to be bivs.
4453 Make a sanity check against regs->n_times_set. */
4455 {
4457 /* Above happens if register modified by subreg, etc. */
4458 /* Make sure it is not recognized as a basic induction var: */
4460 /* If never incremented, it is invariant that we decided not to
4461 move. So leave it alone. */
4463 {
4474 }
4475 else
4476 {
4481 }
4482 }
4483 }
4486 /* Determine how BIVS are initialized by looking through pre-header
4487 extended basic block. */
4488 static void
4490 {
4492 /* Temporary list pointers for traversing ivs->list. */
4495 rtx p;
4497 /* Find initial value for each biv by searching backwards from loop_start,
4498 halting at first label. Also record any test condition. */
4502 {
4503 rtx test;
4513 /* Record any test of a biv that branches around the loop if no store
4514 between it and the start of loop. We only care about tests with
4515 constants and registers and only certain of those. */
4525 {
4526 /* If an NE test, we have an initial value! */
4528 {
4532 }
4533 else
4535 }
4536 }
4537 }
4540 /* Look at the each biv and see if we can say anything better about its
4541 initial value from any initializing insns set up above. (This is done
4542 in two passes to avoid missing SETs in a PARALLEL.) */
4543 static void
4545 {
4547 /* Temporary list pointers for traversing ivs->list. */
4552 {
4553 rtx src;
4554 rtx note;
4559 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4560 is a constant, use the value of that. */
4566 else
4579 {
4583 {
4586 }
4587 }
4588 /* If we can't make it a giv,
4589 let biv keep initial value of "itself". */
4592 }
4593 }
4596 /* Search the loop for general induction variables. */
4598 static void
4600 {
4602 }
4605 /* For each giv for which we still don't know whether or not it is
4606 replaceable, check to see if it is replaceable because its final value
4607 can be calculated. */
4609 static void
4611 {
4616 {
4622 }
4623 }
4626 /* Return nonzero if it is possible to eliminate the biv BL provided
4627 all givs are reduced. This is possible if either the reg is not
4628 used outside the loop, or we can compute what its final value will
4629 be. */
4631 static int
4634 {
4635 /* For architectures with a decrement_and_branch_until_zero insn,
4636 don't do this if we put a REG_NONNEG note on the endtest for this
4637 biv. */
4639 #ifdef HAVE_decrement_and_branch_until_zero
4641 {
4646 }
4647 #endif
4649 /* Check that biv is used outside loop or if it has a final value.
4650 Compare against bl->init_insn rather than loop->start. We aren't
4651 concerned with any uses of the biv between init_insn and
4652 loop->start since these won't be affected by the value of the biv
4653 elsewhere in the function, so long as init_insn doesn't use the
4654 biv itself. */
4665 {
4673 }
4675 }
4678 /* Reduce each giv of BL that we have decided to reduce. */
4680 static void
4682 {
4686 {
4689 {
4692 /* If the code for derived givs immediately below has already
4693 allocated a new_reg, we must keep it. */
4697 #ifdef AUTO_INC_DEC
4698 /* If the target has auto-increment addressing modes, and
4699 this is an address giv, then try to put the increment
4700 immediately after its use, so that flow can create an
4701 auto-increment addressing mode. */
4704 /* We don't handle reversed biv's because bl->biv->insn
4705 does not have a valid INSN_LUID. */
4709 {
4710 /* If other giv's have been combined with this one, then
4711 this will work only if all uses of the other giv's occur
4712 before this giv's insn. This is difficult to check.
4714 We simplify this by looking for the common case where
4715 there is one DEST_REG giv, and this giv's insn is the
4716 last use of the dest_reg of that DEST_REG giv. If the
4717 increment occurs after the address giv, then we can
4718 perform the optimization. (Otherwise, the increment
4719 would have to go before other_giv, and we would not be
4720 able to combine it with the address giv to get an
4721 auto-inc address.) */
4723 {
4728 {
4731 else
4733 }
4740 }
4741 /* Check for case where increment is before the address
4742 giv. Do this test in "loop order". */
4751 else
4754 #ifdef HAVE_cc0
4755 {
4756 rtx prev;
4758 /* We can't put an insn immediately after one setting
4759 cc0, or immediately before one using cc0. */
4766 }
4767 #endif
4771 }
4772 #endif
4774 /* For each place where the biv is incremented, add an insn
4775 to increment the new, reduced reg for the giv. */
4777 {
4778 rtx insert_before;
4780 /* Skip if location is the same as a previous one. */
4787 else
4795 /* A multiply is acceptable here
4796 since this is presumed to be seldom executed. */
4800 }
4802 /* Add code at loop start to initialize giv's reduced reg. */
4807 }
4808 }
4809 }
4812 /* Check for givs whose first use is their definition and whose
4813 last use is the definition of another giv. If so, it is likely
4814 dead and should not be used to derive another giv nor to
4815 eliminate a biv. */
4817 static void
4819 {
4823 {
4830 {
4836 }
4837 }
4838 }
4841 static void
4843 {
4847 {
4854 /* Update expression if this was combined, in case other giv was
4855 replaced. */
4860 /* See if this register is known to be a pointer to something. If
4861 so, see if we can find the alignment. First see if there is a
4862 destination register that is a pointer. If so, this shares the
4863 alignment too. Next see if we can deduce anything from the
4864 computational information. If not, and this is a DEST_ADDR
4865 giv, at least we know that it's a pointer, though we don't know
4866 the alignment. */
4874 {
4883 }
4887 {
4895 }
4900 /* Store reduced reg as the address in the memref where we found
4901 this giv. */
4904 {
4906 }
4907 else
4908 {
4910 rtx note;
4912 /* Not replaceable; emit an insn to set the original giv reg from
4913 the reduced giv, same as above. */
4918 /* The original insn may have a REG_EQUAL note. This note is
4919 now incorrect and may result in invalid substitutions later.
4920 The original insn is dead, but may be part of a libcall
4921 sequence, which doesn't seem worth the bother of handling. */
4925 }
4927 /* When a loop is reversed, givs which depend on the reversed
4928 biv, and which are live outside the loop, must be set to their
4929 correct final value. This insn is only needed if the giv is
4930 not replaceable. The correct final value is the same as the
4931 value that the giv starts the reversed loop with. */
4942 {
4947 }
4948 }
4949 }
4952 static int
4955 rtx test_reg)
4956 {
4965 /* Reduce benefit if not replaceable, since we will insert a
4966 move-insn to replace the insn that calculates this giv. Don't do
4967 this unless the giv is a user variable, since it will often be
4968 marked non-replaceable because of the duplication of the exit
4969 code outside the loop. In such a case, the copies we insert are
4970 dead and will be deleted. So they don't have a cost. Similar
4971 situations exist. */
4972 /* ??? The new final_[bg]iv_value code does a much better job of
4973 finding replaceable giv's, and hence this code may no longer be
4974 necessary. */
4979 /* Decrease the benefit to count the add-insns that we will insert
4980 to increment the reduced reg for the giv. ??? This can
4981 overestimate the run-time cost of the additional insns, e.g. if
4982 there are multiple basic blocks that increment the biv, but only
4983 one of these blocks is executed during each iteration. There is
4984 no good way to detect cases like this with the current structure
4985 of the loop optimizer. This code is more accurate for
4986 determining code size than run-time benefits. */
4989 /* Decide whether to strength-reduce this giv or to leave the code
4990 unchanged (recompute it from the biv each time it is used). This
4991 decision can be made independently for each giv. */
4993 #ifdef AUTO_INC_DEC
4994 /* Attempt to guess whether autoincrement will handle some of the
4995 new add insns; if so, increase BENEFIT (undo the subtraction of
4996 add_cost that was done above). */
4998 /* Increasing the benefit is risky, since this is only a guess.
4999 Avoid increasing register pressure in cases where there would
5000 be no other benefit from reducing this giv. */
5003 {
5018 }
5019 #endif
5022 }
5025 /* Free IV structures for LOOP. */
5027 static void
5029 {
5036 {
5042 {
5045 }
5047 {
5050 }
5054 }
5055 }
5058 /* Perform strength reduction and induction variable elimination.
5060 Pseudo registers created during this function will be beyond the
5061 last valid index in several tables including
5062 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5063 problem here, because the added registers cannot be givs outside of
5064 their loop, and hence will never be reconsidered. But scan_loop
5065 must check regnos to make sure they are in bounds. */
5067 static void
5069 {
5073 rtx p;
5074 /* Temporary list pointer for traversing ivs->list. */
5076 /* Ratio of extra register life span we can justify
5077 for saving an instruction. More if loop doesn't call subroutines
5078 since in that case saving an insn makes more difference
5079 and more registers are available. */
5080 /* ??? could set this to last value of threshold in move_movables */
5082 /* Map of pseudo-register replacements. */
5094 /* Find all BIVs in loop. */
5097 /* Exit if there are no bivs. */
5099 {
5100 /* Can still unroll the loop anyways, but indicate that there is no
5101 strength reduction info available. */
5107 }
5109 /* Determine how BIVS are initialized by looking through pre-header
5110 extended basic block. */
5113 /* Look at the each biv and see if we can say anything better about its
5114 initial value from any initializing insns set up above. */
5117 /* Search the loop for general induction variables. */
5120 /* Try to calculate and save the number of loop iterations. This is
5121 set to zero if the actual number can not be calculated. This must
5122 be called after all giv's have been identified, since otherwise it may
5123 fail if the iteration variable is a giv. */
5126 #ifdef HAVE_prefetch
5129 #endif
5131 /* Now for each giv for which we still don't know whether or not it is
5132 replaceable, check to see if it is replaceable because its final value
5133 can be calculated. This must be done after loop_iterations is called,
5134 so that final_giv_value will work correctly. */
5137 /* Try to prove that the loop counter variable (if any) is always
5138 nonnegative; if so, record that fact with a REG_NONNEG note
5139 so that "decrement and branch until zero" insn can be used. */
5142 /* Create reg_map to hold substitutions for replaceable giv regs.
5143 Some givs might have been made from biv increments, so look at
5144 ivs->reg_iv_type for a suitable size. */
5148 /* Examine each iv class for feasibility of strength reduction/induction
5149 variable elimination. */
5152 {
5156 /* Test whether it will be possible to eliminate this biv
5157 provided all givs are reduced. */
5160 /* This will be true at the end, if all givs which depend on this
5161 biv have been strength reduced.
5162 We can't (currently) eliminate the biv unless this is so. */
5165 /* Check each extension dependent giv in this class to see if its
5166 root biv is safe from wrapping in the interior mode. */
5169 /* Combine all giv's for this iv_class. */
5173 {
5181 /* If an insn is not to be strength reduced, then set its ignore
5182 flag, and clear bl->all_reduced. */
5184 /* A giv that depends on a reversed biv must be reduced if it is
5185 used after the loop exit, otherwise, it would have the wrong
5186 value after the loop exit. To make it simple, just reduce all
5187 of such giv's whether or not we know they are used after the loop
5188 exit. */
5193 {
5201 }
5202 else
5203 {
5204 /* Check that we can increment the reduced giv without a
5205 multiply insn. If not, reject it. */
5210 {
5218 }
5219 }
5220 }
5222 /* Check for givs whose first use is their definition and whose
5223 last use is the definition of another giv. If so, it is likely
5224 dead and should not be used to derive another giv nor to
5225 eliminate a biv. */
5228 /* Reduce each giv that we decided to reduce. */
5231 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5232 as not reduced.
5234 For each giv register that can be reduced now: if replaceable,
5235 substitute reduced reg wherever the old giv occurs;
5236 else add new move insn "giv_reg = reduced_reg". */
5239 /* All the givs based on the biv bl have been reduced if they
5240 merit it. */
5242 /* For each giv not marked as maybe dead that has been combined with a
5243 second giv, clear any "maybe dead" mark on that second giv.
5244 v->new_reg will either be or refer to the register of the giv it
5245 combined with.
5247 Doing this clearing avoids problems in biv elimination where
5248 a giv's new_reg is a complex value that can't be put in the
5249 insn but the giv combined with (with a reg as new_reg) is
5250 marked maybe_dead. Since the register will be used in either
5251 case, we'd prefer it be used from the simpler giv. */
5257 /* Try to eliminate the biv, if it is a candidate.
5258 This won't work if ! bl->all_reduced,
5259 since the givs we planned to use might not have been reduced.
5261 We have to be careful that we didn't initially think we could
5262 eliminate this biv because of a giv that we now think may be
5263 dead and shouldn't be used as a biv replacement.
5265 Also, there is the possibility that we may have a giv that looks
5266 like it can be used to eliminate a biv, but the resulting insn
5267 isn't valid. This can happen, for example, on the 88k, where a
5268 JUMP_INSN can compare a register only with zero. Attempts to
5269 replace it with a compare with a constant will fail.
5271 Note that in cases where this call fails, we may have replaced some
5272 of the occurrences of the biv with a giv, but no harm was done in
5273 doing so in the rare cases where it can occur. */
5277 {
5278 /* ?? If we created a new test to bypass the loop entirely,
5279 or otherwise drop straight in, based on this test, then
5280 we might want to rewrite it also. This way some later
5281 pass has more hope of removing the initialization of this
5282 biv entirely. */
5284 /* If final_value != 0, then the biv may be used after loop end
5285 and we must emit an insn to set it just in case.
5287 Reversed bivs already have an insn after the loop setting their
5288 value, so we don't need another one. We can't calculate the
5289 proper final value for such a biv here anyways. */
5298 }
5299 /* See above note wrt final_value. But since we couldn't eliminate
5300 the biv, we must set the value after the loop instead of before. */
5304 }
5306 /* Go through all the instructions in the loop, making all the
5307 register substitutions scheduled in REG_MAP. */
5312 {
5316 }
5319 {
5320 /* When we completely unroll a loop we will likely not need the increment
5321 of the loop BIV and we will not need the conditional branch at the
5322 end of the loop. */
5325 #ifdef HAVE_cc0
5326 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5327 need the comparison before the conditional branch at the end of the
5328 loop. */
5330 #endif
5332 /* We'll need one copy for each loop iteration. */
5335 /* A little slop to account for the ability to remove initialization
5336 code, better CSE, and other secondary benefits of completely
5337 unrolling some loops. */
5340 /* Clamp the value. */
5343 }
5345 /* Unroll loops from within strength reduction so that we can use the
5346 induction variable information that strength_reduce has already
5347 collected. Always unroll loops that would be as small or smaller
5348 unrolled than when rolled. */
5361 }
5362 \f
5363 /*Record all basic induction variables calculated in the insn. */
5364 static rtx
5367 {
5369 rtx set;
5370 rtx dest_reg;
5371 rtx inc_val;
5372 rtx mult_val;
5378 {
5383 {
5388 {
5389 /* It is a possible basic induction variable.
5390 Create and initialize an induction structure for it. */
5397 }
5400 }
5401 }
5403 }
5404 \f
5405 /* Record all givs calculated in the insn.
5406 A register is a giv if: it is only set once, it is a function of a
5407 biv and a constant (or invariant), and it is not a biv. */
5408 static rtx
5411 {
5414 rtx set;
5415 /* Look for a general induction variable in a register. */
5420 {
5421 rtx src_reg;
5422 rtx dest_reg;
5423 rtx add_val;
5424 rtx mult_val;
5425 rtx ext_val;
5428 rtx last_consec_insn;
5437 /* Equivalent expression is a giv. */
5442 /* Don't try to handle any regs made by loop optimization.
5443 We have nothing on them in regno_first_uid, etc. */
5445 /* Don't recognize a BASIC_INDUCT_VAR here. */
5447 /* This must be the only place where the register is set. */
5449 /* or all sets must be consecutive and make a giv. */
5454 {
5457 /* If this is a library call, increase benefit. */
5461 /* Skip the consecutive insns, if there are any. */
5469 }
5470 }
5472 /* Look for givs which are memory addresses. */
5475 maybe_multiple);
5477 /* Update the status of whether giv can derive other givs. This can
5478 change when we pass a label or an insn that updates a biv. */
5483 }
5484 \f
5485 /* Return 1 if X is a valid source for an initial value (or as value being
5486 compared against in an initial test).
5488 X must be either a register or constant and must not be clobbered between
5489 the current insn and the start of the loop.
5491 INSN is the insn containing X. */
5493 static int
5495 {
5499 /* Only consider pseudos we know about initialized in insns whose luids
5500 we know. */
5505 /* Don't use call-clobbered registers across a call which clobbers it. On
5506 some machines, don't use any hard registers at all. */
5508 && (SMALL_REGISTER_CLASSES
5512 /* Don't use registers that have been clobbered before the start of the
5513 loop. */
5518 }
5519 \f
5520 /* Scan X for memory refs and check each memory address
5521 as a possible giv. INSN is the insn whose pattern X comes from.
5522 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5523 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5524 more than once in each loop iteration. */
5526 static void
5529 {
5539 {
5555 {
5556 rtx src_reg;
5557 rtx add_val;
5558 rtx mult_val;
5559 rtx ext_val;
5562 /* This code used to disable creating GIVs with mult_val == 1 and
5563 add_val == 0. However, this leads to lost optimizations when
5564 it comes time to combine a set of related DEST_ADDR GIVs, since
5565 this one would not be seen. */
5570 {
5571 /* Found one; record it. */
5579 }
5580 }
5585 }
5587 /* Recursively scan the subexpressions for other mem refs. */
5593 maybe_multiple);
5597 maybe_multiple);
5598 }
5599 \f
5600 /* Fill in the data about one biv update.
5601 V is the `struct induction' in which we record the biv. (It is
5602 allocated by the caller, with alloca.)
5603 INSN is the insn that sets it.
5604 DEST_REG is the biv's reg.
5606 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5607 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5608 being set to INC_VAL.
5610 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5611 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5612 can be executed more than once per iteration. If MAYBE_MULTIPLE
5613 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5614 executed exactly once per iteration. */
5616 static void
5620 {
5637 /* Add this to the reg's iv_class, creating a class
5638 if this is the first incrementation of the reg. */
5642 {
5643 /* Create and initialize new iv_class. */
5653 /* Set initial value to the reg itself. */
5656 /* We haven't seen the initializing insn yet. */
5666 /* Add this class to ivs->list. */
5670 /* Put it in the array of biv register classes. */
5672 }
5673 else
5674 {
5675 /* Check if location is the same as a previous one. */
5679 {
5682 }
5683 }
5685 /* Update IV_CLASS entry for this biv. */
5694 }
5695 \f
5696 /* Fill in the data about one giv.
5697 V is the `struct induction' in which we record the giv. (It is
5698 allocated by the caller, with alloca.)
5699 INSN is the insn that sets it.
5700 BENEFIT estimates the savings from deleting this insn.
5701 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5702 into a register or is used as a memory address.
5704 SRC_REG is the biv reg which the giv is computed from.
5705 DEST_REG is the giv's reg (if the giv is stored in a reg).
5706 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5707 LOCATION points to the place where this giv's value appears in INSN. */
5709 static void
5714 {
5719 rtx temp;
5721 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5722 undo the MULT canonicalization that we performed earlier. */
5752 /* The v->always_computable field is used in update_giv_derive, to
5753 determine whether a giv can be used to derive another giv. For a
5754 DEST_REG giv, INSN computes a new value for the giv, so its value
5755 isn't computable if INSN insn't executed every iteration.
5756 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5757 it does not compute a new value. Hence the value is always computable
5758 regardless of whether INSN is executed each iteration. */
5762 else
5768 {
5771 }
5773 {
5778 /* If the lifetime is zero, it means that this register is
5779 really a dead store. So mark this as a giv that can be
5780 ignored. This will not prevent the biv from being eliminated. */
5786 }
5788 /* Add the giv to the class of givs computed from one biv. */
5792 {
5795 /* Don't count DEST_ADDR. This is supposed to count the number of
5796 insns that calculate givs. */
5800 }
5801 else
5802 /* Fatal error, biv missing for this giv? */
5806 {
5809 }
5810 else
5811 {
5812 /* The giv can be replaced outright by the reduced register only if all
5813 of the following conditions are true:
5814 - the insn that sets the giv is always executed on any iteration
5815 on which the giv is used at all
5816 (there are two ways to deduce this:
5817 either the insn is executed on every iteration,
5818 or all uses follow that insn in the same basic block),
5819 - the giv is not used outside the loop
5820 - no assignments to the biv occur during the giv's lifetime. */
5823 /* Previous line always fails if INSN was moved by loop opt. */
5826 && (! not_every_iteration
5828 {
5829 /* Now check that there are no assignments to the biv within the
5830 giv's lifetime. This requires two separate checks. */
5832 /* Check each biv update, and fail if any are between the first
5833 and last use of the giv.
5835 If this loop contains an inner loop that was unrolled, then
5836 the insn modifying the biv may have been emitted by the loop
5837 unrolling code, and hence does not have a valid luid. Just
5838 mark the biv as not replaceable in this case. It is not very
5839 useful as a biv, because it is used in two different loops.
5840 It is very unlikely that we would be able to optimize the giv
5841 using this biv anyways. */
5846 {
5852 {
5856 }
5857 }
5859 /* If there are any backwards branches that go from after the
5860 biv update to before it, then this giv is not replaceable. */
5864 {
5868 }
5869 }
5870 else
5871 {
5872 /* May still be replaceable, we don't have enough info here to
5873 decide. */
5876 }
5877 }
5879 /* Record whether the add_val contains a const_int, for later use by
5880 combine_givs. */
5881 {
5886 ;
5890 {
5892 {
5897 else
5899 }
5902 }
5903 }
5907 }
5909 /* All this does is determine whether a giv can be made replaceable because
5910 its final value can be calculated. This code can not be part of record_giv
5911 above, because final_giv_value requires that the number of loop iterations
5912 be known, and that can not be accurately calculated until after all givs
5913 have been identified. */
5915 static void
5917 {
5920 /* DEST_ADDR givs will never reach here, because they are always marked
5921 replaceable above in record_giv. */
5923 /* The giv can be replaced outright by the reduced register only if all
5924 of the following conditions are true:
5925 - the insn that sets the giv is always executed on any iteration
5926 on which the giv is used at all
5927 (there are two ways to deduce this:
5928 either the insn is executed on every iteration,
5929 or all uses follow that insn in the same basic block),
5930 - its final value can be calculated (this condition is different
5931 than the one above in record_giv)
5932 - it's not used before the it's set
5933 - no assignments to the biv occur during the giv's lifetime. */
5935 #if 0
5936 /* This is only called now when replaceable is known to be false. */
5937 /* Clear replaceable, so that it won't confuse final_giv_value. */
5939 #endif
5944 {
5947 rtx last_giv_use;
5952 /* When trying to determine whether or not a biv increment occurs
5953 during the lifetime of the giv, we can ignore uses of the variable
5954 outside the loop because final_value is true. Hence we can not
5955 use regno_last_uid and regno_first_uid as above in record_giv. */
5957 /* Search the loop to determine whether any assignments to the
5958 biv occur during the giv's lifetime. Start with the insn
5959 that sets the giv, and search around the loop until we come
5960 back to that insn again.
5962 Also fail if there is a jump within the giv's lifetime that jumps
5963 to somewhere outside the lifetime but still within the loop. This
5964 catches spaghetti code where the execution order is not linear, and
5965 hence the above test fails. Here we assume that the giv lifetime
5966 does not extend from one iteration of the loop to the next, so as
5967 to make the test easier. Since the lifetime isn't known yet,
5968 this requires two loops. See also record_giv above. */
5973 {
5976 {
5979 }
5985 {
5986 /* It is possible for the BIV increment to use the GIV if we
5987 have a cycle. Thus we must be sure to check each insn for
5988 both BIV and GIV uses, and we must check for BIV uses
5989 first. */
5996 {
5998 {
6002 }
6004 }
6005 }
6006 }
6008 /* Now that the lifetime of the giv is known, check for branches
6009 from within the lifetime to outside the lifetime if it is still
6010 replaceable. */
6013 {
6016 {
6029 {
6038 }
6039 }
6040 }
6042 /* If it is replaceable, then save the final value. */
6045 }
6050 }
6051 \f
6052 /* Update the status of whether a giv can derive other givs.
6054 We need to do something special if there is or may be an update to the biv
6055 between the time the giv is defined and the time it is used to derive
6056 another giv.
6058 In addition, a giv that is only conditionally set is not allowed to
6059 derive another giv once a label has been passed.
6061 The cases we look at are when a label or an update to a biv is passed. */
6063 static void
6065 {
6069 rtx tem;
6072 /* Search all IV classes, then all bivs, and finally all givs.
6074 There are three cases we are concerned with. First we have the situation
6075 of a giv that is only updated conditionally. In that case, it may not
6076 derive any givs after a label is passed.
6078 The second case is when a biv update occurs, or may occur, after the
6079 definition of a giv. For certain biv updates (see below) that are
6080 known to occur between the giv definition and use, we can adjust the
6081 giv definition. For others, or when the biv update is conditional,
6082 we must prevent the giv from deriving any other givs. There are two
6083 sub-cases within this case.
6085 If this is a label, we are concerned with any biv update that is done
6086 conditionally, since it may be done after the giv is defined followed by
6087 a branch here (actually, we need to pass both a jump and a label, but
6088 this extra tracking doesn't seem worth it).
6090 If this is a jump, we are concerned about any biv update that may be
6091 executed multiple times. We are actually only concerned about
6092 backward jumps, but it is probably not worth performing the test
6093 on the jump again here.
6095 If this is a biv update, we must adjust the giv status to show that a
6096 subsequent biv update was performed. If this adjustment cannot be done,
6097 the giv cannot derive further givs. */
6103 {
6104 /* Skip if location is the same as a previous one. */
6109 {
6110 /* If cant_derive is already true, there is no point in
6111 checking all of these conditions again. */
6115 /* If this giv is conditionally set and we have passed a label,
6116 it cannot derive anything. */
6120 /* Skip givs that have mult_val == 0, since
6121 they are really invariants. Also skip those that are
6122 replaceable, since we know their lifetime doesn't contain
6123 any biv update. */
6127 /* The only way we can allow this giv to derive another
6128 is if this is a biv increment and we can form the product
6129 of biv->add_val and giv->mult_val. In this case, we will
6130 be able to compute a compensation. */
6132 {
6133 rtx ext_val_dummy;
6144 tem = simplify_giv_expr
6151 else
6153 }
6157 }
6158 }
6159 }
6160 \f
6161 /* Check whether an insn is an increment legitimate for a basic induction var.
6162 X is the source of insn P, or a part of it.
6163 MODE is the mode in which X should be interpreted.
6165 DEST_REG is the putative biv, also the destination of the insn.
6166 We accept patterns of these forms:
6167 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6168 REG = INVARIANT + REG
6170 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6171 store the additive term into *INC_VAL, and store the place where
6172 we found the additive term into *LOCATION.
6174 If X is an assignment of an invariant into DEST_REG, we set
6175 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6177 We also want to detect a BIV when it corresponds to a variable
6178 whose mode was promoted. In that case, an increment
6179 of the variable may be a PLUS that adds a SUBREG of that variable to
6180 an invariant and then sign- or zero-extends the result of the PLUS
6181 into the variable.
6183 Most GIVs in such cases will be in the promoted mode, since that is the
6184 probably the natural computation mode (and almost certainly the mode
6185 used for addresses) on the machine. So we view the pseudo-reg containing
6186 the variable as the BIV, as if it were simply incremented.
6188 Note that treating the entire pseudo as a BIV will result in making
6189 simple increments to any GIVs based on it. However, if the variable
6190 overflows in its declared mode but not its promoted mode, the result will
6191 be incorrect. This is acceptable if the variable is signed, since
6192 overflows in such cases are undefined, but not if it is unsigned, since
6193 those overflows are defined. So we only check for SIGN_EXTEND and
6194 not ZERO_EXTEND.
6196 If we cannot find a biv, we return 0. */
6198 static int
6202 {
6210 {
6216 {
6218 }
6223 {
6225 }
6226 else
6233 /* convert_modes can emit new instructions, e.g. when arg is a loop
6234 invariant MEM and dest_reg has a different mode.
6235 These instructions would be emitted after the end of the function
6236 and then *inc_val would be an uninitialized pseudo.
6237 Detect this and bail in this case.
6238 Other alternatives to solve this can be introducing a convert_modes
6239 variant which is allowed to fail but not allowed to emit new
6240 instructions, emit these instructions before loop start and let
6241 it be garbage collected if *inc_val is never used or saving the
6242 *inc_val initialization sequence generated here and when *inc_val
6243 is going to be actually used, emit it at some suitable place. */
6247 {
6250 }
6258 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6259 handle addition of promoted variables.
6260 ??? The comment at the start of this function is wrong: promoted
6261 variable increments don't look like it says they do. */
6267 /* If this register is assigned in a previous insn, look at its
6268 source, but don't go outside the loop or past a label. */
6270 /* If this sets a register to itself, we would repeat any previous
6271 biv increment if we applied this strategy blindly. */
6277 {
6278 rtx dest;
6279 do
6280 {
6282 }
6311 }
6312 /* Fall through. */
6314 /* Can accept constant setting of biv only when inside inner most loop.
6315 Otherwise, a biv of an inner loop may be incorrectly recognized
6316 as a biv of the outer loop,
6317 causing code to be moved INTO the inner loop. */
6324 /* convert_modes aborts if we try to convert to or from CCmode, so just
6325 exclude that case. It is very unlikely that a condition code value
6326 would be a useful iterator anyways. convert_modes aborts if we try to
6327 convert a float mode to non-float or vice versa too. */
6331 {
6332 /* Possible bug here? Perhaps we don't know the mode of X. */
6336 {
6339 }
6344 }
6345 else
6349 /* Ignore this BIV if signed arithmetic overflow is defined. */
6356 /* Similar, since this can be a sign extension. */
6361 ;
6375 location);
6380 }
6381 }
6382 \f
6383 /* A general induction variable (giv) is any quantity that is a linear
6384 function of a basic induction variable,
6385 i.e. giv = biv * mult_val + add_val.
6386 The coefficients can be any loop invariant quantity.
6387 A giv need not be computed directly from the biv;
6388 it can be computed by way of other givs. */
6390 /* Determine whether X computes a giv.
6391 If it does, return a nonzero value
6392 which is the benefit from eliminating the computation of X;
6393 set *SRC_REG to the register of the biv that it is computed from;
6394 set *ADD_VAL and *MULT_VAL to the coefficients,
6395 such that the value of X is biv * mult + add; */
6397 static int
6402 {
6406 /* If this is an invariant, forget it, it isn't a giv. */
6417 {
6420 /* Since this is now an invariant and wasn't before, it must be a giv
6421 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6422 with. */
6429 /* This is equivalent to a BIV. */
6436 /* Either (plus (biv) (invar)) or
6437 (plus (mult (biv) (invar_1)) (invar_2)). */
6439 {
6442 }
6443 else
6444 {
6447 }
6452 /* ADD_VAL is zero. */
6460 }
6462 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6463 unless they are CONST_INT). */
6471 else
6474 /* Always return true if this is a giv so it will be detected as such,
6475 even if the benefit is zero or negative. This allows elimination
6476 of bivs that might otherwise not be eliminated. */
6478 }
6479 \f
6480 /* Given an expression, X, try to form it as a linear function of a biv.
6481 We will canonicalize it to be of the form
6482 (plus (mult (BIV) (invar_1))
6483 (invar_2))
6484 with possible degeneracies.
6486 The invariant expressions must each be of a form that can be used as a
6487 machine operand. We surround then with a USE rtx (a hack, but localized
6488 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6489 routine; it is the caller's responsibility to strip them.
6491 If no such canonicalization is possible (i.e., two biv's are used or an
6492 expression that is neither invariant nor a biv or giv), this routine
6493 returns 0.
6495 For a nonzero return, the result will have a code of CONST_INT, USE,
6496 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6498 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6503 static rtx
6505 {
6510 rtx tem;
6512 /* If this is not an integer mode, or if we cannot do arithmetic in this
6513 mode, this can't be a giv. */
6520 {
6527 /* Put constant last, CONST_INT last if both constant. */
6535 /* Handle addition of zero, then addition of an invariant. */
6540 {
6543 /* Adding two invariants must result in an invariant, so enclose
6544 addition operation inside a USE and return it. */
6554 else
6563 /* biv + invar or mult + invar. Return sum. */
6567 /* (a + invar_1) + invar_2. Associate. */
6568 return
6574 arg1)),
6579 }
6581 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6582 MULT to reduce cases. */
6588 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6589 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6590 Recurse to associate the second PLUS. */
6595 return
6603 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6619 /* Handle "a - b" as "a + b * (-1)". */
6625 constm1_rtx)),
6634 /* Put constant last, CONST_INT last if both constant. */
6639 /* If second argument is not now constant, not giv. */
6643 /* Handle multiply by 0 or 1. */
6651 {
6653 /* biv * invar. Done. */
6657 /* Product of two constants. */
6661 /* invar * invar is a giv, but attempt to simplify it somehow. */
6667 {
6668 /* (invar_0 * invar_1) * invar_2. Associate. */
6675 arg1)),
6677 }
6678 /* Propagate the MULT expressions to the innermost nodes. */
6680 {
6681 /* (invar_0 + invar_1) * invar_2. Distribute. */
6687 arg1),
6691 arg1)),
6693 }
6697 /* (a * invar_1) * invar_2. Associate. */
6703 arg1)),
6707 /* (a + invar_1) * invar_2. Distribute. */
6712 arg1),
6715 arg1)),
6720 }
6723 /* Shift by constant is multiply by power of two. */
6727 return
6736 /* "-a" is "a * (-1)" */
6742 /* "~a" is "-a - 1". Silly, but easy. */
6746 const1_rtx),
6750 /* Already in proper form for invariant. */
6756 /* Conditionally recognize extensions of simple IVs. After we've
6757 computed loop traversal counts and verified the range of the
6758 source IV, we'll reevaluate this as a GIV. */
6760 {
6763 {
6766 }
6767 }
6771 /* If this is a new register, we can't deal with it. */
6775 /* Check for biv or giv. */
6777 {
6781 {
6784 /* Form expression from giv and add benefit. Ensure this giv
6785 can derive another and subtract any needed adjustment if so. */
6787 /* Increasing the benefit here is risky. The only case in which it
6788 is arguably correct is if this is the only use of V. In other
6789 cases, this will artificially inflate the benefit of the current
6790 giv, and lead to suboptimal code. Thus, it is disabled, since
6791 potentially not reducing an only marginally beneficial giv is
6792 less harmful than reducing many givs that are not really
6793 beneficial. */
6794 {
6798 }
6811 {
6814 }
6815 else
6816 {
6819 }
6821 }
6824 do_default:
6825 /* If it isn't an induction variable, and it is invariant, we
6826 may be able to simplify things further by looking through
6827 the bits we just moved outside the loop. */
6829 {
6835 {
6836 /* Ok, we found a match. Substitute and simplify. */
6838 /* If we match another movable, we must use that, as
6839 this one is going away. */
6844 /* If consec is nonzero, this is a member of a group of
6845 instructions that were moved together. We handle this
6846 case only to the point of seeking to the last insn and
6847 looking for a REG_EQUAL. Fail if we don't find one. */
6849 {
6852 do
6853 {
6855 }
6861 }
6862 else
6863 {
6867 }
6870 {
6871 /* What we are most interested in is pointer
6872 arithmetic on invariants -- only take
6873 patterns we may be able to do something with. */
6879 {
6881 benefit);
6884 }
6889 {
6894 }
6895 }
6897 }
6898 }
6900 }
6902 /* Fall through to general case. */
6904 /* If invariant, return as USE (unless CONST_INT).
6905 Otherwise, not giv. */
6910 {
6919 }
6920 else
6922 }
6923 }
6925 /* This routine folds invariants such that there is only ever one
6926 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6928 static rtx
6930 {
6936 {
6939 }
6942 {
6945 }
6946 else
6947 {
6950 }
6951 }
6953 static rtx
6955 {
6957 {
6961 else
6964 }
6967 else
6970 }
6971 \f
6972 /* Help detect a giv that is calculated by several consecutive insns;
6973 for example,
6974 giv = biv * M
6975 giv = giv + A
6976 The caller has already identified the first insn P as having a giv as dest;
6977 we check that all other insns that set the same register follow
6978 immediately after P, that they alter nothing else,
6979 and that the result of the last is still a giv.
6981 The value is 0 if the reg set in P is not really a giv.
6982 Otherwise, the value is the amount gained by eliminating
6983 all the consecutive insns that compute the value.
6985 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6986 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6988 The coefficients of the ultimate giv value are stored in
6989 *MULT_VAL and *ADD_VAL. */
6991 static int
6995 {
7001 rtx temp;
7002 rtx set;
7004 /* Indicate that this is a giv so that we can update the value produced in
7005 each insn of the multi-insn sequence.
7007 This induction structure will be used only by the call to
7008 general_induction_var below, so we can allocate it on our stack.
7009 If this is a giv, our caller will replace the induct var entry with
7010 a new induction structure. */
7031 {
7035 /* If libcall, skip to end of call sequence. */
7046 /* Giv created by equivalent expression. */
7052 {
7056 count--;
7060 }
7062 {
7063 /* Allow insns that set something other than this giv to a
7064 constant. Such insns are needed on machines which cannot
7065 include long constants and should not disqualify a giv. */
7074 }
7075 }
7080 }
7081 \f
7082 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7083 represented by G1. If no such expression can be found, or it is clear that
7084 it cannot possibly be a valid address, 0 is returned.
7086 To perform the computation, we note that
7087 G1 = x * v + a and
7088 G2 = y * v + b
7089 where `v' is the biv.
7091 So G2 = (y/b) * G1 + (b - a*y/x).
7093 Note that MULT = y/x.
7095 Update: A and B are now allowed to be additive expressions such that
7096 B contains all variables in A. That is, computing B-A will not require
7097 subtracting variables. */
7099 static rtx
7101 {
7102 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7107 /* If MULT is not 1, we cannot handle A with non-constants, since we
7108 would then be required to subtract multiples of the registers in A.
7109 This is theoretically possible, and may even apply to some Fortran
7110 constructs, but it is a lot of work and we do not attempt it here. */
7115 /* In general these structures are sorted top to bottom (down the PLUS
7116 chain), but not left to right across the PLUS. If B is a higher
7117 order giv than A, we can strip one level and recurse. If A is higher
7118 order, we'll eventually bail out, but won't know that until the end.
7119 If they are the same, we'll strip one level around this loop. */
7122 {
7134 /* We matched: remove one reg completely. */
7137 /* An alternate match. */
7140 /* An alternate match. */
7142 else
7143 {
7144 /* Indicates an extra register in B. Strip one level from B and
7145 recurse, hoping B was the higher order expression. */
7150 }
7151 }
7153 /* Here we are at the last level of A, go through the cases hoping to
7154 get rid of everything but a constant. */
7157 {
7170 }
7172 {
7174 }
7176 {
7181 }
7183 {
7188 else
7190 }
7195 }
7197 rtx
7199 {
7202 /* The value that G1 will be multiplied by must be a constant integer. Also,
7203 the only chance we have of getting a valid address is if b*c/a (see above
7204 for notation) is also an integer. */
7207 {
7215 }
7218 else
7219 {
7220 /* ??? Find out if the one is a multiple of the other? */
7222 }
7226 {
7227 /* Failed. If we've got a multiplication factor between G1 and G2,
7228 scale G1's addend and try again. */
7230 {
7234 {
7235 HOST_WIDE_INT m;
7239 }
7240 else
7241 {
7243 mult);
7244 }
7247 }
7248 }
7252 /* Form simplified final result. */
7257 else
7262 else
7263 {
7266 {
7270 }
7273 }
7274 }
7275 \f
7276 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7277 represented by G1. This indicates that G2 should be combined with G1 and
7278 that G2 can use (either directly or via an address expression) a register
7279 used to represent G1. */
7281 static rtx
7283 {
7286 /* With the introduction of ext dependent givs, we must care for modes.
7287 G2 must not use a wider mode than G1. */
7297 /* If these givs are identical, they can be combined. We use the results
7298 of express_from because the addends are not in a canonical form, so
7299 rtx_equal_p is a weaker test. */
7300 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7301 combination to be the other way round. */
7304 {
7306 }
7308 /* If G2 can be expressed as a function of G1 and that function is valid
7309 as an address and no more expensive than using a register for G2,
7310 the expression of G2 in terms of G1 can be used. */
7317 }
7318 \f
7319 /* Check each extension dependent giv in this class to see if its
7320 root biv is safe from wrapping in the interior mode, which would
7321 make the giv illegal. */
7323 static void
7325 {
7329 HOST_WIDE_INT start_val;
7335 /* Make sure the iteration data is available. We must have
7336 constants in order to be certain of no overflow. */
7342 /* Make sure the host can represent the arithmetic. */
7344 {
7346 HOST_WIDE_INT s_end_val;
7358 /* Check for host arithmetic overflow. */
7360 {
7362 HOST_WIDE_INT s_max;
7369 /* Check zero extension of biv ok. */
7371 /* Check for host arithmetic overflow. */
7372 && (neg_incr
7375 /* Check for target arithmetic overflow. */
7376 && (neg_incr
7379 {
7381 }
7383 /* Check sign extension of biv ok. */
7384 /* ??? While it is true that overflow with signed and pointer
7385 arithmetic is undefined, I fear too many programmers don't
7386 keep this fact in mind -- myself included on occasion.
7387 So leave alone with the signed overflow optimizations. */
7389 /* Check for host arithmetic overflow. */
7390 && (neg_incr
7393 /* Check for target arithmetic overflow. */
7394 && (neg_incr
7397 {
7399 }
7400 }
7401 }
7403 /* If we know the BIV is compared at run-time against an
7404 invariant value, and the increment is +/- 1, we may also
7405 be able to prove that the BIV cannot overflow. */
7411 {
7412 /* If the increment is +1, and the exit test is a <,
7413 the BIV cannot overflow. (For <=, we have the
7414 problematic case that the comparison value might
7415 be the maximum value of the range.) */
7417 {
7422 }
7424 /* Likewise for increment -1 and exit test >. */
7426 {
7431 }
7432 }
7434 /* Invalidate givs that fail the tests. */
7437 {
7442 {
7451 /* We don't know whether this value is being used as either
7452 signed or unsigned, so to safely truncate we must satisfy
7453 both. The initial check here verifies the BIV itself;
7454 once that is successful we may check its range wrt the
7455 derived GIV. This works only if we were able to determine
7456 constant start and end values above. */
7458 {
7462 /* We know from the above that both endpoints are nonnegative,
7463 and that there is no wrapping. Verify that both endpoints
7464 are within the (signed) range of the outer mode. */
7467 }
7472 }
7475 {
7477 {
7481 }
7482 }
7483 else
7484 {
7486 {
7491 else
7492 {
7497 else
7499 }
7504 }
7507 }
7508 }
7509 }
7511 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7513 rtx
7515 {
7521 /* Recall that check_ext_dependent_givs verified that the known bounds
7522 of a biv did not overflow or wrap with respect to the extension for
7523 the giv. Therefore, constants need no additional adjustment. */
7527 /* Otherwise, we must adjust the value to compensate for the
7528 differing modes of the biv and the giv. */
7530 }
7531 \f
7532 struct combine_givs_stats
7533 {
7536 };
7538 static int
7540 {
7547 /* Stabilize the sort. */
7551 }
7553 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7554 any other. If so, point SAME to the giv combined with and set NEW_REG to
7555 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7556 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7558 static void
7560 {
7561 /* Additional benefit to add for being combined multiple times. */
7569 /* Count givs, because bl->giv_count is incorrect here. */
7573 giv_count++;
7585 {
7587 rtx single_use;
7592 /* If a DEST_REG GIV is used only once, do not allow it to combine
7593 with anything, for in doing so we will gain nothing that cannot
7594 be had by simply letting the GIV with which we would have combined
7595 to be reduced on its own. The losage shows up in particular with
7596 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7597 be seen elsewhere as well. */
7604 /* Add an additional weight for zero addends. */
7609 {
7610 rtx this_combine;
7615 {
7618 }
7619 }
7621 }
7623 /* Iterate, combining until we can't. */
7624 restart:
7628 {
7631 {
7637 }
7639 }
7642 {
7648 /* If it has already been combined, skip. */
7653 {
7656 /* If it has already been combined, skip. */
7658 {
7663 /* For destination, we now may replace by mem expression instead
7664 of register. This changes the costs considerably, so add the
7665 compensation. */
7675 /* ??? The new final_[bg]iv_value code does a much better job
7676 of finding replaceable giv's, and hence this code may no
7677 longer be necessary. */
7681 /* To help optimize the next set of combinations, remove
7682 this giv from the benefits of other potential mates. */
7684 {
7688 }
7695 }
7696 }
7698 /* To help optimize the next set of combinations, remove
7699 this giv from the benefits of other potential mates. */
7701 {
7703 {
7707 }
7711 /* We've finished with this giv, and everything it touched.
7712 Restart the combination so that proper weights for the
7713 rest of the givs are properly taken into account. */
7714 /* ??? Ideally we would compact the arrays at this point, so
7715 as to not cover old ground. But sanely compacting
7716 can_combine is tricky. */
7718 }
7719 }
7721 /* Clean up. */
7724 }
7725 \f
7726 /* Generate sequence for REG = B * M + A. B is the initial value of
7727 the basic induction variable, M a multiplicative constant, A an
7728 additive constant and REG the destination register. */
7730 static rtx
7732 {
7733 rtx seq;
7734 rtx result;
7737 /* Use unsigned arithmetic. */
7745 }
7748 /* Update registers created in insn sequence SEQ. */
7750 static void
7752 {
7753 rtx insn;
7755 /* Update register info for alias analysis. */
7759 {
7766 }
7767 }
7770 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7771 is the initial value of the basic induction variable, M a
7772 multiplicative constant, A an additive constant and REG the
7773 destination register. */
7775 void
7778 {
7779 rtx seq;
7782 {
7785 }
7787 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7790 /* Increase the lifetime of any invariants moved further in code. */
7795 /* It is possible that the expansion created lots of new registers.
7796 Iterate over the sequence we just created and record them all. We
7797 must do this before inserting the sequence. */
7801 }
7804 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7805 initial value of the basic induction variable, M a multiplicative
7806 constant, A an additive constant and REG the destination
7807 register. */
7809 void
7811 {
7812 rtx seq;
7814 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7817 /* Increase the lifetime of any invariants moved further in code.
7818 ???? Is this really necessary? */
7823 /* It is possible that the expansion created lots of new registers.
7824 Iterate over the sequence we just created and record them all. We
7825 must do this before inserting the sequence. */
7829 }
7832 /* Emit insns after loop to set REG = B * M + A. B is the initial
7833 value of the basic induction variable, M a multiplicative constant,
7834 A an additive constant and REG the destination register. */
7836 void
7838 {
7839 rtx seq;
7841 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7844 /* It is possible that the expansion created lots of new registers.
7845 Iterate over the sequence we just created and record them all. We
7846 must do this before inserting the sequence. */
7850 }
7854 /* Similar to gen_add_mult, but compute cost rather than generating
7855 sequence. */
7857 static int
7859 {
7869 {
7874 }
7877 }
7878 \f
7879 /* Test whether A * B can be computed without
7880 an actual multiply insn. Value is 1 if so.
7882 ??? This function stinks because it generates a ton of wasted RTL
7883 ??? and as a result fragments GC memory to no end. There are other
7884 ??? places in the compiler which are invoked a lot and do the same
7885 ??? thing, generate wasted RTL just to see if something is possible. */
7887 static int
7889 {
7890 rtx tmp;
7893 /* If only one is constant, make it B. */
7897 /* If first constant, both constant, so don't need multiply. */
7901 /* If second not constant, neither is constant, so would need multiply. */
7905 /* One operand is constant, so might not need multiply insn. Generate the
7906 code for the multiply and see if a call or multiply, or long sequence
7907 of insns is generated. */
7916 {
7919 {
7929 {
7932 }
7935 }
7936 }
7946 }
7947 \f
7948 /* Check to see if loop can be terminated by a "decrement and branch until
7949 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7950 Also try reversing an increment loop to a decrement loop
7951 to see if the optimization can be performed.
7952 Value is nonzero if optimization was performed. */
7954 /* This is useful even if the architecture doesn't have such an insn,
7955 because it might change a loops which increments from 0 to n to a loop
7956 which decrements from n to 0. A loop that decrements to zero is usually
7957 faster than one that increments from zero. */
7959 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7960 such as approx_final_value, biv_total_increment, loop_iterations, and
7961 final_[bg]iv_value. */
7963 static int
7965 {
7970 rtx reg;
7972 rtx jump_label;
7973 rtx final_value;
7974 rtx start_value;
7975 rtx new_add_val;
7976 rtx comparison;
7977 rtx before_comparison;
7978 rtx p;
7979 rtx jump;
7980 rtx first_compare;
7985 /* If last insn is a conditional branch, and the insn before tests a
7986 register value, try to optimize it. Otherwise, we can't do anything. */
7995 /* Try to compute whether the compare/branch at the loop end is one or
7996 two instructions. */
8002 else
8005 {
8006 /* If more than one condition is present to control the loop, then
8007 do not proceed, as this function does not know how to rewrite
8008 loop tests with more than one condition.
8010 Look backwards from the first insn in the last comparison
8011 sequence and see if we've got another comparison sequence. */
8013 rtx jump1;
8017 }
8019 /* Check all of the bivs to see if the compare uses one of them.
8020 Skip biv's set more than once because we can't guarantee that
8021 it will be zero on the last iteration. Also skip if the biv is
8022 used between its update and the test insn. */
8025 {
8030 first_compare))
8032 }
8034 /* Try swapping the comparison to identify a suitable biv. */
8041 first_compare))
8042 {
8044 VOIDmode,
8048 }
8053 /* Look for the case where the basic induction variable is always
8054 nonnegative, and equals zero on the last iteration.
8055 In this case, add a reg_note REG_NONNEG, which allows the
8056 m68k DBRA instruction to be used. */
8062 {
8063 /* Initial value must be greater than 0,
8064 init_val % -dec_value == 0 to ensure that it equals zero on
8065 the last iteration */
8071 {
8072 /* Register always nonnegative, add REG_NOTE to branch. */
8080 }
8082 /* If the decrement is 1 and the value was tested as >= 0 before
8083 the loop, then we can safely optimize. */
8085 {
8099 {
8107 }
8108 }
8109 }
8112 {
8113 /* Try to change inc to dec, so can apply above optimization. */
8114 /* Can do this if:
8115 all registers modified are induction variables or invariant,
8116 all memory references have non-overlapping addresses
8117 (obviously true if only one write)
8118 allow 2 insns for the compare/jump at the end of the loop. */
8119 /* Also, we must avoid any instructions which use both the reversed
8120 biv and another biv. Such instructions will fail if the loop is
8121 reversed. We meet this condition by requiring that either
8122 no_use_except_counting is true, or else that there is only
8123 one biv. */
8125 /* 1 if the iteration var is used only to count iterations. */
8127 /* 1 if the loop has no memory store, or it has a single memory store
8128 which is reversible. */
8134 {
8138 /* If there are no givs for this biv, and the only exit is the
8139 fall through at the end of the loop, then
8140 see if perhaps there are no uses except to count. */
8144 {
8149 /* An insn that sets the biv is okay. */
8150 ;
8152 /* An insn that doesn't mention the biv is okay. */
8153 ;
8156 {
8157 /* If either of these insns uses the biv and sets a pseudo
8158 that has more than one usage, then the biv has uses
8159 other than counting since it's used to derive a value
8160 that is used more than one time. */
8162 regs);
8164 {
8167 }
8168 }
8169 else
8170 {
8173 }
8174 }
8176 /* A biv has uses besides counting if it is used to set
8177 another biv. */
8181 {
8184 }
8185 }
8188 /* No need to worry about MEMs. */
8189 ;
8191 {
8196 /* If the loop has a single store, and the destination address is
8197 invariant, then we can't reverse the loop, because this address
8198 might then have the wrong value at loop exit.
8199 This would work if the source was invariant also, however, in that
8200 case, the insn should have been moved out of the loop. */
8203 {
8206 /* If we could prove that each of the memory locations
8207 written to was different, then we could reverse the
8208 store -- but we don't presently have any way of
8209 knowing that. */
8212 /* If the store depends on a register that is set after the
8213 store, it depends on the initial value, and is thus not
8214 reversible. */
8216 {
8223 }
8224 }
8225 }
8226 else
8229 /* This code only acts for innermost loops. Also it simplifies
8230 the memory address check by only reversing loops with
8231 zero or one memory access.
8232 Two memory accesses could involve parts of the same array,
8233 and that can't be reversed.
8234 If the biv is used only for counting, than we don't need to worry
8235 about all these things. */
8241 && reversible_mem_store
8246 {
8247 rtx tem;
8249 /* Loop can be reversed. */
8253 /* Now check other conditions:
8255 The increment must be a constant, as must the initial value,
8256 and the comparison code must be LT.
8258 This test can probably be improved since +/- 1 in the constant
8259 can be obtained by changing LT to LE and vice versa; this is
8260 confusing. */
8263 /* for constants, LE gets turned into LT */
8268 {
8279 comparison_const_width
8281 else
8282 comparison_const_width
8286 comparison_sign_mask
8289 /* If the comparison value is not a loop invariant, then we
8290 can not reverse this loop.
8292 ??? If the insns which initialize the comparison value as
8293 a whole compute an invariant result, then we could move
8294 them out of the loop and proceed with loop reversal. */
8302 /* Normalize the initial value if it is an integer and
8303 has no other use except as a counter. This will allow
8304 a few more loops to be reversed. */
8308 {
8310 /* The code below requires comparison_val to be a multiple
8311 of add_val in order to do the loop reversal, so
8312 round up comparison_val to a multiple of add_val.
8313 Since comparison_value is constant, we know that the
8314 current comparison code is LT. */
8316 comparison_val
8318 /* We postpone overflow checks for COMPARISON_VAL here;
8319 even if there is an overflow, we might still be able to
8320 reverse the loop, if converting the loop exit test to
8321 NE is possible. */
8323 }
8325 /* First check if we can do a vanilla loop reversal. */
8327 /* If we have a decrement_and_branch_on_count,
8328 prefer the NE test, since this will allow that
8329 instruction to be generated. Note that we must
8330 use a vanilla loop reversal if the biv is used to
8331 calculate a giv or has a non-counting use. */
8332 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8333 && defined (HAVE_decrement_and_branch_on_count)
8337 #endif
8339 /* Now do postponed overflow checks on COMPARISON_VAL. */
8342 {
8343 /* Register will always be nonnegative, with value
8344 0 on last iteration */
8348 }
8352 {
8355 }
8356 else
8362 /* If the initial value is not zero, or if the comparison
8363 value is not an exact multiple of the increment, then we
8364 can not reverse this loop. */
8367 {
8370 }
8371 else
8372 {
8375 }
8379 /* Reset these in case we normalized the initial value
8380 and comparison value above. */
8383 {
8385 final_value
8387 }
8390 /* Save some info needed to produce the new insns. */
8396 /* Set start_value; if this is not a CONST_INT, we need
8397 to generate a SUB.
8398 Initialize biv to start_value before loop start.
8399 The old initializing insn will be deleted as a
8400 dead store by flow.c. */
8403 {
8404 start_value
8407 }
8409 {
8416 start_value
8422 }
8424 {
8426 initial_value);
8430 start_value
8433 }
8434 else
8435 /* We could handle the other cases too, but it'll be
8436 better to have a testcase first. */
8439 /* We may not have a single insn which can increment a reg, so
8440 create a sequence to hold all the insns from expand_inc. */
8449 /* Update biv info to reflect its new status. */
8454 /* Update loop info. */
8463 /* Inc LABEL_NUSES so that delete_insn will
8464 not delete the label. */
8467 /* Emit an insn after the end of the loop to set the biv's
8468 proper exit value if it is used anywhere outside the loop. */
8474 /* Delete compare/branch at end of loop. */
8479 /* Add new compare/branch insn at end of loop. */
8491 ;
8497 {
8499 {
8500 /* Increment of LABEL_NUSES done above. */
8501 /* Register is now always nonnegative,
8502 so add REG_NONNEG note to the branch. */
8505 }
8507 }
8509 /* No insn may reference both the reversed and another biv or it
8510 will fail (see comment near the top of the loop reversal
8511 code).
8512 Earlier on, we have verified that the biv has no use except
8513 counting, or it is the only biv in this function.
8514 However, the code that computes no_use_except_counting does
8515 not verify reg notes. It's possible to have an insn that
8516 references another biv, and has a REG_EQUAL note with an
8517 expression based on the reversed biv. To avoid this case,
8518 remove all REG_EQUAL notes based on the reversed biv
8519 here. */
8522 {
8525 /* If this is a set of a GIV based on the reversed biv, any
8526 REG_EQUAL notes should still be correct. */
8533 {
8538 else
8540 }
8541 }
8543 /* Mark that this biv has been reversed. Each giv which depends
8544 on this biv, and which is also live past the end of the loop
8545 will have to be fixed up. */
8550 {
8554 else
8556 }
8559 }
8560 }
8561 }
8564 }
8565 \f
8566 /* Verify whether the biv BL appears to be eliminable,
8567 based on the insns in the loop that refer to it.
8569 If ELIMINATE_P is nonzero, actually do the elimination.
8571 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8572 determine whether invariant insns should be placed inside or at the
8573 start of the loop. */
8575 static int
8578 {
8581 rtx p;
8583 /* Scan all insns in the loop, stopping if we find one that uses the
8584 biv in a way that we cannot eliminate. */
8587 {
8591 rtx note;
8593 /* If this is a libcall that sets a giv, skip ahead to its end. */
8595 {
8599 {
8604 {
8611 }
8612 }
8613 }
8615 /* Closely examine the insn if the biv is mentioned. */
8620 {
8626 }
8628 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8633 }
8636 {
8641 }
8644 }
8645 \f
8646 /* INSN and REFERENCE are instructions in the same insn chain.
8647 Return nonzero if INSN is first. */
8649 int
8651 {
8655 {
8656 /* Start with test for not first so that INSN == REFERENCE yields not
8657 first. */
8663 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8664 previous insn, hence the <= comparison below does not work if
8665 P is a note. */
8676 }
8677 }
8679 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8680 the offset that we have to take into account due to auto-increment /
8681 div derivation is zero. */
8682 static int
8685 {
8686 /* If the giv V had the auto-inc address optimization applied
8687 to it, and INSN occurs between the giv insn and the biv
8688 insn, then we'd have to adjust the value used here.
8689 This is rare, so we don't bother to make this possible. */
8698 }
8700 /* If BL appears in X (part of the pattern of INSN), see if we can
8701 eliminate its use. If so, return 1. If not, return 0.
8703 If BIV does not appear in X, return 1.
8705 If ELIMINATE_P is nonzero, actually do the elimination.
8706 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8707 Depending on how many items have been moved out of the loop, it
8708 will either be before INSN (when WHERE_INSN is nonzero) or at the
8709 start of the loop (when WHERE_INSN is zero). */
8711 static int
8715 {
8721 #ifdef HAVE_cc0
8723 #endif
8729 {
8731 /* If we haven't already been able to do something with this BIV,
8732 we can't eliminate it. */
8738 /* If this sets the BIV, it is not a problem. */
8742 /* If this is an insn that defines a giv, it is also ok because
8743 it will go away when the giv is reduced. */
8748 #ifdef HAVE_cc0
8750 {
8751 /* Can replace with any giv that was reduced and
8752 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8753 Require a constant for MULT_VAL, so we know it's nonzero.
8754 ??? We disable this optimization to avoid potential
8755 overflows. */
8763 {
8770 /* If the giv has the opposite direction of change,
8771 then reverse the comparison. */
8775 else
8778 /* We can probably test that giv's reduced reg. */
8781 }
8783 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8784 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8785 Require a constant for MULT_VAL, so we know it's nonzero.
8786 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8787 overflow problem. */
8799 {
8806 /* If the giv has the opposite direction of change,
8807 then reverse the comparison. */
8811 else
8815 /* Replace biv with the giv's reduced register. */
8820 /* Insn doesn't support that constant or invariant. Copy it
8821 into a register (it will be a loop invariant.) */
8828 /* Substitute the new register for its invariant value in
8829 the compare expression. */
8833 }
8834 }
8835 #endif
8842 /* See if either argument is the biv. */
8847 else
8851 {
8852 /* First try to replace with any giv that has constant positive
8853 mult_val and constant add_val. We might be able to support
8854 negative mult_val, but it seems complex to do it in general. */
8866 {
8870 /* Don't eliminate if the linear combination that makes up
8871 the giv overflows when it is applied to ARG. */
8873 {
8874 rtx add_val;
8878 else
8884 }
8889 /* Replace biv with the giv's reduced reg. */
8892 /* If all constants are actually constant integers and
8893 the derived constant can be directly placed in the COMPARE,
8894 do so. */
8897 {
8900 }
8901 else
8902 {
8903 /* Otherwise, load it into a register. */
8908 }
8914 }
8916 /* Look for giv with positive constant mult_val and nonconst add_val.
8917 Insert insns to calculate new compare value.
8918 ??? Turn this off due to possible overflow. */
8926 {
8927 rtx tem;
8937 /* Replace biv with giv's reduced register. */
8941 /* Compute value to compare against. */
8945 /* Use it in this insn. */
8949 }
8950 }
8952 {
8954 {
8955 /* Look for giv with constant positive mult_val and nonconst
8956 add_val. Insert insns to compute new compare value.
8957 ??? Turn this off due to possible overflow. */
8964 {
8965 rtx tem;
8975 /* Replace biv with giv's reduced register. */
8979 /* Compute value to compare against. */
8986 }
8987 }
8989 /* This code has problems. Basically, you can't know when
8990 seeing if we will eliminate BL, whether a particular giv
8991 of ARG will be reduced. If it isn't going to be reduced,
8992 we can't eliminate BL. We can try forcing it to be reduced,
8993 but that can generate poor code.
8995 The problem is that the benefit of reducing TV, below should
8996 be increased if BL can actually be eliminated, but this means
8997 we might have to do a topological sort of the order in which
8998 we try to process biv. It doesn't seem worthwhile to do
8999 this sort of thing now. */
9001 #if 0
9002 /* Otherwise the reg compared with had better be a biv. */
9007 /* Look for a pair of givs, one for each biv,
9008 with identical coefficients. */
9010 {
9022 {
9029 /* Replace biv with its giv's reduced reg. */
9031 /* Replace other operand with the other giv's
9032 reduced reg. */
9035 }
9036 }
9037 #endif
9038 }
9040 /* If we get here, the biv can't be eliminated. */
9044 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9045 biv is used in it, since it will be replaced. */
9053 }
9055 /* See if any subexpression fails elimination. */
9058 {
9060 {
9073 }
9074 }
9077 }
9078 \f
9079 /* Return nonzero if the last use of REG
9080 is in an insn following INSN in the same basic block. */
9082 static int
9084 {
9085 rtx n;
9089 {
9092 }
9094 }
9095 \f
9096 /* Called via `note_stores' to record the initial value of a biv. Here we
9097 just record the location of the set and process it later. */
9099 static void
9101 {
9112 /* If this is the first set found, record it. */
9114 {
9117 }
9118 }
9119 \f
9120 /* If any of the registers in X are "old" and currently have a last use earlier
9121 than INSN, update them to have a last use of INSN. Their actual last use
9122 will be the previous insn but it will not have a valid uid_luid so we can't
9123 use it. X must be a source expression only. */
9125 static void
9127 {
9128 /* Check for the case where INSN does not have a valid luid. In this case,
9129 there is no need to modify the regno_last_uid, as this can only happen
9130 when code is inserted after the loop_end to set a pseudo's final value,
9131 and hence this insn will never be the last use of x.
9132 ???? This comment is not correct. See for example loop_givs_reduce.
9133 This may insert an insn before another new insn. */
9137 {
9139 }
9140 else
9141 {
9145 {
9151 }
9152 }
9153 }
9154 \f
9155 /* Given an insn INSN and condition COND, return the condition in a
9156 canonical form to simplify testing by callers. Specifically:
9158 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9159 (2) Both operands will be machine operands; (cc0) will have been replaced.
9160 (3) If an operand is a constant, it will be the second operand.
9161 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9162 for GE, GEU, and LEU.
9164 If the condition cannot be understood, or is an inequality floating-point
9165 comparison which needs to be reversed, 0 will be returned.
9167 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9169 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9170 insn used in locating the condition was found. If a replacement test
9171 of the condition is desired, it should be placed in front of that
9172 insn and we will be sure that the inputs are still valid.
9174 If WANT_REG is nonzero, we wish the condition to be relative to that
9175 register, if possible. Therefore, do not canonicalize the condition
9176 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9177 to be a compare to a CC mode register. */
9179 rtx
9182 {
9185 rtx set;
9186 rtx tem;
9204 /* If we are comparing a register with zero, see if the register is set
9205 in the previous insn to a COMPARE or a comparison operation. Perform
9206 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9207 in cse.c */
9213 {
9214 /* Set nonzero when we find something of interest. */
9217 #ifdef HAVE_cc0
9218 /* If comparison with cc0, import actual comparison from compare
9219 insn. */
9221 {
9232 }
9233 #endif
9235 /* If this is a COMPARE, pick up the two things being compared. */
9237 {
9241 }
9245 /* Go back to the previous insn. Stop if it is not an INSN. We also
9246 stop if it isn't a single set or if it has a REG_INC note because
9247 we don't want to bother dealing with it. */
9261 /* If this is setting OP0, get what it sets it to if it looks
9262 relevant. */
9264 {
9266 #ifdef FLOAT_STORE_FLAG_VALUE
9267 REAL_VALUE_TYPE fsfv;
9268 #endif
9270 /* ??? We may not combine comparisons done in a CCmode with
9271 comparisons not done in a CCmode. This is to aid targets
9272 like Alpha that have an IEEE compliant EQ instruction, and
9273 a non-IEEE compliant BEQ instruction. The use of CCmode is
9274 actually artificial, simply to prevent the combination, but
9275 should not affect other platforms.
9277 However, we must allow VOIDmode comparisons to match either
9278 CCmode or non-CCmode comparison, because some ports have
9279 modeless comparisons inside branch patterns.
9281 ??? This mode check should perhaps look more like the mode check
9282 in simplify_comparison in combine. */
9290 && (STORE_FLAG_VALUE
9293 #ifdef FLOAT_STORE_FLAG_VALUE
9298 #endif
9299 ))
9310 && (STORE_FLAG_VALUE
9313 #ifdef FLOAT_STORE_FLAG_VALUE
9318 #endif
9319 ))
9325 {
9328 }
9329 else
9331 }
9334 /* If this sets OP0, but not directly, we have to give up. */
9338 {
9342 {
9347 }
9352 }
9353 }
9355 /* If constant is first, put it last. */
9359 /* If OP0 is the result of a comparison, we weren't able to find what
9360 was really being compared, so fail. */
9365 /* Canonicalize any ordered comparison with integers involving equality
9366 if we can do computations in the relevant mode and we do not
9367 overflow. */
9373 {
9376 unsigned HOST_WIDE_INT max_val
9380 {
9386 /* When cross-compiling, const_val might be sign-extended from
9387 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9407 }
9408 }
9410 /* Never return CC0; return zero instead. */
9415 }
9417 /* Given a jump insn JUMP, return the condition that will cause it to branch
9418 to its JUMP_LABEL. If the condition cannot be understood, or is an
9419 inequality floating-point comparison which needs to be reversed, 0 will
9420 be returned.
9422 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9423 insn used in locating the condition was found. If a replacement test
9424 of the condition is desired, it should be placed in front of that
9425 insn and we will be sure that the inputs are still valid.
9427 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9428 compare CC mode register. */
9430 rtx
9432 {
9433 rtx cond;
9435 rtx set;
9437 /* If this is not a standard conditional jump, we can't parse it. */
9445 /* If this branches to JUMP_LABEL when the condition is false, reverse
9446 the condition. */
9447 reverse
9452 allow_cc_mode);
9453 }
9455 /* Similar to above routine, except that we also put an invariant last
9456 unless both operands are invariants. */
9458 rtx
9460 {
9470 }
9472 /* Scan the function and determine whether it has indirect (computed) jumps.
9474 This is taken mostly from flow.c; similar code exists elsewhere
9475 in the compiler. It may be useful to put this into rtlanal.c. */
9476 static int
9478 {
9479 rtx insn;
9486 }
9488 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9489 documentation for LOOP_MEMS for the definition of `appropriate'.
9490 This function is called from prescan_loop via for_each_rtx. */
9492 static int
9494 {
9503 {
9508 /* We're not interested in MEMs that are only clobbered. */
9512 /* We're not interested in the MEM associated with a
9513 CONST_DOUBLE, so there's no need to traverse into this. */
9517 /* We're not interested in any MEMs that only appear in notes. */
9521 /* This is not a MEM. */
9523 }
9525 /* See if we've already seen this MEM. */
9528 {
9532 /* The modes of the two memory accesses are different. If
9533 this happens, something tricky is going on, and we just
9534 don't optimize accesses to this MEM. */
9538 }
9540 /* Resize the array, if necessary. */
9542 {
9545 else
9550 }
9552 /* Actually insert the MEM. */
9554 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9555 because we can't put it in a register. We still store it in the
9556 table, though, so that if we see the same address later, but in a
9557 non-BLK mode, we'll not think we can optimize it at that point. */
9563 }
9566 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9568 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9569 register that is modified by an insn between FROM and TO. If the
9570 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9571 more, stop incrementing it, to avoid overflow.
9573 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9574 register I is used, if it is only used once. Otherwise, it is set
9575 to 0 (for no uses) or const0_rtx for more than one use. This
9576 parameter may be zero, in which case this processing is not done.
9578 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9579 optimize register I. */
9581 static void
9583 {
9586 /* last_set[n] is nonzero iff reg n has been set in the current
9587 basic block. In that case, it is the insn that last set reg n. */
9589 rtx insn;
9595 /* Grow the regs array if not allocated or too small. */
9597 {
9602 /* Zero the new elements. */
9605 }
9607 /* Clear previously scanned fields but do not clear n_times_set. */
9609 {
9613 }
9617 /* Scan the loop, recording register usage. */
9620 {
9622 {
9623 /* Record registers that have exactly one use. */
9626 /* Include uses in REG_EQUAL notes. */
9634 {
9638 last_set);
9639 }
9640 }
9645 /* Invalidate all registers used for function argument passing.
9646 We check rtx_varies_p for the same reason as below, to allow
9647 optimizing PIC calculations. */
9649 {
9650 rtx link;
9652 link;
9654 {
9661 }
9662 }
9663 }
9665 /* Invalidate all hard registers clobbered by calls. With one exception:
9666 a call-clobbered PIC register is still function-invariant for our
9667 purposes, since we can hoist any PIC calculations out of the loop.
9668 Thus the call to rtx_varies_p. */
9673 {
9676 }
9678 #ifdef AVOID_CCMODE_COPIES
9679 /* Don't try to move insns which set CC registers if we should not
9680 create CCmode register copies. */
9684 #endif
9686 /* Set regs->array[I].n_times_set for the new registers. */
9691 }
9693 /* Returns the number of real INSNs in the LOOP. */
9695 static int
9697 {
9699 rtx insn;
9707 }
9709 /* Move MEMs into registers for the duration of the loop. */
9711 static void
9713 {
9720 rtx end_label;
9721 /* Nonzero if the next instruction may never be executed. */
9728 /* We cannot use next_label here because it skips over normal insns. */
9733 /* Check to see if it's possible that some instructions in the loop are
9734 never executed. Also check if there is a goto out of the loop other
9735 than right after the end of the loop. */
9739 {
9743 /* If we enter the loop in the middle, and scan
9744 around to the beginning, don't set maybe_never
9745 for that. This must be an unconditional jump,
9746 otherwise the code at the top of the loop might
9747 never be executed. Unconditional jumps are
9748 followed a by barrier then loop end. */
9753 {
9754 /* If this is a jump outside of the loop but not right
9755 after the end of the loop, we would have to emit new fixup
9756 sequences for each such label. */
9758 JUMP_INSN is executed, we must be conservative. */
9767 /* Something complicated. */
9769 else
9770 /* If there are any more instructions in the loop, they
9771 might not be reached. */
9773 }
9776 }
9778 /* Find start of the extended basic block that enters the loop. */
9782 ;
9787 /* Build table of mems that get set to constant values before the
9788 loop. */
9792 /* Actually move the MEMs. */
9794 {
9795 regset_head load_copies;
9796 regset_head store_copies;
9798 rtx reg;
9800 rtx mem_list_entry;
9804 /* There's no telling whether or not MEM is modified. */
9807 /* Go through the MEMs written to in the loop to see if this
9808 one is aliased by one of them. */
9811 {
9816 {
9817 /* MEM is indeed aliased by this store. */
9820 }
9822 }
9828 /* If this MEM is written to, we must be sure that there
9829 are no reads from another MEM that aliases this one. */
9831 {
9835 {
9839 VOIDmode,
9841 rtx_varies_p))
9842 {
9843 /* It's not safe to hoist loop_info->mems[i] out of
9844 the loop because writes to it might not be
9845 seen by reads from loop_info->mems[j]. */
9848 }
9849 }
9850 }
9853 /* We can't access the MEM outside the loop; it might
9854 cause a trap that wouldn't have happened otherwise. */
9858 /* We thought we were going to lift this MEM out of the
9859 loop, but later discovered that we could not. */
9865 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9866 order to keep scan_loop from moving stores to this MEM
9867 out of the loop just because this REG is neither a
9868 user-variable nor used in the loop test. */
9873 /* Now, replace all references to the MEM with the
9874 corresponding pseudos. */
9879 {
9881 {
9882 rtx set;
9886 /* See if this copies the mem into a register that isn't
9887 modified afterwards. We'll try to do copy propagation
9888 a little further on. */
9890 /* @@@ This test is _way_ too conservative. */
9891 && ! maybe_never
9899 /* See if this copies the mem from a register that isn't
9900 modified afterwards. We'll try to remove the
9901 redundant copy later on by doing a little register
9902 renaming and copy propagation. This will help
9903 to untangle things for the BIV detection code. */
9905 && ! maybe_never
9913 /* If this is a call which uses / clobbers this memory
9914 location, we must not change the interface here. */
9918 {
9922 }
9923 else
9924 /* Replace the memory reference with the shadow register. */
9927 }
9932 }
9937 /* We couldn't replace all occurrences of the MEM. */
9939 else
9940 {
9941 /* Load the memory immediately before LOOP->START, which is
9942 the NOTE_LOOP_BEG. */
9944 rtx set;
9950 {
9954 {
9958 /* Extending hard register lifetimes causes crash
9959 on SRC targets. Doing so on non-SRC is
9960 probably also not good idea, since we most
9961 probably have pseudoregister equivalence as
9962 well. */
9965 }
9966 /* Use the constant equivalence if that is cheap enough. */
9972 {
9975 }
9977 /* If best_equiv is nonzero, we know that MEM is set to a
9978 constant or register before the loop. We will use this
9979 knowledge to initialize the shadow register with that
9980 constant or reg rather than by loading from MEM. */
9983 }
9988 {
9991 {
9994 }
9995 }
10001 {
10003 {
10006 }
10008 /* Store the memory immediately after END, which is
10009 the NOTE_LOOP_END. */
10012 }
10015 {
10020 }
10022 /* Attempt a bit of copy propagation. This helps untangle the
10023 data flow, and enables {basic,general}_induction_var to find
10024 more bivs/givs. */
10025 EXECUTE_IF_SET_IN_REG_SET
10027 {
10029 });
10032 EXECUTE_IF_SET_IN_REG_SET
10034 {
10036 });
10038 }
10039 }
10041 /* Now, we need to replace all references to the previous exit
10042 label with the new one. */
10049 }
10051 /* For communication between note_reg_stored and its caller. */
10052 struct note_reg_stored_arg
10053 {
10055 rtx reg;
10056 };
10058 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10059 is equal to ARG. */
10060 static void
10062 {
10066 }
10068 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10069 There must be exactly one insn that sets this pseudo; it will be
10070 deleted if all replacements succeed and we can prove that the register
10071 is not used after the loop. */
10073 static void
10075 {
10076 /* This is the reg that we are copying from. */
10079 rtx insn;
10080 /* These help keep track of whether we replaced all uses of the reg. */
10087 {
10088 rtx set;
10090 /* Only substitute within one extended basic block from the initializing
10091 insn. */
10098 /* Is this the initializing insn? */
10103 {
10110 }
10112 /* Only substitute after seeing the initializing insn. */
10114 {
10121 /* Stop replacing when REPLACEMENT is modified. */
10126 {
10129 /* It is possible that we've turned previously valid REG_EQUAL to
10130 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10131 REPLACEMENT is modified, we get different meaning. */
10135 }
10136 }
10137 }
10141 {
10145 {
10146 rtx first;
10147 rtx retval_note;
10149 /* Assume we're just deleting INIT_INSN. */
10151 /* Look for REG_RETVAL note. If we're deleting the end of
10152 the libcall sequence, the whole sequence can go. */
10154 /* If we found a REG_RETVAL note, find the first instruction
10155 in the sequence. */
10159 /* Delete the instructions. */
10161 }
10164 }
10165 }
10167 /* Replace all the instructions from FIRST up to and including LAST
10168 with NOTE_INSN_DELETED notes. */
10170 static void
10172 {
10174 {
10180 /* If this was the LAST instructions we're supposed to delete,
10181 we're done. */
10186 }
10187 }
10189 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10190 loop LOOP if the order of the sets of these registers can be
10191 swapped. There must be exactly one insn within the loop that sets
10192 this pseudo followed immediately by a move insn that sets
10193 REPLACEMENT with REGNO. */
10194 static void
10197 {
10198 rtx insn;
10207 {
10208 /* Search for the insn that copies REGNO to NEW_REGNO? */
10216 }
10219 {
10220 rtx prev_insn;
10221 rtx prev_set;
10223 /* Some DEF-USE info would come in handy here to make this
10224 function more general. For now, just check the previous insn
10225 which is the most likely candidate for setting REGNO. */
10233 {
10234 /* We have:
10235 (set (reg regno) (expr))
10236 (set (reg new_regno) (reg regno))
10238 so try converting this to:
10239 (set (reg new_regno) (expr))
10240 (set (reg regno) (reg new_regno))
10242 The former construct is often generated when a global
10243 variable used for an induction variable is shadowed by a
10244 register (NEW_REGNO). The latter construct improves the
10245 chances of GIV replacement and BIV elimination. */
10255 {
10262 /* Update first use of REGNO. */
10266 /* Now perform copy propagation to hopefully
10267 remove all uses of REGNO within the loop. */
10269 }
10270 }
10271 }
10272 }
10274 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10276 static int
10278 {
10280 {
10284 }
10286 }
10288 /* Returns the first MEM found in NOTE by depth-first search. */
10290 static rtx
10292 {
10296 }
10298 /* Replace MEM with its associated pseudo register. This function is
10299 called from load_mems via for_each_rtx. DATA is actually a pointer
10300 to a structure describing the instruction currently being scanned
10301 and the MEM we are currently replacing. */
10303 static int
10305 {
10313 {
10318 /* We're not interested in the MEM associated with a
10319 CONST_DOUBLE, so there's no need to traverse into one. */
10323 /* This is not a MEM. */
10325 }
10328 /* This is not the MEM we are currently replacing. */
10331 /* Actually replace the MEM. */
10335 }
10337 static void
10339 {
10340 loop_replace_args args;
10348 /* If we hoist a mem write out of the loop, then REG_EQUAL
10349 notes referring to the mem are no longer valid. */
10351 {
10356 {
10360 {
10361 /* Remove the note. */
10364 }
10365 }
10366 }
10367 }
10369 /* Replace one register with another. Called through for_each_rtx; PX points
10370 to the rtx being scanned. DATA is actually a pointer to
10371 a structure of arguments. */
10373 static int
10375 {
10386 }
10388 static void
10390 {
10391 loop_replace_args args;
10398 }
10399 \f
10400 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10401 (ignored in the interim). */
10403 static rtx
10406 rtx pattern)
10407 {
10409 }
10412 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10413 in basic block WHERE_BB (ignored in the interim) within the loop
10414 otherwise hoist PATTERN into the loop pre-header. */
10416 rtx
10418 basic_block where_bb ATTRIBUTE_UNUSED,
10420 {
10424 }
10427 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10428 WHERE_BB (ignored in the interim) within the loop. */
10430 static rtx
10432 basic_block where_bb ATTRIBUTE_UNUSED,
10434 {
10436 }
10439 /* Hoist insn for PATTERN into the loop pre-header. */
10441 rtx
10443 {
10445 }
10448 /* Hoist call insn for PATTERN into the loop pre-header. */
10450 static rtx
10452 {
10454 }
10457 /* Sink insn for PATTERN after the loop end. */
10459 rtx
10461 {
10463 }
10465 /* bl->final_value can be either general_operand or PLUS of general_operand
10466 and constant. Emit sequence of instructions to load it into REG. */
10467 static rtx
10469 {
10470 rtx seq;
10478 }
10480 /* If the loop has multiple exits, emit insn for PATTERN before the
10481 loop to ensure that it will always be executed no matter how the
10482 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10483 since this is slightly more efficient. */
10485 static rtx
10487 {
10490 else
10492 }
10493 \f
10494 static void
10496 {
10504 iv_num++;
10509 {
10512 }
10513 }
10516 static void
10519 {
10521 rtx incr;
10532 {
10535 }
10537 {
10540 }
10544 {
10548 }
10551 {
10555 }
10557 /* List the increments. */
10559 {
10563 }
10565 /* List the givs. */
10567 {
10572 else
10575 }
10576 }
10579 static void
10581 {
10592 {
10596 }
10599 }
10602 static void
10604 {
10611 else
10627 {
10629 {
10641 }
10642 }
10653 {
10657 }
10660 }
10663 void
10665 {
10667 }
10670 void
10672 {
10674 }
10677 void
10679 {
10681 }
10684 void
10686 {
10688 }
10691 #define LOOP_BLOCK_NUM_1(INSN) \
10692 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10694 /* The notes do not have an assigned block, so look at the next insn. */
10695 #define LOOP_BLOCK_NUM(INSN) \
10696 ((INSN) ? (GET_CODE (INSN) == NOTE \
10697 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10698 : LOOP_BLOCK_NUM_1 (INSN)) \
10699 : -1)
10701 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10703 static void
10706 {
10707 rtx label;
10712 /* Print diagnostics to compare our concept of a loop with
10713 what the loop notes say. */
10728 {
10748 {
10751 {
10754 }
10755 }
10758 /* This can happen when a marked loop appears as two nested loops,
10759 say from while (a || b) {}. The inner loop won't match
10760 the loop markers but the outer one will. */
10763 }
10764 }
10766 /* Call this function from the debugger to dump LOOP. */
10768 void
10770 {
10772 }
10774 /* Call this function from the debugger to dump LOOPS. */
10776 void
10778 {
10780 }