1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
39 /* Forward declarations */
40 static void set_of_1 (rtx
, const_rtx
, void *);
41 static bool covers_regno_p (const_rtx
, unsigned int);
42 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
43 static int computed_jump_p_1 (const_rtx
);
44 static void parms_set (rtx
, const_rtx
, void *);
46 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
47 const_rtx
, machine_mode
,
48 unsigned HOST_WIDE_INT
);
49 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
50 const_rtx
, machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
55 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
56 machine_mode
, unsigned int);
58 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
59 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
61 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
62 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
63 SIGN_EXTEND then while narrowing we also have to enforce the
64 representation and sign-extend the value to mode DESTINATION_REP.
66 If the value is already sign-extended to DESTINATION_REP mode we
67 can just switch to DESTINATION mode on it. For each pair of
68 integral modes SOURCE and DESTINATION, when truncating from SOURCE
69 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
70 contains the number of high-order bits in SOURCE that have to be
71 copies of the sign-bit so that we can do this mode-switch to
75 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
77 /* Store X into index I of ARRAY. ARRAY is known to have at least I
78 elements. Return the new base of ARRAY. */
81 typename
T::value_type
*
82 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
84 size_t i
, value_type x
)
86 if (base
== array
.stack
)
93 gcc_checking_assert (i
== LOCAL_ELEMS
);
94 /* A previous iteration might also have moved from the stack to the
95 heap, in which case the heap array will already be big enough. */
96 if (vec_safe_length (array
.heap
) <= i
)
97 vec_safe_grow (array
.heap
, i
+ 1);
98 base
= array
.heap
->address ();
99 memcpy (base
, array
.stack
, sizeof (array
.stack
));
100 base
[LOCAL_ELEMS
] = x
;
103 unsigned int length
= array
.heap
->length ();
106 gcc_checking_assert (base
== array
.heap
->address ());
112 gcc_checking_assert (i
== length
);
113 vec_safe_push (array
.heap
, x
);
114 return array
.heap
->address ();
118 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
119 number of elements added to the worklist. */
121 template <typename T
>
123 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
125 size_t end
, rtx_type x
)
127 enum rtx_code code
= GET_CODE (x
);
128 const char *format
= GET_RTX_FORMAT (code
);
129 size_t orig_end
= end
;
130 if (__builtin_expect (INSN_P (x
), false))
132 /* Put the pattern at the top of the queue, since that's what
133 we're likely to want most. It also allows for the SEQUENCE
135 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
136 if (format
[i
] == 'e')
138 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
139 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
142 base
= add_single_to_queue (array
, base
, end
++, subx
);
146 for (int i
= 0; format
[i
]; ++i
)
147 if (format
[i
] == 'e')
149 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
150 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
153 base
= add_single_to_queue (array
, base
, end
++, subx
);
155 else if (format
[i
] == 'E')
157 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
158 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
159 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
160 for (unsigned int j
= 0; j
< length
; j
++)
161 base
[end
++] = T::get_value (vec
[j
]);
163 for (unsigned int j
= 0; j
< length
; j
++)
164 base
= add_single_to_queue (array
, base
, end
++,
165 T::get_value (vec
[j
]));
166 if (code
== SEQUENCE
&& end
== length
)
167 /* If the subrtxes of the sequence fill the entire array then
168 we know that no other parts of a containing insn are queued.
169 The caller is therefore iterating over the sequence as a
170 PATTERN (...), so we also want the patterns of the
172 for (unsigned int j
= 0; j
< length
; j
++)
174 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
176 base
[j
] = T::get_value (PATTERN (x
));
179 return end
- orig_end
;
182 template <typename T
>
184 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
186 vec_free (array
.heap
);
189 template <typename T
>
190 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
192 template class generic_subrtx_iterator
<const_rtx_accessor
>;
193 template class generic_subrtx_iterator
<rtx_var_accessor
>;
194 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
196 /* Return 1 if the value of X is unstable
197 (would be different at a different point in the program).
198 The frame pointer, arg pointer, etc. are considered stable
199 (within one function) and so is anything marked `unchanging'. */
202 rtx_unstable_p (const_rtx x
)
204 const RTX_CODE code
= GET_CODE (x
);
211 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
220 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
221 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
222 /* The arg pointer varies if it is not a fixed register. */
223 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
225 /* ??? When call-clobbered, the value is stable modulo the restore
226 that must happen after a call. This currently screws up local-alloc
227 into believing that the restore is not needed. */
228 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
233 if (MEM_VOLATILE_P (x
))
242 fmt
= GET_RTX_FORMAT (code
);
243 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
246 if (rtx_unstable_p (XEXP (x
, i
)))
249 else if (fmt
[i
] == 'E')
252 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
253 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
260 /* Return 1 if X has a value that can vary even between two
261 executions of the program. 0 means X can be compared reliably
262 against certain constants or near-constants.
263 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
264 zero, we are slightly more conservative.
265 The frame pointer and the arg pointer are considered constant. */
268 rtx_varies_p (const_rtx x
, bool for_alias
)
281 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
290 /* Note that we have to test for the actual rtx used for the frame
291 and arg pointers and not just the register number in case we have
292 eliminated the frame and/or arg pointer and are using it
294 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
295 /* The arg pointer varies if it is not a fixed register. */
296 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
298 if (x
== pic_offset_table_rtx
299 /* ??? When call-clobbered, the value is stable modulo the restore
300 that must happen after a call. This currently screws up
301 local-alloc into believing that the restore is not needed, so we
302 must return 0 only if we are called from alias analysis. */
303 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
308 /* The operand 0 of a LO_SUM is considered constant
309 (in fact it is related specifically to operand 1)
310 during alias analysis. */
311 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
312 || rtx_varies_p (XEXP (x
, 1), for_alias
);
315 if (MEM_VOLATILE_P (x
))
324 fmt
= GET_RTX_FORMAT (code
);
325 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
328 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
331 else if (fmt
[i
] == 'E')
334 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
335 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
342 /* Compute an approximation for the offset between the register
343 FROM and TO for the current function, as it was at the start
347 get_initial_register_offset (int from
, int to
)
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
454 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
455 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
456 references on strict alignment machines. */
459 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
460 machine_mode mode
, bool unaligned_mems
)
462 enum rtx_code code
= GET_CODE (x
);
464 /* The offset must be a multiple of the mode size if we are considering
465 unaligned memory references on strict alignment machines. */
466 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
468 HOST_WIDE_INT actual_offset
= offset
;
470 #ifdef SPARC_STACK_BOUNDARY_HACK
471 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
472 the real alignment of %sp. However, when it does this, the
473 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
474 if (SPARC_STACK_BOUNDARY_HACK
475 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
476 actual_offset
-= STACK_POINTER_OFFSET
;
479 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
486 if (SYMBOL_REF_WEAK (x
))
488 if (!CONSTANT_POOL_ADDRESS_P (x
))
491 HOST_WIDE_INT decl_size
;
496 size
= GET_MODE_SIZE (mode
);
500 /* If the size of the access or of the symbol is unknown,
502 decl
= SYMBOL_REF_DECL (x
);
504 /* Else check that the access is in bounds. TODO: restructure
505 expr_size/tree_expr_size/int_expr_size and just use the latter. */
508 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
509 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
510 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
512 else if (TREE_CODE (decl
) == STRING_CST
)
513 decl_size
= TREE_STRING_LENGTH (decl
);
514 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
515 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
519 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
528 /* Stack references are assumed not to trap, but we need to deal with
529 nonsensical offsets. */
530 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
531 || x
== stack_pointer_rtx
532 /* The arg pointer varies if it is not a fixed register. */
533 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
536 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
538 HOST_WIDE_INT red_zone_size
= 0;
540 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
542 HOST_WIDE_INT low_bound
, high_bound
;
545 size
= GET_MODE_SIZE (mode
);
547 if (x
== frame_pointer_rtx
)
549 if (FRAME_GROWS_DOWNWARD
)
551 high_bound
= STARTING_FRAME_OFFSET
;
552 low_bound
= high_bound
- get_frame_size ();
556 low_bound
= STARTING_FRAME_OFFSET
;
557 high_bound
= low_bound
+ get_frame_size ();
560 else if (x
== hard_frame_pointer_rtx
)
562 HOST_WIDE_INT sp_offset
563 = get_initial_register_offset (STACK_POINTER_REGNUM
,
564 HARD_FRAME_POINTER_REGNUM
);
565 HOST_WIDE_INT ap_offset
566 = get_initial_register_offset (ARG_POINTER_REGNUM
,
567 HARD_FRAME_POINTER_REGNUM
);
569 #if STACK_GROWS_DOWNWARD
570 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
571 high_bound
= ap_offset
572 + FIRST_PARM_OFFSET (current_function_decl
)
573 #if !ARGS_GROW_DOWNWARD
578 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
579 low_bound
= ap_offset
580 + FIRST_PARM_OFFSET (current_function_decl
)
581 #if ARGS_GROW_DOWNWARD
587 else if (x
== stack_pointer_rtx
)
589 HOST_WIDE_INT ap_offset
590 = get_initial_register_offset (ARG_POINTER_REGNUM
,
591 STACK_POINTER_REGNUM
);
593 #if STACK_GROWS_DOWNWARD
594 low_bound
= - red_zone_size
- stack_boundary
;
595 high_bound
= ap_offset
596 + FIRST_PARM_OFFSET (current_function_decl
)
597 #if !ARGS_GROW_DOWNWARD
602 high_bound
= red_zone_size
+ stack_boundary
;
603 low_bound
= ap_offset
604 + FIRST_PARM_OFFSET (current_function_decl
)
605 #if ARGS_GROW_DOWNWARD
613 /* We assume that accesses are safe to at least the
615 Examples are varargs and __builtin_return_address. */
616 #if ARGS_GROW_DOWNWARD
617 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
619 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
620 - crtl
->args
.size
- stack_boundary
;
622 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
625 + crtl
->args
.size
+ stack_boundary
;
629 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
633 /* All of the virtual frame registers are stack references. */
634 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
635 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
640 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
641 mode
, unaligned_mems
);
644 /* An address is assumed not to trap if:
645 - it is the pic register plus a constant. */
646 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
649 /* - or it is an address that can't trap plus a constant integer. */
650 if (CONST_INT_P (XEXP (x
, 1))
651 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
652 size
, mode
, unaligned_mems
))
659 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
660 mode
, unaligned_mems
);
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
668 mode
, unaligned_mems
);
674 /* If it isn't one of the case above, it can cause a trap. */
678 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
681 rtx_addr_can_trap_p (const_rtx x
)
683 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
686 /* Return true if X is an address that is known to not be zero. */
689 nonzero_address_p (const_rtx x
)
691 const enum rtx_code code
= GET_CODE (x
);
696 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
702 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
703 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
704 || x
== stack_pointer_rtx
705 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
707 /* All of the virtual frame registers are stack references. */
708 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
709 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
714 return nonzero_address_p (XEXP (x
, 0));
717 /* Handle PIC references. */
718 if (XEXP (x
, 0) == pic_offset_table_rtx
719 && CONSTANT_P (XEXP (x
, 1)))
724 /* Similar to the above; allow positive offsets. Further, since
725 auto-inc is only allowed in memories, the register must be a
727 if (CONST_INT_P (XEXP (x
, 1))
728 && INTVAL (XEXP (x
, 1)) > 0)
730 return nonzero_address_p (XEXP (x
, 0));
733 /* Similarly. Further, the offset is always positive. */
740 return nonzero_address_p (XEXP (x
, 0));
743 return nonzero_address_p (XEXP (x
, 1));
749 /* If it isn't one of the case above, might be zero. */
753 /* Return 1 if X refers to a memory location whose address
754 cannot be compared reliably with constant addresses,
755 or if X refers to a BLKmode memory object.
756 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
757 zero, we are slightly more conservative. */
760 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
771 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
773 fmt
= GET_RTX_FORMAT (code
);
774 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
777 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
780 else if (fmt
[i
] == 'E')
783 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
784 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
790 /* Return the CALL in X if there is one. */
793 get_call_rtx_from (rtx x
)
797 if (GET_CODE (x
) == PARALLEL
)
798 x
= XVECEXP (x
, 0, 0);
799 if (GET_CODE (x
) == SET
)
801 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
806 /* Return the value of the integer term in X, if one is apparent;
808 Only obvious integer terms are detected.
809 This is used in cse.c with the `related_value' field. */
812 get_integer_term (const_rtx x
)
814 if (GET_CODE (x
) == CONST
)
817 if (GET_CODE (x
) == MINUS
818 && CONST_INT_P (XEXP (x
, 1)))
819 return - INTVAL (XEXP (x
, 1));
820 if (GET_CODE (x
) == PLUS
821 && CONST_INT_P (XEXP (x
, 1)))
822 return INTVAL (XEXP (x
, 1));
826 /* If X is a constant, return the value sans apparent integer term;
828 Only obvious integer terms are detected. */
831 get_related_value (const_rtx x
)
833 if (GET_CODE (x
) != CONST
)
836 if (GET_CODE (x
) == PLUS
837 && CONST_INT_P (XEXP (x
, 1)))
839 else if (GET_CODE (x
) == MINUS
840 && CONST_INT_P (XEXP (x
, 1)))
845 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
846 to somewhere in the same object or object_block as SYMBOL. */
849 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
853 if (GET_CODE (symbol
) != SYMBOL_REF
)
861 if (CONSTANT_POOL_ADDRESS_P (symbol
)
862 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
865 decl
= SYMBOL_REF_DECL (symbol
);
866 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
870 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
871 && SYMBOL_REF_BLOCK (symbol
)
872 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
873 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
874 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
880 /* Split X into a base and a constant offset, storing them in *BASE_OUT
881 and *OFFSET_OUT respectively. */
884 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
886 if (GET_CODE (x
) == CONST
)
889 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
891 *base_out
= XEXP (x
, 0);
892 *offset_out
= XEXP (x
, 1);
897 *offset_out
= const0_rtx
;
900 /* Return the number of places FIND appears within X. If COUNT_DEST is
901 zero, we do not count occurrences inside the destination of a SET. */
904 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
908 const char *format_ptr
;
927 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
929 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
933 if (MEM_P (find
) && rtx_equal_p (x
, find
))
938 if (SET_DEST (x
) == find
&& ! count_dest
)
939 return count_occurrences (SET_SRC (x
), find
, count_dest
);
946 format_ptr
= GET_RTX_FORMAT (code
);
949 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
951 switch (*format_ptr
++)
954 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
958 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
959 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
967 /* Return TRUE if OP is a register or subreg of a register that
968 holds an unsigned quantity. Otherwise, return FALSE. */
971 unsigned_reg_p (rtx op
)
975 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
978 if (GET_CODE (op
) == SUBREG
979 && SUBREG_PROMOTED_SIGN (op
))
986 /* Nonzero if register REG appears somewhere within IN.
987 Also works if REG is not a register; in this case it checks
988 for a subexpression of IN that is Lisp "equal" to REG. */
991 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1003 if (GET_CODE (in
) == LABEL_REF
)
1004 return reg
== label_ref_label (in
);
1006 code
= GET_CODE (in
);
1010 /* Compare registers by number. */
1012 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1014 /* These codes have no constituent expressions
1022 /* These are kept unique for a given value. */
1029 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1032 fmt
= GET_RTX_FORMAT (code
);
1034 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1039 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1040 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1043 else if (fmt
[i
] == 'e'
1044 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1050 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1051 no CODE_LABEL insn. */
1054 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1059 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1065 /* Nonzero if register REG is used in an insn between
1066 FROM_INSN and TO_INSN (exclusive of those two). */
1069 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1070 const rtx_insn
*to_insn
)
1074 if (from_insn
== to_insn
)
1077 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1078 if (NONDEBUG_INSN_P (insn
)
1079 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1080 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1085 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1086 is entirely replaced by a new value and the only use is as a SET_DEST,
1087 we do not consider it a reference. */
1090 reg_referenced_p (const_rtx x
, const_rtx body
)
1094 switch (GET_CODE (body
))
1097 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1100 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1101 of a REG that occupies all of the REG, the insn references X if
1102 it is mentioned in the destination. */
1103 if (GET_CODE (SET_DEST (body
)) != CC0
1104 && GET_CODE (SET_DEST (body
)) != PC
1105 && !REG_P (SET_DEST (body
))
1106 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1107 && REG_P (SUBREG_REG (SET_DEST (body
)))
1108 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1109 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1110 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1111 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1112 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1117 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1118 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1125 return reg_overlap_mentioned_p (x
, body
);
1128 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1131 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1134 case UNSPEC_VOLATILE
:
1135 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1136 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1141 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1142 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1147 if (MEM_P (XEXP (body
, 0)))
1148 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1153 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1155 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1162 /* Nonzero if register REG is set or clobbered in an insn between
1163 FROM_INSN and TO_INSN (exclusive of those two). */
1166 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1167 const rtx_insn
*to_insn
)
1169 const rtx_insn
*insn
;
1171 if (from_insn
== to_insn
)
1174 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1175 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1180 /* Return true if REG is set or clobbered inside INSN. */
1183 reg_set_p (const_rtx reg
, const_rtx insn
)
1185 /* After delay slot handling, call and branch insns might be in a
1186 sequence. Check all the elements there. */
1187 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1189 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1190 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1196 /* We can be passed an insn or part of one. If we are passed an insn,
1197 check if a side-effect of the insn clobbers REG. */
1199 && (FIND_REG_INC_NOTE (insn
, reg
)
1202 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1203 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1204 GET_MODE (reg
), REGNO (reg
)))
1206 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1209 return set_of (reg
, insn
) != NULL_RTX
;
1212 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1213 only if none of them are modified between START and END. Return 1 if
1214 X contains a MEM; this routine does use memory aliasing. */
1217 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1219 const enum rtx_code code
= GET_CODE (x
);
1240 if (modified_between_p (XEXP (x
, 0), start
, end
))
1242 if (MEM_READONLY_P (x
))
1244 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1245 if (memory_modified_in_insn_p (x
, insn
))
1250 return reg_set_between_p (x
, start
, end
);
1256 fmt
= GET_RTX_FORMAT (code
);
1257 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1259 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1262 else if (fmt
[i
] == 'E')
1263 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1264 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1271 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1272 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1273 does use memory aliasing. */
1276 modified_in_p (const_rtx x
, const_rtx insn
)
1278 const enum rtx_code code
= GET_CODE (x
);
1295 if (modified_in_p (XEXP (x
, 0), insn
))
1297 if (MEM_READONLY_P (x
))
1299 if (memory_modified_in_insn_p (x
, insn
))
1304 return reg_set_p (x
, insn
);
1310 fmt
= GET_RTX_FORMAT (code
);
1311 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1313 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1316 else if (fmt
[i
] == 'E')
1317 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1318 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1325 /* Helper function for set_of. */
1333 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1335 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1336 if (rtx_equal_p (x
, data
->pat
)
1337 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1341 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1342 (either directly or via STRICT_LOW_PART and similar modifiers). */
1344 set_of (const_rtx pat
, const_rtx insn
)
1346 struct set_of_data data
;
1347 data
.found
= NULL_RTX
;
1349 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1353 /* Add all hard register in X to *PSET. */
1355 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1357 subrtx_iterator::array_type array
;
1358 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1360 const_rtx x
= *iter
;
1361 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1362 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1366 /* This function, called through note_stores, collects sets and
1367 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1370 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1372 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1373 if (REG_P (x
) && HARD_REGISTER_P (x
))
1374 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1377 /* Examine INSN, and compute the set of hard registers written by it.
1378 Store it in *PSET. Should only be called after reload. */
1380 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1384 CLEAR_HARD_REG_SET (*pset
);
1385 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1389 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1391 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1392 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1394 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1395 if (REG_NOTE_KIND (link
) == REG_INC
)
1396 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1399 /* Like record_hard_reg_sets, but called through note_uses. */
1401 record_hard_reg_uses (rtx
*px
, void *data
)
1403 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1406 /* Given an INSN, return a SET expression if this insn has only a single SET.
1407 It may also have CLOBBERs, USEs, or SET whose output
1408 will not be used, which we ignore. */
1411 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1414 int set_verified
= 1;
1417 if (GET_CODE (pat
) == PARALLEL
)
1419 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1421 rtx sub
= XVECEXP (pat
, 0, i
);
1422 switch (GET_CODE (sub
))
1429 /* We can consider insns having multiple sets, where all
1430 but one are dead as single set insns. In common case
1431 only single set is present in the pattern so we want
1432 to avoid checking for REG_UNUSED notes unless necessary.
1434 When we reach set first time, we just expect this is
1435 the single set we are looking for and only when more
1436 sets are found in the insn, we check them. */
1439 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1440 && !side_effects_p (set
))
1446 set
= sub
, set_verified
= 0;
1447 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1448 || side_effects_p (sub
))
1460 /* Given an INSN, return nonzero if it has more than one SET, else return
1464 multiple_sets (const_rtx insn
)
1469 /* INSN must be an insn. */
1470 if (! INSN_P (insn
))
1473 /* Only a PARALLEL can have multiple SETs. */
1474 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1476 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1477 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1479 /* If we have already found a SET, then return now. */
1487 /* Either zero or one SET. */
1491 /* Return nonzero if the destination of SET equals the source
1492 and there are no side effects. */
1495 set_noop_p (const_rtx set
)
1497 rtx src
= SET_SRC (set
);
1498 rtx dst
= SET_DEST (set
);
1500 if (dst
== pc_rtx
&& src
== pc_rtx
)
1503 if (MEM_P (dst
) && MEM_P (src
))
1504 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1506 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1507 return rtx_equal_p (XEXP (dst
, 0), src
)
1508 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1509 && !side_effects_p (src
);
1511 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1512 dst
= XEXP (dst
, 0);
1514 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1516 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1518 src
= SUBREG_REG (src
);
1519 dst
= SUBREG_REG (dst
);
1522 /* It is a NOOP if destination overlaps with selected src vector
1524 if (GET_CODE (src
) == VEC_SELECT
1525 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1526 && HARD_REGISTER_P (XEXP (src
, 0))
1527 && HARD_REGISTER_P (dst
))
1530 rtx par
= XEXP (src
, 1);
1531 rtx src0
= XEXP (src
, 0);
1532 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1533 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1535 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1536 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1539 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1540 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1543 return (REG_P (src
) && REG_P (dst
)
1544 && REGNO (src
) == REGNO (dst
));
1547 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1551 noop_move_p (const rtx_insn
*insn
)
1553 rtx pat
= PATTERN (insn
);
1555 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1558 /* Insns carrying these notes are useful later on. */
1559 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1562 /* Check the code to be executed for COND_EXEC. */
1563 if (GET_CODE (pat
) == COND_EXEC
)
1564 pat
= COND_EXEC_CODE (pat
);
1566 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1569 if (GET_CODE (pat
) == PARALLEL
)
1572 /* If nothing but SETs of registers to themselves,
1573 this insn can also be deleted. */
1574 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1576 rtx tem
= XVECEXP (pat
, 0, i
);
1578 if (GET_CODE (tem
) == USE
1579 || GET_CODE (tem
) == CLOBBER
)
1582 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1592 /* Return nonzero if register in range [REGNO, ENDREGNO)
1593 appears either explicitly or implicitly in X
1594 other than being stored into.
1596 References contained within the substructure at LOC do not count.
1597 LOC may be zero, meaning don't ignore anything. */
1600 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1604 unsigned int x_regno
;
1609 /* The contents of a REG_NONNEG note is always zero, so we must come here
1610 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1614 code
= GET_CODE (x
);
1619 x_regno
= REGNO (x
);
1621 /* If we modifying the stack, frame, or argument pointer, it will
1622 clobber a virtual register. In fact, we could be more precise,
1623 but it isn't worth it. */
1624 if ((x_regno
== STACK_POINTER_REGNUM
1625 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1626 && x_regno
== ARG_POINTER_REGNUM
)
1627 || x_regno
== FRAME_POINTER_REGNUM
)
1628 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1631 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1634 /* If this is a SUBREG of a hard reg, we can see exactly which
1635 registers are being modified. Otherwise, handle normally. */
1636 if (REG_P (SUBREG_REG (x
))
1637 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1639 unsigned int inner_regno
= subreg_regno (x
);
1640 unsigned int inner_endregno
1641 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1642 ? subreg_nregs (x
) : 1);
1644 return endregno
> inner_regno
&& regno
< inner_endregno
;
1650 if (&SET_DEST (x
) != loc
1651 /* Note setting a SUBREG counts as referring to the REG it is in for
1652 a pseudo but not for hard registers since we can
1653 treat each word individually. */
1654 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1655 && loc
!= &SUBREG_REG (SET_DEST (x
))
1656 && REG_P (SUBREG_REG (SET_DEST (x
)))
1657 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1658 && refers_to_regno_p (regno
, endregno
,
1659 SUBREG_REG (SET_DEST (x
)), loc
))
1660 || (!REG_P (SET_DEST (x
))
1661 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1664 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1673 /* X does not match, so try its subexpressions. */
1675 fmt
= GET_RTX_FORMAT (code
);
1676 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1678 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1686 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1689 else if (fmt
[i
] == 'E')
1692 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1693 if (loc
!= &XVECEXP (x
, i
, j
)
1694 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1701 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1702 we check if any register number in X conflicts with the relevant register
1703 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1704 contains a MEM (we don't bother checking for memory addresses that can't
1705 conflict because we expect this to be a rare case. */
1708 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1710 unsigned int regno
, endregno
;
1712 /* If either argument is a constant, then modifying X can not
1713 affect IN. Here we look at IN, we can profitably combine
1714 CONSTANT_P (x) with the switch statement below. */
1715 if (CONSTANT_P (in
))
1719 switch (GET_CODE (x
))
1721 case STRICT_LOW_PART
:
1724 /* Overly conservative. */
1729 regno
= REGNO (SUBREG_REG (x
));
1730 if (regno
< FIRST_PSEUDO_REGISTER
)
1731 regno
= subreg_regno (x
);
1732 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1733 ? subreg_nregs (x
) : 1);
1738 endregno
= END_REGNO (x
);
1740 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1750 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1751 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1754 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1757 else if (fmt
[i
] == 'E')
1760 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1761 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1771 return reg_mentioned_p (x
, in
);
1777 /* If any register in here refers to it we return true. */
1778 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1779 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1780 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1786 gcc_assert (CONSTANT_P (x
));
1791 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1792 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1793 ignored by note_stores, but passed to FUN.
1795 FUN receives three arguments:
1796 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1797 2. the SET or CLOBBER rtx that does the store,
1798 3. the pointer DATA provided to note_stores.
1800 If the item being stored in or clobbered is a SUBREG of a hard register,
1801 the SUBREG will be passed. */
1804 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1808 if (GET_CODE (x
) == COND_EXEC
)
1809 x
= COND_EXEC_CODE (x
);
1811 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1813 rtx dest
= SET_DEST (x
);
1815 while ((GET_CODE (dest
) == SUBREG
1816 && (!REG_P (SUBREG_REG (dest
))
1817 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1818 || GET_CODE (dest
) == ZERO_EXTRACT
1819 || GET_CODE (dest
) == STRICT_LOW_PART
)
1820 dest
= XEXP (dest
, 0);
1822 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1823 each of whose first operand is a register. */
1824 if (GET_CODE (dest
) == PARALLEL
)
1826 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1827 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1828 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1831 (*fun
) (dest
, x
, data
);
1834 else if (GET_CODE (x
) == PARALLEL
)
1835 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1836 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1839 /* Like notes_stores, but call FUN for each expression that is being
1840 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1841 FUN for each expression, not any interior subexpressions. FUN receives a
1842 pointer to the expression and the DATA passed to this function.
1844 Note that this is not quite the same test as that done in reg_referenced_p
1845 since that considers something as being referenced if it is being
1846 partially set, while we do not. */
1849 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1854 switch (GET_CODE (body
))
1857 (*fun
) (&COND_EXEC_TEST (body
), data
);
1858 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1862 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1863 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1867 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1868 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1872 (*fun
) (&XEXP (body
, 0), data
);
1876 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1877 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1881 (*fun
) (&TRAP_CONDITION (body
), data
);
1885 (*fun
) (&XEXP (body
, 0), data
);
1889 case UNSPEC_VOLATILE
:
1890 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1891 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1895 if (MEM_P (XEXP (body
, 0)))
1896 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1901 rtx dest
= SET_DEST (body
);
1903 /* For sets we replace everything in source plus registers in memory
1904 expression in store and operands of a ZERO_EXTRACT. */
1905 (*fun
) (&SET_SRC (body
), data
);
1907 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1909 (*fun
) (&XEXP (dest
, 1), data
);
1910 (*fun
) (&XEXP (dest
, 2), data
);
1913 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1914 dest
= XEXP (dest
, 0);
1917 (*fun
) (&XEXP (dest
, 0), data
);
1922 /* All the other possibilities never store. */
1923 (*fun
) (pbody
, data
);
1928 /* Return nonzero if X's old contents don't survive after INSN.
1929 This will be true if X is (cc0) or if X is a register and
1930 X dies in INSN or because INSN entirely sets X.
1932 "Entirely set" means set directly and not through a SUBREG, or
1933 ZERO_EXTRACT, so no trace of the old contents remains.
1934 Likewise, REG_INC does not count.
1936 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1937 but for this use that makes no difference, since regs don't overlap
1938 during their lifetimes. Therefore, this function may be used
1939 at any time after deaths have been computed.
1941 If REG is a hard reg that occupies multiple machine registers, this
1942 function will only return 1 if each of those registers will be replaced
1946 dead_or_set_p (const_rtx insn
, const_rtx x
)
1948 unsigned int regno
, end_regno
;
1951 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1952 if (GET_CODE (x
) == CC0
)
1955 gcc_assert (REG_P (x
));
1958 end_regno
= END_REGNO (x
);
1959 for (i
= regno
; i
< end_regno
; i
++)
1960 if (! dead_or_set_regno_p (insn
, i
))
1966 /* Return TRUE iff DEST is a register or subreg of a register and
1967 doesn't change the number of words of the inner register, and any
1968 part of the register is TEST_REGNO. */
1971 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1973 unsigned int regno
, endregno
;
1975 if (GET_CODE (dest
) == SUBREG
1976 && (((GET_MODE_SIZE (GET_MODE (dest
))
1977 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1978 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1979 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1980 dest
= SUBREG_REG (dest
);
1985 regno
= REGNO (dest
);
1986 endregno
= END_REGNO (dest
);
1987 return (test_regno
>= regno
&& test_regno
< endregno
);
1990 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1991 any member matches the covers_regno_no_parallel_p criteria. */
1994 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1996 if (GET_CODE (dest
) == PARALLEL
)
1998 /* Some targets place small structures in registers for return
1999 values of functions, and those registers are wrapped in
2000 PARALLELs that we may see as the destination of a SET. */
2003 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2005 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2006 if (inner
!= NULL_RTX
2007 && covers_regno_no_parallel_p (inner
, test_regno
))
2014 return covers_regno_no_parallel_p (dest
, test_regno
);
2017 /* Utility function for dead_or_set_p to check an individual register. */
2020 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2024 /* See if there is a death note for something that includes TEST_REGNO. */
2025 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2029 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2032 pattern
= PATTERN (insn
);
2034 /* If a COND_EXEC is not executed, the value survives. */
2035 if (GET_CODE (pattern
) == COND_EXEC
)
2038 if (GET_CODE (pattern
) == SET
)
2039 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2040 else if (GET_CODE (pattern
) == PARALLEL
)
2044 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2046 rtx body
= XVECEXP (pattern
, 0, i
);
2048 if (GET_CODE (body
) == COND_EXEC
)
2049 body
= COND_EXEC_CODE (body
);
2051 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2052 && covers_regno_p (SET_DEST (body
), test_regno
))
2060 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2061 If DATUM is nonzero, look for one whose datum is DATUM. */
2064 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2068 gcc_checking_assert (insn
);
2070 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2071 if (! INSN_P (insn
))
2075 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2076 if (REG_NOTE_KIND (link
) == kind
)
2081 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2082 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2087 /* Return the reg-note of kind KIND in insn INSN which applies to register
2088 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2089 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2090 it might be the case that the note overlaps REGNO. */
2093 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2097 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2098 if (! INSN_P (insn
))
2101 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2102 if (REG_NOTE_KIND (link
) == kind
2103 /* Verify that it is a register, so that scratch and MEM won't cause a
2105 && REG_P (XEXP (link
, 0))
2106 && REGNO (XEXP (link
, 0)) <= regno
2107 && END_REGNO (XEXP (link
, 0)) > regno
)
2112 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2116 find_reg_equal_equiv_note (const_rtx insn
)
2123 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2124 if (REG_NOTE_KIND (link
) == REG_EQUAL
2125 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2127 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2128 insns that have multiple sets. Checking single_set to
2129 make sure of this is not the proper check, as explained
2130 in the comment in set_unique_reg_note.
2132 This should be changed into an assert. */
2133 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2140 /* Check whether INSN is a single_set whose source is known to be
2141 equivalent to a constant. Return that constant if so, otherwise
2145 find_constant_src (const rtx_insn
*insn
)
2149 set
= single_set (insn
);
2152 x
= avoid_constant_pool_reference (SET_SRC (set
));
2157 note
= find_reg_equal_equiv_note (insn
);
2158 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2159 return XEXP (note
, 0);
2164 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2165 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2168 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2170 /* If it's not a CALL_INSN, it can't possibly have a
2171 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2181 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2183 link
= XEXP (link
, 1))
2184 if (GET_CODE (XEXP (link
, 0)) == code
2185 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2190 unsigned int regno
= REGNO (datum
);
2192 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2193 to pseudo registers, so don't bother checking. */
2195 if (regno
< FIRST_PSEUDO_REGISTER
)
2197 unsigned int end_regno
= END_REGNO (datum
);
2200 for (i
= regno
; i
< end_regno
; i
++)
2201 if (find_regno_fusage (insn
, code
, i
))
2209 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2210 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2213 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2217 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2218 to pseudo registers, so don't bother checking. */
2220 if (regno
>= FIRST_PSEUDO_REGISTER
2224 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2228 if (GET_CODE (op
= XEXP (link
, 0)) == code
2229 && REG_P (reg
= XEXP (op
, 0))
2230 && REGNO (reg
) <= regno
2231 && END_REGNO (reg
) > regno
)
2239 /* Return true if KIND is an integer REG_NOTE. */
2242 int_reg_note_p (enum reg_note kind
)
2244 return kind
== REG_BR_PROB
;
2247 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2248 stored as the pointer to the next register note. */
2251 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2255 gcc_checking_assert (!int_reg_note_p (kind
));
2260 case REG_LABEL_TARGET
:
2261 case REG_LABEL_OPERAND
:
2263 /* These types of register notes use an INSN_LIST rather than an
2264 EXPR_LIST, so that copying is done right and dumps look
2266 note
= alloc_INSN_LIST (datum
, list
);
2267 PUT_REG_NOTE_KIND (note
, kind
);
2271 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2278 /* Add register note with kind KIND and datum DATUM to INSN. */
2281 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2283 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2286 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2289 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2291 gcc_checking_assert (int_reg_note_p (kind
));
2292 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2293 datum
, REG_NOTES (insn
));
2296 /* Add a register note like NOTE to INSN. */
2299 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2301 if (GET_CODE (note
) == INT_LIST
)
2302 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2304 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2307 /* Duplicate NOTE and return the copy. */
2309 duplicate_reg_note (rtx note
)
2311 reg_note kind
= REG_NOTE_KIND (note
);
2313 if (GET_CODE (note
) == INT_LIST
)
2314 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2315 else if (GET_CODE (note
) == EXPR_LIST
)
2316 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2318 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2321 /* Remove register note NOTE from the REG_NOTES of INSN. */
2324 remove_note (rtx_insn
*insn
, const_rtx note
)
2328 if (note
== NULL_RTX
)
2331 if (REG_NOTES (insn
) == note
)
2332 REG_NOTES (insn
) = XEXP (note
, 1);
2334 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2335 if (XEXP (link
, 1) == note
)
2337 XEXP (link
, 1) = XEXP (note
, 1);
2341 switch (REG_NOTE_KIND (note
))
2345 df_notes_rescan (insn
);
2352 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2355 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2359 loc
= ®_NOTES (insn
);
2362 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2363 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2364 *loc
= XEXP (*loc
, 1);
2366 loc
= &XEXP (*loc
, 1);
2370 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2373 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2380 /* This loop is a little tricky. We cannot just go down the chain because
2381 it is being modified by some actions in the loop. So we just iterate
2382 over the head. We plan to drain the list anyway. */
2383 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2385 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2386 rtx note
= find_reg_equal_equiv_note (insn
);
2388 /* This assert is generally triggered when someone deletes a REG_EQUAL
2389 or REG_EQUIV note by hacking the list manually rather than calling
2393 remove_note (insn
, note
);
2397 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2398 return 1 if it is found. A simple equality test is used to determine if
2402 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2406 for (x
= listp
; x
; x
= XEXP (x
, 1))
2407 if (node
== XEXP (x
, 0))
2413 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2414 remove that entry from the list if it is found.
2416 A simple equality test is used to determine if NODE matches. */
2419 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2421 rtx_expr_list
*temp
= *listp
;
2422 rtx_expr_list
*prev
= NULL
;
2426 if (node
== temp
->element ())
2428 /* Splice the node out of the list. */
2430 XEXP (prev
, 1) = temp
->next ();
2432 *listp
= temp
->next ();
2438 temp
= temp
->next ();
2442 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2443 remove that entry from the list if it is found.
2445 A simple equality test is used to determine if NODE matches. */
2448 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2450 rtx_insn_list
*temp
= *listp
;
2451 rtx_insn_list
*prev
= NULL
;
2455 if (node
== temp
->insn ())
2457 /* Splice the node out of the list. */
2459 XEXP (prev
, 1) = temp
->next ();
2461 *listp
= temp
->next ();
2467 temp
= temp
->next ();
2471 /* Nonzero if X contains any volatile instructions. These are instructions
2472 which may cause unpredictable machine state instructions, and thus no
2473 instructions or register uses should be moved or combined across them.
2474 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2477 volatile_insn_p (const_rtx x
)
2479 const RTX_CODE code
= GET_CODE (x
);
2497 case UNSPEC_VOLATILE
:
2502 if (MEM_VOLATILE_P (x
))
2509 /* Recursively scan the operands of this expression. */
2512 const char *const fmt
= GET_RTX_FORMAT (code
);
2515 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2519 if (volatile_insn_p (XEXP (x
, i
)))
2522 else if (fmt
[i
] == 'E')
2525 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2526 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2534 /* Nonzero if X contains any volatile memory references
2535 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2538 volatile_refs_p (const_rtx x
)
2540 const RTX_CODE code
= GET_CODE (x
);
2556 case UNSPEC_VOLATILE
:
2562 if (MEM_VOLATILE_P (x
))
2569 /* Recursively scan the operands of this expression. */
2572 const char *const fmt
= GET_RTX_FORMAT (code
);
2575 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2579 if (volatile_refs_p (XEXP (x
, i
)))
2582 else if (fmt
[i
] == 'E')
2585 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2586 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2594 /* Similar to above, except that it also rejects register pre- and post-
2598 side_effects_p (const_rtx x
)
2600 const RTX_CODE code
= GET_CODE (x
);
2617 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2618 when some combination can't be done. If we see one, don't think
2619 that we can simplify the expression. */
2620 return (GET_MODE (x
) != VOIDmode
);
2629 case UNSPEC_VOLATILE
:
2635 if (MEM_VOLATILE_P (x
))
2642 /* Recursively scan the operands of this expression. */
2645 const char *fmt
= GET_RTX_FORMAT (code
);
2648 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2652 if (side_effects_p (XEXP (x
, i
)))
2655 else if (fmt
[i
] == 'E')
2658 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2659 if (side_effects_p (XVECEXP (x
, i
, j
)))
2667 /* Return nonzero if evaluating rtx X might cause a trap.
2668 FLAGS controls how to consider MEMs. A nonzero means the context
2669 of the access may have changed from the original, such that the
2670 address may have become invalid. */
2673 may_trap_p_1 (const_rtx x
, unsigned flags
)
2679 /* We make no distinction currently, but this function is part of
2680 the internal target-hooks ABI so we keep the parameter as
2681 "unsigned flags". */
2682 bool code_changed
= flags
!= 0;
2686 code
= GET_CODE (x
);
2689 /* Handle these cases quickly. */
2701 return targetm
.unspec_may_trap_p (x
, flags
);
2703 case UNSPEC_VOLATILE
:
2709 return MEM_VOLATILE_P (x
);
2711 /* Memory ref can trap unless it's a static var or a stack slot. */
2713 /* Recognize specific pattern of stack checking probes. */
2714 if (flag_stack_check
2715 && MEM_VOLATILE_P (x
)
2716 && XEXP (x
, 0) == stack_pointer_rtx
)
2718 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2719 reference; moving it out of context such as when moving code
2720 when optimizing, might cause its address to become invalid. */
2722 || !MEM_NOTRAP_P (x
))
2724 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2725 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2726 GET_MODE (x
), code_changed
);
2731 /* Division by a non-constant might trap. */
2736 if (HONOR_SNANS (x
))
2738 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2739 return flag_trapping_math
;
2740 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2745 /* An EXPR_LIST is used to represent a function call. This
2746 certainly may trap. */
2755 /* Some floating point comparisons may trap. */
2756 if (!flag_trapping_math
)
2758 /* ??? There is no machine independent way to check for tests that trap
2759 when COMPARE is used, though many targets do make this distinction.
2760 For instance, sparc uses CCFPE for compares which generate exceptions
2761 and CCFP for compares which do not generate exceptions. */
2764 /* But often the compare has some CC mode, so check operand
2766 if (HONOR_NANS (XEXP (x
, 0))
2767 || HONOR_NANS (XEXP (x
, 1)))
2773 if (HONOR_SNANS (x
))
2775 /* Often comparison is CC mode, so check operand modes. */
2776 if (HONOR_SNANS (XEXP (x
, 0))
2777 || HONOR_SNANS (XEXP (x
, 1)))
2782 /* Conversion of floating point might trap. */
2783 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2790 /* These operations don't trap even with floating point. */
2794 /* Any floating arithmetic may trap. */
2795 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2799 fmt
= GET_RTX_FORMAT (code
);
2800 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2804 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2807 else if (fmt
[i
] == 'E')
2810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2811 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2818 /* Return nonzero if evaluating rtx X might cause a trap. */
2821 may_trap_p (const_rtx x
)
2823 return may_trap_p_1 (x
, 0);
2826 /* Same as above, but additionally return nonzero if evaluating rtx X might
2827 cause a fault. We define a fault for the purpose of this function as a
2828 erroneous execution condition that cannot be encountered during the normal
2829 execution of a valid program; the typical example is an unaligned memory
2830 access on a strict alignment machine. The compiler guarantees that it
2831 doesn't generate code that will fault from a valid program, but this
2832 guarantee doesn't mean anything for individual instructions. Consider
2833 the following example:
2835 struct S { int d; union { char *cp; int *ip; }; };
2837 int foo(struct S *s)
2845 on a strict alignment machine. In a valid program, foo will never be
2846 invoked on a structure for which d is equal to 1 and the underlying
2847 unique field of the union not aligned on a 4-byte boundary, but the
2848 expression *s->ip might cause a fault if considered individually.
2850 At the RTL level, potentially problematic expressions will almost always
2851 verify may_trap_p; for example, the above dereference can be emitted as
2852 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2853 However, suppose that foo is inlined in a caller that causes s->cp to
2854 point to a local character variable and guarantees that s->d is not set
2855 to 1; foo may have been effectively translated into pseudo-RTL as:
2858 (set (reg:SI) (mem:SI (%fp - 7)))
2860 (set (reg:QI) (mem:QI (%fp - 7)))
2862 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2863 memory reference to a stack slot, but it will certainly cause a fault
2864 on a strict alignment machine. */
2867 may_trap_or_fault_p (const_rtx x
)
2869 return may_trap_p_1 (x
, 1);
2872 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2873 i.e., an inequality. */
2876 inequality_comparisons_p (const_rtx x
)
2880 const enum rtx_code code
= GET_CODE (x
);
2908 len
= GET_RTX_LENGTH (code
);
2909 fmt
= GET_RTX_FORMAT (code
);
2911 for (i
= 0; i
< len
; i
++)
2915 if (inequality_comparisons_p (XEXP (x
, i
)))
2918 else if (fmt
[i
] == 'E')
2921 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2922 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2930 /* Replace any occurrence of FROM in X with TO. The function does
2931 not enter into CONST_DOUBLE for the replace.
2933 Note that copying is not done so X must not be shared unless all copies
2936 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
2937 those pointer-equal ones. */
2940 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
2948 /* Allow this function to make replacements in EXPR_LISTs. */
2955 && REGNO (x
) == REGNO (from
))
2957 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2960 else if (GET_CODE (x
) == SUBREG
)
2962 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
2964 if (CONST_INT_P (new_rtx
))
2966 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2967 GET_MODE (SUBREG_REG (x
)),
2972 SUBREG_REG (x
) = new_rtx
;
2976 else if (GET_CODE (x
) == ZERO_EXTEND
)
2978 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
2980 if (CONST_INT_P (new_rtx
))
2982 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2983 new_rtx
, GET_MODE (XEXP (x
, 0)));
2987 XEXP (x
, 0) = new_rtx
;
2992 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2993 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2996 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
2997 else if (fmt
[i
] == 'E')
2998 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2999 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3000 from
, to
, all_regs
);
3006 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3007 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3010 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3012 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3014 if (JUMP_TABLE_DATA_P (x
))
3017 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3018 int len
= GET_NUM_ELEM (vec
);
3019 for (int i
= 0; i
< len
; ++i
)
3021 rtx ref
= RTVEC_ELT (vec
, i
);
3022 if (XEXP (ref
, 0) == old_label
)
3024 XEXP (ref
, 0) = new_label
;
3025 if (update_label_nuses
)
3027 ++LABEL_NUSES (new_label
);
3028 --LABEL_NUSES (old_label
);
3035 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3036 field. This is not handled by the iterator because it doesn't
3037 handle unprinted ('0') fields. */
3038 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3039 JUMP_LABEL (x
) = new_label
;
3041 subrtx_ptr_iterator::array_type array
;
3042 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3047 if (GET_CODE (x
) == SYMBOL_REF
3048 && CONSTANT_POOL_ADDRESS_P (x
))
3050 rtx c
= get_pool_constant (x
);
3051 if (rtx_referenced_p (old_label
, c
))
3053 /* Create a copy of constant C; replace the label inside
3054 but do not update LABEL_NUSES because uses in constant pool
3056 rtx new_c
= copy_rtx (c
);
3057 replace_label (&new_c
, old_label
, new_label
, false);
3059 /* Add the new constant NEW_C to constant pool and replace
3060 the old reference to constant by new reference. */
3061 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3062 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3066 if ((GET_CODE (x
) == LABEL_REF
3067 || GET_CODE (x
) == INSN_LIST
)
3068 && XEXP (x
, 0) == old_label
)
3070 XEXP (x
, 0) = new_label
;
3071 if (update_label_nuses
)
3073 ++LABEL_NUSES (new_label
);
3074 --LABEL_NUSES (old_label
);
3082 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3083 bool update_label_nuses
)
3085 rtx insn_as_rtx
= insn
;
3086 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3087 gcc_checking_assert (insn_as_rtx
== insn
);
3090 /* Return true if X is referenced in BODY. */
3093 rtx_referenced_p (const_rtx x
, const_rtx body
)
3095 subrtx_iterator::array_type array
;
3096 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3097 if (const_rtx y
= *iter
)
3099 /* Check if a label_ref Y refers to label X. */
3100 if (GET_CODE (y
) == LABEL_REF
3102 && label_ref_label (y
) == x
)
3105 if (rtx_equal_p (x
, y
))
3108 /* If Y is a reference to pool constant traverse the constant. */
3109 if (GET_CODE (y
) == SYMBOL_REF
3110 && CONSTANT_POOL_ADDRESS_P (y
))
3111 iter
.substitute (get_pool_constant (y
));
3116 /* If INSN is a tablejump return true and store the label (before jump table) to
3117 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3120 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3121 rtx_jump_table_data
**tablep
)
3126 rtx target
= JUMP_LABEL (insn
);
3127 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3130 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3131 rtx_insn
*table
= next_insn (label
);
3132 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3138 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3142 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3143 constant that is not in the constant pool and not in the condition
3144 of an IF_THEN_ELSE. */
3147 computed_jump_p_1 (const_rtx x
)
3149 const enum rtx_code code
= GET_CODE (x
);
3166 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3167 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3170 return (computed_jump_p_1 (XEXP (x
, 1))
3171 || computed_jump_p_1 (XEXP (x
, 2)));
3177 fmt
= GET_RTX_FORMAT (code
);
3178 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3181 && computed_jump_p_1 (XEXP (x
, i
)))
3184 else if (fmt
[i
] == 'E')
3185 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3186 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3193 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3195 Tablejumps and casesi insns are not considered indirect jumps;
3196 we can recognize them by a (use (label_ref)). */
3199 computed_jump_p (const rtx_insn
*insn
)
3204 rtx pat
= PATTERN (insn
);
3206 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3207 if (JUMP_LABEL (insn
) != NULL
)
3210 if (GET_CODE (pat
) == PARALLEL
)
3212 int len
= XVECLEN (pat
, 0);
3213 int has_use_labelref
= 0;
3215 for (i
= len
- 1; i
>= 0; i
--)
3216 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3217 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3220 has_use_labelref
= 1;
3224 if (! has_use_labelref
)
3225 for (i
= len
- 1; i
>= 0; i
--)
3226 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3227 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3228 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3231 else if (GET_CODE (pat
) == SET
3232 && SET_DEST (pat
) == pc_rtx
3233 && computed_jump_p_1 (SET_SRC (pat
)))
3241 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3242 the equivalent add insn and pass the result to FN, using DATA as the
3246 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3248 rtx x
= XEXP (mem
, 0);
3249 switch (GET_CODE (x
))
3254 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3255 rtx r1
= XEXP (x
, 0);
3256 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3257 return fn (mem
, x
, r1
, r1
, c
, data
);
3263 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3264 rtx r1
= XEXP (x
, 0);
3265 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3266 return fn (mem
, x
, r1
, r1
, c
, data
);
3272 rtx r1
= XEXP (x
, 0);
3273 rtx add
= XEXP (x
, 1);
3274 return fn (mem
, x
, r1
, add
, NULL
, data
);
3282 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3283 For each such autoinc operation found, call FN, passing it
3284 the innermost enclosing MEM, the operation itself, the RTX modified
3285 by the operation, two RTXs (the second may be NULL) that, once
3286 added, represent the value to be held by the modified RTX
3287 afterwards, and DATA. FN is to return 0 to continue the
3288 traversal or any other value to have it returned to the caller of
3289 for_each_inc_dec. */
3292 for_each_inc_dec (rtx x
,
3293 for_each_inc_dec_fn fn
,
3296 subrtx_var_iterator::array_type array
;
3297 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3302 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3304 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3307 iter
.skip_subrtxes ();
3314 /* Searches X for any reference to REGNO, returning the rtx of the
3315 reference found if any. Otherwise, returns NULL_RTX. */
3318 regno_use_in (unsigned int regno
, rtx x
)
3324 if (REG_P (x
) && REGNO (x
) == regno
)
3327 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3328 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3332 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3335 else if (fmt
[i
] == 'E')
3336 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3337 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3344 /* Return a value indicating whether OP, an operand of a commutative
3345 operation, is preferred as the first or second operand. The more
3346 positive the value, the stronger the preference for being the first
3350 commutative_operand_precedence (rtx op
)
3352 enum rtx_code code
= GET_CODE (op
);
3354 /* Constants always become the second operand. Prefer "nice" constants. */
3355 if (code
== CONST_INT
)
3357 if (code
== CONST_WIDE_INT
)
3359 if (code
== CONST_DOUBLE
)
3361 if (code
== CONST_FIXED
)
3363 op
= avoid_constant_pool_reference (op
);
3364 code
= GET_CODE (op
);
3366 switch (GET_RTX_CLASS (code
))
3369 if (code
== CONST_INT
)
3371 if (code
== CONST_WIDE_INT
)
3373 if (code
== CONST_DOUBLE
)
3375 if (code
== CONST_FIXED
)
3380 /* SUBREGs of objects should come second. */
3381 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3386 /* Complex expressions should be the first, so decrease priority
3387 of objects. Prefer pointer objects over non pointer objects. */
3388 if ((REG_P (op
) && REG_POINTER (op
))
3389 || (MEM_P (op
) && MEM_POINTER (op
)))
3393 case RTX_COMM_ARITH
:
3394 /* Prefer operands that are themselves commutative to be first.
3395 This helps to make things linear. In particular,
3396 (and (and (reg) (reg)) (not (reg))) is canonical. */
3400 /* If only one operand is a binary expression, it will be the first
3401 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3402 is canonical, although it will usually be further simplified. */
3406 /* Then prefer NEG and NOT. */
3407 if (code
== NEG
|| code
== NOT
)
3416 /* Return 1 iff it is necessary to swap operands of commutative operation
3417 in order to canonicalize expression. */
3420 swap_commutative_operands_p (rtx x
, rtx y
)
3422 return (commutative_operand_precedence (x
)
3423 < commutative_operand_precedence (y
));
3426 /* Return 1 if X is an autoincrement side effect and the register is
3427 not the stack pointer. */
3429 auto_inc_p (const_rtx x
)
3431 switch (GET_CODE (x
))
3439 /* There are no REG_INC notes for SP. */
3440 if (XEXP (x
, 0) != stack_pointer_rtx
)
3448 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3450 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3459 code
= GET_CODE (in
);
3460 fmt
= GET_RTX_FORMAT (code
);
3461 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3465 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3468 else if (fmt
[i
] == 'E')
3469 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3470 if (loc
== &XVECEXP (in
, i
, j
)
3471 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3477 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3478 and SUBREG_BYTE, return the bit offset where the subreg begins
3479 (counting from the least significant bit of the operand). */
3482 subreg_lsb_1 (machine_mode outer_mode
,
3483 machine_mode inner_mode
,
3484 unsigned int subreg_byte
)
3486 unsigned int bitpos
;
3490 /* A paradoxical subreg begins at bit position 0. */
3491 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3494 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3495 /* If the subreg crosses a word boundary ensure that
3496 it also begins and ends on a word boundary. */
3497 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3498 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3499 && (subreg_byte
% UNITS_PER_WORD
3500 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3502 if (WORDS_BIG_ENDIAN
)
3503 word
= (GET_MODE_SIZE (inner_mode
)
3504 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3506 word
= subreg_byte
/ UNITS_PER_WORD
;
3507 bitpos
= word
* BITS_PER_WORD
;
3509 if (BYTES_BIG_ENDIAN
)
3510 byte
= (GET_MODE_SIZE (inner_mode
)
3511 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3513 byte
= subreg_byte
% UNITS_PER_WORD
;
3514 bitpos
+= byte
* BITS_PER_UNIT
;
3519 /* Given a subreg X, return the bit offset where the subreg begins
3520 (counting from the least significant bit of the reg). */
3523 subreg_lsb (const_rtx x
)
3525 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3529 /* Fill in information about a subreg of a hard register.
3530 xregno - A regno of an inner hard subreg_reg (or what will become one).
3531 xmode - The mode of xregno.
3532 offset - The byte offset.
3533 ymode - The mode of a top level SUBREG (or what may become one).
3534 info - Pointer to structure to fill in.
3536 Rather than considering one particular inner register (and thus one
3537 particular "outer" register) in isolation, this function really uses
3538 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3539 function does not check whether adding INFO->offset to XREGNO gives
3540 a valid hard register; even if INFO->offset + XREGNO is out of range,
3541 there might be another register of the same type that is in range.
3542 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3543 register, since that can depend on things like whether the final
3544 register number is even or odd. Callers that want to check whether
3545 this particular subreg can be replaced by a simple (reg ...) should
3546 use simplify_subreg_regno. */
3549 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3550 unsigned int offset
, machine_mode ymode
,
3551 struct subreg_info
*info
)
3553 int nregs_xmode
, nregs_ymode
;
3554 int mode_multiple
, nregs_multiple
;
3555 int offset_adj
, y_offset
, y_offset_adj
;
3556 int regsize_xmode
, regsize_ymode
;
3559 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3563 /* If there are holes in a non-scalar mode in registers, we expect
3564 that it is made up of its units concatenated together. */
3565 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3567 machine_mode xmode_unit
;
3569 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3570 xmode_unit
= GET_MODE_INNER (xmode
);
3571 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3572 gcc_assert (nregs_xmode
3573 == (GET_MODE_NUNITS (xmode
)
3574 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3575 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3576 == (hard_regno_nregs
[xregno
][xmode_unit
]
3577 * GET_MODE_NUNITS (xmode
)));
3579 /* You can only ask for a SUBREG of a value with holes in the middle
3580 if you don't cross the holes. (Such a SUBREG should be done by
3581 picking a different register class, or doing it in memory if
3582 necessary.) An example of a value with holes is XCmode on 32-bit
3583 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3584 3 for each part, but in memory it's two 128-bit parts.
3585 Padding is assumed to be at the end (not necessarily the 'high part')
3587 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3588 < GET_MODE_NUNITS (xmode
))
3589 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3590 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3591 / GET_MODE_SIZE (xmode_unit
))))
3593 info
->representable_p
= false;
3598 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3600 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3602 /* Paradoxical subregs are otherwise valid. */
3605 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3607 info
->representable_p
= true;
3608 /* If this is a big endian paradoxical subreg, which uses more
3609 actual hard registers than the original register, we must
3610 return a negative offset so that we find the proper highpart
3612 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3613 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3614 info
->offset
= nregs_xmode
- nregs_ymode
;
3617 info
->nregs
= nregs_ymode
;
3621 /* If registers store different numbers of bits in the different
3622 modes, we cannot generally form this subreg. */
3623 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3624 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3625 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3626 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3628 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3629 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3630 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3632 info
->representable_p
= false;
3634 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3635 info
->offset
= offset
/ regsize_xmode
;
3638 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3640 info
->representable_p
= false;
3642 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3643 info
->offset
= offset
/ regsize_xmode
;
3646 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3647 would go outside of XMODE. */
3649 && GET_MODE_SIZE (ymode
) + offset
> GET_MODE_SIZE (xmode
))
3651 info
->representable_p
= false;
3652 info
->nregs
= nregs_ymode
;
3653 info
->offset
= offset
/ regsize_xmode
;
3656 /* Quick exit for the simple and common case of extracting whole
3657 subregisters from a multiregister value. */
3658 /* ??? It would be better to integrate this into the code below,
3659 if we can generalize the concept enough and figure out how
3660 odd-sized modes can coexist with the other weird cases we support. */
3662 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3663 && regsize_xmode
== regsize_ymode
3664 && (offset
% regsize_ymode
) == 0)
3666 info
->representable_p
= true;
3667 info
->nregs
= nregs_ymode
;
3668 info
->offset
= offset
/ regsize_ymode
;
3669 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3674 /* Lowpart subregs are otherwise valid. */
3675 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3677 info
->representable_p
= true;
3680 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3683 info
->nregs
= nregs_ymode
;
3688 /* This should always pass, otherwise we don't know how to verify
3689 the constraint. These conditions may be relaxed but
3690 subreg_regno_offset would need to be redesigned. */
3691 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3692 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3694 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3695 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3697 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3698 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3699 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3700 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3701 offset
= (xsize
- ysize
- off_high
) | off_low
;
3703 /* The XMODE value can be seen as a vector of NREGS_XMODE
3704 values. The subreg must represent a lowpart of given field.
3705 Compute what field it is. */
3706 offset_adj
= offset
;
3707 offset_adj
-= subreg_lowpart_offset (ymode
,
3708 mode_for_size (GET_MODE_BITSIZE (xmode
)
3712 /* Size of ymode must not be greater than the size of xmode. */
3713 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3714 gcc_assert (mode_multiple
!= 0);
3716 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3717 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3718 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3720 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3721 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3725 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3728 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3729 info
->nregs
= nregs_ymode
;
3732 /* This function returns the regno offset of a subreg expression.
3733 xregno - A regno of an inner hard subreg_reg (or what will become one).
3734 xmode - The mode of xregno.
3735 offset - The byte offset.
3736 ymode - The mode of a top level SUBREG (or what may become one).
3737 RETURN - The regno offset which would be used. */
3739 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3740 unsigned int offset
, machine_mode ymode
)
3742 struct subreg_info info
;
3743 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3747 /* This function returns true when the offset is representable via
3748 subreg_offset in the given regno.
3749 xregno - A regno of an inner hard subreg_reg (or what will become one).
3750 xmode - The mode of xregno.
3751 offset - The byte offset.
3752 ymode - The mode of a top level SUBREG (or what may become one).
3753 RETURN - Whether the offset is representable. */
3755 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3756 unsigned int offset
, machine_mode ymode
)
3758 struct subreg_info info
;
3759 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3760 return info
.representable_p
;
3763 /* Return the number of a YMODE register to which
3765 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3767 can be simplified. Return -1 if the subreg can't be simplified.
3769 XREGNO is a hard register number. */
3772 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3773 unsigned int offset
, machine_mode ymode
)
3775 struct subreg_info info
;
3776 unsigned int yregno
;
3778 #ifdef CANNOT_CHANGE_MODE_CLASS
3779 /* Give the backend a chance to disallow the mode change. */
3780 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3781 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3782 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3783 /* We can use mode change in LRA for some transformations. */
3784 && ! lra_in_progress
)
3788 /* We shouldn't simplify stack-related registers. */
3789 if ((!reload_completed
|| frame_pointer_needed
)
3790 && xregno
== FRAME_POINTER_REGNUM
)
3793 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3794 && xregno
== ARG_POINTER_REGNUM
)
3797 if (xregno
== STACK_POINTER_REGNUM
3798 /* We should convert hard stack register in LRA if it is
3800 && ! lra_in_progress
)
3803 /* Try to get the register offset. */
3804 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3805 if (!info
.representable_p
)
3808 /* Make sure that the offsetted register value is in range. */
3809 yregno
= xregno
+ info
.offset
;
3810 if (!HARD_REGISTER_NUM_P (yregno
))
3813 /* See whether (reg:YMODE YREGNO) is valid.
3815 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3816 This is a kludge to work around how complex FP arguments are passed
3817 on IA-64 and should be fixed. See PR target/49226. */
3818 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3819 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3822 return (int) yregno
;
3825 /* Return the final regno that a subreg expression refers to. */
3827 subreg_regno (const_rtx x
)
3830 rtx subreg
= SUBREG_REG (x
);
3831 int regno
= REGNO (subreg
);
3833 ret
= regno
+ subreg_regno_offset (regno
,
3841 /* Return the number of registers that a subreg expression refers
3844 subreg_nregs (const_rtx x
)
3846 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3849 /* Return the number of registers that a subreg REG with REGNO
3850 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3851 changed so that the regno can be passed in. */
3854 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3856 struct subreg_info info
;
3857 rtx subreg
= SUBREG_REG (x
);
3859 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3865 struct parms_set_data
3871 /* Helper function for noticing stores to parameter registers. */
3873 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3875 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3876 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3877 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3879 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3884 /* Look backward for first parameter to be loaded.
3885 Note that loads of all parameters will not necessarily be
3886 found if CSE has eliminated some of them (e.g., an argument
3887 to the outer function is passed down as a parameter).
3888 Do not skip BOUNDARY. */
3890 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3892 struct parms_set_data parm
;
3894 rtx_insn
*before
, *first_set
;
3896 /* Since different machines initialize their parameter registers
3897 in different orders, assume nothing. Collect the set of all
3898 parameter registers. */
3899 CLEAR_HARD_REG_SET (parm
.regs
);
3901 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3902 if (GET_CODE (XEXP (p
, 0)) == USE
3903 && REG_P (XEXP (XEXP (p
, 0), 0))
3904 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
3906 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3908 /* We only care about registers which can hold function
3910 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3913 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3917 first_set
= call_insn
;
3919 /* Search backward for the first set of a register in this set. */
3920 while (parm
.nregs
&& before
!= boundary
)
3922 before
= PREV_INSN (before
);
3924 /* It is possible that some loads got CSEed from one call to
3925 another. Stop in that case. */
3926 if (CALL_P (before
))
3929 /* Our caller needs either ensure that we will find all sets
3930 (in case code has not been optimized yet), or take care
3931 for possible labels in a way by setting boundary to preceding
3933 if (LABEL_P (before
))
3935 gcc_assert (before
== boundary
);
3939 if (INSN_P (before
))
3941 int nregs_old
= parm
.nregs
;
3942 note_stores (PATTERN (before
), parms_set
, &parm
);
3943 /* If we found something that did not set a parameter reg,
3944 we're done. Do not keep going, as that might result
3945 in hoisting an insn before the setting of a pseudo
3946 that is used by the hoisted insn. */
3947 if (nregs_old
!= parm
.nregs
)
3956 /* Return true if we should avoid inserting code between INSN and preceding
3957 call instruction. */
3960 keep_with_call_p (const rtx_insn
*insn
)
3964 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3966 if (REG_P (SET_DEST (set
))
3967 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3968 && fixed_regs
[REGNO (SET_DEST (set
))]
3969 && general_operand (SET_SRC (set
), VOIDmode
))
3971 if (REG_P (SET_SRC (set
))
3972 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3973 && REG_P (SET_DEST (set
))
3974 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3976 /* There may be a stack pop just after the call and before the store
3977 of the return register. Search for the actual store when deciding
3978 if we can break or not. */
3979 if (SET_DEST (set
) == stack_pointer_rtx
)
3981 /* This CONST_CAST is okay because next_nonnote_insn just
3982 returns its argument and we assign it to a const_rtx
3985 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3986 if (i2
&& keep_with_call_p (i2
))
3993 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3994 to non-complex jumps. That is, direct unconditional, conditional,
3995 and tablejumps, but not computed jumps or returns. It also does
3996 not apply to the fallthru case of a conditional jump. */
3999 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4001 rtx tmp
= JUMP_LABEL (jump_insn
);
4002 rtx_jump_table_data
*table
;
4007 if (tablejump_p (jump_insn
, NULL
, &table
))
4009 rtvec vec
= table
->get_labels ();
4010 int i
, veclen
= GET_NUM_ELEM (vec
);
4012 for (i
= 0; i
< veclen
; ++i
)
4013 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4017 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4024 /* Return an estimate of the cost of computing rtx X.
4025 One use is in cse, to decide which expression to keep in the hash table.
4026 Another is in rtl generation, to pick the cheapest way to multiply.
4027 Other uses like the latter are expected in the future.
4029 X appears as operand OPNO in an expression with code OUTER_CODE.
4030 SPEED specifies whether costs optimized for speed or size should
4034 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4035 int opno
, bool speed
)
4046 if (GET_MODE (x
) != VOIDmode
)
4047 mode
= GET_MODE (x
);
4049 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4050 many insns, taking N times as long. */
4051 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4055 /* Compute the default costs of certain things.
4056 Note that targetm.rtx_costs can override the defaults. */
4058 code
= GET_CODE (x
);
4062 /* Multiplication has time-complexity O(N*N), where N is the
4063 number of units (translated from digits) when using
4064 schoolbook long multiplication. */
4065 total
= factor
* factor
* COSTS_N_INSNS (5);
4071 /* Similarly, complexity for schoolbook long division. */
4072 total
= factor
* factor
* COSTS_N_INSNS (7);
4075 /* Used in combine.c as a marker. */
4079 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4080 the mode for the factor. */
4081 mode
= GET_MODE (SET_DEST (x
));
4082 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4087 total
= factor
* COSTS_N_INSNS (1);
4097 /* If we can't tie these modes, make this expensive. The larger
4098 the mode, the more expensive it is. */
4099 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4100 return COSTS_N_INSNS (2 + factor
);
4104 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4109 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4110 which is already in total. */
4112 fmt
= GET_RTX_FORMAT (code
);
4113 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4115 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4116 else if (fmt
[i
] == 'E')
4117 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4118 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4123 /* Fill in the structure C with information about both speed and size rtx
4124 costs for X, which is operand OPNO in an expression with code OUTER. */
4127 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4128 struct full_rtx_costs
*c
)
4130 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4131 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4135 /* Return cost of address expression X.
4136 Expect that X is properly formed address reference.
4138 SPEED parameter specify whether costs optimized for speed or size should
4142 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4144 /* We may be asked for cost of various unusual addresses, such as operands
4145 of push instruction. It is not worthwhile to complicate writing
4146 of the target hook by such cases. */
4148 if (!memory_address_addr_space_p (mode
, x
, as
))
4151 return targetm
.address_cost (x
, mode
, as
, speed
);
4154 /* If the target doesn't override, compute the cost as with arithmetic. */
4157 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4159 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4163 unsigned HOST_WIDE_INT
4164 nonzero_bits (const_rtx x
, machine_mode mode
)
4166 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4170 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4172 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4175 /* Return true if nonzero_bits1 might recurse into both operands
4179 nonzero_bits_binary_arith_p (const_rtx x
)
4181 if (!ARITHMETIC_P (x
))
4183 switch (GET_CODE (x
))
4205 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4206 It avoids exponential behavior in nonzero_bits1 when X has
4207 identical subexpressions on the first or the second level. */
4209 static unsigned HOST_WIDE_INT
4210 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4211 machine_mode known_mode
,
4212 unsigned HOST_WIDE_INT known_ret
)
4214 if (x
== known_x
&& mode
== known_mode
)
4217 /* Try to find identical subexpressions. If found call
4218 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4219 precomputed value for the subexpression as KNOWN_RET. */
4221 if (nonzero_bits_binary_arith_p (x
))
4223 rtx x0
= XEXP (x
, 0);
4224 rtx x1
= XEXP (x
, 1);
4226 /* Check the first level. */
4228 return nonzero_bits1 (x
, mode
, x0
, mode
,
4229 cached_nonzero_bits (x0
, mode
, known_x
,
4230 known_mode
, known_ret
));
4232 /* Check the second level. */
4233 if (nonzero_bits_binary_arith_p (x0
)
4234 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4235 return nonzero_bits1 (x
, mode
, x1
, mode
,
4236 cached_nonzero_bits (x1
, mode
, known_x
,
4237 known_mode
, known_ret
));
4239 if (nonzero_bits_binary_arith_p (x1
)
4240 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4241 return nonzero_bits1 (x
, mode
, x0
, mode
,
4242 cached_nonzero_bits (x0
, mode
, known_x
,
4243 known_mode
, known_ret
));
4246 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4249 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4250 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4251 is less useful. We can't allow both, because that results in exponential
4252 run time recursion. There is a nullstone testcase that triggered
4253 this. This macro avoids accidental uses of num_sign_bit_copies. */
4254 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4256 /* Given an expression, X, compute which bits in X can be nonzero.
4257 We don't care about bits outside of those defined in MODE.
4259 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4260 an arithmetic operation, we can do better. */
4262 static unsigned HOST_WIDE_INT
4263 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4264 machine_mode known_mode
,
4265 unsigned HOST_WIDE_INT known_ret
)
4267 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4268 unsigned HOST_WIDE_INT inner_nz
;
4270 machine_mode inner_mode
;
4271 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4273 /* For floating-point and vector values, assume all bits are needed. */
4274 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4275 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4278 /* If X is wider than MODE, use its mode instead. */
4279 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4281 mode
= GET_MODE (x
);
4282 nonzero
= GET_MODE_MASK (mode
);
4283 mode_width
= GET_MODE_PRECISION (mode
);
4286 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4287 /* Our only callers in this case look for single bit values. So
4288 just return the mode mask. Those tests will then be false. */
4291 /* If MODE is wider than X, but both are a single word for both the host
4292 and target machines, we can compute this from which bits of the
4293 object might be nonzero in its own mode, taking into account the fact
4294 that on many CISC machines, accessing an object in a wider mode
4295 causes the high-order bits to become undefined. So they are
4296 not known to be zero. */
4298 if (!WORD_REGISTER_OPERATIONS
4299 && GET_MODE (x
) != VOIDmode
4300 && GET_MODE (x
) != mode
4301 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4302 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4303 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4305 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4306 known_x
, known_mode
, known_ret
);
4307 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4311 /* Please keep nonzero_bits_binary_arith_p above in sync with
4312 the code in the switch below. */
4313 code
= GET_CODE (x
);
4317 #if defined(POINTERS_EXTEND_UNSIGNED)
4318 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4319 all the bits above ptr_mode are known to be zero. */
4320 /* As we do not know which address space the pointer is referring to,
4321 we can do this only if the target does not support different pointer
4322 or address modes depending on the address space. */
4323 if (target_default_pointer_address_modes_p ()
4324 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4326 && !targetm
.have_ptr_extend ())
4327 nonzero
&= GET_MODE_MASK (ptr_mode
);
4330 /* Include declared information about alignment of pointers. */
4331 /* ??? We don't properly preserve REG_POINTER changes across
4332 pointer-to-integer casts, so we can't trust it except for
4333 things that we know must be pointers. See execute/960116-1.c. */
4334 if ((x
== stack_pointer_rtx
4335 || x
== frame_pointer_rtx
4336 || x
== arg_pointer_rtx
)
4337 && REGNO_POINTER_ALIGN (REGNO (x
)))
4339 unsigned HOST_WIDE_INT alignment
4340 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4342 #ifdef PUSH_ROUNDING
4343 /* If PUSH_ROUNDING is defined, it is possible for the
4344 stack to be momentarily aligned only to that amount,
4345 so we pick the least alignment. */
4346 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4347 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4351 nonzero
&= ~(alignment
- 1);
4355 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4356 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4357 known_mode
, known_ret
,
4361 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4362 known_mode
, known_ret
);
4364 return nonzero_for_hook
;
4368 /* If X is negative in MODE, sign-extend the value. */
4369 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4370 && mode_width
< BITS_PER_WORD
4371 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
4373 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4378 /* In many, if not most, RISC machines, reading a byte from memory
4379 zeros the rest of the register. Noticing that fact saves a lot
4380 of extra zero-extends. */
4381 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4382 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4386 case UNEQ
: case LTGT
:
4387 case GT
: case GTU
: case UNGT
:
4388 case LT
: case LTU
: case UNLT
:
4389 case GE
: case GEU
: case UNGE
:
4390 case LE
: case LEU
: case UNLE
:
4391 case UNORDERED
: case ORDERED
:
4392 /* If this produces an integer result, we know which bits are set.
4393 Code here used to clear bits outside the mode of X, but that is
4395 /* Mind that MODE is the mode the caller wants to look at this
4396 operation in, and not the actual operation mode. We can wind
4397 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4398 that describes the results of a vector compare. */
4399 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4400 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4401 nonzero
= STORE_FLAG_VALUE
;
4406 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4407 and num_sign_bit_copies. */
4408 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4409 == GET_MODE_PRECISION (GET_MODE (x
)))
4413 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4414 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4419 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4420 and num_sign_bit_copies. */
4421 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4422 == GET_MODE_PRECISION (GET_MODE (x
)))
4428 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4429 known_x
, known_mode
, known_ret
)
4430 & GET_MODE_MASK (mode
));
4434 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4435 known_x
, known_mode
, known_ret
);
4436 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4437 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4441 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4442 Otherwise, show all the bits in the outer mode but not the inner
4444 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4445 known_x
, known_mode
, known_ret
);
4446 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4448 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4449 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4450 inner_nz
|= (GET_MODE_MASK (mode
)
4451 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4454 nonzero
&= inner_nz
;
4458 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4459 known_x
, known_mode
, known_ret
)
4460 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4461 known_x
, known_mode
, known_ret
);
4465 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4467 unsigned HOST_WIDE_INT nonzero0
4468 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4469 known_x
, known_mode
, known_ret
);
4471 /* Don't call nonzero_bits for the second time if it cannot change
4473 if ((nonzero
& nonzero0
) != nonzero
)
4475 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4476 known_x
, known_mode
, known_ret
);
4480 case PLUS
: case MINUS
:
4482 case DIV
: case UDIV
:
4483 case MOD
: case UMOD
:
4484 /* We can apply the rules of arithmetic to compute the number of
4485 high- and low-order zero bits of these operations. We start by
4486 computing the width (position of the highest-order nonzero bit)
4487 and the number of low-order zero bits for each value. */
4489 unsigned HOST_WIDE_INT nz0
4490 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4491 known_x
, known_mode
, known_ret
);
4492 unsigned HOST_WIDE_INT nz1
4493 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4494 known_x
, known_mode
, known_ret
);
4495 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4496 int width0
= floor_log2 (nz0
) + 1;
4497 int width1
= floor_log2 (nz1
) + 1;
4498 int low0
= ctz_or_zero (nz0
);
4499 int low1
= ctz_or_zero (nz1
);
4500 unsigned HOST_WIDE_INT op0_maybe_minusp
4501 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4502 unsigned HOST_WIDE_INT op1_maybe_minusp
4503 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4504 unsigned int result_width
= mode_width
;
4510 result_width
= MAX (width0
, width1
) + 1;
4511 result_low
= MIN (low0
, low1
);
4514 result_low
= MIN (low0
, low1
);
4517 result_width
= width0
+ width1
;
4518 result_low
= low0
+ low1
;
4523 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4524 result_width
= width0
;
4529 result_width
= width0
;
4534 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4535 result_width
= MIN (width0
, width1
);
4536 result_low
= MIN (low0
, low1
);
4541 result_width
= MIN (width0
, width1
);
4542 result_low
= MIN (low0
, low1
);
4548 if (result_width
< mode_width
)
4549 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4552 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4557 if (CONST_INT_P (XEXP (x
, 1))
4558 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4559 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4563 /* If this is a SUBREG formed for a promoted variable that has
4564 been zero-extended, we know that at least the high-order bits
4565 are zero, though others might be too. */
4567 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4568 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4569 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4570 known_x
, known_mode
, known_ret
);
4572 inner_mode
= GET_MODE (SUBREG_REG (x
));
4573 /* If the inner mode is a single word for both the host and target
4574 machines, we can compute this from which bits of the inner
4575 object might be nonzero. */
4576 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4577 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4579 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4580 known_x
, known_mode
, known_ret
);
4582 /* On many CISC machines, accessing an object in a wider mode
4583 causes the high-order bits to become undefined. So they are
4584 not known to be zero. */
4585 if (!WORD_REGISTER_OPERATIONS
4586 /* If this is a typical RISC machine, we only have to worry
4587 about the way loads are extended. */
4588 || ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4589 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4590 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4591 || !MEM_P (SUBREG_REG (x
))))
4593 if (GET_MODE_PRECISION (GET_MODE (x
))
4594 > GET_MODE_PRECISION (inner_mode
))
4595 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4596 & ~GET_MODE_MASK (inner_mode
));
4605 /* The nonzero bits are in two classes: any bits within MODE
4606 that aren't in GET_MODE (x) are always significant. The rest of the
4607 nonzero bits are those that are significant in the operand of
4608 the shift when shifted the appropriate number of bits. This
4609 shows that high-order bits are cleared by the right shift and
4610 low-order bits by left shifts. */
4611 if (CONST_INT_P (XEXP (x
, 1))
4612 && INTVAL (XEXP (x
, 1)) >= 0
4613 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4614 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4616 machine_mode inner_mode
= GET_MODE (x
);
4617 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4618 int count
= INTVAL (XEXP (x
, 1));
4619 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4620 unsigned HOST_WIDE_INT op_nonzero
4621 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4622 known_x
, known_mode
, known_ret
);
4623 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4624 unsigned HOST_WIDE_INT outer
= 0;
4626 if (mode_width
> width
)
4627 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4629 if (code
== LSHIFTRT
)
4631 else if (code
== ASHIFTRT
)
4635 /* If the sign bit may have been nonzero before the shift, we
4636 need to mark all the places it could have been copied to
4637 by the shift as possibly nonzero. */
4638 if (inner
& (HOST_WIDE_INT_1U
<< (width
- 1 - count
)))
4639 inner
|= ((HOST_WIDE_INT_1U
<< count
) - 1)
4642 else if (code
== ASHIFT
)
4645 inner
= ((inner
<< (count
% width
)
4646 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4648 nonzero
&= (outer
| inner
);
4654 /* This is at most the number of bits in the mode. */
4655 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4659 /* If CLZ has a known value at zero, then the nonzero bits are
4660 that value, plus the number of bits in the mode minus one. */
4661 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4663 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4669 /* If CTZ has a known value at zero, then the nonzero bits are
4670 that value, plus the number of bits in the mode minus one. */
4671 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4673 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4679 /* This is at most the number of bits in the mode minus 1. */
4680 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4689 unsigned HOST_WIDE_INT nonzero_true
4690 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4691 known_x
, known_mode
, known_ret
);
4693 /* Don't call nonzero_bits for the second time if it cannot change
4695 if ((nonzero
& nonzero_true
) != nonzero
)
4696 nonzero
&= nonzero_true
4697 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4698 known_x
, known_mode
, known_ret
);
4709 /* See the macro definition above. */
4710 #undef cached_num_sign_bit_copies
4713 /* Return true if num_sign_bit_copies1 might recurse into both operands
4717 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4719 if (!ARITHMETIC_P (x
))
4721 switch (GET_CODE (x
))
4739 /* The function cached_num_sign_bit_copies is a wrapper around
4740 num_sign_bit_copies1. It avoids exponential behavior in
4741 num_sign_bit_copies1 when X has identical subexpressions on the
4742 first or the second level. */
4745 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4746 machine_mode known_mode
,
4747 unsigned int known_ret
)
4749 if (x
== known_x
&& mode
== known_mode
)
4752 /* Try to find identical subexpressions. If found call
4753 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4754 the precomputed value for the subexpression as KNOWN_RET. */
4756 if (num_sign_bit_copies_binary_arith_p (x
))
4758 rtx x0
= XEXP (x
, 0);
4759 rtx x1
= XEXP (x
, 1);
4761 /* Check the first level. */
4764 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4765 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4769 /* Check the second level. */
4770 if (num_sign_bit_copies_binary_arith_p (x0
)
4771 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4773 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4774 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4778 if (num_sign_bit_copies_binary_arith_p (x1
)
4779 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4781 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4782 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4787 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4790 /* Return the number of bits at the high-order end of X that are known to
4791 be equal to the sign bit. X will be used in mode MODE; if MODE is
4792 VOIDmode, X will be used in its own mode. The returned value will always
4793 be between 1 and the number of bits in MODE. */
4796 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4797 machine_mode known_mode
,
4798 unsigned int known_ret
)
4800 enum rtx_code code
= GET_CODE (x
);
4801 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4802 int num0
, num1
, result
;
4803 unsigned HOST_WIDE_INT nonzero
;
4805 /* If we weren't given a mode, use the mode of X. If the mode is still
4806 VOIDmode, we don't know anything. Likewise if one of the modes is
4809 if (mode
== VOIDmode
)
4810 mode
= GET_MODE (x
);
4812 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4813 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4816 /* For a smaller object, just ignore the high bits. */
4817 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4819 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4820 known_x
, known_mode
, known_ret
);
4822 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4825 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4827 /* If this machine does not do all register operations on the entire
4828 register and MODE is wider than the mode of X, we can say nothing
4829 at all about the high-order bits. */
4830 if (!WORD_REGISTER_OPERATIONS
)
4833 /* Likewise on machines that do, if the mode of the object is smaller
4834 than a word and loads of that size don't sign extend, we can say
4835 nothing about the high order bits. */
4836 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4837 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
)
4841 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4842 the code in the switch below. */
4847 #if defined(POINTERS_EXTEND_UNSIGNED)
4848 /* If pointers extend signed and this is a pointer in Pmode, say that
4849 all the bits above ptr_mode are known to be sign bit copies. */
4850 /* As we do not know which address space the pointer is referring to,
4851 we can do this only if the target does not support different pointer
4852 or address modes depending on the address space. */
4853 if (target_default_pointer_address_modes_p ()
4854 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4855 && mode
== Pmode
&& REG_POINTER (x
)
4856 && !targetm
.have_ptr_extend ())
4857 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4861 unsigned int copies_for_hook
= 1, copies
= 1;
4862 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4863 known_mode
, known_ret
,
4867 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4868 known_mode
, known_ret
);
4870 if (copies
> 1 || copies_for_hook
> 1)
4871 return MAX (copies
, copies_for_hook
);
4873 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4878 /* Some RISC machines sign-extend all loads of smaller than a word. */
4879 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4880 return MAX (1, ((int) bitwidth
4881 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4885 /* If the constant is negative, take its 1's complement and remask.
4886 Then see how many zero bits we have. */
4887 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4888 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4889 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
4890 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4892 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4895 /* If this is a SUBREG for a promoted object that is sign-extended
4896 and we are looking at it in a wider mode, we know that at least the
4897 high-order bits are known to be sign bit copies. */
4899 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4901 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4902 known_x
, known_mode
, known_ret
);
4903 return MAX ((int) bitwidth
4904 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4908 /* For a smaller object, just ignore the high bits. */
4909 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4911 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4912 known_x
, known_mode
, known_ret
);
4913 return MAX (1, (num0
4914 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4918 /* For paradoxical SUBREGs on machines where all register operations
4919 affect the entire register, just look inside. Note that we are
4920 passing MODE to the recursive call, so the number of sign bit copies
4921 will remain relative to that mode, not the inner mode. */
4923 /* This works only if loads sign extend. Otherwise, if we get a
4924 reload for the inner part, it may be loaded from the stack, and
4925 then we lose all sign bit copies that existed before the store
4928 if (WORD_REGISTER_OPERATIONS
4929 && paradoxical_subreg_p (x
)
4930 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4931 && MEM_P (SUBREG_REG (x
)))
4932 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4933 known_x
, known_mode
, known_ret
);
4937 if (CONST_INT_P (XEXP (x
, 1)))
4938 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4942 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4943 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4944 known_x
, known_mode
, known_ret
));
4947 /* For a smaller object, just ignore the high bits. */
4948 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4949 known_x
, known_mode
, known_ret
);
4950 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4954 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4955 known_x
, known_mode
, known_ret
);
4957 case ROTATE
: case ROTATERT
:
4958 /* If we are rotating left by a number of bits less than the number
4959 of sign bit copies, we can just subtract that amount from the
4961 if (CONST_INT_P (XEXP (x
, 1))
4962 && INTVAL (XEXP (x
, 1)) >= 0
4963 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4965 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4966 known_x
, known_mode
, known_ret
);
4967 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4968 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4973 /* In general, this subtracts one sign bit copy. But if the value
4974 is known to be positive, the number of sign bit copies is the
4975 same as that of the input. Finally, if the input has just one bit
4976 that might be nonzero, all the bits are copies of the sign bit. */
4977 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4978 known_x
, known_mode
, known_ret
);
4979 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4980 return num0
> 1 ? num0
- 1 : 1;
4982 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4987 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
4992 case IOR
: case AND
: case XOR
:
4993 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
4994 /* Logical operations will preserve the number of sign-bit copies.
4995 MIN and MAX operations always return one of the operands. */
4996 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4997 known_x
, known_mode
, known_ret
);
4998 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4999 known_x
, known_mode
, known_ret
);
5001 /* If num1 is clearing some of the top bits then regardless of
5002 the other term, we are guaranteed to have at least that many
5003 high-order zero bits. */
5006 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5007 && CONST_INT_P (XEXP (x
, 1))
5008 && (UINTVAL (XEXP (x
, 1))
5009 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5012 /* Similarly for IOR when setting high-order bits. */
5015 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5016 && CONST_INT_P (XEXP (x
, 1))
5017 && (UINTVAL (XEXP (x
, 1))
5018 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5021 return MIN (num0
, num1
);
5023 case PLUS
: case MINUS
:
5024 /* For addition and subtraction, we can have a 1-bit carry. However,
5025 if we are subtracting 1 from a positive number, there will not
5026 be such a carry. Furthermore, if the positive number is known to
5027 be 0 or 1, we know the result is either -1 or 0. */
5029 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5030 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5032 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5033 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5034 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5035 : bitwidth
- floor_log2 (nonzero
) - 1);
5038 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5039 known_x
, known_mode
, known_ret
);
5040 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5041 known_x
, known_mode
, known_ret
);
5042 result
= MAX (1, MIN (num0
, num1
) - 1);
5047 /* The number of bits of the product is the sum of the number of
5048 bits of both terms. However, unless one of the terms if known
5049 to be positive, we must allow for an additional bit since negating
5050 a negative number can remove one sign bit copy. */
5052 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5053 known_x
, known_mode
, known_ret
);
5054 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5055 known_x
, known_mode
, known_ret
);
5057 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5059 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5060 || (((nonzero_bits (XEXP (x
, 0), mode
)
5061 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5062 && ((nonzero_bits (XEXP (x
, 1), mode
)
5063 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5067 return MAX (1, result
);
5070 /* The result must be <= the first operand. If the first operand
5071 has the high bit set, we know nothing about the number of sign
5073 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5075 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5076 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5079 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5080 known_x
, known_mode
, known_ret
);
5083 /* The result must be <= the second operand. If the second operand
5084 has (or just might have) the high bit set, we know nothing about
5085 the number of sign bit copies. */
5086 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5088 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5089 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5092 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5093 known_x
, known_mode
, known_ret
);
5096 /* Similar to unsigned division, except that we have to worry about
5097 the case where the divisor is negative, in which case we have
5099 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5100 known_x
, known_mode
, known_ret
);
5102 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5103 || (nonzero_bits (XEXP (x
, 1), mode
)
5104 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5110 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5111 known_x
, known_mode
, known_ret
);
5113 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5114 || (nonzero_bits (XEXP (x
, 1), mode
)
5115 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5121 /* Shifts by a constant add to the number of bits equal to the
5123 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5124 known_x
, known_mode
, known_ret
);
5125 if (CONST_INT_P (XEXP (x
, 1))
5126 && INTVAL (XEXP (x
, 1)) > 0
5127 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5128 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5133 /* Left shifts destroy copies. */
5134 if (!CONST_INT_P (XEXP (x
, 1))
5135 || INTVAL (XEXP (x
, 1)) < 0
5136 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5137 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5140 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5141 known_x
, known_mode
, known_ret
);
5142 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5145 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5146 known_x
, known_mode
, known_ret
);
5147 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5148 known_x
, known_mode
, known_ret
);
5149 return MIN (num0
, num1
);
5151 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5152 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5153 case GEU
: case GTU
: case LEU
: case LTU
:
5154 case UNORDERED
: case ORDERED
:
5155 /* If the constant is negative, take its 1's complement and remask.
5156 Then see how many zero bits we have. */
5157 nonzero
= STORE_FLAG_VALUE
;
5158 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5159 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5160 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5162 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5168 /* If we haven't been able to figure it out by one of the above rules,
5169 see if some of the high-order bits are known to be zero. If so,
5170 count those bits and return one less than that amount. If we can't
5171 safely compute the mask for this mode, always return BITWIDTH. */
5173 bitwidth
= GET_MODE_PRECISION (mode
);
5174 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5177 nonzero
= nonzero_bits (x
, mode
);
5178 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5179 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5182 /* Calculate the rtx_cost of a single instruction. A return value of
5183 zero indicates an instruction pattern without a known cost. */
5186 insn_rtx_cost (rtx pat
, bool speed
)
5191 /* Extract the single set rtx from the instruction pattern.
5192 We can't use single_set since we only have the pattern. */
5193 if (GET_CODE (pat
) == SET
)
5195 else if (GET_CODE (pat
) == PARALLEL
)
5198 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5200 rtx x
= XVECEXP (pat
, 0, i
);
5201 if (GET_CODE (x
) == SET
)
5214 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5215 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5218 /* Returns estimate on cost of computing SEQ. */
5221 seq_cost (const rtx_insn
*seq
, bool speed
)
5226 for (; seq
; seq
= NEXT_INSN (seq
))
5228 set
= single_set (seq
);
5230 cost
+= set_rtx_cost (set
, speed
);
5238 /* Given an insn INSN and condition COND, return the condition in a
5239 canonical form to simplify testing by callers. Specifically:
5241 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5242 (2) Both operands will be machine operands; (cc0) will have been replaced.
5243 (3) If an operand is a constant, it will be the second operand.
5244 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5245 for GE, GEU, and LEU.
5247 If the condition cannot be understood, or is an inequality floating-point
5248 comparison which needs to be reversed, 0 will be returned.
5250 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5252 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5253 insn used in locating the condition was found. If a replacement test
5254 of the condition is desired, it should be placed in front of that
5255 insn and we will be sure that the inputs are still valid.
5257 If WANT_REG is nonzero, we wish the condition to be relative to that
5258 register, if possible. Therefore, do not canonicalize the condition
5259 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5260 to be a compare to a CC mode register.
5262 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5266 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5267 rtx_insn
**earliest
,
5268 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5271 rtx_insn
*prev
= insn
;
5275 int reverse_code
= 0;
5277 basic_block bb
= BLOCK_FOR_INSN (insn
);
5279 code
= GET_CODE (cond
);
5280 mode
= GET_MODE (cond
);
5281 op0
= XEXP (cond
, 0);
5282 op1
= XEXP (cond
, 1);
5285 code
= reversed_comparison_code (cond
, insn
);
5286 if (code
== UNKNOWN
)
5292 /* If we are comparing a register with zero, see if the register is set
5293 in the previous insn to a COMPARE or a comparison operation. Perform
5294 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5297 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5298 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5299 && op1
== CONST0_RTX (GET_MODE (op0
))
5302 /* Set nonzero when we find something of interest. */
5305 /* If comparison with cc0, import actual comparison from compare
5309 if ((prev
= prev_nonnote_insn (prev
)) == 0
5310 || !NONJUMP_INSN_P (prev
)
5311 || (set
= single_set (prev
)) == 0
5312 || SET_DEST (set
) != cc0_rtx
)
5315 op0
= SET_SRC (set
);
5316 op1
= CONST0_RTX (GET_MODE (op0
));
5321 /* If this is a COMPARE, pick up the two things being compared. */
5322 if (GET_CODE (op0
) == COMPARE
)
5324 op1
= XEXP (op0
, 1);
5325 op0
= XEXP (op0
, 0);
5328 else if (!REG_P (op0
))
5331 /* Go back to the previous insn. Stop if it is not an INSN. We also
5332 stop if it isn't a single set or if it has a REG_INC note because
5333 we don't want to bother dealing with it. */
5335 prev
= prev_nonnote_nondebug_insn (prev
);
5338 || !NONJUMP_INSN_P (prev
)
5339 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5340 /* In cfglayout mode, there do not have to be labels at the
5341 beginning of a block, or jumps at the end, so the previous
5342 conditions would not stop us when we reach bb boundary. */
5343 || BLOCK_FOR_INSN (prev
) != bb
)
5346 set
= set_of (op0
, prev
);
5349 && (GET_CODE (set
) != SET
5350 || !rtx_equal_p (SET_DEST (set
), op0
)))
5353 /* If this is setting OP0, get what it sets it to if it looks
5357 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5358 #ifdef FLOAT_STORE_FLAG_VALUE
5359 REAL_VALUE_TYPE fsfv
;
5362 /* ??? We may not combine comparisons done in a CCmode with
5363 comparisons not done in a CCmode. This is to aid targets
5364 like Alpha that have an IEEE compliant EQ instruction, and
5365 a non-IEEE compliant BEQ instruction. The use of CCmode is
5366 actually artificial, simply to prevent the combination, but
5367 should not affect other platforms.
5369 However, we must allow VOIDmode comparisons to match either
5370 CCmode or non-CCmode comparison, because some ports have
5371 modeless comparisons inside branch patterns.
5373 ??? This mode check should perhaps look more like the mode check
5374 in simplify_comparison in combine. */
5375 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5376 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5378 && inner_mode
!= VOIDmode
)
5380 if (GET_CODE (SET_SRC (set
)) == COMPARE
5383 && val_signbit_known_set_p (inner_mode
,
5385 #ifdef FLOAT_STORE_FLAG_VALUE
5387 && SCALAR_FLOAT_MODE_P (inner_mode
)
5388 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5389 REAL_VALUE_NEGATIVE (fsfv
)))
5392 && COMPARISON_P (SET_SRC (set
))))
5394 else if (((code
== EQ
5396 && val_signbit_known_set_p (inner_mode
,
5398 #ifdef FLOAT_STORE_FLAG_VALUE
5400 && SCALAR_FLOAT_MODE_P (inner_mode
)
5401 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5402 REAL_VALUE_NEGATIVE (fsfv
)))
5405 && COMPARISON_P (SET_SRC (set
)))
5410 else if ((code
== EQ
|| code
== NE
)
5411 && GET_CODE (SET_SRC (set
)) == XOR
)
5412 /* Handle sequences like:
5415 ...(eq|ne op0 (const_int 0))...
5419 (eq op0 (const_int 0)) reduces to (eq X Y)
5420 (ne op0 (const_int 0)) reduces to (ne X Y)
5422 This is the form used by MIPS16, for example. */
5428 else if (reg_set_p (op0
, prev
))
5429 /* If this sets OP0, but not directly, we have to give up. */
5434 /* If the caller is expecting the condition to be valid at INSN,
5435 make sure X doesn't change before INSN. */
5436 if (valid_at_insn_p
)
5437 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5439 if (COMPARISON_P (x
))
5440 code
= GET_CODE (x
);
5443 code
= reversed_comparison_code (x
, prev
);
5444 if (code
== UNKNOWN
)
5449 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5455 /* If constant is first, put it last. */
5456 if (CONSTANT_P (op0
))
5457 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5459 /* If OP0 is the result of a comparison, we weren't able to find what
5460 was really being compared, so fail. */
5462 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5465 /* Canonicalize any ordered comparison with integers involving equality
5466 if we can do computations in the relevant mode and we do not
5469 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5470 && CONST_INT_P (op1
)
5471 && GET_MODE (op0
) != VOIDmode
5472 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5474 HOST_WIDE_INT const_val
= INTVAL (op1
);
5475 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5476 unsigned HOST_WIDE_INT max_val
5477 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5482 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5483 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5486 /* When cross-compiling, const_val might be sign-extended from
5487 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5489 if ((const_val
& max_val
)
5490 != (HOST_WIDE_INT_1U
5491 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5492 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5496 if (uconst_val
< max_val
)
5497 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5501 if (uconst_val
!= 0)
5502 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5510 /* Never return CC0; return zero instead. */
5514 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5517 /* Given a jump insn JUMP, return the condition that will cause it to branch
5518 to its JUMP_LABEL. If the condition cannot be understood, or is an
5519 inequality floating-point comparison which needs to be reversed, 0 will
5522 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5523 insn used in locating the condition was found. If a replacement test
5524 of the condition is desired, it should be placed in front of that
5525 insn and we will be sure that the inputs are still valid. If EARLIEST
5526 is null, the returned condition will be valid at INSN.
5528 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5529 compare CC mode register.
5531 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5534 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5535 int valid_at_insn_p
)
5541 /* If this is not a standard conditional jump, we can't parse it. */
5543 || ! any_condjump_p (jump
))
5545 set
= pc_set (jump
);
5547 cond
= XEXP (SET_SRC (set
), 0);
5549 /* If this branches to JUMP_LABEL when the condition is false, reverse
5552 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5553 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5555 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5556 allow_cc_mode
, valid_at_insn_p
);
5559 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5560 TARGET_MODE_REP_EXTENDED.
5562 Note that we assume that the property of
5563 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5564 narrower than mode B. I.e., if A is a mode narrower than B then in
5565 order to be able to operate on it in mode B, mode A needs to
5566 satisfy the requirements set by the representation of mode B. */
5569 init_num_sign_bit_copies_in_rep (void)
5571 machine_mode mode
, in_mode
;
5573 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5574 in_mode
= GET_MODE_WIDER_MODE (mode
))
5575 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5576 mode
= GET_MODE_WIDER_MODE (mode
))
5580 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5581 extends to the next widest mode. */
5582 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5583 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5585 /* We are in in_mode. Count how many bits outside of mode
5586 have to be copies of the sign-bit. */
5587 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5589 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5591 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5592 /* We can only check sign-bit copies starting from the
5593 top-bit. In order to be able to check the bits we
5594 have already seen we pretend that subsequent bits
5595 have to be sign-bit copies too. */
5596 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5597 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5598 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5603 /* Suppose that truncation from the machine mode of X to MODE is not a
5604 no-op. See if there is anything special about X so that we can
5605 assume it already contains a truncated value of MODE. */
5608 truncated_to_mode (machine_mode mode
, const_rtx x
)
5610 /* This register has already been used in MODE without explicit
5612 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5615 /* See if we already satisfy the requirements of MODE. If yes we
5616 can just switch to MODE. */
5617 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5618 && (num_sign_bit_copies (x
, GET_MODE (x
))
5619 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5625 /* Return true if RTX code CODE has a single sequence of zero or more
5626 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5627 entry in that case. */
5630 setup_reg_subrtx_bounds (unsigned int code
)
5632 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5634 for (; format
[i
] != 'e'; ++i
)
5637 /* No subrtxes. Leave start and count as 0. */
5639 if (format
[i
] == 'E' || format
[i
] == 'V')
5643 /* Record the sequence of 'e's. */
5644 rtx_all_subrtx_bounds
[code
].start
= i
;
5647 while (format
[i
] == 'e');
5648 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5649 /* rtl-iter.h relies on this. */
5650 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5652 for (; format
[i
]; ++i
)
5653 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5659 /* Initialize rtx_all_subrtx_bounds. */
5664 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5666 if (!setup_reg_subrtx_bounds (i
))
5667 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5668 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5669 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5672 init_num_sign_bit_copies_in_rep ();
5675 /* Check whether this is a constant pool constant. */
5677 constant_pool_constant_p (rtx x
)
5679 x
= avoid_constant_pool_reference (x
);
5680 return CONST_DOUBLE_P (x
);
5683 /* If M is a bitmask that selects a field of low-order bits within an item but
5684 not the entire word, return the length of the field. Return -1 otherwise.
5685 M is used in machine mode MODE. */
5688 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5690 if (mode
!= VOIDmode
)
5692 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5694 m
&= GET_MODE_MASK (mode
);
5697 return exact_log2 (m
+ 1);
5700 /* Return the mode of MEM's address. */
5703 get_address_mode (rtx mem
)
5707 gcc_assert (MEM_P (mem
));
5708 mode
= GET_MODE (XEXP (mem
, 0));
5709 if (mode
!= VOIDmode
)
5711 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5714 /* Split up a CONST_DOUBLE or integer constant rtx
5715 into two rtx's for single words,
5716 storing in *FIRST the word that comes first in memory in the target
5717 and in *SECOND the other.
5719 TODO: This function needs to be rewritten to work on any size
5723 split_double (rtx value
, rtx
*first
, rtx
*second
)
5725 if (CONST_INT_P (value
))
5727 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5729 /* In this case the CONST_INT holds both target words.
5730 Extract the bits from it into two word-sized pieces.
5731 Sign extend each half to HOST_WIDE_INT. */
5732 unsigned HOST_WIDE_INT low
, high
;
5733 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5734 unsigned bits_per_word
= BITS_PER_WORD
;
5736 /* Set sign_bit to the most significant bit of a word. */
5738 sign_bit
<<= bits_per_word
- 1;
5740 /* Set mask so that all bits of the word are set. We could
5741 have used 1 << BITS_PER_WORD instead of basing the
5742 calculation on sign_bit. However, on machines where
5743 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5744 compiler warning, even though the code would never be
5746 mask
= sign_bit
<< 1;
5749 /* Set sign_extend as any remaining bits. */
5750 sign_extend
= ~mask
;
5752 /* Pick the lower word and sign-extend it. */
5753 low
= INTVAL (value
);
5758 /* Pick the higher word, shifted to the least significant
5759 bits, and sign-extend it. */
5760 high
= INTVAL (value
);
5761 high
>>= bits_per_word
- 1;
5764 if (high
& sign_bit
)
5765 high
|= sign_extend
;
5767 /* Store the words in the target machine order. */
5768 if (WORDS_BIG_ENDIAN
)
5770 *first
= GEN_INT (high
);
5771 *second
= GEN_INT (low
);
5775 *first
= GEN_INT (low
);
5776 *second
= GEN_INT (high
);
5781 /* The rule for using CONST_INT for a wider mode
5782 is that we regard the value as signed.
5783 So sign-extend it. */
5784 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5785 if (WORDS_BIG_ENDIAN
)
5797 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5799 /* All of this is scary code and needs to be converted to
5800 properly work with any size integer. */
5801 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5802 if (WORDS_BIG_ENDIAN
)
5804 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5805 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5809 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5810 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5813 else if (!CONST_DOUBLE_P (value
))
5815 if (WORDS_BIG_ENDIAN
)
5817 *first
= const0_rtx
;
5823 *second
= const0_rtx
;
5826 else if (GET_MODE (value
) == VOIDmode
5827 /* This is the old way we did CONST_DOUBLE integers. */
5828 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5830 /* In an integer, the words are defined as most and least significant.
5831 So order them by the target's convention. */
5832 if (WORDS_BIG_ENDIAN
)
5834 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5835 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5839 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5840 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5847 /* Note, this converts the REAL_VALUE_TYPE to the target's
5848 format, splits up the floating point double and outputs
5849 exactly 32 bits of it into each of l[0] and l[1] --
5850 not necessarily BITS_PER_WORD bits. */
5851 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5853 /* If 32 bits is an entire word for the target, but not for the host,
5854 then sign-extend on the host so that the number will look the same
5855 way on the host that it would on the target. See for instance
5856 simplify_unary_operation. The #if is needed to avoid compiler
5859 #if HOST_BITS_PER_LONG > 32
5860 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5862 if (l
[0] & ((long) 1 << 31))
5863 l
[0] |= ((unsigned long) (-1) << 32);
5864 if (l
[1] & ((long) 1 << 31))
5865 l
[1] |= ((unsigned long) (-1) << 32);
5869 *first
= GEN_INT (l
[0]);
5870 *second
= GEN_INT (l
[1]);
5874 /* Return true if X is a sign_extract or zero_extract from the least
5878 lsb_bitfield_op_p (rtx x
)
5880 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5882 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5883 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5884 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5886 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5891 /* Strip outer address "mutations" from LOC and return a pointer to the
5892 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5893 stripped expression there.
5895 "Mutations" either convert between modes or apply some kind of
5896 extension, truncation or alignment. */
5899 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5903 enum rtx_code code
= GET_CODE (*loc
);
5904 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5905 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5906 used to convert between pointer sizes. */
5907 loc
= &XEXP (*loc
, 0);
5908 else if (lsb_bitfield_op_p (*loc
))
5909 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5910 acts as a combined truncation and extension. */
5911 loc
= &XEXP (*loc
, 0);
5912 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5913 /* (and ... (const_int -X)) is used to align to X bytes. */
5914 loc
= &XEXP (*loc
, 0);
5915 else if (code
== SUBREG
5916 && !OBJECT_P (SUBREG_REG (*loc
))
5917 && subreg_lowpart_p (*loc
))
5918 /* (subreg (operator ...) ...) inside and is used for mode
5920 loc
= &SUBREG_REG (*loc
);
5928 /* Return true if CODE applies some kind of scale. The scaled value is
5929 is the first operand and the scale is the second. */
5932 binary_scale_code_p (enum rtx_code code
)
5934 return (code
== MULT
5936 /* Needed by ARM targets. */
5940 || code
== ROTATERT
);
5943 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5944 (see address_info). Return null otherwise. */
5947 get_base_term (rtx
*inner
)
5949 if (GET_CODE (*inner
) == LO_SUM
)
5950 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5953 || GET_CODE (*inner
) == SUBREG
5954 || GET_CODE (*inner
) == SCRATCH
)
5959 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5960 (see address_info). Return null otherwise. */
5963 get_index_term (rtx
*inner
)
5965 /* At present, only constant scales are allowed. */
5966 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5967 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5970 || GET_CODE (*inner
) == SUBREG
5971 || GET_CODE (*inner
) == SCRATCH
)
5976 /* Set the segment part of address INFO to LOC, given that INNER is the
5980 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5982 gcc_assert (!info
->segment
);
5983 info
->segment
= loc
;
5984 info
->segment_term
= inner
;
5987 /* Set the base part of address INFO to LOC, given that INNER is the
5991 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5993 gcc_assert (!info
->base
);
5995 info
->base_term
= inner
;
5998 /* Set the index part of address INFO to LOC, given that INNER is the
6002 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6004 gcc_assert (!info
->index
);
6006 info
->index_term
= inner
;
6009 /* Set the displacement part of address INFO to LOC, given that INNER
6010 is the constant term. */
6013 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6015 gcc_assert (!info
->disp
);
6017 info
->disp_term
= inner
;
6020 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6021 rest of INFO accordingly. */
6024 decompose_incdec_address (struct address_info
*info
)
6026 info
->autoinc_p
= true;
6028 rtx
*base
= &XEXP (*info
->inner
, 0);
6029 set_address_base (info
, base
, base
);
6030 gcc_checking_assert (info
->base
== info
->base_term
);
6032 /* These addresses are only valid when the size of the addressed
6034 gcc_checking_assert (info
->mode
!= VOIDmode
);
6037 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6038 of INFO accordingly. */
6041 decompose_automod_address (struct address_info
*info
)
6043 info
->autoinc_p
= true;
6045 rtx
*base
= &XEXP (*info
->inner
, 0);
6046 set_address_base (info
, base
, base
);
6047 gcc_checking_assert (info
->base
== info
->base_term
);
6049 rtx plus
= XEXP (*info
->inner
, 1);
6050 gcc_assert (GET_CODE (plus
) == PLUS
);
6052 info
->base_term2
= &XEXP (plus
, 0);
6053 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6055 rtx
*step
= &XEXP (plus
, 1);
6056 rtx
*inner_step
= strip_address_mutations (step
);
6057 if (CONSTANT_P (*inner_step
))
6058 set_address_disp (info
, step
, inner_step
);
6060 set_address_index (info
, step
, inner_step
);
6063 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6064 values in [PTR, END). Return a pointer to the end of the used array. */
6067 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6070 if (GET_CODE (x
) == PLUS
)
6072 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6073 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6077 gcc_assert (ptr
!= end
);
6083 /* Evaluate the likelihood of X being a base or index value, returning
6084 positive if it is likely to be a base, negative if it is likely to be
6085 an index, and 0 if we can't tell. Make the magnitude of the return
6086 value reflect the amount of confidence we have in the answer.
6088 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6091 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6092 enum rtx_code outer_code
, enum rtx_code index_code
)
6094 /* Believe *_POINTER unless the address shape requires otherwise. */
6095 if (REG_P (x
) && REG_POINTER (x
))
6097 if (MEM_P (x
) && MEM_POINTER (x
))
6100 if (REG_P (x
) && HARD_REGISTER_P (x
))
6102 /* X is a hard register. If it only fits one of the base
6103 or index classes, choose that interpretation. */
6104 int regno
= REGNO (x
);
6105 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6106 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6107 if (base_p
!= index_p
)
6108 return base_p
? 1 : -1;
6113 /* INFO->INNER describes a normal, non-automodified address.
6114 Fill in the rest of INFO accordingly. */
6117 decompose_normal_address (struct address_info
*info
)
6119 /* Treat the address as the sum of up to four values. */
6121 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6122 ops
+ ARRAY_SIZE (ops
)) - ops
;
6124 /* If there is more than one component, any base component is in a PLUS. */
6126 info
->base_outer_code
= PLUS
;
6128 /* Try to classify each sum operand now. Leave those that could be
6129 either a base or an index in OPS. */
6132 for (size_t in
= 0; in
< n_ops
; ++in
)
6135 rtx
*inner
= strip_address_mutations (loc
);
6136 if (CONSTANT_P (*inner
))
6137 set_address_disp (info
, loc
, inner
);
6138 else if (GET_CODE (*inner
) == UNSPEC
)
6139 set_address_segment (info
, loc
, inner
);
6142 /* The only other possibilities are a base or an index. */
6143 rtx
*base_term
= get_base_term (inner
);
6144 rtx
*index_term
= get_index_term (inner
);
6145 gcc_assert (base_term
|| index_term
);
6147 set_address_index (info
, loc
, index_term
);
6148 else if (!index_term
)
6149 set_address_base (info
, loc
, base_term
);
6152 gcc_assert (base_term
== index_term
);
6154 inner_ops
[out
] = base_term
;
6160 /* Classify the remaining OPS members as bases and indexes. */
6163 /* If we haven't seen a base or an index yet, assume that this is
6164 the base. If we were confident that another term was the base
6165 or index, treat the remaining operand as the other kind. */
6167 set_address_base (info
, ops
[0], inner_ops
[0]);
6169 set_address_index (info
, ops
[0], inner_ops
[0]);
6173 /* In the event of a tie, assume the base comes first. */
6174 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6176 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6177 GET_CODE (*ops
[0])))
6179 set_address_base (info
, ops
[0], inner_ops
[0]);
6180 set_address_index (info
, ops
[1], inner_ops
[1]);
6184 set_address_base (info
, ops
[1], inner_ops
[1]);
6185 set_address_index (info
, ops
[0], inner_ops
[0]);
6189 gcc_assert (out
== 0);
6192 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6193 or VOIDmode if not known. AS is the address space associated with LOC.
6194 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6197 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6198 addr_space_t as
, enum rtx_code outer_code
)
6200 memset (info
, 0, sizeof (*info
));
6203 info
->addr_outer_code
= outer_code
;
6205 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6206 info
->base_outer_code
= outer_code
;
6207 switch (GET_CODE (*info
->inner
))
6213 decompose_incdec_address (info
);
6218 decompose_automod_address (info
);
6222 decompose_normal_address (info
);
6227 /* Describe address operand LOC in INFO. */
6230 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6232 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6235 /* Describe the address of MEM X in INFO. */
6238 decompose_mem_address (struct address_info
*info
, rtx x
)
6240 gcc_assert (MEM_P (x
));
6241 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6242 MEM_ADDR_SPACE (x
), MEM
);
6245 /* Update INFO after a change to the address it describes. */
6248 update_address (struct address_info
*info
)
6250 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6251 info
->addr_outer_code
);
6254 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6255 more complicated than that. */
6258 get_index_scale (const struct address_info
*info
)
6260 rtx index
= *info
->index
;
6261 if (GET_CODE (index
) == MULT
6262 && CONST_INT_P (XEXP (index
, 1))
6263 && info
->index_term
== &XEXP (index
, 0))
6264 return INTVAL (XEXP (index
, 1));
6266 if (GET_CODE (index
) == ASHIFT
6267 && CONST_INT_P (XEXP (index
, 1))
6268 && info
->index_term
== &XEXP (index
, 0))
6269 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6271 if (info
->index
== info
->index_term
)
6277 /* Return the "index code" of INFO, in the form required by
6281 get_index_code (const struct address_info
*info
)
6284 return GET_CODE (*info
->index
);
6287 return GET_CODE (*info
->disp
);
6292 /* Return true if RTL X contains a SYMBOL_REF. */
6295 contains_symbol_ref_p (const_rtx x
)
6297 subrtx_iterator::array_type array
;
6298 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6299 if (SYMBOL_REF_P (*iter
))
6305 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6308 contains_symbolic_reference_p (const_rtx x
)
6310 subrtx_iterator::array_type array
;
6311 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6312 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6318 /* Return true if X contains a thread-local symbol. */
6321 tls_referenced_p (const_rtx x
)
6323 if (!targetm
.have_tls
)
6326 subrtx_iterator::array_type array
;
6327 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6328 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)