| blob | 69020561c3147fec1c2a085086fbc68505dc83ad |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
97 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
107 /* Number of attempts to combine instructions in this function. */
111 /* Number of attempts that got as far as substitution in this function. */
115 /* Number of instructions combined with added SETs in this function. */
119 /* Number of instructions combined in this function. */
123 /* Totals over entire compilation. */
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 \f
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
158 following ways:
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
173 register's value
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
178 table.
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
196 rtx last_set_value;
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
203 /* Record the value of label_tick when the value for register n is placed in
204 last_set_value. */
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
231 zero.
233 If an entry is zero, it means that we don't know anything special. */
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
248 value. */
251 };
256 /* One plus the highest pseudo for which we track REG_N_SETS.
257 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
258 but during combine_split_insns new pseudos can be created. As we don't have
259 updated DF information in that case, it is hard to initialize the array
260 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
261 so instead of growing the arrays, just assume all newly created pseudos
262 during combine might be set multiple times. */
266 /* Record the luid of the last insn that invalidated memory
267 (anything that writes memory, and subroutine calls, but not pushes). */
271 /* Record the luid of the last CALL_INSN
272 so we can tell whether a potential combination crosses any calls. */
276 /* When `subst' is called, this is the insn that is being modified
277 (by combining in a previous insn). The PATTERN of this insn
278 is still the old pattern partially modified and it should not be
279 looked at, but this may be used to examine the successors of the insn
280 to judge whether a simplification is valid. */
284 /* This is the lowest LUID that `subst' is currently dealing with.
285 get_last_value will not return a value if the register was set at or
286 after this LUID. If not for this mechanism, we could get confused if
287 I2 or I1 in try_combine were an insn that used the old value of a register
288 to obtain a new value. In that case, we might erroneously get the
289 new value of the register when we wanted the old one. */
293 /* This contains any hard registers that are used in newpat; reg_dead_at_p
294 must consider all these registers to be always live. */
298 /* This is an insn to which a LOG_LINKS entry has been added. If this
299 insn is the earlier than I2 or I3, combine should rescan starting at
300 that location. */
304 /* Basic block in which we are performing combines. */
308 \f
309 /* Length of the currently allocated uid_insn_cost array. */
313 /* The following array records the insn_rtx_cost for every insn
314 in the instruction stream. */
318 /* The following array records the LOG_LINKS for every insn in the
319 instruction stream as struct insn_link pointers. */
325 };
329 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
339 /* Allocate a link. */
343 {
351 }
353 /* Incremented for each basic block. */
357 /* Reset to label_tick for each extended basic block in scanning order. */
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
370 in a loop. */
374 \f
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
380 struct undo
381 {
386 };
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
394 struct undobuf
395 {
399 };
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
409 machine_mode,
413 machine_mode,
485 \f
487 /* It is not safe to use ordinary gen_lowpart in combine.
488 See comments in gen_lowpart_for_combine. */
489 #undef RTL_HOOKS_GEN_LOWPART
490 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 /* Our implementation of gen_lowpart never emits a new pseudo. */
493 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
494 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
496 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
497 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
500 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
503 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
507 \f
508 /* Convenience wrapper for the canonicalize_comparison target hook.
509 Target hooks cannot use enum rtx_code. */
513 {
517 }
519 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
520 PATTERN can not be split. Otherwise, it returns an insn sequence.
521 This is a wrapper around split_insns which ensures that the
522 reg_stat vector is made larger if the splitter creates a new
523 register. */
527 {
536 }
538 /* This is used by find_single_use to locate an rtx in LOC that
539 contains exactly one use of DEST, which is typically either a REG
540 or CC0. It returns a pointer to the innermost rtx expression
541 containing DEST. Appearances of DEST that are being used to
542 totally replace it are not counted. */
546 {
555 {
559 CASE_CONST_ANY:
564 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
565 of a REG that occupies all of the REG, the insn uses DEST if
566 it is mentioned in the destination or the source. Otherwise, we
567 need just check the source. */
587 }
589 /* If it wasn't one of the common cases above, check each expression and
590 vector of this code. Look for a unique usage of DEST. */
594 {
596 {
601 else
607 /* Duplicate usage. */
609 }
611 {
615 {
621 else
628 }
629 }
630 }
633 }
636 /* See if DEST, produced in INSN, is used only a single time in the
637 sequel. If so, return a pointer to the innermost rtx expression in which
638 it is used.
640 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
643 care about REG_DEAD notes or LOG_LINKS.
645 Otherwise, we find the single use by finding an insn that has a
646 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
647 only referenced once in that insn, we know that it must be the first
648 and last insn referencing DEST. */
652 {
653 basic_block bb;
659 {
669 }
679 {
685 {
690 }
691 }
694 }
695 \f
696 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
697 insn. The substitution can be undone by undo_all. If INTO is already
698 set to NEWVAL, do not record this change. Because computing NEWVAL might
699 also call SUBST, we have to compute it before we put anything into
700 the undo table. */
702 static void
704 {
711 /* We'd like to catch as many invalid transformations here as
712 possible. Unfortunately, there are way too many mode changes
713 that are perfectly valid, so we'd waste too much effort for
714 little gain doing the checks here. Focus on catching invalid
715 transformations involving integer constants. */
718 {
719 /* Sanity check that we're replacing oldval with a CONST_INT
720 that is a valid sign-extension for the original mode. */
724 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
725 CONST_INT is not valid, because after the replacement, the
726 original mode would be gone. Unfortunately, we can't tell
727 when do_SUBST is called to replace the operand thereof, so we
728 perform this test on oldval instead, checking whether an
729 invalid replacement took place before we got here. */
734 }
738 else
747 }
749 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
751 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
752 for the value of a HOST_WIDE_INT value (including CONST_INT) is
753 not safe. */
755 static void
757 {
766 else
775 }
777 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
779 /* Similar to SUBST, but just substitute the mode. This is used when
780 changing the mode of a pseudo-register, so that any other
781 references to the entry in the regno_reg_rtx array will change as
782 well. */
784 static void
786 {
795 else
804 }
806 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
808 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
810 static void
812 {
821 else
830 }
832 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
833 \f
834 /* Subroutine of try_combine. Determine whether the replacement patterns
835 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
836 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
837 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
838 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
839 of all the instructions can be estimated and the replacements are more
840 expensive than the original sequence. */
842 static bool
845 {
850 /* Lookup the original insn_rtx_costs. */
855 {
858 {
862 }
863 else
864 {
868 }
869 }
870 else
871 {
874 }
876 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
877 correct that. */
882 /* Calculate the replacement insn_rtx_costs. */
885 {
889 }
890 else
891 {
894 }
897 {
903 {
906 }
907 else
909 }
911 /* Disallow this combination if both new_cost and old_cost are greater than
912 zero, and new_cost is greater than old cost. */
916 {
935 else
937 }
942 /* Update the uid_insn_cost array with the replacement costs. */
946 {
950 }
953 }
956 /* Delete any insns that copy a register to itself. */
958 static void
960 {
962 basic_block bb;
965 {
967 {
970 {
975 }
976 }
977 }
978 }
980 \f
981 /* Return false if we do not want to (or cannot) combine DEF. */
982 static bool
984 {
985 /* Do not consider if it is pre/post modification in MEM. */
991 /* Do not combine frame pointer adjustments. */
994 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1002 }
1004 /* Return false if we do not want to (or cannot) combine USE. */
1005 static bool
1007 {
1008 /* Do not consider the usage of the stack pointer by function call. */
1013 }
1015 /* Fill in log links field for all insns. */
1017 static void
1019 {
1020 basic_block bb;
1027 /* Pass through each block from the end, recording the uses of each
1028 register and establishing log links when def is encountered.
1029 Note that we do not clear next_use array in order to save time,
1030 so we have to test whether the use is in the same basic block as def.
1032 There are a few cases below when we do not consider the definition or
1033 usage -- these are taken from original flow.c did. Don't ask me why it is
1034 done this way; I don't know and if it works, I don't want to know. */
1037 {
1039 {
1043 /* Log links are created only once. */
1047 {
1063 /* flow.c claimed:
1065 We don't build a LOG_LINK for hard registers contained
1066 in ASM_OPERANDs. If these registers get replaced,
1067 we might wind up changing the semantics of the insn,
1068 even if reload can make what appear to be valid
1069 assignments later. */
1074 /* Don't add duplicate links between instructions. */
1083 }
1088 }
1089 }
1092 }
1094 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095 true if we found a LOG_LINK that proves that A feeds B. This only works
1096 if there are no instructions between A and B which could have a link
1097 depending on A, since in that case we would not record a link for B.
1098 We also check the implicit dependency created by a cc0 setter/user
1099 pair. */
1101 static bool
1103 {
1111 }
1112 \f
1113 /* Main entry point for combiner. F is the first insn of the function.
1114 NREGS is the first unused pseudo-reg number.
1116 Return nonzero if the combiner has turned an indirect jump
1117 instruction into a direct jump. */
1118 static int
1120 {
1125 basic_block last_bb;
1145 /* Allocate array for insn info. */
1153 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1154 problems when, for example, we have j <<= 1 in a loop. */
1159 /* Scan all SETs and see if we can deduce anything about what
1160 bits are known to be zero for some registers and how many copies
1161 of the sign bit are known to exist for those registers.
1163 Also set any known values so that we can use it while searching
1164 for what bits are known to be set. */
1167 /* Allow the entry block and the first block to fall into the same EBB.
1168 Conceptually the incoming promotions are assigned to the entry block. */
1173 {
1178 label_tick++;
1186 {
1187 rtx links;
1193 insn);
1200 insn);
1202 /* Record the current insn_rtx_cost of this instruction. */
1205 optimize_this_for_speed_p);
1209 }
1210 }
1214 /* Now scan all the insns in forward order. */
1222 {
1228 label_tick++;
1238 {
1252 /* See if we know about function return values before this
1253 insn based upon SUBREG flags. */
1256 /* See if we can find hardregs and subreg of pseudos in
1257 narrower modes. This could help turning TRUNCATEs
1258 into SUBREGs. */
1261 /* Try this insn with each insn it links back to. */
1267 {
1270 }
1272 /* Try each sequence of three linked insns ending with this one. */
1276 {
1279 /* If the linked insn has been replaced by a note, then there
1280 is no point in pursuing this chain any further. */
1288 {
1291 }
1292 }
1294 /* Try to combine a jump insn that uses CC0
1295 with a preceding insn that sets CC0, and maybe with its
1296 logical predecessor as well.
1297 This is how we make decrement-and-branch insns.
1298 We need this special code because data flow connections
1299 via CC0 do not get entered in LOG_LINKS. */
1306 {
1317 }
1319 /* Do the same for an insn that explicitly references CC0. */
1326 {
1337 }
1339 /* Finally, see if any of the insns that this insn links to
1340 explicitly references CC0. If so, try this insn, that insn,
1341 and its predecessor if it sets CC0. */
1343 {
1355 }
1357 /* Try combining an insn with two different insns whose results it
1358 uses. */
1368 {
1371 }
1373 /* Try four-instruction combinations. */
1376 {
1380 /* If the linked insn has been replaced by a note, then there
1381 is no point in pursuing this chain any further. */
1386 {
1390 /* I0 -> I1 -> I2 -> I3. */
1396 {
1399 }
1400 /* I0, I1 -> I2, I2 -> I3. */
1407 {
1410 }
1411 }
1414 {
1418 /* I0 -> I2; I1, I2 -> I3. */
1424 {
1427 }
1428 /* I0 -> I1; I1, I2 -> I3. */
1434 {
1437 }
1438 }
1439 }
1441 /* Try this insn with each REG_EQUAL note it links back to. */
1443 {
1449 /* Avoid using a register that may already been marked
1450 dead by an earlier instruction. */
1458 {
1459 /* Temporarily replace the set's source with the
1460 contents of the REG_EQUAL note. The insn will
1461 be deleted or recognized by try_combine. */
1472 last_combined_insn);
1475 {
1478 }
1481 }
1482 }
1487 retry:
1488 ;
1489 }
1490 }
1497 /* Clean up. */
1503 {
1506 {
1509 }
1511 }
1521 /* Make recognizer allow volatile MEMs again. */
1525 }
1527 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1529 static void
1531 {
1537 }
1538 \f
1539 /* Set up any promoted values for incoming argument registers. */
1541 static void
1543 {
1544 tree arg;
1549 {
1554 /* Only continue if the incoming argument is in a register. */
1558 /* Determine, if possible, whether all call sites of the current
1559 function lie within the current compilation unit. (This does
1560 take into account the exporting of a function via taking its
1561 address, and so forth.) */
1564 /* The mode and signedness of the argument before any promotions happen
1565 (equal to the mode of the pseudo holding it at that stage). */
1569 /* The mode and signedness of the argument after any source language and
1570 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1574 /* The mode and signedness of the argument as it is actually passed,
1575 see assign_parm_setup_reg in function.c. */
1579 /* The mode of the register in which the argument is being passed. */
1582 /* Eliminate sign extensions in the callee when:
1583 (a) A mode promotion has occurred; */
1586 /* (b) The mode of the register is the same as the mode of
1587 the argument as it is passed; */
1590 /* (c) There's no language level extension; */
1592 ;
1593 /* (c.1) All callers are from the current compilation unit. If that's
1594 the case we don't have to rely on an ABI, we only have to know
1595 what we're generating right now, and we know that we will do the
1596 mode1 to mode2 promotion with the given sign. */
1599 /* (c.2) The combination of the two promotions is useful. This is
1600 true when the signs match, or if the first promotion is unsigned.
1601 In the later case, (sign_extend (zero_extend x)) is the same as
1602 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1608 /* Record that the value was promoted from mode1 to mode3,
1609 so that any sign extension at the head of the current
1610 function may be eliminated. */
1614 }
1615 }
1617 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1618 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1619 because some machines (maybe most) will actually do the sign-extension and
1620 this is the conservative approach.
1622 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1623 kludge. */
1625 static rtx
1627 {
1635 }
1637 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1638 and SET. */
1640 static void
1642 rtx x)
1643 {
1653 {
1657 }
1659 /* Don't call nonzero_bits if it cannot change anything. */
1661 {
1666 }
1668 /* Don't call num_sign_bit_copies if it cannot change anything. */
1670 {
1673 {
1677 }
1680 }
1681 }
1683 /* Called via note_stores. If X is a pseudo that is narrower than
1684 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1686 If we are setting only a portion of X and we can't figure out what
1687 portion, assume all bits will be used since we don't know what will
1688 be happening.
1690 Similarly, set how many bits of X are known to be copies of the sign bit
1691 at all locations in the function. This is the smallest number implied
1692 by any set of X. */
1694 static void
1696 {
1701 /* If this register is undefined at the start of the file, we can't
1702 say what its contents were. */
1703 && ! REGNO_REG_SET_P
1706 {
1710 {
1714 }
1716 /* If this register is being initialized using itself, and the
1717 register is uninitialized in this basic block, and there are
1718 no LOG_LINKS which set the register, then part of the
1719 register is uninitialized. In that case we can't assume
1720 anything about the number of nonzero bits.
1722 ??? We could do better if we checked this in
1723 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1724 could avoid making assumptions about the insn which initially
1725 sets the register, while still using the information in other
1726 insns. We would have to be careful to check every insn
1727 involved in the combination. */
1733 {
1740 {
1744 }
1745 }
1747 /* If this is a complex assignment, see if we can convert it into a
1748 simple assignment. */
1751 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1752 set what we know about X. */
1758 else
1759 {
1762 }
1763 }
1764 }
1765 \f
1766 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1767 optionally insns that were previously combined into I3 or that will be
1768 combined into the merger of INSN and I3. The order is PRED, PRED2,
1769 INSN, SUCC, SUCC2, I3.
1771 Return 0 if the combination is not allowed for any reason.
1773 If the combination is allowed, *PDEST will be set to the single
1774 destination of INSN and *PSRC to the single source, and this function
1775 will return 1. */
1777 static int
1781 {
1786 rtx link;
1791 {
1793 {
1798 }
1803 }
1807 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1808 or a PARALLEL consisting of such a SET and CLOBBERs.
1810 If INSN has CLOBBER parallel parts, ignore them for our processing.
1811 By definition, these happen during the execution of the insn. When it
1812 is merged with another insn, all bets are off. If they are, in fact,
1813 needed and aren't also supplied in I3, they may be added by
1814 recog_for_combine. Otherwise, it won't match.
1816 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1817 note.
1819 Get the source and destination of INSN. If more than one, can't
1820 combine. */
1826 {
1828 {
1832 {
1833 /* This is important to combine floating point insns
1834 for the SH4 port. */
1836 /* Combining an isolated USE doesn't make sense.
1837 We depend here on combinable_i3pat to reject them. */
1838 /* The code below this loop only verifies that the inputs of
1839 the SET in INSN do not change. We call reg_set_between_p
1840 to verify that the REG in the USE does not change between
1841 I3 and INSN.
1842 If the USE in INSN was for a pseudo register, the matching
1843 insn pattern will likely match any register; combining this
1844 with any other USE would only be safe if we knew that the
1845 used registers have identical values, or if there was
1846 something to tell them apart, e.g. different modes. For
1847 now, we forgo such complicated tests and simply disallow
1848 combining of USES of pseudo registers with any other USE. */
1851 {
1856 do
1857 {
1867 }
1869 }
1872 /* We can ignore CLOBBERs. */
1877 /* Ignore SETs whose result isn't used but not those that
1878 have side-effects. */
1884 /* If we have already found a SET, this is a second one and
1885 so we cannot combine with this insn. */
1893 /* Anything else means we can't combine. */
1895 }
1896 }
1899 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1900 so don't do anything with it. */
1903 }
1904 else
1910 /* The simplification in expand_field_assignment may call back to
1911 get_last_value, so set safe guard here. */
1917 /* Do not eliminate user-specified register if it is in an
1918 asm input because we may break the register asm usage defined
1919 in GCC manual if allow to do so.
1920 Be aware that this may cover more cases than we expect but this
1921 should be harmless. */
1926 /* Don't eliminate a store in the stack pointer. */
1928 /* Don't combine with an insn that sets a register to itself if it has
1929 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1931 /* Can't merge an ASM_OPERANDS. */
1933 /* Can't merge a function call. */
1935 /* Don't eliminate a function call argument. */
1941 /* Don't substitute into an incremented register. */
1945 /* Don't substitute into a non-local goto, this confuses CFG. */
1947 /* Make sure that DEST is not used after SUCC but before I3. */
1948 || (!all_adjacent
1949 && ((succ2
1953 /* Make sure that the value that is to be substituted for the register
1954 does not use any registers whose values alter in between. However,
1955 If the insns are adjacent, a use can't cross a set even though we
1956 think it might (this can happen for a sequence of insns each setting
1957 the same destination; last_set of that register might point to
1958 a NOTE). If INSN has a REG_EQUIV note, the register is always
1959 equivalent to the memory so the substitution is valid even if there
1960 are intervening stores. Also, don't move a volatile asm or
1961 UNSPEC_VOLATILE across any other insns. */
1962 || (! all_adjacent
1968 /* Don't combine across a CALL_INSN, because that would possibly
1969 change whether the life span of some REGs crosses calls or not,
1970 and it is a pain to update that information.
1971 Exception: if source is a constant, moving it later can't hurt.
1972 Accept that as a special case. */
1976 /* DEST must either be a REG or CC0. */
1978 {
1979 /* If register alignment is being enforced for multi-word items in all
1980 cases except for parameters, it is possible to have a register copy
1981 insn referencing a hard register that is not allowed to contain the
1982 mode being copied and which would not be valid as an operand of most
1983 insns. Eliminate this problem by not combining with such an insn.
1985 Also, on some machines we don't want to extend the life of a hard
1986 register. */
1991 /* Don't extend the life of a hard register unless it is
1992 user variable (if we have few registers) or it can't
1993 fit into the desired register (meaning something special
1994 is going on).
1995 Also avoid substituting a return register into I3, because
1996 reload can't handle a conflict with constraints of other
1997 inputs. */
2001 }
2009 {
2012 /* If the clobber represents an earlyclobber operand, we must not
2013 substitute an expression containing the clobbered register.
2014 As we do not analyze the constraint strings here, we have to
2015 make the conservative assumption. However, if the register is
2016 a fixed hard reg, the clobber cannot represent any operand;
2017 we leave it up to the machine description to either accept or
2018 reject use-and-clobber patterns. */
2024 }
2026 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2027 or not), reject, unless nothing volatile comes between it and I3 */
2030 {
2031 /* Make sure neither succ nor succ2 contains a volatile reference. */
2036 /* We'll check insns between INSN and I3 below. */
2037 }
2039 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2040 to be an explicit register variable, and was chosen for a reason. */
2046 /* If INSN contains volatile references (specifically volatile MEMs),
2047 we cannot combine across any other volatile references.
2048 Even if INSN doesn't contain volatile references, any intervening
2049 volatile insn might affect machine state. */
2052 ? volatile_refs_p
2059 /* If INSN contains an autoincrement or autodecrement, make sure that
2060 register is not used between there and I3, and not already used in
2061 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2062 Also insist that I3 not be a jump; if it were one
2063 and the incremented register were spilled, we would lose. */
2081 /* Don't combine an insn that follows a CC0-setting insn.
2082 An insn that uses CC0 must not be separated from the one that sets it.
2083 We do, however, allow I2 to follow a CC0-setting insn if that insn
2084 is passed as I1; in that case it will be deleted also.
2085 We also allow combining in this case if all the insns are adjacent
2086 because that would leave the two CC0 insns adjacent as well.
2087 It would be more logical to test whether CC0 occurs inside I1 or I2,
2088 but that would be much slower, and this ought to be equivalent. */
2091 {
2096 }
2098 /* If we get here, we have passed all the tests and the combination is
2099 to be allowed. */
2105 }
2106 \f
2107 /* LOC is the location within I3 that contains its pattern or the component
2108 of a PARALLEL of the pattern. We validate that it is valid for combining.
2110 One problem is if I3 modifies its output, as opposed to replacing it
2111 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2112 doing so would produce an insn that is not equivalent to the original insns.
2114 Consider:
2116 (set (reg:DI 101) (reg:DI 100))
2117 (set (subreg:SI (reg:DI 101) 0) <foo>)
2119 This is NOT equivalent to:
2121 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2122 (set (reg:DI 101) (reg:DI 100))])
2124 Not only does this modify 100 (in which case it might still be valid
2125 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2127 We can also run into a problem if I2 sets a register that I1
2128 uses and I1 gets directly substituted into I3 (not via I2). In that
2129 case, we would be getting the wrong value of I2DEST into I3, so we
2130 must reject the combination. This case occurs when I2 and I1 both
2131 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2132 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2133 of a SET must prevent combination from occurring. The same situation
2134 can occur for I0, in which case I0_NOT_IN_SRC is set.
2136 Before doing the above check, we first try to expand a field assignment
2137 into a set of logical operations.
2139 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2140 we place a register that is both set and used within I3. If more than one
2141 such register is detected, we fail.
2143 Return 1 if the combination is valid, zero otherwise. */
2145 static int
2148 {
2152 {
2157 rtx subdest;
2164 /* Check for the case where I3 modifies its output, as discussed
2165 above. We don't want to prevent pseudos from being combined
2166 into the address of a MEM, so only prevent the combination if
2167 i1 or i2 set the same MEM. */
2177 /* This is the same test done in can_combine_p except we can't test
2178 all_adjacent; we don't have to, since this instruction will stay
2179 in place, thus we are not considering increasing the lifetime of
2180 INNER_DEST.
2182 Also, if this insn sets a function argument, combining it with
2183 something that might need a spill could clobber a previous
2184 function argument; the all_adjacent test in can_combine_p also
2185 checks this; here, we do a more specific test for this case. */
2195 /* If DEST is used in I3, it is being killed in this insn, so
2196 record that for later. We have to consider paradoxical
2197 subregs here, since they kill the whole register, but we
2198 ignore partial subregs, STRICT_LOW_PART, etc.
2199 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2200 STACK_POINTER_REGNUM, since these are always considered to be
2201 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2211 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2217 {
2222 }
2223 }
2226 {
2233 }
2236 }
2237 \f
2238 /* Return 1 if X is an arithmetic expression that contains a multiplication
2239 and division. We don't count multiplications by powers of two here. */
2241 static int
2243 {
2245 {
2261 }
2262 }
2263 \f
2264 /* Determine whether INSN can be used in a combination. Return nonzero if
2265 not. This is used in try_combine to detect early some cases where we
2266 can't perform combinations. */
2268 static int
2270 {
2271 rtx set;
2274 /* If this isn't really an insn, we can't do anything.
2275 This can occur when flow deletes an insn that it has merged into an
2276 auto-increment address. */
2280 /* Never combine loads and stores involving hard regs that are likely
2281 to be spilled. The register allocator can usually handle such
2282 reg-reg moves by tying. If we allow the combiner to make
2283 substitutions of likely-spilled regs, reload might die.
2284 As an exception, we allow combinations involving fixed regs; these are
2285 not available to the register allocator so there's no risk involved. */
2306 }
2308 struct likely_spilled_retval_info
2309 {
2312 };
2314 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2315 hard registers that are known to be written to / clobbered in full. */
2316 static void
2318 {
2335 else
2338 }
2340 /* Return nonzero iff part of the return value is live during INSN, and
2341 it is likely spilled. This can happen when more than one insn is needed
2342 to copy the return value, e.g. when we consider to combine into the
2343 second copy insn for a complex value. */
2345 static int
2347 {
2349 rtx reg;
2352 /* We assume here that no machine mode needs more than
2353 32 hard registers when the value overlaps with a register
2354 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2369 /* Disregard parts of the return value that are set later. */
2378 /* Check if any of the (probably) live return value registers is
2379 likely spilled. */
2380 nregs --;
2381 do
2382 {
2388 }
2390 /* Adjust INSN after we made a change to its destination.
2392 Changing the destination can invalidate notes that say something about
2393 the results of the insn and a LOG_LINK pointing to the insn. */
2395 static void
2397 {
2398 /* For notes, be conservative and simply remove them. */
2401 /* The new insn will have a destination that was previously the destination
2402 of an insn just above it. Call distribute_links to make a LOG_LINK from
2403 the next use of that destination. */
2419 }
2421 /* Return TRUE if combine can reuse reg X in mode MODE.
2422 ADDED_SETS is nonzero if the original set is still required. */
2423 static bool
2425 {
2432 /* Allow hard registers if the new mode is legal, and occupies no more
2433 registers than the old mode. */
2438 /* Or a pseudo that is only used once. */
2441 && !added_sets
2443 }
2446 /* Check whether X, the destination of a set, refers to part of
2447 the register specified by REG. */
2449 static bool
2451 {
2452 /* Check that reg is an integer mode register. */
2463 }
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2470 static void
2472 {
2480 {
2485 /* Remove barriers from the footer if there are any. */
2488 {
2491 else
2495 }
2498 }
2499 }
2501 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2502 by an arbitrary number of CLOBBERs. */
2503 static bool
2505 {
2524 }
2526 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2527 CLOBBERs), can be split into individual SETs in that order, without
2528 changing semantics. */
2529 static bool
2531 {
2539 {
2548 }
2551 }
2553 /* Try to combine the insns I0, I1 and I2 into I3.
2554 Here I0, I1 and I2 appear earlier than I3.
2555 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2556 I3.
2558 If we are combining more than two insns and the resulting insn is not
2559 recognized, try splitting it into two insns. If that happens, I2 and I3
2560 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2561 Otherwise, I0, I1 and I2 are pseudo-deleted.
2563 Return 0 if the combination does not work. Then nothing is changed.
2564 If we did the combination, return the insn at which combine should
2565 resume scanning.
2567 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2568 new direct jump instruction.
2570 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2571 been I3 passed to an earlier try_combine within the same basic
2572 block. */
2577 {
2578 /* New patterns for I3 and I2, respectively. */
2582 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2583 dead. */
2585 /* Total number of SETs to put into I3. */
2587 /* Nonzero if I2's or I1's body now appears in I3. */
2589 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2591 /* Contains I3 if the destination of I3 is used in its source, which means
2592 that the old life of I3 is being killed. If that usage is placed into
2593 I2 and not in I3, a REG_DEAD note must be made. */
2595 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2597 /* Copy of SET_SRC of I1 and I0, if needed. */
2599 /* Set if I2DEST was reused as a scratch register. */
2601 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2603 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2608 /* Notes that must be added to REG_NOTES in I3 and I2. */
2610 /* Notes that we substituted I3 into I2 instead of the normal case. */
2612 /* Notes that I1, I2 or I3 is a MULT operation. */
2619 rtx temp_expr;
2622 rtx new_other_notes;
2625 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2626 never be). */
2630 /* Only try four-insn combinations when there's high likelihood of
2631 success. Look for simple insns, such as loads of constants or
2632 binary operations involving a constant. */
2634 {
2644 {
2647 rtx src;
2652 {
2655 }
2657 ngood++;
2660 nshift++;
2661 }
2663 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2664 are likely manipulating its value. Ideally we'll be able to combine
2665 all four insns into a bitfield insertion of some kind.
2667 Note the source in I0 might be inside a sign/zero extension and the
2668 memory modes in I0 and I3 might be different. So extract the address
2669 from the destination of I3 and search for it in the source of I0.
2671 In the event that there's a match but the source/dest do not actually
2672 refer to the same memory, the worst that happens is we try some
2673 combinations that we wouldn't have otherwise. */
2675 /* Ensure the source of SET0 is a MEM, possibly buried inside
2676 an extension. */
2682 /* Ensure the destination of SET3 is a MEM. */
2684 /* Would it be better to extract the base address for the MEM
2685 in SET3 and look for that? I don't have cases where it matters
2686 but I could envision such cases. */
2692 }
2694 /* Exit early if one of the insns involved can't be used for
2695 combinations. */
2706 combine_attempts++;
2709 /* Reset the hard register usage information. */
2713 {
2720 else
2723 }
2725 /* If multiple insns feed into one of I2 or I3, they can be in any
2726 order. To simplify the code below, reorder them in sequence. */
2736 /* First check for one important special case that the code below will
2737 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2738 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2739 we may be able to replace that destination with the destination of I3.
2740 This occurs in the common code where we compute both a quotient and
2741 remainder into a structure, in which case we want to do the computation
2742 directly into the structure to avoid register-register copies.
2744 Note that this case handles both multiple sets in I2 and also cases
2745 where I2 has a number of CLOBBERs inside the PARALLEL.
2747 We make very conservative checks below and only try to handle the
2748 most common cases of this. For example, we only handle the case
2749 where I2 and I3 are adjacent to avoid making difficult register
2750 usage tests. */
2758 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2759 below would need to check what is inside (and reg_overlap_mentioned_p
2760 doesn't support those codes anyway). Don't allow those destinations;
2761 the resulting insn isn't likely to be recognized anyway. */
2767 {
2770 /* Make sure that the destination of I3,
2771 which we are going to substitute into one output of I2,
2772 is not used within another output of I2. We must avoid making this:
2773 (parallel [(set (mem (reg 69)) ...)
2774 (set (reg 69) ...)])
2775 which is not well-defined as to order of actions.
2776 (Besides, reload can't handle output reloads for this.)
2778 The problem can also happen if the dest of I3 is a memory ref,
2779 if another dest in I2 is an indirect memory ref. */
2787 /* Make sure this PARALLEL is not an asm. We do not allow combining
2788 that usually (see can_combine_p), so do not here either. */
2798 {
2799 combine_merges++;
2809 /* Replace the dest in I2 with our dest and make the resulting
2810 insn the new pattern for I3. Then skip to where we validate
2811 the pattern. Everything was set up above. */
2816 }
2817 }
2819 /* If I2 is setting a pseudo to a constant and I3 is setting some
2820 sub-part of it to another constant, merge them by making a new
2821 constant. */
2828 {
2834 {
2837 {
2843 }
2844 }
2845 else
2846 {
2851 }
2854 {
2855 /* If this is the low part, we're done. */
2857 ;
2858 /* Handle the case where inner is twice the size of outer. */
2862 /* Otherwise give up for now. */
2863 else
2865 }
2868 {
2872 wide_int o
2877 combine_merges++;
2884 /* Replace the source in I2 with the new constant and make the
2885 resulting insn the new pattern for I3. Then skip to where we
2886 validate the pattern. Everything was set up above. */
2892 /* The dest of I3 has been replaced with the dest of I2. */
2895 }
2896 }
2898 /* If we have no I1 and I2 looks like:
2899 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2900 (set Y OP)])
2901 make up a dummy I1 that is
2902 (set Y OP)
2903 and change I2 to be
2904 (set (reg:CC X) (compare:CC Y (const_int 0)))
2906 (We can ignore any trailing CLOBBERs.)
2908 This undoes a previous combination and allows us to match a branch-and-
2909 decrement insn. */
2921 {
2922 /* We make I1 with the same INSN_UID as I2. This gives it
2923 the same DF_INSN_LUID for value tracking. Our fake I1 will
2924 never appear in the insn stream so giving it the same INSN_UID
2925 as I2 will not cause a problem. */
2938 }
2940 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2941 make those two SETs separate I1 and I2 insns, and make an I0 that is
2942 the original I1. */
2948 {
2949 /* If there is no I1, there is no I0 either. */
2952 /* We make I1 with the same INSN_UID as I2. This gives it
2953 the same DF_INSN_LUID for value tracking. Our fake I1 will
2954 never appear in the insn stream so giving it the same INSN_UID
2955 as I2 will not cause a problem. */
2963 }
2965 /* Verify that I2 and I1 are valid for combining. */
2971 {
2974 }
2976 /* Record whether I2DEST is used in I2SRC and similarly for the other
2977 cases. Knowing this will help in register status updating below. */
2988 /* For the earlier insns, determine which of the subsequent ones they
2989 feed. */
2996 /* Ensure that I3's pattern can be the destination of combines. */
3002 {
3005 }
3007 /* See if any of the insns is a MULT operation. Unless one is, we will
3008 reject a combination that is, since it must be slower. Be conservative
3009 here. */
3017 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3018 We used to do this EXCEPT in one case: I3 has a post-inc in an
3019 output operand. However, that exception can give rise to insns like
3020 mov r3,(r3)+
3021 which is a famous insn on the PDP-11 where the value of r3 used as the
3022 source was model-dependent. Avoid this sort of thing. */
3024 #if 0
3030 /* It's not the exception. */
3031 #endif
3033 {
3034 rtx link;
3040 {
3043 }
3044 }
3046 /* See if the SETs in I1 or I2 need to be kept around in the merged
3047 instruction: whenever the value set there is still needed past I3.
3048 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3050 For the SET in I1, we have two cases: if I1 and I2 independently feed
3051 into I3, the set in I1 needs to be kept around unless I1DEST dies
3052 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3053 in I1 needs to be kept around unless I1DEST dies or is set in either
3054 I2 or I3. The same considerations apply to I0. */
3061 else
3069 else
3072 /* We are about to copy insns for the case where they need to be kept
3073 around. Check that they can be copied in the merged instruction. */
3079 {
3082 }
3084 /* If the set in I2 needs to be kept around, we must make a copy of
3085 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3086 PATTERN (I2), we are only substituting for the original I1DEST, not into
3087 an already-substituted copy. This also prevents making self-referential
3088 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3089 I2DEST. */
3092 {
3095 else
3097 }
3100 {
3103 else
3105 }
3108 {
3111 else
3113 }
3115 combine_merges++;
3117 /* Substitute in the latest insn for the regs set by the earlier ones. */
3123 /* Many machines that don't use CC0 have insns that can both perform an
3124 arithmetic operation and set the condition code. These operations will
3125 be represented as a PARALLEL with the first element of the vector
3126 being a COMPARE of an arithmetic operation with the constant zero.
3127 The second element of the vector will set some pseudo to the result
3128 of the same arithmetic operation. If we simplify the COMPARE, we won't
3129 match such a pattern and so will generate an extra insn. Here we test
3130 for this case, where both the comparison and the operation result are
3131 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3132 I2SRC. Later we will make the PARALLEL that contains I2. */
3138 {
3139 rtx newpat_dest;
3153 {
3158 }
3160 /* Do the rest only if op1 is const0_rtx, which may be the
3161 result of simplification. */
3163 {
3164 /* If a single use of the CC is found, prepare to modify it
3165 when SELECT_CC_MODE returns a new CC-class mode, or when
3166 the above simplify_compare_const() returned a new comparison
3167 operator. undobuf.other_insn is assigned the CC use insn
3168 when modifying it. */
3170 {
3171 #ifdef SELECT_CC_MODE
3172 machine_mode new_mode
3177 {
3182 else
3183 {
3186 }
3187 }
3188 #endif
3189 /* Cases for modifying the CC-using comparison. */
3191 /* ??? Do we need to verify the zero rtx? */
3193 {
3194 /* Replace cc_use_loc with entire new RTX. */
3199 }
3201 {
3202 /* Just replace the CC reg with a new mode. */
3205 }
3206 }
3208 /* Now we modify the current newpat:
3209 First, SET_DEST(newpat) is updated if the CC mode has been
3210 altered. For targets without SELECT_CC_MODE, this should be
3211 optimized away. */
3214 /* This is always done to propagate i2src into newpat. */
3217 /* Create new version of i2pat if needed; the below PARALLEL
3218 creation needs this to work correctly. */
3222 }
3223 }
3226 {
3227 /* It is possible that the source of I2 or I1 may be performing
3228 an unneeded operation, such as a ZERO_EXTEND of something
3229 that is known to have the high part zero. Handle that case
3230 by letting subst look at the inner insns.
3232 Another way to do this would be to have a function that tries
3233 to simplify a single insn instead of merging two or more
3234 insns. We don't do this because of the potential of infinite
3235 loops and because of the potential extra memory required.
3236 However, doing it the way we are is a bit of a kludge and
3237 doesn't catch all cases.
3239 But only do this if -fexpensive-optimizations since it slows
3240 things down and doesn't usually win.
3242 This is not done in the COMPARE case above because the
3243 unmodified I2PAT is used in the PARALLEL and so a pattern
3244 with a modified I2SRC would not match. */
3247 {
3248 /* Pass pc_rtx so no substitutions are done, just
3249 simplifications. */
3251 {
3254 }
3258 }
3263 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3264 copy of I2SRC each time we substitute it, in order to avoid creating
3265 self-referential RTL when we will be substituting I1SRC for I1DEST
3266 later. Likewise if I0 feeds into I2, either directly or indirectly
3267 through I1, and I0DEST is in I0SRC. */
3274 /* Record whether I2's body now appears within I3's body. */
3276 }
3278 /* If we already got a failure, don't try to do more. Otherwise, try to
3279 substitute I1 if we have it. */
3282 {
3283 /* Check that an autoincrement side-effect on I1 has not been lost.
3284 This happens if I1DEST is mentioned in I2 and dies there, and
3285 has disappeared from the new pattern. */
3287 && i1_feeds_i2_n
3290 /* Before we can do this substitution, we must redo the test done
3291 above (see detailed comments there) that ensures I1DEST isn't
3292 mentioned in any SETs in NEWPAT that are field assignments. */
3295 {
3298 }
3303 /* If the following substitution will modify I1SRC, make a copy of it
3304 for the case where it is substituted for I1DEST in I2PAT later. */
3308 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3309 copy of I1SRC each time we substitute it, in order to avoid creating
3310 self-referential RTL when we will be substituting I0SRC for I0DEST
3311 later. */
3316 /* Record whether I1's body now appears within I3's body. */
3318 }
3320 /* Likewise for I0 if we have it. */
3323 {
3330 {
3333 }
3335 /* If the following substitution will modify I0SRC, make a copy of it
3336 for the case where it is substituted for I0DEST in I1PAT later. */
3339 /* And a copy for I0DEST in I2PAT substitution. */
3348 }
3350 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3351 to count all the ways that I2SRC and I1SRC can be used. */
3362 /* Fail if we tried to make a new register. */
3364 /* Fail if we couldn't do something and have a CLOBBER. */
3366 /* Fail if this new pattern is a MULT and we didn't have one before
3367 at the outer level. */
3370 {
3373 }
3375 /* If the actions of the earlier insns must be kept
3376 in addition to substituting them into the latest one,
3377 we must make a new PARALLEL for the latest insn
3378 to hold additional the SETs. */
3381 {
3383 combine_extras++;
3386 {
3392 }
3393 else
3394 {
3399 }
3405 {
3411 }
3413 {
3422 }
3423 }
3425 validate_replacement:
3427 /* Note which hard regs this insn has as inputs. */
3430 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3431 consider splitting this pattern, we might need these clobbers. */
3434 {
3440 }
3442 /* We have recognized nothing yet. */
3445 /* See if this is a PARALLEL of two SETs where one SET's destination is
3446 a register that is unused and this isn't marked as an instruction that
3447 might trap in an EH region. In that case, we just need the other SET.
3448 We prefer this over the PARALLEL.
3450 This can occur when simplifying a divmod insn. We *must* test for this
3451 case here because the code below that splits two independent SETs doesn't
3452 handle this case correctly when it updates the register status.
3454 It's pointless doing this if we originally had two sets, one from
3455 i3, and one from i2. Combining then splitting the parallel results
3456 in the original i2 again plus an invalid insn (which we delete).
3457 The net effect is only to move instructions around, which makes
3458 debug info less accurate. */
3463 {
3474 {
3477 }
3486 {
3492 }
3496 }
3498 /* Is the result of combination a valid instruction? */
3502 /* If we were combining three insns and the result is a simple SET
3503 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3504 insns. There are two ways to do this. It can be split using a
3505 machine-specific method (like when you have an addition of a large
3506 constant) or by combine in the function find_split_point. */
3510 {
3514 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3515 use I2DEST as a scratch register will help. In the latter case,
3516 convert I2DEST to the mode of the source of NEWPAT if we can. */
3520 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3521 inputs of NEWPAT. */
3523 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3524 possible to try that as a scratch reg. This would require adding
3525 more code to make it work though. */
3528 {
3531 /* First try to split using the original register as a
3532 scratch register. */
3536 i2dest)));
3539 /* If that didn't work, try changing the mode of I2DEST if
3540 we can. */
3545 {
3547 rtx ni2dest;
3551 else
3552 {
3555 }
3557 parallel = (gen_rtx_PARALLEL
3561 ni2dest))));
3566 {
3574 }
3575 }
3578 }
3580 /* If recog_for_combine has discarded clobbers, try to use them
3581 again for the split. */
3583 {
3586 }
3589 {
3594 }
3598 {
3608 /* If I2 or I3 has multiple SETs, we won't know how to track
3609 register status, so don't use these insns. If I2's destination
3610 is used between I2 and I3, we also can't use these insns. */
3620 /* It is possible that both insns now set the destination of I3.
3621 If so, we must show an extra use of it. */
3624 {
3643 }
3644 }
3646 /* If we can split it and use I2DEST, go ahead and see if that
3647 helps things be recognized. Verify that none of the registers
3648 are set between I2 and I3. */
3652 /* We need I2DEST in the proper mode. If it is a hard register
3653 or the only use of a pseudo, we can change its mode.
3654 Make sure we don't change a hard register to have a mode that
3655 isn't valid for it, or change the number of registers. */
3662 /* We can't overwrite I2DEST if its value is still used by
3663 NEWPAT. */
3665 {
3674 /* *SPLIT may be part of I2SRC, so make sure we have the
3675 original expression around for later debug processing.
3676 We should not need I2SRC any more in other cases. */
3679 else
3682 /* Get NEWDEST as a register in the proper mode. We have already
3683 validated that we can do this. */
3685 {
3688 else
3689 {
3692 }
3693 }
3695 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3696 an ASHIFT. This can occur if it was inside a PLUS and hence
3697 appeared to be a memory address. This is a kludge. */
3702 {
3705 /* Update split_code because we may not have a multiply
3706 anymore. */
3708 }
3710 /* Similarly for (plus (mult FOO (const_int pow2))). */
3716 {
3720 /* Update split_code because we may not have a multiply
3721 anymore. */
3723 }
3725 #ifdef INSN_SCHEDULING
3726 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3727 be written as a ZERO_EXTEND. */
3729 {
3730 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3731 what it really is. */
3736 else
3739 }
3740 #endif
3742 /* Attempt to split binary operators using arithmetic identities. */
3746 {
3753 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3755 {
3760 }
3761 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3768 {
3774 /* Split both "((X op Y) op X) op Y" and
3775 "((X op Y) op Y) op X" as "T op T" where T is
3776 "X op Y". */
3779 {
3784 }
3785 /* Split "((X op X) op Y) op Y)" as "T op T" where
3786 T is "X op Y". */
3788 {
3794 }
3795 }
3796 }
3799 {
3802 }
3806 /* recog_for_combine might have added CLOBBERs to newi2pat.
3807 Make sure NEWPAT does not depend on the clobbered regs. */
3811 {
3814 {
3817 }
3818 }
3820 /* If the split point was a MULT and we didn't have one before,
3821 don't use one now. */
3824 }
3825 }
3827 /* Check for a case where we loaded from memory in a narrow mode and
3828 then sign extended it, but we need both registers. In that case,
3829 we have a PARALLEL with both loads from the same memory location.
3830 We can split this into a load from memory followed by a register-register
3831 copy. This saves at least one insn, more if register allocation can
3832 eliminate the copy.
3834 We cannot do this if the destination of the first assignment is a
3835 condition code register or cc0. We eliminate this case by making sure
3836 the SET_DEST and SET_SRC have the same mode.
3838 We cannot do this if the destination of the second assignment is
3839 a register that we have already assumed is zero-extended. Similarly
3840 for a SUBREG of such a register. */
3875 {
3876 rtx ni2dest;
3890 }
3892 /* Similarly, check for a case where we have a PARALLEL of two independent
3893 SETs but we started with three insns. In this case, we can do the sets
3894 as two separate insns. This case occurs when some SET allows two
3895 other insns to combine, but the destination of that SET is still live.
3897 Also do this if we started with two insns and (at least) one of the
3898 resulting sets is a noop; this noop will be deleted later. */
3917 {
3921 /* Normally, it doesn't matter which of the two is done first,
3922 but the one that references cc0 can't be the second, and
3923 one which uses any regs/memory set in between i2 and i3 can't
3924 be first. The PARALLEL might also have been pre-existing in i3,
3925 so we need to make sure that we won't wrongly hoist a SET to i2
3926 that would conflict with a death note present in there. */
3934 /* If I3 is a jump, ensure that set0 is a jump so that
3935 we do not create invalid RTL. */
3937 )
3938 {
3941 }
3949 /* If I3 is a jump, ensure that set1 is a jump so that
3950 we do not create invalid RTL. */
3952 )
3953 {
3956 }
3957 else
3958 {
3961 }
3966 {
3967 /* recog_for_combine might have added CLOBBERs to newi2pat.
3968 Make sure NEWPAT does not depend on the clobbered regs. */
3970 {
3973 {
3976 {
3979 }
3980 }
3981 }
3984 }
3985 }
3987 /* If it still isn't recognized, fail and change things back the way they
3988 were. */
3990 /* Is the result a reasonable ASM_OPERANDS? */
3992 {
3995 }
3997 /* If we had to change another insn, make sure it is valid also. */
3999 {
4007 {
4010 }
4011 }
4013 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4014 they are adjacent to each other or not. */
4016 {
4020 {
4023 }
4024 }
4026 /* Only allow this combination if insn_rtx_costs reports that the
4027 replacement instructions are cheaper than the originals. */
4029 {
4032 }
4035 {
4040 {
4045 /* Temporarily revert mode back. */
4049 {
4050 /* If we used i2dest as a scratch register with a
4051 different mode, substitute it for the original
4052 i2src while its original mode is temporarily
4053 restored, and then clear i2scratch so that we don't
4054 do it again later. */
4056 this_basic_block);
4058 /* Put back the new mode. */
4060 }
4061 else
4062 {
4067 {
4070 }
4071 else
4072 {
4079 }
4081 /* We're dealing with a reg that changed mode but not
4082 meaning, so we want to turn it into a subreg for
4083 the new mode. However, because of REG sharing and
4084 because its mode had already changed, we have to do
4085 it in two steps. First, replace any debug uses of
4086 reg, with its original mode temporarily restored,
4087 with this copy we have created; then, replace the
4088 copy with the SUBREG of the original shared reg,
4089 once again changed to the new mode. */
4091 this_basic_block);
4095 this_basic_block);
4096 }
4097 }
4098 }
4100 /* If we will be able to accept this, we have made a
4101 change to the destination of I3. This requires us to
4102 do a few adjustments. */
4105 {
4108 }
4110 /* We now know that we can do this combination. Merge the insns and
4111 update the status of registers and LOG_LINKS. */
4114 {
4119 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4120 ensure that they are still valid. Then add any non-duplicate
4121 notes added by recog_for_combine. */
4123 {
4133 }
4137 NULL_RTX);
4138 }
4141 {
4144 rtx ni2dest;
4146 /* I3 now uses what used to be its destination and which is now
4147 I2's destination. This requires us to do a few adjustments. */
4151 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4152 so we still will.
4154 However, some later insn might be using I2's dest and have
4155 a LOG_LINK pointing at I3. We must remove this link.
4156 The simplest way to remove the link is to point it at I1,
4157 which we know will be a NOTE. */
4159 /* newi2pat is usually a SET here; however, recog_for_combine might
4160 have added some clobbers. */
4163 else
4170 {
4172 {
4178 }
4179 }
4180 }
4182 {
4187 /* Compute which registers we expect to eliminate. newi2pat may be setting
4188 either i3dest or i2dest, so we must check it. */
4191 || !i2dest_killed
4193 /* For i1, we need to compute both local elimination and global
4194 elimination information with respect to newi2pat because i1dest
4195 may be the same as i3dest, in which case newi2pat may be setting
4196 i1dest. Global information is used when distributing REG_DEAD
4197 note for i2 and i3, in which case it does matter if newi2pat sets
4198 i1dest or not.
4200 Local information is used when distributing REG_DEAD note for i1,
4201 in which case it doesn't matter if newi2pat sets i1dest or not.
4202 See PR62151, if we have four insns combination:
4203 i0: r0 <- i0src
4204 i1: r1 <- i1src (using r0)
4205 REG_DEAD (r0)
4206 i2: r0 <- i2src (using r1)
4207 i3: r3 <- i3src (using r0)
4208 ix: using r0
4209 From i1's point of view, r0 is eliminated, no matter if it is set
4210 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4211 should be discarded.
4213 Note local information only affects cases in forms like "I1->I2->I3",
4214 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4215 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4216 i0dest anyway. */
4218 || !i1dest_killed
4223 /* Same case as i1. */
4230 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4231 clear them. */
4239 /* Ensure that we do not have something that should not be shared but
4240 occurs multiple times in the new insns. Check this by first
4241 resetting all the `used' flags and then copying anything is shared. */
4265 {
4272 {
4273 /* I2SRC must still be meaningful at this point. Some splitting
4274 operations can invalidate I2SRC, but those operations do not
4275 apply to calls. */
4278 }
4286 }
4291 /* We had one special case above where I2 had more than one set and
4292 we replaced a destination of one of those sets with the destination
4293 of I3. In that case, we have to update LOG_LINKS of insns later
4294 in this basic block. Note that this (expensive) case is rare.
4296 Also, in this case, we must pretend that all REG_NOTEs for I2
4297 actually came from I3, so that REG_UNUSED notes from I2 will be
4298 properly handled. */
4301 {
4310 temp_insn
4320 {
4325 }
4326 else
4329 }
4337 {
4340 this_basic_block);
4343 }
4344 else
4345 {
4348 this_basic_block);
4350 }
4353 {
4358 this_basic_block);
4360 }
4363 {
4368 this_basic_block);
4370 }
4372 /* Get death notes for everything that is now used in either I3 or
4373 I2 and used to die in a previous insn. If we built two new
4374 patterns, move from I1 to I2 then I2 to I3 so that we get the
4375 proper movement on registers that I2 modifies. */
4381 else
4387 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4404 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4405 know these are REG_UNUSED and want them to go to the desired insn,
4406 so we always pass it as i3. */
4410 NULL_RTX);
4414 NULL_RTX);
4416 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4417 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4418 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4419 in that case, it might delete I2. Similarly for I2 and I1.
4420 Show an additional death due to the REG_DEAD note we make here. If
4421 we discard it in distribute_notes, we will decrement it again. */
4424 {
4429 else
4432 }
4435 {
4440 else
4443 }
4446 {
4451 else
4454 }
4457 {
4462 else
4465 }
4473 {
4478 /* The insn that used to set this register doesn't exist, and
4479 this life of the register may not exist either. See if one of
4480 I3's links points to an insn that sets I2DEST. If it does,
4481 that is now the last known value for I2DEST. If we don't update
4482 this and I2 set the register to a value that depended on its old
4483 contents, we will get confused. If this insn is used, thing
4484 will be set correctly in combine_instructions. */
4492 /* If the reg formerly set in I2 died only once and that was in I3,
4493 zero its use count so it won't make `reload' do any work. */
4496 && ! i2dest_in_i2src
4499 }
4502 {
4515 && ! i1dest_in_i1src
4518 }
4521 {
4534 && ! i0dest_in_i0src
4537 }
4539 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4540 been made to this insn. The order is important, because newi2pat
4541 can affect nonzero_bits of newpat. */
4545 }
4548 {
4550 {
4553 }
4555 }
4558 {
4560 {
4563 }
4565 }
4568 {
4570 {
4573 }
4575 }
4578 {
4580 {
4583 }
4585 }
4588 {
4590 {
4593 }
4595 }
4597 /* Set new_direct_jump_p if a new return or simple jump instruction
4598 has been created. Adjust the CFG accordingly. */
4600 {
4604 }
4609 {
4612 }
4614 /* A noop might also need cleaning up of CFG, if it comes from the
4615 simplification of a jump. */
4620 {
4623 }
4630 {
4633 }
4635 combine_successes++;
4642 else
4644 }
4645 \f
4646 /* Get a marker for undoing to the current state. */
4650 {
4652 }
4654 /* Undo the modifications up to the marker. */
4656 static void
4658 {
4662 {
4667 {
4682 }
4686 }
4689 }
4691 /* Undo all the modifications recorded in undobuf. */
4693 static void
4695 {
4697 }
4699 /* We've committed to accepting the changes we made. Move all
4700 of the undos to the free list. */
4702 static void
4704 {
4708 {
4712 }
4714 }
4715 \f
4716 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4717 where we have an arithmetic expression and return that point. LOC will
4718 be inside INSN.
4720 try_combine will call this function to see if an insn can be split into
4721 two insns. */
4725 {
4734 /* First special-case some codes. */
4736 {
4738 #ifdef INSN_SCHEDULING
4739 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4740 point. */
4743 #endif
4747 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4748 using LO_SUM and HIGH. */
4751 {
4759 }
4761 /* If we have a PLUS whose second operand is a constant and the
4762 address is not valid, perhaps will can split it up using
4763 the machine-specific way to split large constants. We use
4764 the first pseudo-reg (one of the virtual regs) as a placeholder;
4765 it will not remain in the result. */
4770 {
4773 subst_insn);
4775 /* This should have produced two insns, each of which sets our
4776 placeholder. If the source of the second is a valid address,
4777 we can make put both sources together and make a split point
4778 in the middle. */
4791 && memory_address_addr_space_p
4794 {
4798 /* Replace the placeholder in SRC2 with SRC1. If we can
4799 find where in SRC2 it was placed, that can become our
4800 split point and we can replace this address with SRC2.
4801 Just try two obvious places. */
4812 {
4815 }
4816 }
4818 /* If that didn't work, perhaps the first operand is complex and
4819 needs to be computed separately, so make a split point there.
4820 This will occur on machines that just support REG + CONST
4821 and have a constant moved through some previous computation. */
4827 }
4829 /* If we have a PLUS whose first operand is complex, try computing it
4830 separately by making a split there. */
4841 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4842 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4843 we need to put the operand into a register. So split at that
4844 point. */
4854 /* See if we can split SET_SRC as it stands. */
4859 /* See if we can split SET_DEST as it stands. */
4864 /* See if this is a bitfield assignment with everything constant. If
4865 so, this is an IOR of an AND, so split it into that. */
4875 {
4881 unsigned HOST_WIDE_INT mask
4883 rtx or_mask;
4892 else
4893 {
4899 or_mask));
4900 }
4907 }
4909 /* Otherwise, see if this is an operation that we can split into two.
4910 If so, try to split that. */
4914 {
4916 /* If we are AND'ing with a large constant that is only a single
4917 bit and the result is only being used in a context where we
4918 need to know if it is zero or nonzero, replace it with a bit
4919 extraction. This will avoid the large constant, which might
4920 have taken more than one insn to make. If the constant were
4921 not a valid argument to the AND but took only one insn to make,
4922 this is no worse, but if it took more than one insn, it will
4923 be better. */
4933 {
4938 {
4941 }
4942 }
4946 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4947 is known to be on, this can be converted into a NEG of a shift. */
4953 {
4965 }
4971 /* We can't optimize if either mode is a partial integer
4972 mode as we don't know how many bits are significant
4973 in those modes. */
4987 {
4995 }
5000 }
5004 {
5007 /* For unsigned, we have a choice of a shift followed by an
5008 AND or two shifts. Use two shifts for field sizes where the
5009 constant might be too large. We assume here that we can
5010 always at least get 8-bit constants in an AND insn, which is
5011 true for every current RISC. */
5014 {
5015 unsigned HOST_WIDE_INT mask
5019 gen_rtx_LSHIFTRT
5027 }
5028 else
5029 {
5031 gen_rtx_fmt_ee
5042 }
5043 }
5045 /* See if this is a simple operation with a constant as the second
5046 operand. It might be that this constant is out of range and hence
5047 could be used as a split point. */
5055 /* Finally, see if this is a simple operation with its first operand
5056 not in a register. The operation might require this operand in a
5057 register, so return it as a split point. We can always do this
5058 because if the first operand were another operation, we would have
5059 already found it as a split point. */
5068 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5069 it is better to write this as (not (ior A B)) so we can split it.
5070 Similarly for IOR. */
5072 {
5080 }
5082 /* Many RISC machines have a large set of logical insns. If the
5083 second operand is a NOT, put it first so we will try to split the
5084 other operand first. */
5086 {
5090 }
5095 /* Canonicalization can produce (minus A (mult B C)), where C is a
5096 constant. It may be better to try splitting (plus (mult B -C) A)
5097 instead if this isn't a multiply by a power of two. */
5101 {
5109 mode)),
5112 }
5114 /* Split at a multiply-accumulate instruction. However if this is
5115 the SET_SRC, we likely do not have such an instruction and it's
5116 worthless to try this split. */
5125 }
5127 /* Otherwise, select our actions depending on our rtx class. */
5129 {
5135 /* fall through */
5143 /* fall through */
5145 /* Some machines have (and (shift ...) ...) insns. If X is not
5146 an AND, but XEXP (X, 0) is, use it as our split point. */
5156 /* Otherwise, we don't have a split point. */
5158 }
5159 }
5160 \f
5161 /* Throughout X, replace FROM with TO, and return the result.
5162 The result is TO if X is FROM;
5163 otherwise the result is X, but its contents may have been modified.
5164 If they were modified, a record was made in undobuf so that
5165 undo_all will (among other things) return X to its original state.
5167 If the number of changes necessary is too much to record to undo,
5168 the excess changes are not made, so the result is invalid.
5169 The changes already made can still be undone.
5170 undobuf.num_undo is incremented for such changes, so by testing that
5171 the caller can tell whether the result is valid.
5173 `n_occurrences' is incremented each time FROM is replaced.
5175 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5177 IN_COND is nonzero if we are at the top level of a condition.
5179 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5180 by copying if `n_occurrences' is nonzero. */
5182 static rtx
5184 {
5189 rtx new_rtx;
5191 /* Two expressions are equal if they are identical copies of a shared
5192 RTX or if they are both registers with the same register number
5193 and mode. */
5195 #define COMBINE_RTX_EQUAL_P(X,Y) \
5196 ((X) == (Y) \
5197 || (REG_P (X) && REG_P (Y) \
5198 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5200 /* Do not substitute into clobbers of regs -- this will never result in
5201 valid RTL. */
5206 {
5207 n_occurrences++;
5209 }
5211 /* If X and FROM are the same register but different modes, they
5212 will not have been seen as equal above. However, the log links code
5213 will make a LOG_LINKS entry for that case. If we do nothing, we
5214 will try to rerecognize our original insn and, when it succeeds,
5215 we will delete the feeding insn, which is incorrect.
5217 So force this insn not to match in this (rare) case. */
5222 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5223 of which may contain things that can be combined. */
5227 /* It is possible to have a subexpression appear twice in the insn.
5228 Suppose that FROM is a register that appears within TO.
5229 Then, after that subexpression has been scanned once by `subst',
5230 the second time it is scanned, TO may be found. If we were
5231 to scan TO here, we would find FROM within it and create a
5232 self-referent rtl structure which is completely wrong. */
5236 /* Parallel asm_operands need special attention because all of the
5237 inputs are shared across the arms. Furthermore, unsharing the
5238 rtl results in recognition failures. Failure to handle this case
5239 specially can result in circular rtl.
5241 Solve this by doing a normal pass across the first entry of the
5242 parallel, and only processing the SET_DESTs of the subsequent
5243 entries. Ug. */
5248 {
5251 /* If this substitution failed, this whole thing fails. */
5259 {
5265 {
5268 /* If this substitution failed, this whole thing fails. */
5274 }
5275 }
5276 }
5277 else
5278 {
5282 /* We don't need to process a SET_DEST that is a register, CC0,
5283 or PC, so set up to skip this common case. All other cases
5284 where we want to suppress replacing something inside a
5285 SET_SRC are handled via the IN_DEST operand. */
5292 /* Trying to simplify the operands of a widening MULT is not likely
5293 to create RTL matching a machine insn. */
5305 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5306 constant. */
5311 {
5313 {
5316 {
5318 {
5321 n_occurrences++;
5322 }
5323 else
5324 {
5326 unique_copy);
5328 /* If this substitution failed, this whole thing
5329 fails. */
5333 }
5336 }
5337 }
5339 {
5340 /* If this is a register being set, ignore it. */
5347 ;
5350 {
5351 /* In general, don't install a subreg involving two
5352 modes not tieable. It can worsen register
5353 allocation, and can even make invalid reload
5354 insns, since the reg inside may need to be copied
5355 from in the outside mode, and that may be invalid
5356 if it is an fp reg copied in integer mode.
5358 We allow two exceptions to this: It is valid if
5359 it is inside another SUBREG and the mode of that
5360 SUBREG and the mode of the inside of TO is
5361 tieable and it is valid if X is a SET that copies
5362 FROM to CC0. */
5370 && (!HAVE_cc0
5385 n_occurrences++;
5386 }
5387 else
5388 /* If we are in a SET_DEST, suppress most cases unless we
5389 have gone inside a MEM, in which case we want to
5390 simplify the address. We assume here that things that
5391 are actually part of the destination have their inner
5392 parts in the first expression. This is true for SUBREG,
5393 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5394 things aside from REG and MEM that should appear in a
5395 SET_DEST. */
5397 (((in_dest
5403 unique_copy);
5405 /* If we found that we will have to reject this combination,
5406 indicate that by returning the CLOBBER ourselves, rather than
5407 an expression containing it. This will speed things up as
5408 well as prevent accidents where two CLOBBERs are considered
5409 to be equal, thus producing an incorrect simplification. */
5415 {
5423 }
5426 {
5430 }
5431 else
5433 }
5434 }
5435 }
5437 /* Check if we are loading something from the constant pool via float
5438 extension; in this case we would undo compress_float_constant
5439 optimization and degenerate constant load to an immediate value. */
5443 {
5447 }
5449 /* Try to simplify X. If the simplification changed the code, it is likely
5450 that further simplification will help, so loop, but limit the number
5451 of repetitions that will be performed. */
5454 {
5455 /* If X is sufficiently simple, don't bother trying to do anything
5456 with it. */
5465 /* We no longer know the original mode of operand 0 since we
5466 have changed the form of X) */
5468 }
5471 }
5472 \f
5473 /* Simplify X, a piece of RTL. We just operate on the expression at the
5474 outer level; call `subst' to simplify recursively. Return the new
5475 expression.
5477 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5478 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5479 of a condition. */
5481 static rtx
5484 {
5487 rtx temp;
5490 /* If this is a commutative operation, put a constant last and a complex
5491 expression first. We don't need to do this for comparisons here. */
5494 {
5498 }
5500 /* Try to fold this expression in case we have constants that weren't
5501 present before. */
5504 {
5512 {
5515 {
5519 }
5522 }
5535 }
5538 {
5543 }
5545 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5546 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5547 things. Check for cases where both arms are testing the same
5548 condition.
5550 Don't do anything if all operands are very simple. */
5563 {
5568 /* If everything is a comparison, what we have is highly unlikely
5569 to be simpler, so don't use it. */
5572 {
5579 /* Simplify the alternative arms; this may collapse the true and
5580 false arms to store-flag values. Be careful to use copy_rtx
5581 here since true_rtx or false_rtx might share RTL with x as a
5582 result of the if_then_else_cond call above. */
5586 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5587 is unlikely to be simpler. */
5590 {
5593 /* Restarting if we generate a store-flag expression will cause
5594 us to loop. Just drop through in this case. */
5596 /* If the result values are STORE_FLAG_VALUE and zero, we can
5597 just make the comparison operation. */
5608 /* Likewise, we can make the negate of a comparison operation
5609 if the result values are - STORE_FLAG_VALUE and zero. */
5617 mode);
5628 mode);
5629 else
5632 mode,
5633 VOIDmode,
5634 cond,
5635 cop1),
5640 }
5641 }
5642 }
5644 /* First see if we can apply the inverse distributive law. */
5647 {
5651 }
5653 /* If CODE is an associative operation not otherwise handled, see if we
5654 can associate some operands. This can win if they are constants or
5655 if they are logically related (i.e. (a & b) & a). */
5661 {
5663 {
5667 rtx inner;
5669 /* Make sure we pass the constant operand if any as the second
5670 one if this is a commutative operation. */
5678 /* For commutative operations, try the other pair if that one
5679 didn't simplify. */
5681 {
5686 }
5690 }
5691 }
5693 /* A little bit of algebraic simplification here. */
5695 {
5697 /* Ensure that our address has any ASHIFTs converted to MULT in case
5698 address-recognizing predicates are called later. */
5707 /* See if this can be moved to simplify_subreg. */
5710 /* Don't call gen_lowpart if the inner mode
5711 is VOIDmode and we cannot simplify it, as SUBREG without
5712 inner mode is invalid. */
5719 {
5720 rtx temp;
5726 /* If op is known to have all lower bits zero, the result is zero. */
5736 }
5738 /* Don't change the mode of the MEM if that would change the meaning
5739 of the address. */
5746 /* Note that we cannot do any narrowing for non-constants since
5747 we might have been counting on using the fact that some bits were
5748 zero. We now do this in the SET. */
5755 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5756 replaced by (lshiftrt X C). This will convert
5757 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5765 /* If X has only a single bit that might be nonzero, say, bit I, convert
5766 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5767 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5768 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5769 or a SUBREG of one since we'd be making the expression more
5770 complex if it was just a register. */
5776 {
5777 rtx temp1 = simplify_shift_const
5783 /* If all we did was surround TEMP with the two shifts, we
5784 haven't improved anything, so don't use it. Otherwise,
5785 we are better off with TEMP1. */
5790 }
5794 /* We can't handle truncation to a partial integer mode here
5795 because we don't know the real bitsize of the partial
5796 integer mode. */
5805 /* We can truncate a constant value and return it. */
5809 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5810 whose value is a comparison can be replaced with a subreg if
5811 STORE_FLAG_VALUE permits. */
5820 /* (const (const X)) can become (const X). Do it this way rather than
5821 returning the inner CONST since CONST can be shared with a
5822 REG_EQUAL note. */
5828 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5829 can add in an offset. find_split_point will split this address up
5830 again if it doesn't match. */
5837 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5838 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5839 bit-field and can be replaced by either a sign_extend or a
5840 sign_extract. The `and' may be a zero_extend and the two
5841 <c>, -<c> constants may be reversed. */
5856 return simplify_shift_const
5863 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5864 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5865 the bitsize of the mode - 1. This allows simplification of
5866 "a = (b & 8) == 0;" */
5878 /* If we are adding two things that have no bits in common, convert
5879 the addition into an IOR. This will often be further simplified,
5880 for example in cases like ((a & 1) + (a & 2)), which can
5881 become a & 3. */
5886 {
5887 /* Try to simplify the expression further. */
5891 /* If we could, great. If not, do not go ahead with the IOR
5892 replacement, since PLUS appears in many special purpose
5893 address arithmetic instructions. */
5901 }
5903 /* Canonicalize x + x into x << 1. */
5912 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5913 (and <foo> (const_int pow2-1)) */
5923 /* If we have (mult (plus A B) C), apply the distributive law and then
5924 the inverse distributive law to see if things simplify. This
5925 occurs mostly in addresses, often when unrolling loops. */
5928 {
5932 }
5934 /* Try simplify a*(b/c) as (a*b)/c. */
5937 {
5943 }
5947 /* If this is a divide by a power of two, treat it as a shift if
5948 its first operand is a shift. */
5966 /* If the first operand is a condition code, we can't do anything
5967 with it. */
5971 {
5979 /* Simplify our comparison, if possible. */
5982 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5983 if only the low-order bit is possibly nonzero in X (such as when
5984 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5985 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5986 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5987 (plus X 1).
5989 Remove any ZERO_EXTRACT we made when thinking this was a
5990 comparison. It may now be simpler to use, e.g., an AND. If a
5991 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5992 the call to make_compound_operation in the SET case.
5994 Don't apply these optimizations if the caller would
5995 prefer a comparison rather than a value.
5996 E.g., for the condition in an IF_THEN_ELSE most targets need
5997 an explicit comparison. */
6000 ;
6016 {
6020 mode);
6021 }
6028 {
6032 const1_rtx);
6033 }
6041 {
6044 }
6046 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6047 those above. */
6049 ;
6065 {
6069 mode);
6070 }
6078 {
6082 mode);
6083 }
6085 /* If X is 0/1, (eq X 0) is X-1. */
6091 {
6094 }
6096 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6097 one bit that might be nonzero, we can convert (ne x 0) to
6098 (ashift x c) where C puts the bit in the sign bit. Remove any
6099 AND with STORE_FLAG_VALUE when we are done, since we are only
6100 going to test the sign bit. */
6107 {
6113 else
6115 }
6117 /* If the code changed, return a whole new comparison.
6118 We also need to avoid using SUBST in cases where
6119 simplify_comparison has widened a comparison with a CONST_INT,
6120 since in that case the wider CONST_INT may fail the sanity
6121 checks in do_SUBST. */
6128 /* Otherwise, keep this operation, but maybe change its operands.
6129 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6132 }
6142 /* If we are processing SET_DEST, we are done. */
6160 /* If this is a shift by a constant amount, simplify it. */
6168 (HOST_WIDE_INT_1U
6176 }
6179 }
6180 \f
6181 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6183 static rtx
6185 {
6192 rtx temp;
6195 rtx reversed;
6197 /* Simplify storing of the truth value. */
6202 /* Also when the truth value has to be reversed. */
6208 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6209 in it is being compared against certain values. Get the true and false
6210 comparisons and see if that says anything about the value of each arm. */
6216 {
6217 HOST_WIDE_INT nzb;
6223 /* If FALSE_CODE is EQ, swap the codes and arms. */
6226 {
6229 }
6231 /* If we are comparing against zero and the expression being tested has
6232 only a single bit that might be nonzero, that is its value when it is
6233 not equal to zero. Similarly if it is known to be -1 or 0. */
6237 {
6240 }
6244 {
6247 }
6249 /* Now simplify an arm if we know the value of the register in the
6250 branch and it is used in the arm. Be careful due to the potential
6251 of locally-shared RTL. */
6268 }
6270 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6271 reversed, do so to avoid needing two sets of patterns for
6272 subtract-and-branch insns. Similarly if we have a constant in the true
6273 arm, the false arm is the same as the first operand of the comparison, or
6274 the false arm is more complicated than the true arm. */
6287 {
6296 /* It is possible that the conditional has been simplified out. */
6299 }
6301 /* If the two arms are identical, we don't need the comparison. */
6306 /* Convert a == b ? b : a to "a". */
6318 /* Look for cases where we have (abs x) or (neg (abs X)). */
6321 && comparison_p
6328 {
6334 return
6337 mode);
6340 }
6342 /* Look for MIN or MAX. */
6345 && comparison_p
6350 {
6365 }
6367 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6368 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6369 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6370 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6371 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6372 neither 1 or -1, but it isn't worth checking for. */
6375 && comparison_p
6378 {
6394 /* If an identity-zero op is commutative, check whether there
6395 would be a match if we swapped the operands. */
6415 {
6419 }
6431 {
6435 }
6451 {
6455 }
6467 {
6471 }
6474 {
6480 const_true_rtx));
6488 }
6489 }
6491 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6492 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6493 negation of a single bit, we can convert this operation to a shift. We
6494 can actually do this more generally, but it doesn't seem worth it. */
6503 return
6507 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6517 }
6518 \f
6519 /* Simplify X, a SET expression. Return the new expression. */
6521 static rtx
6523 {
6526 machine_mode mode
6531 /* (set (pc) (return)) gets written as (return). */
6535 /* Now that we know for sure which bits of SRC we are using, see if we can
6536 simplify the expression for the object knowing that we only need the
6537 low-order bits. */
6540 {
6543 }
6545 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6546 the comparison result and try to simplify it unless we already have used
6547 undobuf.other_insn. */
6555 {
6564 {
6567 {
6570 }
6571 }
6572 else
6580 {
6584 }
6585 else
6586 {
6591 /* Attempt to simplify CC user. */
6593 {
6597 }
6599 /* Convert X into a no-op move. */
6603 }
6605 /* Simplify our comparison, if possible. */
6608 #ifdef SELECT_CC_MODE
6609 /* If this machine has CC modes other than CCmode, check to see if we
6610 need to use a different CC mode here. */
6619 else
6622 /* If the mode changed, we have to change SET_DEST, the mode in the
6623 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6624 a hard register, just build new versions with the proper mode. If it
6625 is a pseudo, we lose unless it is only time we set the pseudo, in
6626 which case we can safely change its mode. */
6628 {
6630 {
6632 rtx new_dest;
6636 else
6637 {
6640 }
6647 }
6648 }
6651 /* If the code changed, we have to build a new comparison in
6652 undobuf.other_insn. */
6654 {
6663 /* If the only change we made was to change an EQ into an NE or
6664 vice versa, OP0 has only one bit that might be nonzero, and OP1
6665 is zero, check if changing the user of the condition code will
6666 produce a valid insn. If it won't, we can keep the original code
6667 in that insn by surrounding our operation with an XOR. */
6674 {
6679 {
6686 }
6687 }
6688 }
6693 /* Don't generate a compare of a CC with 0, just use that CC. */
6695 {
6698 }
6699 /* Otherwise, if we didn't previously have the same COMPARE we
6700 want, create it from scratch. */
6703 {
6706 }
6707 }
6708 else
6709 {
6710 /* Get SET_SRC in a form where we have placed back any
6711 compound expressions. Then do the checks below. */
6714 }
6716 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6717 and X being a REG or (subreg (reg)), we may be able to convert this to
6718 (set (subreg:m2 x) (op)).
6720 We can always do this if M1 is narrower than M2 because that means that
6721 we only care about the low bits of the result.
6723 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6724 perform a narrower operation than requested since the high-order bits will
6725 be undefined. On machine where it is defined, this transformation is safe
6726 as long as M1 and M2 have the same number of words. */
6734 && (WORD_REGISTER_OPERATIONS
6737 #ifdef CANNOT_CHANGE_MODE_CLASS
6742 #endif
6746 {
6749 dest));
6753 }
6755 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6756 in SRC. */
6762 {
6766 /* Here we make sure that we don't have a sign bit on. */
6769 {
6772 }
6773 }
6775 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6776 would require a paradoxical subreg. Replace the subreg with a
6777 zero_extend to avoid the reload that would otherwise be required. */
6785 {
6791 }
6793 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6794 are comparing an item known to be 0 or -1 against 0, use a logical
6795 operation instead. Check for one of the arms being an IOR of the other
6796 arm with some value. We compute three terms to be IOR'ed together. In
6797 practice, at most two will be nonzero. Then we do the IOR's. */
6805 && (!HAVE_conditional_move
6811 {
6837 false_rtx);
6843 term3));
6846 }
6848 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6849 whole thing fail. */
6854 else
6855 /* Convert this into a field assignment operation, if possible. */
6857 }
6858 \f
6859 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6860 result. */
6862 static rtx
6864 {
6870 {
6872 /* We can call simplify_and_const_int only if we don't lose
6873 any (sign) bits when converting INTVAL (op1) to
6874 "unsigned HOST_WIDE_INT". */
6878 {
6885 }
6887 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6888 apply the distributive law and then the inverse distributive
6889 law to see if things simplify. */
6891 {
6895 }
6897 {
6901 }
6905 /* If we have (ior (and A B) C), apply the distributive law and then
6906 the inverse distributive law to see if things simplify. */
6909 {
6913 }
6916 {
6920 }
6925 }
6928 }
6929 \f
6930 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6931 operations" because they can be replaced with two more basic operations.
6932 ZERO_EXTEND is also considered "compound" because it can be replaced with
6933 an AND operation, which is simpler, though only one operation.
6935 The function expand_compound_operation is called with an rtx expression
6936 and will convert it to the appropriate shifts and AND operations,
6937 simplifying at each stage.
6939 The function make_compound_operation is called to convert an expression
6940 consisting of shifts and ANDs into the equivalent compound expression.
6941 It is the inverse of this function, loosely speaking. */
6943 static rtx
6945 {
6949 rtx tem;
6952 {
6955 /* FALLTHRU */
6957 /* We can't necessarily use a const_int for a multiword mode;
6958 it depends on implicitly extending the value.
6959 Since we don't know the right way to extend it,
6960 we can't tell whether the implicit way is right.
6962 Even for a mode that is no wider than a const_int,
6963 we can't win, because we need to sign extend one of its bits through
6964 the rest of it, and we don't know which bit. */
6968 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6969 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6970 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6971 reloaded. If not for that, MEM's would very rarely be safe.
6973 Reject MODEs bigger than a word, because we might not be able
6974 to reference a two-register group starting with an arbitrary register
6975 (and currently gen_lowpart might crash for a SUBREG). */
6980 /* Reject MODEs that aren't scalar integers because turning vector
6981 or complex modes into shifts causes problems. */
6987 /* If the inner object has VOIDmode (the only way this can happen
6988 is if it is an ASM_OPERANDS), we can't do anything since we don't
6989 know how much masking to do. */
6998 /* fall through */
7001 /* If the operand is a CLOBBER, just return it. */
7010 /* Reject MODEs that aren't scalar integers because turning vector
7011 or complex modes into shifts causes problems. */
7019 /* This should stay within the object being extracted, fail otherwise. */
7030 }
7031 /* Convert sign extension to zero extension, if we know that the high
7032 bit is not set, as this is easier to optimize. It will be converted
7033 back to cheaper alternative in make_extraction. */
7041 {
7046 /* Make sure this is a profitable operation. */
7053 else
7055 }
7057 /* We can optimize some special cases of ZERO_EXTEND. */
7059 {
7060 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7061 know that the last value didn't have any inappropriate bits
7062 set. */
7070 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7079 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7080 is a comparison and STORE_FLAG_VALUE permits. This is like
7081 the first case, but it works even when GET_MODE (x) is larger
7082 than HOST_WIDE_INT. */
7091 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7101 }
7103 /* If we reach here, we want to return a pair of shifts. The inner
7104 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7105 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7106 logical depending on the value of UNSIGNEDP.
7108 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7109 converted into an AND of a shift.
7111 We must check for the case where the left shift would have a negative
7112 count. This can happen in a case like (x >> 31) & 255 on machines
7113 that can't shift by a constant. On those machines, we would first
7114 combine the shift with the AND to produce a variable-position
7115 extraction. Then the constant of 31 would be substituted in
7116 to produce such a position. */
7120 {
7129 }
7136 else
7137 /* Any other cases we can't handle. */
7140 /* If we couldn't do this for some reason, return the original
7141 expression. */
7146 }
7147 \f
7148 /* X is a SET which contains an assignment of one object into
7149 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7150 or certain SUBREGS). If possible, convert it into a series of
7151 logical operations.
7153 We half-heartedly support variable positions, but do not at all
7154 support variable lengths. */
7156 static const_rtx
7158 {
7159 rtx inner;
7163 machine_mode compute_mode;
7165 /* Loop until we find something we can't simplify. */
7167 {
7170 {
7174 }
7177 {
7182 /* A constant position should stay within the width of INNER. */
7188 {
7196 /* If position is ADJUST - X, new position is X. */
7198 else
7199 {
7204 pos);
7205 }
7206 }
7207 }
7209 /* A SUBREG between two modes that occupy the same numbers of words
7210 can be done by moving the SUBREG to the source. */
7212 /* We need SUBREGs to compute nonzero_bits properly. */
7213 && nonzero_sign_valid
7218 {
7220 gen_lowpart
7224 }
7225 else
7233 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7235 {
7236 machine_mode imode;
7238 /* Don't do anything for vector or complex integral types. */
7242 /* Try to find an integral mode to pun with. */
7249 }
7251 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7255 /* Don't try to compute in too wide unsupported modes. */
7259 /* Now compute the equivalent expression. Make a copy of INNER
7260 for the SET_DEST in case it is a MEM into which we will substitute;
7261 we don't want shared RTL in that case. */
7263 compute_mode);
7267 compute_mode,
7269 compute_mode),
7270 inner);
7275 mask),
7276 pos);
7281 }
7284 }
7285 \f
7286 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7287 it is an RTX that represents the (variable) starting position; otherwise,
7288 POS is the (constant) starting bit position. Both are counted from the LSB.
7290 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7292 IN_DEST is nonzero if this is a reference in the destination of a SET.
7293 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7294 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7295 be used.
7297 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7298 ZERO_EXTRACT should be built even for bits starting at bit 0.
7300 MODE is the desired mode of the result (if IN_DEST == 0).
7302 The result is an RTX for the extraction or NULL_RTX if the target
7303 can't handle it. */
7305 static rtx
7309 {
7310 /* This mode describes the size of the storage area
7311 to fetch the overall value from. Within that, we
7312 ignore the POS lowest bits, etc. */
7314 machine_mode inner_mode;
7315 machine_mode wanted_inner_mode;
7322 HOST_WIDE_INT orig_pos;
7328 {
7329 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7330 consider just the QI as the memory to extract from.
7331 The subreg adds or removes high bits; its mode is
7332 irrelevant to the meaning of this extraction,
7333 since POS and LEN count from the lsb. */
7337 }
7342 {
7343 /* We're extracting the least significant bits of an rtx
7344 (ashift X (const_int C)), where LEN > C. Extract the
7345 least significant (LEN - C) bits of X, giving an rtx
7346 whose mode is MODE, then shift it left C times. */
7352 }
7358 /* See if this can be done without an extraction. We never can if the
7359 width of the field is not the same as that of some integer mode. For
7360 registers, we can only avoid the extraction if the position is at the
7361 low-order bit and this is either not in the destination or we have the
7362 appropriate STRICT_LOW_PART operation available.
7364 For MEM, we can avoid an extract if the field starts on an appropriate
7365 boundary and we can change the mode of the memory reference. */
7374 && (! in_dest
7378 && (pos
7381 /* We can't do this if we are widening INNER_MODE (it
7382 may not be aligned, for one thing). */
7388 {
7389 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7390 field. If the original and current mode are the same, we need not
7391 adjust the offset. Otherwise, we do if bytes big endian.
7393 If INNER is not a MEM, get a piece consisting of just the field
7394 of interest (in this case POS % BITS_PER_WORD must be 0). */
7397 {
7398 HOST_WIDE_INT offset;
7400 /* POS counts from lsb, but make OFFSET count in memory order. */
7403 else
7407 }
7409 {
7411 {
7412 /* We can't call gen_lowpart in a DEST since we
7413 always want a SUBREG (see below) and it would sometimes
7414 return a new hard register. */
7416 {
7431 /* Avoid creating invalid subregs, for example when
7432 simplifying (x>>32)&255. */
7437 }
7438 else
7440 }
7441 else
7443 }
7444 else
7446 len >= HOST_BITS_PER_WIDE_INT
7447 ? HOST_WIDE_INT_M1U
7451 /* If this extraction is going into the destination of a SET,
7452 make a STRICT_LOW_PART unless we made a MEM. */
7467 /* If we know that no extraneous bits are set, and that the high
7468 bit is not set, convert the extraction to the cheaper of
7469 sign and zero extension, that are equivalent in these cases. */
7475 {
7479 /* Prefer ZERO_EXTENSION, since it gives more information to
7480 backends. */
7485 }
7487 /* Otherwise, sign- or zero-extend unless we already are in the
7488 proper mode. */
7492 }
7494 /* Unless this is a COMPARE or we have a funny memory reference,
7495 don't do anything with zero-extending field extracts starting at
7496 the low-order bit since they are simple AND operations. */
7501 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7502 if the position is not a constant and the length is not 1. In all
7503 other cases, we would only be going outside our object in cases when
7504 an original shift would have been undefined. */
7513 /* If INNER is not from memory, we want it to have the mode of a register
7514 extraction pattern's structure operand, or word_mode if there is no
7515 such pattern. The same applies to extraction_mode and pos_mode
7516 and their respective operands.
7518 For memory, assume that the desired extraction_mode and pos_mode
7519 are the same as for a register operation, since at present we don't
7520 have named patterns for aligned memory structures. */
7524 {
7528 }
7530 /* Never narrow an object, since that might not be safe. */
7538 else
7539 {
7540 /* Be careful not to go beyond the extracted object and maintain the
7541 natural alignment of the memory. */
7545 {
7548 }
7549 }
7554 {
7555 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7556 BITS_BIG_ENDIAN style. If position is constant, compute new
7557 position. Otherwise, build subtraction.
7558 Note that POS is relative to the mode of the original argument.
7559 If it's a MEM we need to recompute POS relative to that.
7560 However, if we're extracting from (or inserting into) a register,
7561 we want to recompute POS relative to wanted_inner_mode. */
7568 else
7569 pos_rtx
7572 pos_rtx);
7573 /* POS may be less than 0 now, but we check for that below.
7574 Note that it can only be less than 0 if !MEM_P (inner). */
7575 }
7577 /* If INNER has a wider mode, and this is a constant extraction, try to
7578 make it smaller and adjust the byte to point to the byte containing
7579 the value. */
7582 && ! pos_rtx
7587 {
7590 /* The computations below will be correct if the machine is big
7591 endian in both bits and bytes or little endian in bits and bytes.
7592 If it is mixed, we must adjust. */
7594 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7595 adjust OFFSET to compensate. */
7600 /* We can now move to the desired byte. */
7611 }
7613 /* If INNER is not memory, get it into the proper mode. If we are changing
7614 its mode, POS must be a constant and smaller than the size of the new
7615 mode. */
7617 {
7618 /* On the LHS, don't create paradoxical subregs implicitely truncating
7619 the register unless TRULY_NOOP_TRUNCATION. */
7622 wanted_inner_mode))
7634 pos_rtx
7636 ? HOST_WIDE_INT_M1U
7640 }
7642 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7643 have to zero extend. Otherwise, we can just use a SUBREG. */
7646 {
7650 /* If we know that no extraneous bits are set, and that the high
7651 bit is not set, convert extraction to cheaper one - either
7652 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7653 cases. */
7661 {
7665 /* Prefer ZERO_EXTENSION, since it gives more information to
7666 backends. */
7670 }
7672 }
7674 /* Make POS_RTX unless we already have it and it is correct. If we don't
7675 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7676 be a CONST_INT. */
7683 /* Make the required operation. See if we can use existing rtx. */
7690 }
7691 \f
7692 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7693 with any other operations in X. Return X without that shift if so. */
7695 static rtx
7697 {
7700 rtx tem;
7703 {
7705 /* This is the shift itself. If it is wide enough, we will return
7706 either the value being shifted if the shift count is equal to
7707 COUNT or a shift for the difference. */
7721 /* If we can safely shift this constant and we find the inner shift,
7722 make a new operation. */
7727 {
7731 }
7736 }
7739 }
7740 \f
7741 /* Look at the expression rooted at X. Look for expressions
7742 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7743 Form these expressions.
7745 Return the new rtx, usually just X.
7747 Also, for machines like the VAX that don't have logical shift insns,
7748 try to convert logical to arithmetic shift operations in cases where
7749 they are equivalent. This undoes the canonicalizations to logical
7750 shifts done elsewhere.
7752 We try, as much as possible, to re-use rtl expressions to save memory.
7754 IN_CODE says what kind of expression we are processing. Normally, it is
7755 SET. In a memory address it is MEM. When processing the arguments of
7756 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
7757 precisely it is an equality comparison against zero. */
7759 rtx
7761 {
7769 rtx tem;
7773 /* PR rtl-optimization/70944. */
7777 /* Select the code to be used in recursive calls. Once we are inside an
7778 address, we stay there. If we have a comparison, set to COMPARE,
7779 but once inside, go back to our default of SET. */
7782 {
7785 }
7791 /* Process depending on the code of this operation. If NEW is set
7792 nonzero, it will be returned. */
7795 {
7797 /* Convert shifts by constants into multiplications if inside
7798 an address. */
7803 {
7809 {
7812 }
7815 }
7825 {
7829 }
7832 {
7836 mode));
7838 }
7839 else
7840 {
7844 }
7855 {
7859 }
7862 {
7866 mode));
7868 }
7869 else
7870 {
7874 }
7878 /* If the second operand is not a constant, we can't do anything
7879 with it. */
7883 /* If the constant is a power of two minus one and the first operand
7884 is a logical right shift, make an extraction. */
7887 {
7891 }
7893 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7898 {
7907 {
7908 /* If we narrowed the mode when dropping the subreg, then
7909 we must zero-extend to keep the semantics of the AND. */
7911 ;
7915 else
7917 }
7919 /* If that didn't give anything, see if the AND simplifies on
7920 its own. */
7922 {
7926 }
7927 }
7928 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7934 {
7935 /* Apply the distributive law, and then try to make extractions. */
7942 }
7944 /* If we are have (and (rotate X C) M) and C is larger than the number
7945 of bits in M, this is an extraction. */
7951 {
7957 }
7959 /* On machines without logical shifts, if the operand of the AND is
7960 a logical shift and our mask turns off all the propagated sign
7961 bits, we can replace the logical shift with an arithmetic shift. */
7969 {
7976 make_compound_operation
7979 }
7981 /* If the constant is one less than a power of two, this might be
7982 representable by an extraction even if no shift is present.
7983 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7984 we are in a COMPARE. */
7988 next_code),
7991 /* If we are in a comparison and this is an AND with a power of two,
7992 convert this into the appropriate bit extract. */
7998 next_code),
8001 /* If the one operand is a paradoxical subreg of a register or memory and
8002 the constant (limited to the smaller mode) has only zero bits where
8003 the sub expression has known zero bits, this can be expressed as
8004 a zero_extend. */
8006 {
8007 rtx sub;
8013 {
8017 /* original AND constant with all the known zero bits set */
8020 {
8025 }
8026 }
8027 }
8032 /* If the sign bit is known to be zero, replace this with an
8033 arithmetic shift. */
8038 {
8041 next_code),
8044 }
8046 /* fall through */
8052 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8053 this is a SIGN_EXTRACT. */
8060 {
8067 }
8069 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8070 If so, try to merge the shifts into a SIGN_EXTEND. We could
8071 also do this for some cases of SIGN_EXTRACT, but it doesn't
8072 seem worth the effort; the case checked for occurs on Alpha. */
8089 /* Call ourselves recursively on the inner expression. If we are
8090 narrowing the object and it has a different RTL code from
8091 what it originally did, do this SUBREG as a force_to_mode. */
8092 {
8096 /* If in_code is COMPARE, it isn't always safe to pass it through
8097 to the recursive make_compound_operation call. */
8101 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8102 is (const_int 0), rather than
8103 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8113 simplified
8121 {
8122 rtx newer
8125 /* If we have something other than a SUBREG, we might have
8126 done an expansion, so rerun ourselves. */
8130 /* force_to_mode can expand compounds. If it just re-expanded the
8131 compound, use gen_lowpart to convert to the desired mode. */
8133 /* Likewise if it re-expanded the compound only partially.
8134 This happens for SUBREG of ZERO_EXTRACT if they extract
8135 the same number of bits. */
8144 }
8148 }
8153 }
8156 {
8159 }
8161 /* Now recursively process each operand of this operation. We need to
8162 handle ZERO_EXTEND specially so that we don't lose track of the
8163 inner mode. */
8165 {
8173 }
8178 {
8181 }
8184 {
8187 }
8189 maybe_swap:
8190 /* If this is a commutative operation, the changes to the operands
8191 may have made it noncanonical. */
8194 {
8198 }
8201 }
8202 \f
8203 /* Given M see if it is a value that would select a field of bits
8204 within an item, but not the entire word. Return -1 if not.
8205 Otherwise, return the starting position of the field, where 0 is the
8206 low-order bit.
8208 *PLEN is set to the length of the field. */
8210 static int
8212 {
8213 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8218 /* Now shift off the low-order zero bits and see if we have a
8219 power of two minus 1. */
8227 }
8228 \f
8229 /* If X refers to a register that equals REG in value, replace these
8230 references with REG. */
8231 static rtx
8233 {
8241 {
8274 /* FALLTHRU */
8278 {
8282 else
8284 }
8286 /* fall through */
8293 {
8296 {
8298 {
8301 }
8303 }
8304 }
8306 {
8309 {
8312 {
8314 {
8317 }
8319 }
8320 }
8321 }
8324 }
8327 }
8329 /* Return X converted to MODE. If the value is already truncated to
8330 MODE we can just return a subreg even though in the general case we
8331 would need an explicit truncation. */
8333 static rtx
8335 {
8340 {
8341 /* Bit-cast X into an integer mode. */
8346 }
8349 }
8351 /* See if X can be simplified knowing that we will only refer to it in
8352 MODE and will only refer to those bits that are nonzero in MASK.
8353 If other bits are being computed or if masking operations are done
8354 that select a superset of the bits in MASK, they can sometimes be
8355 ignored.
8357 Return a possibly simplified expression, but always convert X to
8358 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8360 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8361 are all off in X. This is used when X will be complemented, by either
8362 NOT, NEG, or XOR. */
8364 static rtx
8367 {
8370 machine_mode op_mode;
8374 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8375 code below will do the wrong thing since the mode of such an
8376 expression is VOIDmode.
8378 Also do nothing if X is a CLOBBER; this can happen if X was
8379 the return value from a call to gen_lowpart. */
8383 /* We want to perform the operation in its present mode unless we know
8384 that the operation is valid in MODE, in which case we do the operation
8385 in MODE. */
8390 /* It is not valid to do a right-shift in a narrower mode
8391 than the one it came in with. */
8396 /* Truncate MASK to fit OP_MODE. */
8400 /* When we have an arithmetic operation, or a shift whose count we
8401 do not know, we need to assume that all bits up to the highest-order
8402 bit in MASK will be needed. This is how we form such a mask. */
8405 else
8409 /* Determine what bits of X are guaranteed to be (non)zero. */
8412 /* If none of the bits in X are needed, return a zero. */
8416 /* If X is a CONST_INT, return a new one. Do this here since the
8417 test below will fail. */
8419 {
8422 else
8423 {
8426 }
8427 }
8429 /* If X is narrower than MODE and we want all the bits in X's mode, just
8430 get X in the proper mode. */
8435 /* We can ignore the effect of a SUBREG if it narrows the mode or
8436 if the constant masks to zero all the bits the mode doesn't have. */
8446 /* The arithmetic simplifications here only work for scalar integer modes. */
8451 {
8453 /* If X is a (clobber (const_int)), return it since we know we are
8454 generating something that won't match. */
8467 /* Similarly for a truncate. */
8471 /* If this is an AND with a constant, convert it into an AND
8472 whose constant is the AND of that constant with MASK. If it
8473 remains an AND of MASK, delete it since it is redundant. */
8476 {
8480 /* If X is still an AND, see if it is an AND with a mask that
8481 is just some low-order bits. If so, and it is MASK, we don't
8482 need it. */
8489 /* If it remains an AND, try making another AND with the bits
8490 in the mode mask that aren't in MASK turned on. If the
8491 constant in the AND is wide enough, this might make a
8492 cheaper constant. */
8497 {
8498 unsigned HOST_WIDE_INT cval
8501 rtx y;
8508 }
8511 }
8516 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8517 low-order bits (as in an alignment operation) and FOO is already
8518 aligned to that boundary, mask C1 to that boundary as well.
8519 This may eliminate that PLUS and, later, the AND. */
8521 {
8525 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8526 number, sign extend it. */
8539 }
8541 /* fall through */
8544 /* Substituting into the operands of a widening MULT is not likely to
8545 create RTL matching a machine insn. */
8555 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8556 most significant bit in MASK since carries from those bits will
8557 affect the bits we are interested in. */
8562 /* If X is (minus C Y) where C's least set bit is larger than any bit
8563 in the mask, then we may replace with (neg Y). */
8566 {
8570 }
8572 /* Similarly, if C contains every bit in the fuller_mask, then we may
8573 replace with (not Y). */
8576 {
8580 }
8587 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8588 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8589 operation which may be a bitfield extraction. Ensure that the
8590 constant we form is not wider than the mode of X. */
8602 {
8611 }
8613 binop:
8614 /* For most binary operations, just propagate into the operation and
8615 change the mode if we have an operation of that mode. */
8620 /* If we ended up truncating both operands, truncate the result of the
8621 operation instead. */
8624 {
8627 }
8637 /* For left shifts, do the same, but just for the first operand.
8638 However, we cannot do anything with shifts where we cannot
8639 guarantee that the counts are smaller than the size of the mode
8640 because such a count will have a different meaning in a
8641 wider mode. */
8651 /* If the shift count is a constant and we can do arithmetic in
8652 the mode of the shift, refine which bits we need. Otherwise, use the
8653 conservative form of the mask. */
8659 else
8671 /* Here we can only do something if the shift count is a constant,
8672 this shift constant is valid for the host, and we can do arithmetic
8673 in OP_MODE. */
8679 {
8683 /* Select the mask of the bits we need for the shift operand. */
8686 /* We can only change the mode of the shift if we can do arithmetic
8687 in the mode of the shift and INNER_MASK is no wider than the
8688 width of X's mode. */
8696 }
8698 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8699 shift and AND produces only copies of the sign bit (C2 is one less
8700 than a power of two), we can do this with just a shift. */
8704 /* The shift puts one of the sign bit copies in the least significant
8705 bit. */
8710 /* Number of bits left after the shift must be more than the mask
8711 needs. */
8714 /* Must be more sign bit copies than the mask needs. */
8724 /* If we are just looking for the sign bit, we don't need this shift at
8725 all, even if it has a variable count. */
8729 /* If this is a shift by a constant, get a mask that contains those bits
8730 that are not copies of the sign bit. We then have two cases: If
8731 MASK only includes those bits, this can be a logical shift, which may
8732 allow simplifications. If MASK is a single-bit field not within
8733 those bits, we are requesting a copy of the sign bit and hence can
8734 shift the sign bit to the appropriate location. */
8738 {
8741 /* If the considered data is wider than HOST_WIDE_INT, we can't
8742 represent a mask for all its bits in a single scalar.
8743 But we only care about the lower bits, so calculate these. */
8746 {
8749 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8750 is the number of bits a full-width mask would have set.
8751 We need only shift if these are fewer than nonzero can
8752 hold. If not, we must keep all bits set in nonzero. */
8757 + HOST_BITS_PER_WIDE_INT
8759 }
8760 else
8761 {
8764 }
8767 {
8772 }
8775 {
8776 x = simplify_shift_const
8782 }
8783 }
8785 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8786 even if the shift count isn't a constant. */
8791 shiftrt:
8793 /* If this is a zero- or sign-extension operation that just affects bits
8794 we don't care about, remove it. Be sure the call above returned
8795 something that is still a shift. */
8805 next_select);
8811 /* If the shift count is constant and we can do computations
8812 in the mode of X, compute where the bits we care about are.
8813 Otherwise, we can't do anything. Don't change the mode of
8814 the shift or propagate MODE into the shift, though. */
8817 {
8827 }
8831 /* If we just want the low-order bit, the NEG isn't needed since it
8832 won't change the low-order bit. */
8836 /* We need any bits less significant than the most significant bit in
8837 MASK since carries from those bits will affect the bits we are
8838 interested in. */
8843 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8844 same as the XOR case above. Ensure that the constant we form is not
8845 wider than the mode of X. */
8853 {
8862 }
8864 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8865 use the full mask inside the NOT. */
8868 unop:
8871 next_select));
8877 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8878 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8879 which is equal to STORE_FLAG_VALUE. */
8891 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8892 written in a narrower mode. We play it safe and do not do so. */
8908 }
8910 /* Ensure we return a value of the proper mode. */
8912 }
8913 \f
8914 /* Return nonzero if X is an expression that has one of two values depending on
8915 whether some other value is zero or nonzero. In that case, we return the
8916 value that is being tested, *PTRUE is set to the value if the rtx being
8917 returned has a nonzero value, and *PFALSE is set to the other alternative.
8919 If we return zero, we set *PTRUE and *PFALSE to X. */
8921 static rtx
8923 {
8929 /* If we are comparing a value against zero, we are done. */
8932 {
8936 }
8938 /* If this is a unary operation whose operand has one of two values, apply
8939 our opcode to compute those values. */
8942 {
8947 }
8949 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8950 make can't possibly match and would suppress other optimizations. */
8952 ;
8954 /* If this is a binary operation, see if either side has only one of two
8955 values. If either one does or if both do and they are conditional on
8956 the same value, compute the new true and false values. */
8958 {
8964 {
8965 /* If if_then_else_cond returned zero, then true/false are the
8966 same rtl. We must copy one of them to prevent invalid rtl
8967 sharing. */
8974 {
8979 }
8980 else
8981 {
8984 }
8987 }
8989 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8990 operands is zero when the other is nonzero, and vice-versa,
8991 and STORE_FLAG_VALUE is 1 or -1. */
8997 {
9014 {
9021 const_true_rtx);
9023 }
9024 }
9026 /* Similarly for MULT, AND and UMIN, except that for these the result
9027 is always zero. */
9031 {
9045 {
9048 }
9049 }
9050 }
9053 {
9054 /* If we have IF_THEN_ELSE already, extract the condition and
9055 canonicalize it if it is NE or EQ. */
9061 {
9064 }
9065 else
9067 }
9069 /* If X is a SUBREG, we can narrow both the true and false values
9070 if the inner expression, if there is a condition. */
9074 {
9080 {
9084 }
9085 }
9087 /* If X is a constant, this isn't special and will cause confusions
9088 if we treat it as such. Likewise if it is equivalent to a constant. */
9091 ;
9093 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9094 will be least confusing to the rest of the compiler. */
9096 {
9099 }
9101 /* If X is known to be either 0 or -1, those are the true and
9102 false values when testing X. */
9106 {
9109 }
9111 /* Likewise for 0 or a single bit. */
9114 {
9117 }
9119 /* Otherwise fail; show no condition with true and false values the same. */
9122 }
9123 \f
9124 /* Return the value of expression X given the fact that condition COND
9125 is known to be true when applied to REG as its first operand and VAL
9126 as its second. X is known to not be shared and so can be modified in
9127 place.
9129 We only handle the simplest cases, and specifically those cases that
9130 arise with IF_THEN_ELSE expressions. */
9132 static rtx
9134 {
9142 /* If either operand of the condition is a floating point value,
9143 then we have to avoid collapsing an EQ comparison. */
9153 /* If X is (abs REG) and we know something about REG's relationship
9154 with zero, we may be able to simplify this. */
9158 {
9167 }
9169 /* The only other cases we handle are MIN, MAX, and comparisons if the
9170 operands are the same as REG and VAL. */
9173 {
9175 {
9178 }
9181 {
9183 {
9191 else
9193 }
9196 {
9199 /* Do not reverse the condition when it is NE or EQ.
9200 This is because we cannot conclude anything about
9201 the value of 'SMAX (x, y)' when x is not equal to y,
9202 but we can when x equals y. */
9208 {
9219 }
9220 }
9221 }
9222 }
9224 {
9229 {
9230 /* We must simplify subreg here, before we lose track of the
9231 original inner_mode. */
9236 else
9238 }
9241 }
9242 /* We don't have to handle SIGN_EXTEND here, because even in the
9243 case of replacing something with a modeless CONST_INT, a
9244 CONST_INT is already (supposed to be) a valid sign extension for
9245 its narrower mode, which implies it's already properly
9246 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9247 story is different. */
9249 {
9254 {
9255 /* We must simplify the zero_extend here, before we lose
9256 track of the original inner_mode. */
9261 else
9263 }
9266 }
9270 {
9277 }
9280 }
9281 \f
9282 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9283 assignment as a field assignment. */
9285 static int
9287 {
9289 {
9294 /* For big endian, adjust the memory offset. */
9299 else
9301 }
9309 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9310 Note that all SUBREGs of MEM are paradoxical; otherwise they
9311 would have been rewritten. */
9324 /* We used to see if get_last_value of X and Y were the same but that's
9325 not correct. In one direction, we'll cause the assignment to have
9326 the wrong destination and in the case, we'll import a register into this
9327 insn that might have already have been dead. So fail if none of the
9328 above cases are true. */
9330 }
9331 \f
9332 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9333 Return that assignment if so.
9335 We only handle the most common cases. */
9337 static rtx
9339 {
9342 rtx assign;
9344 HOST_WIDE_INT c1;
9345 HOST_WIDE_INT pos;
9347 rtx other;
9348 machine_mode mode;
9350 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9351 a clear of a one-bit field. We will have changed it to
9352 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9353 for a SUBREG. */
9359 {
9365 }
9375 {
9382 }
9384 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9385 one-bit field. */
9389 {
9395 }
9397 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9398 SRC is an AND with all bits of that field set, then we can discard
9399 the AND. */
9404 {
9411 else
9414 /* Complete overlap. We can remove the source AND. */
9418 /* Partial overlap. We can reduce the source AND. */
9420 {
9425 }
9426 }
9428 /* The other case we handle is assignments into a constant-position
9429 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9430 a mask that has all one bits except for a group of zero bits and
9431 OTHER is known to have zeros where C1 has ones, this is such an
9432 assignment. Compute the position and length from C1. Shift OTHER
9433 to the appropriate position, force it to the required mode, and
9434 make the extraction. Check for the AND in both operands. */
9436 /* One or more SUBREGs might obscure the constant-position field
9437 assignment. The first one we are likely to encounter is an outer
9438 narrowing SUBREG, which we can just strip for the purposes of
9439 identifying the constant-field assignment. */
9453 /* The second SUBREG that might get in the way is a paradoxical
9454 SUBREG around the first operand of the AND. We want to
9455 pretend the operand is as wide as the destination here. We
9456 do this by adjusting the MEM to wider mode for the sole
9457 purpose of the call to rtx_equal_for_field_assignment_p. Also
9458 note this trick only works for MEMs. */
9470 /* The second SUBREG that might get in the way is a paradoxical
9471 SUBREG around the first operand of the AND. We want to
9472 pretend the operand is as wide as the destination here. We
9473 do this by adjusting the MEM to wider mode for the sole
9474 purpose of the call to rtx_equal_for_field_assignment_p. Also
9475 note this trick only works for MEMs. */
9483 else
9496 /* The mode to use for the source is the mode of the assignment, or of
9497 what is inside a possible STRICT_LOW_PART. */
9501 /* Shift OTHER right POS places and make it the source, restricting it
9502 to the proper length and mode. */
9507 dest);
9510 ? HOST_WIDE_INT_M1U
9514 /* If SRC is masked by an AND that does not make a difference in
9515 the value being stored, strip it. */
9526 }
9527 \f
9528 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9529 if so. */
9531 static rtx
9533 {
9537 rtx tem;
9539 /* Distributivity is not true for floating point as it can change the
9540 value. So we don't do it unless -funsafe-math-optimizations. */
9545 /* The outer operation can only be one of the following: */
9553 /* If either operand is a primitive we can't do anything, so get out
9554 fast. */
9564 /* See if the inner and outer operations distribute. */
9566 {
9571 /* These all distribute except over PLUS. */
9582 /* This is also a multiply, so it distributes over everything. */
9585 /* This used to handle SUBREG, but this turned out to be counter-
9586 productive, since (subreg (op ...)) usually is not handled by
9587 insn patterns, and this "optimization" therefore transformed
9588 recognizable patterns into unrecognizable ones. Therefore the
9589 SUBREG case was removed from here.
9591 It is possible that distributing SUBREG over arithmetic operations
9592 leads to an intermediate result than can then be optimized further,
9593 e.g. by moving the outer SUBREG to the other side of a SET as done
9594 in simplify_set. This seems to have been the original intent of
9595 handling SUBREGs here.
9597 However, with current GCC this does not appear to actually happen,
9598 at least on major platforms. If some case is found where removing
9599 the SUBREG case here prevents follow-on optimizations, distributing
9600 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9604 }
9606 /* Set LHS and RHS to the inner operands (A and B in the example
9607 above) and set OTHER to the common operand (C in the example).
9608 There is only one way to do this unless the inner operation is
9609 commutative. */
9621 else
9624 /* Form the new inner operation, seeing if it simplifies first. */
9627 /* There is one exception to the general way of distributing:
9628 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9630 {
9633 }
9635 /* We may be able to continuing distributing the result, so call
9636 ourselves recursively on the inner operation before forming the
9637 outer operation, which we return. */
9640 }
9642 /* See if X is of the form (* (+ A B) C), and if so convert to
9643 (+ (* A C) (* B C)) and try to simplify.
9645 Most of the time, this results in no change. However, if some of
9646 the operands are the same or inverses of each other, simplifications
9647 will result.
9649 For example, (and (ior A B) (not B)) can occur as the result of
9650 expanding a bit field assignment. When we apply the distributive
9651 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9652 which then simplifies to (and (A (not B))).
9654 Note that no checks happen on the validity of applying the inverse
9655 distributive law. This is pointless since we can do it in the
9656 few places where this routine is called.
9658 N is the index of the term that is decomposed (the arithmetic operation,
9659 i.e. (+ A B) in the first example above). !N is the index of the term that
9660 is distributed, i.e. of C in the first example above. */
9661 static rtx
9663 {
9664 machine_mode mode;
9668 /* Distributivity is not true for floating point as it can change the
9669 value. So we don't do it unless -funsafe-math-optimizations. */
9686 /* Special case (and (xor B C) (not A)), which is equivalent to
9687 (xor (ior A B) (ior A C)) */
9689 {
9692 }
9695 {
9696 /* Distribute the second term. */
9699 }
9700 else
9701 {
9702 /* Distribute the first term. */
9705 }
9715 }
9716 \f
9717 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9718 in MODE. Return an equivalent form, if different from (and VAROP
9719 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9721 static rtx
9724 {
9727 rtx orig_varop;
9735 /* Simplify VAROP knowing that we will be only looking at some of the
9736 bits in it.
9738 Note by passing in CONSTOP, we guarantee that the bits not set in
9739 CONSTOP are not significant and will never be examined. We must
9740 ensure that is the case by explicitly masking out those bits
9741 before returning. */
9744 /* If VAROP is a CLOBBER, we will fail so return it. */
9748 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9749 to VAROP and return the new constant. */
9753 /* See what bits may be nonzero in VAROP. Unlike the general case of
9754 a call to nonzero_bits, here we don't care about bits outside
9755 MODE. */
9759 /* Turn off all bits in the constant that are known to already be zero.
9760 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9761 which is tested below. */
9765 /* If we don't have any bits left, return zero. */
9769 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9770 a power of two, we can replace this with an ASHIFT. */
9775 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9776 or XOR, then try to apply the distributive law. This may eliminate
9777 operations if either branch can be simplified because of the AND.
9778 It may also make some cases more complex, but those cases probably
9779 won't match a pattern either with or without this. */
9782 return
9783 gen_lowpart
9785 apply_distributive_law
9790 constop),
9794 constop))));
9796 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9797 the AND and see if one of the operands simplifies to zero. If so, we
9798 may eliminate it. */
9802 {
9811 }
9813 /* Make a SUBREG if necessary. If we can't make it, fail. */
9818 /* If we are only masking insignificant bits, return VAROP. */
9825 /* Otherwise, return an AND. */
9827 }
9830 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9831 in MODE.
9833 Return an equivalent form, if different from X. Otherwise, return X. If
9834 X is zero, we are to always construct the equivalent form. */
9836 static rtx
9839 {
9850 }
9851 \f
9852 /* Given a REG, X, compute which bits in X can be nonzero.
9853 We don't care about bits outside of those defined in MODE.
9855 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9856 a shift, AND, or zero_extract, we can do better. */
9858 static rtx
9860 const_rtx known_x ATTRIBUTE_UNUSED,
9861 machine_mode known_mode ATTRIBUTE_UNUSED,
9864 {
9865 rtx tem;
9868 /* If X is a register whose nonzero bits value is current, use it.
9869 Otherwise, if X is a register whose value we can find, use that
9870 value. Otherwise, use the previously-computed global nonzero bits
9871 for this register. */
9885 && !REGNO_REG_SET_P
9888 {
9892 /* We don't know anything about the upper bits. */
9897 }
9902 {
9908 }
9910 {
9914 /* We don't know anything about the upper bits. */
9918 }
9921 }
9923 /* Return the number of bits at the high-order end of X that are known to
9924 be equal to the sign bit. X will be used in mode MODE; if MODE is
9925 VOIDmode, X will be used in its own mode. The returned value will always
9926 be between 1 and the number of bits in MODE. */
9928 static rtx
9930 const_rtx known_x ATTRIBUTE_UNUSED,
9931 machine_mode known_mode
9932 ATTRIBUTE_UNUSED,
9935 {
9936 rtx tem;
9949 && !REGNO_REG_SET_P
9952 {
9955 }
9966 }
9967 \f
9968 /* Return the number of "extended" bits there are in X, when interpreted
9969 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9970 unsigned quantities, this is the number of high-order zero bits.
9971 For signed quantities, this is the number of copies of the sign bit
9972 minus 1. In both case, this function returns the number of "spare"
9973 bits. For example, if two quantities for which this function returns
9974 at least 1 are added, the addition is known not to overflow.
9976 This function will always return 0 unless called during combine, which
9977 implies that it must be called from a define_split. */
9979 unsigned int
9981 {
9991 }
9993 /* This function is called from `simplify_shift_const' to merge two
9994 outer operations. Specifically, we have already found that we need
9995 to perform operation *POP0 with constant *PCONST0 at the outermost
9996 position. We would now like to also perform OP1 with constant CONST1
9997 (with *POP0 being done last).
9999 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10000 the resulting operation. *PCOMP_P is set to 1 if we would need to
10001 complement the innermost operand, otherwise it is unchanged.
10003 MODE is the mode in which the operation will be done. No bits outside
10004 the width of this mode matter. It is assumed that the width of this mode
10005 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10007 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10008 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10009 result is simply *PCONST0.
10011 If the resulting operation cannot be expressed as one operation, we
10012 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10014 static int
10015 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10016 {
10023 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10027 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10028 if OP0 is SET. */
10037 {
10039 {
10057 }
10058 }
10060 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10064 /* If the two constants aren't the same, we can't do anything. The
10065 remaining six cases can all be done. */
10069 else
10071 {
10074 /* (a & b) | b == b */
10077 /* (a ^ b) | b == a | b */
10078 {;}
10083 /* (a & b) ^ b == (~a) & b */
10086 /* (a | b) ^ b == a & ~b */
10092 /* (a | b) & b == b */
10095 /* (a ^ b) & b) == (~a) & b */
10100 }
10102 /* Check for NO-OP cases. */
10115 /* ??? Slightly redundant with the above mask, but not entirely.
10116 Moving this above means we'd have to sign-extend the mode mask
10117 for the final test. */
10122 }
10123 \f
10124 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10125 the shift in. The original shift operation CODE is performed on OP in
10126 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10127 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10128 result of the shift is subject to operation OUTER_CODE with operand
10129 OUTER_CONST. */
10131 static machine_mode
10135 {
10140 /* In general we can't perform in wider mode for right shift and rotate. */
10142 {
10144 /* We can still widen if the bits brought in from the left are identical
10145 to the sign bit of ORIG_MODE. */
10153 /* Similarly here but with zero bits. */
10158 /* We can also widen if the bits brought in will be masked off. This
10159 operation is performed in ORIG_MODE. */
10161 {
10167 }
10168 /* fall through */
10178 }
10179 }
10181 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10182 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10183 if we cannot simplify it. Otherwise, return a simplified value.
10185 The shift is normally computed in the widest mode we find in VAROP, as
10186 long as it isn't a different number of words than RESULT_MODE. Exceptions
10187 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10189 static rtx
10192 {
10198 unsigned int mode_words
10200 /* We form (outer_op (code varop count) (outer_const)). */
10206 /* Make sure and truncate the "natural" shift on the way in. We don't
10207 want to do this inside the loop as it makes it more difficult to
10208 combine shifts. */
10212 /* If we were given an invalid count, don't do anything except exactly
10213 what was requested. */
10220 /* Unless one of the branches of the `if' in this loop does a `continue',
10221 we will `break' the loop after the `if'. */
10224 {
10225 /* If we have an operand of (clobber (const_int 0)), fail. */
10229 /* Convert ROTATERT to ROTATE. */
10231 {
10236 else
10238 }
10243 /* Handle cases where the count is greater than the size of the mode
10244 minus 1. For ASHIFT, use the size minus one as the count (this can
10245 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10246 take the count modulo the size. For other shifts, the result is
10247 zero.
10249 Since these shifts are being produced by the compiler by combining
10250 multiple operations, each of which are defined, we know what the
10251 result is supposed to be. */
10254 {
10259 else
10260 {
10261 /* We can't simply return zero because there may be an
10262 outer op. */
10266 }
10267 }
10269 /* If we discovered we had to complement VAROP, leave. Making a NOT
10270 here would cause an infinite loop. */
10274 /* An arithmetic right shift of a quantity known to be -1 or 0
10275 is a no-op. */
10279 {
10282 }
10284 /* If we are doing an arithmetic right shift and discarding all but
10285 the sign bit copies, this is equivalent to doing a shift by the
10286 bitsize minus one. Convert it into that shift because it will often
10287 allow other simplifications. */
10294 /* We simplify the tests below and elsewhere by converting
10295 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10296 `make_compound_operation' will convert it to an ASHIFTRT for
10297 those machines (such as VAX) that don't have an LSHIFTRT. */
10314 {
10321 {
10324 }
10328 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10329 minus the width of a smaller mode, we can do this with a
10330 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10337 {
10346 }
10350 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10351 the same number of words as what we've seen so far. Then store
10352 the widest mode in MODE. */
10358 == mode_words
10361 {
10366 }
10370 /* Some machines use MULT instead of ASHIFT because MULT
10371 is cheaper. But it is still better on those machines to
10372 merge two shifts into one. */
10375 {
10376 varop
10382 }
10386 /* Similar, for when divides are cheaper. */
10389 {
10390 varop
10396 }
10400 /* If we are extracting just the sign bit of an arithmetic
10401 right shift, that shift is not needed. However, the sign
10402 bit of a wider mode may be different from what would be
10403 interpreted as the sign bit in a narrower mode, so, if
10404 the result is narrower, don't discard the shift. */
10409 {
10412 }
10414 /* fall through */
10419 /* Here we have two nested shifts. The result is usually the
10420 AND of a new shift with a mask. We compute the result below. */
10427 {
10431 rtx mask_rtx;
10433 /* We have one common special case. We can't do any merging if
10434 the inner code is an ASHIFTRT of a smaller mode. However, if
10435 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10436 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10437 we can convert it to
10438 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10439 This simplifies certain SIGN_EXTEND operations. */
10443 {
10444 /* C3 has the low-order C1 bits zero. */
10456 }
10458 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10459 than C1 high-order bits equal to the sign bit, we can convert
10460 this to either an ASHIFT or an ASHIFTRT depending on the
10461 two counts.
10463 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10469 {
10473 {
10476 }
10479 }
10481 /* There are some cases we can't do. If CODE is ASHIFTRT,
10482 we can only do this if FIRST_CODE is also ASHIFTRT.
10484 We can't do the case when CODE is ROTATE and FIRST_CODE is
10485 ASHIFTRT.
10487 If the mode of this shift is not the mode of the outer shift,
10488 we can't do this if either shift is a right shift or ROTATE.
10490 Finally, we can't do any of these if the mode is too wide
10491 unless the codes are the same.
10493 Handle the case where the shift codes are the same
10494 first. */
10497 {
10506 }
10517 /* To compute the mask to apply after the shift, shift the
10518 nonzero bits of the inner shift the same way the
10519 outer shift will. */
10522 result_mode);
10524 mask_rtx
10528 /* Give up if we can't compute an outer operation to use. */
10536 /* If the shifts are in the same direction, we add the
10537 counts. Otherwise, we subtract them. */
10541 else
10544 /* If COUNT is positive, the new shift is usually CODE,
10545 except for the two exceptions below, in which case it is
10546 FIRST_CODE. If the count is negative, FIRST_CODE should
10547 always be used */
10557 }
10559 /* If we have (A << B << C) for any shift, we can convert this to
10560 (A << C << B). This wins if A is a constant. Only try this if
10561 B is not a constant. */
10566 {
10567 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10568 sure the result will be masked. See PR70222. */
10576 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10577 up outer sign extension (often left and right shift) is
10578 hardly more efficient than the original. See PR70429. */
10588 }
10595 /* Make this fit the case below. */
10602 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10603 with C the size of VAROP - 1 and the shift is logical if
10604 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10605 we have an (le X 0) operation. If we have an arithmetic shift
10606 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10607 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10615 {
10618 const0_rtx);
10624 }
10626 /* If we have (shift (logical)), move the logical to the outside
10627 to allow it to possibly combine with another logical and the
10628 shift to combine with another shift. This also canonicalizes to
10629 what a ZERO_EXTRACT looks like. Also, some machines have
10630 (and (shift)) insns. */
10633 /* We can't do this if we have (ashiftrt (xor)) and the
10634 constant has its sign bit set in shift_mode with shift_mode
10635 wider than result_mode. */
10639 shift_mode))
10647 {
10650 }
10652 /* If we can't do that, try to simplify the shift in each arm of the
10653 logical expression, make a new logical expression, and apply
10654 the inverse distributive law. This also can't be done for
10655 (ashiftrt (xor)) where we've widened the shift and the constant
10656 changes the sign bit. */
10661 shift_mode)))
10662 {
10674 }
10678 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10679 says that the sign bit can be tested, FOO has mode MODE, C is
10680 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10681 that may be nonzero. */
10691 {
10695 }
10699 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10700 than the number of bits in the mode is equivalent to A. */
10704 {
10708 }
10710 /* NEG commutes with ASHIFT since it is multiplication. Move the
10711 NEG outside to allow shifts to combine. */
10715 {
10718 }
10722 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10723 is one less than the number of bits in the mode is
10724 equivalent to (xor A 1). */
10731 {
10735 }
10737 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10738 that might be nonzero in BAR are those being shifted out and those
10739 bits are known zero in FOO, we can replace the PLUS with FOO.
10740 Similarly in the other operand order. This code occurs when
10741 we are computing the size of a variable-size array. */
10748 {
10751 }
10759 result_mode)))
10760 {
10763 }
10765 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10775 {
10778 }
10780 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10781 signbit', and attempt to change the PLUS to an XOR and move it to
10782 the outer operation as is done above in the AND/IOR/XOR case
10783 leg for shift(logical). See details in logical handling above
10784 for reasoning in doing so. */
10795 {
10798 }
10803 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10804 with C the size of VAROP - 1 and the shift is logical if
10805 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10806 we have a (gt X 0) operation. If the shift is arithmetic with
10807 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10808 we have a (neg (gt X 0)) operation. */
10817 {
10820 const0_rtx);
10826 }
10830 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10831 if the truncate does not affect the value. */
10838 {
10841 varop_inner
10844 GEN_INT
10849 }
10854 }
10857 }
10862 /* We have now finished analyzing the shift. The result should be
10863 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10864 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10865 to the result of the shift. OUTER_CONST is the relevant constant,
10866 but we must turn off all bits turned off in the shift. */
10874 /* Make a SUBREG if necessary. If we can't make it, fail. */
10879 /* If we have an outer operation and we just made a shift, it is
10880 possible that we could have simplified the shift were it not
10881 for the outer operation. So try to do the simplification
10882 recursively. */
10886 else
10892 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10893 turn off all the bits that the shift would have turned off. */
10898 /* Do the remainder of the processing in RESULT_MODE. */
10901 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10902 operation. */
10907 {
10915 {
10916 /* This means that we have determined that the result is
10917 equivalent to a constant. This should be rare. */
10920 }
10923 else
10926 }
10929 }
10931 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10932 The result of the shift is RESULT_MODE. If we cannot simplify it,
10933 return X or, if it is NULL, synthesize the expression with
10934 simplify_gen_binary. Otherwise, return a simplified value.
10936 The shift is normally computed in the widest mode we find in VAROP, as
10937 long as it isn't a different number of words than RESULT_MODE. Exceptions
10938 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10940 static rtx
10943 {
10953 }
10955 \f
10956 /* A subroutine of recog_for_combine. See there for arguments and
10957 return value. */
10959 static int
10961 {
10963 rtx pat_without_clobbers;
10971 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10972 we use to indicate that something didn't match. If we find such a
10973 thing, force rejection. */
10987 {
10990 else
10993 }
10995 /* If it isn't, there is the possibility that we previously had an insn
10996 that clobbered some register as a side effect, but the combined
10997 insn doesn't need to do that. So try once more without the clobbers
10998 unless this represents an ASM insn. */
11002 {
11007 {
11010 pos++;
11011 }
11021 {
11024 else
11027 }
11028 }
11035 /* Recognize all noop sets, these will be killed by followup pass. */
11039 /* If we had any clobbers to add, make a new pattern than contains
11040 them. Then check to make sure that all of them are dead. */
11042 {
11052 else
11059 {
11064 {
11068 }
11069 }
11071 }
11075 {
11082 /* Allow targets to reject combined insn. */
11084 {
11087 dump_file);
11089 /* Callers expect recog_for_combine to strip
11090 clobbers from the pattern on failure. */
11095 }
11100 }
11106 }
11108 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11109 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11110 Return whether anything was so changed. */
11112 static bool
11114 {
11120 {
11129 {
11138 }
11144 {
11147 }
11152 {
11155 }
11156 else
11164 }
11168 {
11172 {
11176 }
11177 }
11184 {
11205 }
11208 }
11210 /* Like recog, but we receive the address of a pointer to a new pattern.
11211 We try to match the rtx that the pointer points to.
11212 If that fails, we may try to modify or replace the pattern,
11213 storing the replacement into the same pointer object.
11215 Modifications include deletion or addition of CLOBBERs. If the
11216 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11217 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11218 (and undo if that fails).
11220 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11221 the CLOBBERs are placed.
11223 The value is the final insn code from the pattern ultimately matched,
11224 or -1. */
11226 static int
11228 {
11240 {
11243 {
11247 }
11248 }
11251 {
11256 }
11259 }
11260 \f
11261 /* Like gen_lowpart_general but for use by combine. In combine it
11262 is not possible to create any new pseudoregs. However, it is
11263 safe to create invalid memory addresses, because combine will
11264 try to recognize them and all they will do is make the combine
11265 attempt fail.
11267 If for some reason this cannot do its job, an rtx
11268 (clobber (const_int 0)) is returned.
11269 An insn containing that will not be recognized. */
11271 static rtx
11273 {
11277 rtx result;
11282 /* We can only support MODE being wider than a word if X is a
11283 constant integer or has a mode the same size. */
11288 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11289 won't know what to do. So we will strip off the SUBREG here and
11290 process normally. */
11292 {
11295 /* For use in case we fall down into the address adjustments
11296 further below, we need to adjust the known mode and size of
11297 x; imode and isize, since we just adjusted x. */
11304 }
11312 {
11315 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11316 address. */
11321 /* If we want to refer to something bigger than the original memref,
11322 generate a paradoxical subreg instead. That will force a reload
11323 of the original memref X. */
11330 /* Adjust the address so that the address-after-the-data is
11331 unchanged. */
11336 }
11338 /* If X is a comparison operator, rewrite it in a new mode. This
11339 probably won't match, but may allow further simplifications. */
11343 /* If we couldn't simplify X any other way, just enclose it in a
11344 SUBREG. Normally, this SUBREG won't match, but some patterns may
11345 include an explicit SUBREG or we may simplify it further in combine. */
11346 else
11347 {
11348 rtx res;
11351 {
11356 }
11360 }
11362 fail:
11364 }
11365 \f
11366 /* Try to simplify a comparison between OP0 and a constant OP1,
11367 where CODE is the comparison code that will be tested, into a
11368 (CODE OP0 const0_rtx) form.
11370 The result is a possibly different comparison code to use.
11371 *POP1 may be updated. */
11373 static enum rtx_code
11376 {
11380 /* Get the constant we are comparing against and turn off all bits
11381 not on in our mode. */
11385 /* If we are comparing against a constant power of two and the value
11386 being compared can only have that single bit nonzero (e.g., it was
11387 `and'ed with that bit), we can replace this with a comparison
11388 with zero. */
11396 {
11399 }
11401 /* Similarly, if we are comparing a value known to be either -1 or
11402 0 with -1, change it to the opposite comparison against zero. */
11407 {
11410 }
11412 /* Do some canonicalizations based on the comparison code. We prefer
11413 comparisons against zero and then prefer equality comparisons.
11414 If we can reduce the size of a constant, we will do that too. */
11416 {
11418 /* < C is equivalent to <= (C - 1) */
11420 {
11423 /* ... fall through to LE case below. */
11425 }
11426 else
11430 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11432 {
11435 }
11437 /* If we are doing a <= 0 comparison on a value known to have
11438 a zero sign bit, we can replace this with == 0. */
11448 /* >= C is equivalent to > (C - 1). */
11450 {
11453 /* ... fall through to GT below. */
11455 }
11456 else
11460 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11462 {
11465 }
11467 /* If we are doing a > 0 comparison on a value known to have
11468 a zero sign bit, we can replace this with != 0. */
11478 /* < C is equivalent to <= (C - 1). */
11480 {
11483 /* ... fall through ... */
11484 }
11485 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11489 {
11493 }
11494 else
11498 /* unsigned <= 0 is equivalent to == 0 */
11501 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11505 {
11508 }
11512 /* >= C is equivalent to > (C - 1). */
11514 {
11517 /* ... fall through ... */
11518 }
11520 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11524 {
11528 }
11529 else
11533 /* unsigned > 0 is equivalent to != 0 */
11536 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11540 {
11543 }
11548 }
11552 }
11553 \f
11554 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11555 comparison code that will be tested.
11557 The result is a possibly different comparison code to use. *POP0 and
11558 *POP1 may be updated.
11560 It is possible that we might detect that a comparison is either always
11561 true or always false. However, we do not perform general constant
11562 folding in combine, so this knowledge isn't useful. Such tautologies
11563 should have been detected earlier. Hence we ignore all such cases. */
11565 static enum rtx_code
11567 {
11574 /* Try a few ways of applying the same transformation to both operands. */
11576 {
11577 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11578 so check specially. */
11594 - (GET_MODE_PRECISION
11596 {
11599 }
11601 /* If both operands are the same constant shift, see if we can ignore the
11602 shift. We can if the shift is a rotate or if the bits shifted out of
11603 this shift are known to be zero for both inputs and if the type of
11604 comparison is compatible with the shift. */
11617 {
11630 else
11632 }
11634 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11635 SUBREGs are of the same mode, and, in both cases, the AND would
11636 be redundant if the comparison was done in the narrower mode,
11637 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11638 and the operand's possibly nonzero bits are 0xffffff01; in that case
11639 if we only care about QImode, we don't need the AND). This case
11640 occurs if the output mode of an scc insn is not SImode and
11641 STORE_FLAG_VALUE == 1 (e.g., the 386).
11643 Similarly, check for a case where the AND's are ZERO_EXTEND
11644 operations from some narrower mode even though a SUBREG is not
11645 present. */
11650 {
11667 {
11671 /* The resulting comparison is always unsigned since we masked
11672 off the original sign bit. */
11676 }
11683 {
11689 }
11693 }
11695 /* If both operands are NOT, we can strip off the outer operation
11696 and adjust the comparison code for swapped operands; similarly for
11697 NEG, except that this must be an equality comparison. */
11703 else
11705 }
11707 /* If the first operand is a constant, swap the operands and adjust the
11708 comparison code appropriately, but don't do this if the second operand
11709 is already a constant integer. */
11711 {
11714 }
11716 /* We now enter a loop during which we will try to simplify the comparison.
11717 For the most part, we only are concerned with comparisons with zero,
11718 but some things may really be comparisons with zero but not start
11719 out looking that way. */
11722 {
11729 HOST_WIDE_INT const_op;
11731 /* We only want to handle integral modes. This catches VOIDmode,
11732 CCmode, and the floating-point modes. An exception is that we
11733 can handle VOIDmode if OP0 is a COMPARE or a comparison
11734 operation. */
11741 /* Try to simplify the compare to constant, possibly changing the
11742 comparison op, and/or changing op1 to zero. */
11746 /* Compute some predicates to simplify code below. */
11753 /* If this is a sign bit comparison and we can do arithmetic in
11754 MODE, say that we will only be needing the sign bit of OP0. */
11757 HOST_WIDE_INT_1U
11761 /* Now try cases based on the opcode of OP0. If none of the cases
11762 does a "continue", we exit this loop immediately after the
11763 switch. */
11766 {
11768 /* If we are extracting a single bit from a variable position in
11769 a constant that has only a single bit set and are comparing it
11770 with zero, we can convert this into an equality comparison
11771 between the position and the location of the single bit. */
11772 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11773 have already reduced the shift count modulo the word size. */
11779 {
11787 /* Result is nonzero iff shift count is equal to I. */
11790 }
11792 /* fall through */
11797 {
11800 }
11804 /* If testing for equality, we can take the NOT of the constant. */
11807 {
11811 }
11813 /* If just looking at the sign bit, reverse the sense of the
11814 comparison. */
11816 {
11820 }
11824 /* If testing for equality, we can take the NEG of the constant. */
11827 {
11831 }
11833 /* The remaining cases only apply to comparisons with zero. */
11837 /* When X is ABS or is known positive,
11838 (neg X) is < 0 if and only if X != 0. */
11846 {
11850 }
11852 /* If we have NEG of something whose two high-order bits are the
11853 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11855 {
11859 }
11863 /* If we are testing equality and our count is a constant, we
11864 can perform the inverse operation on our RHS. */
11868 {
11872 }
11874 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11875 a particular bit. Convert it to an AND of a constant of that
11876 bit. This will be converted into a ZERO_EXTRACT. */
11880 {
11882 (HOST_WIDE_INT_1U
11887 }
11889 /* Fall through. */
11892 /* ABS is ignorable inside an equality comparison with zero. */
11894 {
11897 }
11901 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11902 (compare FOO CONST) if CONST fits in FOO's mode and we
11903 are either testing inequality or have an unsigned
11904 comparison with ZERO_EXTEND or a signed comparison with
11905 SIGN_EXTEND. But don't do it if we don't have a compare
11906 insn of the given mode, since we'd have to revert it
11907 later on, and then we wouldn't know whether to sign- or
11908 zero-extend. */
11911 && ! unsigned_comparison_p
11915 {
11918 }
11922 /* Check for the case where we are comparing A - C1 with C2, that is
11924 (subreg:MODE (plus (A) (-C1))) op (C2)
11926 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11927 comparison in the wider mode. One of the following two conditions
11928 must be true in order for this to be valid:
11930 1. The mode extension results in the same bit pattern being added
11931 on both sides and the comparison is equality or unsigned. As
11932 C2 has been truncated to fit in MODE, the pattern can only be
11933 all 0s or all 1s.
11935 2. The mode extension results in the sign bit being copied on
11936 each side.
11938 The difficulty here is that we have predicates for A but not for
11939 (A - C1) so we need to check that C1 is within proper bounds so
11940 as to perturbate A as little as possible. */
11947 {
11956 /* (A - C1) zero-extends if it is positive and sign-extends
11957 if it is negative, C2 both zero- and sign-extends. */
11961 /* (A - C1) sign-extends if it is positive and 1-extends
11962 if it is negative, C2 both sign- and 1-extends. */
11969 /* (A - C1) always sign-extends, like C2. */
11973 {
11976 }
11977 }
11979 /* If the inner mode is narrower and we are extracting the low part,
11980 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11983 ;
11984 else
11987 /* FALLTHROUGH */
11997 {
12000 }
12004 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12005 this for equality comparisons due to pathological cases involving
12006 overflows. */
12010 {
12014 }
12016 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12019 {
12023 }
12027 /* We used to optimize signed comparisons against zero, but that
12028 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12029 arrive here as equality comparisons, or (GEU, LTU) are
12030 optimized away. No need to special-case them. */
12032 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12033 (eq B (minus A C)), whichever simplifies. We can only do
12034 this for equality comparisons due to pathological cases involving
12035 overflows. */
12039 {
12043 }
12048 {
12052 }
12054 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12055 of bits in X minus 1, is one iff X > 0. */
12060 {
12064 }
12068 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12069 if C is zero or B is a constant. */
12073 {
12077 }
12085 /* We can't do anything if OP0 is a condition code value, rather
12086 than an actual data value. */
12092 /* Get the two operands being compared. */
12095 else
12098 /* Check for the cases where we simply want the result of the
12099 earlier test or the opposite of that result. */
12103 {
12107 else
12111 {
12116 }
12117 }
12121 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12122 iff X <= 0. */
12126 {
12130 }
12134 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12135 will be converted to a ZERO_EXTRACT later. */
12139 {
12144 }
12146 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12147 zero and X is a comparison and C1 and C2 describe only bits set
12148 in STORE_FLAG_VALUE, we can compare with X. */
12156 {
12163 {
12166 }
12167 }
12169 /* If we are doing an equality comparison of an AND of a bit equal
12170 to the sign bit, replace this with a LT or GE comparison of
12171 the underlying value. */
12178 {
12182 }
12184 /* If this AND operation is really a ZERO_EXTEND from a narrower
12185 mode, the constant fits within that mode, and this is either an
12186 equality or unsigned comparison, try to do this comparison in
12187 the narrower mode.
12189 Note that in:
12191 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12192 -> (ne:DI (reg:SI 4) (const_int 0))
12194 unless TRULY_NOOP_TRUNCATION allows it or the register is
12195 known to hold a value of the required mode the
12196 transformation is invalid. */
12204 {
12207 }
12209 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12210 fits in both M1 and M2 and the SUBREG is either paradoxical
12211 or represents the low part, permute the SUBREG and the AND
12212 and try again. */
12215 {
12218 /* Require an integral mode, to avoid creating something like
12219 (AND:SF ...). */
12221 /* It is unsafe to commute the AND into the SUBREG if the
12222 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12223 not defined. As originally written the upper bits
12224 have a defined value due to the AND operation.
12225 However, if we commute the AND inside the SUBREG then
12226 they no longer have defined values and the meaning of
12227 the code has been changed.
12228 Also C1 should not change value in the smaller mode,
12229 see PR67028 (a positive C1 can become negative in the
12230 smaller mode, so that the AND does no longer mask the
12231 upper bits). */
12232 && ((WORD_REGISTER_OPERATIONS
12244 {
12250 }
12251 }
12253 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12257 {
12262 }
12264 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12265 (eq (and (lshiftrt X) 1) 0).
12266 Also handle the case where (not X) is expressed using xor. */
12270 {
12280 == HOST_WIDE_INT_1U
12282 {
12283 op0
12288 }
12289 }
12293 /* If we have (compare (ashift FOO N) (const_int C)) and
12294 the high order N bits of FOO (N+1 if an inequality comparison)
12295 are known to be zero, we can do this by comparing FOO with C
12296 shifted right N bits so long as the low-order N bits of C are
12297 zero. */
12309 {
12310 /* We must perform a logical shift, not an arithmetic one,
12311 as we want the top N bits of C to be zero. */
12318 }
12320 /* If we are doing a sign bit comparison, it means we are testing
12321 a particular bit. Convert it to the appropriate AND. */
12324 {
12326 (HOST_WIDE_INT_1U
12331 }
12333 /* If this an equality comparison with zero and we are shifting
12334 the low bit to the sign bit, we can convert this to an AND of the
12335 low-order bit. */
12339 {
12342 }
12346 /* If this is an equality comparison with zero, we can do this
12347 as a logical shift, which might be much simpler. */
12350 {
12355 }
12357 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12358 do the comparison in a narrower mode. */
12368 {
12371 }
12373 /* Likewise if OP0 is a PLUS of a sign extension with a
12374 constant, which is usually represented with the PLUS
12375 between the shifts. */
12387 {
12395 new_const);
12397 }
12399 /* FALLTHROUGH */
12401 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12402 the low order N bits of FOO are known to be zero, we can do this
12403 by comparing FOO with C shifted left N bits so long as no
12404 overflow occurs. Even if the low order N bits of FOO aren't known
12405 to be zero, if the comparison is >= or < we can use the same
12406 optimization and for > or <= by setting all the low
12407 order N bits in the comparison constant. */
12418 {
12419 unsigned HOST_WIDE_INT low_bits
12421 & ((HOST_WIDE_INT_1U
12424 {
12425 /* If the shift was logical, then we must make the condition
12426 unsigned. */
12434 const_op
12439 }
12440 }
12442 /* If we are using this shift to extract just the sign bit, we
12443 can replace this with an LT or GE comparison. */
12448 {
12452 }
12457 }
12460 }
12462 /* Now make any compound operations involved in this comparison. Then,
12463 check for an outmost SUBREG on OP0 that is not doing anything or is
12464 paradoxical. The latter transformation must only be performed when
12465 it is known that the "extra" bits will be the same in op0 and op1 or
12466 that they don't matter. There are three cases to consider:
12468 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12469 care bits and we can assume they have any convenient value. So
12470 making the transformation is safe.
12472 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12473 In this case the upper bits of op0 are undefined. We should not make
12474 the simplification in that case as we do not know the contents of
12475 those bits.
12477 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12478 In that case we know those bits are zeros or ones. We must also be
12479 sure that they are the same as the upper bits of op1.
12481 We can never remove a SUBREG for a non-equality comparison because
12482 the sign bit is in a different place in the underlying object. */
12495 {
12497 {
12498 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12499 implemented. */
12501 {
12504 }
12505 }
12511 {
12517 }
12518 }
12520 /* We now do the opposite procedure: Some machines don't have compare
12521 insns in all modes. If OP0's mode is an integer mode smaller than a
12522 word and we can't do a compare in that mode, see if there is a larger
12523 mode for which we can do the compare. There are a number of cases in
12524 which we can use the wider mode. */
12534 {
12537 /* If this is a test for negative, we can make an explicit
12538 test of the sign bit. Test this first so we can use
12539 a paradoxical subreg to extend OP0. */
12543 {
12544 unsigned HOST_WIDE_INT sign
12551 }
12553 /* If the only nonzero bits in OP0 and OP1 are those in the
12554 narrower mode and this is an equality or unsigned comparison,
12555 we can use the wider mode. Similarly for sign-extended
12556 values, in which case it is true for all comparisons. */
12573 {
12574 /* If OP0 is an AND and we don't have an AND in MODE either,
12575 make a new AND in the proper mode. */
12583 else
12584 {
12586 {
12589 }
12590 else
12591 {
12594 }
12596 }
12597 }
12598 }
12600 /* We may have changed the comparison operands. Re-canonicalize. */
12602 {
12605 }
12607 /* If this machine only supports a subset of valid comparisons, see if we
12608 can convert an unsupported one into a supported one. */
12615 }
12616 \f
12617 /* Utility function for record_value_for_reg. Count number of
12618 rtxs in X. */
12619 static int
12621 {
12628 {
12648 }
12659 }
12660 \f
12661 /* Utility function for following routine. Called when X is part of a value
12662 being stored into last_set_value. Sets last_set_table_tick
12663 for each register mentioned. Similar to mention_regs in cse.c */
12665 static void
12667 {
12673 {
12679 {
12682 }
12685 }
12689 {
12690 /* Check for identical subexpressions. If x contains
12691 identical subexpression we only have to traverse one of
12692 them. */
12694 {
12695 /* Note that at this point x1 has already been
12696 processed. */
12700 /* If x0 and x1 are identical then there is no need to
12701 process x0. */
12705 /* If x0 is identical to a subexpression of x1 then while
12706 processing x1, x0 has already been processed. Thus we
12707 are done with x. */
12712 /* If x1 is identical to a subexpression of x0 then we
12713 still have to process the rest of x0. */
12716 {
12719 }
12720 }
12723 }
12727 }
12729 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12730 are saying that the register is clobbered and we no longer know its
12731 value. If INSN is zero, don't update reg_stat[].last_set; this is
12732 only permitted with VALUE also zero and is used to invalidate the
12733 register. */
12735 static void
12737 {
12743 /* If VALUE contains REG and we have a previous value for REG, substitute
12744 the previous value. */
12746 {
12747 rtx tem;
12749 /* Set things up so get_last_value is allowed to see anything set up to
12750 our insn. */
12754 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12755 it isn't going to be useful and will take a lot of time to process,
12756 so just use the CLOBBER. */
12759 {
12765 {
12766 /* If there are two or more occurrences of REG in VALUE,
12767 prevent the value from growing too much. */
12770 }
12773 }
12774 }
12776 /* For each register modified, show we don't know its value, that
12777 we don't know about its bitwise content, that its value has been
12778 updated, and that we don't know the location of the death of the
12779 register. */
12781 {
12793 }
12795 /* Mark registers that are being referenced in this value. */
12799 /* Now update the status of each register being set.
12800 If someone is using this register in this block, set this register
12801 to invalid since we will get confused between the two lives in this
12802 basic block. This makes using this register always invalid. In cse, we
12803 scan the table to invalidate all entries using this register, but this
12804 is too much work for us. */
12807 {
12813 else
12815 }
12817 /* The value being assigned might refer to X (like in "x++;"). In that
12818 case, we must replace it with (clobber (const_int 0)) to prevent
12819 infinite loops. */
12822 {
12826 }
12828 /* For the main register being modified, update the value, the mode, the
12829 nonzero bits, and the number of sign bit copies. */
12834 {
12842 rsp->last_set_sign_bit_copies
12844 }
12845 }
12847 /* Called via note_stores from record_dead_and_set_regs to handle one
12848 SET or CLOBBER in an insn. DATA is the instruction in which the
12849 set is occurring. */
12851 static void
12853 {
12860 {
12864 }
12867 {
12868 /* If we are setting the whole register, we know its value. Otherwise
12869 show that we don't know the value. We can handle SUBREG in
12870 some cases. */
12881 else
12883 }
12885 /* Ignore pushes, they clobber nothing. */
12888 }
12890 /* Update the records of when each REG was most recently set or killed
12891 for the things done by INSN. This is the last thing done in processing
12892 INSN in the combiner loop.
12894 We update reg_stat[], in particular fields last_set, last_set_value,
12895 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12896 last_death, and also the similar information mem_last_set (which insn
12897 most recently modified memory) and last_call_luid (which insn was the
12898 most recent subroutine call). */
12900 static void
12902 {
12903 rtx link;
12907 {
12910 {
12915 {
12920 }
12921 }
12924 }
12927 {
12928 hard_reg_set_iterator hrsi;
12930 {
12942 }
12946 /* We can't combine into a call pattern. Remember, though, that
12947 the return value register is set at this LUID. We could
12948 still replace a register with the return value from the
12949 wrong subroutine call! */
12951 }
12952 else
12954 }
12956 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12957 register present in the SUBREG, so for each such SUBREG go back and
12958 adjust nonzero and sign bit information of the registers that are
12959 known to have some zero/sign bits set.
12961 This is needed because when combine blows the SUBREGs away, the
12962 information on zero/sign bits is lost and further combines can be
12963 missed because of that. */
12965 static void
12967 {
12969 rtx set;
12977 {
12986 {
12989 }
12993 {
12996 }
12999 {
13002 }
13003 else
13005 }
13006 }
13008 /* Check if X, a register, is known to contain a value already
13009 truncated to MODE. In this case we can use a subreg to refer to
13010 the truncated value even though in the generic case we would need
13011 an explicit truncation. */
13013 static bool
13015 {
13027 }
13029 /* If X is a hard reg or a subreg record the mode that the register is
13030 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13031 to turn a truncate into a subreg using this information. Return true
13032 if traversing X is complete. */
13034 static bool
13036 {
13037 machine_mode truncated_mode;
13041 {
13052 }
13053 /* ??? For hard-regs we now record everything. We might be able to
13054 optimize this using last_set_mode. */
13057 else
13065 {
13068 }
13071 }
13073 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13074 the modes they are used in. This can help truning TRUNCATEs into
13075 SUBREGs. */
13077 static void
13079 {
13084 }
13086 /* Scan X for promoted SUBREGs. For each one found,
13087 note what it implies to the registers used in it. */
13089 static void
13091 {
13096 else
13097 {
13103 {
13113 }
13114 }
13115 }
13116 \f
13117 /* Verify that all the registers and memory references mentioned in *LOC are
13118 still valid. *LOC was part of a value set in INSN when label_tick was
13119 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13120 the invalid references with (clobber (const_int 0)) and return 1. This
13121 replacement is useful because we often can get useful information about
13122 the form of a value (e.g., if it was produced by a shift that always
13123 produces -1 or 0) even though we don't know exactly what registers it
13124 was produced from. */
13126 static int
13128 {
13135 {
13141 {
13144 /* If this is a pseudo-register that was only set once and not
13145 live at the beginning of the function, it is always valid. */
13149 && (!REGNO_REG_SET_P
13151 regno)))
13153 {
13157 }
13158 }
13161 }
13162 /* If this is a memory reference, make sure that there were no stores after
13163 it that might have clobbered the value. We don't have alias info, so we
13164 assume any store invalidates it. Moreover, we only have local UIDs, so
13165 we also assume that there were stores in the intervening basic blocks. */
13168 {
13172 }
13175 {
13177 {
13178 /* Check for identical subexpressions. If x contains
13179 identical subexpression we only have to traverse one of
13180 them. */
13182 {
13183 /* Note that at this point x0 has already been checked
13184 and found valid. */
13188 /* If x0 and x1 are identical then x is also valid. */
13192 /* If x1 is identical to a subexpression of x0 then
13193 while checking x0, x1 has already been checked. Thus
13194 it is valid and so as x. */
13199 /* If x0 is identical to a subexpression of x1 then x is
13200 valid iff the rest of x1 is valid. */
13203 return
13207 }
13212 }
13218 }
13220 /* If we haven't found a reason for it to be invalid, it is valid. */
13222 }
13224 /* Get the last value assigned to X, if known. Some registers
13225 in the value may be replaced with (clobber (const_int 0)) if their value
13226 is known longer known reliably. */
13228 static rtx
13230 {
13232 rtx value;
13235 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13236 then convert it to the desired mode. If this is a paradoxical SUBREG,
13237 we cannot predict what values the "extra" bits might have. */
13251 /* If we don't have a value, or if it isn't for this basic block and
13252 it's either a hard register, set more than once, or it's a live
13253 at the beginning of the function, return 0.
13255 Because if it's not live at the beginning of the function then the reg
13256 is always set before being used (is never used without being set).
13257 And, if it's set only once, and it's always set before use, then all
13258 uses must have the same last value, even if it's not from this basic
13259 block. */
13266 || REGNO_REG_SET_P
13270 /* If the value was set in a later insn than the ones we are processing,
13271 we can't use it even if the register was only set once. */
13276 /* If fewer bits were set than what we are asked for now, we cannot use
13277 the value. */
13282 /* If the value has all its registers valid, return it. */
13286 /* Otherwise, make a copy and replace any invalid register with
13287 (clobber (const_int 0)). If that fails for some reason, return 0. */
13294 }
13295 \f
13296 /* Return nonzero if expression X refers to a REG or to memory
13297 that is set in an instruction more recent than FROM_LUID. */
13299 static int
13301 {
13307 {
13311 #ifdef PUSH_ROUNDING
13312 /* Don't allow uses of the stack pointer to be moved,
13313 because we don't know whether the move crosses a push insn. */
13316 #endif
13318 {
13324 }
13326 }
13334 {
13336 {
13341 }
13345 }
13347 }
13348 \f
13349 /* Define three variables used for communication between the following
13350 routines. */
13355 /* Function called via note_stores from reg_dead_at_p.
13357 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13358 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13360 static void
13362 {
13372 }
13374 /* Return nonzero if REG is known to be dead at INSN.
13376 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13377 referencing REG, it is dead. If we hit a SET referencing REG, it is
13378 live. Otherwise, see if it is live or dead at the start of the basic
13379 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13380 must be assumed to be always live. */
13382 static int
13384 {
13385 basic_block block;
13388 /* Set variables for reg_dead_at_p_1. */
13394 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13395 we allow the machine description to decide whether use-and-clobber
13396 patterns are OK. */
13398 {
13402 }
13404 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13405 beginning of basic block. */
13408 {
13410 {
13420 }
13426 }
13428 /* Look at live-in sets for the basic block that we were in. */
13434 }
13435 \f
13436 /* Note hard registers in X that are used. */
13438 static void
13440 {
13446 {
13450 CASE_CONST_ANY:
13455 /* CC0 must die in the insn after it is set, so we don't need to take
13456 special note of it here. */
13461 /* If we are clobbering a MEM, mark any hard registers inside the
13462 address as used. */
13469 /* A hard reg in a wide mode may really be multiple registers.
13470 If so, mark all of them just like the first. */
13472 {
13473 /* None of this applies to the stack, frame or arg pointers. */
13475 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13483 }
13487 {
13488 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13489 the address. */
13501 }
13506 }
13508 /* Recursively scan the operands of this expression. */
13510 {
13514 {
13518 {
13523 }
13524 }
13525 }
13526 }
13527 \f
13528 /* Remove register number REGNO from the dead registers list of INSN.
13530 Return the note used to record the death, if there was one. */
13532 rtx
13534 {
13541 }
13543 /* For each register (hardware or pseudo) used within expression X, if its
13544 death is in an instruction with luid between FROM_LUID (inclusive) and
13545 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13546 list headed by PNOTES.
13548 That said, don't move registers killed by maybe_kill_insn.
13550 This is done when X is being merged by combination into TO_INSN. These
13551 notes will then be distributed as needed. */
13553 static void
13556 {
13562 {
13566 /* Don't move the register if it gets killed in between from and to. */
13575 {
13578 /* It is possible for the call above to return 0. This can occur
13579 when last_death points to I2 or I1 that we combined with.
13580 In that case make a new note.
13582 We must also check for the case where X is a hard register
13583 and NOTE is a death note for a range of hard registers
13584 including X. In that case, we must put REG_DEAD notes for
13585 the remaining registers in place of NOTE. */
13590 {
13599 }
13601 /* If we didn't find any note, or if we found a REG_DEAD note that
13602 covers only part of the given reg, and we have a multi-reg hard
13603 register, then to be safe we must check for REG_DEAD notes
13604 for each register other than the first. They could have
13605 their own REG_DEAD notes lying around. */
13612 {
13619 else
13625 }
13628 {
13631 }
13632 else
13634 }
13637 }
13640 {
13645 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13646 that accesses one word of a multi-word item, some
13647 piece of everything register in the expression is used by
13648 this insn, so remove any old death. */
13649 /* ??? So why do we test for equality of the sizes? */
13658 {
13661 }
13663 /* If this is some other SUBREG, we know it replaces the entire
13664 value, so use that as the destination. */
13668 /* If this is a MEM, adjust deaths of anything used in the address.
13669 For a REG (the only other possibility), the entire value is
13670 being replaced so the old value is not used in this insn. */
13676 }
13685 {
13687 {
13692 }
13695 }
13696 }
13697 \f
13698 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13699 pattern of an insn. X must be a REG. */
13701 static int
13703 {
13707 {
13709 rtx target;
13716 else
13733 }
13741 }
13742 \f
13743 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13744 as appropriate. I3 and I2 are the insns resulting from the combination
13745 insns including FROM (I2 may be zero).
13747 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13748 not need REG_DEAD notes because they are being substituted for. This
13749 saves searching in the most common cases.
13751 Each note in the list is either ignored or placed on some insns, depending
13752 on the type of note. */
13754 static void
13757 {
13759 rtx tem_note;
13763 {
13768 {
13771 /* Doesn't matter much where we put this, as long as it's somewhere.
13772 It is preferable to keep these notes on branches, which is most
13773 likely to be i3. */
13780 else
13781 {
13784 }
13788 /* These notes must remain with the call or trapping instruction. */
13793 else
13794 {
13800 /* ??? Otherwise assume we've combined things such that we
13801 can now prove that the instructions can't trap. Drop the
13802 note in this case. */
13803 }
13807 /* ??? How to distribute between i3-i1. Assume i3 contains the
13808 entire adjustment. Assert i3 contains at least some adjust. */
13810 {
13812 /* fixup_args_size_notes looks at REG_NORETURN note,
13813 so ensure the note is placed there first. */
13815 {
13819 {
13825 }
13826 }
13828 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13829 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13832 && !ACCUMULATE_OUTGOING_ARGS
13834 }
13841 /* These notes must remain with the call. It should not be
13842 possible for both I2 and I3 to be a call. */
13845 else
13846 {
13849 }
13853 /* Any clobbers for i3 may still exist, and so we must process
13854 REG_UNUSED notes from that insn.
13856 Any clobbers from i2 or i1 can only exist if they were added by
13857 recog_for_combine. In that case, recog_for_combine created the
13858 necessary REG_UNUSED notes. Trying to keep any original
13859 REG_UNUSED notes from these insns can cause incorrect output
13860 if it is for the same register as the original i3 dest.
13861 In that case, we will notice that the register is set in i3,
13862 and then add a REG_UNUSED note for the destination of i3, which
13863 is wrong. However, it is possible to have REG_UNUSED notes from
13864 i2 or i1 for register which were both used and clobbered, so
13865 we keep notes from i2 or i1 if they will turn into REG_DEAD
13866 notes. */
13868 /* If this register is set or clobbered in I3, put the note there
13869 unless there is one already. */
13871 {
13879 }
13880 /* Otherwise, if this register is used by I3, then this register
13881 now dies here, so we must put a REG_DEAD note here unless there
13882 is one already. */
13888 {
13891 }
13897 /* These notes say something about results of an insn. We can
13898 only support them if they used to be on I3 in which case they
13899 remain on I3. Otherwise they are ignored.
13901 If the note refers to an expression that is not a constant, we
13902 must also ignore the note since we cannot tell whether the
13903 equivalence is still true. It might be possible to do
13904 slightly better than this (we only have a problem if I2DEST
13905 or I1DEST is present in the expression), but it doesn't
13906 seem worth the trouble. */
13914 /* These notes say something about how a register is used. They must
13915 be present on any use of the register in I2 or I3. */
13920 {
13923 else
13925 }
13930 /* This can show up in several ways -- either directly in the
13931 pattern, or hidden off in the constant pool with (or without?)
13932 a REG_EQUAL note. */
13933 /* ??? Ignore the without-reg_equal-note problem for now. */
13945 {
13948 else
13950 }
13952 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13953 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13954 there. */
13959 {
13966 }
13972 {
13980 }
13984 /* This note says something about the value of a register prior
13985 to the execution of an insn. It is too much trouble to see
13986 if the note is still correct in all situations. It is better
13987 to simply delete it. */
13991 /* If we replaced the right hand side of FROM_INSN with a
13992 REG_EQUAL note, the original use of the dying register
13993 will not have been combined into I3 and I2. In such cases,
13994 FROM_INSN is guaranteed to be the first of the combined
13995 instructions, so we simply need to search back before
13996 FROM_INSN for the previous use or set of this register,
13997 then alter the notes there appropriately.
13999 If the register is used as an input in I3, it dies there.
14000 Similarly for I2, if it is nonzero and adjacent to I3.
14002 If the register is not used as an input in either I3 or I2
14003 and it is not one of the registers we were supposed to eliminate,
14004 there are two possibilities. We might have a non-adjacent I2
14005 or we might have somehow eliminated an additional register
14006 from a computation. For example, we might have had A & B where
14007 we discover that B will always be zero. In this case we will
14008 eliminate the reference to A.
14010 In both cases, we must search to see if we can find a previous
14011 use of A and put the death note there. */
14017 else
14018 {
14029 && !(i2mod
14031 i2mod_old_rhs)))
14036 /* If the new I2 sets the same register that is marked dead
14037 in the note, we do not know where to put the note.
14038 Give up. */
14041 }
14044 {
14048 {
14050 {
14054 }
14056 /* If the register is being set at TEM_INSN, see if that is all
14057 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14058 into a REG_UNUSED note instead. Don't delete sets to
14059 global register vars. */
14063 {
14074 ;
14076 /* Verify that it was the set, and not a clobber that
14077 modified the register.
14079 CC0 targets must be careful to maintain setter/user
14080 pairs. If we cannot delete the setter due to side
14081 effects, mark the user with an UNUSED note instead
14082 of deleting it. */
14086 && (!HAVE_cc0
14090 {
14091 /* Move the notes and links of TEM_INSN elsewhere.
14092 This might delete other dead insns recursively.
14093 First set the pattern to something that won't use
14094 any register. */
14108 /* Delete the setter too. */
14110 {
14123 }
14124 }
14125 else
14126 {
14129 /* If there isn't already a REG_UNUSED note, put one
14130 here. Do not place a REG_DEAD note, even if
14131 the register is also used here; that would not
14132 match the algorithm used in lifetime analysis
14133 and can cause the consistency check in the
14134 scheduler to fail. */
14139 }
14140 }
14144 {
14147 /* If we are doing a 3->2 combination, and we have a
14148 register which formerly died in i3 and was not used
14149 by i2, which now no longer dies in i3 and is used in
14150 i2 but does not die in i2, and place is between i2
14151 and i3, then we may need to move a link from place to
14152 i2. */
14154 && from_insn
14157 {
14161 }
14163 }
14167 }
14169 }
14171 /* If the register is set or already dead at PLACE, we needn't do
14172 anything with this note if it is still a REG_DEAD note.
14173 We check here if it is set at all, not if is it totally replaced,
14174 which is what `dead_or_set_p' checks, so also check for it being
14175 set partially. */
14178 {
14184 {
14185 /* Unless the register previously died in PLACE, clear
14186 last_death. [I no longer understand why this is
14187 being done.] */
14191 }
14192 else
14195 /* If this is a death note for a hard reg that is occupying
14196 multiple registers, ensure that we are still using all
14197 parts of the object. If we find a piece of the object
14198 that is unused, we must arrange for an appropriate REG_DEAD
14199 note to be added for it. However, we can't just emit a USE
14200 and tag the note to it, since the register might actually
14201 be dead; so we recourse, and the recursive call then finds
14202 the previous insn that used this register. */
14205 {
14214 {
14217 }
14220 {
14221 /* Put only REG_DEAD notes for pieces that are
14222 not already dead or set. */
14226 {
14233 {
14235 NULL_RTX);
14239 NULL_RTX);
14240 }
14245 {
14247 {
14251 }
14255 {
14258 }
14259 }
14260 }
14263 }
14264 }
14265 }
14269 /* Any other notes should not be present at this point in the
14270 compilation. */
14272 }
14275 {
14278 }
14282 }
14283 }
14284 \f
14285 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14286 I3, I2, and I1 to new locations. This is also called to add a link
14287 pointing at I3 when I3's destination is changed. */
14289 static void
14291 {
14295 {
14302 /* If the insn that this link points to is a NOTE, ignore it. */
14311 {
14314 {
14330 }
14333 }
14334 else
14344 /* A LOG_LINK is defined as being placed on the first insn that uses
14345 a register and points to the insn that sets the register. Start
14346 searching at the next insn after the target of the link and stop
14347 when we reach a set of the register or the end of the basic block.
14349 Note that this correctly handles the link that used to point from
14350 I3 to I2. Also note that not much searching is typically done here
14351 since most links don't point very far away. */
14360 {
14364 }
14367 {
14370 }
14374 /* If we found a place to put the link, place it there unless there
14375 is already a link to the same insn as LINK at that point. */
14378 {
14386 {
14390 /* Set added_links_insn to the earliest insn we added a
14391 link to. */
14395 }
14396 }
14397 }
14398 }
14399 \f
14400 /* Check for any register or memory mentioned in EQUIV that is not
14401 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14402 of EXPR where some registers may have been replaced by constants. */
14404 static bool
14406 {
14409 {
14414 }
14416 }
14417 \f
14418 DEBUG_FUNCTION void
14420 {
14421 fprintf
14423 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14425 }
14427 void
14429 {
14430 fprintf
14432 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14434 }
14435 \f
14436 /* Try combining insns through substitution. */
14437 static unsigned int
14439 {
14449 rebuild_jump_labels_after_combine
14452 /* Combining insns may have turned an indirect jump into a
14453 direct jump. Rebuild the JUMP_LABEL fields of jumping
14454 instructions. */
14456 {
14463 }
14467 }
14472 {
14482 };
14485 {
14489 {}
14491 /* opt_pass methods: */
14494 {
14496 }
14502 rtl_opt_pass *
14504 {
14506 }