2008-07-01 Jerry DeLisle <jvdelisle@gcc.gnu.org>
[official-gcc.git] / gcc / config / mips / mips.c
blob48ba54b1cef6dcae5924a032d24336ea8d3c6350
1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include <signal.h>
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "output.h"
41 #include "tree.h"
42 #include "function.h"
43 #include "expr.h"
44 #include "optabs.h"
45 #include "libfuncs.h"
46 #include "flags.h"
47 #include "reload.h"
48 #include "tm_p.h"
49 #include "ggc.h"
50 #include "gstab.h"
51 #include "hashtab.h"
52 #include "debug.h"
53 #include "target.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
59 #include "tree-gimple.h"
60 #include "bitmap.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
71 XVECEXP (X, 0, 0)
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
92 part of the frame. */
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 : (INSN))
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 : (INSN))
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
131 ADDRESS_REG
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
135 ADDRESS_LO_SUM
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
139 ADDRESS_CONST_INT
140 A signed 16-bit constant address.
142 ADDRESS_SYMBOLIC:
143 A constant symbolic address. */
144 enum mips_address_type {
145 ADDRESS_REG,
146 ADDRESS_LO_SUM,
147 ADDRESS_CONST_INT,
148 ADDRESS_SYMBOLIC
151 /* Macros to create an enumeration identifier for a function prototype. */
152 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
153 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
154 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
155 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
157 /* Classifies the prototype of a built-in function. */
158 enum mips_function_type {
159 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
160 #include "config/mips/mips-ftypes.def"
161 #undef DEF_MIPS_FTYPE
162 MIPS_MAX_FTYPE_MAX
165 /* Specifies how a built-in function should be converted into rtl. */
166 enum mips_builtin_type {
167 /* The function corresponds directly to an .md pattern. The return
168 value is mapped to operand 0 and the arguments are mapped to
169 operands 1 and above. */
170 MIPS_BUILTIN_DIRECT,
172 /* The function corresponds directly to an .md pattern. There is no return
173 value and the arguments are mapped to operands 0 and above. */
174 MIPS_BUILTIN_DIRECT_NO_TARGET,
176 /* The function corresponds to a comparison instruction followed by
177 a mips_cond_move_tf_ps pattern. The first two arguments are the
178 values to compare and the second two arguments are the vector
179 operands for the movt.ps or movf.ps instruction (in assembly order). */
180 MIPS_BUILTIN_MOVF,
181 MIPS_BUILTIN_MOVT,
183 /* The function corresponds to a V2SF comparison instruction. Operand 0
184 of this instruction is the result of the comparison, which has mode
185 CCV2 or CCV4. The function arguments are mapped to operands 1 and
186 above. The function's return value is an SImode boolean that is
187 true under the following conditions:
189 MIPS_BUILTIN_CMP_ANY: one of the registers is true
190 MIPS_BUILTIN_CMP_ALL: all of the registers are true
191 MIPS_BUILTIN_CMP_LOWER: the first register is true
192 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
193 MIPS_BUILTIN_CMP_ANY,
194 MIPS_BUILTIN_CMP_ALL,
195 MIPS_BUILTIN_CMP_UPPER,
196 MIPS_BUILTIN_CMP_LOWER,
198 /* As above, but the instruction only sets a single $fcc register. */
199 MIPS_BUILTIN_CMP_SINGLE,
201 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
202 MIPS_BUILTIN_BPOSGE32
205 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
206 #define MIPS_FP_CONDITIONS(MACRO) \
207 MACRO (f), \
208 MACRO (un), \
209 MACRO (eq), \
210 MACRO (ueq), \
211 MACRO (olt), \
212 MACRO (ult), \
213 MACRO (ole), \
214 MACRO (ule), \
215 MACRO (sf), \
216 MACRO (ngle), \
217 MACRO (seq), \
218 MACRO (ngl), \
219 MACRO (lt), \
220 MACRO (nge), \
221 MACRO (le), \
222 MACRO (ngt)
224 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
225 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
226 enum mips_fp_condition {
227 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
230 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
231 #define STRINGIFY(X) #X
232 static const char *const mips_fp_conditions[] = {
233 MIPS_FP_CONDITIONS (STRINGIFY)
236 /* Information about a function's frame layout. */
237 struct mips_frame_info GTY(()) {
238 /* The size of the frame in bytes. */
239 HOST_WIDE_INT total_size;
241 /* The number of bytes allocated to variables. */
242 HOST_WIDE_INT var_size;
244 /* The number of bytes allocated to outgoing function arguments. */
245 HOST_WIDE_INT args_size;
247 /* The number of bytes allocated to the .cprestore slot, or 0 if there
248 is no such slot. */
249 HOST_WIDE_INT cprestore_size;
251 /* Bit X is set if the function saves or restores GPR X. */
252 unsigned int mask;
254 /* Likewise FPR X. */
255 unsigned int fmask;
257 /* The number of GPRs and FPRs saved. */
258 unsigned int num_gp;
259 unsigned int num_fp;
261 /* The offset of the topmost GPR and FPR save slots from the top of
262 the frame, or zero if no such slots are needed. */
263 HOST_WIDE_INT gp_save_offset;
264 HOST_WIDE_INT fp_save_offset;
266 /* Likewise, but giving offsets from the bottom of the frame. */
267 HOST_WIDE_INT gp_sp_offset;
268 HOST_WIDE_INT fp_sp_offset;
270 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
271 HOST_WIDE_INT arg_pointer_offset;
273 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
274 HOST_WIDE_INT hard_frame_pointer_offset;
277 struct machine_function GTY(()) {
278 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
279 rtx mips16_gp_pseudo_rtx;
281 /* The number of extra stack bytes taken up by register varargs.
282 This area is allocated by the callee at the very top of the frame. */
283 int varargs_size;
285 /* The current frame information, calculated by mips_compute_frame_info. */
286 struct mips_frame_info frame;
288 /* The register to use as the function's global pointer. */
289 unsigned int global_pointer;
291 /* True if mips_adjust_insn_length should ignore an instruction's
292 hazard attribute. */
293 bool ignore_hazard_length_p;
295 /* True if the whole function is suitable for .set noreorder and
296 .set nomacro. */
297 bool all_noreorder_p;
299 /* True if the function is known to have an instruction that needs $gp. */
300 bool has_gp_insn_p;
302 /* True if we have emitted an instruction to initialize
303 mips16_gp_pseudo_rtx. */
304 bool initialized_mips16_gp_pseudo_p;
307 /* Information about a single argument. */
308 struct mips_arg_info {
309 /* True if the argument is passed in a floating-point register, or
310 would have been if we hadn't run out of registers. */
311 bool fpr_p;
313 /* The number of words passed in registers, rounded up. */
314 unsigned int reg_words;
316 /* For EABI, the offset of the first register from GP_ARG_FIRST or
317 FP_ARG_FIRST. For other ABIs, the offset of the first register from
318 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
319 comment for details).
321 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
322 on the stack. */
323 unsigned int reg_offset;
325 /* The number of words that must be passed on the stack, rounded up. */
326 unsigned int stack_words;
328 /* The offset from the start of the stack overflow area of the argument's
329 first stack word. Only meaningful when STACK_WORDS is nonzero. */
330 unsigned int stack_offset;
333 /* Information about an address described by mips_address_type.
335 ADDRESS_CONST_INT
336 No fields are used.
338 ADDRESS_REG
339 REG is the base register and OFFSET is the constant offset.
341 ADDRESS_LO_SUM
342 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
343 is the type of symbol it references.
345 ADDRESS_SYMBOLIC
346 SYMBOL_TYPE is the type of symbol that the address references. */
347 struct mips_address_info {
348 enum mips_address_type type;
349 rtx reg;
350 rtx offset;
351 enum mips_symbol_type symbol_type;
354 /* One stage in a constant building sequence. These sequences have
355 the form:
357 A = VALUE[0]
358 A = A CODE[1] VALUE[1]
359 A = A CODE[2] VALUE[2]
362 where A is an accumulator, each CODE[i] is a binary rtl operation
363 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
364 struct mips_integer_op {
365 enum rtx_code code;
366 unsigned HOST_WIDE_INT value;
369 /* The largest number of operations needed to load an integer constant.
370 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
371 When the lowest bit is clear, we can try, but reject a sequence with
372 an extra SLL at the end. */
373 #define MIPS_MAX_INTEGER_OPS 7
375 /* Information about a MIPS16e SAVE or RESTORE instruction. */
376 struct mips16e_save_restore_info {
377 /* The number of argument registers saved by a SAVE instruction.
378 0 for RESTORE instructions. */
379 unsigned int nargs;
381 /* Bit X is set if the instruction saves or restores GPR X. */
382 unsigned int mask;
384 /* The total number of bytes to allocate. */
385 HOST_WIDE_INT size;
388 /* Global variables for machine-dependent things. */
390 /* The -G setting, or the configuration's default small-data limit if
391 no -G option is given. */
392 static unsigned int mips_small_data_threshold;
394 /* The number of file directives written by mips_output_filename. */
395 int num_source_filenames;
397 /* The name that appeared in the last .file directive written by
398 mips_output_filename, or "" if mips_output_filename hasn't
399 written anything yet. */
400 const char *current_function_file = "";
402 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
403 int sdb_label_count;
405 /* Arrays that map GCC register numbers to debugger register numbers. */
406 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
407 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
409 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
410 int set_noreorder;
411 int set_nomacro;
412 static int set_noat;
414 /* True if we're writing out a branch-likely instruction rather than a
415 normal branch. */
416 static bool mips_branch_likely;
418 /* The operands passed to the last cmpMM expander. */
419 rtx cmp_operands[2];
421 /* The current instruction-set architecture. */
422 enum processor_type mips_arch;
423 const struct mips_cpu_info *mips_arch_info;
425 /* The processor that we should tune the code for. */
426 enum processor_type mips_tune;
427 const struct mips_cpu_info *mips_tune_info;
429 /* The ISA level associated with mips_arch. */
430 int mips_isa;
432 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
433 static const struct mips_cpu_info *mips_isa_option_info;
435 /* Which ABI to use. */
436 int mips_abi = MIPS_ABI_DEFAULT;
438 /* Which cost information to use. */
439 const struct mips_rtx_cost_data *mips_cost;
441 /* The ambient target flags, excluding MASK_MIPS16. */
442 static int mips_base_target_flags;
444 /* True if MIPS16 is the default mode. */
445 static bool mips_base_mips16;
447 /* The ambient values of other global variables. */
448 static int mips_base_delayed_branch; /* flag_delayed_branch */
449 static int mips_base_schedule_insns; /* flag_schedule_insns */
450 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
451 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
452 static int mips_base_align_loops; /* align_loops */
453 static int mips_base_align_jumps; /* align_jumps */
454 static int mips_base_align_functions; /* align_functions */
456 /* The -mcode-readable setting. */
457 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
459 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
460 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
462 /* Index C is true if character C is a valid PRINT_OPERAND punctation
463 character. */
464 bool mips_print_operand_punct[256];
466 static GTY (()) int mips_output_filename_first_time = 1;
468 /* mips_split_p[X] is true if symbols of type X can be split by
469 mips_split_symbol. */
470 bool mips_split_p[NUM_SYMBOL_TYPES];
472 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
473 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
474 if they are matched by a special .md file pattern. */
475 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
477 /* Likewise for HIGHs. */
478 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
480 /* Index R is the smallest register class that contains register R. */
481 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
482 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
483 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
484 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
485 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
486 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
487 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
488 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
489 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
490 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
491 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
492 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
493 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
494 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
495 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
496 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
497 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
498 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
499 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
500 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
501 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
502 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
503 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
504 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
505 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
506 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
507 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
508 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
509 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
510 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
511 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
512 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
513 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
514 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
515 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
516 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
517 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
518 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
519 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
520 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
521 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
522 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
523 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
524 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
525 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
526 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
527 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
528 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
531 /* The value of TARGET_ATTRIBUTE_TABLE. */
532 const struct attribute_spec mips_attribute_table[] = {
533 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
534 { "long_call", 0, 0, false, true, true, NULL },
535 { "far", 0, 0, false, true, true, NULL },
536 { "near", 0, 0, false, true, true, NULL },
537 /* We would really like to treat "mips16" and "nomips16" as type
538 attributes, but GCC doesn't provide the hooks we need to support
539 the right conversion rules. As declaration attributes, they affect
540 code generation but don't carry other semantics. */
541 { "mips16", 0, 0, true, false, false, NULL },
542 { "nomips16", 0, 0, true, false, false, NULL },
543 { NULL, 0, 0, false, false, false, NULL }
546 /* A table describing all the processors GCC knows about. Names are
547 matched in the order listed. The first mention of an ISA level is
548 taken as the canonical name for that ISA.
550 To ease comparison, please keep this table in the same order
551 as GAS's mips_cpu_info_table. Please also make sure that
552 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
553 options correctly. */
554 static const struct mips_cpu_info mips_cpu_info_table[] = {
555 /* Entries for generic ISAs. */
556 { "mips1", PROCESSOR_R3000, 1, 0 },
557 { "mips2", PROCESSOR_R6000, 2, 0 },
558 { "mips3", PROCESSOR_R4000, 3, 0 },
559 { "mips4", PROCESSOR_R8000, 4, 0 },
560 /* Prefer not to use branch-likely instructions for generic MIPS32rX
561 and MIPS64rX code. The instructions were officially deprecated
562 in revisions 2 and earlier, but revision 3 is likely to downgrade
563 that to a recommendation to avoid the instructions in code that
564 isn't tuned to a specific processor. */
565 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
566 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
567 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
569 /* MIPS I processors. */
570 { "r3000", PROCESSOR_R3000, 1, 0 },
571 { "r2000", PROCESSOR_R3000, 1, 0 },
572 { "r3900", PROCESSOR_R3900, 1, 0 },
574 /* MIPS II processors. */
575 { "r6000", PROCESSOR_R6000, 2, 0 },
577 /* MIPS III processors. */
578 { "r4000", PROCESSOR_R4000, 3, 0 },
579 { "vr4100", PROCESSOR_R4100, 3, 0 },
580 { "vr4111", PROCESSOR_R4111, 3, 0 },
581 { "vr4120", PROCESSOR_R4120, 3, 0 },
582 { "vr4130", PROCESSOR_R4130, 3, 0 },
583 { "vr4300", PROCESSOR_R4300, 3, 0 },
584 { "r4400", PROCESSOR_R4000, 3, 0 },
585 { "r4600", PROCESSOR_R4600, 3, 0 },
586 { "orion", PROCESSOR_R4600, 3, 0 },
587 { "r4650", PROCESSOR_R4650, 3, 0 },
588 /* ST Loongson 2E/2F processors. */
589 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
590 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
592 /* MIPS IV processors. */
593 { "r8000", PROCESSOR_R8000, 4, 0 },
594 { "vr5000", PROCESSOR_R5000, 4, 0 },
595 { "vr5400", PROCESSOR_R5400, 4, 0 },
596 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
597 { "rm7000", PROCESSOR_R7000, 4, 0 },
598 { "rm9000", PROCESSOR_R9000, 4, 0 },
600 /* MIPS32 processors. */
601 { "4kc", PROCESSOR_4KC, 32, 0 },
602 { "4km", PROCESSOR_4KC, 32, 0 },
603 { "4kp", PROCESSOR_4KP, 32, 0 },
604 { "4ksc", PROCESSOR_4KC, 32, 0 },
606 /* MIPS32 Release 2 processors. */
607 { "m4k", PROCESSOR_M4K, 33, 0 },
608 { "4kec", PROCESSOR_4KC, 33, 0 },
609 { "4kem", PROCESSOR_4KC, 33, 0 },
610 { "4kep", PROCESSOR_4KP, 33, 0 },
611 { "4ksd", PROCESSOR_4KC, 33, 0 },
613 { "24kc", PROCESSOR_24KC, 33, 0 },
614 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
615 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
616 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
617 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
618 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
620 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
621 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
622 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
623 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
624 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
625 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
627 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
628 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
629 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
630 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
631 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
632 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
634 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
635 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
636 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
637 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
638 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
639 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
640 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
642 /* MIPS64 processors. */
643 { "5kc", PROCESSOR_5KC, 64, 0 },
644 { "5kf", PROCESSOR_5KF, 64, 0 },
645 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
646 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
647 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
648 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
649 { "xlr", PROCESSOR_XLR, 64, 0 }
652 /* Default costs. If these are used for a processor we should look
653 up the actual costs. */
654 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
655 COSTS_N_INSNS (7), /* fp_mult_sf */ \
656 COSTS_N_INSNS (8), /* fp_mult_df */ \
657 COSTS_N_INSNS (23), /* fp_div_sf */ \
658 COSTS_N_INSNS (36), /* fp_div_df */ \
659 COSTS_N_INSNS (10), /* int_mult_si */ \
660 COSTS_N_INSNS (10), /* int_mult_di */ \
661 COSTS_N_INSNS (69), /* int_div_si */ \
662 COSTS_N_INSNS (69), /* int_div_di */ \
663 2, /* branch_cost */ \
664 4 /* memory_latency */
666 /* Floating-point costs for processors without an FPU. Just assume that
667 all floating-point libcalls are very expensive. */
668 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
669 COSTS_N_INSNS (256), /* fp_mult_sf */ \
670 COSTS_N_INSNS (256), /* fp_mult_df */ \
671 COSTS_N_INSNS (256), /* fp_div_sf */ \
672 COSTS_N_INSNS (256) /* fp_div_df */
674 /* Costs to use when optimizing for size. */
675 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
676 COSTS_N_INSNS (1), /* fp_add */
677 COSTS_N_INSNS (1), /* fp_mult_sf */
678 COSTS_N_INSNS (1), /* fp_mult_df */
679 COSTS_N_INSNS (1), /* fp_div_sf */
680 COSTS_N_INSNS (1), /* fp_div_df */
681 COSTS_N_INSNS (1), /* int_mult_si */
682 COSTS_N_INSNS (1), /* int_mult_di */
683 COSTS_N_INSNS (1), /* int_div_si */
684 COSTS_N_INSNS (1), /* int_div_di */
685 2, /* branch_cost */
686 4 /* memory_latency */
689 /* Costs to use when optimizing for speed, indexed by processor. */
690 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
691 { /* R3000 */
692 COSTS_N_INSNS (2), /* fp_add */
693 COSTS_N_INSNS (4), /* fp_mult_sf */
694 COSTS_N_INSNS (5), /* fp_mult_df */
695 COSTS_N_INSNS (12), /* fp_div_sf */
696 COSTS_N_INSNS (19), /* fp_div_df */
697 COSTS_N_INSNS (12), /* int_mult_si */
698 COSTS_N_INSNS (12), /* int_mult_di */
699 COSTS_N_INSNS (35), /* int_div_si */
700 COSTS_N_INSNS (35), /* int_div_di */
701 1, /* branch_cost */
702 4 /* memory_latency */
704 { /* 4KC */
705 SOFT_FP_COSTS,
706 COSTS_N_INSNS (6), /* int_mult_si */
707 COSTS_N_INSNS (6), /* int_mult_di */
708 COSTS_N_INSNS (36), /* int_div_si */
709 COSTS_N_INSNS (36), /* int_div_di */
710 1, /* branch_cost */
711 4 /* memory_latency */
713 { /* 4KP */
714 SOFT_FP_COSTS,
715 COSTS_N_INSNS (36), /* int_mult_si */
716 COSTS_N_INSNS (36), /* int_mult_di */
717 COSTS_N_INSNS (37), /* int_div_si */
718 COSTS_N_INSNS (37), /* int_div_di */
719 1, /* branch_cost */
720 4 /* memory_latency */
722 { /* 5KC */
723 SOFT_FP_COSTS,
724 COSTS_N_INSNS (4), /* int_mult_si */
725 COSTS_N_INSNS (11), /* int_mult_di */
726 COSTS_N_INSNS (36), /* int_div_si */
727 COSTS_N_INSNS (68), /* int_div_di */
728 1, /* branch_cost */
729 4 /* memory_latency */
731 { /* 5KF */
732 COSTS_N_INSNS (4), /* fp_add */
733 COSTS_N_INSNS (4), /* fp_mult_sf */
734 COSTS_N_INSNS (5), /* fp_mult_df */
735 COSTS_N_INSNS (17), /* fp_div_sf */
736 COSTS_N_INSNS (32), /* fp_div_df */
737 COSTS_N_INSNS (4), /* int_mult_si */
738 COSTS_N_INSNS (11), /* int_mult_di */
739 COSTS_N_INSNS (36), /* int_div_si */
740 COSTS_N_INSNS (68), /* int_div_di */
741 1, /* branch_cost */
742 4 /* memory_latency */
744 { /* 20KC */
745 COSTS_N_INSNS (4), /* fp_add */
746 COSTS_N_INSNS (4), /* fp_mult_sf */
747 COSTS_N_INSNS (5), /* fp_mult_df */
748 COSTS_N_INSNS (17), /* fp_div_sf */
749 COSTS_N_INSNS (32), /* fp_div_df */
750 COSTS_N_INSNS (4), /* int_mult_si */
751 COSTS_N_INSNS (7), /* int_mult_di */
752 COSTS_N_INSNS (42), /* int_div_si */
753 COSTS_N_INSNS (72), /* int_div_di */
754 1, /* branch_cost */
755 4 /* memory_latency */
757 { /* 24KC */
758 SOFT_FP_COSTS,
759 COSTS_N_INSNS (5), /* int_mult_si */
760 COSTS_N_INSNS (5), /* int_mult_di */
761 COSTS_N_INSNS (41), /* int_div_si */
762 COSTS_N_INSNS (41), /* int_div_di */
763 1, /* branch_cost */
764 4 /* memory_latency */
766 { /* 24KF2_1 */
767 COSTS_N_INSNS (8), /* fp_add */
768 COSTS_N_INSNS (8), /* fp_mult_sf */
769 COSTS_N_INSNS (10), /* fp_mult_df */
770 COSTS_N_INSNS (34), /* fp_div_sf */
771 COSTS_N_INSNS (64), /* fp_div_df */
772 COSTS_N_INSNS (5), /* int_mult_si */
773 COSTS_N_INSNS (5), /* int_mult_di */
774 COSTS_N_INSNS (41), /* int_div_si */
775 COSTS_N_INSNS (41), /* int_div_di */
776 1, /* branch_cost */
777 4 /* memory_latency */
779 { /* 24KF1_1 */
780 COSTS_N_INSNS (4), /* fp_add */
781 COSTS_N_INSNS (4), /* fp_mult_sf */
782 COSTS_N_INSNS (5), /* fp_mult_df */
783 COSTS_N_INSNS (17), /* fp_div_sf */
784 COSTS_N_INSNS (32), /* fp_div_df */
785 COSTS_N_INSNS (5), /* int_mult_si */
786 COSTS_N_INSNS (5), /* int_mult_di */
787 COSTS_N_INSNS (41), /* int_div_si */
788 COSTS_N_INSNS (41), /* int_div_di */
789 1, /* branch_cost */
790 4 /* memory_latency */
792 { /* 74KC */
793 SOFT_FP_COSTS,
794 COSTS_N_INSNS (5), /* int_mult_si */
795 COSTS_N_INSNS (5), /* int_mult_di */
796 COSTS_N_INSNS (41), /* int_div_si */
797 COSTS_N_INSNS (41), /* int_div_di */
798 1, /* branch_cost */
799 4 /* memory_latency */
801 { /* 74KF2_1 */
802 COSTS_N_INSNS (8), /* fp_add */
803 COSTS_N_INSNS (8), /* fp_mult_sf */
804 COSTS_N_INSNS (10), /* fp_mult_df */
805 COSTS_N_INSNS (34), /* fp_div_sf */
806 COSTS_N_INSNS (64), /* fp_div_df */
807 COSTS_N_INSNS (5), /* int_mult_si */
808 COSTS_N_INSNS (5), /* int_mult_di */
809 COSTS_N_INSNS (41), /* int_div_si */
810 COSTS_N_INSNS (41), /* int_div_di */
811 1, /* branch_cost */
812 4 /* memory_latency */
814 { /* 74KF1_1 */
815 COSTS_N_INSNS (4), /* fp_add */
816 COSTS_N_INSNS (4), /* fp_mult_sf */
817 COSTS_N_INSNS (5), /* fp_mult_df */
818 COSTS_N_INSNS (17), /* fp_div_sf */
819 COSTS_N_INSNS (32), /* fp_div_df */
820 COSTS_N_INSNS (5), /* int_mult_si */
821 COSTS_N_INSNS (5), /* int_mult_di */
822 COSTS_N_INSNS (41), /* int_div_si */
823 COSTS_N_INSNS (41), /* int_div_di */
824 1, /* branch_cost */
825 4 /* memory_latency */
827 { /* 74KF3_2 */
828 COSTS_N_INSNS (6), /* fp_add */
829 COSTS_N_INSNS (6), /* fp_mult_sf */
830 COSTS_N_INSNS (7), /* fp_mult_df */
831 COSTS_N_INSNS (25), /* fp_div_sf */
832 COSTS_N_INSNS (48), /* fp_div_df */
833 COSTS_N_INSNS (5), /* int_mult_si */
834 COSTS_N_INSNS (5), /* int_mult_di */
835 COSTS_N_INSNS (41), /* int_div_si */
836 COSTS_N_INSNS (41), /* int_div_di */
837 1, /* branch_cost */
838 4 /* memory_latency */
840 { /* Loongson-2E */
841 DEFAULT_COSTS
843 { /* Loongson-2F */
844 DEFAULT_COSTS
846 { /* M4k */
847 DEFAULT_COSTS
849 { /* R3900 */
850 COSTS_N_INSNS (2), /* fp_add */
851 COSTS_N_INSNS (4), /* fp_mult_sf */
852 COSTS_N_INSNS (5), /* fp_mult_df */
853 COSTS_N_INSNS (12), /* fp_div_sf */
854 COSTS_N_INSNS (19), /* fp_div_df */
855 COSTS_N_INSNS (2), /* int_mult_si */
856 COSTS_N_INSNS (2), /* int_mult_di */
857 COSTS_N_INSNS (35), /* int_div_si */
858 COSTS_N_INSNS (35), /* int_div_di */
859 1, /* branch_cost */
860 4 /* memory_latency */
862 { /* R6000 */
863 COSTS_N_INSNS (3), /* fp_add */
864 COSTS_N_INSNS (5), /* fp_mult_sf */
865 COSTS_N_INSNS (6), /* fp_mult_df */
866 COSTS_N_INSNS (15), /* fp_div_sf */
867 COSTS_N_INSNS (16), /* fp_div_df */
868 COSTS_N_INSNS (17), /* int_mult_si */
869 COSTS_N_INSNS (17), /* int_mult_di */
870 COSTS_N_INSNS (38), /* int_div_si */
871 COSTS_N_INSNS (38), /* int_div_di */
872 2, /* branch_cost */
873 6 /* memory_latency */
875 { /* R4000 */
876 COSTS_N_INSNS (6), /* fp_add */
877 COSTS_N_INSNS (7), /* fp_mult_sf */
878 COSTS_N_INSNS (8), /* fp_mult_df */
879 COSTS_N_INSNS (23), /* fp_div_sf */
880 COSTS_N_INSNS (36), /* fp_div_df */
881 COSTS_N_INSNS (10), /* int_mult_si */
882 COSTS_N_INSNS (10), /* int_mult_di */
883 COSTS_N_INSNS (69), /* int_div_si */
884 COSTS_N_INSNS (69), /* int_div_di */
885 2, /* branch_cost */
886 6 /* memory_latency */
888 { /* R4100 */
889 DEFAULT_COSTS
891 { /* R4111 */
892 DEFAULT_COSTS
894 { /* R4120 */
895 DEFAULT_COSTS
897 { /* R4130 */
898 /* The only costs that appear to be updated here are
899 integer multiplication. */
900 SOFT_FP_COSTS,
901 COSTS_N_INSNS (4), /* int_mult_si */
902 COSTS_N_INSNS (6), /* int_mult_di */
903 COSTS_N_INSNS (69), /* int_div_si */
904 COSTS_N_INSNS (69), /* int_div_di */
905 1, /* branch_cost */
906 4 /* memory_latency */
908 { /* R4300 */
909 DEFAULT_COSTS
911 { /* R4600 */
912 DEFAULT_COSTS
914 { /* R4650 */
915 DEFAULT_COSTS
917 { /* R5000 */
918 COSTS_N_INSNS (6), /* fp_add */
919 COSTS_N_INSNS (4), /* fp_mult_sf */
920 COSTS_N_INSNS (5), /* fp_mult_df */
921 COSTS_N_INSNS (23), /* fp_div_sf */
922 COSTS_N_INSNS (36), /* fp_div_df */
923 COSTS_N_INSNS (5), /* int_mult_si */
924 COSTS_N_INSNS (5), /* int_mult_di */
925 COSTS_N_INSNS (36), /* int_div_si */
926 COSTS_N_INSNS (36), /* int_div_di */
927 1, /* branch_cost */
928 4 /* memory_latency */
930 { /* R5400 */
931 COSTS_N_INSNS (6), /* fp_add */
932 COSTS_N_INSNS (5), /* fp_mult_sf */
933 COSTS_N_INSNS (6), /* fp_mult_df */
934 COSTS_N_INSNS (30), /* fp_div_sf */
935 COSTS_N_INSNS (59), /* fp_div_df */
936 COSTS_N_INSNS (3), /* int_mult_si */
937 COSTS_N_INSNS (4), /* int_mult_di */
938 COSTS_N_INSNS (42), /* int_div_si */
939 COSTS_N_INSNS (74), /* int_div_di */
940 1, /* branch_cost */
941 4 /* memory_latency */
943 { /* R5500 */
944 COSTS_N_INSNS (6), /* fp_add */
945 COSTS_N_INSNS (5), /* fp_mult_sf */
946 COSTS_N_INSNS (6), /* fp_mult_df */
947 COSTS_N_INSNS (30), /* fp_div_sf */
948 COSTS_N_INSNS (59), /* fp_div_df */
949 COSTS_N_INSNS (5), /* int_mult_si */
950 COSTS_N_INSNS (9), /* int_mult_di */
951 COSTS_N_INSNS (42), /* int_div_si */
952 COSTS_N_INSNS (74), /* int_div_di */
953 1, /* branch_cost */
954 4 /* memory_latency */
956 { /* R7000 */
957 /* The only costs that are changed here are
958 integer multiplication. */
959 COSTS_N_INSNS (6), /* fp_add */
960 COSTS_N_INSNS (7), /* fp_mult_sf */
961 COSTS_N_INSNS (8), /* fp_mult_df */
962 COSTS_N_INSNS (23), /* fp_div_sf */
963 COSTS_N_INSNS (36), /* fp_div_df */
964 COSTS_N_INSNS (5), /* int_mult_si */
965 COSTS_N_INSNS (9), /* int_mult_di */
966 COSTS_N_INSNS (69), /* int_div_si */
967 COSTS_N_INSNS (69), /* int_div_di */
968 1, /* branch_cost */
969 4 /* memory_latency */
971 { /* R8000 */
972 DEFAULT_COSTS
974 { /* R9000 */
975 /* The only costs that are changed here are
976 integer multiplication. */
977 COSTS_N_INSNS (6), /* fp_add */
978 COSTS_N_INSNS (7), /* fp_mult_sf */
979 COSTS_N_INSNS (8), /* fp_mult_df */
980 COSTS_N_INSNS (23), /* fp_div_sf */
981 COSTS_N_INSNS (36), /* fp_div_df */
982 COSTS_N_INSNS (3), /* int_mult_si */
983 COSTS_N_INSNS (8), /* int_mult_di */
984 COSTS_N_INSNS (69), /* int_div_si */
985 COSTS_N_INSNS (69), /* int_div_di */
986 1, /* branch_cost */
987 4 /* memory_latency */
989 { /* SB1 */
990 /* These costs are the same as the SB-1A below. */
991 COSTS_N_INSNS (4), /* fp_add */
992 COSTS_N_INSNS (4), /* fp_mult_sf */
993 COSTS_N_INSNS (4), /* fp_mult_df */
994 COSTS_N_INSNS (24), /* fp_div_sf */
995 COSTS_N_INSNS (32), /* fp_div_df */
996 COSTS_N_INSNS (3), /* int_mult_si */
997 COSTS_N_INSNS (4), /* int_mult_di */
998 COSTS_N_INSNS (36), /* int_div_si */
999 COSTS_N_INSNS (68), /* int_div_di */
1000 1, /* branch_cost */
1001 4 /* memory_latency */
1003 { /* SB1-A */
1004 /* These costs are the same as the SB-1 above. */
1005 COSTS_N_INSNS (4), /* fp_add */
1006 COSTS_N_INSNS (4), /* fp_mult_sf */
1007 COSTS_N_INSNS (4), /* fp_mult_df */
1008 COSTS_N_INSNS (24), /* fp_div_sf */
1009 COSTS_N_INSNS (32), /* fp_div_df */
1010 COSTS_N_INSNS (3), /* int_mult_si */
1011 COSTS_N_INSNS (4), /* int_mult_di */
1012 COSTS_N_INSNS (36), /* int_div_si */
1013 COSTS_N_INSNS (68), /* int_div_di */
1014 1, /* branch_cost */
1015 4 /* memory_latency */
1017 { /* SR71000 */
1018 DEFAULT_COSTS
1020 { /* XLR */
1021 /* Need to replace first five with the costs of calling the appropriate
1022 libgcc routine. */
1023 COSTS_N_INSNS (256), /* fp_add */
1024 COSTS_N_INSNS (256), /* fp_mult_sf */
1025 COSTS_N_INSNS (256), /* fp_mult_df */
1026 COSTS_N_INSNS (256), /* fp_div_sf */
1027 COSTS_N_INSNS (256), /* fp_div_df */
1028 COSTS_N_INSNS (8), /* int_mult_si */
1029 COSTS_N_INSNS (8), /* int_mult_di */
1030 COSTS_N_INSNS (72), /* int_div_si */
1031 COSTS_N_INSNS (72), /* int_div_di */
1032 1, /* branch_cost */
1033 4 /* memory_latency */
1037 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1038 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1039 struct mflip_mips16_entry GTY (()) {
1040 const char *name;
1041 bool mips16_p;
1043 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1045 /* Hash table callbacks for mflip_mips16_htab. */
1047 static hashval_t
1048 mflip_mips16_htab_hash (const void *entry)
1050 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1053 static int
1054 mflip_mips16_htab_eq (const void *entry, const void *name)
1056 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1057 (const char *) name) == 0;
1060 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1061 mode, false if it should next add an attribute for the opposite mode. */
1062 static GTY(()) bool mips16_flipper;
1064 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1065 for -mflip-mips16. Return true if it should use "mips16" and false if
1066 it should use "nomips16". */
1068 static bool
1069 mflip_mips16_use_mips16_p (tree decl)
1071 struct mflip_mips16_entry *entry;
1072 const char *name;
1073 hashval_t hash;
1074 void **slot;
1076 /* Use the opposite of the command-line setting for anonymous decls. */
1077 if (!DECL_NAME (decl))
1078 return !mips_base_mips16;
1080 if (!mflip_mips16_htab)
1081 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1082 mflip_mips16_htab_eq, NULL);
1084 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1085 hash = htab_hash_string (name);
1086 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1087 entry = (struct mflip_mips16_entry *) *slot;
1088 if (!entry)
1090 mips16_flipper = !mips16_flipper;
1091 entry = GGC_NEW (struct mflip_mips16_entry);
1092 entry->name = name;
1093 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1094 *slot = entry;
1096 return entry->mips16_p;
1099 /* Predicates to test for presence of "near" and "far"/"long_call"
1100 attributes on the given TYPE. */
1102 static bool
1103 mips_near_type_p (const_tree type)
1105 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1108 static bool
1109 mips_far_type_p (const_tree type)
1111 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1112 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1115 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1117 static bool
1118 mips_mips16_decl_p (const_tree decl)
1120 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1123 static bool
1124 mips_nomips16_decl_p (const_tree decl)
1126 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1129 /* Return true if function DECL is a MIPS16 function. Return the ambient
1130 setting if DECL is null. */
1132 static bool
1133 mips_use_mips16_mode_p (tree decl)
1135 if (decl)
1137 /* Nested functions must use the same frame pointer as their
1138 parent and must therefore use the same ISA mode. */
1139 tree parent = decl_function_context (decl);
1140 if (parent)
1141 decl = parent;
1142 if (mips_mips16_decl_p (decl))
1143 return true;
1144 if (mips_nomips16_decl_p (decl))
1145 return false;
1147 return mips_base_mips16;
1150 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1152 static int
1153 mips_comp_type_attributes (const_tree type1, const_tree type2)
1155 /* Disallow mixed near/far attributes. */
1156 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1157 return 0;
1158 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1159 return 0;
1160 return 1;
1163 /* Implement TARGET_INSERT_ATTRIBUTES. */
1165 static void
1166 mips_insert_attributes (tree decl, tree *attributes)
1168 const char *name;
1169 bool mips16_p, nomips16_p;
1171 /* Check for "mips16" and "nomips16" attributes. */
1172 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1173 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1174 if (TREE_CODE (decl) != FUNCTION_DECL)
1176 if (mips16_p)
1177 error ("%qs attribute only applies to functions", "mips16");
1178 if (nomips16_p)
1179 error ("%qs attribute only applies to functions", "nomips16");
1181 else
1183 mips16_p |= mips_mips16_decl_p (decl);
1184 nomips16_p |= mips_nomips16_decl_p (decl);
1185 if (mips16_p || nomips16_p)
1187 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1188 if (mips16_p && nomips16_p)
1189 error ("%qs cannot have both %<mips16%> and "
1190 "%<nomips16%> attributes",
1191 IDENTIFIER_POINTER (DECL_NAME (decl)));
1193 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1195 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1196 "mips16" attribute, arbitrarily pick one. We must pick the same
1197 setting for duplicate declarations of a function. */
1198 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1199 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1204 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1206 static tree
1207 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1209 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1210 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1211 error ("%qs redeclared with conflicting %qs attributes",
1212 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1213 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1214 error ("%qs redeclared with conflicting %qs attributes",
1215 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1217 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1218 DECL_ATTRIBUTES (newdecl));
1221 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1222 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1224 static void
1225 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1227 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1229 *base_ptr = XEXP (x, 0);
1230 *offset_ptr = INTVAL (XEXP (x, 1));
1232 else
1234 *base_ptr = x;
1235 *offset_ptr = 0;
1239 static unsigned int mips_build_integer (struct mips_integer_op *,
1240 unsigned HOST_WIDE_INT);
1242 /* A subroutine of mips_build_integer, with the same interface.
1243 Assume that the final action in the sequence should be a left shift. */
1245 static unsigned int
1246 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1248 unsigned int i, shift;
1250 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1251 since signed numbers are easier to load than unsigned ones. */
1252 shift = 0;
1253 while ((value & 1) == 0)
1254 value /= 2, shift++;
1256 i = mips_build_integer (codes, value);
1257 codes[i].code = ASHIFT;
1258 codes[i].value = shift;
1259 return i + 1;
1262 /* As for mips_build_shift, but assume that the final action will be
1263 an IOR or PLUS operation. */
1265 static unsigned int
1266 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1268 unsigned HOST_WIDE_INT high;
1269 unsigned int i;
1271 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1272 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1274 /* The constant is too complex to load with a simple LUI/ORI pair,
1275 so we want to give the recursive call as many trailing zeros as
1276 possible. In this case, we know bit 16 is set and that the
1277 low 16 bits form a negative number. If we subtract that number
1278 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1279 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1280 codes[i].code = PLUS;
1281 codes[i].value = CONST_LOW_PART (value);
1283 else
1285 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1286 bits gives a value with at least 17 trailing zeros. */
1287 i = mips_build_integer (codes, high);
1288 codes[i].code = IOR;
1289 codes[i].value = value & 0xffff;
1291 return i + 1;
1294 /* Fill CODES with a sequence of rtl operations to load VALUE.
1295 Return the number of operations needed. */
1297 static unsigned int
1298 mips_build_integer (struct mips_integer_op *codes,
1299 unsigned HOST_WIDE_INT value)
1301 if (SMALL_OPERAND (value)
1302 || SMALL_OPERAND_UNSIGNED (value)
1303 || LUI_OPERAND (value))
1305 /* The value can be loaded with a single instruction. */
1306 codes[0].code = UNKNOWN;
1307 codes[0].value = value;
1308 return 1;
1310 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1312 /* Either the constant is a simple LUI/ORI combination or its
1313 lowest bit is set. We don't want to shift in this case. */
1314 return mips_build_lower (codes, value);
1316 else if ((value & 0xffff) == 0)
1318 /* The constant will need at least three actions. The lowest
1319 16 bits are clear, so the final action will be a shift. */
1320 return mips_build_shift (codes, value);
1322 else
1324 /* The final action could be a shift, add or inclusive OR.
1325 Rather than use a complex condition to select the best
1326 approach, try both mips_build_shift and mips_build_lower
1327 and pick the one that gives the shortest sequence.
1328 Note that this case is only used once per constant. */
1329 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1330 unsigned int cost, alt_cost;
1332 cost = mips_build_shift (codes, value);
1333 alt_cost = mips_build_lower (alt_codes, value);
1334 if (alt_cost < cost)
1336 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1337 cost = alt_cost;
1339 return cost;
1343 /* Return true if X is a thread-local symbol. */
1345 static bool
1346 mips_tls_symbol_p (rtx x)
1348 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1351 /* Return true if SYMBOL_REF X is associated with a global symbol
1352 (in the STB_GLOBAL sense). */
1354 static bool
1355 mips_global_symbol_p (const_rtx x)
1357 const_tree decl = SYMBOL_REF_DECL (x);
1359 if (!decl)
1360 return !SYMBOL_REF_LOCAL_P (x);
1362 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1363 or weak symbols. Relocations in the object file will be against
1364 the target symbol, so it's that symbol's binding that matters here. */
1365 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1368 /* Return true if SYMBOL_REF X binds locally. */
1370 static bool
1371 mips_symbol_binds_local_p (const_rtx x)
1373 return (SYMBOL_REF_DECL (x)
1374 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1375 : SYMBOL_REF_LOCAL_P (x));
1378 /* Return true if rtx constants of mode MODE should be put into a small
1379 data section. */
1381 static bool
1382 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1384 return (!TARGET_EMBEDDED_DATA
1385 && TARGET_LOCAL_SDATA
1386 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1389 /* Return true if X should not be moved directly into register $25.
1390 We need this because many versions of GAS will treat "la $25,foo" as
1391 part of a call sequence and so allow a global "foo" to be lazily bound. */
1393 bool
1394 mips_dangerous_for_la25_p (rtx x)
1396 return (!TARGET_EXPLICIT_RELOCS
1397 && TARGET_USE_GOT
1398 && GET_CODE (x) == SYMBOL_REF
1399 && mips_global_symbol_p (x));
1402 /* Return the method that should be used to access SYMBOL_REF or
1403 LABEL_REF X in context CONTEXT. */
1405 static enum mips_symbol_type
1406 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1408 if (TARGET_RTP_PIC)
1409 return SYMBOL_GOT_DISP;
1411 if (GET_CODE (x) == LABEL_REF)
1413 /* LABEL_REFs are used for jump tables as well as text labels.
1414 Only return SYMBOL_PC_RELATIVE if we know the label is in
1415 the text section. */
1416 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1417 return SYMBOL_PC_RELATIVE;
1419 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1420 return SYMBOL_GOT_PAGE_OFST;
1422 return SYMBOL_ABSOLUTE;
1425 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1427 if (SYMBOL_REF_TLS_MODEL (x))
1428 return SYMBOL_TLS;
1430 if (CONSTANT_POOL_ADDRESS_P (x))
1432 if (TARGET_MIPS16_TEXT_LOADS)
1433 return SYMBOL_PC_RELATIVE;
1435 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1436 return SYMBOL_PC_RELATIVE;
1438 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1439 return SYMBOL_GP_RELATIVE;
1442 /* Do not use small-data accesses for weak symbols; they may end up
1443 being zero. */
1444 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1445 return SYMBOL_GP_RELATIVE;
1447 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1448 is in effect. */
1449 if (TARGET_ABICALLS
1450 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1452 /* There are three cases to consider:
1454 - o32 PIC (either with or without explicit relocs)
1455 - n32/n64 PIC without explicit relocs
1456 - n32/n64 PIC with explicit relocs
1458 In the first case, both local and global accesses will use an
1459 R_MIPS_GOT16 relocation. We must correctly predict which of
1460 the two semantics (local or global) the assembler and linker
1461 will apply. The choice depends on the symbol's binding rather
1462 than its visibility.
1464 In the second case, the assembler will not use R_MIPS_GOT16
1465 relocations, but it chooses between local and global accesses
1466 in the same way as for o32 PIC.
1468 In the third case we have more freedom since both forms of
1469 access will work for any kind of symbol. However, there seems
1470 little point in doing things differently. */
1471 if (mips_global_symbol_p (x))
1472 return SYMBOL_GOT_DISP;
1474 return SYMBOL_GOT_PAGE_OFST;
1477 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1478 return SYMBOL_FORCE_TO_MEM;
1480 return SYMBOL_ABSOLUTE;
1483 /* Classify the base of symbolic expression X, given that X appears in
1484 context CONTEXT. */
1486 static enum mips_symbol_type
1487 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1489 rtx offset;
1491 split_const (x, &x, &offset);
1492 if (UNSPEC_ADDRESS_P (x))
1493 return UNSPEC_ADDRESS_TYPE (x);
1495 return mips_classify_symbol (x, context);
1498 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1499 is the alignment in bytes of SYMBOL_REF X. */
1501 static bool
1502 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1504 HOST_WIDE_INT align;
1506 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1507 return IN_RANGE (offset, 0, align - 1);
1510 /* Return true if X is a symbolic constant that can be used in context
1511 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1513 bool
1514 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1515 enum mips_symbol_type *symbol_type)
1517 rtx offset;
1519 split_const (x, &x, &offset);
1520 if (UNSPEC_ADDRESS_P (x))
1522 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1523 x = UNSPEC_ADDRESS (x);
1525 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1527 *symbol_type = mips_classify_symbol (x, context);
1528 if (*symbol_type == SYMBOL_TLS)
1529 return false;
1531 else
1532 return false;
1534 if (offset == const0_rtx)
1535 return true;
1537 /* Check whether a nonzero offset is valid for the underlying
1538 relocations. */
1539 switch (*symbol_type)
1541 case SYMBOL_ABSOLUTE:
1542 case SYMBOL_FORCE_TO_MEM:
1543 case SYMBOL_32_HIGH:
1544 case SYMBOL_64_HIGH:
1545 case SYMBOL_64_MID:
1546 case SYMBOL_64_LOW:
1547 /* If the target has 64-bit pointers and the object file only
1548 supports 32-bit symbols, the values of those symbols will be
1549 sign-extended. In this case we can't allow an arbitrary offset
1550 in case the 32-bit value X + OFFSET has a different sign from X. */
1551 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1552 return offset_within_block_p (x, INTVAL (offset));
1554 /* In other cases the relocations can handle any offset. */
1555 return true;
1557 case SYMBOL_PC_RELATIVE:
1558 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1559 In this case, we no longer have access to the underlying constant,
1560 but the original symbol-based access was known to be valid. */
1561 if (GET_CODE (x) == LABEL_REF)
1562 return true;
1564 /* Fall through. */
1566 case SYMBOL_GP_RELATIVE:
1567 /* Make sure that the offset refers to something within the
1568 same object block. This should guarantee that the final
1569 PC- or GP-relative offset is within the 16-bit limit. */
1570 return offset_within_block_p (x, INTVAL (offset));
1572 case SYMBOL_GOT_PAGE_OFST:
1573 case SYMBOL_GOTOFF_PAGE:
1574 /* If the symbol is global, the GOT entry will contain the symbol's
1575 address, and we will apply a 16-bit offset after loading it.
1576 If the symbol is local, the linker should provide enough local
1577 GOT entries for a 16-bit offset, but larger offsets may lead
1578 to GOT overflow. */
1579 return SMALL_INT (offset);
1581 case SYMBOL_TPREL:
1582 case SYMBOL_DTPREL:
1583 /* There is no carry between the HI and LO REL relocations, so the
1584 offset is only valid if we know it won't lead to such a carry. */
1585 return mips_offset_within_alignment_p (x, INTVAL (offset));
1587 case SYMBOL_GOT_DISP:
1588 case SYMBOL_GOTOFF_DISP:
1589 case SYMBOL_GOTOFF_CALL:
1590 case SYMBOL_GOTOFF_LOADGP:
1591 case SYMBOL_TLSGD:
1592 case SYMBOL_TLSLDM:
1593 case SYMBOL_GOTTPREL:
1594 case SYMBOL_TLS:
1595 case SYMBOL_HALF:
1596 return false;
1598 gcc_unreachable ();
1601 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1602 single instruction. We rely on the fact that, in the worst case,
1603 all instructions involved in a MIPS16 address calculation are usually
1604 extended ones. */
1606 static int
1607 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1609 switch (type)
1611 case SYMBOL_ABSOLUTE:
1612 /* When using 64-bit symbols, we need 5 preparatory instructions,
1613 such as:
1615 lui $at,%highest(symbol)
1616 daddiu $at,$at,%higher(symbol)
1617 dsll $at,$at,16
1618 daddiu $at,$at,%hi(symbol)
1619 dsll $at,$at,16
1621 The final address is then $at + %lo(symbol). With 32-bit
1622 symbols we just need a preparatory LUI for normal mode and
1623 a preparatory LI and SLL for MIPS16. */
1624 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1626 case SYMBOL_GP_RELATIVE:
1627 /* Treat GP-relative accesses as taking a single instruction on
1628 MIPS16 too; the copy of $gp can often be shared. */
1629 return 1;
1631 case SYMBOL_PC_RELATIVE:
1632 /* PC-relative constants can be only be used with ADDIUPC,
1633 DADDIUPC, LWPC and LDPC. */
1634 if (mode == MAX_MACHINE_MODE
1635 || GET_MODE_SIZE (mode) == 4
1636 || GET_MODE_SIZE (mode) == 8)
1637 return 1;
1639 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1640 return 0;
1642 case SYMBOL_FORCE_TO_MEM:
1643 /* LEAs will be converted into constant-pool references by
1644 mips_reorg. */
1645 if (mode == MAX_MACHINE_MODE)
1646 return 1;
1648 /* The constant must be loaded and then dereferenced. */
1649 return 0;
1651 case SYMBOL_GOT_DISP:
1652 /* The constant will have to be loaded from the GOT before it
1653 is used in an address. */
1654 if (mode != MAX_MACHINE_MODE)
1655 return 0;
1657 /* Fall through. */
1659 case SYMBOL_GOT_PAGE_OFST:
1660 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1661 local/global classification is accurate. The worst cases are:
1663 (1) For local symbols when generating o32 or o64 code. The assembler
1664 will use:
1666 lw $at,%got(symbol)
1669 ...and the final address will be $at + %lo(symbol).
1671 (2) For global symbols when -mxgot. The assembler will use:
1673 lui $at,%got_hi(symbol)
1674 (d)addu $at,$at,$gp
1676 ...and the final address will be $at + %got_lo(symbol). */
1677 return 3;
1679 case SYMBOL_GOTOFF_PAGE:
1680 case SYMBOL_GOTOFF_DISP:
1681 case SYMBOL_GOTOFF_CALL:
1682 case SYMBOL_GOTOFF_LOADGP:
1683 case SYMBOL_32_HIGH:
1684 case SYMBOL_64_HIGH:
1685 case SYMBOL_64_MID:
1686 case SYMBOL_64_LOW:
1687 case SYMBOL_TLSGD:
1688 case SYMBOL_TLSLDM:
1689 case SYMBOL_DTPREL:
1690 case SYMBOL_GOTTPREL:
1691 case SYMBOL_TPREL:
1692 case SYMBOL_HALF:
1693 /* A 16-bit constant formed by a single relocation, or a 32-bit
1694 constant formed from a high 16-bit relocation and a low 16-bit
1695 relocation. Use mips_split_p to determine which. 32-bit
1696 constants need an "lui; addiu" sequence for normal mode and
1697 an "li; sll; addiu" sequence for MIPS16 mode. */
1698 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1700 case SYMBOL_TLS:
1701 /* We don't treat a bare TLS symbol as a constant. */
1702 return 0;
1704 gcc_unreachable ();
1707 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1708 to load symbols of type TYPE into a register. Return 0 if the given
1709 type of symbol cannot be used as an immediate operand.
1711 Otherwise, return the number of instructions needed to load or store
1712 values of mode MODE to or from addresses of type TYPE. Return 0 if
1713 the given type of symbol is not valid in addresses.
1715 In both cases, treat extended MIPS16 instructions as two instructions. */
1717 static int
1718 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1720 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1723 /* A for_each_rtx callback. Stop the search if *X references a
1724 thread-local symbol. */
1726 static int
1727 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1729 return mips_tls_symbol_p (*x);
1732 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1734 static bool
1735 mips_cannot_force_const_mem (rtx x)
1737 rtx base, offset;
1739 if (!TARGET_MIPS16)
1741 /* As an optimization, reject constants that mips_legitimize_move
1742 can expand inline.
1744 Suppose we have a multi-instruction sequence that loads constant C
1745 into register R. If R does not get allocated a hard register, and
1746 R is used in an operand that allows both registers and memory
1747 references, reload will consider forcing C into memory and using
1748 one of the instruction's memory alternatives. Returning false
1749 here will force it to use an input reload instead. */
1750 if (GET_CODE (x) == CONST_INT)
1751 return true;
1753 split_const (x, &base, &offset);
1754 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1755 return true;
1758 /* TLS symbols must be computed by mips_legitimize_move. */
1759 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1760 return true;
1762 return false;
1765 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1766 constants when we're using a per-function constant pool. */
1768 static bool
1769 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1770 const_rtx x ATTRIBUTE_UNUSED)
1772 return !TARGET_MIPS16_PCREL_LOADS;
1775 /* Return true if register REGNO is a valid base register for mode MODE.
1776 STRICT_P is true if REG_OK_STRICT is in effect. */
1779 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1780 bool strict_p)
1782 if (!HARD_REGISTER_NUM_P (regno))
1784 if (!strict_p)
1785 return true;
1786 regno = reg_renumber[regno];
1789 /* These fake registers will be eliminated to either the stack or
1790 hard frame pointer, both of which are usually valid base registers.
1791 Reload deals with the cases where the eliminated form isn't valid. */
1792 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1793 return true;
1795 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1796 values, nothing smaller. There are two problems here:
1798 (a) Instantiating virtual registers can introduce new uses of the
1799 stack pointer. If these virtual registers are valid addresses,
1800 the stack pointer should be too.
1802 (b) Most uses of the stack pointer are not made explicit until
1803 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1804 We don't know until that stage whether we'll be eliminating to the
1805 stack pointer (which needs the restriction) or the hard frame
1806 pointer (which doesn't).
1808 All in all, it seems more consistent to only enforce this restriction
1809 during and after reload. */
1810 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1811 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1813 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1816 /* Return true if X is a valid base register for mode MODE.
1817 STRICT_P is true if REG_OK_STRICT is in effect. */
1819 static bool
1820 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1822 if (!strict_p && GET_CODE (x) == SUBREG)
1823 x = SUBREG_REG (x);
1825 return (REG_P (x)
1826 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1829 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1830 can address a value of mode MODE. */
1832 static bool
1833 mips_valid_offset_p (rtx x, enum machine_mode mode)
1835 /* Check that X is a signed 16-bit number. */
1836 if (!const_arith_operand (x, Pmode))
1837 return false;
1839 /* We may need to split multiword moves, so make sure that every word
1840 is accessible. */
1841 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1842 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
1843 return false;
1845 return true;
1848 /* Return true if a LO_SUM can address a value of mode MODE when the
1849 LO_SUM symbol has type SYMBOL_TYPE. */
1851 static bool
1852 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
1854 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1855 of mode MODE. */
1856 if (mips_symbol_insns (symbol_type, mode) == 0)
1857 return false;
1859 /* Check that there is a known low-part relocation. */
1860 if (mips_lo_relocs[symbol_type] == NULL)
1861 return false;
1863 /* We may need to split multiword moves, so make sure that each word
1864 can be accessed without inducing a carry. This is mainly needed
1865 for o64, which has historically only guaranteed 64-bit alignment
1866 for 128-bit types. */
1867 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1868 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
1869 return false;
1871 return true;
1874 /* Return true if X is a valid address for machine mode MODE. If it is,
1875 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1876 effect. */
1878 static bool
1879 mips_classify_address (struct mips_address_info *info, rtx x,
1880 enum machine_mode mode, bool strict_p)
1882 switch (GET_CODE (x))
1884 case REG:
1885 case SUBREG:
1886 info->type = ADDRESS_REG;
1887 info->reg = x;
1888 info->offset = const0_rtx;
1889 return mips_valid_base_register_p (info->reg, mode, strict_p);
1891 case PLUS:
1892 info->type = ADDRESS_REG;
1893 info->reg = XEXP (x, 0);
1894 info->offset = XEXP (x, 1);
1895 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1896 && mips_valid_offset_p (info->offset, mode));
1898 case LO_SUM:
1899 info->type = ADDRESS_LO_SUM;
1900 info->reg = XEXP (x, 0);
1901 info->offset = XEXP (x, 1);
1902 /* We have to trust the creator of the LO_SUM to do something vaguely
1903 sane. Target-independent code that creates a LO_SUM should also
1904 create and verify the matching HIGH. Target-independent code that
1905 adds an offset to a LO_SUM must prove that the offset will not
1906 induce a carry. Failure to do either of these things would be
1907 a bug, and we are not required to check for it here. The MIPS
1908 backend itself should only create LO_SUMs for valid symbolic
1909 constants, with the high part being either a HIGH or a copy
1910 of _gp. */
1911 info->symbol_type
1912 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1913 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1914 && mips_valid_lo_sum_p (info->symbol_type, mode));
1916 case CONST_INT:
1917 /* Small-integer addresses don't occur very often, but they
1918 are legitimate if $0 is a valid base register. */
1919 info->type = ADDRESS_CONST_INT;
1920 return !TARGET_MIPS16 && SMALL_INT (x);
1922 case CONST:
1923 case LABEL_REF:
1924 case SYMBOL_REF:
1925 info->type = ADDRESS_SYMBOLIC;
1926 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1927 &info->symbol_type)
1928 && mips_symbol_insns (info->symbol_type, mode) > 0
1929 && !mips_split_p[info->symbol_type]);
1931 default:
1932 return false;
1936 /* Return true if X is a legitimate address for a memory operand of mode
1937 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1939 bool
1940 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1942 struct mips_address_info addr;
1944 return mips_classify_address (&addr, x, mode, strict_p);
1947 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1949 bool
1950 mips_stack_address_p (rtx x, enum machine_mode mode)
1952 struct mips_address_info addr;
1954 return (mips_classify_address (&addr, x, mode, false)
1955 && addr.type == ADDRESS_REG
1956 && addr.reg == stack_pointer_rtx);
1959 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1960 address instruction. Note that such addresses are not considered
1961 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1962 is so restricted. */
1964 static bool
1965 mips_lwxs_address_p (rtx addr)
1967 if (ISA_HAS_LWXS
1968 && GET_CODE (addr) == PLUS
1969 && REG_P (XEXP (addr, 1)))
1971 rtx offset = XEXP (addr, 0);
1972 if (GET_CODE (offset) == MULT
1973 && REG_P (XEXP (offset, 0))
1974 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1975 && INTVAL (XEXP (offset, 1)) == 4)
1976 return true;
1978 return false;
1981 /* Return true if a value at OFFSET bytes from base register BASE can be
1982 accessed using an unextended MIPS16 instruction. MODE is the mode of
1983 the value.
1985 Usually the offset in an unextended instruction is a 5-bit field.
1986 The offset is unsigned and shifted left once for LH and SH, twice
1987 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1988 an 8-bit immediate field that's shifted left twice. */
1990 static bool
1991 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
1992 unsigned HOST_WIDE_INT offset)
1994 if (offset % GET_MODE_SIZE (mode) == 0)
1996 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1997 return offset < 256U * GET_MODE_SIZE (mode);
1998 return offset < 32U * GET_MODE_SIZE (mode);
2000 return false;
2003 /* Return the number of instructions needed to load or store a value
2004 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2005 Assume that multiword moves may need to be split into word moves
2006 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2007 enough.
2009 For MIPS16 code, count extended instructions as two instructions. */
2012 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2014 struct mips_address_info addr;
2015 int factor;
2017 /* BLKmode is used for single unaligned loads and stores and should
2018 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2019 meaningless, so we have to single it out as a special case one way
2020 or the other.) */
2021 if (mode != BLKmode && might_split_p)
2022 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2023 else
2024 factor = 1;
2026 if (mips_classify_address (&addr, x, mode, false))
2027 switch (addr.type)
2029 case ADDRESS_REG:
2030 if (TARGET_MIPS16
2031 && !mips16_unextended_reference_p (mode, addr.reg,
2032 UINTVAL (addr.offset)))
2033 return factor * 2;
2034 return factor;
2036 case ADDRESS_LO_SUM:
2037 return TARGET_MIPS16 ? factor * 2 : factor;
2039 case ADDRESS_CONST_INT:
2040 return factor;
2042 case ADDRESS_SYMBOLIC:
2043 return factor * mips_symbol_insns (addr.symbol_type, mode);
2045 return 0;
2048 /* Return the number of instructions needed to load constant X.
2049 Return 0 if X isn't a valid constant. */
2052 mips_const_insns (rtx x)
2054 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2055 enum mips_symbol_type symbol_type;
2056 rtx offset;
2058 switch (GET_CODE (x))
2060 case HIGH:
2061 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2062 &symbol_type)
2063 || !mips_split_p[symbol_type])
2064 return 0;
2066 /* This is simply an LUI for normal mode. It is an extended
2067 LI followed by an extended SLL for MIPS16. */
2068 return TARGET_MIPS16 ? 4 : 1;
2070 case CONST_INT:
2071 if (TARGET_MIPS16)
2072 /* Unsigned 8-bit constants can be loaded using an unextended
2073 LI instruction. Unsigned 16-bit constants can be loaded
2074 using an extended LI. Negative constants must be loaded
2075 using LI and then negated. */
2076 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2077 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2078 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2079 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2080 : 0);
2082 return mips_build_integer (codes, INTVAL (x));
2084 case CONST_DOUBLE:
2085 case CONST_VECTOR:
2086 /* Allow zeros for normal mode, where we can use $0. */
2087 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2089 case CONST:
2090 if (CONST_GP_P (x))
2091 return 1;
2093 /* See if we can refer to X directly. */
2094 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2095 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2097 /* Otherwise try splitting the constant into a base and offset.
2098 16-bit offsets can be added using an extra ADDIU. Larger offsets
2099 must be calculated separately and then added to the base. */
2100 split_const (x, &x, &offset);
2101 if (offset != 0)
2103 int n = mips_const_insns (x);
2104 if (n != 0)
2106 if (SMALL_INT (offset))
2107 return n + 1;
2108 else
2109 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2112 return 0;
2114 case SYMBOL_REF:
2115 case LABEL_REF:
2116 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2117 MAX_MACHINE_MODE);
2119 default:
2120 return 0;
2124 /* X is a doubleword constant that can be handled by splitting it into
2125 two words and loading each word separately. Return the number of
2126 instructions required to do this. */
2129 mips_split_const_insns (rtx x)
2131 unsigned int low, high;
2133 low = mips_const_insns (mips_subword (x, false));
2134 high = mips_const_insns (mips_subword (x, true));
2135 gcc_assert (low > 0 && high > 0);
2136 return low + high;
2139 /* Return the number of instructions needed to implement INSN,
2140 given that it loads from or stores to MEM. Count extended
2141 MIPS16 instructions as two instructions. */
2144 mips_load_store_insns (rtx mem, rtx insn)
2146 enum machine_mode mode;
2147 bool might_split_p;
2148 rtx set;
2150 gcc_assert (MEM_P (mem));
2151 mode = GET_MODE (mem);
2153 /* Try to prove that INSN does not need to be split. */
2154 might_split_p = true;
2155 if (GET_MODE_BITSIZE (mode) == 64)
2157 set = single_set (insn);
2158 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2159 might_split_p = false;
2162 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2165 /* Return the number of instructions needed for an integer division. */
2168 mips_idiv_insns (void)
2170 int count;
2172 count = 1;
2173 if (TARGET_CHECK_ZERO_DIV)
2175 if (GENERATE_DIVIDE_TRAPS)
2176 count++;
2177 else
2178 count += 2;
2181 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2182 count++;
2183 return count;
2186 /* Emit a move from SRC to DEST. Assume that the move expanders can
2187 handle all moves if !can_create_pseudo_p (). The distinction is
2188 important because, unlike emit_move_insn, the move expanders know
2189 how to force Pmode objects into the constant pool even when the
2190 constant pool address is not itself legitimate. */
2193 mips_emit_move (rtx dest, rtx src)
2195 return (can_create_pseudo_p ()
2196 ? emit_move_insn (dest, src)
2197 : emit_move_insn_1 (dest, src));
2200 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2202 static void
2203 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2205 emit_insn (gen_rtx_SET (VOIDmode, target,
2206 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2209 /* Compute (CODE OP0 OP1) and store the result in a new register
2210 of mode MODE. Return that new register. */
2212 static rtx
2213 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2215 rtx reg;
2217 reg = gen_reg_rtx (mode);
2218 mips_emit_binary (code, reg, op0, op1);
2219 return reg;
2222 /* Copy VALUE to a register and return that register. If new pseudos
2223 are allowed, copy it into a new register, otherwise use DEST. */
2225 static rtx
2226 mips_force_temporary (rtx dest, rtx value)
2228 if (can_create_pseudo_p ())
2229 return force_reg (Pmode, value);
2230 else
2232 mips_emit_move (dest, value);
2233 return dest;
2237 /* Emit a call sequence with call pattern PATTERN and return the call
2238 instruction itself (which is not necessarily the last instruction
2239 emitted). LAZY_P is true if the call address is lazily-bound. */
2241 static rtx
2242 mips_emit_call_insn (rtx pattern, bool lazy_p)
2244 rtx insn;
2246 insn = emit_call_insn (pattern);
2248 /* Lazy-binding stubs require $gp to be valid on entry. */
2249 if (lazy_p)
2250 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2252 if (TARGET_USE_GOT)
2254 /* See the comment above load_call<mode> for details. */
2255 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2256 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2257 emit_insn (gen_update_got_version ());
2259 return insn;
2262 /* Return an instruction that copies $gp into register REG. We want
2263 GCC to treat the register's value as constant, so that its value
2264 can be rematerialized on demand. */
2266 static rtx
2267 gen_load_const_gp (rtx reg)
2269 return (Pmode == SImode
2270 ? gen_load_const_gp_si (reg)
2271 : gen_load_const_gp_di (reg));
2274 /* Return a pseudo register that contains the value of $gp throughout
2275 the current function. Such registers are needed by MIPS16 functions,
2276 for which $gp itself is not a valid base register or addition operand. */
2278 static rtx
2279 mips16_gp_pseudo_reg (void)
2281 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2282 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2284 /* Don't emit an instruction to initialize the pseudo register if
2285 we are being called from the tree optimizers' cost-calculation
2286 routines. */
2287 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2288 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2290 rtx insn, scan, after;
2292 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2294 push_topmost_sequence ();
2295 /* We need to emit the initialization after the FUNCTION_BEG
2296 note, so that it will be integrated. */
2297 after = get_insns ();
2298 for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
2299 if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2301 after = scan;
2302 break;
2304 insn = emit_insn_after (insn, after);
2305 pop_topmost_sequence ();
2307 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2310 return cfun->machine->mips16_gp_pseudo_rtx;
2313 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2314 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2315 constant in that context and can be split into a high part and a LO_SUM.
2316 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2317 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2319 TEMP is as for mips_force_temporary and is used to load the high
2320 part into a register. */
2322 bool
2323 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2325 enum mips_symbol_context context;
2326 enum mips_symbol_type symbol_type;
2327 rtx high;
2329 context = (mode == MAX_MACHINE_MODE
2330 ? SYMBOL_CONTEXT_LEA
2331 : SYMBOL_CONTEXT_MEM);
2332 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2333 || mips_symbol_insns (symbol_type, mode) == 0
2334 || !mips_split_p[symbol_type])
2335 return false;
2337 if (lo_sum_out)
2339 if (symbol_type == SYMBOL_GP_RELATIVE)
2341 if (!can_create_pseudo_p ())
2343 emit_insn (gen_load_const_gp (temp));
2344 high = temp;
2346 else
2347 high = mips16_gp_pseudo_reg ();
2349 else
2351 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2352 high = mips_force_temporary (temp, high);
2354 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2356 return true;
2359 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2360 then add CONST_INT OFFSET to the result. */
2362 static rtx
2363 mips_unspec_address_offset (rtx base, rtx offset,
2364 enum mips_symbol_type symbol_type)
2366 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2367 UNSPEC_ADDRESS_FIRST + symbol_type);
2368 if (offset != const0_rtx)
2369 base = gen_rtx_PLUS (Pmode, base, offset);
2370 return gen_rtx_CONST (Pmode, base);
2373 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2374 type SYMBOL_TYPE. */
2377 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2379 rtx base, offset;
2381 split_const (address, &base, &offset);
2382 return mips_unspec_address_offset (base, offset, symbol_type);
2385 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2386 high part to BASE and return the result. Just return BASE otherwise.
2387 TEMP is as for mips_force_temporary.
2389 The returned expression can be used as the first operand to a LO_SUM. */
2391 static rtx
2392 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2393 enum mips_symbol_type symbol_type)
2395 if (mips_split_p[symbol_type])
2397 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2398 addr = mips_force_temporary (temp, addr);
2399 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2401 return base;
2404 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2405 mips_force_temporary; it is only needed when OFFSET is not a
2406 SMALL_OPERAND. */
2408 static rtx
2409 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2411 if (!SMALL_OPERAND (offset))
2413 rtx high;
2415 if (TARGET_MIPS16)
2417 /* Load the full offset into a register so that we can use
2418 an unextended instruction for the address itself. */
2419 high = GEN_INT (offset);
2420 offset = 0;
2422 else
2424 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2425 high = GEN_INT (CONST_HIGH_PART (offset));
2426 offset = CONST_LOW_PART (offset);
2428 high = mips_force_temporary (temp, high);
2429 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2431 return plus_constant (reg, offset);
2434 /* The __tls_get_attr symbol. */
2435 static GTY(()) rtx mips_tls_symbol;
2437 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2438 the TLS symbol we are referencing and TYPE is the symbol type to use
2439 (either global dynamic or local dynamic). V0 is an RTX for the
2440 return value location. */
2442 static rtx
2443 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2445 rtx insn, loc, a0;
2447 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2449 if (!mips_tls_symbol)
2450 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2452 loc = mips_unspec_address (sym, type);
2454 start_sequence ();
2456 emit_insn (gen_rtx_SET (Pmode, a0,
2457 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2458 insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false);
2459 RTL_CONST_CALL_P (insn) = 1;
2460 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2461 insn = get_insns ();
2463 end_sequence ();
2465 return insn;
2468 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2469 its address. The return value will be both a valid address and a valid
2470 SET_SRC (either a REG or a LO_SUM). */
2472 static rtx
2473 mips_legitimize_tls_address (rtx loc)
2475 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2476 enum tls_model model;
2478 if (TARGET_MIPS16)
2480 sorry ("MIPS16 TLS");
2481 return gen_reg_rtx (Pmode);
2484 model = SYMBOL_REF_TLS_MODEL (loc);
2485 /* Only TARGET_ABICALLS code can have more than one module; other
2486 code must be be static and should not use a GOT. All TLS models
2487 reduce to local exec in this situation. */
2488 if (!TARGET_ABICALLS)
2489 model = TLS_MODEL_LOCAL_EXEC;
2491 switch (model)
2493 case TLS_MODEL_GLOBAL_DYNAMIC:
2494 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2495 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2496 dest = gen_reg_rtx (Pmode);
2497 emit_libcall_block (insn, dest, v0, loc);
2498 break;
2500 case TLS_MODEL_LOCAL_DYNAMIC:
2501 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2502 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2503 tmp1 = gen_reg_rtx (Pmode);
2505 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2506 share the LDM result with other LD model accesses. */
2507 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2508 UNSPEC_TLS_LDM);
2509 emit_libcall_block (insn, tmp1, v0, eqv);
2511 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2512 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2513 mips_unspec_address (loc, SYMBOL_DTPREL));
2514 break;
2516 case TLS_MODEL_INITIAL_EXEC:
2517 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2518 tmp1 = gen_reg_rtx (Pmode);
2519 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2520 if (Pmode == DImode)
2522 emit_insn (gen_tls_get_tp_di (v1));
2523 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2525 else
2527 emit_insn (gen_tls_get_tp_si (v1));
2528 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2530 dest = gen_reg_rtx (Pmode);
2531 emit_insn (gen_add3_insn (dest, tmp1, v1));
2532 break;
2534 case TLS_MODEL_LOCAL_EXEC:
2535 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2536 if (Pmode == DImode)
2537 emit_insn (gen_tls_get_tp_di (v1));
2538 else
2539 emit_insn (gen_tls_get_tp_si (v1));
2541 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2542 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2543 mips_unspec_address (loc, SYMBOL_TPREL));
2544 break;
2546 default:
2547 gcc_unreachable ();
2549 return dest;
2552 /* If X is not a valid address for mode MODE, force it into a register. */
2554 static rtx
2555 mips_force_address (rtx x, enum machine_mode mode)
2557 if (!mips_legitimate_address_p (mode, x, false))
2558 x = force_reg (Pmode, x);
2559 return x;
2562 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2563 be legitimized in a way that the generic machinery might not expect,
2564 put the new address in *XLOC and return true. MODE is the mode of
2565 the memory being accessed. */
2567 bool
2568 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2570 rtx base, addr;
2571 HOST_WIDE_INT offset;
2573 if (mips_tls_symbol_p (*xloc))
2575 *xloc = mips_legitimize_tls_address (*xloc);
2576 return true;
2579 /* See if the address can split into a high part and a LO_SUM. */
2580 if (mips_split_symbol (NULL, *xloc, mode, &addr))
2582 *xloc = mips_force_address (addr, mode);
2583 return true;
2586 /* Handle BASE + OFFSET using mips_add_offset. */
2587 mips_split_plus (*xloc, &base, &offset);
2588 if (offset != 0)
2590 if (!mips_valid_base_register_p (base, mode, false))
2591 base = copy_to_mode_reg (Pmode, base);
2592 addr = mips_add_offset (NULL, base, offset);
2593 *xloc = mips_force_address (addr, mode);
2594 return true;
2596 return false;
2599 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2601 void
2602 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2604 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2605 enum machine_mode mode;
2606 unsigned int i, num_ops;
2607 rtx x;
2609 mode = GET_MODE (dest);
2610 num_ops = mips_build_integer (codes, value);
2612 /* Apply each binary operation to X. Invariant: X is a legitimate
2613 source operand for a SET pattern. */
2614 x = GEN_INT (codes[0].value);
2615 for (i = 1; i < num_ops; i++)
2617 if (!can_create_pseudo_p ())
2619 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2620 x = temp;
2622 else
2623 x = force_reg (mode, x);
2624 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2627 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2630 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2631 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2632 move_operand. */
2634 static void
2635 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2637 rtx base, offset;
2639 /* Split moves of big integers into smaller pieces. */
2640 if (splittable_const_int_operand (src, mode))
2642 mips_move_integer (dest, dest, INTVAL (src));
2643 return;
2646 /* Split moves of symbolic constants into high/low pairs. */
2647 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2649 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2650 return;
2653 /* Generate the appropriate access sequences for TLS symbols. */
2654 if (mips_tls_symbol_p (src))
2656 mips_emit_move (dest, mips_legitimize_tls_address (src));
2657 return;
2660 /* If we have (const (plus symbol offset)), and that expression cannot
2661 be forced into memory, load the symbol first and add in the offset.
2662 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2663 forced into memory, as it usually produces better code. */
2664 split_const (src, &base, &offset);
2665 if (offset != const0_rtx
2666 && (targetm.cannot_force_const_mem (src)
2667 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2669 base = mips_force_temporary (dest, base);
2670 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2671 return;
2674 src = force_const_mem (mode, src);
2676 /* When using explicit relocs, constant pool references are sometimes
2677 not legitimate addresses. */
2678 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2679 mips_emit_move (dest, src);
2682 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2683 sequence that is valid. */
2685 bool
2686 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2688 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2690 mips_emit_move (dest, force_reg (mode, src));
2691 return true;
2694 /* We need to deal with constants that would be legitimate
2695 immediate_operands but aren't legitimate move_operands. */
2696 if (CONSTANT_P (src) && !move_operand (src, mode))
2698 mips_legitimize_const_move (mode, dest, src);
2699 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2700 return true;
2702 return false;
2705 /* Return true if value X in context CONTEXT is a small-data address
2706 that can be rewritten as a LO_SUM. */
2708 static bool
2709 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2711 enum mips_symbol_type symbol_type;
2713 return (TARGET_EXPLICIT_RELOCS
2714 && mips_symbolic_constant_p (x, context, &symbol_type)
2715 && symbol_type == SYMBOL_GP_RELATIVE);
2718 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2719 containing MEM, or null if none. */
2721 static int
2722 mips_small_data_pattern_1 (rtx *loc, void *data)
2724 enum mips_symbol_context context;
2726 if (GET_CODE (*loc) == LO_SUM)
2727 return -1;
2729 if (MEM_P (*loc))
2731 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2732 return 1;
2733 return -1;
2736 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2737 return mips_rewrite_small_data_p (*loc, context);
2740 /* Return true if OP refers to small data symbols directly, not through
2741 a LO_SUM. */
2743 bool
2744 mips_small_data_pattern_p (rtx op)
2746 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2749 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2750 DATA is the containing MEM, or null if none. */
2752 static int
2753 mips_rewrite_small_data_1 (rtx *loc, void *data)
2755 enum mips_symbol_context context;
2757 if (MEM_P (*loc))
2759 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2760 return -1;
2763 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2764 if (mips_rewrite_small_data_p (*loc, context))
2765 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2767 if (GET_CODE (*loc) == LO_SUM)
2768 return -1;
2770 return 0;
2773 /* Rewrite instruction pattern PATTERN so that it refers to small data
2774 using explicit relocations. */
2777 mips_rewrite_small_data (rtx pattern)
2779 pattern = copy_insn (pattern);
2780 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
2781 return pattern;
2784 /* We need a lot of little routines to check the range of MIPS16 immediate
2785 operands. */
2787 static int
2788 m16_check_op (rtx op, int low, int high, int mask)
2790 return (GET_CODE (op) == CONST_INT
2791 && IN_RANGE (INTVAL (op), low, high)
2792 && (INTVAL (op) & mask) == 0);
2796 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2798 return m16_check_op (op, 0x1, 0x8, 0);
2802 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2804 return m16_check_op (op, -0x8, 0x7, 0);
2808 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2810 return m16_check_op (op, -0x7, 0x8, 0);
2814 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2816 return m16_check_op (op, -0x10, 0xf, 0);
2820 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2822 return m16_check_op (op, -0xf, 0x10, 0);
2826 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2828 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
2832 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2834 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
2838 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2840 return m16_check_op (op, -0x80, 0x7f, 0);
2844 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2846 return m16_check_op (op, -0x7f, 0x80, 0);
2850 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2852 return m16_check_op (op, 0x0, 0xff, 0);
2856 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2858 return m16_check_op (op, -0xff, 0x0, 0);
2862 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2864 return m16_check_op (op, -0x1, 0xfe, 0);
2868 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2870 return m16_check_op (op, 0x0, 0xff << 2, 3);
2874 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2876 return m16_check_op (op, -0xff << 2, 0x0, 3);
2880 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2882 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
2886 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2888 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
2891 /* The cost of loading values from the constant pool. It should be
2892 larger than the cost of any constant we want to synthesize inline. */
2893 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2895 /* Return the cost of X when used as an operand to the MIPS16 instruction
2896 that implements CODE. Return -1 if there is no such instruction, or if
2897 X is not a valid immediate operand for it. */
2899 static int
2900 mips16_constant_cost (int code, HOST_WIDE_INT x)
2902 switch (code)
2904 case ASHIFT:
2905 case ASHIFTRT:
2906 case LSHIFTRT:
2907 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2908 other shifts are extended. The shift patterns truncate the shift
2909 count to the right size, so there are no out-of-range values. */
2910 if (IN_RANGE (x, 1, 8))
2911 return 0;
2912 return COSTS_N_INSNS (1);
2914 case PLUS:
2915 if (IN_RANGE (x, -128, 127))
2916 return 0;
2917 if (SMALL_OPERAND (x))
2918 return COSTS_N_INSNS (1);
2919 return -1;
2921 case LEU:
2922 /* Like LE, but reject the always-true case. */
2923 if (x == -1)
2924 return -1;
2925 case LE:
2926 /* We add 1 to the immediate and use SLT. */
2927 x += 1;
2928 case XOR:
2929 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2930 case LT:
2931 case LTU:
2932 if (IN_RANGE (x, 0, 255))
2933 return 0;
2934 if (SMALL_OPERAND_UNSIGNED (x))
2935 return COSTS_N_INSNS (1);
2936 return -1;
2938 case EQ:
2939 case NE:
2940 /* Equality comparisons with 0 are cheap. */
2941 if (x == 0)
2942 return 0;
2943 return -1;
2945 default:
2946 return -1;
2950 /* Return true if there is a non-MIPS16 instruction that implements CODE
2951 and if that instruction accepts X as an immediate operand. */
2953 static int
2954 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2956 switch (code)
2958 case ASHIFT:
2959 case ASHIFTRT:
2960 case LSHIFTRT:
2961 /* All shift counts are truncated to a valid constant. */
2962 return true;
2964 case ROTATE:
2965 case ROTATERT:
2966 /* Likewise rotates, if the target supports rotates at all. */
2967 return ISA_HAS_ROR;
2969 case AND:
2970 case IOR:
2971 case XOR:
2972 /* These instructions take 16-bit unsigned immediates. */
2973 return SMALL_OPERAND_UNSIGNED (x);
2975 case PLUS:
2976 case LT:
2977 case LTU:
2978 /* These instructions take 16-bit signed immediates. */
2979 return SMALL_OPERAND (x);
2981 case EQ:
2982 case NE:
2983 case GT:
2984 case GTU:
2985 /* The "immediate" forms of these instructions are really
2986 implemented as comparisons with register 0. */
2987 return x == 0;
2989 case GE:
2990 case GEU:
2991 /* Likewise, meaning that the only valid immediate operand is 1. */
2992 return x == 1;
2994 case LE:
2995 /* We add 1 to the immediate and use SLT. */
2996 return SMALL_OPERAND (x + 1);
2998 case LEU:
2999 /* Likewise SLTU, but reject the always-true case. */
3000 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3002 case SIGN_EXTRACT:
3003 case ZERO_EXTRACT:
3004 /* The bit position and size are immediate operands. */
3005 return ISA_HAS_EXT_INS;
3007 default:
3008 /* By default assume that $0 can be used for 0. */
3009 return x == 0;
3013 /* Return the cost of binary operation X, given that the instruction
3014 sequence for a word-sized or smaller operation has cost SINGLE_COST
3015 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3017 static int
3018 mips_binary_cost (rtx x, int single_cost, int double_cost)
3020 int cost;
3022 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3023 cost = double_cost;
3024 else
3025 cost = single_cost;
3026 return (cost
3027 + rtx_cost (XEXP (x, 0), 0)
3028 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
3031 /* Return the cost of floating-point multiplications of mode MODE. */
3033 static int
3034 mips_fp_mult_cost (enum machine_mode mode)
3036 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3039 /* Return the cost of floating-point divisions of mode MODE. */
3041 static int
3042 mips_fp_div_cost (enum machine_mode mode)
3044 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3047 /* Return the cost of sign-extending OP to mode MODE, not including the
3048 cost of OP itself. */
3050 static int
3051 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3053 if (MEM_P (op))
3054 /* Extended loads are as cheap as unextended ones. */
3055 return 0;
3057 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3058 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3059 return 0;
3061 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3062 /* We can use SEB or SEH. */
3063 return COSTS_N_INSNS (1);
3065 /* We need to use a shift left and a shift right. */
3066 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3069 /* Return the cost of zero-extending OP to mode MODE, not including the
3070 cost of OP itself. */
3072 static int
3073 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3075 if (MEM_P (op))
3076 /* Extended loads are as cheap as unextended ones. */
3077 return 0;
3079 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3080 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3081 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3083 if (GENERATE_MIPS16E)
3084 /* We can use ZEB or ZEH. */
3085 return COSTS_N_INSNS (1);
3087 if (TARGET_MIPS16)
3088 /* We need to load 0xff or 0xffff into a register and use AND. */
3089 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3091 /* We can use ANDI. */
3092 return COSTS_N_INSNS (1);
3095 /* Implement TARGET_RTX_COSTS. */
3097 static bool
3098 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
3100 enum machine_mode mode = GET_MODE (x);
3101 bool float_mode_p = FLOAT_MODE_P (mode);
3102 int cost;
3103 rtx addr;
3105 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3106 appear in the instruction stream, and the cost of a comparison is
3107 really the cost of the branch or scc condition. At the time of
3108 writing, GCC only uses an explicit outer COMPARE code when optabs
3109 is testing whether a constant is expensive enough to force into a
3110 register. We want optabs to pass such constants through the MIPS
3111 expanders instead, so make all constants very cheap here. */
3112 if (outer_code == COMPARE)
3114 gcc_assert (CONSTANT_P (x));
3115 *total = 0;
3116 return true;
3119 switch (code)
3121 case CONST_INT:
3122 /* Treat *clear_upper32-style ANDs as having zero cost in the
3123 second operand. The cost is entirely in the first operand.
3125 ??? This is needed because we would otherwise try to CSE
3126 the constant operand. Although that's the right thing for
3127 instructions that continue to be a register operation throughout
3128 compilation, it is disastrous for instructions that could
3129 later be converted into a memory operation. */
3130 if (TARGET_64BIT
3131 && outer_code == AND
3132 && UINTVAL (x) == 0xffffffff)
3134 *total = 0;
3135 return true;
3138 if (TARGET_MIPS16)
3140 cost = mips16_constant_cost (outer_code, INTVAL (x));
3141 if (cost >= 0)
3143 *total = cost;
3144 return true;
3147 else
3149 /* When not optimizing for size, we care more about the cost
3150 of hot code, and hot code is often in a loop. If a constant
3151 operand needs to be forced into a register, we will often be
3152 able to hoist the constant load out of the loop, so the load
3153 should not contribute to the cost. */
3154 if (!optimize_size
3155 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3157 *total = 0;
3158 return true;
3161 /* Fall through. */
3163 case CONST:
3164 case SYMBOL_REF:
3165 case LABEL_REF:
3166 case CONST_DOUBLE:
3167 if (force_to_mem_operand (x, VOIDmode))
3169 *total = COSTS_N_INSNS (1);
3170 return true;
3172 cost = mips_const_insns (x);
3173 if (cost > 0)
3175 /* If the constant is likely to be stored in a GPR, SETs of
3176 single-insn constants are as cheap as register sets; we
3177 never want to CSE them.
3179 Don't reduce the cost of storing a floating-point zero in
3180 FPRs. If we have a zero in an FPR for other reasons, we
3181 can get better cfg-cleanup and delayed-branch results by
3182 using it consistently, rather than using $0 sometimes and
3183 an FPR at other times. Also, moves between floating-point
3184 registers are sometimes cheaper than (D)MTC1 $0. */
3185 if (cost == 1
3186 && outer_code == SET
3187 && !(float_mode_p && TARGET_HARD_FLOAT))
3188 cost = 0;
3189 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3190 want to CSE the constant itself. It is usually better to
3191 have N copies of the last operation in the sequence and one
3192 shared copy of the other operations. (Note that this is
3193 not true for MIPS16 code, where the final operation in the
3194 sequence is often an extended instruction.)
3196 Also, if we have a CONST_INT, we don't know whether it is
3197 for a word or doubleword operation, so we cannot rely on
3198 the result of mips_build_integer. */
3199 else if (!TARGET_MIPS16
3200 && (outer_code == SET || mode == VOIDmode))
3201 cost = 1;
3202 *total = COSTS_N_INSNS (cost);
3203 return true;
3205 /* The value will need to be fetched from the constant pool. */
3206 *total = CONSTANT_POOL_COST;
3207 return true;
3209 case MEM:
3210 /* If the address is legitimate, return the number of
3211 instructions it needs. */
3212 addr = XEXP (x, 0);
3213 cost = mips_address_insns (addr, mode, true);
3214 if (cost > 0)
3216 *total = COSTS_N_INSNS (cost + 1);
3217 return true;
3219 /* Check for a scaled indexed address. */
3220 if (mips_lwxs_address_p (addr))
3222 *total = COSTS_N_INSNS (2);
3223 return true;
3225 /* Otherwise use the default handling. */
3226 return false;
3228 case FFS:
3229 *total = COSTS_N_INSNS (6);
3230 return false;
3232 case NOT:
3233 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3234 return false;
3236 case AND:
3237 /* Check for a *clear_upper32 pattern and treat it like a zero
3238 extension. See the pattern's comment for details. */
3239 if (TARGET_64BIT
3240 && mode == DImode
3241 && CONST_INT_P (XEXP (x, 1))
3242 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3244 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3245 + rtx_cost (XEXP (x, 0), 0));
3246 return true;
3248 /* Fall through. */
3250 case IOR:
3251 case XOR:
3252 /* Double-word operations use two single-word operations. */
3253 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3254 return true;
3256 case ASHIFT:
3257 case ASHIFTRT:
3258 case LSHIFTRT:
3259 case ROTATE:
3260 case ROTATERT:
3261 if (CONSTANT_P (XEXP (x, 1)))
3262 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3263 else
3264 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3265 return true;
3267 case ABS:
3268 if (float_mode_p)
3269 *total = mips_cost->fp_add;
3270 else
3271 *total = COSTS_N_INSNS (4);
3272 return false;
3274 case LO_SUM:
3275 /* Low-part immediates need an extended MIPS16 instruction. */
3276 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3277 + rtx_cost (XEXP (x, 0), 0));
3278 return true;
3280 case LT:
3281 case LTU:
3282 case LE:
3283 case LEU:
3284 case GT:
3285 case GTU:
3286 case GE:
3287 case GEU:
3288 case EQ:
3289 case NE:
3290 case UNORDERED:
3291 case LTGT:
3292 /* Branch comparisons have VOIDmode, so use the first operand's
3293 mode instead. */
3294 mode = GET_MODE (XEXP (x, 0));
3295 if (FLOAT_MODE_P (mode))
3297 *total = mips_cost->fp_add;
3298 return false;
3300 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3301 return true;
3303 case MINUS:
3304 if (float_mode_p
3305 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3306 && TARGET_FUSED_MADD
3307 && !HONOR_NANS (mode)
3308 && !HONOR_SIGNED_ZEROS (mode))
3310 /* See if we can use NMADD or NMSUB. See mips.md for the
3311 associated patterns. */
3312 rtx op0 = XEXP (x, 0);
3313 rtx op1 = XEXP (x, 1);
3314 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3316 *total = (mips_fp_mult_cost (mode)
3317 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3318 + rtx_cost (XEXP (op0, 1), 0)
3319 + rtx_cost (op1, 0));
3320 return true;
3322 if (GET_CODE (op1) == MULT)
3324 *total = (mips_fp_mult_cost (mode)
3325 + rtx_cost (op0, 0)
3326 + rtx_cost (XEXP (op1, 0), 0)
3327 + rtx_cost (XEXP (op1, 1), 0));
3328 return true;
3331 /* Fall through. */
3333 case PLUS:
3334 if (float_mode_p)
3336 /* If this is part of a MADD or MSUB, treat the PLUS as
3337 being free. */
3338 if (ISA_HAS_FP4
3339 && TARGET_FUSED_MADD
3340 && GET_CODE (XEXP (x, 0)) == MULT)
3341 *total = 0;
3342 else
3343 *total = mips_cost->fp_add;
3344 return false;
3347 /* Double-word operations require three single-word operations and
3348 an SLTU. The MIPS16 version then needs to move the result of
3349 the SLTU from $24 to a MIPS16 register. */
3350 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3351 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3352 return true;
3354 case NEG:
3355 if (float_mode_p
3356 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3357 && TARGET_FUSED_MADD
3358 && !HONOR_NANS (mode)
3359 && HONOR_SIGNED_ZEROS (mode))
3361 /* See if we can use NMADD or NMSUB. See mips.md for the
3362 associated patterns. */
3363 rtx op = XEXP (x, 0);
3364 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3365 && GET_CODE (XEXP (op, 0)) == MULT)
3367 *total = (mips_fp_mult_cost (mode)
3368 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3369 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3370 + rtx_cost (XEXP (op, 1), 0));
3371 return true;
3375 if (float_mode_p)
3376 *total = mips_cost->fp_add;
3377 else
3378 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3379 return false;
3381 case MULT:
3382 if (float_mode_p)
3383 *total = mips_fp_mult_cost (mode);
3384 else if (mode == DImode && !TARGET_64BIT)
3385 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3386 where the mulsidi3 always includes an MFHI and an MFLO. */
3387 *total = (optimize_size
3388 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3389 : mips_cost->int_mult_si * 3 + 6);
3390 else if (optimize_size)
3391 *total = (ISA_HAS_MUL3 ? 1 : 2);
3392 else if (mode == DImode)
3393 *total = mips_cost->int_mult_di;
3394 else
3395 *total = mips_cost->int_mult_si;
3396 return false;
3398 case DIV:
3399 /* Check for a reciprocal. */
3400 if (float_mode_p
3401 && ISA_HAS_FP4
3402 && flag_unsafe_math_optimizations
3403 && XEXP (x, 0) == CONST1_RTX (mode))
3405 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3406 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3407 division as being free. */
3408 *total = rtx_cost (XEXP (x, 1), 0);
3409 else
3410 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3411 return true;
3413 /* Fall through. */
3415 case SQRT:
3416 case MOD:
3417 if (float_mode_p)
3419 *total = mips_fp_div_cost (mode);
3420 return false;
3422 /* Fall through. */
3424 case UDIV:
3425 case UMOD:
3426 if (optimize_size)
3428 /* It is our responsibility to make division by a power of 2
3429 as cheap as 2 register additions if we want the division
3430 expanders to be used for such operations; see the setting
3431 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3432 should always produce shorter code than using
3433 expand_sdiv2_pow2. */
3434 if (TARGET_MIPS16
3435 && CONST_INT_P (XEXP (x, 1))
3436 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3438 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3439 return true;
3441 *total = COSTS_N_INSNS (mips_idiv_insns ());
3443 else if (mode == DImode)
3444 *total = mips_cost->int_div_di;
3445 else
3446 *total = mips_cost->int_div_si;
3447 return false;
3449 case SIGN_EXTEND:
3450 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3451 return false;
3453 case ZERO_EXTEND:
3454 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3455 return false;
3457 case FLOAT:
3458 case UNSIGNED_FLOAT:
3459 case FIX:
3460 case FLOAT_EXTEND:
3461 case FLOAT_TRUNCATE:
3462 *total = mips_cost->fp_add;
3463 return false;
3465 default:
3466 return false;
3470 /* Implement TARGET_ADDRESS_COST. */
3472 static int
3473 mips_address_cost (rtx addr)
3475 return mips_address_insns (addr, SImode, false);
3478 /* Return one word of double-word value OP, taking into account the fixed
3479 endianness of certain registers. HIGH_P is true to select the high part,
3480 false to select the low part. */
3483 mips_subword (rtx op, bool high_p)
3485 unsigned int byte, offset;
3486 enum machine_mode mode;
3488 mode = GET_MODE (op);
3489 if (mode == VOIDmode)
3490 mode = TARGET_64BIT ? TImode : DImode;
3492 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3493 byte = UNITS_PER_WORD;
3494 else
3495 byte = 0;
3497 if (FP_REG_RTX_P (op))
3499 /* Paired FPRs are always ordered little-endian. */
3500 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3501 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3504 if (MEM_P (op))
3505 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3507 return simplify_gen_subreg (word_mode, op, mode, byte);
3510 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3512 bool
3513 mips_split_64bit_move_p (rtx dest, rtx src)
3515 if (TARGET_64BIT)
3516 return false;
3518 /* FPR-to-FPR moves can be done in a single instruction, if they're
3519 allowed at all. */
3520 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3521 return false;
3523 /* Check for floating-point loads and stores. */
3524 if (ISA_HAS_LDC1_SDC1)
3526 if (FP_REG_RTX_P (dest) && MEM_P (src))
3527 return false;
3528 if (FP_REG_RTX_P (src) && MEM_P (dest))
3529 return false;
3531 return true;
3534 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3535 this function handles 64-bit moves for which mips_split_64bit_move_p
3536 holds. For 64-bit targets, this function handles 128-bit moves. */
3538 void
3539 mips_split_doubleword_move (rtx dest, rtx src)
3541 rtx low_dest;
3543 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3545 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3546 emit_insn (gen_move_doubleword_fprdi (dest, src));
3547 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3548 emit_insn (gen_move_doubleword_fprdf (dest, src));
3549 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3550 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3551 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3552 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3553 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3554 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3555 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3556 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3557 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3558 emit_insn (gen_move_doubleword_fprtf (dest, src));
3559 else
3560 gcc_unreachable ();
3562 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3564 low_dest = mips_subword (dest, false);
3565 mips_emit_move (low_dest, mips_subword (src, false));
3566 if (TARGET_64BIT)
3567 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3568 else
3569 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3571 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3573 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3574 if (TARGET_64BIT)
3575 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3576 else
3577 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3579 else
3581 /* The operation can be split into two normal moves. Decide in
3582 which order to do them. */
3583 low_dest = mips_subword (dest, false);
3584 if (REG_P (low_dest)
3585 && reg_overlap_mentioned_p (low_dest, src))
3587 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3588 mips_emit_move (low_dest, mips_subword (src, false));
3590 else
3592 mips_emit_move (low_dest, mips_subword (src, false));
3593 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3598 /* Return the appropriate instructions to move SRC into DEST. Assume
3599 that SRC is operand 1 and DEST is operand 0. */
3601 const char *
3602 mips_output_move (rtx dest, rtx src)
3604 enum rtx_code dest_code, src_code;
3605 enum machine_mode mode;
3606 enum mips_symbol_type symbol_type;
3607 bool dbl_p;
3609 dest_code = GET_CODE (dest);
3610 src_code = GET_CODE (src);
3611 mode = GET_MODE (dest);
3612 dbl_p = (GET_MODE_SIZE (mode) == 8);
3614 if (dbl_p && mips_split_64bit_move_p (dest, src))
3615 return "#";
3617 if ((src_code == REG && GP_REG_P (REGNO (src)))
3618 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3620 if (dest_code == REG)
3622 if (GP_REG_P (REGNO (dest)))
3623 return "move\t%0,%z1";
3625 /* Moves to HI are handled by special .md insns. */
3626 if (REGNO (dest) == LO_REGNUM)
3627 return "mtlo\t%z1";
3629 if (DSP_ACC_REG_P (REGNO (dest)))
3631 static char retval[] = "mt__\t%z1,%q0";
3633 retval[2] = reg_names[REGNO (dest)][4];
3634 retval[3] = reg_names[REGNO (dest)][5];
3635 return retval;
3638 if (FP_REG_P (REGNO (dest)))
3639 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3641 if (ALL_COP_REG_P (REGNO (dest)))
3643 static char retval[] = "dmtc_\t%z1,%0";
3645 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3646 return dbl_p ? retval : retval + 1;
3649 if (dest_code == MEM)
3650 switch (GET_MODE_SIZE (mode))
3652 case 1: return "sb\t%z1,%0";
3653 case 2: return "sh\t%z1,%0";
3654 case 4: return "sw\t%z1,%0";
3655 case 8: return "sd\t%z1,%0";
3658 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3660 if (src_code == REG)
3662 /* Moves from HI are handled by special .md insns. */
3663 if (REGNO (src) == LO_REGNUM)
3665 /* When generating VR4120 or VR4130 code, we use MACC and
3666 DMACC instead of MFLO. This avoids both the normal
3667 MIPS III HI/LO hazards and the errata related to
3668 -mfix-vr4130. */
3669 if (ISA_HAS_MACCHI)
3670 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3671 return "mflo\t%0";
3674 if (DSP_ACC_REG_P (REGNO (src)))
3676 static char retval[] = "mf__\t%0,%q1";
3678 retval[2] = reg_names[REGNO (src)][4];
3679 retval[3] = reg_names[REGNO (src)][5];
3680 return retval;
3683 if (FP_REG_P (REGNO (src)))
3684 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3686 if (ALL_COP_REG_P (REGNO (src)))
3688 static char retval[] = "dmfc_\t%0,%1";
3690 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3691 return dbl_p ? retval : retval + 1;
3694 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3695 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3698 if (src_code == MEM)
3699 switch (GET_MODE_SIZE (mode))
3701 case 1: return "lbu\t%0,%1";
3702 case 2: return "lhu\t%0,%1";
3703 case 4: return "lw\t%0,%1";
3704 case 8: return "ld\t%0,%1";
3707 if (src_code == CONST_INT)
3709 /* Don't use the X format for the operand itself, because that
3710 will give out-of-range numbers for 64-bit hosts and 32-bit
3711 targets. */
3712 if (!TARGET_MIPS16)
3713 return "li\t%0,%1\t\t\t# %X1";
3715 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3716 return "li\t%0,%1";
3718 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3719 return "#";
3722 if (src_code == HIGH)
3723 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3725 if (CONST_GP_P (src))
3726 return "move\t%0,%1";
3728 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3729 && mips_lo_relocs[symbol_type] != 0)
3731 /* A signed 16-bit constant formed by applying a relocation
3732 operator to a symbolic address. */
3733 gcc_assert (!mips_split_p[symbol_type]);
3734 return "li\t%0,%R1";
3737 if (symbolic_operand (src, VOIDmode))
3739 gcc_assert (TARGET_MIPS16
3740 ? TARGET_MIPS16_TEXT_LOADS
3741 : !TARGET_EXPLICIT_RELOCS);
3742 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3745 if (src_code == REG && FP_REG_P (REGNO (src)))
3747 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3749 if (GET_MODE (dest) == V2SFmode)
3750 return "mov.ps\t%0,%1";
3751 else
3752 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3755 if (dest_code == MEM)
3756 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3758 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3760 if (src_code == MEM)
3761 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3763 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3765 static char retval[] = "l_c_\t%0,%1";
3767 retval[1] = (dbl_p ? 'd' : 'w');
3768 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3769 return retval;
3771 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3773 static char retval[] = "s_c_\t%1,%0";
3775 retval[1] = (dbl_p ? 'd' : 'w');
3776 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3777 return retval;
3779 gcc_unreachable ();
3782 /* Return true if CMP1 is a suitable second operand for integer ordering
3783 test CODE. See also the *sCC patterns in mips.md. */
3785 static bool
3786 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3788 switch (code)
3790 case GT:
3791 case GTU:
3792 return reg_or_0_operand (cmp1, VOIDmode);
3794 case GE:
3795 case GEU:
3796 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3798 case LT:
3799 case LTU:
3800 return arith_operand (cmp1, VOIDmode);
3802 case LE:
3803 return sle_operand (cmp1, VOIDmode);
3805 case LEU:
3806 return sleu_operand (cmp1, VOIDmode);
3808 default:
3809 gcc_unreachable ();
3813 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3814 integer ordering test *CODE, or if an equivalent combination can
3815 be formed by adjusting *CODE and *CMP1. When returning true, update
3816 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3817 them alone. */
3819 static bool
3820 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3821 enum machine_mode mode)
3823 HOST_WIDE_INT plus_one;
3825 if (mips_int_order_operand_ok_p (*code, *cmp1))
3826 return true;
3828 if (GET_CODE (*cmp1) == CONST_INT)
3829 switch (*code)
3831 case LE:
3832 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3833 if (INTVAL (*cmp1) < plus_one)
3835 *code = LT;
3836 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3837 return true;
3839 break;
3841 case LEU:
3842 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3843 if (plus_one != 0)
3845 *code = LTU;
3846 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3847 return true;
3849 break;
3851 default:
3852 break;
3854 return false;
3857 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3858 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
3859 is nonnull, it's OK to set TARGET to the inverse of the result and
3860 flip *INVERT_PTR instead. */
3862 static void
3863 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
3864 rtx target, rtx cmp0, rtx cmp1)
3866 enum machine_mode mode;
3868 /* First see if there is a MIPS instruction that can do this operation.
3869 If not, try doing the same for the inverse operation. If that also
3870 fails, force CMP1 into a register and try again. */
3871 mode = GET_MODE (cmp0);
3872 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
3873 mips_emit_binary (code, target, cmp0, cmp1);
3874 else
3876 enum rtx_code inv_code = reverse_condition (code);
3877 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3879 cmp1 = force_reg (mode, cmp1);
3880 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3882 else if (invert_ptr == 0)
3884 rtx inv_target;
3886 inv_target = mips_force_binary (GET_MODE (target),
3887 inv_code, cmp0, cmp1);
3888 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3890 else
3892 *invert_ptr = !*invert_ptr;
3893 mips_emit_binary (inv_code, target, cmp0, cmp1);
3898 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3899 The register will have the same mode as CMP0. */
3901 static rtx
3902 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3904 if (cmp1 == const0_rtx)
3905 return cmp0;
3907 if (uns_arith_operand (cmp1, VOIDmode))
3908 return expand_binop (GET_MODE (cmp0), xor_optab,
3909 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3911 return expand_binop (GET_MODE (cmp0), sub_optab,
3912 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3915 /* Convert *CODE into a code that can be used in a floating-point
3916 scc instruction (C.cond.fmt). Return true if the values of
3917 the condition code registers will be inverted, with 0 indicating
3918 that the condition holds. */
3920 static bool
3921 mips_reversed_fp_cond (enum rtx_code *code)
3923 switch (*code)
3925 case NE:
3926 case LTGT:
3927 case ORDERED:
3928 *code = reverse_condition_maybe_unordered (*code);
3929 return true;
3931 default:
3932 return false;
3936 /* Convert a comparison into something that can be used in a branch or
3937 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3938 being compared and *CODE is the code used to compare them.
3940 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3941 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3942 otherwise any standard branch condition can be used. The standard branch
3943 conditions are:
3945 - EQ or NE between two registers.
3946 - any comparison between a register and zero. */
3948 static void
3949 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3951 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3953 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3955 *op0 = cmp_operands[0];
3956 *op1 = cmp_operands[1];
3958 else if (*code == EQ || *code == NE)
3960 if (need_eq_ne_p)
3962 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3963 *op1 = const0_rtx;
3965 else
3967 *op0 = cmp_operands[0];
3968 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3971 else
3973 /* The comparison needs a separate scc instruction. Store the
3974 result of the scc in *OP0 and compare it against zero. */
3975 bool invert = false;
3976 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3977 mips_emit_int_order_test (*code, &invert, *op0,
3978 cmp_operands[0], cmp_operands[1]);
3979 *code = (invert ? EQ : NE);
3980 *op1 = const0_rtx;
3983 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3985 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3986 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3987 *code = NE;
3988 *op1 = const0_rtx;
3990 else
3992 enum rtx_code cmp_code;
3994 /* Floating-point tests use a separate C.cond.fmt comparison to
3995 set a condition code register. The branch or conditional move
3996 will then compare that register against zero.
3998 Set CMP_CODE to the code of the comparison instruction and
3999 *CODE to the code that the branch or move should use. */
4000 cmp_code = *code;
4001 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4002 *op0 = (ISA_HAS_8CC
4003 ? gen_reg_rtx (CCmode)
4004 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4005 *op1 = const0_rtx;
4006 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
4010 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4011 Store the result in TARGET and return true if successful.
4013 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4015 bool
4016 mips_expand_scc (enum rtx_code code, rtx target)
4018 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
4019 return false;
4021 if (code == EQ || code == NE)
4023 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4024 mips_emit_binary (code, target, zie, const0_rtx);
4026 else
4027 mips_emit_int_order_test (code, 0, target,
4028 cmp_operands[0], cmp_operands[1]);
4029 return true;
4032 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4033 CODE and jump to OPERANDS[0] if the condition holds. */
4035 void
4036 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
4038 rtx op0, op1, condition;
4040 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4041 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4042 emit_jump_insn (gen_condjump (condition, operands[0]));
4045 /* Implement:
4047 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4048 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4050 void
4051 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4052 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4054 rtx cmp_result;
4055 bool reversed_p;
4057 reversed_p = mips_reversed_fp_cond (&cond);
4058 cmp_result = gen_reg_rtx (CCV2mode);
4059 emit_insn (gen_scc_ps (cmp_result,
4060 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4061 if (reversed_p)
4062 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4063 cmp_result));
4064 else
4065 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4066 cmp_result));
4069 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4070 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4071 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4073 void
4074 mips_expand_conditional_move (rtx *operands)
4076 enum rtx_code code;
4077 rtx cond, op0, op1;
4079 code = GET_CODE (operands[1]);
4080 mips_emit_compare (&code, &op0, &op1, true);
4081 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
4082 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4083 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4084 operands[2], operands[3])));
4087 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4088 then trap if the condition holds. */
4090 void
4091 mips_expand_conditional_trap (enum rtx_code code)
4093 rtx op0, op1;
4094 enum machine_mode mode;
4096 /* MIPS conditional trap instructions don't have GT or LE flavors,
4097 so we must swap the operands and convert to LT and GE respectively. */
4098 switch (code)
4100 case GT:
4101 case LE:
4102 case GTU:
4103 case LEU:
4104 code = swap_condition (code);
4105 op0 = cmp_operands[1];
4106 op1 = cmp_operands[0];
4107 break;
4109 default:
4110 op0 = cmp_operands[0];
4111 op1 = cmp_operands[1];
4112 break;
4115 mode = GET_MODE (cmp_operands[0]);
4116 op0 = force_reg (mode, op0);
4117 if (!arith_operand (op1, mode))
4118 op1 = force_reg (mode, op1);
4120 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4121 gen_rtx_fmt_ee (code, mode, op0, op1),
4122 const0_rtx));
4125 /* Initialize *CUM for a call to a function of type FNTYPE. */
4127 void
4128 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4130 memset (cum, 0, sizeof (*cum));
4131 cum->prototype = (fntype && prototype_p (fntype));
4132 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4135 /* Fill INFO with information about a single argument. CUM is the
4136 cumulative state for earlier arguments. MODE is the mode of this
4137 argument and TYPE is its type (if known). NAMED is true if this
4138 is a named (fixed) argument rather than a variable one. */
4140 static void
4141 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4142 enum machine_mode mode, tree type, int named)
4144 bool doubleword_aligned_p;
4145 unsigned int num_bytes, num_words, max_regs;
4147 /* Work out the size of the argument. */
4148 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4149 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4151 /* Decide whether it should go in a floating-point register, assuming
4152 one is free. Later code checks for availability.
4154 The checks against UNITS_PER_FPVALUE handle the soft-float and
4155 single-float cases. */
4156 switch (mips_abi)
4158 case ABI_EABI:
4159 /* The EABI conventions have traditionally been defined in terms
4160 of TYPE_MODE, regardless of the actual type. */
4161 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4162 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4163 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4164 break;
4166 case ABI_32:
4167 case ABI_O64:
4168 /* Only leading floating-point scalars are passed in
4169 floating-point registers. We also handle vector floats the same
4170 say, which is OK because they are not covered by the standard ABI. */
4171 info->fpr_p = (!cum->gp_reg_found
4172 && cum->arg_number < 2
4173 && (type == 0
4174 || SCALAR_FLOAT_TYPE_P (type)
4175 || VECTOR_FLOAT_TYPE_P (type))
4176 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4177 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4178 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4179 break;
4181 case ABI_N32:
4182 case ABI_64:
4183 /* Scalar, complex and vector floating-point types are passed in
4184 floating-point registers, as long as this is a named rather
4185 than a variable argument. */
4186 info->fpr_p = (named
4187 && (type == 0 || FLOAT_TYPE_P (type))
4188 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4189 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4190 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4191 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4193 /* ??? According to the ABI documentation, the real and imaginary
4194 parts of complex floats should be passed in individual registers.
4195 The real and imaginary parts of stack arguments are supposed
4196 to be contiguous and there should be an extra word of padding
4197 at the end.
4199 This has two problems. First, it makes it impossible to use a
4200 single "void *" va_list type, since register and stack arguments
4201 are passed differently. (At the time of writing, MIPSpro cannot
4202 handle complex float varargs correctly.) Second, it's unclear
4203 what should happen when there is only one register free.
4205 For now, we assume that named complex floats should go into FPRs
4206 if there are two FPRs free, otherwise they should be passed in the
4207 same way as a struct containing two floats. */
4208 if (info->fpr_p
4209 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4210 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4212 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4213 info->fpr_p = false;
4214 else
4215 num_words = 2;
4217 break;
4219 default:
4220 gcc_unreachable ();
4223 /* See whether the argument has doubleword alignment. */
4224 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4226 /* Set REG_OFFSET to the register count we're interested in.
4227 The EABI allocates the floating-point registers separately,
4228 but the other ABIs allocate them like integer registers. */
4229 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4230 ? cum->num_fprs
4231 : cum->num_gprs);
4233 /* Advance to an even register if the argument is doubleword-aligned. */
4234 if (doubleword_aligned_p)
4235 info->reg_offset += info->reg_offset & 1;
4237 /* Work out the offset of a stack argument. */
4238 info->stack_offset = cum->stack_words;
4239 if (doubleword_aligned_p)
4240 info->stack_offset += info->stack_offset & 1;
4242 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4244 /* Partition the argument between registers and stack. */
4245 info->reg_words = MIN (num_words, max_regs);
4246 info->stack_words = num_words - info->reg_words;
4249 /* INFO describes a register argument that has the normal format for the
4250 argument's mode. Return the register it uses, assuming that FPRs are
4251 available if HARD_FLOAT_P. */
4253 static unsigned int
4254 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4256 if (!info->fpr_p || !hard_float_p)
4257 return GP_ARG_FIRST + info->reg_offset;
4258 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4259 /* In o32, the second argument is always passed in $f14
4260 for TARGET_DOUBLE_FLOAT, regardless of whether the
4261 first argument was a word or doubleword. */
4262 return FP_ARG_FIRST + 2;
4263 else
4264 return FP_ARG_FIRST + info->reg_offset;
4267 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4269 static bool
4270 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4272 return !TARGET_OLDABI;
4275 /* Implement FUNCTION_ARG. */
4278 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4279 tree type, int named)
4281 struct mips_arg_info info;
4283 /* We will be called with a mode of VOIDmode after the last argument
4284 has been seen. Whatever we return will be passed to the call expander.
4285 If we need a MIPS16 fp_code, return a REG with the code stored as
4286 the mode. */
4287 if (mode == VOIDmode)
4289 if (TARGET_MIPS16 && cum->fp_code != 0)
4290 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4291 else
4292 return NULL;
4295 mips_get_arg_info (&info, cum, mode, type, named);
4297 /* Return straight away if the whole argument is passed on the stack. */
4298 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4299 return NULL;
4301 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4302 contains a double in its entirety, then that 64-bit chunk is passed
4303 in a floating-point register. */
4304 if (TARGET_NEWABI
4305 && TARGET_HARD_FLOAT
4306 && named
4307 && type != 0
4308 && TREE_CODE (type) == RECORD_TYPE
4309 && TYPE_SIZE_UNIT (type)
4310 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4312 tree field;
4314 /* First check to see if there is any such field. */
4315 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4316 if (TREE_CODE (field) == FIELD_DECL
4317 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4318 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4319 && host_integerp (bit_position (field), 0)
4320 && int_bit_position (field) % BITS_PER_WORD == 0)
4321 break;
4323 if (field != 0)
4325 /* Now handle the special case by returning a PARALLEL
4326 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4327 chunks are passed in registers. */
4328 unsigned int i;
4329 HOST_WIDE_INT bitpos;
4330 rtx ret;
4332 /* assign_parms checks the mode of ENTRY_PARM, so we must
4333 use the actual mode here. */
4334 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4336 bitpos = 0;
4337 field = TYPE_FIELDS (type);
4338 for (i = 0; i < info.reg_words; i++)
4340 rtx reg;
4342 for (; field; field = TREE_CHAIN (field))
4343 if (TREE_CODE (field) == FIELD_DECL
4344 && int_bit_position (field) >= bitpos)
4345 break;
4347 if (field
4348 && int_bit_position (field) == bitpos
4349 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4350 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4351 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4352 else
4353 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4355 XVECEXP (ret, 0, i)
4356 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4357 GEN_INT (bitpos / BITS_PER_UNIT));
4359 bitpos += BITS_PER_WORD;
4361 return ret;
4365 /* Handle the n32/n64 conventions for passing complex floating-point
4366 arguments in FPR pairs. The real part goes in the lower register
4367 and the imaginary part goes in the upper register. */
4368 if (TARGET_NEWABI
4369 && info.fpr_p
4370 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4372 rtx real, imag;
4373 enum machine_mode inner;
4374 unsigned int regno;
4376 inner = GET_MODE_INNER (mode);
4377 regno = FP_ARG_FIRST + info.reg_offset;
4378 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4380 /* Real part in registers, imaginary part on stack. */
4381 gcc_assert (info.stack_words == info.reg_words);
4382 return gen_rtx_REG (inner, regno);
4384 else
4386 gcc_assert (info.stack_words == 0);
4387 real = gen_rtx_EXPR_LIST (VOIDmode,
4388 gen_rtx_REG (inner, regno),
4389 const0_rtx);
4390 imag = gen_rtx_EXPR_LIST (VOIDmode,
4391 gen_rtx_REG (inner,
4392 regno + info.reg_words / 2),
4393 GEN_INT (GET_MODE_SIZE (inner)));
4394 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4398 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4401 /* Implement FUNCTION_ARG_ADVANCE. */
4403 void
4404 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4405 tree type, int named)
4407 struct mips_arg_info info;
4409 mips_get_arg_info (&info, cum, mode, type, named);
4411 if (!info.fpr_p)
4412 cum->gp_reg_found = true;
4414 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4415 an explanation of what this code does. It assumes that we're using
4416 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4417 in FPRs. */
4418 if (cum->arg_number < 2 && info.fpr_p)
4419 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4421 /* Advance the register count. This has the effect of setting
4422 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4423 argument required us to skip the final GPR and pass the whole
4424 argument on the stack. */
4425 if (mips_abi != ABI_EABI || !info.fpr_p)
4426 cum->num_gprs = info.reg_offset + info.reg_words;
4427 else if (info.reg_words > 0)
4428 cum->num_fprs += MAX_FPRS_PER_FMT;
4430 /* Advance the stack word count. */
4431 if (info.stack_words > 0)
4432 cum->stack_words = info.stack_offset + info.stack_words;
4434 cum->arg_number++;
4437 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4439 static int
4440 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4441 enum machine_mode mode, tree type, bool named)
4443 struct mips_arg_info info;
4445 mips_get_arg_info (&info, cum, mode, type, named);
4446 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4449 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4450 PARM_BOUNDARY bits of alignment, but will be given anything up
4451 to STACK_BOUNDARY bits if the type requires it. */
4454 mips_function_arg_boundary (enum machine_mode mode, tree type)
4456 unsigned int alignment;
4458 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4459 if (alignment < PARM_BOUNDARY)
4460 alignment = PARM_BOUNDARY;
4461 if (alignment > STACK_BOUNDARY)
4462 alignment = STACK_BOUNDARY;
4463 return alignment;
4466 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4467 upward rather than downward. In other words, return true if the
4468 first byte of the stack slot has useful data, false if the last
4469 byte does. */
4471 bool
4472 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4474 /* On little-endian targets, the first byte of every stack argument
4475 is passed in the first byte of the stack slot. */
4476 if (!BYTES_BIG_ENDIAN)
4477 return true;
4479 /* Otherwise, integral types are padded downward: the last byte of a
4480 stack argument is passed in the last byte of the stack slot. */
4481 if (type != 0
4482 ? (INTEGRAL_TYPE_P (type)
4483 || POINTER_TYPE_P (type)
4484 || FIXED_POINT_TYPE_P (type))
4485 : (SCALAR_INT_MODE_P (mode)
4486 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4487 return false;
4489 /* Big-endian o64 pads floating-point arguments downward. */
4490 if (mips_abi == ABI_O64)
4491 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4492 return false;
4494 /* Other types are padded upward for o32, o64, n32 and n64. */
4495 if (mips_abi != ABI_EABI)
4496 return true;
4498 /* Arguments smaller than a stack slot are padded downward. */
4499 if (mode != BLKmode)
4500 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4501 else
4502 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4505 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4506 if the least significant byte of the register has useful data. Return
4507 the opposite if the most significant byte does. */
4509 bool
4510 mips_pad_reg_upward (enum machine_mode mode, tree type)
4512 /* No shifting is required for floating-point arguments. */
4513 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4514 return !BYTES_BIG_ENDIAN;
4516 /* Otherwise, apply the same padding to register arguments as we do
4517 to stack arguments. */
4518 return mips_pad_arg_upward (mode, type);
4521 /* Return nonzero when an argument must be passed by reference. */
4523 static bool
4524 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4525 enum machine_mode mode, const_tree type,
4526 bool named ATTRIBUTE_UNUSED)
4528 if (mips_abi == ABI_EABI)
4530 int size;
4532 /* ??? How should SCmode be handled? */
4533 if (mode == DImode || mode == DFmode
4534 || mode == DQmode || mode == UDQmode
4535 || mode == DAmode || mode == UDAmode)
4536 return 0;
4538 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4539 return size == -1 || size > UNITS_PER_WORD;
4541 else
4543 /* If we have a variable-sized parameter, we have no choice. */
4544 return targetm.calls.must_pass_in_stack (mode, type);
4548 /* Implement TARGET_CALLEE_COPIES. */
4550 static bool
4551 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4552 enum machine_mode mode ATTRIBUTE_UNUSED,
4553 const_tree type ATTRIBUTE_UNUSED, bool named)
4555 return mips_abi == ABI_EABI && named;
4558 /* See whether VALTYPE is a record whose fields should be returned in
4559 floating-point registers. If so, return the number of fields and
4560 list them in FIELDS (which should have two elements). Return 0
4561 otherwise.
4563 For n32 & n64, a structure with one or two fields is returned in
4564 floating-point registers as long as every field has a floating-point
4565 type. */
4567 static int
4568 mips_fpr_return_fields (const_tree valtype, tree *fields)
4570 tree field;
4571 int i;
4573 if (!TARGET_NEWABI)
4574 return 0;
4576 if (TREE_CODE (valtype) != RECORD_TYPE)
4577 return 0;
4579 i = 0;
4580 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4582 if (TREE_CODE (field) != FIELD_DECL)
4583 continue;
4585 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4586 return 0;
4588 if (i == 2)
4589 return 0;
4591 fields[i++] = field;
4593 return i;
4596 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4597 a value in the most significant part of $2/$3 if:
4599 - the target is big-endian;
4601 - the value has a structure or union type (we generalize this to
4602 cover aggregates from other languages too); and
4604 - the structure is not returned in floating-point registers. */
4606 static bool
4607 mips_return_in_msb (const_tree valtype)
4609 tree fields[2];
4611 return (TARGET_NEWABI
4612 && TARGET_BIG_ENDIAN
4613 && AGGREGATE_TYPE_P (valtype)
4614 && mips_fpr_return_fields (valtype, fields) == 0);
4617 /* Return true if the function return value MODE will get returned in a
4618 floating-point register. */
4620 static bool
4621 mips_return_mode_in_fpr_p (enum machine_mode mode)
4623 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4624 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4625 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4626 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4629 /* Return the representation of an FPR return register when the
4630 value being returned in FP_RETURN has mode VALUE_MODE and the
4631 return type itself has mode TYPE_MODE. On NewABI targets,
4632 the two modes may be different for structures like:
4634 struct __attribute__((packed)) foo { float f; }
4636 where we return the SFmode value of "f" in FP_RETURN, but where
4637 the structure itself has mode BLKmode. */
4639 static rtx
4640 mips_return_fpr_single (enum machine_mode type_mode,
4641 enum machine_mode value_mode)
4643 rtx x;
4645 x = gen_rtx_REG (value_mode, FP_RETURN);
4646 if (type_mode != value_mode)
4648 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4649 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4651 return x;
4654 /* Return a composite value in a pair of floating-point registers.
4655 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4656 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4657 complete value.
4659 For n32 & n64, $f0 always holds the first value and $f2 the second.
4660 Otherwise the values are packed together as closely as possible. */
4662 static rtx
4663 mips_return_fpr_pair (enum machine_mode mode,
4664 enum machine_mode mode1, HOST_WIDE_INT offset1,
4665 enum machine_mode mode2, HOST_WIDE_INT offset2)
4667 int inc;
4669 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4670 return gen_rtx_PARALLEL
4671 (mode,
4672 gen_rtvec (2,
4673 gen_rtx_EXPR_LIST (VOIDmode,
4674 gen_rtx_REG (mode1, FP_RETURN),
4675 GEN_INT (offset1)),
4676 gen_rtx_EXPR_LIST (VOIDmode,
4677 gen_rtx_REG (mode2, FP_RETURN + inc),
4678 GEN_INT (offset2))));
4682 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4683 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4684 VALTYPE is null and MODE is the mode of the return value. */
4687 mips_function_value (const_tree valtype, enum machine_mode mode)
4689 if (valtype)
4691 tree fields[2];
4692 int unsigned_p;
4694 mode = TYPE_MODE (valtype);
4695 unsigned_p = TYPE_UNSIGNED (valtype);
4697 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4698 we must promote the mode just as PROMOTE_MODE does. */
4699 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4701 /* Handle structures whose fields are returned in $f0/$f2. */
4702 switch (mips_fpr_return_fields (valtype, fields))
4704 case 1:
4705 return mips_return_fpr_single (mode,
4706 TYPE_MODE (TREE_TYPE (fields[0])));
4708 case 2:
4709 return mips_return_fpr_pair (mode,
4710 TYPE_MODE (TREE_TYPE (fields[0])),
4711 int_byte_position (fields[0]),
4712 TYPE_MODE (TREE_TYPE (fields[1])),
4713 int_byte_position (fields[1]));
4716 /* If a value is passed in the most significant part of a register, see
4717 whether we have to round the mode up to a whole number of words. */
4718 if (mips_return_in_msb (valtype))
4720 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4721 if (size % UNITS_PER_WORD != 0)
4723 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4724 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4728 /* For EABI, the class of return register depends entirely on MODE.
4729 For example, "struct { some_type x; }" and "union { some_type x; }"
4730 are returned in the same way as a bare "some_type" would be.
4731 Other ABIs only use FPRs for scalar, complex or vector types. */
4732 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4733 return gen_rtx_REG (mode, GP_RETURN);
4736 if (!TARGET_MIPS16)
4738 /* Handle long doubles for n32 & n64. */
4739 if (mode == TFmode)
4740 return mips_return_fpr_pair (mode,
4741 DImode, 0,
4742 DImode, GET_MODE_SIZE (mode) / 2);
4744 if (mips_return_mode_in_fpr_p (mode))
4746 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4747 return mips_return_fpr_pair (mode,
4748 GET_MODE_INNER (mode), 0,
4749 GET_MODE_INNER (mode),
4750 GET_MODE_SIZE (mode) / 2);
4751 else
4752 return gen_rtx_REG (mode, FP_RETURN);
4756 return gen_rtx_REG (mode, GP_RETURN);
4759 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4760 all BLKmode objects are returned in memory. Under the n32, n64
4761 and embedded ABIs, small structures are returned in a register.
4762 Objects with varying size must still be returned in memory, of
4763 course. */
4765 static bool
4766 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4768 return (TARGET_OLDABI
4769 ? TYPE_MODE (type) == BLKmode
4770 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
4773 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4775 static void
4776 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4777 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4778 int no_rtl)
4780 CUMULATIVE_ARGS local_cum;
4781 int gp_saved, fp_saved;
4783 /* The caller has advanced CUM up to, but not beyond, the last named
4784 argument. Advance a local copy of CUM past the last "real" named
4785 argument, to find out how many registers are left over. */
4786 local_cum = *cum;
4787 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
4789 /* Found out how many registers we need to save. */
4790 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4791 fp_saved = (EABI_FLOAT_VARARGS_P
4792 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4793 : 0);
4795 if (!no_rtl)
4797 if (gp_saved > 0)
4799 rtx ptr, mem;
4801 ptr = plus_constant (virtual_incoming_args_rtx,
4802 REG_PARM_STACK_SPACE (cfun->decl)
4803 - gp_saved * UNITS_PER_WORD);
4804 mem = gen_frame_mem (BLKmode, ptr);
4805 set_mem_alias_set (mem, get_varargs_alias_set ());
4807 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4808 mem, gp_saved);
4810 if (fp_saved > 0)
4812 /* We can't use move_block_from_reg, because it will use
4813 the wrong mode. */
4814 enum machine_mode mode;
4815 int off, i;
4817 /* Set OFF to the offset from virtual_incoming_args_rtx of
4818 the first float register. The FP save area lies below
4819 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4820 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
4821 off -= fp_saved * UNITS_PER_FPREG;
4823 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4825 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4826 i += MAX_FPRS_PER_FMT)
4828 rtx ptr, mem;
4830 ptr = plus_constant (virtual_incoming_args_rtx, off);
4831 mem = gen_frame_mem (mode, ptr);
4832 set_mem_alias_set (mem, get_varargs_alias_set ());
4833 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4834 off += UNITS_PER_HWFPVALUE;
4838 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4839 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4840 + fp_saved * UNITS_PER_FPREG);
4843 /* Implement TARGET_BUILTIN_VA_LIST. */
4845 static tree
4846 mips_build_builtin_va_list (void)
4848 if (EABI_FLOAT_VARARGS_P)
4850 /* We keep 3 pointers, and two offsets.
4852 Two pointers are to the overflow area, which starts at the CFA.
4853 One of these is constant, for addressing into the GPR save area
4854 below it. The other is advanced up the stack through the
4855 overflow region.
4857 The third pointer is to the bottom of the GPR save area.
4858 Since the FPR save area is just below it, we can address
4859 FPR slots off this pointer.
4861 We also keep two one-byte offsets, which are to be subtracted
4862 from the constant pointers to yield addresses in the GPR and
4863 FPR save areas. These are downcounted as float or non-float
4864 arguments are used, and when they get to zero, the argument
4865 must be obtained from the overflow region. */
4866 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4867 tree array, index;
4869 record = lang_hooks.types.make_type (RECORD_TYPE);
4871 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4872 ptr_type_node);
4873 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4874 ptr_type_node);
4875 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4876 ptr_type_node);
4877 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4878 unsigned_char_type_node);
4879 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4880 unsigned_char_type_node);
4881 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4882 warn on every user file. */
4883 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4884 array = build_array_type (unsigned_char_type_node,
4885 build_index_type (index));
4886 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4888 DECL_FIELD_CONTEXT (f_ovfl) = record;
4889 DECL_FIELD_CONTEXT (f_gtop) = record;
4890 DECL_FIELD_CONTEXT (f_ftop) = record;
4891 DECL_FIELD_CONTEXT (f_goff) = record;
4892 DECL_FIELD_CONTEXT (f_foff) = record;
4893 DECL_FIELD_CONTEXT (f_res) = record;
4895 TYPE_FIELDS (record) = f_ovfl;
4896 TREE_CHAIN (f_ovfl) = f_gtop;
4897 TREE_CHAIN (f_gtop) = f_ftop;
4898 TREE_CHAIN (f_ftop) = f_goff;
4899 TREE_CHAIN (f_goff) = f_foff;
4900 TREE_CHAIN (f_foff) = f_res;
4902 layout_type (record);
4903 return record;
4905 else if (TARGET_IRIX && TARGET_IRIX6)
4906 /* On IRIX 6, this type is 'char *'. */
4907 return build_pointer_type (char_type_node);
4908 else
4909 /* Otherwise, we use 'void *'. */
4910 return ptr_type_node;
4913 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
4915 static void
4916 mips_va_start (tree valist, rtx nextarg)
4918 if (EABI_FLOAT_VARARGS_P)
4920 const CUMULATIVE_ARGS *cum;
4921 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4922 tree ovfl, gtop, ftop, goff, foff;
4923 tree t;
4924 int gpr_save_area_size;
4925 int fpr_save_area_size;
4926 int fpr_offset;
4928 cum = &crtl->args.info;
4929 gpr_save_area_size
4930 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4931 fpr_save_area_size
4932 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4934 f_ovfl = TYPE_FIELDS (va_list_type_node);
4935 f_gtop = TREE_CHAIN (f_ovfl);
4936 f_ftop = TREE_CHAIN (f_gtop);
4937 f_goff = TREE_CHAIN (f_ftop);
4938 f_foff = TREE_CHAIN (f_goff);
4940 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4941 NULL_TREE);
4942 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4943 NULL_TREE);
4944 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4945 NULL_TREE);
4946 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4947 NULL_TREE);
4948 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4949 NULL_TREE);
4951 /* Emit code to initialize OVFL, which points to the next varargs
4952 stack argument. CUM->STACK_WORDS gives the number of stack
4953 words used by named arguments. */
4954 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4955 if (cum->stack_words > 0)
4956 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4957 size_int (cum->stack_words * UNITS_PER_WORD));
4958 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4959 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4961 /* Emit code to initialize GTOP, the top of the GPR save area. */
4962 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4963 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4964 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4966 /* Emit code to initialize FTOP, the top of the FPR save area.
4967 This address is gpr_save_area_bytes below GTOP, rounded
4968 down to the next fp-aligned boundary. */
4969 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4970 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4971 fpr_offset &= -UNITS_PER_FPVALUE;
4972 if (fpr_offset)
4973 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4974 size_int (-fpr_offset));
4975 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4976 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4978 /* Emit code to initialize GOFF, the offset from GTOP of the
4979 next GPR argument. */
4980 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4981 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
4982 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4984 /* Likewise emit code to initialize FOFF, the offset from FTOP
4985 of the next FPR argument. */
4986 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4987 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
4988 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4990 else
4992 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4993 std_expand_builtin_va_start (valist, nextarg);
4997 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
4999 static tree
5000 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5002 tree addr;
5003 bool indirect_p;
5005 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5006 if (indirect_p)
5007 type = build_pointer_type (type);
5009 if (!EABI_FLOAT_VARARGS_P)
5010 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5011 else
5013 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5014 tree ovfl, top, off, align;
5015 HOST_WIDE_INT size, rsize, osize;
5016 tree t, u;
5018 f_ovfl = TYPE_FIELDS (va_list_type_node);
5019 f_gtop = TREE_CHAIN (f_ovfl);
5020 f_ftop = TREE_CHAIN (f_gtop);
5021 f_goff = TREE_CHAIN (f_ftop);
5022 f_foff = TREE_CHAIN (f_goff);
5024 /* Let:
5026 TOP be the top of the GPR or FPR save area;
5027 OFF be the offset from TOP of the next register;
5028 ADDR_RTX be the address of the argument;
5029 SIZE be the number of bytes in the argument type;
5030 RSIZE be the number of bytes used to store the argument
5031 when it's in the register save area; and
5032 OSIZE be the number of bytes used to store it when it's
5033 in the stack overflow area.
5035 The code we want is:
5037 1: off &= -rsize; // round down
5038 2: if (off != 0)
5039 3: {
5040 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5041 5: off -= rsize;
5042 6: }
5043 7: else
5044 8: {
5045 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5046 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5047 11: ovfl += osize;
5048 14: }
5050 [1] and [9] can sometimes be optimized away. */
5052 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5053 NULL_TREE);
5054 size = int_size_in_bytes (type);
5056 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5057 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5059 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5060 NULL_TREE);
5061 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5062 NULL_TREE);
5064 /* When va_start saves FPR arguments to the stack, each slot
5065 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5066 argument's precision. */
5067 rsize = UNITS_PER_HWFPVALUE;
5069 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5070 (= PARM_BOUNDARY bits). This can be different from RSIZE
5071 in two cases:
5073 (1) On 32-bit targets when TYPE is a structure such as:
5075 struct s { float f; };
5077 Such structures are passed in paired FPRs, so RSIZE
5078 will be 8 bytes. However, the structure only takes
5079 up 4 bytes of memory, so OSIZE will only be 4.
5081 (2) In combinations such as -mgp64 -msingle-float
5082 -fshort-double. Doubles passed in registers will then take
5083 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5084 stack take up UNITS_PER_WORD bytes. */
5085 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5087 else
5089 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5090 NULL_TREE);
5091 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5092 NULL_TREE);
5093 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5094 if (rsize > UNITS_PER_WORD)
5096 /* [1] Emit code for: off &= -rsize. */
5097 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
5098 build_int_cst (NULL_TREE, -rsize));
5099 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
5100 gimplify_and_add (t, pre_p);
5102 osize = rsize;
5105 /* [2] Emit code to branch if off == 0. */
5106 t = build2 (NE_EXPR, boolean_type_node, off,
5107 build_int_cst (TREE_TYPE (off), 0));
5108 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5110 /* [5] Emit code for: off -= rsize. We do this as a form of
5111 post-decrement not available to C. */
5112 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5113 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5115 /* [4] Emit code for:
5116 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5117 t = fold_convert (sizetype, t);
5118 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5119 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5120 if (BYTES_BIG_ENDIAN && rsize > size)
5122 u = size_int (rsize - size);
5123 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5125 COND_EXPR_THEN (addr) = t;
5127 if (osize > UNITS_PER_WORD)
5129 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5130 u = size_int (osize - 1);
5131 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
5132 t = fold_convert (sizetype, t);
5133 u = size_int (-osize);
5134 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5135 t = fold_convert (TREE_TYPE (ovfl), t);
5136 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
5138 else
5139 align = NULL;
5141 /* [10, 11] Emit code for:
5142 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5143 ovfl += osize. */
5144 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5145 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5146 if (BYTES_BIG_ENDIAN && osize > size)
5148 u = size_int (osize - size);
5149 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5152 /* String [9] and [10, 11] together. */
5153 if (align)
5154 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5155 COND_EXPR_ELSE (addr) = t;
5157 addr = fold_convert (build_pointer_type (type), addr);
5158 addr = build_va_arg_indirect_ref (addr);
5161 if (indirect_p)
5162 addr = build_va_arg_indirect_ref (addr);
5164 return addr;
5167 /* A chained list of functions for which mips16_build_call_stub has already
5168 generated a stub. NAME is the name of the function and FP_RET_P is true
5169 if the function returns a value in floating-point registers. */
5170 struct mips16_stub {
5171 struct mips16_stub *next;
5172 char *name;
5173 bool fp_ret_p;
5175 static struct mips16_stub *mips16_stubs;
5177 /* Return the two-character string that identifies floating-point
5178 return mode MODE in the name of a MIPS16 function stub. */
5180 static const char *
5181 mips16_call_stub_mode_suffix (enum machine_mode mode)
5183 if (mode == SFmode)
5184 return "sf";
5185 else if (mode == DFmode)
5186 return "df";
5187 else if (mode == SCmode)
5188 return "sc";
5189 else if (mode == DCmode)
5190 return "dc";
5191 else if (mode == V2SFmode)
5192 return "df";
5193 else
5194 gcc_unreachable ();
5197 /* Write instructions to move a 32-bit value between general register
5198 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5199 from GPREG to FPREG and 'f' to move in the opposite direction. */
5201 static void
5202 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5204 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5205 reg_names[gpreg], reg_names[fpreg]);
5208 /* Likewise for 64-bit values. */
5210 static void
5211 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5213 if (TARGET_64BIT)
5214 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5215 reg_names[gpreg], reg_names[fpreg]);
5216 else if (TARGET_FLOAT64)
5218 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5219 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5220 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5221 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5223 else
5225 /* Move the least-significant word. */
5226 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5227 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5228 /* ...then the most significant word. */
5229 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5230 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5234 /* Write out code to move floating-point arguments into or out of
5235 general registers. FP_CODE is the code describing which arguments
5236 are present (see the comment above the definition of CUMULATIVE_ARGS
5237 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5239 static void
5240 mips_output_args_xfer (int fp_code, char direction)
5242 unsigned int gparg, fparg, f;
5243 CUMULATIVE_ARGS cum;
5245 /* This code only works for o32 and o64. */
5246 gcc_assert (TARGET_OLDABI);
5248 mips_init_cumulative_args (&cum, NULL);
5250 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5252 enum machine_mode mode;
5253 struct mips_arg_info info;
5255 if ((f & 3) == 1)
5256 mode = SFmode;
5257 else if ((f & 3) == 2)
5258 mode = DFmode;
5259 else
5260 gcc_unreachable ();
5262 mips_get_arg_info (&info, &cum, mode, NULL, true);
5263 gparg = mips_arg_regno (&info, false);
5264 fparg = mips_arg_regno (&info, true);
5266 if (mode == SFmode)
5267 mips_output_32bit_xfer (direction, gparg, fparg);
5268 else
5269 mips_output_64bit_xfer (direction, gparg, fparg);
5271 mips_function_arg_advance (&cum, mode, NULL, true);
5275 /* Write a MIPS16 stub for the current function. This stub is used
5276 for functions which take arguments in the floating-point registers.
5277 It is normal-mode code that moves the floating-point arguments
5278 into the general registers and then jumps to the MIPS16 code. */
5280 static void
5281 mips16_build_function_stub (void)
5283 const char *fnname, *separator;
5284 char *secname, *stubname;
5285 tree stubdecl;
5286 unsigned int f;
5288 /* Create the name of the stub, and its unique section. */
5289 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5290 fnname = targetm.strip_name_encoding (fnname);
5291 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5292 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5294 /* Build a decl for the stub. */
5295 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5296 build_function_type (void_type_node, NULL_TREE));
5297 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5298 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5300 /* Output a comment. */
5301 fprintf (asm_out_file, "\t# Stub function for %s (",
5302 current_function_name ());
5303 separator = "";
5304 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5306 fprintf (asm_out_file, "%s%s", separator,
5307 (f & 3) == 1 ? "float" : "double");
5308 separator = ", ";
5310 fprintf (asm_out_file, ")\n");
5312 /* Write the preamble leading up to the function declaration. */
5313 fprintf (asm_out_file, "\t.set\tnomips16\n");
5314 switch_to_section (function_section (stubdecl));
5315 ASM_OUTPUT_ALIGN (asm_out_file,
5316 floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
5318 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5319 within a .ent, and we cannot emit another .ent. */
5320 if (!FUNCTION_NAME_ALREADY_DECLARED)
5322 fputs ("\t.ent\t", asm_out_file);
5323 assemble_name (asm_out_file, stubname);
5324 fputs ("\n", asm_out_file);
5327 /* Start the definition proper. */
5328 assemble_name (asm_out_file, stubname);
5329 fputs (":\n", asm_out_file);
5331 /* Load the address of the MIPS16 function into $at. Do this first so
5332 that targets with coprocessor interlocks can use an MFC1 to fill the
5333 delay slot. */
5334 fprintf (asm_out_file, "\t.set\tnoat\n");
5335 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5336 assemble_name (asm_out_file, fnname);
5337 fprintf (asm_out_file, "\n");
5339 /* Move the arguments from floating-point registers to general registers. */
5340 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5342 /* Jump to the MIPS16 function. */
5343 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5344 fprintf (asm_out_file, "\t.set\tat\n");
5346 if (!FUNCTION_NAME_ALREADY_DECLARED)
5348 fputs ("\t.end\t", asm_out_file);
5349 assemble_name (asm_out_file, stubname);
5350 fputs ("\n", asm_out_file);
5353 switch_to_section (function_section (current_function_decl));
5356 /* The current function is a MIPS16 function that returns a value in an FPR.
5357 Copy the return value from its soft-float to its hard-float location.
5358 libgcc2 has special non-MIPS16 helper functions for each case. */
5360 static void
5361 mips16_copy_fpr_return_value (void)
5363 rtx fn, insn, arg, call;
5364 tree id, return_type;
5365 enum machine_mode return_mode;
5367 return_type = DECL_RESULT (current_function_decl);
5368 return_mode = DECL_MODE (return_type);
5370 id = get_identifier (ACONCAT (("__mips16_ret_",
5371 mips16_call_stub_mode_suffix (return_mode),
5372 NULL)));
5373 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5374 arg = gen_rtx_REG (return_mode, GP_RETURN);
5375 call = gen_call_value_internal (arg, fn, const0_rtx);
5376 insn = mips_emit_call_insn (call, false);
5377 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5380 /* Consider building a stub for a MIPS16 call to function FN.
5381 RETVAL is the location of the return value, or null if this is
5382 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5383 arguments and FP_CODE is the code built by mips_function_arg;
5384 see the comment above CUMULATIVE_ARGS for details.
5386 If a stub was needed, emit the call and return the call insn itself.
5387 Return null otherwise.
5389 A stub is needed for calls to functions that, in normal mode,
5390 receive arguments in FPRs or return values in FPRs. The stub
5391 copies the arguments from their soft-float positions to their
5392 hard-float positions, calls the real function, then copies the
5393 return value from its hard-float position to its soft-float
5394 position.
5396 We emit a JAL to FN even when FN might need a stub. If FN turns out
5397 to be to a non-MIPS16 function, the linker automatically redirects
5398 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5400 static rtx
5401 mips16_build_call_stub (rtx retval, rtx fn, rtx args_size, int fp_code)
5403 const char *fnname;
5404 bool fp_ret_p;
5405 struct mips16_stub *l;
5406 rtx insn;
5408 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5409 we were invoked with the -msoft-float option. */
5410 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5411 return NULL_RTX;
5413 /* Figure out whether the value might come back in a floating-point
5414 register. */
5415 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5417 /* We don't need to do anything if there were no floating-point
5418 arguments and the value will not be returned in a floating-point
5419 register. */
5420 if (fp_code == 0 && !fp_ret_p)
5421 return NULL_RTX;
5423 /* We don't need to do anything if this is a call to a special
5424 MIPS16 support function. */
5425 if (GET_CODE (fn) == SYMBOL_REF
5426 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5427 return NULL_RTX;
5429 /* This code will only work for o32 and o64 abis. The other ABI's
5430 require more sophisticated support. */
5431 gcc_assert (TARGET_OLDABI);
5433 /* If we're calling via a function pointer, use one of the magic
5434 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5435 Each stub expects the function address to arrive in register $2. */
5436 if (GET_CODE (fn) != SYMBOL_REF)
5438 char buf[30];
5439 tree id;
5440 rtx stub_fn, insn;
5442 /* Create a SYMBOL_REF for the libgcc.a function. */
5443 if (fp_ret_p)
5444 sprintf (buf, "__mips16_call_stub_%s_%d",
5445 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5446 fp_code);
5447 else
5448 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5449 id = get_identifier (buf);
5450 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5452 /* Load the target function into $2. */
5453 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5455 /* Emit the call. */
5456 if (retval == NULL_RTX)
5457 insn = gen_call_internal (stub_fn, args_size);
5458 else
5459 insn = gen_call_value_internal (retval, stub_fn, args_size);
5460 insn = mips_emit_call_insn (insn, false);
5462 /* Tell GCC that this call does indeed use the value of $2. */
5463 CALL_INSN_FUNCTION_USAGE (insn) =
5464 gen_rtx_EXPR_LIST (VOIDmode,
5465 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5466 CALL_INSN_FUNCTION_USAGE (insn));
5468 /* If we are handling a floating-point return value, we need to
5469 save $18 in the function prologue. Putting a note on the
5470 call will mean that df_regs_ever_live_p ($18) will be true if the
5471 call is not eliminated, and we can check that in the prologue
5472 code. */
5473 if (fp_ret_p)
5474 CALL_INSN_FUNCTION_USAGE (insn) =
5475 gen_rtx_EXPR_LIST (VOIDmode,
5476 gen_rtx_USE (VOIDmode,
5477 gen_rtx_REG (word_mode, 18)),
5478 CALL_INSN_FUNCTION_USAGE (insn));
5480 return insn;
5483 /* We know the function we are going to call. If we have already
5484 built a stub, we don't need to do anything further. */
5485 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5486 for (l = mips16_stubs; l != NULL; l = l->next)
5487 if (strcmp (l->name, fnname) == 0)
5488 break;
5490 if (l == NULL)
5492 const char *separator;
5493 char *secname, *stubname;
5494 tree stubid, stubdecl;
5495 unsigned int f;
5497 /* If the function does not return in FPRs, the special stub
5498 section is named
5499 .mips16.call.FNNAME
5501 If the function does return in FPRs, the stub section is named
5502 .mips16.call.fp.FNNAME
5504 Build a decl for the stub. */
5505 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5506 fnname, NULL));
5507 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5508 fnname, NULL));
5509 stubid = get_identifier (stubname);
5510 stubdecl = build_decl (FUNCTION_DECL, stubid,
5511 build_function_type (void_type_node, NULL_TREE));
5512 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5513 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5514 void_type_node);
5516 /* Output a comment. */
5517 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5518 (fp_ret_p
5519 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5520 : ""),
5521 fnname);
5522 separator = "";
5523 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5525 fprintf (asm_out_file, "%s%s", separator,
5526 (f & 3) == 1 ? "float" : "double");
5527 separator = ", ";
5529 fprintf (asm_out_file, ")\n");
5531 /* Write the preamble leading up to the function declaration. */
5532 fprintf (asm_out_file, "\t.set\tnomips16\n");
5533 assemble_start_function (stubdecl, stubname);
5535 if (!FUNCTION_NAME_ALREADY_DECLARED)
5537 fputs ("\t.ent\t", asm_out_file);
5538 assemble_name (asm_out_file, stubname);
5539 fputs ("\n", asm_out_file);
5541 assemble_name (asm_out_file, stubname);
5542 fputs (":\n", asm_out_file);
5545 if (!fp_ret_p)
5547 /* Load the address of the MIPS16 function into $at. Do this
5548 first so that targets with coprocessor interlocks can use
5549 an MFC1 to fill the delay slot. */
5550 fprintf (asm_out_file, "\t.set\tnoat\n");
5551 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5552 fnname);
5555 /* Move the arguments from general registers to floating-point
5556 registers. */
5557 mips_output_args_xfer (fp_code, 't');
5559 if (!fp_ret_p)
5561 /* Jump to the previously-loaded address. */
5562 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5563 fprintf (asm_out_file, "\t.set\tat\n");
5565 else
5567 /* Save the return address in $18 and call the non-MIPS16 function.
5568 The stub's caller knows that $18 might be clobbered, even though
5569 $18 is usually a call-saved register. */
5570 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5571 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5572 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5574 /* Move the result from floating-point registers to
5575 general registers. */
5576 switch (GET_MODE (retval))
5578 case SCmode:
5579 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5580 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5581 /* Fall though. */
5582 case SFmode:
5583 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5584 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5586 /* On 64-bit targets, complex floats are returned in
5587 a single GPR, such that "sd" on a suitably-aligned
5588 target would store the value correctly. */
5589 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5590 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5591 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5592 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5593 reg_names[GP_RETURN],
5594 reg_names[GP_RETURN],
5595 reg_names[GP_RETURN + 1]);
5597 break;
5599 case DCmode:
5600 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5601 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5602 /* Fall though. */
5603 case DFmode:
5604 case V2SFmode:
5605 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5606 break;
5608 default:
5609 gcc_unreachable ();
5611 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
5614 #ifdef ASM_DECLARE_FUNCTION_SIZE
5615 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5616 #endif
5618 if (!FUNCTION_NAME_ALREADY_DECLARED)
5620 fputs ("\t.end\t", asm_out_file);
5621 assemble_name (asm_out_file, stubname);
5622 fputs ("\n", asm_out_file);
5625 /* Record this stub. */
5626 l = XNEW (struct mips16_stub);
5627 l->name = xstrdup (fnname);
5628 l->fp_ret_p = fp_ret_p;
5629 l->next = mips16_stubs;
5630 mips16_stubs = l;
5633 /* If we expect a floating-point return value, but we've built a
5634 stub which does not expect one, then we're in trouble. We can't
5635 use the existing stub, because it won't handle the floating-point
5636 value. We can't build a new stub, because the linker won't know
5637 which stub to use for the various calls in this object file.
5638 Fortunately, this case is illegal, since it means that a function
5639 was declared in two different ways in a single compilation. */
5640 if (fp_ret_p && !l->fp_ret_p)
5641 error ("cannot handle inconsistent calls to %qs", fnname);
5643 if (retval == NULL_RTX)
5644 insn = gen_call_internal_direct (fn, args_size);
5645 else
5646 insn = gen_call_value_internal_direct (retval, fn, args_size);
5647 insn = mips_emit_call_insn (insn, false);
5649 /* If we are calling a stub which handles a floating-point return
5650 value, we need to arrange to save $18 in the prologue. We do this
5651 by marking the function call as using the register. The prologue
5652 will later see that it is used, and emit code to save it. */
5653 if (fp_ret_p)
5654 CALL_INSN_FUNCTION_USAGE (insn) =
5655 gen_rtx_EXPR_LIST (VOIDmode,
5656 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5657 CALL_INSN_FUNCTION_USAGE (insn));
5659 return insn;
5662 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5664 static bool
5665 mips_ok_for_lazy_binding_p (rtx x)
5667 return (TARGET_USE_GOT
5668 && GET_CODE (x) == SYMBOL_REF
5669 && !mips_symbol_binds_local_p (x));
5672 /* Load function address ADDR into register DEST. SIBCALL_P is true
5673 if the address is needed for a sibling call. Return true if we
5674 used an explicit lazy-binding sequence. */
5676 static bool
5677 mips_load_call_address (rtx dest, rtx addr, bool sibcall_p)
5679 /* If we're generating PIC, and this call is to a global function,
5680 try to allow its address to be resolved lazily. This isn't
5681 possible for sibcalls when $gp is call-saved because the value
5682 of $gp on entry to the stub would be our caller's gp, not ours. */
5683 if (TARGET_EXPLICIT_RELOCS
5684 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5685 && mips_ok_for_lazy_binding_p (addr))
5687 rtx high, lo_sum_symbol;
5689 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5690 addr, SYMBOL_GOTOFF_CALL);
5691 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5692 if (Pmode == SImode)
5693 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5694 else
5695 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5696 return true;
5698 else
5700 mips_emit_move (dest, addr);
5701 return false;
5705 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5706 RESULT is where the result will go (null for "call"s and "sibcall"s),
5707 ADDR is the address of the function, ARGS_SIZE is the size of the
5708 arguments and AUX is the value passed to us by mips_function_arg.
5709 SIBCALL_P is true if we are expanding a sibling call, false if we're
5710 expanding a normal call.
5712 Return the call itself. */
5715 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, bool sibcall_p)
5717 rtx orig_addr, pattern, insn;
5718 bool lazy_p;
5720 orig_addr = addr;
5721 lazy_p = false;
5722 if (!call_insn_operand (addr, VOIDmode))
5724 addr = gen_reg_rtx (Pmode);
5725 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5728 insn = mips16_build_call_stub (result, addr, args_size,
5729 aux == 0 ? 0 : (int) GET_MODE (aux));
5730 if (insn)
5732 gcc_assert (!sibcall_p && !lazy_p);
5733 return insn;
5736 if (result == 0)
5737 pattern = (sibcall_p
5738 ? gen_sibcall_internal (addr, args_size)
5739 : gen_call_internal (addr, args_size));
5740 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5742 /* Handle return values created by mips_return_fpr_pair. */
5743 rtx reg1, reg2;
5745 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5746 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5747 pattern =
5748 (sibcall_p
5749 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5750 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5752 else
5754 /* Handle return values created by mips_return_fpr_single. */
5755 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
5756 result = XEXP (XVECEXP (result, 0, 0), 0);
5757 pattern = (sibcall_p
5758 ? gen_sibcall_value_internal (result, addr, args_size)
5759 : gen_call_value_internal (result, addr, args_size));
5762 return mips_emit_call_insn (pattern, lazy_p);
5765 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5767 static bool
5768 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5770 if (!TARGET_SIBCALLS)
5771 return false;
5773 /* We can't do a sibcall if the called function is a MIPS16 function
5774 because there is no direct "jx" instruction equivalent to "jalx" to
5775 switch the ISA mode. We only care about cases where the sibling
5776 and normal calls would both be direct. */
5777 if (mips_use_mips16_mode_p (decl)
5778 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5779 return false;
5781 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
5782 functions could be MIPS16 ones unless an attribute explicitly tells
5783 us otherwise. */
5784 if (TARGET_INTERLINK_MIPS16
5785 && decl
5786 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
5787 && !mips_nomips16_decl_p (decl)
5788 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5789 return false;
5791 /* Otherwise OK. */
5792 return true;
5795 /* Emit code to move general operand SRC into condition-code
5796 register DEST given that SCRATCH is a scratch TFmode FPR.
5797 The sequence is:
5799 FP1 = SRC
5800 FP2 = 0.0f
5801 DEST = FP2 < FP1
5803 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5805 void
5806 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
5808 rtx fp1, fp2;
5810 /* Change the source to SFmode. */
5811 if (MEM_P (src))
5812 src = adjust_address (src, SFmode, 0);
5813 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5814 src = gen_rtx_REG (SFmode, true_regnum (src));
5816 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5817 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5819 mips_emit_move (copy_rtx (fp1), src);
5820 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5821 emit_insn (gen_slt_sf (dest, fp2, fp1));
5824 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5825 Assume that the areas do not overlap. */
5827 static void
5828 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5830 HOST_WIDE_INT offset, delta;
5831 unsigned HOST_WIDE_INT bits;
5832 int i;
5833 enum machine_mode mode;
5834 rtx *regs;
5836 /* Work out how many bits to move at a time. If both operands have
5837 half-word alignment, it is usually better to move in half words.
5838 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5839 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5840 Otherwise move word-sized chunks. */
5841 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5842 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5843 bits = BITS_PER_WORD / 2;
5844 else
5845 bits = BITS_PER_WORD;
5847 mode = mode_for_size (bits, MODE_INT, 0);
5848 delta = bits / BITS_PER_UNIT;
5850 /* Allocate a buffer for the temporary registers. */
5851 regs = XALLOCAVEC (rtx, length / delta);
5853 /* Load as many BITS-sized chunks as possible. Use a normal load if
5854 the source has enough alignment, otherwise use left/right pairs. */
5855 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5857 regs[i] = gen_reg_rtx (mode);
5858 if (MEM_ALIGN (src) >= bits)
5859 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5860 else
5862 rtx part = adjust_address (src, BLKmode, offset);
5863 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
5864 gcc_unreachable ();
5868 /* Copy the chunks to the destination. */
5869 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5870 if (MEM_ALIGN (dest) >= bits)
5871 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5872 else
5874 rtx part = adjust_address (dest, BLKmode, offset);
5875 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
5876 gcc_unreachable ();
5879 /* Mop up any left-over bytes. */
5880 if (offset < length)
5882 src = adjust_address (src, BLKmode, offset);
5883 dest = adjust_address (dest, BLKmode, offset);
5884 move_by_pieces (dest, src, length - offset,
5885 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5889 /* Helper function for doing a loop-based block operation on memory
5890 reference MEM. Each iteration of the loop will operate on LENGTH
5891 bytes of MEM.
5893 Create a new base register for use within the loop and point it to
5894 the start of MEM. Create a new memory reference that uses this
5895 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5897 static void
5898 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5899 rtx *loop_reg, rtx *loop_mem)
5901 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5903 /* Although the new mem does not refer to a known location,
5904 it does keep up to LENGTH bytes of alignment. */
5905 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5906 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5909 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5910 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5911 the memory regions do not overlap. */
5913 static void
5914 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
5915 HOST_WIDE_INT bytes_per_iter)
5917 rtx label, src_reg, dest_reg, final_src;
5918 HOST_WIDE_INT leftover;
5920 leftover = length % bytes_per_iter;
5921 length -= leftover;
5923 /* Create registers and memory references for use within the loop. */
5924 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
5925 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
5927 /* Calculate the value that SRC_REG should have after the last iteration
5928 of the loop. */
5929 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5930 0, 0, OPTAB_WIDEN);
5932 /* Emit the start of the loop. */
5933 label = gen_label_rtx ();
5934 emit_label (label);
5936 /* Emit the loop body. */
5937 mips_block_move_straight (dest, src, bytes_per_iter);
5939 /* Move on to the next block. */
5940 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
5941 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
5943 /* Emit the loop condition. */
5944 if (Pmode == DImode)
5945 emit_insn (gen_cmpdi (src_reg, final_src));
5946 else
5947 emit_insn (gen_cmpsi (src_reg, final_src));
5948 emit_jump_insn (gen_bne (label));
5950 /* Mop up any left-over bytes. */
5951 if (leftover)
5952 mips_block_move_straight (dest, src, leftover);
5955 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5956 memory reference SRC to memory reference DEST. */
5958 bool
5959 mips_expand_block_move (rtx dest, rtx src, rtx length)
5961 if (GET_CODE (length) == CONST_INT)
5963 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
5965 mips_block_move_straight (dest, src, INTVAL (length));
5966 return true;
5968 else if (optimize)
5970 mips_block_move_loop (dest, src, INTVAL (length),
5971 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
5972 return true;
5975 return false;
5978 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5980 void
5981 mips_expand_synci_loop (rtx begin, rtx end)
5983 rtx inc, label, cmp, cmp_result;
5985 /* Load INC with the cache line size (rdhwr INC,$1). */
5986 inc = gen_reg_rtx (SImode);
5987 emit_insn (gen_rdhwr (inc, const1_rtx));
5989 /* Loop back to here. */
5990 label = gen_label_rtx ();
5991 emit_label (label);
5993 emit_insn (gen_synci (begin));
5995 cmp = mips_force_binary (Pmode, GTU, begin, end);
5997 mips_emit_binary (PLUS, begin, begin, inc);
5999 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6000 emit_jump_insn (gen_condjump (cmp_result, label));
6003 /* Expand a QI or HI mode atomic memory operation.
6005 GENERATOR contains a pointer to the gen_* function that generates
6006 the SI mode underlying atomic operation using masks that we
6007 calculate.
6009 RESULT is the return register for the operation. Its value is NULL
6010 if unused.
6012 MEM is the location of the atomic access.
6014 OLDVAL is the first operand for the operation.
6016 NEWVAL is the optional second operand for the operation. Its value
6017 is NULL if unused. */
6019 void
6020 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6021 rtx result, rtx mem, rtx oldval, rtx newval)
6023 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6024 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6025 rtx res = NULL;
6026 enum machine_mode mode;
6028 mode = GET_MODE (mem);
6030 /* Compute the address of the containing SImode value. */
6031 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6032 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6033 force_reg (Pmode, GEN_INT (-4)));
6035 /* Create a memory reference for it. */
6036 memsi = gen_rtx_MEM (SImode, memsi_addr);
6037 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6038 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6040 /* Work out the byte offset of the QImode or HImode value,
6041 counting from the least significant byte. */
6042 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6043 if (TARGET_BIG_ENDIAN)
6044 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6046 /* Multiply by eight to convert the shift value from bytes to bits. */
6047 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6049 /* Make the final shift an SImode value, so that it can be used in
6050 SImode operations. */
6051 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6053 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6054 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6055 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6056 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6058 /* Compute the equivalent exclusive mask. */
6059 inverted_mask = gen_reg_rtx (SImode);
6060 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6061 gen_rtx_NOT (SImode, mask)));
6063 /* Shift the old value into place. */
6064 if (oldval != const0_rtx)
6066 oldval = convert_modes (SImode, mode, oldval, true);
6067 oldval = force_reg (SImode, oldval);
6068 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6071 /* Do the same for the new value. */
6072 if (newval && newval != const0_rtx)
6074 newval = convert_modes (SImode, mode, newval, true);
6075 newval = force_reg (SImode, newval);
6076 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6079 /* Do the SImode atomic access. */
6080 if (result)
6081 res = gen_reg_rtx (SImode);
6082 if (newval)
6083 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6084 else if (result)
6085 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6086 else
6087 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6089 emit_insn (si_op);
6091 if (result)
6093 /* Shift and convert the result. */
6094 mips_emit_binary (AND, res, res, mask);
6095 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6096 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6100 /* Return true if it is possible to use left/right accesses for a
6101 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6102 returning true, update *OP, *LEFT and *RIGHT as follows:
6104 *OP is a BLKmode reference to the whole field.
6106 *LEFT is a QImode reference to the first byte if big endian or
6107 the last byte if little endian. This address can be used in the
6108 left-side instructions (LWL, SWL, LDL, SDL).
6110 *RIGHT is a QImode reference to the opposite end of the field and
6111 can be used in the patterning right-side instruction. */
6113 static bool
6114 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6115 rtx *left, rtx *right)
6117 rtx first, last;
6119 /* Check that the operand really is a MEM. Not all the extv and
6120 extzv predicates are checked. */
6121 if (!MEM_P (*op))
6122 return false;
6124 /* Check that the size is valid. */
6125 if (width != 32 && (!TARGET_64BIT || width != 64))
6126 return false;
6128 /* We can only access byte-aligned values. Since we are always passed
6129 a reference to the first byte of the field, it is not necessary to
6130 do anything with BITPOS after this check. */
6131 if (bitpos % BITS_PER_UNIT != 0)
6132 return false;
6134 /* Reject aligned bitfields: we want to use a normal load or store
6135 instead of a left/right pair. */
6136 if (MEM_ALIGN (*op) >= width)
6137 return false;
6139 /* Adjust *OP to refer to the whole field. This also has the effect
6140 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6141 *op = adjust_address (*op, BLKmode, 0);
6142 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6144 /* Get references to both ends of the field. We deliberately don't
6145 use the original QImode *OP for FIRST since the new BLKmode one
6146 might have a simpler address. */
6147 first = adjust_address (*op, QImode, 0);
6148 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6150 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6151 correspond to the MSB and RIGHT to the LSB. */
6152 if (TARGET_BIG_ENDIAN)
6153 *left = first, *right = last;
6154 else
6155 *left = last, *right = first;
6157 return true;
6160 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6161 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6162 the operation is the equivalent of:
6164 (set DEST (*_extract SRC WIDTH BITPOS))
6166 Return true on success. */
6168 bool
6169 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6170 HOST_WIDE_INT bitpos)
6172 rtx left, right, temp;
6174 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6175 be a paradoxical word_mode subreg. This is the only case in which
6176 we allow the destination to be larger than the source. */
6177 if (GET_CODE (dest) == SUBREG
6178 && GET_MODE (dest) == DImode
6179 && GET_MODE (SUBREG_REG (dest)) == SImode)
6180 dest = SUBREG_REG (dest);
6182 /* After the above adjustment, the destination must be the same
6183 width as the source. */
6184 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6185 return false;
6187 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6188 return false;
6190 temp = gen_reg_rtx (GET_MODE (dest));
6191 if (GET_MODE (dest) == DImode)
6193 emit_insn (gen_mov_ldl (temp, src, left));
6194 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6196 else
6198 emit_insn (gen_mov_lwl (temp, src, left));
6199 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6201 return true;
6204 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6205 BITPOS and SRC are the operands passed to the expander; the operation
6206 is the equivalent of:
6208 (set (zero_extract DEST WIDTH BITPOS) SRC)
6210 Return true on success. */
6212 bool
6213 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6214 HOST_WIDE_INT bitpos)
6216 rtx left, right;
6217 enum machine_mode mode;
6219 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6220 return false;
6222 mode = mode_for_size (width, MODE_INT, 0);
6223 src = gen_lowpart (mode, src);
6224 if (mode == DImode)
6226 emit_insn (gen_mov_sdl (dest, src, left));
6227 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6229 else
6231 emit_insn (gen_mov_swl (dest, src, left));
6232 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6234 return true;
6237 /* Return true if X is a MEM with the same size as MODE. */
6239 bool
6240 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6242 rtx size;
6244 if (!MEM_P (x))
6245 return false;
6247 size = MEM_SIZE (x);
6248 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6251 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6252 source of an "ext" instruction or the destination of an "ins"
6253 instruction. OP must be a register operand and the following
6254 conditions must hold:
6256 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6257 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6258 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6260 Also reject lengths equal to a word as they are better handled
6261 by the move patterns. */
6263 bool
6264 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6266 if (!ISA_HAS_EXT_INS
6267 || !register_operand (op, VOIDmode)
6268 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6269 return false;
6271 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6272 return false;
6274 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6275 return false;
6277 return true;
6280 /* Return true if -msplit-addresses is selected and should be honored.
6282 -msplit-addresses is a half-way house between explicit relocations
6283 and the traditional assembler macros. It can split absolute 32-bit
6284 symbolic constants into a high/lo_sum pair but uses macros for other
6285 sorts of access.
6287 Like explicit relocation support for REL targets, it relies
6288 on GNU extensions in the assembler and the linker.
6290 Although this code should work for -O0, it has traditionally
6291 been treated as an optimization. */
6293 static bool
6294 mips_split_addresses_p (void)
6296 return (TARGET_SPLIT_ADDRESSES
6297 && optimize
6298 && !TARGET_MIPS16
6299 && !flag_pic
6300 && !ABI_HAS_64BIT_SYMBOLS);
6303 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6305 static void
6306 mips_init_relocs (void)
6308 memset (mips_split_p, '\0', sizeof (mips_split_p));
6309 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6310 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6312 if (ABI_HAS_64BIT_SYMBOLS)
6314 if (TARGET_EXPLICIT_RELOCS)
6316 mips_split_p[SYMBOL_64_HIGH] = true;
6317 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6318 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6320 mips_split_p[SYMBOL_64_MID] = true;
6321 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6322 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6324 mips_split_p[SYMBOL_64_LOW] = true;
6325 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6326 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6328 mips_split_p[SYMBOL_ABSOLUTE] = true;
6329 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6332 else
6334 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6336 mips_split_p[SYMBOL_ABSOLUTE] = true;
6337 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6338 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6340 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6344 if (TARGET_MIPS16)
6346 /* The high part is provided by a pseudo copy of $gp. */
6347 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6348 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6351 if (TARGET_EXPLICIT_RELOCS)
6353 /* Small data constants are kept whole until after reload,
6354 then lowered by mips_rewrite_small_data. */
6355 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6357 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6358 if (TARGET_NEWABI)
6360 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6361 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6363 else
6365 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6366 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6369 if (TARGET_XGOT)
6371 /* The HIGH and LO_SUM are matched by special .md patterns. */
6372 mips_split_p[SYMBOL_GOT_DISP] = true;
6374 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6375 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6376 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6378 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6379 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6380 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6382 else
6384 if (TARGET_NEWABI)
6385 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6386 else
6387 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6388 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6392 if (TARGET_NEWABI)
6394 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6395 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6396 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6399 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6400 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6402 mips_split_p[SYMBOL_DTPREL] = true;
6403 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6404 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6406 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6408 mips_split_p[SYMBOL_TPREL] = true;
6409 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6410 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6412 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6415 /* If OP is an UNSPEC address, return the address to which it refers,
6416 otherwise return OP itself. */
6418 static rtx
6419 mips_strip_unspec_address (rtx op)
6421 rtx base, offset;
6423 split_const (op, &base, &offset);
6424 if (UNSPEC_ADDRESS_P (base))
6425 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6426 return op;
6429 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6430 in context CONTEXT. RELOCS is the array of relocations to use. */
6432 static void
6433 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6434 const char **relocs)
6436 enum mips_symbol_type symbol_type;
6437 const char *p;
6439 symbol_type = mips_classify_symbolic_expression (op, context);
6440 gcc_assert (relocs[symbol_type]);
6442 fputs (relocs[symbol_type], file);
6443 output_addr_const (file, mips_strip_unspec_address (op));
6444 for (p = relocs[symbol_type]; *p != 0; p++)
6445 if (*p == '(')
6446 fputc (')', file);
6449 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6450 The punctuation characters are:
6452 '(' Start a nested ".set noreorder" block.
6453 ')' End a nested ".set noreorder" block.
6454 '[' Start a nested ".set noat" block.
6455 ']' End a nested ".set noat" block.
6456 '<' Start a nested ".set nomacro" block.
6457 '>' End a nested ".set nomacro" block.
6458 '*' Behave like %(%< if generating a delayed-branch sequence.
6459 '#' Print a nop if in a ".set noreorder" block.
6460 '/' Like '#', but do nothing within a delayed-branch sequence.
6461 '?' Print "l" if mips_branch_likely is true
6462 '.' Print the name of the register with a hard-wired zero (zero or $0).
6463 '@' Print the name of the assembler temporary register (at or $1).
6464 '^' Print the name of the pic call-through register (t9 or $25).
6465 '+' Print the name of the gp register (usually gp or $28).
6466 '$' Print the name of the stack pointer register (sp or $29).
6467 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6468 '-' Print ".set pop" under the same conditions for '|'.
6470 See also mips_init_print_operand_pucnt. */
6472 static void
6473 mips_print_operand_punctuation (FILE *file, int ch)
6475 switch (ch)
6477 case '(':
6478 if (set_noreorder++ == 0)
6479 fputs (".set\tnoreorder\n\t", file);
6480 break;
6482 case ')':
6483 gcc_assert (set_noreorder > 0);
6484 if (--set_noreorder == 0)
6485 fputs ("\n\t.set\treorder", file);
6486 break;
6488 case '[':
6489 if (set_noat++ == 0)
6490 fputs (".set\tnoat\n\t", file);
6491 break;
6493 case ']':
6494 gcc_assert (set_noat > 0);
6495 if (--set_noat == 0)
6496 fputs ("\n\t.set\tat", file);
6497 break;
6499 case '<':
6500 if (set_nomacro++ == 0)
6501 fputs (".set\tnomacro\n\t", file);
6502 break;
6504 case '>':
6505 gcc_assert (set_nomacro > 0);
6506 if (--set_nomacro == 0)
6507 fputs ("\n\t.set\tmacro", file);
6508 break;
6510 case '*':
6511 if (final_sequence != 0)
6513 mips_print_operand_punctuation (file, '(');
6514 mips_print_operand_punctuation (file, '<');
6516 break;
6518 case '#':
6519 if (set_noreorder != 0)
6520 fputs ("\n\tnop", file);
6521 break;
6523 case '/':
6524 /* Print an extra newline so that the delayed insn is separated
6525 from the following ones. This looks neater and is consistent
6526 with non-nop delayed sequences. */
6527 if (set_noreorder != 0 && final_sequence == 0)
6528 fputs ("\n\tnop\n", file);
6529 break;
6531 case '?':
6532 if (mips_branch_likely)
6533 putc ('l', file);
6534 break;
6536 case '.':
6537 fputs (reg_names[GP_REG_FIRST + 0], file);
6538 break;
6540 case '@':
6541 fputs (reg_names[GP_REG_FIRST + 1], file);
6542 break;
6544 case '^':
6545 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6546 break;
6548 case '+':
6549 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6550 break;
6552 case '$':
6553 fputs (reg_names[STACK_POINTER_REGNUM], file);
6554 break;
6556 case '|':
6557 if (!ISA_HAS_LL_SC)
6558 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6559 break;
6561 case '-':
6562 if (!ISA_HAS_LL_SC)
6563 fputs ("\n\t.set\tpop", file);
6564 break;
6566 default:
6567 gcc_unreachable ();
6568 break;
6572 /* Initialize mips_print_operand_punct. */
6574 static void
6575 mips_init_print_operand_punct (void)
6577 const char *p;
6579 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6580 mips_print_operand_punct[(unsigned char) *p] = true;
6583 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6584 associated with condition CODE. Print the condition part of the
6585 opcode to FILE. */
6587 static void
6588 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6590 switch (code)
6592 case EQ:
6593 case NE:
6594 case GT:
6595 case GE:
6596 case LT:
6597 case LE:
6598 case GTU:
6599 case GEU:
6600 case LTU:
6601 case LEU:
6602 /* Conveniently, the MIPS names for these conditions are the same
6603 as their RTL equivalents. */
6604 fputs (GET_RTX_NAME (code), file);
6605 break;
6607 default:
6608 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6609 break;
6613 /* Likewise floating-point branches. */
6615 static void
6616 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6618 switch (code)
6620 case EQ:
6621 fputs ("c1f", file);
6622 break;
6624 case NE:
6625 fputs ("c1t", file);
6626 break;
6628 default:
6629 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6630 break;
6634 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6636 'X' Print CONST_INT OP in hexadecimal format.
6637 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6638 'd' Print CONST_INT OP in decimal.
6639 'h' Print the high-part relocation associated with OP, after stripping
6640 any outermost HIGH.
6641 'R' Print the low-part relocation associated with OP.
6642 'C' Print the integer branch condition for comparison OP.
6643 'N' Print the inverse of the integer branch condition for comparison OP.
6644 'F' Print the FPU branch condition for comparison OP.
6645 'W' Print the inverse of the FPU branch condition for comparison OP.
6646 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6647 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6648 't' Like 'T', but with the EQ/NE cases reversed
6649 'Y' Print mips_fp_conditions[INTVAL (OP)]
6650 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6651 'q' Print a DSP accumulator register.
6652 'D' Print the second part of a double-word register or memory operand.
6653 'L' Print the low-order register in a double-word register operand.
6654 'M' Print high-order register in a double-word register operand.
6655 'z' Print $0 if OP is zero, otherwise print OP normally. */
6657 void
6658 mips_print_operand (FILE *file, rtx op, int letter)
6660 enum rtx_code code;
6662 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6664 mips_print_operand_punctuation (file, letter);
6665 return;
6668 gcc_assert (op);
6669 code = GET_CODE (op);
6671 switch (letter)
6673 case 'X':
6674 if (GET_CODE (op) == CONST_INT)
6675 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6676 else
6677 output_operand_lossage ("invalid use of '%%%c'", letter);
6678 break;
6680 case 'x':
6681 if (GET_CODE (op) == CONST_INT)
6682 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6683 else
6684 output_operand_lossage ("invalid use of '%%%c'", letter);
6685 break;
6687 case 'd':
6688 if (GET_CODE (op) == CONST_INT)
6689 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6690 else
6691 output_operand_lossage ("invalid use of '%%%c'", letter);
6692 break;
6694 case 'h':
6695 if (code == HIGH)
6696 op = XEXP (op, 0);
6697 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6698 break;
6700 case 'R':
6701 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6702 break;
6704 case 'C':
6705 mips_print_int_branch_condition (file, code, letter);
6706 break;
6708 case 'N':
6709 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6710 break;
6712 case 'F':
6713 mips_print_float_branch_condition (file, code, letter);
6714 break;
6716 case 'W':
6717 mips_print_float_branch_condition (file, reverse_condition (code),
6718 letter);
6719 break;
6721 case 'T':
6722 case 't':
6724 int truth = (code == NE) == (letter == 'T');
6725 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6727 break;
6729 case 'Y':
6730 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6731 fputs (mips_fp_conditions[UINTVAL (op)], file);
6732 else
6733 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6734 letter);
6735 break;
6737 case 'Z':
6738 if (ISA_HAS_8CC)
6740 mips_print_operand (file, op, 0);
6741 fputc (',', file);
6743 break;
6745 case 'q':
6746 if (code == REG && MD_REG_P (REGNO (op)))
6747 fprintf (file, "$ac0");
6748 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6749 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6750 else
6751 output_operand_lossage ("invalid use of '%%%c'", letter);
6752 break;
6754 default:
6755 switch (code)
6757 case REG:
6759 unsigned int regno = REGNO (op);
6760 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6761 || (letter == 'L' && TARGET_BIG_ENDIAN)
6762 || letter == 'D')
6763 regno++;
6764 fprintf (file, "%s", reg_names[regno]);
6766 break;
6768 case MEM:
6769 if (letter == 'D')
6770 output_address (plus_constant (XEXP (op, 0), 4));
6771 else
6772 output_address (XEXP (op, 0));
6773 break;
6775 default:
6776 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6777 fputs (reg_names[GP_REG_FIRST], file);
6778 else if (CONST_GP_P (op))
6779 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6780 else
6781 output_addr_const (file, mips_strip_unspec_address (op));
6782 break;
6787 /* Output address operand X to FILE. */
6789 void
6790 mips_print_operand_address (FILE *file, rtx x)
6792 struct mips_address_info addr;
6794 if (mips_classify_address (&addr, x, word_mode, true))
6795 switch (addr.type)
6797 case ADDRESS_REG:
6798 mips_print_operand (file, addr.offset, 0);
6799 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6800 return;
6802 case ADDRESS_LO_SUM:
6803 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6804 mips_lo_relocs);
6805 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6806 return;
6808 case ADDRESS_CONST_INT:
6809 output_addr_const (file, x);
6810 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
6811 return;
6813 case ADDRESS_SYMBOLIC:
6814 output_addr_const (file, mips_strip_unspec_address (x));
6815 return;
6817 gcc_unreachable ();
6820 /* Implement TARGET_ENCODE_SECTION_INFO. */
6822 static void
6823 mips_encode_section_info (tree decl, rtx rtl, int first)
6825 default_encode_section_info (decl, rtl, first);
6827 if (TREE_CODE (decl) == FUNCTION_DECL)
6829 rtx symbol = XEXP (rtl, 0);
6830 tree type = TREE_TYPE (decl);
6832 /* Encode whether the symbol is short or long. */
6833 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6834 || mips_far_type_p (type))
6835 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6839 /* Implement TARGET_SELECT_RTX_SECTION. */
6841 static section *
6842 mips_select_rtx_section (enum machine_mode mode, rtx x,
6843 unsigned HOST_WIDE_INT align)
6845 /* ??? Consider using mergeable small data sections. */
6846 if (mips_rtx_constant_in_small_data_p (mode))
6847 return get_named_section (NULL, ".sdata", 0);
6849 return default_elf_select_rtx_section (mode, x, align);
6852 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6854 The complication here is that, with the combination TARGET_ABICALLS
6855 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6856 therefore not be included in the read-only part of a DSO. Handle such
6857 cases by selecting a normal data section instead of a read-only one.
6858 The logic apes that in default_function_rodata_section. */
6860 static section *
6861 mips_function_rodata_section (tree decl)
6863 if (!TARGET_ABICALLS || TARGET_GPWORD)
6864 return default_function_rodata_section (decl);
6866 if (decl && DECL_SECTION_NAME (decl))
6868 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6869 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6871 char *rname = ASTRDUP (name);
6872 rname[14] = 'd';
6873 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6875 else if (flag_function_sections
6876 && flag_data_sections
6877 && strncmp (name, ".text.", 6) == 0)
6879 char *rname = ASTRDUP (name);
6880 memcpy (rname + 1, "data", 4);
6881 return get_section (rname, SECTION_WRITE, decl);
6884 return data_section;
6887 /* Implement TARGET_IN_SMALL_DATA_P. */
6889 static bool
6890 mips_in_small_data_p (const_tree decl)
6892 unsigned HOST_WIDE_INT size;
6894 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6895 return false;
6897 /* We don't yet generate small-data references for -mabicalls
6898 or VxWorks RTP code. See the related -G handling in
6899 mips_override_options. */
6900 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6901 return false;
6903 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6905 const char *name;
6907 /* Reject anything that isn't in a known small-data section. */
6908 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6909 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6910 return false;
6912 /* If a symbol is defined externally, the assembler will use the
6913 usual -G rules when deciding how to implement macros. */
6914 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6915 return true;
6917 else if (TARGET_EMBEDDED_DATA)
6919 /* Don't put constants into the small data section: we want them
6920 to be in ROM rather than RAM. */
6921 if (TREE_CODE (decl) != VAR_DECL)
6922 return false;
6924 if (TREE_READONLY (decl)
6925 && !TREE_SIDE_EFFECTS (decl)
6926 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6927 return false;
6930 /* Enforce -mlocal-sdata. */
6931 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6932 return false;
6934 /* Enforce -mextern-sdata. */
6935 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6937 if (DECL_EXTERNAL (decl))
6938 return false;
6939 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6940 return false;
6943 /* We have traditionally not treated zero-sized objects as small data,
6944 so this is now effectively part of the ABI. */
6945 size = int_size_in_bytes (TREE_TYPE (decl));
6946 return size > 0 && size <= mips_small_data_threshold;
6949 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6950 anchors for small data: the GP register acts as an anchor in that
6951 case. We also don't want to use them for PC-relative accesses,
6952 where the PC acts as an anchor. */
6954 static bool
6955 mips_use_anchors_for_symbol_p (const_rtx symbol)
6957 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6959 case SYMBOL_PC_RELATIVE:
6960 case SYMBOL_GP_RELATIVE:
6961 return false;
6963 default:
6964 return default_use_anchors_for_symbol_p (symbol);
6968 /* The MIPS debug format wants all automatic variables and arguments
6969 to be in terms of the virtual frame pointer (stack pointer before
6970 any adjustment in the function), while the MIPS 3.0 linker wants
6971 the frame pointer to be the stack pointer after the initial
6972 adjustment. So, we do the adjustment here. The arg pointer (which
6973 is eliminated) points to the virtual frame pointer, while the frame
6974 pointer (which may be eliminated) points to the stack pointer after
6975 the initial adjustments. */
6977 HOST_WIDE_INT
6978 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6980 rtx offset2 = const0_rtx;
6981 rtx reg = eliminate_constant_term (addr, &offset2);
6983 if (offset == 0)
6984 offset = INTVAL (offset2);
6986 if (reg == stack_pointer_rtx
6987 || reg == frame_pointer_rtx
6988 || reg == hard_frame_pointer_rtx)
6990 offset -= cfun->machine->frame.total_size;
6991 if (reg == hard_frame_pointer_rtx)
6992 offset += cfun->machine->frame.hard_frame_pointer_offset;
6995 /* sdbout_parms does not want this to crash for unrecognized cases. */
6996 #if 0
6997 else if (reg != arg_pointer_rtx)
6998 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6999 addr);
7000 #endif
7002 return offset;
7005 /* Implement ASM_OUTPUT_EXTERNAL. */
7007 void
7008 mips_output_external (FILE *file, tree decl, const char *name)
7010 default_elf_asm_output_external (file, decl, name);
7012 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7013 set in order to avoid putting out names that are never really
7014 used. */
7015 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7017 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7019 /* When using assembler macros, emit .extern directives for
7020 all small-data externs so that the assembler knows how
7021 big they are.
7023 In most cases it would be safe (though pointless) to emit
7024 .externs for other symbols too. One exception is when an
7025 object is within the -G limit but declared by the user to
7026 be in a section other than .sbss or .sdata. */
7027 fputs ("\t.extern\t", file);
7028 assemble_name (file, name);
7029 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7030 int_size_in_bytes (TREE_TYPE (decl)));
7032 else if (TARGET_IRIX
7033 && mips_abi == ABI_32
7034 && TREE_CODE (decl) == FUNCTION_DECL)
7036 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7037 `.global name .text' directive for every used but
7038 undefined function. If we don't, the linker may perform
7039 an optimization (skipping over the insns that set $gp)
7040 when it is unsafe. */
7041 fputs ("\t.globl ", file);
7042 assemble_name (file, name);
7043 fputs (" .text\n", file);
7048 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7050 void
7051 mips_output_filename (FILE *stream, const char *name)
7053 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7054 directives. */
7055 if (write_symbols == DWARF2_DEBUG)
7056 return;
7057 else if (mips_output_filename_first_time)
7059 mips_output_filename_first_time = 0;
7060 num_source_filenames += 1;
7061 current_function_file = name;
7062 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7063 output_quoted_string (stream, name);
7064 putc ('\n', stream);
7066 /* If we are emitting stabs, let dbxout.c handle this (except for
7067 the mips_output_filename_first_time case). */
7068 else if (write_symbols == DBX_DEBUG)
7069 return;
7070 else if (name != current_function_file
7071 && strcmp (name, current_function_file) != 0)
7073 num_source_filenames += 1;
7074 current_function_file = name;
7075 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7076 output_quoted_string (stream, name);
7077 putc ('\n', stream);
7081 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7083 static void ATTRIBUTE_UNUSED
7084 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7086 switch (size)
7088 case 4:
7089 fputs ("\t.dtprelword\t", file);
7090 break;
7092 case 8:
7093 fputs ("\t.dtpreldword\t", file);
7094 break;
7096 default:
7097 gcc_unreachable ();
7099 output_addr_const (file, x);
7100 fputs ("+0x8000", file);
7103 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7105 static rtx
7106 mips_dwarf_register_span (rtx reg)
7108 rtx high, low;
7109 enum machine_mode mode;
7111 /* By default, GCC maps increasing register numbers to increasing
7112 memory locations, but paired FPRs are always little-endian,
7113 regardless of the prevailing endianness. */
7114 mode = GET_MODE (reg);
7115 if (FP_REG_P (REGNO (reg))
7116 && TARGET_BIG_ENDIAN
7117 && MAX_FPRS_PER_FMT > 1
7118 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7120 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7121 high = mips_subword (reg, true);
7122 low = mips_subword (reg, false);
7123 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7126 return NULL_RTX;
7129 /* Implement ASM_OUTPUT_ASCII. */
7131 void
7132 mips_output_ascii (FILE *stream, const char *string, size_t len)
7134 size_t i;
7135 int cur_pos;
7137 cur_pos = 17;
7138 fprintf (stream, "\t.ascii\t\"");
7139 for (i = 0; i < len; i++)
7141 int c;
7143 c = (unsigned char) string[i];
7144 if (ISPRINT (c))
7146 if (c == '\\' || c == '\"')
7148 putc ('\\', stream);
7149 cur_pos++;
7151 putc (c, stream);
7152 cur_pos++;
7154 else
7156 fprintf (stream, "\\%03o", c);
7157 cur_pos += 4;
7160 if (cur_pos > 72 && i+1 < len)
7162 cur_pos = 17;
7163 fprintf (stream, "\"\n\t.ascii\t\"");
7166 fprintf (stream, "\"\n");
7169 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7170 macros, mark the symbol as written so that mips_asm_output_external
7171 won't emit an .extern for it. STREAM is the output file, NAME is the
7172 name of the symbol, INIT_STRING is the string that should be written
7173 before the symbol and FINAL_STRING is the string that should be
7174 written after it. FINAL_STRING is a printf format that consumes the
7175 remaining arguments. */
7177 void
7178 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7179 const char *final_string, ...)
7181 va_list ap;
7183 fputs (init_string, stream);
7184 assemble_name (stream, name);
7185 va_start (ap, final_string);
7186 vfprintf (stream, final_string, ap);
7187 va_end (ap);
7189 if (!TARGET_EXPLICIT_RELOCS)
7191 tree name_tree = get_identifier (name);
7192 TREE_ASM_WRITTEN (name_tree) = 1;
7196 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7197 NAME is the name of the object and ALIGN is the required alignment
7198 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7199 alignment argument. */
7201 void
7202 mips_declare_common_object (FILE *stream, const char *name,
7203 const char *init_string,
7204 unsigned HOST_WIDE_INT size,
7205 unsigned int align, bool takes_alignment_p)
7207 if (!takes_alignment_p)
7209 size += (align / BITS_PER_UNIT) - 1;
7210 size -= size % (align / BITS_PER_UNIT);
7211 mips_declare_object (stream, name, init_string,
7212 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7214 else
7215 mips_declare_object (stream, name, init_string,
7216 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7217 size, align / BITS_PER_UNIT);
7220 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7221 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7223 void
7224 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7225 unsigned HOST_WIDE_INT size,
7226 unsigned int align)
7228 /* If the target wants uninitialized const declarations in
7229 .rdata then don't put them in .comm. */
7230 if (TARGET_EMBEDDED_DATA
7231 && TARGET_UNINIT_CONST_IN_RODATA
7232 && TREE_CODE (decl) == VAR_DECL
7233 && TREE_READONLY (decl)
7234 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7236 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7237 targetm.asm_out.globalize_label (stream, name);
7239 switch_to_section (readonly_data_section);
7240 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7241 mips_declare_object (stream, name, "",
7242 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7243 size);
7245 else
7246 mips_declare_common_object (stream, name, "\n\t.comm\t",
7247 size, align, true);
7250 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7251 extern int size_directive_output;
7253 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7254 definitions except that it uses mips_declare_object to emit the label. */
7256 void
7257 mips_declare_object_name (FILE *stream, const char *name,
7258 tree decl ATTRIBUTE_UNUSED)
7260 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7261 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7262 #endif
7264 size_directive_output = 0;
7265 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7267 HOST_WIDE_INT size;
7269 size_directive_output = 1;
7270 size = int_size_in_bytes (TREE_TYPE (decl));
7271 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7274 mips_declare_object (stream, name, "", ":\n");
7277 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7279 void
7280 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7282 const char *name;
7284 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7285 if (!flag_inhibit_size_directive
7286 && DECL_SIZE (decl) != 0
7287 && !at_end
7288 && top_level
7289 && DECL_INITIAL (decl) == error_mark_node
7290 && !size_directive_output)
7292 HOST_WIDE_INT size;
7294 size_directive_output = 1;
7295 size = int_size_in_bytes (TREE_TYPE (decl));
7296 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7299 #endif
7301 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7302 with the current ABI. */
7304 static const char *
7305 mips_mdebug_abi_name (void)
7307 switch (mips_abi)
7309 case ABI_32:
7310 return "abi32";
7311 case ABI_O64:
7312 return "abiO64";
7313 case ABI_N32:
7314 return "abiN32";
7315 case ABI_64:
7316 return "abiN64";
7317 case ABI_EABI:
7318 return TARGET_64BIT ? "eabi64" : "eabi32";
7319 default:
7320 gcc_unreachable ();
7324 /* Implement TARGET_ASM_FILE_START. */
7326 static void
7327 mips_file_start (void)
7329 default_file_start ();
7331 /* Generate a special section to describe the ABI switches used to
7332 produce the resultant binary. This is unnecessary on IRIX and
7333 causes unwanted warnings from the native linker. */
7334 if (!TARGET_IRIX)
7336 /* Record the ABI itself. Modern versions of binutils encode
7337 this information in the ELF header flags, but GDB needs the
7338 information in order to correctly debug binaries produced by
7339 older binutils. See the function mips_gdbarch_init in
7340 gdb/mips-tdep.c. */
7341 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7342 mips_mdebug_abi_name ());
7344 /* There is no ELF header flag to distinguish long32 forms of the
7345 EABI from long64 forms. Emit a special section to help tools
7346 such as GDB. Do the same for o64, which is sometimes used with
7347 -mlong64. */
7348 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7349 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7350 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7352 #ifdef HAVE_AS_GNU_ATTRIBUTE
7353 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7354 (TARGET_HARD_FLOAT_ABI
7355 ? (TARGET_DOUBLE_FLOAT
7356 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7357 #endif
7360 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7361 if (TARGET_ABICALLS)
7362 fprintf (asm_out_file, "\t.abicalls\n");
7364 if (flag_verbose_asm)
7365 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7366 ASM_COMMENT_START,
7367 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7370 /* Make the last instruction frame-related and note that it performs
7371 the operation described by FRAME_PATTERN. */
7373 static void
7374 mips_set_frame_expr (rtx frame_pattern)
7376 rtx insn;
7378 insn = get_last_insn ();
7379 RTX_FRAME_RELATED_P (insn) = 1;
7380 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7381 frame_pattern,
7382 REG_NOTES (insn));
7385 /* Return a frame-related rtx that stores REG at MEM.
7386 REG must be a single register. */
7388 static rtx
7389 mips_frame_set (rtx mem, rtx reg)
7391 rtx set;
7393 /* If we're saving the return address register and the DWARF return
7394 address column differs from the hard register number, adjust the
7395 note reg to refer to the former. */
7396 if (REGNO (reg) == GP_REG_FIRST + 31
7397 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7398 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7400 set = gen_rtx_SET (VOIDmode, mem, reg);
7401 RTX_FRAME_RELATED_P (set) = 1;
7403 return set;
7406 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7407 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7408 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7409 static const unsigned char mips16e_s2_s8_regs[] = {
7410 30, 23, 22, 21, 20, 19, 18
7412 static const unsigned char mips16e_a0_a3_regs[] = {
7413 4, 5, 6, 7
7416 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7417 ordered from the uppermost in memory to the lowest in memory. */
7418 static const unsigned char mips16e_save_restore_regs[] = {
7419 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7422 /* Return the index of the lowest X in the range [0, SIZE) for which
7423 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7425 static unsigned int
7426 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7427 unsigned int size)
7429 unsigned int i;
7431 for (i = 0; i < size; i++)
7432 if (BITSET_P (mask, regs[i]))
7433 break;
7435 return i;
7438 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7439 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7440 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7441 is true for all indexes (X, SIZE). */
7443 static void
7444 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7445 unsigned int size, unsigned int *num_regs_ptr)
7447 unsigned int i;
7449 i = mips16e_find_first_register (*mask_ptr, regs, size);
7450 for (i++; i < size; i++)
7451 if (!BITSET_P (*mask_ptr, regs[i]))
7453 *num_regs_ptr += 1;
7454 *mask_ptr |= 1 << regs[i];
7458 /* Return a simplified form of X using the register values in REG_VALUES.
7459 REG_VALUES[R] is the last value assigned to hard register R, or null
7460 if R has not been modified.
7462 This function is rather limited, but is good enough for our purposes. */
7464 static rtx
7465 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7467 x = avoid_constant_pool_reference (x);
7469 if (UNARY_P (x))
7471 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7472 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7473 x0, GET_MODE (XEXP (x, 0)));
7476 if (ARITHMETIC_P (x))
7478 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7479 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7480 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7483 if (REG_P (x)
7484 && reg_values[REGNO (x)]
7485 && !rtx_unstable_p (reg_values[REGNO (x)]))
7486 return reg_values[REGNO (x)];
7488 return x;
7491 /* Return true if (set DEST SRC) stores an argument register into its
7492 caller-allocated save slot, storing the number of that argument
7493 register in *REGNO_PTR if so. REG_VALUES is as for
7494 mips16e_collect_propagate_value. */
7496 static bool
7497 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7498 unsigned int *regno_ptr)
7500 unsigned int argno, regno;
7501 HOST_WIDE_INT offset, required_offset;
7502 rtx addr, base;
7504 /* Check that this is a word-mode store. */
7505 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7506 return false;
7508 /* Check that the register being saved is an unmodified argument
7509 register. */
7510 regno = REGNO (src);
7511 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7512 return false;
7513 argno = regno - GP_ARG_FIRST;
7515 /* Check whether the address is an appropriate stack-pointer or
7516 frame-pointer access. */
7517 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7518 mips_split_plus (addr, &base, &offset);
7519 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7520 if (base == hard_frame_pointer_rtx)
7521 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7522 else if (base != stack_pointer_rtx)
7523 return false;
7524 if (offset != required_offset)
7525 return false;
7527 *regno_ptr = regno;
7528 return true;
7531 /* A subroutine of mips_expand_prologue, called only when generating
7532 MIPS16e SAVE instructions. Search the start of the function for any
7533 instructions that save argument registers into their caller-allocated
7534 save slots. Delete such instructions and return a value N such that
7535 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7536 instructions redundant. */
7538 static unsigned int
7539 mips16e_collect_argument_saves (void)
7541 rtx reg_values[FIRST_PSEUDO_REGISTER];
7542 rtx insn, next, set, dest, src;
7543 unsigned int nargs, regno;
7545 push_topmost_sequence ();
7546 nargs = 0;
7547 memset (reg_values, 0, sizeof (reg_values));
7548 for (insn = get_insns (); insn; insn = next)
7550 next = NEXT_INSN (insn);
7551 if (NOTE_P (insn))
7552 continue;
7554 if (!INSN_P (insn))
7555 break;
7557 set = PATTERN (insn);
7558 if (GET_CODE (set) != SET)
7559 break;
7561 dest = SET_DEST (set);
7562 src = SET_SRC (set);
7563 if (mips16e_collect_argument_save_p (dest, src, reg_values, &regno))
7565 if (!BITSET_P (cfun->machine->frame.mask, regno))
7567 delete_insn (insn);
7568 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7571 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7572 reg_values[REGNO (dest)]
7573 = mips16e_collect_propagate_value (src, reg_values);
7574 else
7575 break;
7577 pop_topmost_sequence ();
7579 return nargs;
7582 /* Return a move between register REGNO and memory location SP + OFFSET.
7583 Make the move a load if RESTORE_P, otherwise make it a frame-related
7584 store. */
7586 static rtx
7587 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7588 unsigned int regno)
7590 rtx reg, mem;
7592 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7593 reg = gen_rtx_REG (SImode, regno);
7594 return (restore_p
7595 ? gen_rtx_SET (VOIDmode, reg, mem)
7596 : mips_frame_set (mem, reg));
7599 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7600 The instruction must:
7602 - Allocate or deallocate SIZE bytes in total; SIZE is known
7603 to be nonzero.
7605 - Save or restore as many registers in *MASK_PTR as possible.
7606 The instruction saves the first registers at the top of the
7607 allocated area, with the other registers below it.
7609 - Save NARGS argument registers above the allocated area.
7611 (NARGS is always zero if RESTORE_P.)
7613 The SAVE and RESTORE instructions cannot save and restore all general
7614 registers, so there may be some registers left over for the caller to
7615 handle. Destructively modify *MASK_PTR so that it contains the registers
7616 that still need to be saved or restored. The caller can save these
7617 registers in the memory immediately below *OFFSET_PTR, which is a
7618 byte offset from the bottom of the allocated stack area. */
7620 static rtx
7621 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7622 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7623 HOST_WIDE_INT size)
7625 rtx pattern, set;
7626 HOST_WIDE_INT offset, top_offset;
7627 unsigned int i, regno;
7628 int n;
7630 gcc_assert (cfun->machine->frame.num_fp == 0);
7632 /* Calculate the number of elements in the PARALLEL. We need one element
7633 for the stack adjustment, one for each argument register save, and one
7634 for each additional register move. */
7635 n = 1 + nargs;
7636 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7637 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7638 n++;
7640 /* Create the final PARALLEL. */
7641 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7642 n = 0;
7644 /* Add the stack pointer adjustment. */
7645 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7646 plus_constant (stack_pointer_rtx,
7647 restore_p ? size : -size));
7648 RTX_FRAME_RELATED_P (set) = 1;
7649 XVECEXP (pattern, 0, n++) = set;
7651 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7652 top_offset = restore_p ? size : 0;
7654 /* Save the arguments. */
7655 for (i = 0; i < nargs; i++)
7657 offset = top_offset + i * UNITS_PER_WORD;
7658 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7659 XVECEXP (pattern, 0, n++) = set;
7662 /* Then fill in the other register moves. */
7663 offset = top_offset;
7664 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7666 regno = mips16e_save_restore_regs[i];
7667 if (BITSET_P (*mask_ptr, regno))
7669 offset -= UNITS_PER_WORD;
7670 set = mips16e_save_restore_reg (restore_p, offset, regno);
7671 XVECEXP (pattern, 0, n++) = set;
7672 *mask_ptr &= ~(1 << regno);
7676 /* Tell the caller what offset it should use for the remaining registers. */
7677 *offset_ptr = size + (offset - top_offset);
7679 gcc_assert (n == XVECLEN (pattern, 0));
7681 return pattern;
7684 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7685 pointer. Return true if PATTERN matches the kind of instruction
7686 generated by mips16e_build_save_restore. If INFO is nonnull,
7687 initialize it when returning true. */
7689 bool
7690 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7691 struct mips16e_save_restore_info *info)
7693 unsigned int i, nargs, mask, extra;
7694 HOST_WIDE_INT top_offset, save_offset, offset;
7695 rtx set, reg, mem, base;
7696 int n;
7698 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7699 return false;
7701 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7702 top_offset = adjust > 0 ? adjust : 0;
7704 /* Interpret all other members of the PARALLEL. */
7705 save_offset = top_offset - UNITS_PER_WORD;
7706 mask = 0;
7707 nargs = 0;
7708 i = 0;
7709 for (n = 1; n < XVECLEN (pattern, 0); n++)
7711 /* Check that we have a SET. */
7712 set = XVECEXP (pattern, 0, n);
7713 if (GET_CODE (set) != SET)
7714 return false;
7716 /* Check that the SET is a load (if restoring) or a store
7717 (if saving). */
7718 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7719 if (!MEM_P (mem))
7720 return false;
7722 /* Check that the address is the sum of the stack pointer and a
7723 possibly-zero constant offset. */
7724 mips_split_plus (XEXP (mem, 0), &base, &offset);
7725 if (base != stack_pointer_rtx)
7726 return false;
7728 /* Check that SET's other operand is a register. */
7729 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7730 if (!REG_P (reg))
7731 return false;
7733 /* Check for argument saves. */
7734 if (offset == top_offset + nargs * UNITS_PER_WORD
7735 && REGNO (reg) == GP_ARG_FIRST + nargs)
7736 nargs++;
7737 else if (offset == save_offset)
7739 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7740 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7741 return false;
7743 mask |= 1 << REGNO (reg);
7744 save_offset -= UNITS_PER_WORD;
7746 else
7747 return false;
7750 /* Check that the restrictions on register ranges are met. */
7751 extra = 0;
7752 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7753 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7754 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7755 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7756 if (extra != 0)
7757 return false;
7759 /* Make sure that the topmost argument register is not saved twice.
7760 The checks above ensure that the same is then true for the other
7761 argument registers. */
7762 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7763 return false;
7765 /* Pass back information, if requested. */
7766 if (info)
7768 info->nargs = nargs;
7769 info->mask = mask;
7770 info->size = (adjust > 0 ? adjust : -adjust);
7773 return true;
7776 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7777 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7778 the null terminator. */
7780 static char *
7781 mips16e_add_register_range (char *s, unsigned int min_reg,
7782 unsigned int max_reg)
7784 if (min_reg != max_reg)
7785 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7786 else
7787 s += sprintf (s, ",%s", reg_names[min_reg]);
7788 return s;
7791 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7792 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7794 const char *
7795 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7797 static char buffer[300];
7799 struct mips16e_save_restore_info info;
7800 unsigned int i, end;
7801 char *s;
7803 /* Parse the pattern. */
7804 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7805 gcc_unreachable ();
7807 /* Add the mnemonic. */
7808 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7809 s += strlen (s);
7811 /* Save the arguments. */
7812 if (info.nargs > 1)
7813 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7814 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7815 else if (info.nargs == 1)
7816 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7818 /* Emit the amount of stack space to allocate or deallocate. */
7819 s += sprintf (s, "%d", (int) info.size);
7821 /* Save or restore $16. */
7822 if (BITSET_P (info.mask, 16))
7823 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7825 /* Save or restore $17. */
7826 if (BITSET_P (info.mask, 17))
7827 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7829 /* Save or restore registers in the range $s2...$s8, which
7830 mips16e_s2_s8_regs lists in decreasing order. Note that this
7831 is a software register range; the hardware registers are not
7832 numbered consecutively. */
7833 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7834 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7835 if (i < end)
7836 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7837 mips16e_s2_s8_regs[i]);
7839 /* Save or restore registers in the range $a0...$a3. */
7840 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7841 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7842 if (i < end)
7843 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7844 mips16e_a0_a3_regs[end - 1]);
7846 /* Save or restore $31. */
7847 if (BITSET_P (info.mask, 31))
7848 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7850 return buffer;
7853 /* Return true if the current function has an insn that implicitly
7854 refers to $gp. */
7856 static bool
7857 mips_function_has_gp_insn (void)
7859 /* Don't bother rechecking if we found one last time. */
7860 if (!cfun->machine->has_gp_insn_p)
7862 rtx insn;
7864 push_topmost_sequence ();
7865 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7866 if (USEFUL_INSN_P (insn)
7867 && (get_attr_got (insn) != GOT_UNSET
7868 || mips_small_data_pattern_p (PATTERN (insn))))
7870 cfun->machine->has_gp_insn_p = true;
7871 break;
7873 pop_topmost_sequence ();
7875 return cfun->machine->has_gp_insn_p;
7878 /* Return the register that should be used as the global pointer
7879 within this function. Return 0 if the function doesn't need
7880 a global pointer. */
7882 static unsigned int
7883 mips_global_pointer (void)
7885 unsigned int regno;
7887 /* $gp is always available unless we're using a GOT. */
7888 if (!TARGET_USE_GOT)
7889 return GLOBAL_POINTER_REGNUM;
7891 /* We must always provide $gp when it is used implicitly. */
7892 if (!TARGET_EXPLICIT_RELOCS)
7893 return GLOBAL_POINTER_REGNUM;
7895 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7896 a valid gp. */
7897 if (crtl->profile)
7898 return GLOBAL_POINTER_REGNUM;
7900 /* If the function has a nonlocal goto, $gp must hold the correct
7901 global pointer for the target function. */
7902 if (crtl->has_nonlocal_goto)
7903 return GLOBAL_POINTER_REGNUM;
7905 /* If the gp is never referenced, there's no need to initialize it.
7906 Note that reload can sometimes introduce constant pool references
7907 into a function that otherwise didn't need them. For example,
7908 suppose we have an instruction like:
7910 (set (reg:DF R1) (float:DF (reg:SI R2)))
7912 If R2 turns out to be constant such as 1, the instruction may have a
7913 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7914 using this constant if R2 doesn't get allocated to a register.
7916 In cases like these, reload will have added the constant to the pool
7917 but no instruction will yet refer to it. */
7918 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7919 && !crtl->uses_const_pool
7920 && !mips_function_has_gp_insn ())
7921 return 0;
7923 /* We need a global pointer, but perhaps we can use a call-clobbered
7924 register instead of $gp. */
7925 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7926 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7927 if (!df_regs_ever_live_p (regno)
7928 && call_really_used_regs[regno]
7929 && !fixed_regs[regno]
7930 && regno != PIC_FUNCTION_ADDR_REGNUM)
7931 return regno;
7933 return GLOBAL_POINTER_REGNUM;
7936 /* Return true if the current function returns its value in a floating-point
7937 register in MIPS16 mode. */
7939 static bool
7940 mips16_cfun_returns_in_fpr_p (void)
7942 tree return_type = DECL_RESULT (current_function_decl);
7943 return (TARGET_MIPS16
7944 && TARGET_HARD_FLOAT_ABI
7945 && !aggregate_value_p (return_type, current_function_decl)
7946 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7949 /* Return true if the current function must save register REGNO. */
7951 static bool
7952 mips_save_reg_p (unsigned int regno)
7954 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7955 if we have not chosen a call-clobbered substitute. */
7956 if (regno == GLOBAL_POINTER_REGNUM)
7957 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7959 /* Check call-saved registers. */
7960 if ((crtl->saves_all_registers || df_regs_ever_live_p (regno))
7961 && !call_really_used_regs[regno])
7962 return true;
7964 /* Save both registers in an FPR pair if either one is used. This is
7965 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7966 register to be used without the even register. */
7967 if (FP_REG_P (regno)
7968 && MAX_FPRS_PER_FMT == 2
7969 && df_regs_ever_live_p (regno + 1)
7970 && !call_really_used_regs[regno + 1])
7971 return true;
7973 /* We need to save the old frame pointer before setting up a new one. */
7974 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7975 return true;
7977 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7978 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7979 return true;
7981 /* We need to save the incoming return address if it is ever clobbered
7982 within the function, if __builtin_eh_return is being used to set a
7983 different return address, or if a stub is being used to return a
7984 value in FPRs. */
7985 if (regno == GP_REG_FIRST + 31
7986 && (df_regs_ever_live_p (regno)
7987 || crtl->calls_eh_return
7988 || mips16_cfun_returns_in_fpr_p ()))
7989 return true;
7991 return false;
7994 /* Populate the current function's mips_frame_info structure.
7996 MIPS stack frames look like:
7998 +-------------------------------+
8000 | incoming stack arguments |
8002 +-------------------------------+
8004 | caller-allocated save area |
8005 A | for register arguments |
8007 +-------------------------------+ <-- incoming stack pointer
8009 | callee-allocated save area |
8010 B | for arguments that are |
8011 | split between registers and |
8012 | the stack |
8014 +-------------------------------+ <-- arg_pointer_rtx
8016 C | callee-allocated save area |
8017 | for register varargs |
8019 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
8020 | | + UNITS_PER_HWFPVALUE
8021 | FPR save area |
8023 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
8024 | | + UNITS_PER_WORD
8025 | GPR save area |
8027 +-------------------------------+
8028 | | \
8029 | local variables | | var_size
8030 | | /
8031 +-------------------------------+
8032 | | \
8033 | $gp save area | | cprestore_size
8034 | | /
8035 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8036 | | MIPS16 code
8037 | outgoing stack arguments |
8039 +-------------------------------+
8041 | caller-allocated save area |
8042 | for register arguments |
8044 +-------------------------------+ <-- stack_pointer_rtx
8045 frame_pointer_rtx
8046 hard_frame_pointer_rtx for
8047 non-MIPS16 code.
8049 At least two of A, B and C will be empty.
8051 Dynamic stack allocations such as alloca insert data at point P.
8052 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8053 hard_frame_pointer_rtx unchanged. */
8055 static void
8056 mips_compute_frame_info (void)
8058 struct mips_frame_info *frame;
8059 HOST_WIDE_INT offset, size;
8060 unsigned int regno, i;
8062 frame = &cfun->machine->frame;
8063 memset (frame, 0, sizeof (*frame));
8064 size = get_frame_size ();
8066 cfun->machine->global_pointer = mips_global_pointer ();
8068 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8069 area and the $gp save slot. This area isn't needed in leaf functions,
8070 but if the target-independent frame size is nonzero, we're committed
8071 to allocating it anyway. */
8072 if (size == 0 && current_function_is_leaf)
8074 /* The MIPS 3.0 linker does not like functions that dynamically
8075 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8076 looks like we are trying to create a second frame pointer to the
8077 function, so allocate some stack space to make it happy. */
8078 if (cfun->calls_alloca)
8079 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8080 else
8081 frame->args_size = 0;
8082 frame->cprestore_size = 0;
8084 else
8086 frame->args_size = crtl->outgoing_args_size;
8087 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
8089 offset = frame->args_size + frame->cprestore_size;
8091 /* Move above the local variables. */
8092 frame->var_size = MIPS_STACK_ALIGN (size);
8093 offset += frame->var_size;
8095 /* Find out which GPRs we need to save. */
8096 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8097 if (mips_save_reg_p (regno))
8099 frame->num_gp++;
8100 frame->mask |= 1 << (regno - GP_REG_FIRST);
8103 /* If this function calls eh_return, we must also save and restore the
8104 EH data registers. */
8105 if (crtl->calls_eh_return)
8106 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8108 frame->num_gp++;
8109 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8112 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8113 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8114 save all later registers too. */
8115 if (GENERATE_MIPS16E_SAVE_RESTORE)
8117 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8118 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8119 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8120 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8123 /* Move above the GPR save area. */
8124 if (frame->num_gp > 0)
8126 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8127 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8130 /* Find out which FPRs we need to save. This loop must iterate over
8131 the same space as its companion in mips_for_each_saved_reg. */
8132 if (TARGET_HARD_FLOAT)
8133 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8134 if (mips_save_reg_p (regno))
8136 frame->num_fp += MAX_FPRS_PER_FMT;
8137 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8140 /* Move above the FPR save area. */
8141 if (frame->num_fp > 0)
8143 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8144 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8147 /* Move above the callee-allocated varargs save area. */
8148 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8149 frame->arg_pointer_offset = offset;
8151 /* Move above the callee-allocated area for pretend stack arguments. */
8152 offset += crtl->args.pretend_args_size;
8153 frame->total_size = offset;
8155 /* Work out the offsets of the save areas from the top of the frame. */
8156 if (frame->gp_sp_offset > 0)
8157 frame->gp_save_offset = frame->gp_sp_offset - offset;
8158 if (frame->fp_sp_offset > 0)
8159 frame->fp_save_offset = frame->fp_sp_offset - offset;
8161 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8162 arguments. This tends to increase the chances of using unextended
8163 instructions for local variables and incoming arguments. */
8164 if (TARGET_MIPS16)
8165 frame->hard_frame_pointer_offset = frame->args_size;
8168 /* Return the style of GP load sequence that is being used for the
8169 current function. */
8171 enum mips_loadgp_style
8172 mips_current_loadgp_style (void)
8174 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
8175 return LOADGP_NONE;
8177 if (TARGET_RTP_PIC)
8178 return LOADGP_RTP;
8180 if (TARGET_ABSOLUTE_ABICALLS)
8181 return LOADGP_ABSOLUTE;
8183 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8186 /* Implement FRAME_POINTER_REQUIRED. */
8188 bool
8189 mips_frame_pointer_required (void)
8191 /* If the function contains dynamic stack allocations, we need to
8192 use the frame pointer to access the static parts of the frame. */
8193 if (cfun->calls_alloca)
8194 return true;
8196 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8197 reload may be unable to compute the address of a local variable,
8198 since there is no way to add a large constant to the stack pointer
8199 without using a second temporary register. */
8200 if (TARGET_MIPS16)
8202 mips_compute_frame_info ();
8203 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8204 return true;
8207 return false;
8210 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8211 or argument pointer. TO is either the stack pointer or hard frame
8212 pointer. */
8214 HOST_WIDE_INT
8215 mips_initial_elimination_offset (int from, int to)
8217 HOST_WIDE_INT offset;
8219 mips_compute_frame_info ();
8221 /* Set OFFSET to the offset from the soft frame pointer, which is also
8222 the offset from the end-of-prologue stack pointer. */
8223 switch (from)
8225 case FRAME_POINTER_REGNUM:
8226 offset = 0;
8227 break;
8229 case ARG_POINTER_REGNUM:
8230 offset = cfun->machine->frame.arg_pointer_offset;
8231 break;
8233 default:
8234 gcc_unreachable ();
8237 if (to == HARD_FRAME_POINTER_REGNUM)
8238 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8240 return offset;
8243 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8245 static void
8246 mips_extra_live_on_entry (bitmap regs)
8248 if (TARGET_USE_GOT)
8250 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8251 the global pointer. */
8252 if (!TARGET_ABSOLUTE_ABICALLS)
8253 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8255 /* See the comment above load_call<mode> for details. */
8256 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8260 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8261 previous frame. */
8264 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8266 if (count != 0)
8267 return const0_rtx;
8269 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8272 /* Emit code to change the current function's return address to
8273 ADDRESS. SCRATCH is available as a scratch register, if needed.
8274 ADDRESS and SCRATCH are both word-mode GPRs. */
8276 void
8277 mips_set_return_address (rtx address, rtx scratch)
8279 rtx slot_address;
8281 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
8282 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8283 cfun->machine->frame.gp_sp_offset);
8284 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8287 /* Restore $gp from its save slot. Valid only when using o32 or
8288 o64 abicalls. */
8290 void
8291 mips_restore_gp (void)
8293 rtx base, address;
8295 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8297 base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
8298 address = mips_add_offset (pic_offset_table_rtx, base,
8299 crtl->outgoing_args_size);
8300 mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
8301 if (!TARGET_EXPLICIT_RELOCS)
8302 emit_insn (gen_blockage ());
8305 /* A function to save or store a register. The first argument is the
8306 register and the second is the stack slot. */
8307 typedef void (*mips_save_restore_fn) (rtx, rtx);
8309 /* Use FN to save or restore register REGNO. MODE is the register's
8310 mode and OFFSET is the offset of its save slot from the current
8311 stack pointer. */
8313 static void
8314 mips_save_restore_reg (enum machine_mode mode, int regno,
8315 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8317 rtx mem;
8319 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8320 fn (gen_rtx_REG (mode, regno), mem);
8323 /* Call FN for each register that is saved by the current function.
8324 SP_OFFSET is the offset of the current stack pointer from the start
8325 of the frame. */
8327 static void
8328 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8330 enum machine_mode fpr_mode;
8331 HOST_WIDE_INT offset;
8332 int regno;
8334 /* Save registers starting from high to low. The debuggers prefer at least
8335 the return register be stored at func+4, and also it allows us not to
8336 need a nop in the epilogue if at least one register is reloaded in
8337 addition to return address. */
8338 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8339 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8340 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8342 mips_save_restore_reg (word_mode, regno, offset, fn);
8343 offset -= UNITS_PER_WORD;
8346 /* This loop must iterate over the same space as its companion in
8347 mips_compute_frame_info. */
8348 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8349 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8350 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8351 regno >= FP_REG_FIRST;
8352 regno -= MAX_FPRS_PER_FMT)
8353 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8355 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8356 offset -= GET_MODE_SIZE (fpr_mode);
8360 /* If we're generating n32 or n64 abicalls, and the current function
8361 does not use $28 as its global pointer, emit a cplocal directive.
8362 Use pic_offset_table_rtx as the argument to the directive. */
8364 static void
8365 mips_output_cplocal (void)
8367 if (!TARGET_EXPLICIT_RELOCS
8368 && cfun->machine->global_pointer > 0
8369 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8370 output_asm_insn (".cplocal %+", 0);
8373 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8375 static void
8376 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8378 const char *fnname;
8380 #ifdef SDB_DEBUGGING_INFO
8381 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8382 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8383 #endif
8385 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8386 floating-point arguments. */
8387 if (TARGET_MIPS16
8388 && TARGET_HARD_FLOAT_ABI
8389 && crtl->args.info.fp_code != 0)
8390 mips16_build_function_stub ();
8392 /* Select the MIPS16 mode for this function. */
8393 if (TARGET_MIPS16)
8394 fprintf (file, "\t.set\tmips16\n");
8395 else
8396 fprintf (file, "\t.set\tnomips16\n");
8398 if (!FUNCTION_NAME_ALREADY_DECLARED)
8400 /* Get the function name the same way that toplev.c does before calling
8401 assemble_start_function. This is needed so that the name used here
8402 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8403 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8405 if (!flag_inhibit_size_directive)
8407 fputs ("\t.ent\t", file);
8408 assemble_name (file, fnname);
8409 fputs ("\n", file);
8412 assemble_name (file, fnname);
8413 fputs (":\n", file);
8416 /* Stop mips_file_end from treating this function as external. */
8417 if (TARGET_IRIX && mips_abi == ABI_32)
8418 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8420 /* Output MIPS-specific frame information. */
8421 if (!flag_inhibit_size_directive)
8423 const struct mips_frame_info *frame;
8425 frame = &cfun->machine->frame;
8427 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8428 fprintf (file,
8429 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8430 "# vars= " HOST_WIDE_INT_PRINT_DEC
8431 ", regs= %d/%d"
8432 ", args= " HOST_WIDE_INT_PRINT_DEC
8433 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8434 reg_names[frame_pointer_needed
8435 ? HARD_FRAME_POINTER_REGNUM
8436 : STACK_POINTER_REGNUM],
8437 (frame_pointer_needed
8438 ? frame->total_size - frame->hard_frame_pointer_offset
8439 : frame->total_size),
8440 reg_names[GP_REG_FIRST + 31],
8441 frame->var_size,
8442 frame->num_gp, frame->num_fp,
8443 frame->args_size,
8444 frame->cprestore_size);
8446 /* .mask MASK, OFFSET. */
8447 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8448 frame->mask, frame->gp_save_offset);
8450 /* .fmask MASK, OFFSET. */
8451 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8452 frame->fmask, frame->fp_save_offset);
8455 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8456 Also emit the ".set noreorder; .set nomacro" sequence for functions
8457 that need it. */
8458 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8460 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8461 if (!cfun->machine->all_noreorder_p)
8462 output_asm_insn ("%(.cpload\t%^%)", 0);
8463 else
8464 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8466 else if (cfun->machine->all_noreorder_p)
8467 output_asm_insn ("%(%<", 0);
8469 /* Tell the assembler which register we're using as the global
8470 pointer. This is needed for thunks, since they can use either
8471 explicit relocs or assembler macros. */
8472 mips_output_cplocal ();
8475 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8477 static void
8478 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8479 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8481 /* Reinstate the normal $gp. */
8482 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8483 mips_output_cplocal ();
8485 if (cfun->machine->all_noreorder_p)
8487 /* Avoid using %>%) since it adds excess whitespace. */
8488 output_asm_insn (".set\tmacro", 0);
8489 output_asm_insn (".set\treorder", 0);
8490 set_noreorder = set_nomacro = 0;
8493 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
8495 const char *fnname;
8497 /* Get the function name the same way that toplev.c does before calling
8498 assemble_start_function. This is needed so that the name used here
8499 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8500 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8501 fputs ("\t.end\t", file);
8502 assemble_name (file, fnname);
8503 fputs ("\n", file);
8507 /* Save register REG to MEM. Make the instruction frame-related. */
8509 static void
8510 mips_save_reg (rtx reg, rtx mem)
8512 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8514 rtx x1, x2;
8516 if (mips_split_64bit_move_p (mem, reg))
8517 mips_split_doubleword_move (mem, reg);
8518 else
8519 mips_emit_move (mem, reg);
8521 x1 = mips_frame_set (mips_subword (mem, false),
8522 mips_subword (reg, false));
8523 x2 = mips_frame_set (mips_subword (mem, true),
8524 mips_subword (reg, true));
8525 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8527 else
8529 if (TARGET_MIPS16
8530 && REGNO (reg) != GP_REG_FIRST + 31
8531 && !M16_REG_P (REGNO (reg)))
8533 /* Save a non-MIPS16 register by moving it through a temporary.
8534 We don't need to do this for $31 since there's a special
8535 instruction for it. */
8536 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8537 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8539 else
8540 mips_emit_move (mem, reg);
8542 mips_set_frame_expr (mips_frame_set (mem, reg));
8546 /* The __gnu_local_gp symbol. */
8548 static GTY(()) rtx mips_gnu_local_gp;
8550 /* If we're generating n32 or n64 abicalls, emit instructions
8551 to set up the global pointer. */
8553 static void
8554 mips_emit_loadgp (void)
8556 rtx addr, offset, incoming_address, base, index, pic_reg;
8558 pic_reg = pic_offset_table_rtx;
8559 switch (mips_current_loadgp_style ())
8561 case LOADGP_ABSOLUTE:
8562 if (mips_gnu_local_gp == NULL)
8564 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8565 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8567 emit_insn (Pmode == SImode
8568 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
8569 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
8570 break;
8572 case LOADGP_NEWABI:
8573 addr = XEXP (DECL_RTL (current_function_decl), 0);
8574 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8575 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8576 emit_insn (Pmode == SImode
8577 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
8578 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
8579 break;
8581 case LOADGP_RTP:
8582 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8583 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8584 emit_insn (Pmode == SImode
8585 ? gen_loadgp_rtp_si (pic_reg, base, index)
8586 : gen_loadgp_rtp_di (pic_reg, base, index));
8587 break;
8589 default:
8590 return;
8592 /* Emit a blockage if there are implicit uses of the GP register.
8593 This includes profiled functions, because FUNCTION_PROFILE uses
8594 a jal macro. */
8595 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
8596 emit_insn (gen_loadgp_blockage ());
8599 /* Expand the "prologue" pattern. */
8601 void
8602 mips_expand_prologue (void)
8604 const struct mips_frame_info *frame;
8605 HOST_WIDE_INT size;
8606 unsigned int nargs;
8607 rtx insn;
8609 if (cfun->machine->global_pointer > 0)
8610 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8612 frame = &cfun->machine->frame;
8613 size = frame->total_size;
8615 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8616 bytes beforehand; this is enough to cover the register save area
8617 without going out of range. */
8618 if ((frame->mask | frame->fmask) != 0)
8620 HOST_WIDE_INT step1;
8622 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8623 if (GENERATE_MIPS16E_SAVE_RESTORE)
8625 HOST_WIDE_INT offset;
8626 unsigned int mask, regno;
8628 /* Try to merge argument stores into the save instruction. */
8629 nargs = mips16e_collect_argument_saves ();
8631 /* Build the save instruction. */
8632 mask = frame->mask;
8633 insn = mips16e_build_save_restore (false, &mask, &offset,
8634 nargs, step1);
8635 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8636 size -= step1;
8638 /* Check if we need to save other registers. */
8639 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8640 if (BITSET_P (mask, regno - GP_REG_FIRST))
8642 offset -= UNITS_PER_WORD;
8643 mips_save_restore_reg (word_mode, regno,
8644 offset, mips_save_reg);
8647 else
8649 insn = gen_add3_insn (stack_pointer_rtx,
8650 stack_pointer_rtx,
8651 GEN_INT (-step1));
8652 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8653 size -= step1;
8654 mips_for_each_saved_reg (size, mips_save_reg);
8658 /* Allocate the rest of the frame. */
8659 if (size > 0)
8661 if (SMALL_OPERAND (-size))
8662 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8663 stack_pointer_rtx,
8664 GEN_INT (-size)))) = 1;
8665 else
8667 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8668 if (TARGET_MIPS16)
8670 /* There are no instructions to add or subtract registers
8671 from the stack pointer, so use the frame pointer as a
8672 temporary. We should always be using a frame pointer
8673 in this case anyway. */
8674 gcc_assert (frame_pointer_needed);
8675 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8676 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8677 hard_frame_pointer_rtx,
8678 MIPS_PROLOGUE_TEMP (Pmode)));
8679 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8681 else
8682 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8683 stack_pointer_rtx,
8684 MIPS_PROLOGUE_TEMP (Pmode)));
8686 /* Describe the combined effect of the previous instructions. */
8687 mips_set_frame_expr
8688 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8689 plus_constant (stack_pointer_rtx, -size)));
8693 /* Set up the frame pointer, if we're using one. */
8694 if (frame_pointer_needed)
8696 HOST_WIDE_INT offset;
8698 offset = frame->hard_frame_pointer_offset;
8699 if (offset == 0)
8701 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8702 RTX_FRAME_RELATED_P (insn) = 1;
8704 else if (SMALL_OPERAND (offset))
8706 insn = gen_add3_insn (hard_frame_pointer_rtx,
8707 stack_pointer_rtx, GEN_INT (offset));
8708 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8710 else
8712 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8713 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8714 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8715 hard_frame_pointer_rtx,
8716 MIPS_PROLOGUE_TEMP (Pmode)));
8717 mips_set_frame_expr
8718 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8719 plus_constant (stack_pointer_rtx, offset)));
8723 mips_emit_loadgp ();
8725 /* Initialize the $gp save slot. */
8726 if (frame->cprestore_size > 0)
8727 emit_insn (gen_cprestore (GEN_INT (crtl->outgoing_args_size)));
8729 /* If we are profiling, make sure no instructions are scheduled before
8730 the call to mcount. */
8731 if (crtl->profile)
8732 emit_insn (gen_blockage ());
8735 /* Emit instructions to restore register REG from slot MEM. */
8737 static void
8738 mips_restore_reg (rtx reg, rtx mem)
8740 /* There's no MIPS16 instruction to load $31 directly. Load into
8741 $7 instead and adjust the return insn appropriately. */
8742 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8743 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
8745 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8747 /* Can't restore directly; move through a temporary. */
8748 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8749 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8751 else
8752 mips_emit_move (reg, mem);
8755 /* Emit any instructions needed before a return. */
8757 void
8758 mips_expand_before_return (void)
8760 /* When using a call-clobbered gp, we start out with unified call
8761 insns that include instructions to restore the gp. We then split
8762 these unified calls after reload. These split calls explicitly
8763 clobber gp, so there is no need to define
8764 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
8766 For consistency, we should also insert an explicit clobber of $28
8767 before return insns, so that the post-reload optimizers know that
8768 the register is not live on exit. */
8769 if (TARGET_CALL_CLOBBERED_GP)
8770 emit_clobber (pic_offset_table_rtx);
8773 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8774 says which. */
8776 void
8777 mips_expand_epilogue (bool sibcall_p)
8779 const struct mips_frame_info *frame;
8780 HOST_WIDE_INT step1, step2;
8781 rtx base, target;
8783 if (!sibcall_p && mips_can_use_return_insn ())
8785 emit_jump_insn (gen_return ());
8786 return;
8789 /* In MIPS16 mode, if the return value should go into a floating-point
8790 register, we need to call a helper routine to copy it over. */
8791 if (mips16_cfun_returns_in_fpr_p ())
8792 mips16_copy_fpr_return_value ();
8794 /* Split the frame into two. STEP1 is the amount of stack we should
8795 deallocate before restoring the registers. STEP2 is the amount we
8796 should deallocate afterwards.
8798 Start off by assuming that no registers need to be restored. */
8799 frame = &cfun->machine->frame;
8800 step1 = frame->total_size;
8801 step2 = 0;
8803 /* Work out which register holds the frame address. */
8804 if (!frame_pointer_needed)
8805 base = stack_pointer_rtx;
8806 else
8808 base = hard_frame_pointer_rtx;
8809 step1 -= frame->hard_frame_pointer_offset;
8812 /* If we need to restore registers, deallocate as much stack as
8813 possible in the second step without going out of range. */
8814 if ((frame->mask | frame->fmask) != 0)
8816 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8817 step1 -= step2;
8820 /* Set TARGET to BASE + STEP1. */
8821 target = base;
8822 if (step1 > 0)
8824 rtx adjust;
8826 /* Get an rtx for STEP1 that we can add to BASE. */
8827 adjust = GEN_INT (step1);
8828 if (!SMALL_OPERAND (step1))
8830 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8831 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8834 /* Normal mode code can copy the result straight into $sp. */
8835 if (!TARGET_MIPS16)
8836 target = stack_pointer_rtx;
8838 emit_insn (gen_add3_insn (target, base, adjust));
8841 /* Copy TARGET into the stack pointer. */
8842 if (target != stack_pointer_rtx)
8843 mips_emit_move (stack_pointer_rtx, target);
8845 /* If we're using addressing macros, $gp is implicitly used by all
8846 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8847 from the stack. */
8848 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8849 emit_insn (gen_blockage ());
8851 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
8853 unsigned int regno, mask;
8854 HOST_WIDE_INT offset;
8855 rtx restore;
8857 /* Generate the restore instruction. */
8858 mask = frame->mask;
8859 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8861 /* Restore any other registers manually. */
8862 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8863 if (BITSET_P (mask, regno - GP_REG_FIRST))
8865 offset -= UNITS_PER_WORD;
8866 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8869 /* Restore the remaining registers and deallocate the final bit
8870 of the frame. */
8871 emit_insn (restore);
8873 else
8875 /* Restore the registers. */
8876 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
8878 /* Deallocate the final bit of the frame. */
8879 if (step2 > 0)
8880 emit_insn (gen_add3_insn (stack_pointer_rtx,
8881 stack_pointer_rtx,
8882 GEN_INT (step2)));
8885 /* Add in the __builtin_eh_return stack adjustment. We need to
8886 use a temporary in MIPS16 code. */
8887 if (crtl->calls_eh_return)
8889 if (TARGET_MIPS16)
8891 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8892 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8893 MIPS_EPILOGUE_TEMP (Pmode),
8894 EH_RETURN_STACKADJ_RTX));
8895 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8897 else
8898 emit_insn (gen_add3_insn (stack_pointer_rtx,
8899 stack_pointer_rtx,
8900 EH_RETURN_STACKADJ_RTX));
8903 if (!sibcall_p)
8905 unsigned int regno;
8907 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8908 path will restore the return address into $7 rather than $31. */
8909 if (TARGET_MIPS16
8910 && !GENERATE_MIPS16E_SAVE_RESTORE
8911 && BITSET_P (frame->mask, 31))
8912 regno = GP_REG_FIRST + 7;
8913 else
8914 regno = GP_REG_FIRST + 31;
8915 mips_expand_before_return ();
8916 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
8920 /* Return nonzero if this function is known to have a null epilogue.
8921 This allows the optimizer to omit jumps to jumps if no stack
8922 was created. */
8924 bool
8925 mips_can_use_return_insn (void)
8927 if (!reload_completed)
8928 return false;
8930 if (crtl->profile)
8931 return false;
8933 /* In MIPS16 mode, a function that returns a floating-point value
8934 needs to arrange to copy the return value into the floating-point
8935 registers. */
8936 if (mips16_cfun_returns_in_fpr_p ())
8937 return false;
8939 return cfun->machine->frame.total_size == 0;
8942 /* Return true if register REGNO can store a value of mode MODE.
8943 The result of this function is cached in mips_hard_regno_mode_ok. */
8945 static bool
8946 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8948 unsigned int size;
8949 enum mode_class class;
8951 if (mode == CCV2mode)
8952 return (ISA_HAS_8CC
8953 && ST_REG_P (regno)
8954 && (regno - ST_REG_FIRST) % 2 == 0);
8956 if (mode == CCV4mode)
8957 return (ISA_HAS_8CC
8958 && ST_REG_P (regno)
8959 && (regno - ST_REG_FIRST) % 4 == 0);
8961 if (mode == CCmode)
8963 if (!ISA_HAS_8CC)
8964 return regno == FPSW_REGNUM;
8966 return (ST_REG_P (regno)
8967 || GP_REG_P (regno)
8968 || FP_REG_P (regno));
8971 size = GET_MODE_SIZE (mode);
8972 class = GET_MODE_CLASS (mode);
8974 if (GP_REG_P (regno))
8975 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8977 if (FP_REG_P (regno)
8978 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8979 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8981 /* Allow TFmode for CCmode reloads. */
8982 if (mode == TFmode && ISA_HAS_8CC)
8983 return true;
8985 /* Allow 64-bit vector modes for Loongson-2E/2F. */
8986 if (TARGET_LOONGSON_VECTORS
8987 && (mode == V2SImode
8988 || mode == V4HImode
8989 || mode == V8QImode
8990 || mode == DImode))
8991 return true;
8993 if (class == MODE_FLOAT
8994 || class == MODE_COMPLEX_FLOAT
8995 || class == MODE_VECTOR_FLOAT)
8996 return size <= UNITS_PER_FPVALUE;
8998 /* Allow integer modes that fit into a single register. We need
8999 to put integers into FPRs when using instructions like CVT
9000 and TRUNC. There's no point allowing sizes smaller than a word,
9001 because the FPU has no appropriate load/store instructions. */
9002 if (class == MODE_INT)
9003 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
9006 if (ACC_REG_P (regno)
9007 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
9009 if (MD_REG_P (regno))
9011 /* After a multiplication or division, clobbering HI makes
9012 the value of LO unpredictable, and vice versa. This means
9013 that, for all interesting cases, HI and LO are effectively
9014 a single register.
9016 We model this by requiring that any value that uses HI
9017 also uses LO. */
9018 if (size <= UNITS_PER_WORD * 2)
9019 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
9021 else
9023 /* DSP accumulators do not have the same restrictions as
9024 HI and LO, so we can treat them as normal doubleword
9025 registers. */
9026 if (size <= UNITS_PER_WORD)
9027 return true;
9029 if (size <= UNITS_PER_WORD * 2
9030 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
9031 return true;
9035 if (ALL_COP_REG_P (regno))
9036 return class == MODE_INT && size <= UNITS_PER_WORD;
9038 if (regno == GOT_VERSION_REGNUM)
9039 return mode == SImode;
9041 return false;
9044 /* Implement HARD_REGNO_NREGS. */
9046 unsigned int
9047 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9049 if (ST_REG_P (regno))
9050 /* The size of FP status registers is always 4, because they only hold
9051 CCmode values, and CCmode is always considered to be 4 bytes wide. */
9052 return (GET_MODE_SIZE (mode) + 3) / 4;
9054 if (FP_REG_P (regno))
9055 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
9057 /* All other registers are word-sized. */
9058 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
9061 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
9062 in mips_hard_regno_nregs. */
9065 mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
9067 int size;
9068 HARD_REG_SET left;
9070 size = 0x8000;
9071 COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
9072 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
9074 size = MIN (size, 4);
9075 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
9077 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
9079 size = MIN (size, UNITS_PER_FPREG);
9080 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
9082 if (!hard_reg_set_empty_p (left))
9083 size = MIN (size, UNITS_PER_WORD);
9084 return (GET_MODE_SIZE (mode) + size - 1) / size;
9087 /* Implement CANNOT_CHANGE_MODE_CLASS. */
9089 bool
9090 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
9091 enum machine_mode to ATTRIBUTE_UNUSED,
9092 enum reg_class class)
9094 /* There are several problems with changing the modes of values
9095 in floating-point registers:
9097 - When a multi-word value is stored in paired floating-point
9098 registers, the first register always holds the low word.
9099 We therefore can't allow FPRs to change between single-word
9100 and multi-word modes on big-endian targets.
9102 - GCC assumes that each word of a multiword register can be accessed
9103 individually using SUBREGs. This is not true for floating-point
9104 registers if they are bigger than a word.
9106 - Loading a 32-bit value into a 64-bit floating-point register
9107 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9108 We can't allow FPRs to change from SImode to to a wider mode on
9109 64-bit targets.
9111 - If the FPU has already interpreted a value in one format, we must
9112 not ask it to treat the value as having a different format.
9114 We therefore disallow all mode changes involving FPRs. */
9115 return reg_classes_intersect_p (FP_REGS, class);
9118 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
9120 static bool
9121 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
9123 switch (mode)
9125 case SFmode:
9126 return TARGET_HARD_FLOAT;
9128 case DFmode:
9129 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
9131 case V2SFmode:
9132 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
9134 default:
9135 return false;
9139 /* Implement MODES_TIEABLE_P. */
9141 bool
9142 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9144 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9145 prefer to put one of them in FPRs. */
9146 return (mode1 == mode2
9147 || (!mips_mode_ok_for_mov_fmt_p (mode1)
9148 && !mips_mode_ok_for_mov_fmt_p (mode2)));
9151 /* Implement PREFERRED_RELOAD_CLASS. */
9153 enum reg_class
9154 mips_preferred_reload_class (rtx x, enum reg_class class)
9156 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
9157 return LEA_REGS;
9159 if (reg_class_subset_p (FP_REGS, class)
9160 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
9161 return FP_REGS;
9163 if (reg_class_subset_p (GR_REGS, class))
9164 class = GR_REGS;
9166 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
9167 class = M16_REGS;
9169 return class;
9172 /* Implement REGISTER_MOVE_COST. */
9175 mips_register_move_cost (enum machine_mode mode,
9176 enum reg_class to, enum reg_class from)
9178 if (TARGET_MIPS16)
9180 /* ??? We cannot move general registers into HI and LO because
9181 MIPS16 has no MTHI and MTLO instructions. Make the cost of
9182 moves in the opposite direction just as high, which stops the
9183 register allocators from using HI and LO for pseudos. */
9184 if (reg_class_subset_p (from, GENERAL_REGS)
9185 && reg_class_subset_p (to, GENERAL_REGS))
9187 if (reg_class_subset_p (from, M16_REGS)
9188 || reg_class_subset_p (to, M16_REGS))
9189 return 2;
9190 /* Two MOVEs. */
9191 return 4;
9194 else if (reg_class_subset_p (from, GENERAL_REGS))
9196 if (reg_class_subset_p (to, GENERAL_REGS))
9197 return 2;
9198 if (reg_class_subset_p (to, FP_REGS))
9199 return 4;
9200 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
9201 return 5;
9202 if (reg_class_subset_p (to, ACC_REGS))
9203 return 6;
9205 else if (reg_class_subset_p (to, GENERAL_REGS))
9207 if (reg_class_subset_p (from, FP_REGS))
9208 return 4;
9209 if (reg_class_subset_p (from, ST_REGS))
9210 /* LUI followed by MOVF. */
9211 return 4;
9212 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
9213 return 5;
9214 if (reg_class_subset_p (from, ACC_REGS))
9215 return 6;
9217 else if (reg_class_subset_p (from, FP_REGS))
9219 if (reg_class_subset_p (to, FP_REGS)
9220 && mips_mode_ok_for_mov_fmt_p (mode))
9221 return 4;
9222 if (reg_class_subset_p (to, ST_REGS))
9223 /* An expensive sequence. */
9224 return 8;
9227 return 12;
9230 /* Return the register class required for a secondary register when
9231 copying between one of the registers in CLASS and value X, which
9232 has mode MODE. X is the source of the move if IN_P, otherwise it
9233 is the destination. Return NO_REGS if no secondary register is
9234 needed. */
9236 enum reg_class
9237 mips_secondary_reload_class (enum reg_class class,
9238 enum machine_mode mode, rtx x, bool in_p)
9240 int regno;
9242 /* If X is a constant that cannot be loaded into $25, it must be loaded
9243 into some other GPR. No other register class allows a direct move. */
9244 if (mips_dangerous_for_la25_p (x))
9245 return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
9247 regno = true_regnum (x);
9248 if (TARGET_MIPS16)
9250 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9251 if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
9252 return M16_REGS;
9254 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9255 if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
9256 return M16_REGS;
9258 return NO_REGS;
9261 /* Copying from accumulator registers to anywhere other than a general
9262 register requires a temporary general register. */
9263 if (reg_class_subset_p (class, ACC_REGS))
9264 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9265 if (ACC_REG_P (regno))
9266 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9268 /* We can only copy a value to a condition code register from a
9269 floating-point register, and even then we require a scratch
9270 floating-point register. We can only copy a value out of a
9271 condition-code register into a general register. */
9272 if (reg_class_subset_p (class, ST_REGS))
9274 if (in_p)
9275 return FP_REGS;
9276 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9278 if (ST_REG_P (regno))
9280 if (!in_p)
9281 return FP_REGS;
9282 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9285 if (reg_class_subset_p (class, FP_REGS))
9287 if (MEM_P (x)
9288 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9289 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9290 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9291 return NO_REGS;
9293 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9294 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9295 return NO_REGS;
9297 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9298 /* We can force the constant to memory and use lwc1
9299 and ldc1. As above, we will use pairs of lwc1s if
9300 ldc1 is not supported. */
9301 return NO_REGS;
9303 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9304 /* In this case we can use mov.fmt. */
9305 return NO_REGS;
9307 /* Otherwise, we need to reload through an integer register. */
9308 return GR_REGS;
9310 if (FP_REG_P (regno))
9311 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9313 return NO_REGS;
9316 /* Implement TARGET_MODE_REP_EXTENDED. */
9318 static int
9319 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9321 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9322 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9323 return SIGN_EXTEND;
9325 return UNKNOWN;
9328 /* Implement TARGET_VALID_POINTER_MODE. */
9330 static bool
9331 mips_valid_pointer_mode (enum machine_mode mode)
9333 return mode == SImode || (TARGET_64BIT && mode == DImode);
9336 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9338 static bool
9339 mips_vector_mode_supported_p (enum machine_mode mode)
9341 switch (mode)
9343 case V2SFmode:
9344 return TARGET_PAIRED_SINGLE_FLOAT;
9346 case V2HImode:
9347 case V4QImode:
9348 case V2HQmode:
9349 case V2UHQmode:
9350 case V2HAmode:
9351 case V2UHAmode:
9352 case V4QQmode:
9353 case V4UQQmode:
9354 return TARGET_DSP;
9356 case V2SImode:
9357 case V4HImode:
9358 case V8QImode:
9359 return TARGET_LOONGSON_VECTORS;
9361 default:
9362 return false;
9366 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9368 static bool
9369 mips_scalar_mode_supported_p (enum machine_mode mode)
9371 if (ALL_FIXED_POINT_MODE_P (mode)
9372 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9373 return true;
9375 return default_scalar_mode_supported_p (mode);
9378 /* Implement TARGET_INIT_LIBFUNCS. */
9380 #include "config/gofast.h"
9382 static void
9383 mips_init_libfuncs (void)
9385 if (TARGET_FIX_VR4120)
9387 /* Register the special divsi3 and modsi3 functions needed to work
9388 around VR4120 division errata. */
9389 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9390 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9393 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9395 /* Register the MIPS16 -mhard-float stubs. */
9396 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9397 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9398 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9399 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9401 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9402 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9403 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9404 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9405 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9406 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9407 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9409 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9410 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9411 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9413 if (TARGET_DOUBLE_FLOAT)
9415 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9416 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9417 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9418 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9420 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9421 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9422 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9423 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9424 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9425 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9426 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9428 set_conv_libfunc (sext_optab, DFmode, SFmode,
9429 "__mips16_extendsfdf2");
9430 set_conv_libfunc (trunc_optab, SFmode, DFmode,
9431 "__mips16_truncdfsf2");
9432 set_conv_libfunc (sfix_optab, SImode, DFmode,
9433 "__mips16_fix_truncdfsi");
9434 set_conv_libfunc (sfloat_optab, DFmode, SImode,
9435 "__mips16_floatsidf");
9436 set_conv_libfunc (ufloat_optab, DFmode, SImode,
9437 "__mips16_floatunsidf");
9440 else
9441 /* Register the gofast functions if selected using --enable-gofast. */
9442 gofast_maybe_init_libfuncs ();
9444 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
9445 on an external non-MIPS16 routine to implement __sync_synchronize. */
9446 if (TARGET_MIPS16)
9447 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
9450 /* Return the length of INSN. LENGTH is the initial length computed by
9451 attributes in the machine-description file. */
9454 mips_adjust_insn_length (rtx insn, int length)
9456 /* A unconditional jump has an unfilled delay slot if it is not part
9457 of a sequence. A conditional jump normally has a delay slot, but
9458 does not on MIPS16. */
9459 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9460 length += 4;
9462 /* See how many nops might be needed to avoid hardware hazards. */
9463 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9464 switch (get_attr_hazard (insn))
9466 case HAZARD_NONE:
9467 break;
9469 case HAZARD_DELAY:
9470 length += 4;
9471 break;
9473 case HAZARD_HILO:
9474 length += 8;
9475 break;
9478 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9479 the .md file length attributes are 4-based for both modes.
9480 Adjust the MIPS16 ones here. */
9481 if (TARGET_MIPS16)
9482 length /= 2;
9484 return length;
9487 /* Return an asm sequence to start a noat block and load the address
9488 of a label into $1. */
9490 const char *
9491 mips_output_load_label (void)
9493 if (TARGET_EXPLICIT_RELOCS)
9494 switch (mips_abi)
9496 case ABI_N32:
9497 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9499 case ABI_64:
9500 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9502 default:
9503 if (ISA_HAS_LOAD_DELAY)
9504 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9505 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9507 else
9509 if (Pmode == DImode)
9510 return "%[dla\t%@,%0";
9511 else
9512 return "%[la\t%@,%0";
9516 /* Return the assembly code for INSN, which has the operands given by
9517 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9518 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9519 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9520 version of BRANCH_IF_TRUE. */
9522 const char *
9523 mips_output_conditional_branch (rtx insn, rtx *operands,
9524 const char *branch_if_true,
9525 const char *branch_if_false)
9527 unsigned int length;
9528 rtx taken, not_taken;
9530 length = get_attr_length (insn);
9531 if (length <= 8)
9533 /* Just a simple conditional branch. */
9534 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9535 return branch_if_true;
9538 /* Generate a reversed branch around a direct jump. This fallback does
9539 not use branch-likely instructions. */
9540 mips_branch_likely = false;
9541 not_taken = gen_label_rtx ();
9542 taken = operands[1];
9544 /* Generate the reversed branch to NOT_TAKEN. */
9545 operands[1] = not_taken;
9546 output_asm_insn (branch_if_false, operands);
9548 /* If INSN has a delay slot, we must provide delay slots for both the
9549 branch to NOT_TAKEN and the conditional jump. We must also ensure
9550 that INSN's delay slot is executed in the appropriate cases. */
9551 if (final_sequence)
9553 /* This first delay slot will always be executed, so use INSN's
9554 delay slot if is not annulled. */
9555 if (!INSN_ANNULLED_BRANCH_P (insn))
9557 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9558 asm_out_file, optimize, 1, NULL);
9559 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9561 else
9562 output_asm_insn ("nop", 0);
9563 fprintf (asm_out_file, "\n");
9566 /* Output the unconditional branch to TAKEN. */
9567 if (length <= 16)
9568 output_asm_insn ("j\t%0%/", &taken);
9569 else
9571 output_asm_insn (mips_output_load_label (), &taken);
9572 output_asm_insn ("jr\t%@%]%/", 0);
9575 /* Now deal with its delay slot; see above. */
9576 if (final_sequence)
9578 /* This delay slot will only be executed if the branch is taken.
9579 Use INSN's delay slot if is annulled. */
9580 if (INSN_ANNULLED_BRANCH_P (insn))
9582 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9583 asm_out_file, optimize, 1, NULL);
9584 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9586 else
9587 output_asm_insn ("nop", 0);
9588 fprintf (asm_out_file, "\n");
9591 /* Output NOT_TAKEN. */
9592 targetm.asm_out.internal_label (asm_out_file, "L",
9593 CODE_LABEL_NUMBER (not_taken));
9594 return "";
9597 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9598 if some ordering condition is true. The condition is given by
9599 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9600 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9601 its second is always zero. */
9603 const char *
9604 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9606 const char *branch[2];
9608 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9609 Make BRANCH[0] branch on the inverse condition. */
9610 switch (GET_CODE (operands[0]))
9612 /* These cases are equivalent to comparisons against zero. */
9613 case LEU:
9614 inverted_p = !inverted_p;
9615 /* Fall through. */
9616 case GTU:
9617 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9618 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9619 break;
9621 /* These cases are always true or always false. */
9622 case LTU:
9623 inverted_p = !inverted_p;
9624 /* Fall through. */
9625 case GEU:
9626 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9627 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9628 break;
9630 default:
9631 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9632 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9633 break;
9635 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9638 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9639 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9641 When working around R4000 and R4400 errata, we need to make sure that
9642 the division is not immediately followed by a shift[1][2]. We also
9643 need to stop the division from being put into a branch delay slot[3].
9644 The easiest way to avoid both problems is to add a nop after the
9645 division. When a divide-by-zero check is needed, this nop can be
9646 used to fill the branch delay slot.
9648 [1] If a double-word or a variable shift executes immediately
9649 after starting an integer division, the shift may give an
9650 incorrect result. See quotations of errata #16 and #28 from
9651 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9652 in mips.md for details.
9654 [2] A similar bug to [1] exists for all revisions of the
9655 R4000 and the R4400 when run in an MC configuration.
9656 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9658 "19. In this following sequence:
9660 ddiv (or ddivu or div or divu)
9661 dsll32 (or dsrl32, dsra32)
9663 if an MPT stall occurs, while the divide is slipping the cpu
9664 pipeline, then the following double shift would end up with an
9665 incorrect result.
9667 Workaround: The compiler needs to avoid generating any
9668 sequence with divide followed by extended double shift."
9670 This erratum is also present in "MIPS R4400MC Errata, Processor
9671 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9672 & 3.0" as errata #10 and #4, respectively.
9674 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9675 (also valid for MIPS R4000MC processors):
9677 "52. R4000SC: This bug does not apply for the R4000PC.
9679 There are two flavors of this bug:
9681 1) If the instruction just after divide takes an RF exception
9682 (tlb-refill, tlb-invalid) and gets an instruction cache
9683 miss (both primary and secondary) and the line which is
9684 currently in secondary cache at this index had the first
9685 data word, where the bits 5..2 are set, then R4000 would
9686 get a wrong result for the div.
9690 div r8, r9
9691 ------------------- # end-of page. -tlb-refill
9695 div r8, r9
9696 ------------------- # end-of page. -tlb-invalid
9699 2) If the divide is in the taken branch delay slot, where the
9700 target takes RF exception and gets an I-cache miss for the
9701 exception vector or where I-cache miss occurs for the
9702 target address, under the above mentioned scenarios, the
9703 div would get wrong results.
9706 j r2 # to next page mapped or unmapped
9707 div r8,r9 # this bug would be there as long
9708 # as there is an ICache miss and
9709 nop # the "data pattern" is present
9712 beq r0, r0, NextPage # to Next page
9713 div r8,r9
9716 This bug is present for div, divu, ddiv, and ddivu
9717 instructions.
9719 Workaround: For item 1), OS could make sure that the next page
9720 after the divide instruction is also mapped. For item 2), the
9721 compiler could make sure that the divide instruction is not in
9722 the branch delay slot."
9724 These processors have PRId values of 0x00004220 and 0x00004300 for
9725 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9727 const char *
9728 mips_output_division (const char *division, rtx *operands)
9730 const char *s;
9732 s = division;
9733 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9735 output_asm_insn (s, operands);
9736 s = "nop";
9738 if (TARGET_CHECK_ZERO_DIV)
9740 if (TARGET_MIPS16)
9742 output_asm_insn (s, operands);
9743 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9745 else if (GENERATE_DIVIDE_TRAPS)
9747 output_asm_insn (s, operands);
9748 s = "teq\t%2,%.,7";
9750 else
9752 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9753 output_asm_insn (s, operands);
9754 s = "break\t7%)\n1:";
9757 return s;
9760 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9761 instruction and if OUT_INSN assigns to the accumulator operand. */
9763 bool
9764 mips_linked_madd_p (rtx out_insn, rtx in_insn)
9766 rtx x;
9768 x = single_set (in_insn);
9769 if (x == 0)
9770 return false;
9772 x = SET_SRC (x);
9774 if (GET_CODE (x) == PLUS
9775 && GET_CODE (XEXP (x, 0)) == MULT
9776 && reg_set_p (XEXP (x, 1), out_insn))
9777 return true;
9779 if (GET_CODE (x) == MINUS
9780 && GET_CODE (XEXP (x, 1)) == MULT
9781 && reg_set_p (XEXP (x, 0), out_insn))
9782 return true;
9784 return false;
9787 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9788 data rather than the address. We need this because the cprestore
9789 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9790 which causes the default routine to abort. We just return false
9791 for that case. */
9793 bool
9794 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9796 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9797 return false;
9799 return !store_data_bypass_p (out_insn, in_insn);
9803 /* Variables and flags used in scheduler hooks when tuning for
9804 Loongson 2E/2F. */
9805 static struct
9807 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
9808 strategy. */
9810 /* If true, then next ALU1/2 instruction will go to ALU1. */
9811 bool alu1_turn_p;
9813 /* If true, then next FALU1/2 unstruction will go to FALU1. */
9814 bool falu1_turn_p;
9816 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
9817 int alu1_core_unit_code;
9818 int alu2_core_unit_code;
9819 int falu1_core_unit_code;
9820 int falu2_core_unit_code;
9822 /* True if current cycle has a multi instruction.
9823 This flag is used in mips_ls2_dfa_post_advance_cycle. */
9824 bool cycle_has_multi_p;
9826 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
9827 These are used in mips_ls2_dfa_post_advance_cycle to initialize
9828 DFA state.
9829 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
9830 instruction to go ALU1. */
9831 rtx alu1_turn_enabled_insn;
9832 rtx alu2_turn_enabled_insn;
9833 rtx falu1_turn_enabled_insn;
9834 rtx falu2_turn_enabled_insn;
9835 } mips_ls2;
9837 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9838 dependencies have no cost, except on the 20Kc where output-dependence
9839 is treated like input-dependence. */
9841 static int
9842 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9843 rtx dep ATTRIBUTE_UNUSED, int cost)
9845 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9846 && TUNE_20KC)
9847 return cost;
9848 if (REG_NOTE_KIND (link) != 0)
9849 return 0;
9850 return cost;
9853 /* Return the number of instructions that can be issued per cycle. */
9855 static int
9856 mips_issue_rate (void)
9858 switch (mips_tune)
9860 case PROCESSOR_74KC:
9861 case PROCESSOR_74KF2_1:
9862 case PROCESSOR_74KF1_1:
9863 case PROCESSOR_74KF3_2:
9864 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9865 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9866 but in reality only a maximum of 3 insns can be issued as
9867 floating-point loads and stores also require a slot in the
9868 AGEN pipe. */
9869 return 4;
9871 case PROCESSOR_20KC:
9872 case PROCESSOR_R4130:
9873 case PROCESSOR_R5400:
9874 case PROCESSOR_R5500:
9875 case PROCESSOR_R7000:
9876 case PROCESSOR_R9000:
9877 return 2;
9879 case PROCESSOR_SB1:
9880 case PROCESSOR_SB1A:
9881 /* This is actually 4, but we get better performance if we claim 3.
9882 This is partly because of unwanted speculative code motion with the
9883 larger number, and partly because in most common cases we can't
9884 reach the theoretical max of 4. */
9885 return 3;
9887 case PROCESSOR_LOONGSON_2E:
9888 case PROCESSOR_LOONGSON_2F:
9889 return 4;
9891 default:
9892 return 1;
9896 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
9898 static void
9899 mips_ls2_init_dfa_post_cycle_insn (void)
9901 start_sequence ();
9902 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
9903 mips_ls2.alu1_turn_enabled_insn = get_insns ();
9904 end_sequence ();
9906 start_sequence ();
9907 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
9908 mips_ls2.alu2_turn_enabled_insn = get_insns ();
9909 end_sequence ();
9911 start_sequence ();
9912 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
9913 mips_ls2.falu1_turn_enabled_insn = get_insns ();
9914 end_sequence ();
9916 start_sequence ();
9917 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
9918 mips_ls2.falu2_turn_enabled_insn = get_insns ();
9919 end_sequence ();
9921 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
9922 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
9923 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
9924 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
9927 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
9928 Init data used in mips_dfa_post_advance_cycle. */
9930 static void
9931 mips_init_dfa_post_cycle_insn (void)
9933 if (TUNE_LOONGSON_2EF)
9934 mips_ls2_init_dfa_post_cycle_insn ();
9937 /* Initialize STATE when scheduling for Loongson 2E/2F.
9938 Support round-robin dispatch scheme by enabling only one of
9939 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
9940 respectively. */
9942 static void
9943 mips_ls2_dfa_post_advance_cycle (state_t state)
9945 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
9947 /* Though there are no non-pipelined ALU1 insns,
9948 we can get an instruction of type 'multi' before reload. */
9949 gcc_assert (mips_ls2.cycle_has_multi_p);
9950 mips_ls2.alu1_turn_p = false;
9953 mips_ls2.cycle_has_multi_p = false;
9955 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
9956 /* We have a non-pipelined alu instruction in the core,
9957 adjust round-robin counter. */
9958 mips_ls2.alu1_turn_p = true;
9960 if (mips_ls2.alu1_turn_p)
9962 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
9963 gcc_unreachable ();
9965 else
9967 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
9968 gcc_unreachable ();
9971 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
9973 /* There are no non-pipelined FALU1 insns. */
9974 gcc_unreachable ();
9975 mips_ls2.falu1_turn_p = false;
9978 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
9979 /* We have a non-pipelined falu instruction in the core,
9980 adjust round-robin counter. */
9981 mips_ls2.falu1_turn_p = true;
9983 if (mips_ls2.falu1_turn_p)
9985 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
9986 gcc_unreachable ();
9988 else
9990 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
9991 gcc_unreachable ();
9995 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
9996 This hook is being called at the start of each cycle. */
9998 static void
9999 mips_dfa_post_advance_cycle (void)
10001 if (TUNE_LOONGSON_2EF)
10002 mips_ls2_dfa_post_advance_cycle (curr_state);
10005 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10006 be as wide as the scheduling freedom in the DFA. */
10008 static int
10009 mips_multipass_dfa_lookahead (void)
10011 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10012 if (TUNE_SB1)
10013 return 4;
10015 if (TUNE_LOONGSON_2EF)
10016 return 4;
10018 return 0;
10021 /* Remove the instruction at index LOWER from ready queue READY and
10022 reinsert it in front of the instruction at index HIGHER. LOWER must
10023 be <= HIGHER. */
10025 static void
10026 mips_promote_ready (rtx *ready, int lower, int higher)
10028 rtx new_head;
10029 int i;
10031 new_head = ready[lower];
10032 for (i = lower; i < higher; i++)
10033 ready[i] = ready[i + 1];
10034 ready[i] = new_head;
10037 /* If the priority of the instruction at POS2 in the ready queue READY
10038 is within LIMIT units of that of the instruction at POS1, swap the
10039 instructions if POS2 is not already less than POS1. */
10041 static void
10042 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
10044 if (pos1 < pos2
10045 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
10047 rtx temp;
10049 temp = ready[pos1];
10050 ready[pos1] = ready[pos2];
10051 ready[pos2] = temp;
10055 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10056 that may clobber hi or lo. */
10057 static rtx mips_macc_chains_last_hilo;
10059 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10060 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10062 static void
10063 mips_macc_chains_record (rtx insn)
10065 if (get_attr_may_clobber_hilo (insn))
10066 mips_macc_chains_last_hilo = insn;
10069 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10070 has NREADY elements, looking for a multiply-add or multiply-subtract
10071 instruction that is cumulative with mips_macc_chains_last_hilo.
10072 If there is one, promote it ahead of anything else that might
10073 clobber hi or lo. */
10075 static void
10076 mips_macc_chains_reorder (rtx *ready, int nready)
10078 int i, j;
10080 if (mips_macc_chains_last_hilo != 0)
10081 for (i = nready - 1; i >= 0; i--)
10082 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10084 for (j = nready - 1; j > i; j--)
10085 if (recog_memoized (ready[j]) >= 0
10086 && get_attr_may_clobber_hilo (ready[j]))
10088 mips_promote_ready (ready, i, j);
10089 break;
10091 break;
10095 /* The last instruction to be scheduled. */
10096 static rtx vr4130_last_insn;
10098 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10099 points to an rtx that is initially an instruction. Nullify the rtx
10100 if the instruction uses the value of register X. */
10102 static void
10103 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
10104 void *data)
10106 rtx *insn_ptr;
10108 insn_ptr = (rtx *) data;
10109 if (REG_P (x)
10110 && *insn_ptr != 0
10111 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10112 *insn_ptr = 0;
10115 /* Return true if there is true register dependence between vr4130_last_insn
10116 and INSN. */
10118 static bool
10119 vr4130_true_reg_dependence_p (rtx insn)
10121 note_stores (PATTERN (vr4130_last_insn),
10122 vr4130_true_reg_dependence_p_1, &insn);
10123 return insn == 0;
10126 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10127 the ready queue and that INSN2 is the instruction after it, return
10128 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10129 in which INSN1 and INSN2 can probably issue in parallel, but for
10130 which (INSN2, INSN1) should be less sensitive to instruction
10131 alignment than (INSN1, INSN2). See 4130.md for more details. */
10133 static bool
10134 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10136 sd_iterator_def sd_it;
10137 dep_t dep;
10139 /* Check for the following case:
10141 1) there is some other instruction X with an anti dependence on INSN1;
10142 2) X has a higher priority than INSN2; and
10143 3) X is an arithmetic instruction (and thus has no unit restrictions).
10145 If INSN1 is the last instruction blocking X, it would better to
10146 choose (INSN1, X) over (INSN2, INSN1). */
10147 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
10148 if (DEP_TYPE (dep) == REG_DEP_ANTI
10149 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
10150 && recog_memoized (DEP_CON (dep)) >= 0
10151 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
10152 return false;
10154 if (vr4130_last_insn != 0
10155 && recog_memoized (insn1) >= 0
10156 && recog_memoized (insn2) >= 0)
10158 /* See whether INSN1 and INSN2 use different execution units,
10159 or if they are both ALU-type instructions. If so, they can
10160 probably execute in parallel. */
10161 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10162 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10163 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10165 /* If only one of the instructions has a dependence on
10166 vr4130_last_insn, prefer to schedule the other one first. */
10167 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
10168 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
10169 if (dep1_p != dep2_p)
10170 return dep1_p;
10172 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10173 is not an ALU-type instruction and if INSN1 uses the same
10174 execution unit. (Note that if this condition holds, we already
10175 know that INSN2 uses a different execution unit.) */
10176 if (class1 != VR4130_CLASS_ALU
10177 && recog_memoized (vr4130_last_insn) >= 0
10178 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10179 return true;
10182 return false;
10185 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10186 queue with at least two instructions. Swap the first two if
10187 vr4130_swap_insns_p says that it could be worthwhile. */
10189 static void
10190 vr4130_reorder (rtx *ready, int nready)
10192 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10193 mips_promote_ready (ready, nready - 2, nready - 1);
10196 /* Record whether last 74k AGEN instruction was a load or store. */
10197 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
10199 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
10200 resets to TYPE_UNKNOWN state. */
10202 static void
10203 mips_74k_agen_init (rtx insn)
10205 if (!insn || !NONJUMP_INSN_P (insn))
10206 mips_last_74k_agen_insn = TYPE_UNKNOWN;
10207 else
10209 enum attr_type type = get_attr_type (insn);
10210 if (type == TYPE_LOAD || type == TYPE_STORE)
10211 mips_last_74k_agen_insn = type;
10215 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
10216 loads to be grouped together, and multiple stores to be grouped
10217 together. Swap things around in the ready queue to make this happen. */
10219 static void
10220 mips_74k_agen_reorder (rtx *ready, int nready)
10222 int i;
10223 int store_pos, load_pos;
10225 store_pos = -1;
10226 load_pos = -1;
10228 for (i = nready - 1; i >= 0; i--)
10230 rtx insn = ready[i];
10231 if (USEFUL_INSN_P (insn))
10232 switch (get_attr_type (insn))
10234 case TYPE_STORE:
10235 if (store_pos == -1)
10236 store_pos = i;
10237 break;
10239 case TYPE_LOAD:
10240 if (load_pos == -1)
10241 load_pos = i;
10242 break;
10244 default:
10245 break;
10249 if (load_pos == -1 || store_pos == -1)
10250 return;
10252 switch (mips_last_74k_agen_insn)
10254 case TYPE_UNKNOWN:
10255 /* Prefer to schedule loads since they have a higher latency. */
10256 case TYPE_LOAD:
10257 /* Swap loads to the front of the queue. */
10258 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
10259 break;
10260 case TYPE_STORE:
10261 /* Swap stores to the front of the queue. */
10262 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
10263 break;
10264 default:
10265 break;
10269 /* Implement TARGET_SCHED_INIT. */
10271 static void
10272 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10273 int max_ready ATTRIBUTE_UNUSED)
10275 mips_macc_chains_last_hilo = 0;
10276 vr4130_last_insn = 0;
10277 mips_74k_agen_init (NULL_RTX);
10279 /* When scheduling for Loongson2, branch instructions go to ALU1,
10280 therefore basic block is most likely to start with round-robin counter
10281 pointed to ALU2. */
10282 mips_ls2.alu1_turn_p = false;
10283 mips_ls2.falu1_turn_p = true;
10286 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
10288 static int
10289 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10290 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
10292 if (!reload_completed
10293 && TUNE_MACC_CHAINS
10294 && *nreadyp > 0)
10295 mips_macc_chains_reorder (ready, *nreadyp);
10297 if (reload_completed
10298 && TUNE_MIPS4130
10299 && !TARGET_VR4130_ALIGN
10300 && *nreadyp > 1)
10301 vr4130_reorder (ready, *nreadyp);
10303 if (TUNE_74K)
10304 mips_74k_agen_reorder (ready, *nreadyp);
10306 return mips_issue_rate ();
10309 /* Update round-robin counters for ALU1/2 and FALU1/2. */
10311 static void
10312 mips_ls2_variable_issue (rtx insn)
10314 if (mips_ls2.alu1_turn_p)
10316 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
10317 mips_ls2.alu1_turn_p = false;
10319 else
10321 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
10322 mips_ls2.alu1_turn_p = true;
10325 if (mips_ls2.falu1_turn_p)
10327 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
10328 mips_ls2.falu1_turn_p = false;
10330 else
10332 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
10333 mips_ls2.falu1_turn_p = true;
10336 if (recog_memoized (insn) >= 0)
10337 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
10340 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10342 static int
10343 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10344 rtx insn, int more)
10346 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
10347 if (USEFUL_INSN_P (insn))
10349 more--;
10350 if (!reload_completed && TUNE_MACC_CHAINS)
10351 mips_macc_chains_record (insn);
10352 vr4130_last_insn = insn;
10353 if (TUNE_74K)
10354 mips_74k_agen_init (insn);
10355 else if (TUNE_LOONGSON_2EF)
10356 mips_ls2_variable_issue (insn);
10359 /* Instructions of type 'multi' should all be split before
10360 the second scheduling pass. */
10361 gcc_assert (!reload_completed
10362 || recog_memoized (insn) < 0
10363 || get_attr_type (insn) != TYPE_MULTI);
10365 return more;
10368 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10369 return the first operand of the associated PREF or PREFX insn. */
10372 mips_prefetch_cookie (rtx write, rtx locality)
10374 /* store_streamed / load_streamed. */
10375 if (INTVAL (locality) <= 0)
10376 return GEN_INT (INTVAL (write) + 4);
10378 /* store / load. */
10379 if (INTVAL (locality) <= 2)
10380 return write;
10382 /* store_retained / load_retained. */
10383 return GEN_INT (INTVAL (write) + 6);
10386 /* Flags that indicate when a built-in function is available.
10388 BUILTIN_AVAIL_NON_MIPS16
10389 The function is available on the current target, but only
10390 in non-MIPS16 mode. */
10391 #define BUILTIN_AVAIL_NON_MIPS16 1
10393 /* Declare an availability predicate for built-in functions that
10394 require non-MIPS16 mode and also require COND to be true.
10395 NAME is the main part of the predicate's name. */
10396 #define AVAIL_NON_MIPS16(NAME, COND) \
10397 static unsigned int \
10398 mips_builtin_avail_##NAME (void) \
10400 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
10403 /* This structure describes a single built-in function. */
10404 struct mips_builtin_description {
10405 /* The code of the main .md file instruction. See mips_builtin_type
10406 for more information. */
10407 enum insn_code icode;
10409 /* The floating-point comparison code to use with ICODE, if any. */
10410 enum mips_fp_condition cond;
10412 /* The name of the built-in function. */
10413 const char *name;
10415 /* Specifies how the function should be expanded. */
10416 enum mips_builtin_type builtin_type;
10418 /* The function's prototype. */
10419 enum mips_function_type function_type;
10421 /* Whether the function is available. */
10422 unsigned int (*avail) (void);
10425 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
10426 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
10427 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
10428 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
10429 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
10430 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
10431 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
10432 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
10434 /* Construct a mips_builtin_description from the given arguments.
10436 INSN is the name of the associated instruction pattern, without the
10437 leading CODE_FOR_mips_.
10439 CODE is the floating-point condition code associated with the
10440 function. It can be 'f' if the field is not applicable.
10442 NAME is the name of the function itself, without the leading
10443 "__builtin_mips_".
10445 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
10447 AVAIL is the name of the availability predicate, without the leading
10448 mips_builtin_avail_. */
10449 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
10450 FUNCTION_TYPE, AVAIL) \
10451 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
10452 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
10453 mips_builtin_avail_ ## AVAIL }
10455 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
10456 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
10457 are as for MIPS_BUILTIN. */
10458 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
10459 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
10461 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
10462 are subject to mips_builtin_avail_<AVAIL>. */
10463 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
10464 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
10465 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
10466 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
10467 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
10469 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10470 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
10471 while the any and all forms are subject to mips_builtin_avail_mips3d. */
10472 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
10473 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
10474 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
10475 mips3d), \
10476 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
10477 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
10478 mips3d), \
10479 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
10480 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
10481 AVAIL), \
10482 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
10483 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
10484 AVAIL)
10486 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10487 are subject to mips_builtin_avail_mips3d. */
10488 #define CMP_4S_BUILTINS(INSN, COND) \
10489 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
10490 MIPS_BUILTIN_CMP_ANY, \
10491 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
10492 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
10493 MIPS_BUILTIN_CMP_ALL, \
10494 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
10496 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10497 instruction requires mips_builtin_avail_<AVAIL>. */
10498 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
10499 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
10500 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10501 AVAIL), \
10502 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
10503 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10504 AVAIL)
10506 /* Define all the built-in functions related to C.cond.fmt condition COND. */
10507 #define CMP_BUILTINS(COND) \
10508 MOVTF_BUILTINS (c, COND, paired_single), \
10509 MOVTF_BUILTINS (cabs, COND, mips3d), \
10510 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
10511 CMP_PS_BUILTINS (c, COND, paired_single), \
10512 CMP_PS_BUILTINS (cabs, COND, mips3d), \
10513 CMP_4S_BUILTINS (c, COND), \
10514 CMP_4S_BUILTINS (cabs, COND)
10516 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
10517 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
10518 and AVAIL are as for MIPS_BUILTIN. */
10519 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
10520 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
10521 FUNCTION_TYPE, AVAIL)
10523 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10524 branch instruction. AVAIL is as for MIPS_BUILTIN. */
10525 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
10526 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
10527 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
10529 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
10530 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
10531 builtin_description field. */
10532 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
10533 { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
10534 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
10536 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
10537 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
10538 builtin_description field. */
10539 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
10540 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
10542 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
10543 We use functions of this form when the same insn can be usefully applied
10544 to more than one datatype. */
10545 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
10546 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
10548 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10549 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10550 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10551 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10552 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10553 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10555 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
10556 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
10557 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
10558 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
10559 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
10560 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
10561 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
10562 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
10563 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
10564 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
10565 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
10566 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
10567 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
10568 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
10569 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
10570 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
10571 #define CODE_FOR_loongson_biadd CODE_FOR_reduc_uplus_v8qi
10572 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
10573 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
10574 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
10575 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
10576 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
10577 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
10578 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
10579 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
10580 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
10581 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
10582 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
10583 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
10584 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
10586 static const struct mips_builtin_description mips_builtins[] = {
10587 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10588 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10589 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10590 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
10591 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
10592 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
10593 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
10594 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
10596 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
10597 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10598 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10599 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10600 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
10602 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
10603 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
10604 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10605 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
10606 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
10607 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10609 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
10610 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
10611 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
10612 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
10613 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
10614 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
10616 MIPS_FP_CONDITIONS (CMP_BUILTINS),
10618 /* Built-in functions for the SB-1 processor. */
10619 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
10621 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
10622 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10623 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10624 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10625 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10626 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10627 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10628 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10629 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10630 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10631 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10632 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
10633 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
10634 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
10635 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
10636 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
10637 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
10638 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
10639 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
10640 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
10641 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
10642 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
10643 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
10644 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
10645 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
10646 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
10647 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
10648 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
10649 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
10650 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
10651 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
10652 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
10653 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10654 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10655 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
10656 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
10657 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10658 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
10659 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
10660 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
10661 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
10662 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10663 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
10664 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
10665 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
10666 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
10667 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
10668 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
10669 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10670 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10671 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
10672 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10673 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10674 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
10675 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10676 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10677 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
10678 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
10679 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10680 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
10681 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
10682 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
10683 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
10684 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
10685 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
10686 BPOSGE_BUILTIN (32, dsp),
10688 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
10689 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
10690 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10691 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10692 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10693 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10694 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10695 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10696 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10697 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10698 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
10699 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10700 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10701 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10702 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10703 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10704 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
10705 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
10706 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
10707 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
10708 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
10709 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
10710 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
10711 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10712 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10713 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10714 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
10715 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10716 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10717 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10718 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10719 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10720 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
10721 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10722 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
10724 /* Built-in functions for the DSP ASE (32-bit only). */
10725 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10726 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10727 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10728 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
10729 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10730 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10731 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10732 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
10733 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
10734 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10735 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10736 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10737 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
10738 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10739 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10740 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
10741 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
10742 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
10743 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
10744 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
10745 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
10747 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
10748 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10749 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10750 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
10751 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
10752 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
10753 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
10754 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10755 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
10756 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
10757 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10758 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10759 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10760 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10761 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10762 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
10764 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
10765 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
10766 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
10767 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
10768 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10769 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10770 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10771 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10772 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10773 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10774 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
10775 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
10776 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10777 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10778 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10779 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10780 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
10781 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10782 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10783 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10784 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
10785 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
10786 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10787 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10788 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10789 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10790 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10791 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10792 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10793 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10794 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10795 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10796 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10797 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10798 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10799 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10800 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10801 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10802 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
10803 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
10804 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10805 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10806 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10807 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10808 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10809 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10810 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10811 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10812 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
10813 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10814 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10815 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10816 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10817 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
10818 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
10819 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10820 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10821 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10822 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
10823 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10824 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
10825 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
10826 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
10827 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
10828 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10829 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10830 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10831 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10832 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10833 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10834 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10835 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10836 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
10837 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
10838 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
10839 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
10840 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10841 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10842 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10843 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10844 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10845 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10846 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
10847 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
10848 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
10849 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
10850 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10851 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10852 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10853 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10854 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10855 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10856 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10857 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
10858 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
10859 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
10860 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
10861 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
10862 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
10863 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI)
10866 /* MODE is a vector mode whose elements have type TYPE. Return the type
10867 of the vector itself. */
10869 static tree
10870 mips_builtin_vector_type (tree type, enum machine_mode mode)
10872 static tree types[2 * (int) MAX_MACHINE_MODE];
10873 int mode_index;
10875 mode_index = (int) mode;
10877 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
10878 mode_index += MAX_MACHINE_MODE;
10880 if (types[mode_index] == NULL_TREE)
10881 types[mode_index] = build_vector_type_for_mode (type, mode);
10882 return types[mode_index];
10885 /* Source-level argument types. */
10886 #define MIPS_ATYPE_VOID void_type_node
10887 #define MIPS_ATYPE_INT integer_type_node
10888 #define MIPS_ATYPE_POINTER ptr_type_node
10890 /* Standard mode-based argument types. */
10891 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
10892 #define MIPS_ATYPE_SI intSI_type_node
10893 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10894 #define MIPS_ATYPE_DI intDI_type_node
10895 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
10896 #define MIPS_ATYPE_SF float_type_node
10897 #define MIPS_ATYPE_DF double_type_node
10899 /* Vector argument types. */
10900 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10901 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10902 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
10903 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10904 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
10905 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
10906 #define MIPS_ATYPE_UV2SI \
10907 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
10908 #define MIPS_ATYPE_UV4HI \
10909 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
10910 #define MIPS_ATYPE_UV8QI \
10911 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
10913 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10914 their associated MIPS_ATYPEs. */
10915 #define MIPS_FTYPE_ATYPES1(A, B) \
10916 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10918 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10919 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10921 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10922 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10924 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10925 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10926 MIPS_ATYPE_##E
10928 /* Return the function type associated with function prototype TYPE. */
10930 static tree
10931 mips_build_function_type (enum mips_function_type type)
10933 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10935 if (types[(int) type] == NULL_TREE)
10936 switch (type)
10938 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10939 case MIPS_FTYPE_NAME##NUM ARGS: \
10940 types[(int) type] \
10941 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10942 NULL_TREE); \
10943 break;
10944 #include "config/mips/mips-ftypes.def"
10945 #undef DEF_MIPS_FTYPE
10946 default:
10947 gcc_unreachable ();
10950 return types[(int) type];
10953 /* Implement TARGET_INIT_BUILTINS. */
10955 static void
10956 mips_init_builtins (void)
10958 const struct mips_builtin_description *d;
10959 unsigned int i;
10961 /* Iterate through all of the bdesc arrays, initializing all of the
10962 builtin functions. */
10963 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
10965 d = &mips_builtins[i];
10966 if (d->avail ())
10967 add_builtin_function (d->name,
10968 mips_build_function_type (d->function_type),
10969 i, BUILT_IN_MD, NULL, NULL);
10973 /* Take argument ARGNO from EXP's argument list and convert it into a
10974 form suitable for input operand OPNO of instruction ICODE. Return the
10975 value. */
10977 static rtx
10978 mips_prepare_builtin_arg (enum insn_code icode,
10979 unsigned int opno, tree exp, unsigned int argno)
10981 rtx value;
10982 enum machine_mode mode;
10984 value = expand_normal (CALL_EXPR_ARG (exp, argno));
10985 mode = insn_data[icode].operand[opno].mode;
10986 if (!insn_data[icode].operand[opno].predicate (value, mode))
10988 value = copy_to_mode_reg (mode, value);
10989 /* Check the predicate again. */
10990 if (!insn_data[icode].operand[opno].predicate (value, mode))
10992 error ("invalid argument to built-in function");
10993 return const0_rtx;
10997 return value;
11000 /* Return an rtx suitable for output operand OP of instruction ICODE.
11001 If TARGET is non-null, try to use it where possible. */
11003 static rtx
11004 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11006 enum machine_mode mode;
11008 mode = insn_data[icode].operand[op].mode;
11009 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11010 target = gen_reg_rtx (mode);
11012 return target;
11015 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
11016 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
11017 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
11018 suggests a good place to put the result. */
11020 static rtx
11021 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11022 bool has_target_p)
11024 rtx ops[MAX_RECOG_OPERANDS];
11025 int opno, argno;
11027 /* Map any target to operand 0. */
11028 opno = 0;
11029 if (has_target_p)
11031 ops[opno] = mips_prepare_builtin_target (icode, opno, target);
11032 opno++;
11035 /* Map the arguments to the other operands. The n_operands value
11036 for an expander includes match_dups and match_scratches as well as
11037 match_operands, so n_operands is only an upper bound on the number
11038 of arguments to the expander function. */
11039 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
11040 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
11041 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
11043 switch (opno)
11045 case 2:
11046 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11047 break;
11049 case 3:
11050 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11051 break;
11053 case 4:
11054 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11055 break;
11057 default:
11058 gcc_unreachable ();
11060 return target;
11063 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
11064 function; TYPE says which. EXP is the CALL_EXPR that calls the
11065 function, ICODE is the instruction that should be used to compare
11066 the first two arguments, and COND is the condition it should test.
11067 TARGET, if nonnull, suggests a good place to put the result. */
11069 static rtx
11070 mips_expand_builtin_movtf (enum mips_builtin_type type,
11071 enum insn_code icode, enum mips_fp_condition cond,
11072 rtx target, tree exp)
11074 rtx cmp_result, op0, op1;
11076 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11077 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11078 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11079 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11081 icode = CODE_FOR_mips_cond_move_tf_ps;
11082 target = mips_prepare_builtin_target (icode, 0, target);
11083 if (type == MIPS_BUILTIN_MOVT)
11085 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11086 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11088 else
11090 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11091 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11093 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11094 return target;
11097 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11098 into TARGET otherwise. Return TARGET. */
11100 static rtx
11101 mips_builtin_branch_and_move (rtx condition, rtx target,
11102 rtx value_if_true, rtx value_if_false)
11104 rtx true_label, done_label;
11106 true_label = gen_label_rtx ();
11107 done_label = gen_label_rtx ();
11109 /* First assume that CONDITION is false. */
11110 mips_emit_move (target, value_if_false);
11112 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11113 emit_jump_insn (gen_condjump (condition, true_label));
11114 emit_jump_insn (gen_jump (done_label));
11115 emit_barrier ();
11117 /* Fix TARGET if CONDITION is true. */
11118 emit_label (true_label);
11119 mips_emit_move (target, value_if_true);
11121 emit_label (done_label);
11122 return target;
11125 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
11126 the CALL_EXPR that calls the function, ICODE is the code of the
11127 comparison instruction, and COND is the condition it should test.
11128 TARGET, if nonnull, suggests a good place to put the boolean result. */
11130 static rtx
11131 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11132 enum insn_code icode, enum mips_fp_condition cond,
11133 rtx target, tree exp)
11135 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
11136 int argno;
11138 if (target == 0 || GET_MODE (target) != SImode)
11139 target = gen_reg_rtx (SImode);
11141 /* The instruction should have a target operand, an operand for each
11142 argument, and an operand for COND. */
11143 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
11145 /* Prepare the operands to the comparison. */
11146 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11147 for (argno = 0; argno < call_expr_nargs (exp); argno++)
11148 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
11150 switch (insn_data[icode].n_operands)
11152 case 4:
11153 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11154 GEN_INT (cond)));
11155 break;
11157 case 6:
11158 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11159 args[2], args[3], GEN_INT (cond)));
11160 break;
11162 default:
11163 gcc_unreachable ();
11166 /* If the comparison sets more than one register, we define the result
11167 to be 0 if all registers are false and -1 if all registers are true.
11168 The value of the complete result is indeterminate otherwise. */
11169 switch (builtin_type)
11171 case MIPS_BUILTIN_CMP_ALL:
11172 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11173 return mips_builtin_branch_and_move (condition, target,
11174 const0_rtx, const1_rtx);
11176 case MIPS_BUILTIN_CMP_UPPER:
11177 case MIPS_BUILTIN_CMP_LOWER:
11178 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11179 condition = gen_single_cc (cmp_result, offset);
11180 return mips_builtin_branch_and_move (condition, target,
11181 const1_rtx, const0_rtx);
11183 default:
11184 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11185 return mips_builtin_branch_and_move (condition, target,
11186 const1_rtx, const0_rtx);
11190 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
11191 if nonnull, suggests a good place to put the boolean result. */
11193 static rtx
11194 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11196 rtx condition, cmp_result;
11197 int cmp_value;
11199 if (target == 0 || GET_MODE (target) != SImode)
11200 target = gen_reg_rtx (SImode);
11202 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11204 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11205 cmp_value = 32;
11206 else
11207 gcc_assert (0);
11209 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11210 return mips_builtin_branch_and_move (condition, target,
11211 const1_rtx, const0_rtx);
11214 /* Implement TARGET_EXPAND_BUILTIN. */
11216 static rtx
11217 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11218 enum machine_mode mode ATTRIBUTE_UNUSED,
11219 int ignore ATTRIBUTE_UNUSED)
11221 tree fndecl;
11222 unsigned int fcode, avail;
11223 const struct mips_builtin_description *d;
11225 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11226 fcode = DECL_FUNCTION_CODE (fndecl);
11227 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
11228 d = &mips_builtins[fcode];
11229 avail = d->avail ();
11230 gcc_assert (avail != 0);
11231 if (TARGET_MIPS16)
11233 error ("built-in function %qs not supported for MIPS16",
11234 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
11235 return const0_rtx;
11237 switch (d->builtin_type)
11239 case MIPS_BUILTIN_DIRECT:
11240 return mips_expand_builtin_direct (d->icode, target, exp, true);
11242 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11243 return mips_expand_builtin_direct (d->icode, target, exp, false);
11245 case MIPS_BUILTIN_MOVT:
11246 case MIPS_BUILTIN_MOVF:
11247 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
11248 d->cond, target, exp);
11250 case MIPS_BUILTIN_CMP_ANY:
11251 case MIPS_BUILTIN_CMP_ALL:
11252 case MIPS_BUILTIN_CMP_UPPER:
11253 case MIPS_BUILTIN_CMP_LOWER:
11254 case MIPS_BUILTIN_CMP_SINGLE:
11255 return mips_expand_builtin_compare (d->builtin_type, d->icode,
11256 d->cond, target, exp);
11258 case MIPS_BUILTIN_BPOSGE32:
11259 return mips_expand_builtin_bposge (d->builtin_type, target);
11261 gcc_unreachable ();
11264 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
11265 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
11266 struct mips16_constant {
11267 struct mips16_constant *next;
11268 rtx value;
11269 rtx label;
11270 enum machine_mode mode;
11273 /* Information about an incomplete MIPS16 constant pool. FIRST is the
11274 first constant, HIGHEST_ADDRESS is the highest address that the first
11275 byte of the pool can have, and INSN_ADDRESS is the current instruction
11276 address. */
11277 struct mips16_constant_pool {
11278 struct mips16_constant *first;
11279 int highest_address;
11280 int insn_address;
11283 /* Add constant VALUE to POOL and return its label. MODE is the
11284 value's mode (used for CONST_INTs, etc.). */
11286 static rtx
11287 mips16_add_constant (struct mips16_constant_pool *pool,
11288 rtx value, enum machine_mode mode)
11290 struct mips16_constant **p, *c;
11291 bool first_of_size_p;
11293 /* See whether the constant is already in the pool. If so, return the
11294 existing label, otherwise leave P pointing to the place where the
11295 constant should be added.
11297 Keep the pool sorted in increasing order of mode size so that we can
11298 reduce the number of alignments needed. */
11299 first_of_size_p = true;
11300 for (p = &pool->first; *p != 0; p = &(*p)->next)
11302 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
11303 return (*p)->label;
11304 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
11305 break;
11306 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
11307 first_of_size_p = false;
11310 /* In the worst case, the constant needed by the earliest instruction
11311 will end up at the end of the pool. The entire pool must then be
11312 accessible from that instruction.
11314 When adding the first constant, set the pool's highest address to
11315 the address of the first out-of-range byte. Adjust this address
11316 downwards each time a new constant is added. */
11317 if (pool->first == 0)
11318 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
11319 of the instruction with the lowest two bits clear. The base PC
11320 value for LDPC has the lowest three bits clear. Assume the worst
11321 case here; namely that the PC-relative instruction occupies the
11322 last 2 bytes in an aligned word. */
11323 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
11324 pool->highest_address -= GET_MODE_SIZE (mode);
11325 if (first_of_size_p)
11326 /* Take into account the worst possible padding due to alignment. */
11327 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
11329 /* Create a new entry. */
11330 c = XNEW (struct mips16_constant);
11331 c->value = value;
11332 c->mode = mode;
11333 c->label = gen_label_rtx ();
11334 c->next = *p;
11335 *p = c;
11337 return c->label;
11340 /* Output constant VALUE after instruction INSN and return the last
11341 instruction emitted. MODE is the mode of the constant. */
11343 static rtx
11344 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
11346 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
11348 rtx size = GEN_INT (GET_MODE_SIZE (mode));
11349 return emit_insn_after (gen_consttable_int (value, size), insn);
11352 if (SCALAR_FLOAT_MODE_P (mode))
11353 return emit_insn_after (gen_consttable_float (value), insn);
11355 if (VECTOR_MODE_P (mode))
11357 int i;
11359 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
11360 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
11361 CONST_VECTOR_ELT (value, i), insn);
11362 return insn;
11365 gcc_unreachable ();
11368 /* Dump out the constants in CONSTANTS after INSN. */
11370 static void
11371 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
11373 struct mips16_constant *c, *next;
11374 int align;
11376 align = 0;
11377 for (c = constants; c != NULL; c = next)
11379 /* If necessary, increase the alignment of PC. */
11380 if (align < GET_MODE_SIZE (c->mode))
11382 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
11383 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
11385 align = GET_MODE_SIZE (c->mode);
11387 insn = emit_label_after (c->label, insn);
11388 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
11390 next = c->next;
11391 free (c);
11394 emit_barrier_after (insn);
11397 /* Return the length of instruction INSN. */
11399 static int
11400 mips16_insn_length (rtx insn)
11402 if (JUMP_P (insn))
11404 rtx body = PATTERN (insn);
11405 if (GET_CODE (body) == ADDR_VEC)
11406 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
11407 if (GET_CODE (body) == ADDR_DIFF_VEC)
11408 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
11410 return get_attr_length (insn);
11413 /* If *X is a symbolic constant that refers to the constant pool, add
11414 the constant to POOL and rewrite *X to use the constant's label. */
11416 static void
11417 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
11419 rtx base, offset, label;
11421 split_const (*x, &base, &offset);
11422 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
11424 label = mips16_add_constant (pool, get_pool_constant (base),
11425 get_pool_mode (base));
11426 base = gen_rtx_LABEL_REF (Pmode, label);
11427 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
11431 /* This structure is used to communicate with mips16_rewrite_pool_refs.
11432 INSN is the instruction we're rewriting and POOL points to the current
11433 constant pool. */
11434 struct mips16_rewrite_pool_refs_info {
11435 rtx insn;
11436 struct mips16_constant_pool *pool;
11439 /* Rewrite *X so that constant pool references refer to the constant's
11440 label instead. DATA points to a mips16_rewrite_pool_refs_info
11441 structure. */
11443 static int
11444 mips16_rewrite_pool_refs (rtx *x, void *data)
11446 struct mips16_rewrite_pool_refs_info *info =
11447 (struct mips16_rewrite_pool_refs_info *) data;
11449 if (force_to_mem_operand (*x, Pmode))
11451 rtx mem = force_const_mem (GET_MODE (*x), *x);
11452 validate_change (info->insn, x, mem, false);
11455 if (MEM_P (*x))
11457 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
11458 return -1;
11461 if (TARGET_MIPS16_TEXT_LOADS)
11462 mips16_rewrite_pool_constant (info->pool, x);
11464 return GET_CODE (*x) == CONST ? -1 : 0;
11467 /* Build MIPS16 constant pools. */
11469 static void
11470 mips16_lay_out_constants (void)
11472 struct mips16_constant_pool pool;
11473 struct mips16_rewrite_pool_refs_info info;
11474 rtx insn, barrier;
11476 if (!TARGET_MIPS16_PCREL_LOADS)
11477 return;
11479 barrier = 0;
11480 memset (&pool, 0, sizeof (pool));
11481 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11483 /* Rewrite constant pool references in INSN. */
11484 if (INSN_P (insn))
11486 info.insn = insn;
11487 info.pool = &pool;
11488 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
11491 pool.insn_address += mips16_insn_length (insn);
11493 if (pool.first != NULL)
11495 /* If there are no natural barriers between the first user of
11496 the pool and the highest acceptable address, we'll need to
11497 create a new instruction to jump around the constant pool.
11498 In the worst case, this instruction will be 4 bytes long.
11500 If it's too late to do this transformation after INSN,
11501 do it immediately before INSN. */
11502 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
11504 rtx label, jump;
11506 label = gen_label_rtx ();
11508 jump = emit_jump_insn_before (gen_jump (label), insn);
11509 JUMP_LABEL (jump) = label;
11510 LABEL_NUSES (label) = 1;
11511 barrier = emit_barrier_after (jump);
11513 emit_label_after (label, barrier);
11514 pool.insn_address += 4;
11517 /* See whether the constant pool is now out of range of the first
11518 user. If so, output the constants after the previous barrier.
11519 Note that any instructions between BARRIER and INSN (inclusive)
11520 will use negative offsets to refer to the pool. */
11521 if (pool.insn_address > pool.highest_address)
11523 mips16_emit_constants (pool.first, barrier);
11524 pool.first = NULL;
11525 barrier = 0;
11527 else if (BARRIER_P (insn))
11528 barrier = insn;
11531 mips16_emit_constants (pool.first, get_last_insn ());
11534 /* A temporary variable used by for_each_rtx callbacks, etc. */
11535 static rtx mips_sim_insn;
11537 /* A structure representing the state of the processor pipeline.
11538 Used by the mips_sim_* family of functions. */
11539 struct mips_sim {
11540 /* The maximum number of instructions that can be issued in a cycle.
11541 (Caches mips_issue_rate.) */
11542 unsigned int issue_rate;
11544 /* The current simulation time. */
11545 unsigned int time;
11547 /* How many more instructions can be issued in the current cycle. */
11548 unsigned int insns_left;
11550 /* LAST_SET[X].INSN is the last instruction to set register X.
11551 LAST_SET[X].TIME is the time at which that instruction was issued.
11552 INSN is null if no instruction has yet set register X. */
11553 struct {
11554 rtx insn;
11555 unsigned int time;
11556 } last_set[FIRST_PSEUDO_REGISTER];
11558 /* The pipeline's current DFA state. */
11559 state_t dfa_state;
11562 /* Reset STATE to the initial simulation state. */
11564 static void
11565 mips_sim_reset (struct mips_sim *state)
11567 state->time = 0;
11568 state->insns_left = state->issue_rate;
11569 memset (&state->last_set, 0, sizeof (state->last_set));
11570 state_reset (state->dfa_state);
11573 /* Initialize STATE before its first use. DFA_STATE points to an
11574 allocated but uninitialized DFA state. */
11576 static void
11577 mips_sim_init (struct mips_sim *state, state_t dfa_state)
11579 state->issue_rate = mips_issue_rate ();
11580 state->dfa_state = dfa_state;
11581 mips_sim_reset (state);
11584 /* Advance STATE by one clock cycle. */
11586 static void
11587 mips_sim_next_cycle (struct mips_sim *state)
11589 state->time++;
11590 state->insns_left = state->issue_rate;
11591 state_transition (state->dfa_state, 0);
11594 /* Advance simulation state STATE until instruction INSN can read
11595 register REG. */
11597 static void
11598 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
11600 unsigned int regno, end_regno;
11602 end_regno = END_REGNO (reg);
11603 for (regno = REGNO (reg); regno < end_regno; regno++)
11604 if (state->last_set[regno].insn != 0)
11606 unsigned int t;
11608 t = (state->last_set[regno].time
11609 + insn_latency (state->last_set[regno].insn, insn));
11610 while (state->time < t)
11611 mips_sim_next_cycle (state);
11615 /* A for_each_rtx callback. If *X is a register, advance simulation state
11616 DATA until mips_sim_insn can read the register's value. */
11618 static int
11619 mips_sim_wait_regs_2 (rtx *x, void *data)
11621 if (REG_P (*x))
11622 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
11623 return 0;
11626 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11628 static void
11629 mips_sim_wait_regs_1 (rtx *x, void *data)
11631 for_each_rtx (x, mips_sim_wait_regs_2, data);
11634 /* Advance simulation state STATE until all of INSN's register
11635 dependencies are satisfied. */
11637 static void
11638 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
11640 mips_sim_insn = insn;
11641 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
11644 /* Advance simulation state STATE until the units required by
11645 instruction INSN are available. */
11647 static void
11648 mips_sim_wait_units (struct mips_sim *state, rtx insn)
11650 state_t tmp_state;
11652 tmp_state = alloca (state_size ());
11653 while (state->insns_left == 0
11654 || (memcpy (tmp_state, state->dfa_state, state_size ()),
11655 state_transition (tmp_state, insn) >= 0))
11656 mips_sim_next_cycle (state);
11659 /* Advance simulation state STATE until INSN is ready to issue. */
11661 static void
11662 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
11664 mips_sim_wait_regs (state, insn);
11665 mips_sim_wait_units (state, insn);
11668 /* mips_sim_insn has just set X. Update the LAST_SET array
11669 in simulation state DATA. */
11671 static void
11672 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
11674 struct mips_sim *state;
11676 state = (struct mips_sim *) data;
11677 if (REG_P (x))
11679 unsigned int regno, end_regno;
11681 end_regno = END_REGNO (x);
11682 for (regno = REGNO (x); regno < end_regno; regno++)
11684 state->last_set[regno].insn = mips_sim_insn;
11685 state->last_set[regno].time = state->time;
11690 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11691 can issue immediately (i.e., that mips_sim_wait_insn has already
11692 been called). */
11694 static void
11695 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
11697 state_transition (state->dfa_state, insn);
11698 state->insns_left--;
11700 mips_sim_insn = insn;
11701 note_stores (PATTERN (insn), mips_sim_record_set, state);
11704 /* Simulate issuing a NOP in state STATE. */
11706 static void
11707 mips_sim_issue_nop (struct mips_sim *state)
11709 if (state->insns_left == 0)
11710 mips_sim_next_cycle (state);
11711 state->insns_left--;
11714 /* Update simulation state STATE so that it's ready to accept the instruction
11715 after INSN. INSN should be part of the main rtl chain, not a member of a
11716 SEQUENCE. */
11718 static void
11719 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11721 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11722 if (JUMP_P (insn))
11723 mips_sim_issue_nop (state);
11725 switch (GET_CODE (SEQ_BEGIN (insn)))
11727 case CODE_LABEL:
11728 case CALL_INSN:
11729 /* We can't predict the processor state after a call or label. */
11730 mips_sim_reset (state);
11731 break;
11733 case JUMP_INSN:
11734 /* The delay slots of branch likely instructions are only executed
11735 when the branch is taken. Therefore, if the caller has simulated
11736 the delay slot instruction, STATE does not really reflect the state
11737 of the pipeline for the instruction after the delay slot. Also,
11738 branch likely instructions tend to incur a penalty when not taken,
11739 so there will probably be an extra delay between the branch and
11740 the instruction after the delay slot. */
11741 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11742 mips_sim_reset (state);
11743 break;
11745 default:
11746 break;
11750 /* The VR4130 pipeline issues aligned pairs of instructions together,
11751 but it stalls the second instruction if it depends on the first.
11752 In order to cut down the amount of logic required, this dependence
11753 check is not based on a full instruction decode. Instead, any non-SPECIAL
11754 instruction is assumed to modify the register specified by bits 20-16
11755 (which is usually the "rt" field).
11757 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11758 input, so we can end up with a false dependence between the branch
11759 and its delay slot. If this situation occurs in instruction INSN,
11760 try to avoid it by swapping rs and rt. */
11762 static void
11763 vr4130_avoid_branch_rt_conflict (rtx insn)
11765 rtx first, second;
11767 first = SEQ_BEGIN (insn);
11768 second = SEQ_END (insn);
11769 if (JUMP_P (first)
11770 && NONJUMP_INSN_P (second)
11771 && GET_CODE (PATTERN (first)) == SET
11772 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11773 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11775 /* Check for the right kind of condition. */
11776 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11777 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11778 && REG_P (XEXP (cond, 0))
11779 && REG_P (XEXP (cond, 1))
11780 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11781 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11783 /* SECOND mentions the rt register but not the rs register. */
11784 rtx tmp = XEXP (cond, 0);
11785 XEXP (cond, 0) = XEXP (cond, 1);
11786 XEXP (cond, 1) = tmp;
11791 /* Implement -mvr4130-align. Go through each basic block and simulate the
11792 processor pipeline. If we find that a pair of instructions could execute
11793 in parallel, and the first of those instructions is not 8-byte aligned,
11794 insert a nop to make it aligned. */
11796 static void
11797 vr4130_align_insns (void)
11799 struct mips_sim state;
11800 rtx insn, subinsn, last, last2, next;
11801 bool aligned_p;
11803 dfa_start ();
11805 /* LAST is the last instruction before INSN to have a nonzero length.
11806 LAST2 is the last such instruction before LAST. */
11807 last = 0;
11808 last2 = 0;
11810 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11811 aligned_p = true;
11813 mips_sim_init (&state, alloca (state_size ()));
11814 for (insn = get_insns (); insn != 0; insn = next)
11816 unsigned int length;
11818 next = NEXT_INSN (insn);
11820 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11821 This isn't really related to the alignment pass, but we do it on
11822 the fly to avoid a separate instruction walk. */
11823 vr4130_avoid_branch_rt_conflict (insn);
11825 if (USEFUL_INSN_P (insn))
11826 FOR_EACH_SUBINSN (subinsn, insn)
11828 mips_sim_wait_insn (&state, subinsn);
11830 /* If we want this instruction to issue in parallel with the
11831 previous one, make sure that the previous instruction is
11832 aligned. There are several reasons why this isn't worthwhile
11833 when the second instruction is a call:
11835 - Calls are less likely to be performance critical,
11836 - There's a good chance that the delay slot can execute
11837 in parallel with the call.
11838 - The return address would then be unaligned.
11840 In general, if we're going to insert a nop between instructions
11841 X and Y, it's better to insert it immediately after X. That
11842 way, if the nop makes Y aligned, it will also align any labels
11843 between X and Y. */
11844 if (state.insns_left != state.issue_rate
11845 && !CALL_P (subinsn))
11847 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11849 /* SUBINSN is the first instruction in INSN and INSN is
11850 aligned. We want to align the previous instruction
11851 instead, so insert a nop between LAST2 and LAST.
11853 Note that LAST could be either a single instruction
11854 or a branch with a delay slot. In the latter case,
11855 LAST, like INSN, is already aligned, but the delay
11856 slot must have some extra delay that stops it from
11857 issuing at the same time as the branch. We therefore
11858 insert a nop before the branch in order to align its
11859 delay slot. */
11860 emit_insn_after (gen_nop (), last2);
11861 aligned_p = false;
11863 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11865 /* SUBINSN is the delay slot of INSN, but INSN is
11866 currently unaligned. Insert a nop between
11867 LAST and INSN to align it. */
11868 emit_insn_after (gen_nop (), last);
11869 aligned_p = true;
11872 mips_sim_issue_insn (&state, subinsn);
11874 mips_sim_finish_insn (&state, insn);
11876 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11877 length = get_attr_length (insn);
11878 if (length > 0)
11880 /* If the instruction is an asm statement or multi-instruction
11881 mips.md patern, the length is only an estimate. Insert an
11882 8 byte alignment after it so that the following instructions
11883 can be handled correctly. */
11884 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11885 && (recog_memoized (insn) < 0 || length >= 8))
11887 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11888 next = NEXT_INSN (next);
11889 mips_sim_next_cycle (&state);
11890 aligned_p = true;
11892 else if (length & 4)
11893 aligned_p = !aligned_p;
11894 last2 = last;
11895 last = insn;
11898 /* See whether INSN is an aligned label. */
11899 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11900 aligned_p = true;
11902 dfa_finish ();
11905 /* This structure records that the current function has a LO_SUM
11906 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
11907 the largest offset applied to BASE by all such LO_SUMs. */
11908 struct mips_lo_sum_offset {
11909 rtx base;
11910 HOST_WIDE_INT offset;
11913 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
11915 static hashval_t
11916 mips_hash_base (rtx base)
11918 int do_not_record_p;
11920 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
11923 /* Hash-table callbacks for mips_lo_sum_offsets. */
11925 static hashval_t
11926 mips_lo_sum_offset_hash (const void *entry)
11928 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
11931 static int
11932 mips_lo_sum_offset_eq (const void *entry, const void *value)
11934 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
11935 (const_rtx) value);
11938 /* Look up symbolic constant X in HTAB, which is a hash table of
11939 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
11940 paired with a recorded LO_SUM, otherwise record X in the table. */
11942 static bool
11943 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
11945 rtx base, offset;
11946 void **slot;
11947 struct mips_lo_sum_offset *entry;
11949 /* Split X into a base and offset. */
11950 split_const (x, &base, &offset);
11951 if (UNSPEC_ADDRESS_P (base))
11952 base = UNSPEC_ADDRESS (base);
11954 /* Look up the base in the hash table. */
11955 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
11956 if (slot == NULL)
11957 return false;
11959 entry = (struct mips_lo_sum_offset *) *slot;
11960 if (option == INSERT)
11962 if (entry == NULL)
11964 entry = XNEW (struct mips_lo_sum_offset);
11965 entry->base = base;
11966 entry->offset = INTVAL (offset);
11967 *slot = entry;
11969 else
11971 if (INTVAL (offset) > entry->offset)
11972 entry->offset = INTVAL (offset);
11975 return INTVAL (offset) <= entry->offset;
11978 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
11979 Record every LO_SUM in *LOC. */
11981 static int
11982 mips_record_lo_sum (rtx *loc, void *data)
11984 if (GET_CODE (*loc) == LO_SUM)
11985 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
11986 return 0;
11989 /* Return true if INSN is a SET of an orphaned high-part relocation.
11990 HTAB is a hash table of mips_lo_sum_offsets that describes all the
11991 LO_SUMs in the current function. */
11993 static bool
11994 mips_orphaned_high_part_p (htab_t htab, rtx insn)
11996 enum mips_symbol_type type;
11997 rtx x, set;
11999 set = single_set (insn);
12000 if (set)
12002 /* Check for %his. */
12003 x = SET_SRC (set);
12004 if (GET_CODE (x) == HIGH
12005 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
12006 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
12008 /* Check for local %gots (and %got_pages, which is redundant but OK). */
12009 if (GET_CODE (x) == UNSPEC
12010 && XINT (x, 1) == UNSPEC_LOAD_GOT
12011 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
12012 SYMBOL_CONTEXT_LEA, &type)
12013 && type == SYMBOL_GOTOFF_PAGE)
12014 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
12016 return false;
12019 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
12020 INSN and a previous instruction, avoid it by inserting nops after
12021 instruction AFTER.
12023 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
12024 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
12025 before using the value of that register. *HILO_DELAY counts the
12026 number of instructions since the last hilo hazard (that is,
12027 the number of instructions since the last MFLO or MFHI).
12029 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
12030 for the next instruction.
12032 LO_REG is an rtx for the LO register, used in dependence checking. */
12034 static void
12035 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
12036 rtx *delayed_reg, rtx lo_reg)
12038 rtx pattern, set;
12039 int nops, ninsns;
12041 pattern = PATTERN (insn);
12043 /* Do not put the whole function in .set noreorder if it contains
12044 an asm statement. We don't know whether there will be hazards
12045 between the asm statement and the gcc-generated code. */
12046 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
12047 cfun->machine->all_noreorder_p = false;
12049 /* Ignore zero-length instructions (barriers and the like). */
12050 ninsns = get_attr_length (insn) / 4;
12051 if (ninsns == 0)
12052 return;
12054 /* Work out how many nops are needed. Note that we only care about
12055 registers that are explicitly mentioned in the instruction's pattern.
12056 It doesn't matter that calls use the argument registers or that they
12057 clobber hi and lo. */
12058 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
12059 nops = 2 - *hilo_delay;
12060 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
12061 nops = 1;
12062 else
12063 nops = 0;
12065 /* Insert the nops between this instruction and the previous one.
12066 Each new nop takes us further from the last hilo hazard. */
12067 *hilo_delay += nops;
12068 while (nops-- > 0)
12069 emit_insn_after (gen_hazard_nop (), after);
12071 /* Set up the state for the next instruction. */
12072 *hilo_delay += ninsns;
12073 *delayed_reg = 0;
12074 if (INSN_CODE (insn) >= 0)
12075 switch (get_attr_hazard (insn))
12077 case HAZARD_NONE:
12078 break;
12080 case HAZARD_HILO:
12081 *hilo_delay = 0;
12082 break;
12084 case HAZARD_DELAY:
12085 set = single_set (insn);
12086 gcc_assert (set);
12087 *delayed_reg = SET_DEST (set);
12088 break;
12092 /* Go through the instruction stream and insert nops where necessary.
12093 Also delete any high-part relocations whose partnering low parts
12094 are now all dead. See if the whole function can then be put into
12095 .set noreorder and .set nomacro. */
12097 static void
12098 mips_reorg_process_insns (void)
12100 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
12101 int hilo_delay;
12102 htab_t htab;
12104 /* Force all instructions to be split into their final form. */
12105 split_all_insns_noflow ();
12107 /* Recalculate instruction lengths without taking nops into account. */
12108 cfun->machine->ignore_hazard_length_p = true;
12109 shorten_branches (get_insns ());
12111 cfun->machine->all_noreorder_p = true;
12113 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
12114 if (!TARGET_EXPLICIT_RELOCS)
12115 cfun->machine->all_noreorder_p = false;
12117 /* Profiled functions can't be all noreorder because the profiler
12118 support uses assembler macros. */
12119 if (crtl->profile)
12120 cfun->machine->all_noreorder_p = false;
12122 /* Code compiled with -mfix-vr4120 can't be all noreorder because
12123 we rely on the assembler to work around some errata. */
12124 if (TARGET_FIX_VR4120)
12125 cfun->machine->all_noreorder_p = false;
12127 /* The same is true for -mfix-vr4130 if we might generate MFLO or
12128 MFHI instructions. Note that we avoid using MFLO and MFHI if
12129 the VR4130 MACC and DMACC instructions are available instead;
12130 see the *mfhilo_{si,di}_macc patterns. */
12131 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
12132 cfun->machine->all_noreorder_p = false;
12134 htab = htab_create (37, mips_lo_sum_offset_hash,
12135 mips_lo_sum_offset_eq, free);
12137 /* Make a first pass over the instructions, recording all the LO_SUMs. */
12138 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12139 FOR_EACH_SUBINSN (subinsn, insn)
12140 if (INSN_P (subinsn))
12141 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
12143 last_insn = 0;
12144 hilo_delay = 2;
12145 delayed_reg = 0;
12146 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
12148 /* Make a second pass over the instructions. Delete orphaned
12149 high-part relocations or turn them into NOPs. Avoid hazards
12150 by inserting NOPs. */
12151 for (insn = get_insns (); insn != 0; insn = next_insn)
12153 next_insn = NEXT_INSN (insn);
12154 if (INSN_P (insn))
12156 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
12158 /* If we find an orphaned high-part relocation in a delay
12159 slot, it's easier to turn that instruction into a NOP than
12160 to delete it. The delay slot will be a NOP either way. */
12161 FOR_EACH_SUBINSN (subinsn, insn)
12162 if (INSN_P (subinsn))
12164 if (mips_orphaned_high_part_p (htab, subinsn))
12166 PATTERN (subinsn) = gen_nop ();
12167 INSN_CODE (subinsn) = CODE_FOR_nop;
12169 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
12170 &delayed_reg, lo_reg);
12172 last_insn = insn;
12174 else
12176 /* INSN is a single instruction. Delete it if it's an
12177 orphaned high-part relocation. */
12178 if (mips_orphaned_high_part_p (htab, insn))
12179 delete_insn (insn);
12180 else
12182 mips_avoid_hazard (last_insn, insn, &hilo_delay,
12183 &delayed_reg, lo_reg);
12184 last_insn = insn;
12190 htab_delete (htab);
12193 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
12195 static void
12196 mips_reorg (void)
12198 mips16_lay_out_constants ();
12199 if (mips_base_delayed_branch)
12200 dbr_schedule (get_insns ());
12201 mips_reorg_process_insns ();
12202 if (TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
12203 vr4130_align_insns ();
12206 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
12207 in order to avoid duplicating too much logic from elsewhere. */
12209 static void
12210 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12211 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12212 tree function)
12214 rtx this, temp1, temp2, insn, fnaddr;
12215 bool use_sibcall_p;
12217 /* Pretend to be a post-reload pass while generating rtl. */
12218 reload_completed = 1;
12220 /* Mark the end of the (empty) prologue. */
12221 emit_note (NOTE_INSN_PROLOGUE_END);
12223 /* Determine if we can use a sibcall to call FUNCTION directly. */
12224 fnaddr = XEXP (DECL_RTL (function), 0);
12225 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
12226 && const_call_insn_operand (fnaddr, Pmode));
12228 /* Determine if we need to load FNADDR from the GOT. */
12229 if (!use_sibcall_p)
12230 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
12232 case SYMBOL_GOT_PAGE_OFST:
12233 case SYMBOL_GOT_DISP:
12234 /* Pick a global pointer. Use a call-clobbered register if
12235 TARGET_CALL_SAVED_GP. */
12236 cfun->machine->global_pointer =
12237 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
12238 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
12240 /* Set up the global pointer for n32 or n64 abicalls. */
12241 mips_emit_loadgp ();
12242 break;
12244 default:
12245 break;
12248 /* We need two temporary registers in some cases. */
12249 temp1 = gen_rtx_REG (Pmode, 2);
12250 temp2 = gen_rtx_REG (Pmode, 3);
12252 /* Find out which register contains the "this" pointer. */
12253 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12254 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
12255 else
12256 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
12258 /* Add DELTA to THIS. */
12259 if (delta != 0)
12261 rtx offset = GEN_INT (delta);
12262 if (!SMALL_OPERAND (delta))
12264 mips_emit_move (temp1, offset);
12265 offset = temp1;
12267 emit_insn (gen_add3_insn (this, this, offset));
12270 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
12271 if (vcall_offset != 0)
12273 rtx addr;
12275 /* Set TEMP1 to *THIS. */
12276 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
12278 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
12279 addr = mips_add_offset (temp2, temp1, vcall_offset);
12281 /* Load the offset and add it to THIS. */
12282 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
12283 emit_insn (gen_add3_insn (this, this, temp1));
12286 /* Jump to the target function. Use a sibcall if direct jumps are
12287 allowed, otherwise load the address into a register first. */
12288 if (use_sibcall_p)
12290 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
12291 SIBLING_CALL_P (insn) = 1;
12293 else
12295 /* This is messy. GAS treats "la $25,foo" as part of a call
12296 sequence and may allow a global "foo" to be lazily bound.
12297 The general move patterns therefore reject this combination.
12299 In this context, lazy binding would actually be OK
12300 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
12301 TARGET_CALL_SAVED_GP; see mips_load_call_address.
12302 We must therefore load the address via a temporary
12303 register if mips_dangerous_for_la25_p.
12305 If we jump to the temporary register rather than $25, the assembler
12306 can use the move insn to fill the jump's delay slot. */
12307 if (TARGET_USE_PIC_FN_ADDR_REG
12308 && !mips_dangerous_for_la25_p (fnaddr))
12309 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
12310 mips_load_call_address (temp1, fnaddr, true);
12312 if (TARGET_USE_PIC_FN_ADDR_REG
12313 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
12314 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
12315 emit_jump_insn (gen_indirect_jump (temp1));
12318 /* Run just enough of rest_of_compilation. This sequence was
12319 "borrowed" from alpha.c. */
12320 insn = get_insns ();
12321 insn_locators_alloc ();
12322 split_all_insns_noflow ();
12323 mips16_lay_out_constants ();
12324 shorten_branches (insn);
12325 final_start_function (insn, file, 1);
12326 final (insn, file, 1);
12327 final_end_function ();
12328 free_after_compilation (cfun);
12330 /* Clean up the vars set above. Note that final_end_function resets
12331 the global pointer for us. */
12332 reload_completed = 0;
12335 /* The last argument passed to mips_set_mips16_mode, or negative if the
12336 function hasn't been called yet. */
12337 static GTY(()) int was_mips16_p = -1;
12339 /* Set up the target-dependent global state so that it matches the
12340 current function's ISA mode. */
12342 static void
12343 mips_set_mips16_mode (int mips16_p)
12345 if (mips16_p == was_mips16_p)
12346 return;
12348 /* Restore base settings of various flags. */
12349 target_flags = mips_base_target_flags;
12350 flag_schedule_insns = mips_base_schedule_insns;
12351 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
12352 flag_move_loop_invariants = mips_base_move_loop_invariants;
12353 align_loops = mips_base_align_loops;
12354 align_jumps = mips_base_align_jumps;
12355 align_functions = mips_base_align_functions;
12357 if (mips16_p)
12359 /* Switch to MIPS16 mode. */
12360 target_flags |= MASK_MIPS16;
12362 /* Don't run the scheduler before reload, since it tends to
12363 increase register pressure. */
12364 flag_schedule_insns = 0;
12366 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
12367 the whole function to be in a single section. */
12368 flag_reorder_blocks_and_partition = 0;
12370 /* Don't move loop invariants, because it tends to increase
12371 register pressure. It also introduces an extra move in cases
12372 where the constant is the first operand in a two-operand binary
12373 instruction, or when it forms a register argument to a functon
12374 call. */
12375 flag_move_loop_invariants = 0;
12377 /* Silently disable -mexplicit-relocs since it doesn't apply
12378 to MIPS16 code. Even so, it would overly pedantic to warn
12379 about "-mips16 -mexplicit-relocs", especially given that
12380 we use a %gprel() operator. */
12381 target_flags &= ~MASK_EXPLICIT_RELOCS;
12383 /* Experiments suggest we get the best overall section-anchor
12384 results from using the range of an unextended LW or SW. Code
12385 that makes heavy use of byte or short accesses can do better
12386 with ranges of 0...31 and 0...63 respectively, but most code is
12387 sensitive to the range of LW and SW instead. */
12388 targetm.min_anchor_offset = 0;
12389 targetm.max_anchor_offset = 127;
12391 if (flag_pic || TARGET_ABICALLS)
12392 sorry ("MIPS16 PIC");
12394 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
12395 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
12397 else
12399 /* Switch to normal (non-MIPS16) mode. */
12400 target_flags &= ~MASK_MIPS16;
12402 /* Provide default values for align_* for 64-bit targets. */
12403 if (TARGET_64BIT)
12405 if (align_loops == 0)
12406 align_loops = 8;
12407 if (align_jumps == 0)
12408 align_jumps = 8;
12409 if (align_functions == 0)
12410 align_functions = 8;
12413 targetm.min_anchor_offset = -32768;
12414 targetm.max_anchor_offset = 32767;
12417 /* (Re)initialize MIPS target internals for new ISA. */
12418 mips_init_relocs ();
12420 if (was_mips16_p >= 0)
12421 /* Reinitialize target-dependent state. */
12422 target_reinit ();
12424 was_mips16_p = mips16_p;
12427 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
12428 function should use the MIPS16 ISA and switch modes accordingly. */
12430 static void
12431 mips_set_current_function (tree fndecl)
12433 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
12436 /* Allocate a chunk of memory for per-function machine-dependent data. */
12438 static struct machine_function *
12439 mips_init_machine_status (void)
12441 return ((struct machine_function *)
12442 ggc_alloc_cleared (sizeof (struct machine_function)));
12445 /* Return the processor associated with the given ISA level, or null
12446 if the ISA isn't valid. */
12448 static const struct mips_cpu_info *
12449 mips_cpu_info_from_isa (int isa)
12451 unsigned int i;
12453 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
12454 if (mips_cpu_info_table[i].isa == isa)
12455 return mips_cpu_info_table + i;
12457 return NULL;
12460 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
12461 with a final "000" replaced by "k". Ignore case.
12463 Note: this function is shared between GCC and GAS. */
12465 static bool
12466 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
12468 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
12469 given++, canonical++;
12471 return ((*given == 0 && *canonical == 0)
12472 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
12475 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
12476 CPU name. We've traditionally allowed a lot of variation here.
12478 Note: this function is shared between GCC and GAS. */
12480 static bool
12481 mips_matching_cpu_name_p (const char *canonical, const char *given)
12483 /* First see if the name matches exactly, or with a final "000"
12484 turned into "k". */
12485 if (mips_strict_matching_cpu_name_p (canonical, given))
12486 return true;
12488 /* If not, try comparing based on numerical designation alone.
12489 See if GIVEN is an unadorned number, or 'r' followed by a number. */
12490 if (TOLOWER (*given) == 'r')
12491 given++;
12492 if (!ISDIGIT (*given))
12493 return false;
12495 /* Skip over some well-known prefixes in the canonical name,
12496 hoping to find a number there too. */
12497 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
12498 canonical += 2;
12499 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
12500 canonical += 2;
12501 else if (TOLOWER (canonical[0]) == 'r')
12502 canonical += 1;
12504 return mips_strict_matching_cpu_name_p (canonical, given);
12507 /* Return the mips_cpu_info entry for the processor or ISA given
12508 by CPU_STRING. Return null if the string isn't recognized.
12510 A similar function exists in GAS. */
12512 static const struct mips_cpu_info *
12513 mips_parse_cpu (const char *cpu_string)
12515 unsigned int i;
12516 const char *s;
12518 /* In the past, we allowed upper-case CPU names, but it doesn't
12519 work well with the multilib machinery. */
12520 for (s = cpu_string; *s != 0; s++)
12521 if (ISUPPER (*s))
12523 warning (0, "CPU names must be lower case");
12524 break;
12527 /* 'from-abi' selects the most compatible architecture for the given
12528 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
12529 EABIs, we have to decide whether we're using the 32-bit or 64-bit
12530 version. */
12531 if (strcasecmp (cpu_string, "from-abi") == 0)
12532 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
12533 : ABI_NEEDS_64BIT_REGS ? 3
12534 : (TARGET_64BIT ? 3 : 1));
12536 /* 'default' has traditionally been a no-op. Probably not very useful. */
12537 if (strcasecmp (cpu_string, "default") == 0)
12538 return NULL;
12540 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
12541 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
12542 return mips_cpu_info_table + i;
12544 return NULL;
12547 /* Set up globals to generate code for the ISA or processor
12548 described by INFO. */
12550 static void
12551 mips_set_architecture (const struct mips_cpu_info *info)
12553 if (info != 0)
12555 mips_arch_info = info;
12556 mips_arch = info->cpu;
12557 mips_isa = info->isa;
12561 /* Likewise for tuning. */
12563 static void
12564 mips_set_tune (const struct mips_cpu_info *info)
12566 if (info != 0)
12568 mips_tune_info = info;
12569 mips_tune = info->cpu;
12573 /* Implement TARGET_HANDLE_OPTION. */
12575 static bool
12576 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
12578 switch (code)
12580 case OPT_mabi_:
12581 if (strcmp (arg, "32") == 0)
12582 mips_abi = ABI_32;
12583 else if (strcmp (arg, "o64") == 0)
12584 mips_abi = ABI_O64;
12585 else if (strcmp (arg, "n32") == 0)
12586 mips_abi = ABI_N32;
12587 else if (strcmp (arg, "64") == 0)
12588 mips_abi = ABI_64;
12589 else if (strcmp (arg, "eabi") == 0)
12590 mips_abi = ABI_EABI;
12591 else
12592 return false;
12593 return true;
12595 case OPT_march_:
12596 case OPT_mtune_:
12597 return mips_parse_cpu (arg) != 0;
12599 case OPT_mips:
12600 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
12601 return mips_isa_option_info != 0;
12603 case OPT_mno_flush_func:
12604 mips_cache_flush_func = NULL;
12605 return true;
12607 case OPT_mcode_readable_:
12608 if (strcmp (arg, "yes") == 0)
12609 mips_code_readable = CODE_READABLE_YES;
12610 else if (strcmp (arg, "pcrel") == 0)
12611 mips_code_readable = CODE_READABLE_PCREL;
12612 else if (strcmp (arg, "no") == 0)
12613 mips_code_readable = CODE_READABLE_NO;
12614 else
12615 return false;
12616 return true;
12618 default:
12619 return true;
12623 /* Implement OVERRIDE_OPTIONS. */
12625 void
12626 mips_override_options (void)
12628 int i, start, regno, mode;
12630 #ifdef SUBTARGET_OVERRIDE_OPTIONS
12631 SUBTARGET_OVERRIDE_OPTIONS;
12632 #endif
12634 /* Set the small data limit. */
12635 mips_small_data_threshold = (g_switch_set
12636 ? g_switch_value
12637 : MIPS_DEFAULT_GVALUE);
12639 /* The following code determines the architecture and register size.
12640 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
12641 The GAS and GCC code should be kept in sync as much as possible. */
12643 if (mips_arch_string != 0)
12644 mips_set_architecture (mips_parse_cpu (mips_arch_string));
12646 if (mips_isa_option_info != 0)
12648 if (mips_arch_info == 0)
12649 mips_set_architecture (mips_isa_option_info);
12650 else if (mips_arch_info->isa != mips_isa_option_info->isa)
12651 error ("%<-%s%> conflicts with the other architecture options, "
12652 "which specify a %s processor",
12653 mips_isa_option_info->name,
12654 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
12657 if (mips_arch_info == 0)
12659 #ifdef MIPS_CPU_STRING_DEFAULT
12660 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
12661 #else
12662 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
12663 #endif
12666 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
12667 error ("%<-march=%s%> is not compatible with the selected ABI",
12668 mips_arch_info->name);
12670 /* Optimize for mips_arch, unless -mtune selects a different processor. */
12671 if (mips_tune_string != 0)
12672 mips_set_tune (mips_parse_cpu (mips_tune_string));
12674 if (mips_tune_info == 0)
12675 mips_set_tune (mips_arch_info);
12677 if ((target_flags_explicit & MASK_64BIT) != 0)
12679 /* The user specified the size of the integer registers. Make sure
12680 it agrees with the ABI and ISA. */
12681 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
12682 error ("%<-mgp64%> used with a 32-bit processor");
12683 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
12684 error ("%<-mgp32%> used with a 64-bit ABI");
12685 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
12686 error ("%<-mgp64%> used with a 32-bit ABI");
12688 else
12690 /* Infer the integer register size from the ABI and processor.
12691 Restrict ourselves to 32-bit registers if that's all the
12692 processor has, or if the ABI cannot handle 64-bit registers. */
12693 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
12694 target_flags &= ~MASK_64BIT;
12695 else
12696 target_flags |= MASK_64BIT;
12699 if ((target_flags_explicit & MASK_FLOAT64) != 0)
12701 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
12702 error ("unsupported combination: %s", "-mfp64 -msingle-float");
12703 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
12704 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
12705 else if (!TARGET_64BIT && TARGET_FLOAT64)
12707 if (!ISA_HAS_MXHC1)
12708 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
12709 " the target supports the mfhc1 and mthc1 instructions");
12710 else if (mips_abi != ABI_32)
12711 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
12712 " the o32 ABI");
12715 else
12717 /* -msingle-float selects 32-bit float registers. Otherwise the
12718 float registers should be the same size as the integer ones. */
12719 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
12720 target_flags |= MASK_FLOAT64;
12721 else
12722 target_flags &= ~MASK_FLOAT64;
12725 /* End of code shared with GAS. */
12727 /* If no -mlong* option was given, infer it from the other options. */
12728 if ((target_flags_explicit & MASK_LONG64) == 0)
12730 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
12731 target_flags |= MASK_LONG64;
12732 else
12733 target_flags &= ~MASK_LONG64;
12736 if (!TARGET_OLDABI)
12737 flag_pcc_struct_return = 0;
12739 /* Decide which rtx_costs structure to use. */
12740 if (optimize_size)
12741 mips_cost = &mips_rtx_cost_optimize_size;
12742 else
12743 mips_cost = &mips_rtx_cost_data[mips_tune];
12745 /* If the user hasn't specified a branch cost, use the processor's
12746 default. */
12747 if (mips_branch_cost == 0)
12748 mips_branch_cost = mips_cost->branch_cost;
12750 /* If neither -mbranch-likely nor -mno-branch-likely was given
12751 on the command line, set MASK_BRANCHLIKELY based on the target
12752 architecture and tuning flags. Annulled delay slots are a
12753 size win, so we only consider the processor-specific tuning
12754 for !optimize_size. */
12755 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
12757 if (ISA_HAS_BRANCHLIKELY
12758 && (optimize_size
12759 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
12760 target_flags |= MASK_BRANCHLIKELY;
12761 else
12762 target_flags &= ~MASK_BRANCHLIKELY;
12764 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
12765 warning (0, "the %qs architecture does not support branch-likely"
12766 " instructions", mips_arch_info->name);
12768 /* The effect of -mabicalls isn't defined for the EABI. */
12769 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
12771 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12772 target_flags &= ~MASK_ABICALLS;
12775 /* MIPS16 cannot generate PIC yet. */
12776 if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
12778 sorry ("MIPS16 PIC");
12779 target_flags &= ~MASK_ABICALLS;
12780 flag_pic = flag_pie = flag_shlib = 0;
12783 if (TARGET_ABICALLS)
12784 /* We need to set flag_pic for executables as well as DSOs
12785 because we may reference symbols that are not defined in
12786 the final executable. (MIPS does not use things like
12787 copy relocs, for example.)
12789 Also, there is a body of code that uses __PIC__ to distinguish
12790 between -mabicalls and -mno-abicalls code. */
12791 flag_pic = 1;
12793 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12794 faster code, but at the expense of more nops. Enable it at -O3 and
12795 above. */
12796 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
12797 target_flags |= MASK_VR4130_ALIGN;
12799 /* Prefer a call to memcpy over inline code when optimizing for size,
12800 though see MOVE_RATIO in mips.h. */
12801 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
12802 target_flags |= MASK_MEMCPY;
12804 /* If we have a nonzero small-data limit, check that the -mgpopt
12805 setting is consistent with the other target flags. */
12806 if (mips_small_data_threshold > 0)
12808 if (!TARGET_GPOPT)
12810 if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
12811 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12813 TARGET_LOCAL_SDATA = false;
12814 TARGET_EXTERN_SDATA = false;
12816 else
12818 if (TARGET_VXWORKS_RTP)
12819 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12821 if (TARGET_ABICALLS)
12822 warning (0, "cannot use small-data accesses for %qs",
12823 "-mabicalls");
12827 #ifdef MIPS_TFMODE_FORMAT
12828 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
12829 #endif
12831 /* Make sure that the user didn't turn off paired single support when
12832 MIPS-3D support is requested. */
12833 if (TARGET_MIPS3D
12834 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
12835 && !TARGET_PAIRED_SINGLE_FLOAT)
12836 error ("%<-mips3d%> requires %<-mpaired-single%>");
12838 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12839 if (TARGET_MIPS3D)
12840 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
12842 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12843 and TARGET_HARD_FLOAT_ABI are both true. */
12844 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
12845 error ("%qs must be used with %qs",
12846 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
12847 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
12849 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12850 enabled. */
12851 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
12852 warning (0, "the %qs architecture does not support paired-single"
12853 " instructions", mips_arch_info->name);
12855 /* If TARGET_DSPR2, enable MASK_DSP. */
12856 if (TARGET_DSPR2)
12857 target_flags |= MASK_DSP;
12859 mips_init_print_operand_punct ();
12861 /* Set up array to map GCC register number to debug register number.
12862 Ignore the special purpose register numbers. */
12864 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12866 mips_dbx_regno[i] = INVALID_REGNUM;
12867 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12868 mips_dwarf_regno[i] = i;
12869 else
12870 mips_dwarf_regno[i] = INVALID_REGNUM;
12873 start = GP_DBX_FIRST - GP_REG_FIRST;
12874 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12875 mips_dbx_regno[i] = i + start;
12877 start = FP_DBX_FIRST - FP_REG_FIRST;
12878 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12879 mips_dbx_regno[i] = i + start;
12881 /* Accumulator debug registers use big-endian ordering. */
12882 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12883 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12884 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12885 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12886 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12888 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12889 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12892 /* Set up mips_hard_regno_mode_ok. */
12893 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12894 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12895 mips_hard_regno_mode_ok[(int)mode][regno]
12896 = mips_hard_regno_mode_ok_p (regno, mode);
12898 /* Function to allocate machine-dependent function status. */
12899 init_machine_status = &mips_init_machine_status;
12901 /* Default to working around R4000 errata only if the processor
12902 was selected explicitly. */
12903 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12904 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12905 target_flags |= MASK_FIX_R4000;
12907 /* Default to working around R4400 errata only if the processor
12908 was selected explicitly. */
12909 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12910 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12911 target_flags |= MASK_FIX_R4400;
12913 /* Save base state of options. */
12914 mips_base_mips16 = TARGET_MIPS16;
12915 mips_base_target_flags = target_flags;
12916 mips_base_delayed_branch = flag_delayed_branch;
12917 mips_base_schedule_insns = flag_schedule_insns;
12918 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12919 mips_base_move_loop_invariants = flag_move_loop_invariants;
12920 mips_base_align_loops = align_loops;
12921 mips_base_align_jumps = align_jumps;
12922 mips_base_align_functions = align_functions;
12924 /* Now select the ISA mode. */
12925 mips_set_mips16_mode (mips_base_mips16);
12927 /* We call dbr_schedule from within mips_reorg. */
12928 flag_delayed_branch = 0;
12931 /* Swap the register information for registers I and I + 1, which
12932 currently have the wrong endianness. Note that the registers'
12933 fixedness and call-clobberedness might have been set on the
12934 command line. */
12936 static void
12937 mips_swap_registers (unsigned int i)
12939 int tmpi;
12940 const char *tmps;
12942 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12943 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12945 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12946 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12947 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12948 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12950 #undef SWAP_STRING
12951 #undef SWAP_INT
12954 /* Implement CONDITIONAL_REGISTER_USAGE. */
12956 void
12957 mips_conditional_register_usage (void)
12959 if (!ISA_HAS_DSP)
12961 int regno;
12963 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12964 fixed_regs[regno] = call_used_regs[regno] = 1;
12966 if (!TARGET_HARD_FLOAT)
12968 int regno;
12970 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12971 fixed_regs[regno] = call_used_regs[regno] = 1;
12972 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12973 fixed_regs[regno] = call_used_regs[regno] = 1;
12975 else if (! ISA_HAS_8CC)
12977 int regno;
12979 /* We only have a single condition-code register. We implement
12980 this by fixing all the condition-code registers and generating
12981 RTL that refers directly to ST_REG_FIRST. */
12982 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12983 fixed_regs[regno] = call_used_regs[regno] = 1;
12985 /* In MIPS16 mode, we permit the $t temporary registers to be used
12986 for reload. We prohibit the unused $s registers, since they
12987 are call-saved, and saving them via a MIPS16 register would
12988 probably waste more time than just reloading the value. */
12989 if (TARGET_MIPS16)
12991 fixed_regs[18] = call_used_regs[18] = 1;
12992 fixed_regs[19] = call_used_regs[19] = 1;
12993 fixed_regs[20] = call_used_regs[20] = 1;
12994 fixed_regs[21] = call_used_regs[21] = 1;
12995 fixed_regs[22] = call_used_regs[22] = 1;
12996 fixed_regs[23] = call_used_regs[23] = 1;
12997 fixed_regs[26] = call_used_regs[26] = 1;
12998 fixed_regs[27] = call_used_regs[27] = 1;
12999 fixed_regs[30] = call_used_regs[30] = 1;
13001 /* $f20-$f23 are call-clobbered for n64. */
13002 if (mips_abi == ABI_64)
13004 int regno;
13005 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
13006 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13008 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
13009 for n32. */
13010 if (mips_abi == ABI_N32)
13012 int regno;
13013 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
13014 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13016 /* Make sure that double-register accumulator values are correctly
13017 ordered for the current endianness. */
13018 if (TARGET_LITTLE_ENDIAN)
13020 unsigned int regno;
13022 mips_swap_registers (MD_REG_FIRST);
13023 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
13024 mips_swap_registers (regno);
13028 /* Initialize vector TARGET to VALS. */
13030 void
13031 mips_expand_vector_init (rtx target, rtx vals)
13033 enum machine_mode mode;
13034 enum machine_mode inner;
13035 unsigned int i, n_elts;
13036 rtx mem;
13038 mode = GET_MODE (target);
13039 inner = GET_MODE_INNER (mode);
13040 n_elts = GET_MODE_NUNITS (mode);
13042 gcc_assert (VECTOR_MODE_P (mode));
13044 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
13045 for (i = 0; i < n_elts; i++)
13046 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
13047 XVECEXP (vals, 0, i));
13049 emit_move_insn (target, mem);
13052 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
13053 other registers for instructions for which it is possible. This
13054 encourages the compiler to use CMP in cases where an XOR would
13055 require some register shuffling. */
13057 void
13058 mips_order_regs_for_local_alloc (void)
13060 int i;
13062 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
13063 reg_alloc_order[i] = i;
13065 if (TARGET_MIPS16)
13067 /* It really doesn't matter where we put register 0, since it is
13068 a fixed register anyhow. */
13069 reg_alloc_order[0] = 24;
13070 reg_alloc_order[24] = 0;
13074 /* Initialize the GCC target structure. */
13075 #undef TARGET_ASM_ALIGNED_HI_OP
13076 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
13077 #undef TARGET_ASM_ALIGNED_SI_OP
13078 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
13079 #undef TARGET_ASM_ALIGNED_DI_OP
13080 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
13082 #undef TARGET_ASM_FUNCTION_PROLOGUE
13083 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
13084 #undef TARGET_ASM_FUNCTION_EPILOGUE
13085 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
13086 #undef TARGET_ASM_SELECT_RTX_SECTION
13087 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
13088 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
13089 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
13091 #undef TARGET_SCHED_INIT
13092 #define TARGET_SCHED_INIT mips_sched_init
13093 #undef TARGET_SCHED_REORDER
13094 #define TARGET_SCHED_REORDER mips_sched_reorder
13095 #undef TARGET_SCHED_REORDER2
13096 #define TARGET_SCHED_REORDER2 mips_sched_reorder
13097 #undef TARGET_SCHED_VARIABLE_ISSUE
13098 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
13099 #undef TARGET_SCHED_ADJUST_COST
13100 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
13101 #undef TARGET_SCHED_ISSUE_RATE
13102 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
13103 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
13104 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
13105 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
13106 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
13107 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13108 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
13109 mips_multipass_dfa_lookahead
13111 #undef TARGET_DEFAULT_TARGET_FLAGS
13112 #define TARGET_DEFAULT_TARGET_FLAGS \
13113 (TARGET_DEFAULT \
13114 | TARGET_CPU_DEFAULT \
13115 | TARGET_ENDIAN_DEFAULT \
13116 | TARGET_FP_EXCEPTIONS_DEFAULT \
13117 | MASK_CHECK_ZERO_DIV \
13118 | MASK_FUSED_MADD)
13119 #undef TARGET_HANDLE_OPTION
13120 #define TARGET_HANDLE_OPTION mips_handle_option
13122 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13123 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
13125 #undef TARGET_INSERT_ATTRIBUTES
13126 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
13127 #undef TARGET_MERGE_DECL_ATTRIBUTES
13128 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
13129 #undef TARGET_SET_CURRENT_FUNCTION
13130 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
13132 #undef TARGET_VALID_POINTER_MODE
13133 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
13134 #undef TARGET_RTX_COSTS
13135 #define TARGET_RTX_COSTS mips_rtx_costs
13136 #undef TARGET_ADDRESS_COST
13137 #define TARGET_ADDRESS_COST mips_address_cost
13139 #undef TARGET_IN_SMALL_DATA_P
13140 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
13142 #undef TARGET_MACHINE_DEPENDENT_REORG
13143 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
13145 #undef TARGET_ASM_FILE_START
13146 #define TARGET_ASM_FILE_START mips_file_start
13147 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
13148 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
13150 #undef TARGET_INIT_LIBFUNCS
13151 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
13153 #undef TARGET_BUILD_BUILTIN_VA_LIST
13154 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
13155 #undef TARGET_EXPAND_BUILTIN_VA_START
13156 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
13157 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13158 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
13160 #undef TARGET_PROMOTE_FUNCTION_ARGS
13161 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
13162 #undef TARGET_PROMOTE_FUNCTION_RETURN
13163 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
13164 #undef TARGET_PROMOTE_PROTOTYPES
13165 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
13167 #undef TARGET_RETURN_IN_MEMORY
13168 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
13169 #undef TARGET_RETURN_IN_MSB
13170 #define TARGET_RETURN_IN_MSB mips_return_in_msb
13172 #undef TARGET_ASM_OUTPUT_MI_THUNK
13173 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
13174 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
13175 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
13177 #undef TARGET_SETUP_INCOMING_VARARGS
13178 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
13179 #undef TARGET_STRICT_ARGUMENT_NAMING
13180 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
13181 #undef TARGET_MUST_PASS_IN_STACK
13182 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
13183 #undef TARGET_PASS_BY_REFERENCE
13184 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
13185 #undef TARGET_CALLEE_COPIES
13186 #define TARGET_CALLEE_COPIES mips_callee_copies
13187 #undef TARGET_ARG_PARTIAL_BYTES
13188 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
13190 #undef TARGET_MODE_REP_EXTENDED
13191 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
13193 #undef TARGET_VECTOR_MODE_SUPPORTED_P
13194 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
13196 #undef TARGET_SCALAR_MODE_SUPPORTED_P
13197 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
13199 #undef TARGET_INIT_BUILTINS
13200 #define TARGET_INIT_BUILTINS mips_init_builtins
13201 #undef TARGET_EXPAND_BUILTIN
13202 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
13204 #undef TARGET_HAVE_TLS
13205 #define TARGET_HAVE_TLS HAVE_AS_TLS
13207 #undef TARGET_CANNOT_FORCE_CONST_MEM
13208 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
13210 #undef TARGET_ENCODE_SECTION_INFO
13211 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
13213 #undef TARGET_ATTRIBUTE_TABLE
13214 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
13215 /* All our function attributes are related to how out-of-line copies should
13216 be compiled or called. They don't in themselves prevent inlining. */
13217 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
13218 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
13220 #undef TARGET_EXTRA_LIVE_ON_ENTRY
13221 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
13223 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
13224 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
13225 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
13226 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
13228 #undef TARGET_COMP_TYPE_ATTRIBUTES
13229 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
13231 #ifdef HAVE_AS_DTPRELWORD
13232 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
13233 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
13234 #endif
13235 #undef TARGET_DWARF_REGISTER_SPAN
13236 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
13238 struct gcc_target targetm = TARGET_INITIALIZER;
13240 #include "gt-mips.h"