| blob | 0a507e07a2f388e7fc4a817aed2674bb4ba9c369 |
1 ;; GCC machine description for MMX and 3dNOW! instructions
2 ;; Copyright (C) 2005, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The MMX and 3dNOW! patterns are in the same file because they use
22 ;; the same register file, and 3dNOW! adds a number of extensions to
23 ;; the base integer MMX isa.
25 ;; Note! Except for the basic move instructions, *all* of these
26 ;; patterns are outside the normal optabs namespace. This is because
27 ;; use of these registers requires the insertion of emms or femms
28 ;; instructions to return to normal fpu mode. The compiler doesn't
29 ;; know how to do that itself, which means it's up to the user. Which
30 ;; means that we should never use any of these patterns except at the
31 ;; direction of the user via a builtin.
33 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
34 (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
35 (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI])
37 ;; All 8-byte vector modes handled by MMX
38 (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF])
40 ;; Mix-n-match
41 (define_mode_iterator MMXMODE12 [V8QI V4HI])
42 (define_mode_iterator MMXMODE24 [V4HI V2SI])
43 (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
45 ;; Mapping from integer vector mode to mnemonic suffix
46 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")])
48 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
49 ;;
50 ;; Move patterns
51 ;;
52 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54 ;; All of these patterns are enabled for MMX as well as 3dNOW.
55 ;; This is essential for maintaining stable calling conventions.
57 (define_expand "mov<mode>"
58 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "")
59 (match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))]
60 "TARGET_MMX"
61 {
62 ix86_expand_vector_move (<MODE>mode, operands);
63 DONE;
64 })
66 (define_insn "*mov<mode>_internal_rex64"
67 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
68 "=rm,r,!?y,!?y ,m ,!y,Y2,x,x ,m,r,x")
69 (match_operand:MMXMODEI8 1 "vector_move_operand"
70 "Cr ,m,C ,!?ym,!?y,Y2,!y,C,xm,x,x,r"))]
71 "TARGET_64BIT && TARGET_MMX
72 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
73 "@
74 mov{q}\t{%1, %0|%0, %1}
75 mov{q}\t{%1, %0|%0, %1}
76 pxor\t%0, %0
77 movq\t{%1, %0|%0, %1}
78 movq\t{%1, %0|%0, %1}
79 movdq2q\t{%1, %0|%0, %1}
80 movq2dq\t{%1, %0|%0, %1}
81 pxor\t%0, %0
82 movq\t{%1, %0|%0, %1}
83 movq\t{%1, %0|%0, %1}
84 movd\t{%1, %0|%0, %1}
85 movd\t{%1, %0|%0, %1}"
86 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
87 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
88 (set_attr "mode" "DI")])
90 (define_insn "*mov<mode>_internal"
91 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
92 "=!?y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,r ,m")
93 (match_operand:MMXMODEI8 1 "vector_move_operand"
94 "C ,!ym,!?y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))]
95 "TARGET_MMX
96 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
97 "@
98 pxor\t%0, %0
99 movq\t{%1, %0|%0, %1}
100 movq\t{%1, %0|%0, %1}
101 movdq2q\t{%1, %0|%0, %1}
102 movq2dq\t{%1, %0|%0, %1}
103 pxor\t%0, %0
104 movq\t{%1, %0|%0, %1}
105 movq\t{%1, %0|%0, %1}
106 xorps\t%0, %0
107 movaps\t{%1, %0|%0, %1}
108 movlps\t{%1, %0|%0, %1}
109 movlps\t{%1, %0|%0, %1}
110 #
111 #"
112 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
113 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
114 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
116 (define_expand "movv2sf"
117 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
118 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
119 "TARGET_MMX"
120 {
121 ix86_expand_vector_move (V2SFmode, operands);
122 DONE;
123 })
125 (define_insn "*movv2sf_internal_rex64"
126 [(set (match_operand:V2SF 0 "nonimmediate_operand"
127 "=rm,r ,!?y,!?y ,m ,!y,Y2,x,x,x,m,r,x")
128 (match_operand:V2SF 1 "vector_move_operand"
129 "Cr ,m ,C ,!?ym,!y,Y2,!y,C,x,m,x,x,r"))]
130 "TARGET_64BIT && TARGET_MMX
131 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
132 "@
133 mov{q}\t{%1, %0|%0, %1}
134 mov{q}\t{%1, %0|%0, %1}
135 pxor\t%0, %0
136 movq\t{%1, %0|%0, %1}
137 movq\t{%1, %0|%0, %1}
138 movdq2q\t{%1, %0|%0, %1}
139 movq2dq\t{%1, %0|%0, %1}
140 xorps\t%0, %0
141 movaps\t{%1, %0|%0, %1}
142 movlps\t{%1, %0|%0, %1}
143 movlps\t{%1, %0|%0, %1}
144 movd\t{%1, %0|%0, %1}
145 movd\t{%1, %0|%0, %1}"
146 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
147 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
148 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
150 (define_insn "*movv2sf_internal"
151 [(set (match_operand:V2SF 0 "nonimmediate_operand"
152 "=!?y,!?y ,m ,!y ,*Y2,*x,*x,*x,m ,r ,m")
153 (match_operand:V2SF 1 "vector_move_operand"
154 "C ,!?ym,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))]
155 "TARGET_MMX
156 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
157 "@
158 pxor\t%0, %0
159 movq\t{%1, %0|%0, %1}
160 movq\t{%1, %0|%0, %1}
161 movdq2q\t{%1, %0|%0, %1}
162 movq2dq\t{%1, %0|%0, %1}
163 xorps\t%0, %0
164 movaps\t{%1, %0|%0, %1}
165 movlps\t{%1, %0|%0, %1}
166 movlps\t{%1, %0|%0, %1}
167 #
168 #"
169 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
170 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
171 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
173 ;; %%% This multiword shite has got to go.
174 (define_split
175 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
176 (match_operand:MMXMODE 1 "general_operand" ""))]
177 "!TARGET_64BIT && reload_completed
178 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
179 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
180 [(const_int 0)]
181 "ix86_split_long_move (operands); DONE;")
183 (define_expand "push<mode>1"
184 [(match_operand:MMXMODE 0 "register_operand" "")]
185 "TARGET_MMX"
186 {
187 ix86_expand_push (<MODE>mode, operands[0]);
188 DONE;
189 })
191 (define_expand "movmisalign<mode>"
192 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
193 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
194 "TARGET_MMX"
195 {
196 ix86_expand_vector_move (<MODE>mode, operands);
197 DONE;
198 })
200 (define_insn "sse_movntdi"
201 [(set (match_operand:DI 0 "memory_operand" "=m")
202 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
203 UNSPEC_MOVNT))]
204 "TARGET_SSE || TARGET_3DNOW_A"
205 "movntq\t{%1, %0|%0, %1}"
206 [(set_attr "type" "mmxmov")
207 (set_attr "mode" "DI")])
209 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
210 ;;
211 ;; Parallel single-precision floating point arithmetic
212 ;;
213 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215 (define_expand "mmx_addv2sf3"
216 [(set (match_operand:V2SF 0 "register_operand" "")
217 (plus:V2SF
218 (match_operand:V2SF 1 "nonimmediate_operand" "")
219 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
220 "TARGET_3DNOW"
221 "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
223 (define_insn "*mmx_addv2sf3"
224 [(set (match_operand:V2SF 0 "register_operand" "=y")
225 (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
226 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
227 "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
228 "pfadd\t{%2, %0|%0, %2}"
229 [(set_attr "type" "mmxadd")
230 (set_attr "mode" "V2SF")])
232 (define_expand "mmx_subv2sf3"
233 [(set (match_operand:V2SF 0 "register_operand" "")
234 (minus:V2SF (match_operand:V2SF 1 "register_operand" "")
235 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
236 "TARGET_3DNOW"
237 "")
239 (define_expand "mmx_subrv2sf3"
240 [(set (match_operand:V2SF 0 "register_operand" "")
241 (minus:V2SF (match_operand:V2SF 2 "register_operand" "")
242 (match_operand:V2SF 1 "nonimmediate_operand" "")))]
243 "TARGET_3DNOW"
244 "")
246 (define_insn "*mmx_subv2sf3"
247 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
248 (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
249 (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
250 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
251 "@
252 pfsub\t{%2, %0|%0, %2}
253 pfsubr\t{%2, %0|%0, %2}"
254 [(set_attr "type" "mmxadd")
255 (set_attr "mode" "V2SF")])
257 (define_expand "mmx_mulv2sf3"
258 [(set (match_operand:V2SF 0 "register_operand" "")
259 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
260 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
261 "TARGET_3DNOW"
262 "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
264 (define_insn "*mmx_mulv2sf3"
265 [(set (match_operand:V2SF 0 "register_operand" "=y")
266 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
267 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
268 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
269 "pfmul\t{%2, %0|%0, %2}"
270 [(set_attr "type" "mmxmul")
271 (set_attr "mode" "V2SF")])
273 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
274 ;; isn't really correct, as those rtl operators aren't defined when
275 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
277 (define_expand "mmx_<code>v2sf3"
278 [(set (match_operand:V2SF 0 "register_operand" "")
279 (smaxmin:V2SF
280 (match_operand:V2SF 1 "nonimmediate_operand" "")
281 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
282 "TARGET_3DNOW"
283 {
284 if (!flag_finite_math_only)
285 operands[1] = force_reg (V2SFmode, operands[1]);
286 ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
287 })
289 (define_insn "*mmx_<code>v2sf3_finite"
290 [(set (match_operand:V2SF 0 "register_operand" "=y")
291 (smaxmin:V2SF
292 (match_operand:V2SF 1 "nonimmediate_operand" "%0")
293 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
294 "TARGET_3DNOW && flag_finite_math_only
295 && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
296 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
297 [(set_attr "type" "mmxadd")
298 (set_attr "mode" "V2SF")])
300 (define_insn "*mmx_<code>v2sf3"
301 [(set (match_operand:V2SF 0 "register_operand" "=y")
302 (smaxmin:V2SF
303 (match_operand:V2SF 1 "register_operand" "0")
304 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
305 "TARGET_3DNOW"
306 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
307 [(set_attr "type" "mmxadd")
308 (set_attr "mode" "V2SF")])
310 (define_insn "mmx_rcpv2sf2"
311 [(set (match_operand:V2SF 0 "register_operand" "=y")
312 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
313 UNSPEC_PFRCP))]
314 "TARGET_3DNOW"
315 "pfrcp\t{%1, %0|%0, %1}"
316 [(set_attr "type" "mmx")
317 (set_attr "mode" "V2SF")])
319 (define_insn "mmx_rcpit1v2sf3"
320 [(set (match_operand:V2SF 0 "register_operand" "=y")
321 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
322 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
323 UNSPEC_PFRCPIT1))]
324 "TARGET_3DNOW"
325 "pfrcpit1\t{%2, %0|%0, %2}"
326 [(set_attr "type" "mmx")
327 (set_attr "mode" "V2SF")])
329 (define_insn "mmx_rcpit2v2sf3"
330 [(set (match_operand:V2SF 0 "register_operand" "=y")
331 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
332 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
333 UNSPEC_PFRCPIT2))]
334 "TARGET_3DNOW"
335 "pfrcpit2\t{%2, %0|%0, %2}"
336 [(set_attr "type" "mmx")
337 (set_attr "mode" "V2SF")])
339 (define_insn "mmx_rsqrtv2sf2"
340 [(set (match_operand:V2SF 0 "register_operand" "=y")
341 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
342 UNSPEC_PFRSQRT))]
343 "TARGET_3DNOW"
344 "pfrsqrt\t{%1, %0|%0, %1}"
345 [(set_attr "type" "mmx")
346 (set_attr "mode" "V2SF")])
348 (define_insn "mmx_rsqit1v2sf3"
349 [(set (match_operand:V2SF 0 "register_operand" "=y")
350 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
351 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
352 UNSPEC_PFRSQIT1))]
353 "TARGET_3DNOW"
354 "pfrsqit1\t{%2, %0|%0, %2}"
355 [(set_attr "type" "mmx")
356 (set_attr "mode" "V2SF")])
358 (define_insn "mmx_haddv2sf3"
359 [(set (match_operand:V2SF 0 "register_operand" "=y")
360 (vec_concat:V2SF
361 (plus:SF
362 (vec_select:SF
363 (match_operand:V2SF 1 "register_operand" "0")
364 (parallel [(const_int 0)]))
365 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
366 (plus:SF
367 (vec_select:SF
368 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
369 (parallel [(const_int 0)]))
370 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
371 "TARGET_3DNOW"
372 "pfacc\t{%2, %0|%0, %2}"
373 [(set_attr "type" "mmxadd")
374 (set_attr "mode" "V2SF")])
376 (define_insn "mmx_hsubv2sf3"
377 [(set (match_operand:V2SF 0 "register_operand" "=y")
378 (vec_concat:V2SF
379 (minus:SF
380 (vec_select:SF
381 (match_operand:V2SF 1 "register_operand" "0")
382 (parallel [(const_int 0)]))
383 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
384 (minus:SF
385 (vec_select:SF
386 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
387 (parallel [(const_int 0)]))
388 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
389 "TARGET_3DNOW_A"
390 "pfnacc\t{%2, %0|%0, %2}"
391 [(set_attr "type" "mmxadd")
392 (set_attr "mode" "V2SF")])
394 (define_insn "mmx_addsubv2sf3"
395 [(set (match_operand:V2SF 0 "register_operand" "=y")
396 (vec_merge:V2SF
397 (plus:V2SF
398 (match_operand:V2SF 1 "register_operand" "0")
399 (match_operand:V2SF 2 "nonimmediate_operand" "ym"))
400 (minus:V2SF (match_dup 1) (match_dup 2))
401 (const_int 1)))]
402 "TARGET_3DNOW_A"
403 "pfpnacc\t{%2, %0|%0, %2}"
404 [(set_attr "type" "mmxadd")
405 (set_attr "mode" "V2SF")])
407 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
408 ;;
409 ;; Parallel single-precision floating point comparisons
410 ;;
411 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
413 (define_expand "mmx_eqv2sf3"
414 [(set (match_operand:V2SI 0 "register_operand" "")
415 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "")
416 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
417 "TARGET_3DNOW"
418 "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
420 (define_insn "*mmx_eqv2sf3"
421 [(set (match_operand:V2SI 0 "register_operand" "=y")
422 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
423 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
424 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
425 "pfcmpeq\t{%2, %0|%0, %2}"
426 [(set_attr "type" "mmxcmp")
427 (set_attr "mode" "V2SF")])
429 (define_insn "mmx_gtv2sf3"
430 [(set (match_operand:V2SI 0 "register_operand" "=y")
431 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
432 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
433 "TARGET_3DNOW"
434 "pfcmpgt\t{%2, %0|%0, %2}"
435 [(set_attr "type" "mmxcmp")
436 (set_attr "mode" "V2SF")])
438 (define_insn "mmx_gev2sf3"
439 [(set (match_operand:V2SI 0 "register_operand" "=y")
440 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
441 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
442 "TARGET_3DNOW"
443 "pfcmpge\t{%2, %0|%0, %2}"
444 [(set_attr "type" "mmxcmp")
445 (set_attr "mode" "V2SF")])
447 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
448 ;;
449 ;; Parallel single-precision floating point conversion operations
450 ;;
451 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
453 (define_insn "mmx_pf2id"
454 [(set (match_operand:V2SI 0 "register_operand" "=y")
455 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
456 "TARGET_3DNOW"
457 "pf2id\t{%1, %0|%0, %1}"
458 [(set_attr "type" "mmxcvt")
459 (set_attr "mode" "V2SF")])
461 (define_insn "mmx_pf2iw"
462 [(set (match_operand:V2SI 0 "register_operand" "=y")
463 (sign_extend:V2SI
464 (ss_truncate:V2HI
465 (fix:V2SI
466 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
467 "TARGET_3DNOW_A"
468 "pf2iw\t{%1, %0|%0, %1}"
469 [(set_attr "type" "mmxcvt")
470 (set_attr "mode" "V2SF")])
472 (define_insn "mmx_pi2fw"
473 [(set (match_operand:V2SF 0 "register_operand" "=y")
474 (float:V2SF
475 (sign_extend:V2SI
476 (truncate:V2HI
477 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
478 "TARGET_3DNOW_A"
479 "pi2fw\t{%1, %0|%0, %1}"
480 [(set_attr "type" "mmxcvt")
481 (set_attr "mode" "V2SF")])
483 (define_insn "mmx_floatv2si2"
484 [(set (match_operand:V2SF 0 "register_operand" "=y")
485 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
486 "TARGET_3DNOW"
487 "pi2fd\t{%1, %0|%0, %1}"
488 [(set_attr "type" "mmxcvt")
489 (set_attr "mode" "V2SF")])
491 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
492 ;;
493 ;; Parallel single-precision floating point element swizzling
494 ;;
495 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
497 (define_insn "mmx_pswapdv2sf2"
498 [(set (match_operand:V2SF 0 "register_operand" "=y")
499 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
500 (parallel [(const_int 1) (const_int 0)])))]
501 "TARGET_3DNOW_A"
502 "pswapd\t{%1, %0|%0, %1}"
503 [(set_attr "type" "mmxcvt")
504 (set_attr "mode" "V2SF")])
506 (define_insn "*vec_dupv2sf"
507 [(set (match_operand:V2SF 0 "register_operand" "=y")
508 (vec_duplicate:V2SF
509 (match_operand:SF 1 "register_operand" "0")))]
510 "TARGET_MMX"
511 "punpckldq\t%0, %0"
512 [(set_attr "type" "mmxcvt")
513 (set_attr "mode" "DI")])
515 (define_insn "*mmx_concatv2sf"
516 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
517 (vec_concat:V2SF
518 (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
519 (match_operand:SF 2 "vector_move_operand" "ym,C")))]
520 "TARGET_MMX && !TARGET_SSE"
521 "@
522 punpckldq\t{%2, %0|%0, %2}
523 movd\t{%1, %0|%0, %1}"
524 [(set_attr "type" "mmxcvt,mmxmov")
525 (set_attr "mode" "DI")])
527 (define_expand "vec_setv2sf"
528 [(match_operand:V2SF 0 "register_operand" "")
529 (match_operand:SF 1 "register_operand" "")
530 (match_operand 2 "const_int_operand" "")]
531 "TARGET_MMX"
532 {
533 ix86_expand_vector_set (false, operands[0], operands[1],
534 INTVAL (operands[2]));
535 DONE;
536 })
538 (define_insn_and_split "*vec_extractv2sf_0"
539 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,m,m,frxy")
540 (vec_select:SF
541 (match_operand:V2SF 1 "nonimmediate_operand" " x,y,x,y,m")
542 (parallel [(const_int 0)])))]
543 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
544 "#"
545 "&& reload_completed"
546 [(const_int 0)]
547 {
548 rtx op1 = operands[1];
549 if (REG_P (op1))
550 op1 = gen_rtx_REG (SFmode, REGNO (op1));
551 else
552 op1 = gen_lowpart (SFmode, op1);
553 emit_move_insn (operands[0], op1);
554 DONE;
555 })
557 (define_insn "*vec_extractv2sf_1"
558 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,frxy")
559 (vec_select:SF
560 (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o")
561 (parallel [(const_int 1)])))]
562 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
563 "@
564 punpckhdq\t%0, %0
565 unpckhps\t%0, %0
566 #"
567 [(set_attr "type" "mmxcvt,sselog1,*")
568 (set_attr "mode" "DI,V4SF,SI")])
570 (define_split
571 [(set (match_operand:SF 0 "register_operand" "")
572 (vec_select:SF
573 (match_operand:V2SF 1 "memory_operand" "")
574 (parallel [(const_int 1)])))]
575 "TARGET_MMX && reload_completed"
576 [(const_int 0)]
577 {
578 operands[1] = adjust_address (operands[1], SFmode, 4);
579 emit_move_insn (operands[0], operands[1]);
580 DONE;
581 })
583 (define_expand "vec_extractv2sf"
584 [(match_operand:SF 0 "register_operand" "")
585 (match_operand:V2SF 1 "register_operand" "")
586 (match_operand 2 "const_int_operand" "")]
587 "TARGET_MMX"
588 {
589 ix86_expand_vector_extract (false, operands[0], operands[1],
590 INTVAL (operands[2]));
591 DONE;
592 })
594 (define_expand "vec_initv2sf"
595 [(match_operand:V2SF 0 "register_operand" "")
596 (match_operand 1 "" "")]
597 "TARGET_SSE"
598 {
599 ix86_expand_vector_init (false, operands[0], operands[1]);
600 DONE;
601 })
603 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
604 ;;
605 ;; Parallel integral arithmetic
606 ;;
607 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
609 (define_expand "mmx_<plusminus_insn><mode>3"
610 [(set (match_operand:MMXMODEI8 0 "register_operand" "")
611 (plusminus:MMXMODEI8
612 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "")
613 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))]
614 "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
615 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
617 (define_insn "*mmx_<plusminus_insn><mode>3"
618 [(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
619 (plusminus:MMXMODEI8
620 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
621 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
622 "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
623 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
624 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
625 [(set_attr "type" "mmxadd")
626 (set_attr "mode" "DI")])
628 (define_expand "mmx_<plusminus_insn><mode>3"
629 [(set (match_operand:MMXMODE12 0 "register_operand" "")
630 (sat_plusminus:MMXMODE12
631 (match_operand:MMXMODE12 1 "nonimmediate_operand" "")
632 (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))]
633 "TARGET_MMX"
634 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
636 (define_insn "*mmx_<plusminus_insn><mode>3"
637 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
638 (sat_plusminus:MMXMODE12
639 (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
640 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
641 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
642 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
643 [(set_attr "type" "mmxadd")
644 (set_attr "mode" "DI")])
646 (define_expand "mmx_mulv4hi3"
647 [(set (match_operand:V4HI 0 "register_operand" "")
648 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "")
649 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
650 "TARGET_MMX"
651 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
653 (define_insn "*mmx_mulv4hi3"
654 [(set (match_operand:V4HI 0 "register_operand" "=y")
655 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
656 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
657 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
658 "pmullw\t{%2, %0|%0, %2}"
659 [(set_attr "type" "mmxmul")
660 (set_attr "mode" "DI")])
662 (define_expand "mmx_smulv4hi3_highpart"
663 [(set (match_operand:V4HI 0 "register_operand" "")
664 (truncate:V4HI
665 (lshiftrt:V4SI
666 (mult:V4SI
667 (sign_extend:V4SI
668 (match_operand:V4HI 1 "nonimmediate_operand" ""))
669 (sign_extend:V4SI
670 (match_operand:V4HI 2 "nonimmediate_operand" "")))
671 (const_int 16))))]
672 "TARGET_MMX"
673 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
675 (define_insn "*mmx_smulv4hi3_highpart"
676 [(set (match_operand:V4HI 0 "register_operand" "=y")
677 (truncate:V4HI
678 (lshiftrt:V4SI
679 (mult:V4SI
680 (sign_extend:V4SI
681 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
682 (sign_extend:V4SI
683 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
684 (const_int 16))))]
685 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
686 "pmulhw\t{%2, %0|%0, %2}"
687 [(set_attr "type" "mmxmul")
688 (set_attr "mode" "DI")])
690 (define_expand "mmx_umulv4hi3_highpart"
691 [(set (match_operand:V4HI 0 "register_operand" "")
692 (truncate:V4HI
693 (lshiftrt:V4SI
694 (mult:V4SI
695 (zero_extend:V4SI
696 (match_operand:V4HI 1 "nonimmediate_operand" ""))
697 (zero_extend:V4SI
698 (match_operand:V4HI 2 "nonimmediate_operand" "")))
699 (const_int 16))))]
700 "TARGET_SSE || TARGET_3DNOW_A"
701 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
703 (define_insn "*mmx_umulv4hi3_highpart"
704 [(set (match_operand:V4HI 0 "register_operand" "=y")
705 (truncate:V4HI
706 (lshiftrt:V4SI
707 (mult:V4SI
708 (zero_extend:V4SI
709 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
710 (zero_extend:V4SI
711 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
712 (const_int 16))))]
713 "(TARGET_SSE || TARGET_3DNOW_A)
714 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
715 "pmulhuw\t{%2, %0|%0, %2}"
716 [(set_attr "type" "mmxmul")
717 (set_attr "mode" "DI")])
719 (define_expand "mmx_pmaddwd"
720 [(set (match_operand:V2SI 0 "register_operand" "")
721 (plus:V2SI
722 (mult:V2SI
723 (sign_extend:V2SI
724 (vec_select:V2HI
725 (match_operand:V4HI 1 "nonimmediate_operand" "")
726 (parallel [(const_int 0) (const_int 2)])))
727 (sign_extend:V2SI
728 (vec_select:V2HI
729 (match_operand:V4HI 2 "nonimmediate_operand" "")
730 (parallel [(const_int 0) (const_int 2)]))))
731 (mult:V2SI
732 (sign_extend:V2SI
733 (vec_select:V2HI (match_dup 1)
734 (parallel [(const_int 1) (const_int 3)])))
735 (sign_extend:V2SI
736 (vec_select:V2HI (match_dup 2)
737 (parallel [(const_int 1) (const_int 3)]))))))]
738 "TARGET_MMX"
739 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
741 (define_insn "*mmx_pmaddwd"
742 [(set (match_operand:V2SI 0 "register_operand" "=y")
743 (plus:V2SI
744 (mult:V2SI
745 (sign_extend:V2SI
746 (vec_select:V2HI
747 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
748 (parallel [(const_int 0) (const_int 2)])))
749 (sign_extend:V2SI
750 (vec_select:V2HI
751 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
752 (parallel [(const_int 0) (const_int 2)]))))
753 (mult:V2SI
754 (sign_extend:V2SI
755 (vec_select:V2HI (match_dup 1)
756 (parallel [(const_int 1) (const_int 3)])))
757 (sign_extend:V2SI
758 (vec_select:V2HI (match_dup 2)
759 (parallel [(const_int 1) (const_int 3)]))))))]
760 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
761 "pmaddwd\t{%2, %0|%0, %2}"
762 [(set_attr "type" "mmxmul")
763 (set_attr "mode" "DI")])
765 (define_expand "mmx_pmulhrwv4hi3"
766 [(set (match_operand:V4HI 0 "register_operand" "")
767 (truncate:V4HI
768 (lshiftrt:V4SI
769 (plus:V4SI
770 (mult:V4SI
771 (sign_extend:V4SI
772 (match_operand:V4HI 1 "nonimmediate_operand" ""))
773 (sign_extend:V4SI
774 (match_operand:V4HI 2 "nonimmediate_operand" "")))
775 (const_vector:V4SI [(const_int 32768) (const_int 32768)
776 (const_int 32768) (const_int 32768)]))
777 (const_int 16))))]
778 "TARGET_3DNOW"
779 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
781 (define_insn "*mmx_pmulhrwv4hi3"
782 [(set (match_operand:V4HI 0 "register_operand" "=y")
783 (truncate:V4HI
784 (lshiftrt:V4SI
785 (plus:V4SI
786 (mult:V4SI
787 (sign_extend:V4SI
788 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
789 (sign_extend:V4SI
790 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
791 (const_vector:V4SI [(const_int 32768) (const_int 32768)
792 (const_int 32768) (const_int 32768)]))
793 (const_int 16))))]
794 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
795 "pmulhrw\t{%2, %0|%0, %2}"
796 [(set_attr "type" "mmxmul")
797 (set_attr "mode" "DI")])
799 (define_expand "sse2_umulv1siv1di3"
800 [(set (match_operand:V1DI 0 "register_operand" "")
801 (mult:V1DI
802 (zero_extend:V1DI
803 (vec_select:V1SI
804 (match_operand:V2SI 1 "nonimmediate_operand" "")
805 (parallel [(const_int 0)])))
806 (zero_extend:V1DI
807 (vec_select:V1SI
808 (match_operand:V2SI 2 "nonimmediate_operand" "")
809 (parallel [(const_int 0)])))))]
810 "TARGET_SSE2"
811 "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
813 (define_insn "*sse2_umulv1siv1di3"
814 [(set (match_operand:V1DI 0 "register_operand" "=y")
815 (mult:V1DI
816 (zero_extend:V1DI
817 (vec_select:V1SI
818 (match_operand:V2SI 1 "nonimmediate_operand" "%0")
819 (parallel [(const_int 0)])))
820 (zero_extend:V1DI
821 (vec_select:V1SI
822 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
823 (parallel [(const_int 0)])))))]
824 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
825 "pmuludq\t{%2, %0|%0, %2}"
826 [(set_attr "type" "mmxmul")
827 (set_attr "mode" "DI")])
829 (define_expand "mmx_<code>v4hi3"
830 [(set (match_operand:V4HI 0 "register_operand" "")
831 (smaxmin:V4HI
832 (match_operand:V4HI 1 "nonimmediate_operand" "")
833 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
834 "TARGET_SSE || TARGET_3DNOW_A"
835 "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
837 (define_insn "*mmx_<code>v4hi3"
838 [(set (match_operand:V4HI 0 "register_operand" "=y")
839 (smaxmin:V4HI
840 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
841 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
842 "(TARGET_SSE || TARGET_3DNOW_A)
843 && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
844 "p<maxminiprefix>w\t{%2, %0|%0, %2}"
845 [(set_attr "type" "mmxadd")
846 (set_attr "mode" "DI")])
848 (define_expand "mmx_<code>v8qi3"
849 [(set (match_operand:V8QI 0 "register_operand" "")
850 (umaxmin:V8QI
851 (match_operand:V8QI 1 "nonimmediate_operand" "")
852 (match_operand:V8QI 2 "nonimmediate_operand" "")))]
853 "TARGET_SSE || TARGET_3DNOW_A"
854 "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
856 (define_insn "*mmx_<code>v8qi3"
857 [(set (match_operand:V8QI 0 "register_operand" "=y")
858 (umaxmin:V8QI
859 (match_operand:V8QI 1 "nonimmediate_operand" "%0")
860 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
861 "(TARGET_SSE || TARGET_3DNOW_A)
862 && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
863 "p<maxminiprefix>b\t{%2, %0|%0, %2}"
864 [(set_attr "type" "mmxadd")
865 (set_attr "mode" "DI")])
867 (define_insn "mmx_ashr<mode>3"
868 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
869 (ashiftrt:MMXMODE24
870 (match_operand:MMXMODE24 1 "register_operand" "0")
871 (match_operand:SI 2 "nonmemory_operand" "yN")))]
872 "TARGET_MMX"
873 "psra<mmxvecsize>\t{%2, %0|%0, %2}"
874 [(set_attr "type" "mmxshft")
875 (set_attr "mode" "DI")])
877 (define_insn "mmx_lshr<mode>3"
878 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
879 (lshiftrt:MMXMODE248
880 (match_operand:MMXMODE248 1 "register_operand" "0")
881 (match_operand:SI 2 "nonmemory_operand" "yN")))]
882 "TARGET_MMX"
883 "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
884 [(set_attr "type" "mmxshft")
885 (set_attr "mode" "DI")])
887 (define_insn "mmx_ashl<mode>3"
888 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
889 (ashift:MMXMODE248
890 (match_operand:MMXMODE248 1 "register_operand" "0")
891 (match_operand:SI 2 "nonmemory_operand" "yN")))]
892 "TARGET_MMX"
893 "psll<mmxvecsize>\t{%2, %0|%0, %2}"
894 [(set_attr "type" "mmxshft")
895 (set_attr "mode" "DI")])
897 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
898 ;;
899 ;; Parallel integral comparisons
900 ;;
901 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
903 (define_expand "mmx_eq<mode>3"
904 [(set (match_operand:MMXMODEI 0 "register_operand" "")
905 (eq:MMXMODEI
906 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
907 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
908 "TARGET_MMX"
909 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
911 (define_insn "*mmx_eq<mode>3"
912 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
913 (eq:MMXMODEI
914 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
915 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
916 "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
917 "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}"
918 [(set_attr "type" "mmxcmp")
919 (set_attr "mode" "DI")])
921 (define_insn "mmx_gt<mode>3"
922 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
923 (gt:MMXMODEI
924 (match_operand:MMXMODEI 1 "register_operand" "0")
925 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
926 "TARGET_MMX"
927 "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}"
928 [(set_attr "type" "mmxcmp")
929 (set_attr "mode" "DI")])
931 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
932 ;;
933 ;; Parallel integral logical operations
934 ;;
935 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
937 (define_insn "mmx_nand<mode>3"
938 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
939 (and:MMXMODEI
940 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
941 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
942 "TARGET_MMX"
943 "pandn\t{%2, %0|%0, %2}"
944 [(set_attr "type" "mmxadd")
945 (set_attr "mode" "DI")])
947 (define_expand "mmx_<code><mode>3"
948 [(set (match_operand:MMXMODEI 0 "register_operand" "")
949 (plogic:MMXMODEI
950 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
951 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
952 "TARGET_MMX"
953 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
955 (define_insn "*mmx_<code><mode>3"
956 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
957 (plogic:MMXMODEI
958 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
959 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
960 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
961 "p<plogicprefix>\t{%2, %0|%0, %2}"
962 [(set_attr "type" "mmxadd")
963 (set_attr "mode" "DI")])
965 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
966 ;;
967 ;; Parallel integral element swizzling
968 ;;
969 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
971 (define_insn "mmx_packsswb"
972 [(set (match_operand:V8QI 0 "register_operand" "=y")
973 (vec_concat:V8QI
974 (ss_truncate:V4QI
975 (match_operand:V4HI 1 "register_operand" "0"))
976 (ss_truncate:V4QI
977 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
978 "TARGET_MMX"
979 "packsswb\t{%2, %0|%0, %2}"
980 [(set_attr "type" "mmxshft")
981 (set_attr "mode" "DI")])
983 (define_insn "mmx_packssdw"
984 [(set (match_operand:V4HI 0 "register_operand" "=y")
985 (vec_concat:V4HI
986 (ss_truncate:V2HI
987 (match_operand:V2SI 1 "register_operand" "0"))
988 (ss_truncate:V2HI
989 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))]
990 "TARGET_MMX"
991 "packssdw\t{%2, %0|%0, %2}"
992 [(set_attr "type" "mmxshft")
993 (set_attr "mode" "DI")])
995 (define_insn "mmx_packuswb"
996 [(set (match_operand:V8QI 0 "register_operand" "=y")
997 (vec_concat:V8QI
998 (us_truncate:V4QI
999 (match_operand:V4HI 1 "register_operand" "0"))
1000 (us_truncate:V4QI
1001 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1002 "TARGET_MMX"
1003 "packuswb\t{%2, %0|%0, %2}"
1004 [(set_attr "type" "mmxshft")
1005 (set_attr "mode" "DI")])
1007 (define_insn "mmx_punpckhbw"
1008 [(set (match_operand:V8QI 0 "register_operand" "=y")
1009 (vec_select:V8QI
1010 (vec_concat:V16QI
1011 (match_operand:V8QI 1 "register_operand" "0")
1012 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1013 (parallel [(const_int 4) (const_int 12)
1014 (const_int 5) (const_int 13)
1015 (const_int 6) (const_int 14)
1016 (const_int 7) (const_int 15)])))]
1017 "TARGET_MMX"
1018 "punpckhbw\t{%2, %0|%0, %2}"
1019 [(set_attr "type" "mmxcvt")
1020 (set_attr "mode" "DI")])
1022 (define_insn "mmx_punpcklbw"
1023 [(set (match_operand:V8QI 0 "register_operand" "=y")
1024 (vec_select:V8QI
1025 (vec_concat:V16QI
1026 (match_operand:V8QI 1 "register_operand" "0")
1027 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1028 (parallel [(const_int 0) (const_int 8)
1029 (const_int 1) (const_int 9)
1030 (const_int 2) (const_int 10)
1031 (const_int 3) (const_int 11)])))]
1032 "TARGET_MMX"
1033 "punpcklbw\t{%2, %0|%0, %2}"
1034 [(set_attr "type" "mmxcvt")
1035 (set_attr "mode" "DI")])
1037 (define_insn "mmx_punpckhwd"
1038 [(set (match_operand:V4HI 0 "register_operand" "=y")
1039 (vec_select:V4HI
1040 (vec_concat:V8HI
1041 (match_operand:V4HI 1 "register_operand" "0")
1042 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1043 (parallel [(const_int 2) (const_int 6)
1044 (const_int 3) (const_int 7)])))]
1045 "TARGET_MMX"
1046 "punpckhwd\t{%2, %0|%0, %2}"
1047 [(set_attr "type" "mmxcvt")
1048 (set_attr "mode" "DI")])
1050 (define_insn "mmx_punpcklwd"
1051 [(set (match_operand:V4HI 0 "register_operand" "=y")
1052 (vec_select:V4HI
1053 (vec_concat:V8HI
1054 (match_operand:V4HI 1 "register_operand" "0")
1055 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1056 (parallel [(const_int 0) (const_int 4)
1057 (const_int 1) (const_int 5)])))]
1058 "TARGET_MMX"
1059 "punpcklwd\t{%2, %0|%0, %2}"
1060 [(set_attr "type" "mmxcvt")
1061 (set_attr "mode" "DI")])
1063 (define_insn "mmx_punpckhdq"
1064 [(set (match_operand:V2SI 0 "register_operand" "=y")
1065 (vec_select:V2SI
1066 (vec_concat:V4SI
1067 (match_operand:V2SI 1 "register_operand" "0")
1068 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1069 (parallel [(const_int 1)
1070 (const_int 3)])))]
1071 "TARGET_MMX"
1072 "punpckhdq\t{%2, %0|%0, %2}"
1073 [(set_attr "type" "mmxcvt")
1074 (set_attr "mode" "DI")])
1076 (define_insn "mmx_punpckldq"
1077 [(set (match_operand:V2SI 0 "register_operand" "=y")
1078 (vec_select:V2SI
1079 (vec_concat:V4SI
1080 (match_operand:V2SI 1 "register_operand" "0")
1081 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1082 (parallel [(const_int 0)
1083 (const_int 2)])))]
1084 "TARGET_MMX"
1085 "punpckldq\t{%2, %0|%0, %2}"
1086 [(set_attr "type" "mmxcvt")
1087 (set_attr "mode" "DI")])
1089 (define_expand "mmx_pinsrw"
1090 [(set (match_operand:V4HI 0 "register_operand" "")
1091 (vec_merge:V4HI
1092 (vec_duplicate:V4HI
1093 (match_operand:SI 2 "nonimmediate_operand" ""))
1094 (match_operand:V4HI 1 "register_operand" "")
1095 (match_operand:SI 3 "const_0_to_3_operand" "")))]
1096 "TARGET_SSE || TARGET_3DNOW_A"
1097 {
1098 operands[2] = gen_lowpart (HImode, operands[2]);
1099 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
1100 })
1102 (define_insn "*mmx_pinsrw"
1103 [(set (match_operand:V4HI 0 "register_operand" "=y")
1104 (vec_merge:V4HI
1105 (vec_duplicate:V4HI
1106 (match_operand:HI 2 "nonimmediate_operand" "rm"))
1107 (match_operand:V4HI 1 "register_operand" "0")
1108 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
1109 "TARGET_SSE || TARGET_3DNOW_A"
1110 {
1111 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
1112 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
1113 }
1114 [(set_attr "type" "mmxcvt")
1115 (set_attr "mode" "DI")])
1117 (define_insn "mmx_pextrw"
1118 [(set (match_operand:SI 0 "register_operand" "=r")
1119 (zero_extend:SI
1120 (vec_select:HI
1121 (match_operand:V4HI 1 "register_operand" "y")
1122 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
1123 "TARGET_SSE || TARGET_3DNOW_A"
1124 "pextrw\t{%2, %1, %0|%0, %1, %2}"
1125 [(set_attr "type" "mmxcvt")
1126 (set_attr "mode" "DI")])
1128 (define_expand "mmx_pshufw"
1129 [(match_operand:V4HI 0 "register_operand" "")
1130 (match_operand:V4HI 1 "nonimmediate_operand" "")
1131 (match_operand:SI 2 "const_int_operand" "")]
1132 "TARGET_SSE || TARGET_3DNOW_A"
1133 {
1134 int mask = INTVAL (operands[2]);
1135 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
1136 GEN_INT ((mask >> 0) & 3),
1137 GEN_INT ((mask >> 2) & 3),
1138 GEN_INT ((mask >> 4) & 3),
1139 GEN_INT ((mask >> 6) & 3)));
1140 DONE;
1141 })
1143 (define_insn "mmx_pshufw_1"
1144 [(set (match_operand:V4HI 0 "register_operand" "=y")
1145 (vec_select:V4HI
1146 (match_operand:V4HI 1 "nonimmediate_operand" "ym")
1147 (parallel [(match_operand 2 "const_0_to_3_operand" "")
1148 (match_operand 3 "const_0_to_3_operand" "")
1149 (match_operand 4 "const_0_to_3_operand" "")
1150 (match_operand 5 "const_0_to_3_operand" "")])))]
1151 "TARGET_SSE || TARGET_3DNOW_A"
1152 {
1153 int mask = 0;
1154 mask |= INTVAL (operands[2]) << 0;
1155 mask |= INTVAL (operands[3]) << 2;
1156 mask |= INTVAL (operands[4]) << 4;
1157 mask |= INTVAL (operands[5]) << 6;
1158 operands[2] = GEN_INT (mask);
1160 return "pshufw\t{%2, %1, %0|%0, %1, %2}";
1161 }
1162 [(set_attr "type" "mmxcvt")
1163 (set_attr "mode" "DI")])
1165 (define_insn "mmx_pswapdv2si2"
1166 [(set (match_operand:V2SI 0 "register_operand" "=y")
1167 (vec_select:V2SI
1168 (match_operand:V2SI 1 "nonimmediate_operand" "ym")
1169 (parallel [(const_int 1) (const_int 0)])))]
1170 "TARGET_3DNOW_A"
1171 "pswapd\t{%1, %0|%0, %1}"
1172 [(set_attr "type" "mmxcvt")
1173 (set_attr "mode" "DI")])
1175 (define_insn "*vec_dupv4hi"
1176 [(set (match_operand:V4HI 0 "register_operand" "=y")
1177 (vec_duplicate:V4HI
1178 (truncate:HI
1179 (match_operand:SI 1 "register_operand" "0"))))]
1180 "TARGET_SSE || TARGET_3DNOW_A"
1181 "pshufw\t{$0, %0, %0|%0, %0, 0}"
1182 [(set_attr "type" "mmxcvt")
1183 (set_attr "mode" "DI")])
1185 (define_insn "*vec_dupv2si"
1186 [(set (match_operand:V2SI 0 "register_operand" "=y")
1187 (vec_duplicate:V2SI
1188 (match_operand:SI 1 "register_operand" "0")))]
1189 "TARGET_MMX"
1190 "punpckldq\t%0, %0"
1191 [(set_attr "type" "mmxcvt")
1192 (set_attr "mode" "DI")])
1194 (define_insn "*mmx_concatv2si"
1195 [(set (match_operand:V2SI 0 "register_operand" "=y,y")
1196 (vec_concat:V2SI
1197 (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
1198 (match_operand:SI 2 "vector_move_operand" "ym,C")))]
1199 "TARGET_MMX && !TARGET_SSE"
1200 "@
1201 punpckldq\t{%2, %0|%0, %2}
1202 movd\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "mmxcvt,mmxmov")
1204 (set_attr "mode" "DI")])
1206 (define_expand "vec_setv2si"
1207 [(match_operand:V2SI 0 "register_operand" "")
1208 (match_operand:SI 1 "register_operand" "")
1209 (match_operand 2 "const_int_operand" "")]
1210 "TARGET_MMX"
1211 {
1212 ix86_expand_vector_set (false, operands[0], operands[1],
1213 INTVAL (operands[2]));
1214 DONE;
1215 })
1217 (define_insn_and_split "*vec_extractv2si_0"
1218 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y,m,m,frxy")
1219 (vec_select:SI
1220 (match_operand:V2SI 1 "nonimmediate_operand" " x,y,x,y,m")
1221 (parallel [(const_int 0)])))]
1222 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1223 "#"
1224 "&& reload_completed"
1225 [(const_int 0)]
1226 {
1227 rtx op1 = operands[1];
1228 if (REG_P (op1))
1229 op1 = gen_rtx_REG (SImode, REGNO (op1));
1230 else
1231 op1 = gen_lowpart (SImode, op1);
1232 emit_move_insn (operands[0], op1);
1233 DONE;
1234 })
1236 (define_insn "*vec_extractv2si_1"
1237 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,frxy")
1238 (vec_select:SI
1239 (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o")
1240 (parallel [(const_int 1)])))]
1241 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1242 "@
1243 punpckhdq\t%0, %0
1244 punpckhdq\t%0, %0
1245 pshufd\t{$85, %1, %0|%0, %1, 85}
1246 unpckhps\t%0, %0
1247 #"
1248 [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,*")
1249 (set_attr "mode" "DI,TI,TI,V4SF,SI")])
1251 (define_split
1252 [(set (match_operand:SI 0 "register_operand" "")
1253 (vec_select:SI
1254 (match_operand:V2SI 1 "memory_operand" "")
1255 (parallel [(const_int 1)])))]
1256 "TARGET_MMX && reload_completed"
1257 [(const_int 0)]
1258 {
1259 operands[1] = adjust_address (operands[1], SImode, 4);
1260 emit_move_insn (operands[0], operands[1]);
1261 DONE;
1262 })
1264 (define_expand "vec_extractv2si"
1265 [(match_operand:SI 0 "register_operand" "")
1266 (match_operand:V2SI 1 "register_operand" "")
1267 (match_operand 2 "const_int_operand" "")]
1268 "TARGET_MMX"
1269 {
1270 ix86_expand_vector_extract (false, operands[0], operands[1],
1271 INTVAL (operands[2]));
1272 DONE;
1273 })
1275 (define_expand "vec_initv2si"
1276 [(match_operand:V2SI 0 "register_operand" "")
1277 (match_operand 1 "" "")]
1278 "TARGET_SSE"
1279 {
1280 ix86_expand_vector_init (false, operands[0], operands[1]);
1281 DONE;
1282 })
1284 (define_expand "vec_setv4hi"
1285 [(match_operand:V4HI 0 "register_operand" "")
1286 (match_operand:HI 1 "register_operand" "")
1287 (match_operand 2 "const_int_operand" "")]
1288 "TARGET_MMX"
1289 {
1290 ix86_expand_vector_set (false, operands[0], operands[1],
1291 INTVAL (operands[2]));
1292 DONE;
1293 })
1295 (define_expand "vec_extractv4hi"
1296 [(match_operand:HI 0 "register_operand" "")
1297 (match_operand:V4HI 1 "register_operand" "")
1298 (match_operand 2 "const_int_operand" "")]
1299 "TARGET_MMX"
1300 {
1301 ix86_expand_vector_extract (false, operands[0], operands[1],
1302 INTVAL (operands[2]));
1303 DONE;
1304 })
1306 (define_expand "vec_initv4hi"
1307 [(match_operand:V4HI 0 "register_operand" "")
1308 (match_operand 1 "" "")]
1309 "TARGET_SSE"
1310 {
1311 ix86_expand_vector_init (false, operands[0], operands[1]);
1312 DONE;
1313 })
1315 (define_expand "vec_setv8qi"
1316 [(match_operand:V8QI 0 "register_operand" "")
1317 (match_operand:QI 1 "register_operand" "")
1318 (match_operand 2 "const_int_operand" "")]
1319 "TARGET_MMX"
1320 {
1321 ix86_expand_vector_set (false, operands[0], operands[1],
1322 INTVAL (operands[2]));
1323 DONE;
1324 })
1326 (define_expand "vec_extractv8qi"
1327 [(match_operand:QI 0 "register_operand" "")
1328 (match_operand:V8QI 1 "register_operand" "")
1329 (match_operand 2 "const_int_operand" "")]
1330 "TARGET_MMX"
1331 {
1332 ix86_expand_vector_extract (false, operands[0], operands[1],
1333 INTVAL (operands[2]));
1334 DONE;
1335 })
1337 (define_expand "vec_initv8qi"
1338 [(match_operand:V8QI 0 "register_operand" "")
1339 (match_operand 1 "" "")]
1340 "TARGET_SSE"
1341 {
1342 ix86_expand_vector_init (false, operands[0], operands[1]);
1343 DONE;
1344 })
1346 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1347 ;;
1348 ;; Miscellaneous
1349 ;;
1350 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1352 (define_expand "mmx_uavgv8qi3"
1353 [(set (match_operand:V8QI 0 "register_operand" "")
1354 (truncate:V8QI
1355 (lshiftrt:V8HI
1356 (plus:V8HI
1357 (plus:V8HI
1358 (zero_extend:V8HI
1359 (match_operand:V8QI 1 "nonimmediate_operand" ""))
1360 (zero_extend:V8HI
1361 (match_operand:V8QI 2 "nonimmediate_operand" "")))
1362 (const_vector:V8HI [(const_int 1) (const_int 1)
1363 (const_int 1) (const_int 1)
1364 (const_int 1) (const_int 1)
1365 (const_int 1) (const_int 1)]))
1366 (const_int 1))))]
1367 "TARGET_SSE || TARGET_3DNOW"
1368 "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
1370 (define_insn "*mmx_uavgv8qi3"
1371 [(set (match_operand:V8QI 0 "register_operand" "=y")
1372 (truncate:V8QI
1373 (lshiftrt:V8HI
1374 (plus:V8HI
1375 (plus:V8HI
1376 (zero_extend:V8HI
1377 (match_operand:V8QI 1 "nonimmediate_operand" "%0"))
1378 (zero_extend:V8HI
1379 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))
1380 (const_vector:V8HI [(const_int 1) (const_int 1)
1381 (const_int 1) (const_int 1)
1382 (const_int 1) (const_int 1)
1383 (const_int 1) (const_int 1)]))
1384 (const_int 1))))]
1385 "(TARGET_SSE || TARGET_3DNOW)
1386 && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
1387 {
1388 /* These two instructions have the same operation, but their encoding
1389 is different. Prefer the one that is de facto standard. */
1390 if (TARGET_SSE || TARGET_3DNOW_A)
1391 return "pavgb\t{%2, %0|%0, %2}";
1392 else
1393 return "pavgusb\t{%2, %0|%0, %2}";
1394 }
1395 [(set_attr "type" "mmxshft")
1396 (set_attr "mode" "DI")])
1398 (define_expand "mmx_uavgv4hi3"
1399 [(set (match_operand:V4HI 0 "register_operand" "")
1400 (truncate:V4HI
1401 (lshiftrt:V4SI
1402 (plus:V4SI
1403 (plus:V4SI
1404 (zero_extend:V4SI
1405 (match_operand:V4HI 1 "nonimmediate_operand" ""))
1406 (zero_extend:V4SI
1407 (match_operand:V4HI 2 "nonimmediate_operand" "")))
1408 (const_vector:V4SI [(const_int 1) (const_int 1)
1409 (const_int 1) (const_int 1)]))
1410 (const_int 1))))]
1411 "TARGET_SSE || TARGET_3DNOW_A"
1412 "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
1414 (define_insn "*mmx_uavgv4hi3"
1415 [(set (match_operand:V4HI 0 "register_operand" "=y")
1416 (truncate:V4HI
1417 (lshiftrt:V4SI
1418 (plus:V4SI
1419 (plus:V4SI
1420 (zero_extend:V4SI
1421 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
1422 (zero_extend:V4SI
1423 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
1424 (const_vector:V4SI [(const_int 1) (const_int 1)
1425 (const_int 1) (const_int 1)]))
1426 (const_int 1))))]
1427 "(TARGET_SSE || TARGET_3DNOW_A)
1428 && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
1429 "pavgw\t{%2, %0|%0, %2}"
1430 [(set_attr "type" "mmxshft")
1431 (set_attr "mode" "DI")])
1433 (define_insn "mmx_psadbw"
1434 [(set (match_operand:V1DI 0 "register_operand" "=y")
1435 (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0")
1436 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
1437 UNSPEC_PSADBW))]
1438 "TARGET_SSE || TARGET_3DNOW_A"
1439 "psadbw\t{%2, %0|%0, %2}"
1440 [(set_attr "type" "mmxshft")
1441 (set_attr "mode" "DI")])
1443 (define_insn "mmx_pmovmskb"
1444 [(set (match_operand:SI 0 "register_operand" "=r")
1445 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
1446 UNSPEC_MOVMSK))]
1447 "TARGET_SSE || TARGET_3DNOW_A"
1448 "pmovmskb\t{%1, %0|%0, %1}"
1449 [(set_attr "type" "mmxcvt")
1450 (set_attr "mode" "DI")])
1452 (define_expand "mmx_maskmovq"
1453 [(set (match_operand:V8QI 0 "memory_operand" "")
1454 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
1455 (match_operand:V8QI 2 "register_operand" "")
1456 (match_dup 0)]
1457 UNSPEC_MASKMOV))]
1458 "TARGET_SSE || TARGET_3DNOW_A"
1459 "")
1461 (define_insn "*mmx_maskmovq"
1462 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
1463 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1464 (match_operand:V8QI 2 "register_operand" "y")
1465 (mem:V8QI (match_dup 0))]
1466 UNSPEC_MASKMOV))]
1467 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
1468 ;; @@@ check ordering of operands in intel/nonintel syntax
1469 "maskmovq\t{%2, %1|%1, %2}"
1470 [(set_attr "type" "mmxcvt")
1471 (set_attr "mode" "DI")])
1473 (define_insn "*mmx_maskmovq_rex"
1474 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
1475 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1476 (match_operand:V8QI 2 "register_operand" "y")
1477 (mem:V8QI (match_dup 0))]
1478 UNSPEC_MASKMOV))]
1479 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
1480 ;; @@@ check ordering of operands in intel/nonintel syntax
1481 "maskmovq\t{%2, %1|%1, %2}"
1482 [(set_attr "type" "mmxcvt")
1483 (set_attr "mode" "DI")])
1485 (define_insn "mmx_emms"
1486 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
1487 (clobber (reg:XF 8))
1488 (clobber (reg:XF 9))
1489 (clobber (reg:XF 10))
1490 (clobber (reg:XF 11))
1491 (clobber (reg:XF 12))
1492 (clobber (reg:XF 13))
1493 (clobber (reg:XF 14))
1494 (clobber (reg:XF 15))
1495 (clobber (reg:DI 29))
1496 (clobber (reg:DI 30))
1497 (clobber (reg:DI 31))
1498 (clobber (reg:DI 32))
1499 (clobber (reg:DI 33))
1500 (clobber (reg:DI 34))
1501 (clobber (reg:DI 35))
1502 (clobber (reg:DI 36))]
1503 "TARGET_MMX"
1504 "emms"
1505 [(set_attr "type" "mmx")
1506 (set_attr "memory" "unknown")])
1508 (define_insn "mmx_femms"
1509 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
1510 (clobber (reg:XF 8))
1511 (clobber (reg:XF 9))
1512 (clobber (reg:XF 10))
1513 (clobber (reg:XF 11))
1514 (clobber (reg:XF 12))
1515 (clobber (reg:XF 13))
1516 (clobber (reg:XF 14))
1517 (clobber (reg:XF 15))
1518 (clobber (reg:DI 29))
1519 (clobber (reg:DI 30))
1520 (clobber (reg:DI 31))
1521 (clobber (reg:DI 32))
1522 (clobber (reg:DI 33))
1523 (clobber (reg:DI 34))
1524 (clobber (reg:DI 35))
1525 (clobber (reg:DI 36))]
1526 "TARGET_3DNOW"
1527 "femms"
1528 [(set_attr "type" "mmx")
1529 (set_attr "memory" "none")])