gcc/config/s390/s390.h

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   5                   Ulrich Weigand (uweigand@de.ibm.com).
   6                   Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   7
   8 This file is part of GCC.
   9
  10 GCC is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free
  12 Software Foundation; either version 3, or (at your option) any later
  13 version.
  14
  15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18 for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with GCC; see the file COPYING3.  If not see
  22 <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef _S390_H
  25 #define _S390_H
  26
  27 /* Which processor to generate code or schedule for. The cpu attribute
  28    defines a list that mirrors this list, so changes to s390.md must be
  29    made at the same time.  */
  30
  31 enum processor_type
  32 {
  33   PROCESSOR_9672_G5,
  34   PROCESSOR_9672_G6,
  35   PROCESSOR_2064_Z900,
  36   PROCESSOR_2084_Z990,
  37   PROCESSOR_2094_Z9_109,
  38   PROCESSOR_2097_Z10,
  39   PROCESSOR_2817_Z196,
  40   PROCESSOR_max
  41 };
  42
  43 /* Optional architectural facilities supported by the processor.  */
  44
  45 enum processor_flags
  46 {
  47   PF_IEEE_FLOAT = 1,
  48   PF_ZARCH = 2,
  49   PF_LONG_DISPLACEMENT = 4,
  50   PF_EXTIMM = 8,
  51   PF_DFP = 16,
  52   PF_Z10 = 32,
  53   PF_Z196 = 64
  54 };
  55
  56 extern enum processor_type s390_tune;
  57 extern int s390_tune_flags;
  58
  59 /* This is necessary to avoid a warning about comparing different enum
  60    types.  */
  61 #define s390_tune_attr ((enum attr_cpu)s390_tune)
  62
  63 extern enum processor_type s390_arch;
  64 extern int s390_arch_flags;
  65
  66 /* These flags indicate that the generated code should run on a cpu
  67    providing the respective hardware facility regardless of the
  68    current cpu mode (ESA or z/Architecture).  */
  69
  70 #define TARGET_CPU_IEEE_FLOAT \
  71         (s390_arch_flags & PF_IEEE_FLOAT)
  72 #define TARGET_CPU_ZARCH \
  73         (s390_arch_flags & PF_ZARCH)
  74 #define TARGET_CPU_LONG_DISPLACEMENT \
  75         (s390_arch_flags & PF_LONG_DISPLACEMENT)
  76 #define TARGET_CPU_EXTIMM \
  77         (s390_arch_flags & PF_EXTIMM)
  78 #define TARGET_CPU_DFP \
  79         (s390_arch_flags & PF_DFP)
  80 #define TARGET_CPU_Z10 \
  81         (s390_arch_flags & PF_Z10)
  82 #define TARGET_CPU_Z196 \
  83         (s390_arch_flags & PF_Z196)
  84
  85 /* These flags indicate that the generated code should run on a cpu
  86    providing the respective hardware facility when run in
  87    z/Architecture mode.  */
  88
  89 #define TARGET_LONG_DISPLACEMENT \
  90        (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
  91 #define TARGET_EXTIMM \
  92        (TARGET_ZARCH && TARGET_CPU_EXTIMM)
  93 #define TARGET_DFP \
  94        (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
  95 #define TARGET_Z10 \
  96        (TARGET_ZARCH && TARGET_CPU_Z10)
  97 #define TARGET_Z196 \
  98        (TARGET_ZARCH && TARGET_CPU_Z196)
  99
 100
 101 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
 102
 103 /* Run-time target specification.  */
 104
 105 /* Defaults for option flags defined only on some subtargets.  */
 106 #ifndef TARGET_TPF_PROFILING
 107 #define TARGET_TPF_PROFILING 0
 108 #endif
 109
 110 /* This will be overridden by OS headers.  */
 111 #define TARGET_TPF 0
 112
 113 /* Target CPU builtins.  */
 114 #define TARGET_CPU_CPP_BUILTINS()                       \
 115   do                                                    \
 116     {                                                   \
 117       builtin_assert ("cpu=s390");                      \
 118       builtin_assert ("machine=s390");                  \
 119       builtin_define ("__s390__");                      \
 120       if (TARGET_ZARCH)                                 \
 121         builtin_define ("__zarch__");                   \
 122       if (TARGET_64BIT)                                 \
 123         builtin_define ("__s390x__");                   \
 124       if (TARGET_LONG_DOUBLE_128)                       \
 125         builtin_define ("__LONG_DOUBLE_128__");         \
 126     }                                                   \
 127   while (0)
 128
 129 #ifdef DEFAULT_TARGET_64BIT
 130 #define TARGET_DEFAULT             (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP)
 131 #else
 132 #define TARGET_DEFAULT             0
 133 #endif
 134
 135 /* Support for configure-time defaults.  */
 136 #define OPTION_DEFAULT_SPECS                                    \
 137   { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" },                 \
 138   { "arch", "%{!march=*:-march=%(VALUE)}" },                    \
 139   { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
 140
 141 /* Defaulting rules.  */
 142 #ifdef DEFAULT_TARGET_64BIT
 143 #define DRIVER_SELF_SPECS                                       \
 144   "%{!m31:%{!m64:-m64}}",                                       \
 145   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 146   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 147 #else
 148 #define DRIVER_SELF_SPECS                                       \
 149   "%{!m31:%{!m64:-m31}}",                                       \
 150   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
 151   "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
 152 #endif
 153
 154 /* Target version string.  Overridden by the OS header.  */
 155 #ifdef DEFAULT_TARGET_64BIT
 156 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
 157 #else
 158 #define TARGET_VERSION fprintf (stderr, " (S/390)");
 159 #endif
 160
 161 /* Constants needed to control the TEST DATA CLASS (TDC) instruction.  */
 162 #define S390_TDC_POSITIVE_ZERO                     (1 << 11)
 163 #define S390_TDC_NEGATIVE_ZERO                     (1 << 10)
 164 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER    (1 << 9)
 165 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER    (1 << 8)
 166 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER  (1 << 7)
 167 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER  (1 << 6)
 168 #define S390_TDC_POSITIVE_INFINITY                 (1 << 5)
 169 #define S390_TDC_NEGATIVE_INFINITY                 (1 << 4)
 170 #define S390_TDC_POSITIVE_QUIET_NAN                (1 << 3)
 171 #define S390_TDC_NEGATIVE_QUIET_NAN                (1 << 2)
 172 #define S390_TDC_POSITIVE_SIGNALING_NAN            (1 << 1)
 173 #define S390_TDC_NEGATIVE_SIGNALING_NAN            (1 << 0)
 174
 175 /* The following values are different for DFP.  */
 176 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
 177 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
 178 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER   (1 << 7)
 179 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER   (1 << 6)
 180
 181 /* For signbit, the BFP-DFP-difference makes no difference. */
 182 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
 183                           | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
 184                           | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
 185                           | S390_TDC_NEGATIVE_INFINITY \
 186                           | S390_TDC_NEGATIVE_QUIET_NAN \
 187                           | S390_TDC_NEGATIVE_SIGNALING_NAN )
 188
 189 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
 190                           | S390_TDC_NEGATIVE_INFINITY )
 191
 192 /* Target machine storage layout.  */
 193
 194 /* Everything is big-endian.  */
 195 #define BITS_BIG_ENDIAN 1
 196 #define BYTES_BIG_ENDIAN 1
 197 #define WORDS_BIG_ENDIAN 1
 198
 199 #define STACK_SIZE_MODE (Pmode)
 200
 201 #ifndef IN_LIBGCC2
 202
 203 /* Width of a word, in units (bytes).  */
 204   #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
 205
 206 /* Width of a pointer.  To be used instead of UNITS_PER_WORD in
 207    ABI-relevant contexts.  This always matches
 208    GET_MODE_SIZE (Pmode).  */
 209   #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
 210   #define MIN_UNITS_PER_WORD 4
 211   #define MAX_BITS_PER_WORD 64
 212 #else
 213
 214   /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
 215      the library should export TImode functions or not.  Thus, we have
 216      to redefine UNITS_PER_WORD depending on __s390x__ for libgcc.  */
 217   #ifdef __s390x__
 218     #define UNITS_PER_WORD 8
 219   #else
 220     #define UNITS_PER_WORD 4
 221   #endif
 222 #endif
 223
 224 /* Width of a pointer, in bits.  */
 225 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
 226
 227 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 228 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
 229
 230 /* Boundary (in *bits*) on which stack pointer should be aligned.  */
 231 #define STACK_BOUNDARY 64
 232
 233 /* Allocation boundary (in *bits*) for the code of a function.  */
 234 #define FUNCTION_BOUNDARY 32
 235
 236 /* There is no point aligning anything to a rounder boundary than this.  */
 237 #define BIGGEST_ALIGNMENT 64
 238
 239 /* Alignment of field after `int : 0' in a structure.  */
 240 #define EMPTY_FIELD_BOUNDARY 32
 241
 242 /* Alignment on even addresses for LARL instruction.  */
 243 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 244 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
 245
 246 /* Alignment is not required by the hardware.  */
 247 #define STRICT_ALIGNMENT 0
 248
 249 /* Mode of stack savearea.
 250    FUNCTION is VOIDmode because calling convention maintains SP.
 251    BLOCK needs Pmode for SP.
 252    NONLOCAL needs twice Pmode to maintain both backchain and SP.  */
 253 #define STACK_SAVEAREA_MODE(LEVEL)      \
 254   (LEVEL == SAVE_FUNCTION ? VOIDmode    \
 255   : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
 256
 257
 258 /* Type layout.  */
 259
 260 /* Sizes in bits of the source language data types.  */
 261 #define SHORT_TYPE_SIZE 16
 262 #define INT_TYPE_SIZE 32
 263 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
 264 #define LONG_LONG_TYPE_SIZE 64
 265 #define FLOAT_TYPE_SIZE 32
 266 #define DOUBLE_TYPE_SIZE 64
 267 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
 268
 269 /* Define this to set long double type size to use in libgcc2.c, which can
 270    not depend on target_flags.  */
 271 #ifdef __LONG_DOUBLE_128__
 272 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
 273 #else
 274 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
 275 #endif
 276
 277 /* Work around target_flags dependency in ada/targtyps.c.  */
 278 #define WIDEST_HARDWARE_FP_SIZE 64
 279
 280 /* We use "unsigned char" as default.  */
 281 #define DEFAULT_SIGNED_CHAR 0
 282
 283
 284 /* Register usage.  */
 285
 286 /* We have 16 general purpose registers (registers 0-15),
 287    and 16 floating point registers (registers 16-31).
 288    (On non-IEEE machines, we have only 4 fp registers.)
 289
 290    Amongst the general purpose registers, some are used
 291    for specific purposes:
 292    GPR 11: Hard frame pointer (if needed)
 293    GPR 12: Global offset table pointer (if needed)
 294    GPR 13: Literal pool base register
 295    GPR 14: Return address register
 296    GPR 15: Stack pointer
 297
 298    Registers 32-35 are 'fake' hard registers that do not
 299    correspond to actual hardware:
 300    Reg 32: Argument pointer
 301    Reg 33: Condition code
 302    Reg 34: Frame pointer
 303    Reg 35: Return address pointer
 304
 305    Registers 36 and 37 are mapped to access registers
 306    0 and 1, used to implement thread-local storage.  */
 307
 308 #define FIRST_PSEUDO_REGISTER 38
 309
 310 /* Standard register usage.  */
 311 #define GENERAL_REGNO_P(N)      ((int)(N) >= 0 && (N) < 16)
 312 #define ADDR_REGNO_P(N)         ((N) >= 1 && (N) < 16)
 313 #define FP_REGNO_P(N)           ((N) >= 16 && (N) < 32)
 314 #define CC_REGNO_P(N)           ((N) == 33)
 315 #define FRAME_REGNO_P(N)        ((N) == 32 || (N) == 34 || (N) == 35)
 316 #define ACCESS_REGNO_P(N)       ((N) == 36 || (N) == 37)
 317
 318 #define GENERAL_REG_P(X)        (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
 319 #define ADDR_REG_P(X)           (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
 320 #define FP_REG_P(X)             (REG_P (X) && FP_REGNO_P (REGNO (X)))
 321 #define CC_REG_P(X)             (REG_P (X) && CC_REGNO_P (REGNO (X)))
 322 #define FRAME_REG_P(X)          (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
 323 #define ACCESS_REG_P(X)         (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
 324
 325 /* Set up fixed registers and calling convention:
 326
 327    GPRs 0-5 are always call-clobbered,
 328    GPRs 6-15 are always call-saved.
 329    GPR 12 is fixed if used as GOT pointer.
 330    GPR 13 is always fixed (as literal pool pointer).
 331    GPR 14 is always fixed on S/390 machines (as return address).
 332    GPR 15 is always fixed (as stack pointer).
 333    The 'fake' hard registers are call-clobbered and fixed.
 334    The access registers are call-saved and fixed.
 335
 336    On 31-bit, FPRs 18-19 are call-clobbered;
 337    on 64-bit, FPRs 24-31 are call-clobbered.
 338    The remaining FPRs are call-saved.  */
 339
 340 #define FIXED_REGISTERS                         \
 341 { 0, 0, 0, 0,                                   \
 342   0, 0, 0, 0,                                   \
 343   0, 0, 0, 0,                                   \
 344   0, 1, 1, 1,                                   \
 345   0, 0, 0, 0,                                   \
 346   0, 0, 0, 0,                                   \
 347   0, 0, 0, 0,                                   \
 348   0, 0, 0, 0,                                   \
 349   1, 1, 1, 1,                                   \
 350   1, 1 }
 351
 352 #define CALL_USED_REGISTERS                     \
 353 { 1, 1, 1, 1,                                   \
 354   1, 1, 0, 0,                                   \
 355   0, 0, 0, 0,                                   \
 356   0, 1, 1, 1,                                   \
 357   1, 1, 1, 1,                                   \
 358   1, 1, 1, 1,                                   \
 359   1, 1, 1, 1,                                   \
 360   1, 1, 1, 1,                                   \
 361   1, 1, 1, 1,                                   \
 362   1, 1 }
 363
 364 #define CALL_REALLY_USED_REGISTERS              \
 365 { 1, 1, 1, 1,                                   \
 366   1, 1, 0, 0,                                   \
 367   0, 0, 0, 0,                                   \
 368   0, 0, 0, 0,                                   \
 369   1, 1, 1, 1,                                   \
 370   1, 1, 1, 1,                                   \
 371   1, 1, 1, 1,                                   \
 372   1, 1, 1, 1,                                   \
 373   1, 1, 1, 1,                                   \
 374   0, 0 }
 375
 376 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage ()
 377
 378 /* Preferred register allocation order.  */
 379 #define REG_ALLOC_ORDER                                         \
 380 {  1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13,            \
 381    16, 17, 18, 19, 20, 21, 22, 23,                              \
 382    24, 25, 26, 27, 28, 29, 30, 31,                              \
 383    15, 32, 33, 34, 35, 36, 37 }
 384
 385
 386 /* Fitting values into registers.  */
 387
 388 /* Integer modes <= word size fit into any GPR.
 389    Integer modes > word size fit into successive GPRs, starting with
 390    an even-numbered register.
 391    SImode and DImode fit into FPRs as well.
 392
 393    Floating point modes <= word size fit into any FPR or GPR.
 394    Floating point modes > word size (i.e. DFmode on 32-bit) fit
 395    into any FPR, or an even-odd GPR pair.
 396    TFmode fits only into an even-odd FPR pair.
 397
 398    Complex floating point modes fit either into two FPRs, or into
 399    successive GPRs (again starting with an even number).
 400    TCmode fits only into two successive even-odd FPR pairs.
 401
 402    Condition code modes fit only into the CC register.  */
 403
 404 /* Because all registers in a class have the same size HARD_REGNO_NREGS
 405    is equivalent to CLASS_MAX_NREGS.  */
 406 #define HARD_REGNO_NREGS(REGNO, MODE)                           \
 407   s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
 408
 409 #define HARD_REGNO_MODE_OK(REGNO, MODE)         \
 410   s390_hard_regno_mode_ok ((REGNO), (MODE))
 411
 412 #define HARD_REGNO_RENAME_OK(FROM, TO)          \
 413   s390_hard_regno_rename_ok (FROM, TO)
 414
 415 #define MODES_TIEABLE_P(MODE1, MODE2)           \
 416    (((MODE1) == SFmode || (MODE1) == DFmode)    \
 417    == ((MODE2) == SFmode || (MODE2) == DFmode))
 418
 419 /* When generating code that runs in z/Architecture mode,
 420    but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
 421    the ABI guarantees only that the lower 4 bytes are
 422    saved across calls, however.  */
 423 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)             \
 424   (!TARGET_64BIT && TARGET_ZARCH                                \
 425    && GET_MODE_SIZE (MODE) > 4                                  \
 426    && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
 427
 428 /* Maximum number of registers to represent a value of mode MODE
 429    in a register of class CLASS.  */
 430 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 431   s390_class_max_nregs ((CLASS), (MODE))
 432
 433 /* If a 4-byte value is loaded into a FPR, it is placed into the
 434    *upper* half of the register, not the lower.  Therefore, we
 435    cannot use SUBREGs to switch between modes in FP registers.
 436    Likewise for access registers, since they have only half the
 437    word size on 64-bit.  */
 438 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)                       \
 439   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)                           \
 440    ? ((reg_classes_intersect_p (FP_REGS, CLASS)                         \
 441        && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8))         \
 442       || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
 443
 444 /* Register classes.  */
 445
 446 /* We use the following register classes:
 447    GENERAL_REGS     All general purpose registers
 448    ADDR_REGS        All general purpose registers except %r0
 449                     (These registers can be used in address generation)
 450    FP_REGS          All floating point registers
 451    CC_REGS          The condition code register
 452    ACCESS_REGS      The access registers
 453
 454    GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
 455    ADDR_FP_REGS     Union of ADDR_REGS and FP_REGS
 456    GENERAL_CC_REGS  Union of GENERAL_REGS and CC_REGS
 457    ADDR_CC_REGS     Union of ADDR_REGS and CC_REGS
 458
 459    NO_REGS          No registers
 460    ALL_REGS         All registers
 461
 462    Note that the 'fake' frame pointer and argument pointer registers
 463    are included amongst the address registers here.  */
 464
 465 enum reg_class
 466 {
 467   NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
 468   ADDR_CC_REGS, GENERAL_CC_REGS,
 469   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
 470   ALL_REGS, LIM_REG_CLASSES
 471 };
 472 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 473
 474 #define REG_CLASS_NAMES                                                 \
 475 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS",     \
 476   "ADDR_CC_REGS", "GENERAL_CC_REGS",                                    \
 477   "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
 478
 479 /* Class -> register mapping.  */
 480 #define REG_CLASS_CONTENTS \
 481 {                                                       \
 482   { 0x00000000, 0x00000000 },   /* NO_REGS */           \
 483   { 0x00000000, 0x00000002 },   /* CC_REGS */           \
 484   { 0x0000fffe, 0x0000000d },   /* ADDR_REGS */         \
 485   { 0x0000ffff, 0x0000000d },   /* GENERAL_REGS */      \
 486   { 0x00000000, 0x00000030 },   /* ACCESS_REGS */       \
 487   { 0x0000fffe, 0x0000000f },   /* ADDR_CC_REGS */      \
 488   { 0x0000ffff, 0x0000000f },   /* GENERAL_CC_REGS */   \
 489   { 0xffff0000, 0x00000000 },   /* FP_REGS */           \
 490   { 0xfffffffe, 0x0000000d },   /* ADDR_FP_REGS */      \
 491   { 0xffffffff, 0x0000000d },   /* GENERAL_FP_REGS */   \
 492   { 0xffffffff, 0x0000003f },   /* ALL_REGS */          \
 493 }
 494
 495 /* The following macro defines cover classes for Integrated Register
 496    Allocator.  Cover classes is a set of non-intersected register
 497    classes covering all hard registers used for register allocation
 498    purpose.  Any move between two registers of a cover class should be
 499    cheaper than load or store of the registers.  The macro value is
 500    array of register classes with LIM_REG_CLASSES used as the end
 501    marker.  */
 502
 503 #define IRA_COVER_CLASSES                                                    \
 504 {                                                                            \
 505   GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES               \
 506 }
 507
 508 /* In some case register allocation order is not enough for IRA to
 509    generate a good code.  The following macro (if defined) increases
 510    cost of REGNO for a pseudo approximately by pseudo usage frequency
 511    multiplied by the macro value.
 512
 513    We avoid usage of BASE_REGNUM by nonzero macro value because the
 514    reload can decide not to use the hard register because some
 515    constant was forced to be in memory.  */
 516 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno)       \
 517   (regno == BASE_REGNUM ? 0.0 : 0.5)
 518
 519 /* Register -> class mapping.  */
 520 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 521 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
 522
 523 /* ADDR_REGS can be used as base or index register.  */
 524 #define INDEX_REG_CLASS ADDR_REGS
 525 #define BASE_REG_CLASS ADDR_REGS
 526
 527 /* Check whether REGNO is a hard register of the suitable class
 528    or a pseudo register currently allocated to one such.  */
 529 #define REGNO_OK_FOR_INDEX_P(REGNO)                                     \
 530     (((REGNO) < FIRST_PSEUDO_REGISTER                                   \
 531       && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS)                        \
 532      || ADDR_REGNO_P (reg_renumber[REGNO]))
 533 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
 534
 535
 536 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
 537    return the class of reg to actually use.  */
 538 #define PREFERRED_RELOAD_CLASS(X, CLASS)        \
 539   s390_preferred_reload_class ((X), (CLASS))
 540
 541 /* We need secondary memory to move data between GPRs and FPRs.  With
 542    DFP the ldgr lgdr instructions are available.  But these
 543    instructions do not handle GPR pairs so it is not possible for 31
 544    bit.  */
 545 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
 546  ((CLASS1) != (CLASS2)                                \
 547   && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)     \
 548   && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
 549
 550 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
 551    because the movsi and movsf patterns don't handle r/f moves.  */
 552 #define SECONDARY_MEMORY_NEEDED_MODE(MODE)              \
 553  (GET_MODE_BITSIZE (MODE) < 32                          \
 554   ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)        \
 555   : MODE)
 556
 557
 558 /* Stack layout and calling conventions.  */
 559
 560 /* Our stack grows from higher to lower addresses.  However, local variables
 561    are accessed by positive offsets, and function arguments are stored at
 562    increasing addresses.  */
 563 #define STACK_GROWS_DOWNWARD
 564 #define FRAME_GROWS_DOWNWARD 1
 565 /* #undef ARGS_GROW_DOWNWARD */
 566
 567 /* The basic stack layout looks like this: the stack pointer points
 568    to the register save area for called functions.  Above that area
 569    is the location to place outgoing arguments.  Above those follow
 570    dynamic allocations (alloca), and finally the local variables.  */
 571
 572 /* Offset from stack-pointer to first location of outgoing args.  */
 573 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
 574
 575 /* Offset within stack frame to start allocating local variables at.  */
 576 #define STARTING_FRAME_OFFSET 0
 577
 578 /* Offset from the stack pointer register to an item dynamically
 579    allocated on the stack, e.g., by `alloca'.  */
 580 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
 581   (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
 582
 583 /* Offset of first parameter from the argument pointer register value.
 584    We have a fake argument pointer register that points directly to
 585    the argument area.  */
 586 #define FIRST_PARM_OFFSET(FNDECL) 0
 587
 588 /* Defining this macro makes __builtin_frame_address(0) and
 589    __builtin_return_address(0) work with -fomit-frame-pointer.  */
 590 #define INITIAL_FRAME_ADDRESS_RTX                                             \
 591   (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
 592
 593 /* The return address of the current frame is retrieved
 594    from the initial value of register RETURN_REGNUM.
 595    For frames farther back, we use the stack slot where
 596    the corresponding RETURN_REGNUM register was saved.  */
 597 #define DYNAMIC_CHAIN_ADDRESS(FRAME)                                          \
 598   (TARGET_PACKED_STACK ?                                                      \
 599    plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
 600
 601 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
 602    builtin_frame_address.  Otherwise arg pointer -
 603    STACK_POINTER_OFFSET would be returned for
 604    __builtin_frame_address(0) what might result in an address pointing
 605    somewhere into the middle of the local variables since the packed
 606    stack layout generally does not need all the bytes in the register
 607    save area.  */
 608 #define FRAME_ADDR_RTX(FRAME)                   \
 609   DYNAMIC_CHAIN_ADDRESS ((FRAME))
 610
 611 #define RETURN_ADDR_RTX(COUNT, FRAME)                                         \
 612   s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
 613
 614 /* In 31-bit mode, we need to mask off the high bit of return addresses.  */
 615 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
 616
 617
 618 /* Exception handling.  */
 619
 620 /* Describe calling conventions for DWARF-2 exception handling.  */
 621 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, RETURN_REGNUM)
 622 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
 623 #define DWARF_FRAME_RETURN_COLUMN  14
 624
 625 /* Describe how we implement __builtin_eh_return.  */
 626 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
 627 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
 628
 629 /* Select a format to encode pointers in exception handling data.  */
 630 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                          \
 631   (flag_pic                                                                 \
 632     ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
 633    : DW_EH_PE_absptr)
 634
 635 /* Register save slot alignment.  */
 636 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
 637
 638
 639 /* Frame registers.  */
 640
 641 #define STACK_POINTER_REGNUM 15
 642 #define FRAME_POINTER_REGNUM 34
 643 #define HARD_FRAME_POINTER_REGNUM 11
 644 #define ARG_POINTER_REGNUM 32
 645 #define RETURN_ADDRESS_POINTER_REGNUM 35
 646
 647 /* The static chain must be call-clobbered, but not used for
 648    function argument passing.  As register 1 is clobbered by
 649    the trampoline code, we only have one option.  */
 650 #define STATIC_CHAIN_REGNUM 0
 651
 652 /* Number of hardware registers that go into the DWARF-2 unwind info.
 653    To avoid ABI incompatibility, this number must not change even as
 654    'fake' hard registers are added or removed.  */
 655 #define DWARF_FRAME_REGISTERS 34
 656
 657
 658 /* Frame pointer and argument pointer elimination.  */
 659
 660 #define ELIMINABLE_REGS                                         \
 661 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },                \
 662  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },           \
 663  { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },                  \
 664  { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },             \
 665  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM },       \
 666  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },  \
 667  { BASE_REGNUM, BASE_REGNUM }}
 668
 669 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 670   (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
 671
 672
 673 /* Stack arguments.  */
 674
 675 /* We need current_function_outgoing_args to be valid.  */
 676 #define ACCUMULATE_OUTGOING_ARGS 1
 677
 678
 679 /* Register arguments.  */
 680
 681 typedef struct s390_arg_structure
 682 {
 683   int gprs;                     /* gpr so far */
 684   int fprs;                     /* fpr so far */
 685 }
 686 CUMULATIVE_ARGS;
 687
 688 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
 689   ((CUM).gprs=0, (CUM).fprs=0)
 690
 691 /* Arguments can be placed in general registers 2 to 6, or in floating
 692    point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
 693    bit.  */
 694 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
 695   (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19)))
 696
 697
 698 /* Scalar return values.  */
 699
 700 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 701   s390_function_value ((VALTYPE), (FUNC), VOIDmode)
 702
 703 #define LIBCALL_VALUE(MODE) \
 704   s390_function_value (NULL, NULL, (MODE))
 705
 706 /* Only gpr 2 and fpr 0 are ever used as return registers.  */
 707 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
 708
 709
 710 /* Function entry and exit.  */
 711
 712 /* When returning from a function, the stack pointer does not matter.  */
 713 #define EXIT_IGNORE_STACK       1
 714
 715
 716 /* Profiling.  */
 717
 718 #define FUNCTION_PROFILER(FILE, LABELNO)                        \
 719   s390_function_profiler ((FILE), ((LABELNO)))
 720
 721 #define PROFILE_BEFORE_PROLOGUE 1
 722
 723
 724 /* Trampolines for nested functions.  */
 725
 726 #define TRAMPOLINE_SIZE         (TARGET_64BIT ? 32 : 16)
 727 #define TRAMPOLINE_ALIGNMENT    BITS_PER_WORD
 728
 729 /* Addressing modes, and classification of registers for them.  */
 730
 731 /* Recognize any constant value that is a valid address.  */
 732 #define CONSTANT_ADDRESS_P(X) 0
 733
 734 /* Maximum number of registers that can appear in a valid memory address.  */
 735 #define MAX_REGS_PER_ADDRESS 2
 736
 737 /* This definition replaces the formerly used 'm' constraint with a
 738    different constraint letter in order to avoid changing semantics of
 739    the 'm' constraint when accepting new address formats in
 740    TARGET_LEGITIMATE_ADDRESS_P.  The constraint letter defined here
 741    must not be used in insn definitions or inline assemblies.  */
 742 #define TARGET_MEM_CONSTRAINT 'e'
 743
 744 /* Try a machine-dependent way of reloading an illegitimate address
 745    operand.  If we find one, push the reload and jump to WIN.  This
 746    macro is used in only one place: `find_reloads_address' in reload.c.  */
 747 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN)      \
 748 do {                                                                    \
 749   rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE));       \
 750   if (new_rtx)                                                          \
 751     {                                                                   \
 752       (AD) = new_rtx;                                                   \
 753       goto WIN;                                                         \
 754     }                                                                   \
 755 } while (0)
 756
 757 /* Nonzero if the constant value X is a legitimate general operand.
 758    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 759 #define LEGITIMATE_CONSTANT_P(X) \
 760      legitimate_constant_p (X)
 761
 762 /* Helper macro for s390.c and s390.md to check for symbolic constants.  */
 763 #define SYMBOLIC_CONST(X)       \
 764 (GET_CODE (X) == SYMBOL_REF                                             \
 765  || GET_CODE (X) == LABEL_REF                                           \
 766  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
 767
 768 #define TLS_SYMBOLIC_CONST(X)   \
 769 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X))       \
 770  || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
 771
 772
 773 /* Condition codes.  */
 774
 775 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
 776    return the mode to be used for the comparison.  */
 777 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
 778
 779 /* Canonicalize a comparison from one we don't have to one we do have.  */
 780 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
 781   s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
 782
 783 /* Relative costs of operations.  */
 784
 785 /* On s390, copy between fprs and gprs is expensive.  */
 786 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)                        \
 787   ((   (   reg_classes_intersect_p ((CLASS1), GENERAL_REGS)             \
 788         && reg_classes_intersect_p ((CLASS2), FP_REGS))                 \
 789     || (   reg_classes_intersect_p ((CLASS1), FP_REGS)                  \
 790         && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
 791
 792 /* A C expression for the cost of moving data of mode M between a
 793    register and memory.  A value of 2 is the default; this cost is
 794    relative to those in `REGISTER_MOVE_COST'.  */
 795 #define MEMORY_MOVE_COST(M, C, I) 1
 796
 797 /* A C expression for the cost of a branch instruction.  A value of 1
 798    is the default; other values are interpreted relative to that.  */
 799 #define BRANCH_COST(speed_p, predictable_p) 1
 800
 801 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 802 #define SLOW_BYTE_ACCESS 1
 803
 804 /* An integer expression for the size in bits of the largest integer machine
 805    mode that should actually be used.  We allow pairs of registers.  */
 806 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 807
 808 /* The maximum number of bytes that a single instruction can move quickly
 809    between memory and registers or between two memory locations.  */
 810 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
 811 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
 812 #define MAX_MOVE_MAX 16
 813
 814 /* Determine whether to use move_by_pieces or block move insn.  */
 815 #define MOVE_BY_PIECES_P(SIZE, ALIGN)           \
 816   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 817     || (TARGET_ZARCH && (SIZE) == 8) )
 818
 819 /* Determine whether to use clear_by_pieces or block clear insn.  */
 820 #define CLEAR_BY_PIECES_P(SIZE, ALIGN)          \
 821   ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
 822     || (TARGET_ZARCH && (SIZE) == 8) )
 823
 824 /* This macro is used to determine whether store_by_pieces should be
 825    called to "memcpy" storage when the source is a constant string.  */
 826 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
 827
 828 /* Likewise to decide whether to "memset" storage with byte values
 829    other than zero.  */
 830 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN)
 831
 832 /* Don't perform CSE on function addresses.  */
 833 #define NO_FUNCTION_CSE
 834
 835 /* This value is used in tree-sra to decide whether it might benefical
 836    to split a struct move into several word-size moves.  For S/390
 837    only small values make sense here since struct moves are relatively
 838    cheap thanks to mvc so the small default value choosen for archs
 839    with memmove patterns should be ok.  But this value is multiplied
 840    in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
 841    here to compensate for that factor since mvc costs exactly the same
 842    on 31 and 64 bit.  */
 843 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
 844
 845
 846 /* Sections.  */
 847
 848 /* Output before read-only data.  */
 849 #define TEXT_SECTION_ASM_OP ".text"
 850
 851 /* Output before writable (initialized) data.  */
 852 #define DATA_SECTION_ASM_OP ".data"
 853
 854 /* Output before writable (uninitialized) data.  */
 855 #define BSS_SECTION_ASM_OP ".bss"
 856
 857 /* S/390 constant pool breaks the devices in crtstuff.c to control section
 858    in where code resides.  We have to write it as asm code.  */
 859 #ifndef __s390x__
 860 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
 861     asm (SECTION_OP "\n\
 862         bras\t%r2,1f\n\
 863 0:      .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
 864 1:      l\t%r3,0(%r2)\n\
 865         bas\t%r14,0(%r3,%r2)\n\
 866         .previous");
 867 #endif
 868
 869
 870 /* Position independent code.  */
 871
 872 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
 873
 874 #define LEGITIMATE_PIC_OPERAND_P(X)  legitimate_pic_operand_p (X)
 875
 876
 877 /* Assembler file format.  */
 878
 879 /* Character to start a comment.  */
 880 #define ASM_COMMENT_START "#"
 881
 882 /* Declare an uninitialized external linkage data object.  */
 883 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
 884   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
 885
 886 /* Globalizing directive for a label.  */
 887 #define GLOBAL_ASM_OP ".globl "
 888
 889 /* Advance the location counter to a multiple of 2**LOG bytes.  */
 890 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
 891   if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
 892
 893 /* Advance the location counter by SIZE bytes.  */
 894 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
 895   fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
 896
 897 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h.  */
 898 #define LOCAL_LABEL_PREFIX "."
 899
 900 /* How to refer to registers in assembler output.  This sequence is
 901    indexed by compiler's hard-register-number (see above).  */
 902 #define REGISTER_NAMES                                                  \
 903 { "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",        \
 904   "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",       \
 905   "%f0",  "%f2",  "%f4",  "%f6",  "%f1",  "%f3",  "%f5",  "%f7",        \
 906   "%f8",  "%f10", "%f12", "%f14", "%f9",  "%f11", "%f13", "%f15",       \
 907   "%ap",  "%cc",  "%fp",  "%rp",  "%a0",  "%a1"                         \
 908 }
 909
 910 /* Print operand X (an rtx) in assembler syntax to file FILE.  */
 911 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
 912 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
 913
 914 /* Output machine-dependent UNSPECs in address constants.  */
 915 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL)          \
 916 do {                                                    \
 917   if (!s390_output_addr_const_extra (FILE, (X)))        \
 918     goto FAIL;                                          \
 919 } while (0);
 920
 921 /* Output an element of a case-vector that is absolute.  */
 922 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)                            \
 923 do {                                                                    \
 924   char buf[32];                                                         \
 925   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 926   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 927   assemble_name ((FILE), buf);                                          \
 928   fputc ('\n', (FILE));                                                 \
 929 } while (0)
 930
 931 /* Output an element of a case-vector that is relative.  */
 932 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)                \
 933 do {                                                                    \
 934   char buf[32];                                                         \
 935   fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
 936   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
 937   assemble_name ((FILE), buf);                                          \
 938   fputc ('-', (FILE));                                                  \
 939   ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL));                        \
 940   assemble_name ((FILE), buf);                                          \
 941   fputc ('\n', (FILE));                                                 \
 942 } while (0)
 943
 944
 945 /* Miscellaneous parameters.  */
 946
 947 /* Specify the machine mode that this machine uses for the index in the
 948    tablejump instruction.  */
 949 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
 950
 951 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
 952    is done just by pretending it is already truncated.  */
 953 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
 954
 955 /* Specify the machine mode that pointers have.
 956    After generation of rtl, the compiler makes no further distinction
 957    between pointers and any other objects of this machine mode.  */
 958 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
 959
 960 /* This is -1 for "pointer mode" extend.  See ptr_extend in s390.md.  */
 961 #define POINTERS_EXTEND_UNSIGNED -1
 962
 963 /* A function address in a call instruction is a byte address (for
 964    indexing purposes) so give the MEM rtx a byte's mode.  */
 965 #define FUNCTION_MODE QImode
 966
 967 /* Specify the value which is used when clz operand is zero.  */
 968 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
 969
 970 /* Machine-specific symbol_ref flags.  */
 971 #define SYMBOL_FLAG_ALIGN1                (SYMBOL_FLAG_MACH_DEP << 0)
 972 #define SYMBOL_REF_ALIGN1_P(X)          \
 973   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
 974 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
 975 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
 976   ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
 977
 978 /* Check whether integer displacement is in range.  */
 979 #define DISP_IN_RANGE(d) \
 980   (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
 981                            : ((d) >= 0 && (d) <= 4095))
 982
 983 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c.  */
 984 #define READ_CAN_USE_WRITE_PREFETCH 1
 985 #endif