| blob | 933f5fe68b41b9a1806904db1d107a4ec752d471 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
55 /* Information about the loop being processed used to compute
56 the number of loop iterations for loop unrolling and doloop
57 optimization. */
60 /* Vector mapping INSN_UIDs to luids.
61 The luids are like uids but increase monotonically always.
62 We use them to see whether a jump comes from outside a given loop. */
66 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
67 number the insn is contained in. */
71 /* 1 + largest uid of any insn. */
75 /* 1 + luid of last insn. */
79 /* Number of loops detected in current function. Used as index to the
80 next few tables. */
84 /* Indexed by loop number, contains the first and last insn of each loop. */
88 /* Likewise for the continue insn */
91 /* The first code_label that is reached in every loop iteration.
92 0 when not computed yet, initially const0_rtx if a jump couldn't be
93 followed.
94 Also set to 0 when there is no such label before the NOTE_INSN_LOOP_CONT
95 of this loop, or in verify_dominator, if a jump couldn't be followed. */
98 /* For each loop, gives the containing loop number, -1 if none. */
102 #ifdef HAVE_decrement_and_branch_on_count
103 /* Records whether resource in use by inner loop. */
108 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
109 really a loop (an insn outside the loop branches into it). */
113 /* Indexed by loop number, links together all LABEL_REFs which refer to
114 code labels outside the loop. Used by routines that need to know all
115 loop exits, such as final_biv_value and final_giv_value.
117 This does not include loop exits due to return instructions. This is
118 because all bivs and givs are pseudos, and hence must be dead after a
119 return, so the presense of a return does not affect any of the
120 optimizations that use this info. It is simpler to just not include return
121 instructions on this list. */
125 /* Indexed by loop number, counts the number of LABEL_REFs on
126 loop_number_exit_labels for this loop and all loops nested inside it. */
130 /* Indexed by register number, contains the number of times the reg
131 is set during the loop being scanned.
132 During code motion, a negative value indicates a reg that has been
133 made a candidate; in particular -2 means that it is an candidate that
134 we know is equal to a constant and -1 means that it is an candidate
135 not known equal to a constant.
136 After code motion, regs moved have 0 (which is accurate now)
137 while the failed candidates have the original number of times set.
139 Therefore, at all times, == 0 indicates an invariant register;
140 < 0 a conditionally invariant one. */
144 /* Original value of set_in_loop; same except that this value
145 is not set negative for a reg whose sets have been made candidates
146 and not set to 0 for a reg that is moved. */
150 /* Index by register number, 1 indicates that the register
151 cannot be moved or strength reduced. */
155 /* Contains the insn in which a register was used if it was used
156 exactly once; contains const0_rtx if it was used more than once. */
160 /* Nonzero means reg N has already been moved out of one loop.
161 This reduces the desire to move it out of another. */
165 /* List of MEMs that are stored in this loop. */
169 /* The insn where the first of these was found. */
178 /* Array of MEMs that are used (read or written) in this loop, but
179 cannot be aliased by anything in this loop, except perhaps
180 themselves. In other words, if loop_mems[i] is altered during the
181 loop, it is altered by an expression that is rtx_equal_p to it. */
185 /* The index of the next available slot in LOOP_MEMS. */
189 /* The number of elements allocated in LOOP_MEMs. */
193 /* Nonzero if we don't know what MEMs were changed in the current
194 loop. This happens if the loop contains a call (in which case
195 `loop_info->has_call' will also be set) or if we store into more
196 than NUM_STORES MEMs. */
200 /* The above doesn't count any readonly memory locations that are stored.
201 This does. */
205 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
208 /* Count of memory write instructions discovered in the loop. */
211 /* Bound on pseudo register number before loop optimization.
212 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
215 /* This obstack is used in product_cheap_p to allocate its rtl. It
216 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
217 If we used the same obstack that it did, we would be deallocating
218 that array. */
222 /* This is where the pointer to the obstack being used for RTL is stored. */
226 #define obstack_chunk_alloc xmalloc
227 #define obstack_chunk_free free
228 \f
229 /* During the analysis of a loop, a chain of `struct movable's
230 is made to record all the movable insns found.
231 Then the entire chain can be scanned to decide which to move. */
233 struct movable
234 {
239 of any registers used within the LIBCALL. */
241 that must be moved with this one. */
244 may be adjusted when matching movables
245 that load the same value are found. */
247 including other movables that force this
248 or match this one. */
252 /* If PARTIAL is 1, GLOBAL means something different:
253 that the reg is live outside the range from where it is set
254 to the following label. */
258 In particular, moving it does not make it
259 invariant. */
261 load SRC, rather than copying INSN. */
263 first insn of a consecutive sets group. */
266 that we should avoid changing when clearing
267 the rest of the reg. */
271 };
277 /* Forward declarations. */
294 #if 0
296 #endif
315 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, int, rtx *, rtx, rtx));
343 rtx r;
348 rtx r1;
349 rtx r2;
352 /* Nonzero iff INSN is between START and END, inclusive. */
353 #define INSN_IN_RANGE_P(INSN, START, END) \
354 (INSN_UID (INSN) < max_uid_for_loop \
355 && INSN_LUID (INSN) >= INSN_LUID (START) \
356 && INSN_LUID (INSN) <= INSN_LUID (END))
358 #ifdef HAVE_decrement_and_branch_on_count
359 /* Test whether BCT applicable and safe. */
362 /* Auxiliary function that inserts the BCT pattern into the loop. */
366 /* Indirect_jump_in_function is computed once per function. */
374 \f
375 /* Relative gain of eliminating various kinds of operations. */
377 #if 0
380 #endif
382 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
383 copy the value of the strength reduced giv to its original register. */
386 /* Cost of using a register, to normalize the benefits of a giv. */
390 void
392 {
398 #ifdef ADDRESS_COST
400 #else
402 #endif
404 /* We multiply by 2 to reconcile the difference in scale between
405 these two ways of computing costs. Otherwise the cost of a copy
406 will be far less than the cost of an add. */
410 /* Free the objects we just allocated. */
413 /* Initialize the obstack used for rtl in product_cheap_p. */
415 }
416 \f
417 /* Compute the mapping from uids to luids.
418 LUIDs are numbers assigned to insns, like uids,
419 except that luids increase monotonically through the code.
420 Start at insn START and stop just before END. Assign LUIDs
421 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
422 static int
426 {
428 rtx insn;
431 {
434 /* Don't assign luids to line-number NOTEs, so that the distance in
435 luids between two insns is not affected by -g. */
439 else
440 /* Give a line number note the same luid as preceding insn. */
442 }
444 }
445 \f
446 /* Entry point of this file. Perform loop optimization
447 on the current function. F is the first insn of the function
448 and DUMPFILE is a stream for output of a trace of actions taken
449 (or 0 if none should be output). */
451 void
453 /* f is the first instruction of a chain of insns for one function */
454 rtx f;
457 {
472 /* Count the number of loops. */
476 {
479 max_loop_num++;
480 }
482 /* Don't waste time if no loops. */
486 /* Get size to use for tables indexed by uids.
487 Leave some space for labels allocated by find_and_verify_loops. */
496 /* Allocate tables for recording each loop. We set each entry, so they need
497 not be zeroed. */
507 #ifdef HAVE_decrement_and_branch_on_count
508 /* Allocate for BCT optimization */
513 /* Find and process each loop.
514 First, find them, and record them in order of their beginnings. */
517 /* Now find all register lifetimes. This must be done after
518 find_and_verify_loops, because it might reorder the insns in the
519 function. */
522 /* This must occur after reg_scan so that registers created by gcse
523 will have entries in the register tables.
525 We could have added a call to reg_scan after gcse_main in toplev.c,
526 but moving this call to init_alias_analysis is more efficient. */
529 /* See if we went too far. Note that get_max_uid already returns
530 one more that the maximum uid of all insn. */
533 /* Now reset it to the actual size we need. See above. */
536 /* find_and_verify_loops has already called compute_luids, but it might
537 have rearranged code afterwards, so we need to recompute the luids now. */
540 /* Don't leave gaps in uid_luid for insns that have been
541 deleted. It is possible that the first or last insn
542 using some register has been deleted by cross-jumping.
543 Make sure that uid_luid for that former insn's uid
544 points to the general area where that insn used to be. */
546 {
550 }
555 /* Create a mapping from loops to BLOCK tree nodes. */
559 /* Determine if the function has indirect jump. On some systems
560 this prevents low overhead loop instructions from being used. */
563 /* Now scan the loops, last ones first, since this means inner ones are done
564 before outer ones. */
570 /* If debugging and unrolling loops, we must replicate the tree nodes
571 corresponding to the blocks inside the loop, so that the original one
572 to one mapping will remain. */
577 }
578 \f
579 /* Returns the next insn, in execution order, after INSN. START and
580 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
581 respectively. LOOP_TOP, if non-NULL, is the top of the loop in the
582 insn-stream; it is used with loops that are entered near the
583 bottom. */
585 static rtx
587 rtx insn;
588 rtx start;
589 rtx end;
590 rtx loop_top;
591 {
595 {
597 /* Go to the top of the loop, and continue there. */
599 else
600 /* We're done. */
602 }
605 /* We're done. */
609 }
611 /* Optimize one loop whose start is LOOP_START and end is END.
612 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
613 NOTE_INSN_LOOP_END.
614 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
616 /* ??? Could also move memory writes out of loops if the destination address
617 is invariant, the source is invariant, the memory write is not volatile,
618 and if we can prove that no read inside the loop can read this address
619 before the write occurs. If there is a read of this address after the
620 write, then we can also mark the memory read as invariant. */
622 static void
626 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* For a rotated loop that is entered near the bottom,
635 this is the label at the top. Otherwise it is zero. */
637 /* Jump insn that enters the loop, or 0 if control drops in. */
639 /* Place in the loop where control enters. */
640 rtx scan_start;
641 /* Number of insns in the loop. */
645 rtx temp;
646 /* The SET from an insn, if it is the only SET in the insn. */
648 /* Chain describing insns movable in current loop. */
650 /* Last element in `movables' -- so we can add elements at the end. */
652 /* Ratio of extra register life span we can justify
653 for saving an instruction. More if loop doesn't call subroutines
654 since in that case saving an insn makes more difference
655 and more registers are available. */
657 /* Nonzero if we are scanning instructions in a sub-loop. */
662 /* Determine whether this loop starts with a jump down to a test at
663 the end. This will occur for a small number of loops with a test
664 that is too complex to duplicate in front of the loop.
666 We search for the first insn or label in the loop, skipping NOTEs.
667 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
668 (because we might have a loop executed only once that contains a
669 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
670 (in case we have a degenerate loop).
672 Note that if we mistakenly think that a loop is entered at the top
673 when, in fact, it is entered at the exit test, the only effect will be
674 slightly poorer optimization. Making the opposite error can generate
675 incorrect code. Since very few loops now start with a jump to the
676 exit test, the code here to detect that case is very conservative. */
679 p != end
685 ;
689 /* Set up variables describing this loop. */
693 /* If loop has a jump before the first label,
694 the true entry is the target of that jump.
695 Start scan from there.
696 But record in LOOP_TOP the place where the end-test jumps
697 back to so we can scan that after the end of the loop. */
699 {
702 /* Loop entry must be unconditional jump (and not a RETURN) */
705 /* Check to see whether the jump actually
706 jumps out of the loop (meaning it's no loop).
707 This case can happen for things like
708 do {..} while (0). If this label was generated previously
709 by loop, we can't tell anything about it and have to reject
710 the loop. */
712 {
715 }
716 }
718 /* If SCAN_START was an insn created by loop, we don't know its luid
719 as required by loop_reg_used_before_p. So skip such loops. (This
720 test may never be true, but it's best to play it safe.)
722 Also, skip loops where we do not start scanning at a label. This
723 test also rejects loops starting with a JUMP_INSN that failed the
724 test above. */
728 {
733 }
735 /* Count number of times each reg is set during this loop.
736 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
737 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
739 /* Allocate extra space for REGS that might be created by
740 load_mems. We allocate a little extra slop as well, in the hopes
741 that even after the moving of movables creates some new registers
742 we won't have to reallocate these arrays. However, we do grow
743 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
754 {
757 }
759 #ifdef AVOID_CCMODE_COPIES
760 /* Don't try to move insns which set CC registers if we should not
761 create CCmode register copies. */
765 #endif
771 {
777 }
779 /* Scan through the loop finding insns that are safe to move.
780 Set set_in_loop negative for the reg being set, so that
781 this reg will be considered invariant for subsequent insns.
782 We consider whether subsequent insns use the reg
783 in deciding whether it is worth actually moving.
785 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
786 and therefore it is possible that the insns we are scanning
787 would never be executed. At such times, we must make sure
788 that it is safe to execute the insn once instead of zero times.
789 When MAYBE_NEVER is 0, all insns will be executed at least once
790 so that is not a problem. */
795 {
807 {
814 /* Figure out what to use as a source of this insn. If a REG_EQUIV
815 note is given or if a REG_EQUAL note with a constant operand is
816 specified, use it as the source and mark that we should move
817 this insn by calling emit_move_insn rather that duplicating the
818 insn.
820 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
821 is present. */
825 else
826 {
831 {
833 /* A libcall block can use regs that don't appear in
834 the equivalent expression. To move the libcall,
835 we must move those regs too. */
837 }
838 }
840 /* Don't try to optimize a register that was made
841 by loop-optimization for an inner loop.
842 We don't know its life-span, so we can't compute the benefit. */
844 ;
846 than the one where it is set (meaning that
847 something after this point in the loop might
848 depend on its value before the set). */
850 /* And the set is not guaranteed to be executed one
851 the loop starts, or the value before the set is
852 needed before the set occurs...
854 ??? Note we have quadratic behaviour here, mitigated
855 by the fact that the previous test will often fail for
856 large loops. Rather than re-scanning the entire loop
857 each time for register usage, we should build tables
858 of the register usage and use them here instead. */
859 && (maybe_never
862 /* It is unsafe to move the set.
864 This code used to consider it OK to move a set of a variable
865 which was not created by the user and not used in an exit test.
866 That behavior is incorrect and was removed. */
867 ;
873 || (tem1
874 = consec_sets_invariant_p
877 p)))
878 /* If the insn can cause a trap (such as divide by zero),
879 can't move it unless it's guaranteed to be executed
880 once loop is entered. Even a function call might
881 prevent the trap insn from being reached
882 (since it might exit!) */
885 {
889 /* A potential lossage is where we have a case where two insns
890 can be combined as long as they are both in the loop, but
891 we move one of them outside the loop. For large loops,
892 this can lose. The most common case of this is the address
893 of a function being called.
895 Therefore, if this register is marked as being used exactly
896 once if we are in a loop with calls (a "large loop"), see if
897 we can replace the usage of this register with the source
898 of this SET. If we can, delete this insn.
900 Don't do this if P has a REG_RETVAL note or if we have
901 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
912 && (! SMALL_REGISTER_CLASSES
915 /* This test is not redundant; SET_SRC (set) might be
916 a call-clobbered register and the life of REGNO
917 might span a call. */
919 VARRAY_RTX
923 VARRAY_RTX
925 {
926 /* Replace any usage in a REG_EQUAL note. Must copy the
927 new source, so that we don't get rtx sharing between the
928 SET_SOURCE and REG_NOTES of insn p. */
939 }
958 /* Set M->cond if either invariant_p or consec_sets_invariant_p
959 returned 2 (only conditionally invariant). */
970 /* Add M to the end of the chain MOVABLES. */
973 else
978 {
979 /* It is possible for the first instruction to have a
980 REG_EQUAL note but a non-invariant SET_SRC, so we must
981 remember the status of the first instruction in case
982 the last instruction doesn't have a REG_EQUAL note. */
985 /* Skip this insn, not checking REG_LIBCALL notes. */
987 /* Skip the consecutive insns, if there are any. */
989 /* Back up to the last insn of the consecutive group. */
992 /* We must now reset m->move_insn, m->is_equiv, and possibly
993 m->set_src to correspond to the effects of all the
994 insns. */
998 else
999 {
1003 else
1006 }
1008 }
1009 }
1010 /* If this register is always set within a STRICT_LOW_PART
1011 or set to zero, then its high bytes are constant.
1012 So clear them outside the loop and within the loop
1013 just load the low bytes.
1014 We must check that the machine has an instruction to do so.
1015 Also, if the value loaded into the register
1016 depends on the same register, this cannot be done. */
1026 {
1029 {
1043 /* If the insn may not be executed on some cycles,
1044 we can't clear the whole reg; clear just high part.
1045 Not even if the reg is used only within this loop.
1046 Consider this:
1047 while (1)
1048 while (s != t) {
1049 if (foo ()) x = *s;
1050 use (x);
1051 }
1052 Clearing x before the inner loop could clobber a value
1053 being saved from the last time around the outer loop.
1054 However, if the reg is not used outside this loop
1055 and all uses of the register are in the same
1056 basic block as the store, there is no problem.
1058 If this insn was made by loop, we don't know its
1059 INSN_LUID and hence must make a conservative
1060 assumption. */
1066 || (labels_in_range_p
1070 else
1079 /* Add M to the end of the chain MOVABLES. */
1082 else
1085 }
1086 }
1087 }
1088 /* Past a call insn, we get to insns which might not be executed
1089 because the call might exit. This matters for insns that trap.
1090 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1091 so they don't count. */
1094 /* Past a label or a jump, we get to insns for which we
1095 can't count on whether or how many times they will be
1096 executed during each iteration. Therefore, we can
1097 only move out sets of trivial variables
1098 (those not used after the loop). */
1099 /* Similar code appears twice in strength_reduce. */
1101 /* If we enter the loop in the middle, and scan around to the
1102 beginning, don't set maybe_never for that. This must be an
1103 unconditional jump, otherwise the code at the top of the
1104 loop might never be executed. Unconditional jumps are
1105 followed a by barrier then loop end. */
1111 {
1112 /* At the virtual top of a converted loop, insns are again known to
1113 be executed: logically, the loop begins here even though the exit
1114 code has been duplicated. */
1118 loop_depth++;
1120 loop_depth--;
1121 }
1122 }
1124 /* If one movable subsumes another, ignore that other. */
1128 /* For each movable insn, see if the reg that it loads
1129 leads when it dies right into another conditionally movable insn.
1130 If so, record that the second insn "forces" the first one,
1131 since the second can be moved only if the first is. */
1135 /* See if there are multiple movable insns that load the same value.
1136 If there are, make all but the first point at the first one
1137 through the `match' field, and add the priorities of them
1138 all together as the priority of the first. */
1142 /* Now consider each movable insn to decide whether it is worth moving.
1143 Store 0 in set_in_loop for each reg that is moved.
1145 Generally this increases code size, so do not move moveables when
1146 optimizing for code size. */
1152 /* Now candidates that still are negative are those not moved.
1153 Change set_in_loop to indicate that those are not actually invariant. */
1158 /* Now that we've moved some things out of the loop, we might be able to
1159 hoist even more memory references. */
1164 {
1169 }
1175 }
1176 \f
1177 /* Add elements to *OUTPUT to record all the pseudo-regs
1178 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1180 void
1184 {
1192 {
1210 }
1214 {
1218 {
1227 }
1228 }
1229 }
1230 \f
1231 /* Check what regs are referred to in the libcall block ending with INSN,
1232 aside from those mentioned in the equivalent value.
1233 If there are none, return 0.
1234 If there are one or more, return an EXPR_LIST containing all of them. */
1236 rtx
1239 {
1244 /* First, find all the regs used in the libcall block
1245 that are not mentioned as inputs to the result. */
1248 {
1253 }
1256 }
1257 \f
1258 /* Return 1 if all uses of REG
1259 are between INSN and the end of the basic block. */
1261 static int
1264 {
1266 rtx p;
1271 /* Search this basic block for the already recorded last use of the reg. */
1273 {
1275 {
1281 /* Ordinary insn: if this is the last use, we win. */
1287 /* Jump insn: if this is the last use, we win. */
1290 /* Otherwise, it's the end of the basic block, so we lose. */
1295 /* It's the end of the basic block, so we lose. */
1300 }
1301 }
1303 /* The "last use" doesn't follow the "first use"?? */
1305 }
1306 \f
1307 /* Compute the benefit of eliminating the insns in the block whose
1308 last insn is LAST. This may be a group of insns used to compute a
1309 value directly or can contain a library call. */
1311 static int
1313 rtx last;
1314 {
1315 rtx insn;
1320 {
1323 routine. */
1327 benefit++;
1328 }
1331 }
1332 \f
1333 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1335 static rtx
1337 rtx insn;
1339 {
1341 {
1342 rtx temp;
1344 /* If first insn of libcall sequence, skip to end. */
1345 /* Do this at start of loop, since INSN is guaranteed to
1346 be an insn here. */
1353 }
1356 }
1358 /* Ignore any movable whose insn falls within a libcall
1359 which is part of another movable.
1360 We make use of the fact that the movable for the libcall value
1361 was made later and so appears later on the chain. */
1363 static void
1366 {
1370 {
1371 /* Is this a movable for the value of a libcall? */
1374 {
1375 rtx insn;
1376 /* Check for earlier movables inside that range,
1377 and mark them invalid. We cannot use LUIDs here because
1378 insns created by loop.c for prior loops don't have LUIDs.
1379 Rather than reject all such insns from movables, we just
1380 explicitly check each insn in the libcall (since invariant
1381 libcalls aren't that common). */
1386 }
1387 }
1388 }
1390 /* For each movable insn, see if the reg that it loads
1391 leads when it dies right into another conditionally movable insn.
1392 If so, record that the second insn "forces" the first one,
1393 since the second can be moved only if the first is. */
1395 static void
1398 {
1401 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1403 {
1406 /* ??? Could this be a bug? What if CSE caused the
1407 register of M1 to be used after this insn?
1408 Since CSE does not update regno_last_uid,
1409 this insn M->insn might not be where it dies.
1410 But very likely this doesn't matter; what matters is
1411 that M's reg is computed from M1's reg. */
1416 /* If m->consec, m->set_src isn't valid. */
1420 /* Increase the priority of the moving the first insn
1421 since it permits the second to be moved as well. */
1423 {
1427 }
1428 }
1429 }
1430 \f
1431 /* Find invariant expressions that are equal and can be combined into
1432 one register. */
1434 static void
1438 {
1443 /* Regs that are set more than once are not allowed to match
1444 or be matched. I'm no longer sure why not. */
1445 /* Perhaps testing m->consec_sets would be more appropriate here? */
1449 {
1456 /* We want later insns to match the first one. Don't make the first
1457 one match any later ones. So start this loop at m->next. */
1460 /* A reg used outside the loop mustn't be eliminated. */
1462 /* A reg used for zero-extending mustn't be eliminated. */
1465 ||
1466 (
1467 /* Can combine regs with different modes loaded from the
1468 same constant only if the modes are the same or
1469 if both are integer modes with M wider or the same
1470 width as M1. The check for integer is redundant, but
1471 safe, since the only case of differing destination
1472 modes with equal sources is when both sources are
1473 VOIDmode, i.e., CONST_INT. */
1479 /* See if the source of M1 says it matches M. */
1483 movables))))
1486 {
1492 }
1493 }
1495 /* Now combine the regs used for zero-extension.
1496 This can be done for those not marked `global'
1497 provided their lives don't overlap. */
1501 {
1504 /* Combine all the registers for extension from mode MODE.
1505 Don't combine any that are used outside this loop. */
1509 {
1515 {
1516 /* First one: don't check for overlap, just record it. */
1519 }
1521 /* Make sure they extend to the same mode.
1522 (Almost always true.) */
1526 /* We already have one: check for overlap with those
1527 already combined together. */
1534 /* No overlap: we can combine this with the others. */
1540 overlap: ;
1541 }
1542 }
1543 }
1544 \f
1545 /* Return 1 if regs X and Y will become the same if moved. */
1547 static int
1551 {
1568 }
1570 /* Return 1 if X and Y are identical-looking rtx's.
1571 This is the Lisp function EQUAL for rtx arguments.
1573 If two registers are matching movables or a movable register and an
1574 equivalent constant, consider them equal. */
1576 static int
1580 {
1594 /* If we have a register and a constant, they may sometimes be
1595 equal. */
1598 {
1603 }
1606 {
1611 }
1613 /* Otherwise, rtx's of different codes cannot be equal. */
1617 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1618 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1623 /* These three types of rtx's can be compared nonrecursively. */
1632 /* Compare the elements. If any pair of corresponding elements
1633 fail to match, return 0 for the whole things. */
1637 {
1639 {
1651 /* Two vectors must have the same length. */
1655 /* And the corresponding elements must match. */
1672 /* These are just backpointers, so they don't matter. */
1678 /* It is believed that rtx's at this level will never
1679 contain anything but integers and other rtx's,
1680 except for within LABEL_REFs and SYMBOL_REFs. */
1683 }
1684 }
1686 }
1687 \f
1688 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1689 insns in INSNS which use the reference. */
1691 static void
1693 rtx x;
1694 rtx insns;
1695 {
1699 rtx insn;
1702 {
1703 /* This code used to ignore labels that referred to dispatch tables to
1704 avoid flow generating (slighly) worse code.
1706 We no longer ignore such label references (see LABEL_REF handling in
1707 mark_jump_label for additional information). */
1712 }
1716 {
1722 }
1723 }
1724 \f
1725 /* Scan MOVABLES, and move the insns that deserve to be moved.
1726 If two matching movables are combined, replace one reg with the
1727 other throughout. */
1729 static void
1734 rtx loop_start;
1735 rtx end;
1737 {
1741 /* Map of pseudo-register replacements to handle combining
1742 when we move several insns that load the same value
1743 into different pseudo-registers. */
1753 {
1754 /* Describe this movable insn. */
1757 {
1778 }
1780 /* Count movables. Value used in heuristics in strength_reduce. */
1781 num_movables++;
1783 /* Ignore the insn if it's already done (it matched something else).
1784 Otherwise, see if it is now safe to move. */
1796 {
1801 /* We have an insn that is safe to move.
1802 Compute its desirability. */
1813 /* An insn MUST be moved if we already moved something else
1814 which is safe only if this one is moved too: that is,
1815 if already_moved[REGNO] is nonzero. */
1817 /* An insn is desirable to move if the new lifetime of the
1818 register is no more than THRESHOLD times the old lifetime.
1819 If it's not desirable, it means the loop is so big
1820 that moving won't speed things up much,
1821 and it is liable to make register usage worse. */
1823 /* It is also desirable to move if it can be moved at no
1824 extra cost because something else was already moved. */
1827 || flag_move_all_movables
1832 {
1837 /* Now move the insns that set the reg. */
1840 {
1843 /* Find the end of this chain of matching regs.
1844 Thus, we load each reg in the chain from that one reg.
1845 And that reg is loaded with 0 directly,
1846 since it has ->match == 0. */
1852 /* Mark the moved, invariant reg as being allowed to
1853 share a hard reg with the other matching invariant. */
1857 regs_may_share
1860 regs_may_share));
1868 }
1869 /* If we are to re-generate the item being moved with a
1870 new move insn, first delete what we have and then emit
1871 the move insn before the loop. */
1873 {
1877 {
1878 /* If this is the first insn of a library call sequence,
1879 skip to the end. */
1884 /* If this is the last insn of a libcall sequence, then
1885 delete every insn in the sequence except the last.
1886 The last insn is handled in the normal manner. */
1889 {
1893 }
1898 /* simplify_giv_expr expects that it can walk the insns
1899 at m->insn forwards and see this old sequence we are
1900 tossing here. delete_insn does preserve the next
1901 pointers, but when we skip over a NOTE we must fix
1902 it up. Otherwise that code walks into the non-deleted
1903 insn stream. */
1906 }
1924 /* The more regs we move, the less we like moving them. */
1926 }
1927 else
1928 {
1930 {
1933 /* If first insn of libcall sequence, skip to end. */
1934 /* Do this at start of loop, since p is guaranteed to
1935 be an insn here. */
1940 /* If last insn of libcall sequence, move all
1941 insns except the last before the loop. The last
1942 insn is handled in the normal manner. */
1945 {
1953 {
1954 rtx body;
1955 rtx n;
1956 rtx next;
1963 /* Find the next insn after TEMP,
1964 not counting USE or NOTE insns. */
1972 /* If that is the call, this may be the insn
1973 that loads the function address.
1975 Extract the function address from the insn
1976 that loads it into a register.
1977 If this insn was cse'd, we get incorrect code.
1979 So emit a new move insn that copies the
1980 function address into the register that the
1981 call insn will use. flow.c will delete any
1982 redundant stores that we have created. */
1987 NULL_RTX)))
1988 {
1994 }
1995 /* We have the call insn.
1996 If it uses the register we suspect it might,
1997 load it with the correct address directly. */
2002 fn_address),
2003 fn_address_insn);
2006 {
2008 /* Because the USAGE information potentially
2009 contains objects other than hard registers
2010 we need to copy it. */
2014 }
2015 else
2023 }
2026 }
2028 {
2029 /* P sets REG to zero; but we should clear only
2030 the bits that are not covered by the mode
2031 m->savemode. */
2033 rtx sequence;
2034 rtx tem;
2037 tem = expand_binop
2050 }
2052 {
2054 /* Because the USAGE information potentially
2055 contains objects other than hard registers
2056 we need to copy it. */
2060 }
2062 {
2063 /* The SET_SRC might not be invariant, so we must
2064 use the REG_EQUAL note. */
2078 }
2079 else
2083 {
2086 /* If there is a REG_EQUAL note present whose value
2087 is not loop invariant, then delete it, since it
2088 may cause problems with later optimization passes.
2089 It is possible for cse to create such notes
2090 like this as a result of record_jump_cond. */
2095 }
2104 /* If library call, now fix the REG_NOTES that contain
2105 insn pointers, namely REG_LIBCALL on FIRST
2106 and REG_RETVAL on I1. */
2108 {
2112 }
2118 /* simplify_giv_expr expects that it can walk the insns
2119 at m->insn forwards and see this old sequence we are
2120 tossing here. delete_insn does preserve the next
2121 pointers, but when we skip over a NOTE we must fix
2122 it up. Otherwise that code walks into the non-deleted
2123 insn stream. */
2126 }
2128 /* The more regs we move, the less we like moving them. */
2130 }
2132 /* Any other movable that loads the same register
2133 MUST be moved. */
2136 /* This reg has been moved out of one loop. */
2139 /* The reg set here is now invariant. */
2145 /* Change the length-of-life info for the register
2146 to say it lives at least the full length of this loop.
2147 This will help guide optimizations in outer loops. */
2150 /* This is the old insn before all the moved insns.
2151 We can't use the moved insn because it is out of range
2152 in uid_luid. Only the old insns have luids. */
2157 /* Combine with this moved insn any other matching movables. */
2162 {
2163 rtx temp;
2165 /* Schedule the reg loaded by M1
2166 for replacement so that shares the reg of M.
2167 If the modes differ (only possible in restricted
2168 circumstances, make a SUBREG.
2170 Note this assumes that the target dependent files
2171 treat REG and SUBREG equally, including within
2172 GO_IF_LEGITIMATE_ADDRESS and in all the
2173 predicates since we never verify that replacing the
2174 original register with a SUBREG results in a
2175 recognizable insn. */
2178 else
2183 /* Get rid of the matching insn
2184 and prevent further processing of it. */
2187 /* if library call, delete all insn except last, which
2188 is deleted below */
2190 NULL_RTX)))
2191 {
2195 }
2198 /* Any other movable that loads the same register
2199 MUST be moved. */
2202 /* The reg merged here is now invariant,
2203 if the reg it matches is invariant. */
2206 }
2207 }
2210 }
2216 }
2221 /* Go through all the instructions in the loop, making
2222 all the register substitutions scheduled in REG_MAP. */
2226 {
2230 }
2231 }
2232 \f
2233 #if 0
2234 /* Scan X and replace the address of any MEM in it with ADDR.
2235 REG is the address that MEM should have before the replacement. */
2237 static void
2240 {
2249 {
2261 /* Short cut for very common case. */
2266 /* Short cut for very common case. */
2271 /* If this MEM uses a reg other than the one we expected,
2272 something is wrong. */
2280 }
2284 {
2288 {
2292 }
2293 }
2294 }
2295 #endif
2296 \f
2297 /* Return the number of memory refs to addresses that vary
2298 in the rtx X. */
2300 static int
2302 rtx x;
2303 {
2314 {
2331 }
2336 {
2340 {
2344 }
2345 }
2347 }
2349 \f
2350 #if 0
2351 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2352 Replace it with an instruction to load just the low bytes
2353 if the machine supports such an instruction,
2354 and insert above LOOP_START an instruction to clear the register. */
2356 static void
2359 {
2363 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2364 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2366 new
2367 = gen_rtx_SET
2369 gen_rtx_STRICT_LOW_PART
2378 {
2381 /* Clear destination register before the loop. */
2384 loop_start);
2386 /* Inside the loop, just load the low part. */
2388 }
2389 }
2390 #endif
2391 \f
2392 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2393 `has_call', `has_volatile', and `has_tablejump' within LOOP_INFO.
2394 Set the global variables `unknown_address_altered',
2395 `unknown_constant_address_altered', and `num_mem_sets'. Also, fill
2396 in the array `loop_mems' and the list `loop_store_mems'. */
2398 static void
2402 {
2404 rtx insn;
2405 /* The label after END. Jumping here is just like falling off the
2406 end of the loop. We use next_nonnote_insn instead of next_label
2407 as a hedge against the (pathological) case where some actual insn
2408 might end up between the two. */
2430 {
2432 {
2434 {
2436 /* Count number of loops contained in this one. */
2438 }
2440 {
2443 {
2446 }
2447 }
2449 {
2452 }
2454 {
2455 /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for
2456 or while style loop, with a loop exit test at the
2457 start. Thus, we can assume that the loop condition
2458 was true when the loop was entered. */
2461 }
2462 }
2464 {
2468 }
2470 {
2490 {
2492 {
2495 }
2496 else
2497 {
2499 }
2503 {
2505 {
2506 /* Something tricky. */
2509 }
2512 {
2513 /* A jump outside the current loop. */
2516 }
2517 }
2522 }
2523 }
2526 }
2528 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2530 !unknown_address_altered
2531 /* An exception thrown by a called function might land us
2532 anywhere. */
2534 /* We don't want loads for MEMs moved to a location before the
2535 one at which their stack memory becomes allocated. (Note
2536 that this is not a problem for malloc, etc., since those
2537 require actual function calls. */
2538 && !current_function_calls_alloca
2539 /* There are ways to leave the loop other than falling off the
2540 end. */
2545 }
2546 \f
2547 /* LOOP_NUMBER_CONT_DOMINATOR is now the last label between the loop start
2548 and the continue note that is a the destination of a (cond)jump after
2549 the continue note. If there is any (cond)jump between the loop start
2550 and what we have so far as LOOP_NUMBER_CONT_DOMINATOR that has a
2551 target between LOOP_DOMINATOR and the continue note, move
2552 LOOP_NUMBER_CONT_DOMINATOR forward to that label; if a jump's
2553 destination cannot be determined, clear LOOP_NUMBER_CONT_DOMINATOR. */
2555 static void
2558 {
2559 rtx insn;
2562 /* This can happen for an empty loop, e.g. in
2563 gcc.c-torture/compile/920410-2.c */
2566 {
2569 }
2573 {
2576 {
2580 /* If it is not a jump we can easily understand or for
2581 which we do not have jump target information in the JUMP_LABEL
2582 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2583 LOOP_NUMBER_CONT_DOMINATOR. */
2587 {
2590 }
2594 && (label_luid
2597 }
2598 }
2599 }
2601 /* Scan the function looking for loops. Record the start and end of each loop.
2602 Also mark as invalid loops any loops that contain a setjmp or are branched
2603 to from outside the loop. */
2605 static void
2607 rtx f;
2608 {
2616 /* If there are jumps to undefined labels,
2617 treat them as jumps out of any/all loops.
2618 This also avoids writing past end of tables when there are no loops. */
2621 /* Find boundaries of loops, mark which loops are contained within
2622 loops, and invalidate loops that have setjmp. */
2625 {
2628 {
2642 /* In this case, we must invalidate our current loop and any
2643 enclosing loop. */
2645 {
2651 }
2668 }
2669 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2670 and NOTE_INSN_LOOP_END notes, update loop_number_loop_dominator. */
2674 {
2682 do
2683 {
2684 /* First see if we care about this loop. */
2687 {
2688 /* If the jump destination is not known, invalidate
2689 loop_number_const_dominator. */
2692 else
2693 /* Check if the destination is between loop start and
2694 cont. */
2699 /* And if there is no later destination already
2700 recorded. */
2706 }
2708 }
2710 }
2712 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2713 enclosing loop, but this doesn't matter. */
2715 }
2717 /* Any loop containing a label used in an initializer must be invalidated,
2718 because it can be jumped into from anywhere. */
2721 {
2728 }
2730 /* Any loop containing a label used for an exception handler must be
2731 invalidated, because it can be jumped into from anywhere. */
2734 {
2741 }
2743 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2744 loop that it is not contained within, that loop is marked invalid.
2745 If any INSN or CALL_INSN uses a label's address, then the loop containing
2746 that label is marked invalid, because it could be jumped into from
2747 anywhere.
2749 Also look for blocks of code ending in an unconditional branch that
2750 exits the loop. If such a block is surrounded by a conditional
2751 branch around the block, move the block elsewhere (see below) and
2752 invert the jump to point to the code block. This may eliminate a
2753 label in our loop and will simplify processing by both us and a
2754 possible second cse pass. */
2758 {
2762 {
2765 {
2772 }
2773 }
2780 /* See if this is an unconditional branch outside the loop. */
2787 {
2788 rtx p;
2794 /* Go backwards until we reach the start of the loop, a label,
2795 or a JUMP_INSN. */
2802 ;
2804 /* Check for the case where we have a jump to an inner nested
2805 loop, and do not perform the optimization in that case. */
2808 {
2811 {
2816 }
2817 }
2819 /* Make sure that the target of P is within the current loop. */
2825 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2826 we have a block of code to try to move.
2828 We look backward and then forward from the target of INSN
2829 to find a BARRIER at the same loop depth as the target.
2830 If we find such a BARRIER, we make a new label for the start
2831 of the block, invert the jump in P and point it to that label,
2832 and move the block of code to the spot we found. */
2837 /* Just ignore jumps to labels that were never emitted.
2838 These always indicate compilation errors. */
2843 /* If it's not safe to move the sequence, then we
2844 mustn't try. */
2847 {
2848 rtx target
2855 /* Don't move things inside a tablejump. */
2868 /* Don't move things inside a tablejump. */
2879 {
2883 /* Ensure our label doesn't go away. */
2886 /* Verify that uid_loop_num is large enough and that
2887 we can invert P. */
2889 {
2892 /* If no suitable BARRIER was found, create a suitable
2893 one before TARGET. Since TARGET is a fall through
2894 path, we'll need to insert an jump around our block
2895 and a add a BARRIER before TARGET.
2897 This creates an extra unconditional jump outside
2898 the loop. However, the benefits of removing rarely
2899 executed instructions from inside the loop usually
2900 outweighs the cost of the extra unconditional jump
2901 outside the loop. */
2903 {
2904 rtx temp;
2911 }
2913 /* Include the BARRIER after INSN and copy the
2914 block after LOC. */
2916 last_insn_to_move);
2919 /* All those insns are now in TARGET_LOOP_NUM. */
2925 /* The label jumped to by INSN is no longer a loop exit.
2926 Unless INSN does not have a label (e.g., it is a
2927 RETURN insn), search loop_number_exit_labels to find
2928 its label_ref, and remove it. Also turn off
2929 LABEL_OUTSIDE_LOOP_P bit. */
2931 {
2938 {
2942 else
2946 }
2953 /* If we didn't find it, then something is wrong. */
2956 }
2958 /* P is now a jump outside the loop, so it must be put
2959 in loop_number_exit_labels, and marked as such.
2960 The easiest way to do this is to just call
2961 mark_loop_jump again for P. */
2964 /* If INSN now jumps to the insn after it,
2965 delete INSN. */
2970 }
2972 /* Continue the loop after where the conditional
2973 branch used to jump, since the only branch insn
2974 in the block (if it still remains) is an inter-loop
2975 branch and hence needs no processing. */
2981 /* This loop will be continued with NEXT_INSN (insn). */
2983 }
2984 }
2985 }
2986 }
2987 }
2989 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2990 loops it is contained in, mark the target loop invalid.
2992 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2994 static void
2996 rtx x;
2998 {
3004 {
3016 /* There could be a label reference in here. */
3028 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3040 /* Link together all labels that branch outside the loop. This
3041 is used by final_[bg]iv_value and the loop unrolling code. Also
3042 mark this LABEL_REF so we know that this branch should predict
3043 false. */
3045 /* A check to make sure the label is not in an inner nested loop,
3046 since this does not count as a loop exit. */
3048 {
3053 }
3054 else
3058 {
3067 }
3069 /* If this is inside a loop, but not in the current loop or one enclosed
3070 by it, it invalidates at least one loop. */
3075 /* We must invalidate every nested loop containing the target of this
3076 label, except those that also contain the jump insn. */
3079 {
3080 /* Stop when we reach a loop that also contains the jump insn. */
3086 /* If we get here, we know we need to invalidate a loop. */
3093 }
3097 /* If this is not setting pc, ignore. */
3119 /* Strictly speaking this is not a jump into the loop, only a possible
3120 jump out of the loop. However, we have no way to link the destination
3121 of this jump onto the list of exit labels. To be safe we mark this
3122 loop and any containing loops as invalid. */
3124 {
3127 {
3133 }
3134 }
3136 }
3137 }
3138 \f
3139 /* Return nonzero if there is a label in the range from
3140 insn INSN to and including the insn whose luid is END
3141 INSN must have an assigned luid (i.e., it must not have
3142 been previously created by loop.c). */
3144 static int
3146 rtx insn;
3148 {
3150 {
3154 }
3157 }
3159 /* Record that a memory reference X is being set. */
3161 static void
3163 rtx x;
3164 rtx y ATTRIBUTE_UNUSED;
3166 {
3170 /* Count number of memory writes.
3171 This affects heuristics in strength_reduce. */
3172 num_mem_sets++;
3174 /* BLKmode MEM means all memory is clobbered. */
3176 {
3179 else
3183 }
3186 }
3188 /* X is a value modified by an INSN that references a biv inside a loop
3189 exit test (ie, X is somehow related to the value of the biv). If X
3190 is a pseudo that is used more than once, then the biv is (effectively)
3191 used more than once. DATA is really an `int *', and is set if the
3192 biv is used more than once. */
3194 static void
3196 rtx x;
3197 rtx y ATTRIBUTE_UNUSED;
3199 {
3212 /* If we do not have usage information, or if we know the register
3213 is used more than once, note that fact for check_dbra_loop. */
3218 }
3219 \f
3220 /* Return nonzero if the rtx X is invariant over the current loop.
3222 The value is 2 if we refer to something only conditionally invariant.
3224 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3225 Otherwise, a memory ref is invariant if it does not conflict with
3226 anything stored in `loop_store_mems'. */
3228 int
3231 {
3236 rtx mem_list_entry;
3242 {
3250 /* A LABEL_REF is normally invariant, however, if we are unrolling
3251 loops, and this label is inside the loop, then it isn't invariant.
3252 This is because each unrolled copy of the loop body will have
3253 a copy of this label. If this was invariant, then an insn loading
3254 the address of this label into a register might get moved outside
3255 the loop, and then each loop body would end up using the same label.
3257 We don't know the loop bounds here though, so just fail for all
3258 labels. */
3261 else
3270 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3271 since the reg might be set by initialization within the loop. */
3288 /* If we had a subroutine call, any location in memory could
3289 have been clobbered. We used to test here for volatile and
3290 readonly, but true_dependence knows how to do that better
3291 than we do. */
3296 /* See if there is any dependence between a store and this load. */
3299 {
3305 }
3307 /* It's not invalidated by a store in memory
3308 but we must still verify the address is invariant. */
3312 /* Don't mess with insns declared volatile. */
3319 }
3323 {
3325 {
3331 }
3333 {
3336 {
3342 }
3344 }
3345 }
3348 }
3350 \f
3351 /* Return nonzero if all the insns in the loop that set REG
3352 are INSN and the immediately following insns,
3353 and if each of those insns sets REG in an invariant way
3354 (not counting uses of REG in them).
3356 The value is 2 if some of these insns are only conditionally invariant.
3358 We assume that INSN itself is the first set of REG
3359 and that its source is invariant. */
3361 static int
3365 {
3368 rtx temp;
3369 /* Number of sets we have to insist on finding after INSN. */
3375 /* If N_SETS hit the limit, we can't rely on its value. */
3382 {
3384 rtx set;
3389 /* If library call, skip to end of it. */
3398 {
3403 {
3404 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3405 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3406 notes are OK. */
3412 }
3413 }
3415 count--;
3417 {
3420 }
3421 }
3424 /* If invariant_p ever returned 2, we return 2. */
3426 }
3428 #if 0
3429 /* I don't think this condition is sufficient to allow INSN
3430 to be moved, so we no longer test it. */
3432 /* Return 1 if all insns in the basic block of INSN and following INSN
3433 that set REG are invariant according to TABLE. */
3435 static int
3439 {
3444 {
3453 {
3456 }
3457 }
3458 }
3460 \f
3461 /* Look at all uses (not sets) of registers in X. For each, if it is
3462 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3463 a different insn, set USAGE[REGNO] to const0_rtx. */
3465 static void
3467 rtx insn;
3468 rtx x;
3469 varray_type usage;
3470 {
3482 {
3483 /* Don't count SET_DEST if it is a REG; otherwise count things
3484 in SET_DEST because if a register is partially modified, it won't
3485 show up as a potential movable so we don't care how USAGE is set
3486 for it. */
3490 }
3491 else
3493 {
3499 }
3500 }
3501 \f
3502 /* Count and record any set in X which is contained in INSN. Update
3503 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3505 static void
3508 varray_type may_not_move;
3510 {
3512 /* Don't move a reg that has an explicit clobber.
3513 It's not worth the pain to try to do it correctly. */
3517 {
3525 {
3527 /* If this is the first setting of this reg
3528 in current basic block, and it was set before,
3529 it must be set in two basic blocks, so it cannot
3530 be moved out of the loop. */
3534 /* If this is not first setting in current basic block,
3535 see if reg was used in between previous one and this.
3536 If so, neither one can be moved. */
3543 }
3544 }
3545 }
3547 /* Increment SET_IN_LOOP at the index of each register
3548 that is modified by an insn between FROM and TO.
3549 If the value of an element of SET_IN_LOOP becomes 127 or more,
3550 stop incrementing it, to avoid overflow.
3552 Store in SINGLE_USAGE[I] the single insn in which register I is
3553 used, if it is only used once. Otherwise, it is set to 0 (for no
3554 uses) or const0_rtx for more than one use. This parameter may be zero,
3555 in which case this processing is not done.
3557 Store in *COUNT_PTR the number of actual instruction
3558 in the loop. We use this to decide what is worth moving out. */
3560 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3561 In that case, it is the insn that last set reg n. */
3563 static void
3566 varray_type may_not_move;
3567 varray_type single_usage;
3570 {
3577 {
3579 {
3582 /* Record registers that have exactly one use. */
3585 /* Include uses in REG_EQUAL notes. */
3593 {
3598 }
3599 }
3603 }
3605 }
3606 \f
3607 /* Given a loop that is bounded by LOOP_START and LOOP_END
3608 and that is entered at SCAN_START,
3609 return 1 if the register set in SET contained in insn INSN is used by
3610 any insn that precedes INSN in cyclic order starting
3611 from the loop entry point.
3613 We don't want to use INSN_LUID here because if we restrict INSN to those
3614 that have a valid INSN_LUID, it means we cannot move an invariant out
3615 from an inner loop past two loops. */
3617 static int
3620 {
3622 rtx p;
3624 /* Scan forward checking for register usage. If we hit INSN, we
3625 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3627 {
3634 }
3637 }
3638 \f
3639 /* A "basic induction variable" or biv is a pseudo reg that is set
3640 (within this loop) only by incrementing or decrementing it. */
3641 /* A "general induction variable" or giv is a pseudo reg whose
3642 value is a linear function of a biv. */
3644 /* Bivs are recognized by `basic_induction_var';
3645 Givs by `general_induction_var'. */
3647 /* Indexed by register number, indicates whether or not register is an
3648 induction variable, and if so what type. */
3650 varray_type reg_iv_type;
3652 /* Indexed by register number, contains pointer to `struct induction'
3653 if register is an induction variable. This holds general info for
3654 all induction variables. */
3656 varray_type reg_iv_info;
3658 /* Indexed by register number, contains pointer to `struct iv_class'
3659 if register is a basic induction variable. This holds info describing
3660 the class (a related group) of induction variables that the biv belongs
3661 to. */
3665 /* The head of a list which links together (via the next field)
3666 every iv class for the current loop. */
3670 /* Givs made from biv increments are always splittable for loop unrolling.
3671 Since there is no regscan info for them, we have to keep track of them
3672 separately. */
3675 /* Communication with routines called via `note_stores'. */
3679 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3683 /* ??? Unfinished optimizations, and possible future optimizations,
3684 for the strength reduction code. */
3686 /* ??? The interaction of biv elimination, and recognition of 'constant'
3687 bivs, may cause problems. */
3689 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3690 performance problems.
3692 Perhaps don't eliminate things that can be combined with an addressing
3693 mode. Find all givs that have the same biv, mult_val, and add_val;
3694 then for each giv, check to see if its only use dies in a following
3695 memory address. If so, generate a new memory address and check to see
3696 if it is valid. If it is valid, then store the modified memory address,
3697 otherwise, mark the giv as not done so that it will get its own iv. */
3699 /* ??? Could try to optimize branches when it is known that a biv is always
3700 positive. */
3702 /* ??? When replace a biv in a compare insn, we should replace with closest
3703 giv so that an optimized branch can still be recognized by the combiner,
3704 e.g. the VAX acb insn. */
3706 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3707 was rerun in loop_optimize whenever a register was added or moved.
3708 Also, some of the optimizations could be a little less conservative. */
3709 \f
3710 /* Perform strength reduction and induction variable elimination.
3712 Pseudo registers created during this function will be beyond the last
3713 valid index in several tables including n_times_set and regno_last_uid.
3714 This does not cause a problem here, because the added registers cannot be
3715 givs outside of their loop, and hence will never be reconsidered.
3716 But scan_loop must check regnos to make sure they are in bounds.
3718 SCAN_START is the first instruction in the loop, as the loop would
3719 actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is
3720 the first instruction in the loop, as it is layed out in the
3721 instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG.
3722 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
3724 static void
3727 rtx scan_start;
3728 rtx end;
3729 rtx loop_top;
3731 rtx loop_start;
3732 rtx loop_end;
3734 rtx loop_cont;
3736 {
3737 rtx p;
3738 rtx set;
3739 rtx inc_val;
3740 rtx mult_val;
3741 rtx dest_reg;
3743 /* This is 1 if current insn is not executed at least once for every loop
3744 iteration. */
3746 /* This is 1 if current insn may be executed more than once for every
3747 loop iteration. */
3749 /* This is 1 if we have past a branch back to the top of the loop
3750 (aka a loop latch). */
3752 /* Temporary list pointers for traversing loop_iv_list. */
3754 /* Ratio of extra register life span we can justify
3755 for saving an instruction. More if loop doesn't call subroutines
3756 since in that case saving an insn makes more difference
3757 and more registers are available. */
3758 /* ??? could set this to last value of threshold in move_movables */
3760 /* Map of pseudo-register replacements. */
3764 rtx test;
3765 rtx end_insert_before;
3770 /* If scan_start points to the loop exit test, we have to be wary of
3771 subversive use of gotos inside expression statements. */
3785 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3786 must be put before this insn, so that they will appear in the right
3787 order (i.e. loop order).
3789 If loop_end is the end of the current function, then emit a
3790 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3791 dummy note insn. */
3794 else
3797 /* Scan through loop to find all possible bivs. */
3802 {
3806 {
3811 {
3815 {
3816 /* It is a possible basic induction variable.
3817 Create and initialize an induction structure for it. */
3825 }
3828 }
3829 }
3831 /* Past CODE_LABEL, we get to insns that may be executed multiple
3832 times. The only way we can be sure that they can't is if every
3833 jump insn between here and the end of the loop either
3834 returns, exits the loop, is a jump to a location that is still
3835 behind the label, or is a jump to the loop start. */
3838 {
3844 {
3849 {
3852 else
3856 }
3864 {
3867 }
3868 }
3869 }
3871 /* Past a jump, we get to insns for which we can't count
3872 on whether they will be executed during each iteration. */
3873 /* This code appears twice in strength_reduce. There is also similar
3874 code in scan_loop. */
3876 /* If we enter the loop in the middle, and scan around to the
3877 beginning, don't set not_every_iteration for that.
3878 This can be any kind of jump, since we want to know if insns
3879 will be executed if the loop is executed. */
3883 {
3886 /* If this is a jump outside the loop, then it also doesn't
3887 matter. Check to see if the target of this branch is on the
3888 loop_number_exits_labels list. */
3891 label;
3898 }
3901 {
3902 /* At the virtual top of a converted loop, insns are again known to
3903 be executed each iteration: logically, the loop begins here
3904 even though the exit code has been duplicated.
3906 Insns are also again known to be executed each iteration at
3907 the LOOP_CONT note. */
3913 loop_depth++;
3915 loop_depth--;
3916 }
3918 /* Note if we pass a loop latch. If we do, then we can not clear
3919 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3920 a loop since a jump before the last CODE_LABEL may have started
3921 a new loop iteration.
3923 Note that LOOP_TOP is only set for rotated loops and we need
3924 this check for all loops, so compare against the CODE_LABEL
3925 which immediately follows LOOP_START. */
3929 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3930 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3931 or not an insn is known to be executed each iteration of the
3932 loop, whether or not any iterations are known to occur.
3934 Therefore, if we have just passed a label and have no more labels
3935 between here and the test insn of the loop, and we have not passed
3936 a jump to the top of the loop, then we know these insns will be
3937 executed each iteration. */
3940 && ! past_loop_latch
3945 }
3947 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3948 Make a sanity check against n_times_set. */
3950 {
3952 /* Above happens if register modified by subreg, etc. */
3953 /* Make sure it is not recognized as a basic induction var: */
3955 /* If never incremented, it is invariant that we decided not to
3956 move. So leave it alone. */
3958 {
3969 }
3970 else
3971 {
3976 }
3977 }
3979 /* Exit if there are no bivs. */
3981 {
3982 /* Can still unroll the loop anyways, but indicate that there is no
3983 strength reduction info available. */
3989 }
3991 /* Find initial value for each biv by searching backwards from loop_start,
3992 halting at first label. Also record any test condition. */
3996 {
4006 /* Record any test of a biv that branches around the loop if no store
4007 between it and the start of loop. We only care about tests with
4008 constants and registers and only certain of those. */
4018 {
4019 /* If an NE test, we have an initial value! */
4021 {
4025 }
4026 else
4028 }
4029 }
4031 /* Look at the each biv and see if we can say anything better about its
4032 initial value from any initializing insns set up above. (This is done
4033 in two passes to avoid missing SETs in a PARALLEL.) */
4035 {
4036 rtx src;
4037 rtx note;
4042 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4043 is a constant, use the value of that. */
4049 else
4060 {
4064 {
4066 {
4069 }
4070 else
4071 {
4074 }
4075 }
4076 }
4077 else
4078 {
4082 /* Biv initial value is not a simple move. If it is the sum of
4083 another biv and a constant, check if both bivs are incremented
4084 in lockstep. Then we are actually looking at a giv.
4085 For simplicity, we only handle the case where there is but a
4086 single increment, and the register is not used elsewhere. */
4095 {
4101 }
4103 /* Now, can we transform this biv into a giv? */
4108 /* init_insn is only set to insns that are before loop_start
4109 without any intervening labels. */
4112 /* The register from BL2 must be set before the register from
4113 BL is set, or we must be able to move the latter set after
4114 the former set. Currently there can't be any labels
4115 in-between when biv_total_increment returns nonzero both times
4116 but we test it here in case some day some real cfg analysis
4117 gets used to set always_computable. */
4126 {
4135 /* Let this giv be discovered by the generic code. */
4138 /* We can get better optimization if we can move the giv setting
4139 before the first giv use. */
4143 dominator)
4146 {
4147 rtx p;
4148 rtx next;
4151 {
4157 #ifdef HAVE_cc0
4160 #endif
4162 }
4166 /* Avoid problems with luids by actually moving the insn
4167 and adjusting all luids in the range. */
4172 /* If the only purpose of the init insn is to initialize
4173 this giv, delete it. */
4177 }
4179 {
4186 }
4187 /* Remove this biv from the chain. */
4189 {
4190 /* We move the following giv from *bl->next into *bl.
4191 We have to update reg_biv_class for that moved biv
4192 to point to its new address. */
4195 }
4196 else
4197 {
4200 }
4201 }
4203 /* If we can't make it a giv,
4204 let biv keep initial value of "itself". */
4207 }
4208 }
4210 /* If a biv is unconditionally incremented several times in a row, convert
4211 all but the last increment into a giv. */
4213 /* Get an upper bound for the number of registers
4214 we might have after all bivs have been processed. */
4219 /* If the loop contains volatile memory references do not allow any
4220 replacements to take place, since this could loose the volatile markers. */
4222 {
4225 /* Reallocate reg_iv_type and reg_iv_info. */
4230 {
4234 /* The biv increments lists are in reverse order. Fix this first. */
4236 {
4240 }
4242 /* We must guard against the case that an early exit between v->insn
4243 and next->insn leaves the biv live after the loop, since that
4244 would mean that we'd be missing an increment for the final
4245 value. The following test to set biv_dead_after_loop is like
4246 the first part of the test to set bl->eliminable.
4247 We don't check here if we can calculate the final value, since
4248 this can't succeed if we already know that there is a jump
4249 between v->insn and next->insn, yet next->always_executed is
4250 set and next->maybe_multiple is cleared. Such a combination
4251 implies that the jump destination is outside the loop.
4252 If we want to make this check more sophisticated, we should
4253 check each branch between v->insn and next->insn individually
4254 to see if the biv is dead at its destination. */
4261 #ifdef HAVE_decrement_and_branch_until_zero
4263 #endif
4268 {
4269 HOST_WIDE_INT offset;
4281 || ! (biv_dead_after_loop
4283 {
4286 }
4293 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4294 have been allocated with some slop space, so we may not
4295 actually need to reallocate them. If we do, the following
4296 if statement will be executed just once in this loop. */
4298 {
4299 /* Grow all the remaining arrays. */
4304 }
4307 {
4310 }
4312 /* Here we can try to eliminate the increment by combining
4313 it into the uses. */
4315 /* Set last_use_insn so that we can check against it. */
4320 {
4324 {
4326 }
4327 }
4329 /* If we can't get the LUIDs for the insns, we can't
4330 calculate the lifetime. This is likely from unrolling
4331 of an inner loop, so there is little point in making this
4332 a DEST_REG giv anyways. */
4336 {
4337 /* Change the increment at NEXT back to what it was. */
4343 }
4377 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4378 it must be replaced. */
4383 /* Remove the increment from the list of biv increments,
4384 and record it as a giv. */
4393 /* Now replace the biv with DEST_REG in all insns between
4394 the replaced increment and the next increment, and
4395 remember the last insn that needed a replacement. */
4399 {
4400 rtx note;
4405 {
4409 }
4411 {
4415 }
4416 }
4420 /* If the lifetime is zero, it means that this register is really
4421 a dead store. So mark this as a giv that can be ignored.
4422 This will not prevent the biv from being eliminated. */
4430 }
4431 }
4432 }
4435 /* Search the loop for general induction variables. */
4437 /* A register is a giv if: it is only set once, it is a function of a
4438 biv and a constant (or invariant), and it is not a biv. */
4445 {
4447 /* At end of a straight-in loop, we are done.
4448 At end of a loop entered at the bottom, scan the top. */
4452 {
4455 else
4459 }
4461 /* Look for a general induction variable in a register. */
4466 {
4467 rtx src_reg;
4468 rtx add_val;
4469 rtx mult_val;
4472 rtx last_consec_insn;
4481 /* Equivalent expression is a giv. */
4486 /* Don't try to handle any regs made by loop optimization.
4487 We have nothing on them in regno_first_uid, etc. */
4489 /* Don't recognize a BASIC_INDUCT_VAR here. */
4491 /* This must be the only place where the register is set. */
4493 /* or all sets must be consecutive and make a giv. */
4498 {
4502 /* If this is a library call, increase benefit. */
4506 /* Skip the consecutive insns, if there are any. */
4514 }
4515 }
4517 #ifndef DONT_REDUCE_ADDR
4518 /* Look for givs which are memory addresses. */
4519 /* This resulted in worse code on a VAX 8600. I wonder if it
4520 still does. */
4524 #endif
4526 /* Update the status of whether giv can derive other givs. This can
4527 change when we pass a label or an insn that updates a biv. */
4532 /* Past CODE_LABEL, we get to insns that may be executed multiple
4533 times. The only way we can be sure that they can't is if every
4534 every jump insn between here and the end of the loop either
4535 returns, exits the loop, is a forward jump, or is a jump
4536 to the loop start. */
4539 {
4545 {
4550 {
4553 else
4557 }
4568 {
4571 }
4572 }
4573 }
4575 /* Past a jump, we get to insns for which we can't count
4576 on whether they will be executed during each iteration. */
4577 /* This code appears twice in strength_reduce. There is also similar
4578 code in scan_loop. */
4580 /* If we enter the loop in the middle, and scan around to the
4581 beginning, don't set not_every_iteration for that.
4582 This can be any kind of jump, since we want to know if insns
4583 will be executed if the loop is executed. */
4587 {
4590 /* If this is a jump outside the loop, then it also doesn't
4591 matter. Check to see if the target of this branch is on the
4592 loop_number_exits_labels list. */
4595 label;
4602 }
4605 {
4606 /* At the virtual top of a converted loop, insns are again known to
4607 be executed each iteration: logically, the loop begins here
4608 even though the exit code has been duplicated.
4610 Insns are also again known to be executed each iteration at
4611 the LOOP_CONT note. */
4617 loop_depth++;
4619 loop_depth--;
4620 }
4622 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4623 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4624 or not an insn is known to be executed each iteration of the
4625 loop, whether or not any iterations are known to occur.
4627 Therefore, if we have just passed a label and have no more labels
4628 between here and the test insn of the loop, we know these insns
4629 will be executed each iteration. */
4635 }
4637 /* Try to calculate and save the number of loop iterations. This is
4638 set to zero if the actual number can not be calculated. This must
4639 be called after all giv's have been identified, since otherwise it may
4640 fail if the iteration variable is a giv. */
4644 /* Now for each giv for which we still don't know whether or not it is
4645 replaceable, check to see if it is replaceable because its final value
4646 can be calculated. This must be done after loop_iterations is called,
4647 so that final_giv_value will work correctly. */
4650 {
4656 }
4658 /* Try to prove that the loop counter variable (if any) is always
4659 nonnegative; if so, record that fact with a REG_NONNEG note
4660 so that "decrement and branch until zero" insn can be used. */
4663 /* Create reg_map to hold substitutions for replaceable giv regs.
4664 Some givs might have been made from biv increments, so look at
4665 reg_iv_type for a suitable size. */
4670 /* Examine each iv class for feasibility of strength reduction/induction
4671 variable elimination. */
4674 {
4681 /* Test whether it will be possible to eliminate this biv
4682 provided all givs are reduced. This is possible if either
4683 the reg is not used outside the loop, or we can compute
4684 what its final value will be.
4686 For architectures with a decrement_and_branch_until_zero insn,
4687 don't do this if we put a REG_NONNEG note on the endtest for
4688 this biv. */
4690 /* Compare against bl->init_insn rather than loop_start.
4691 We aren't concerned with any uses of the biv between
4692 init_insn and loop_start since these won't be affected
4693 by the value of the biv elsewhere in the function, so
4694 long as init_insn doesn't use the biv itself.
4695 March 14, 1989 -- self@bayes.arc.nasa.gov */
4701 #ifdef HAVE_decrement_and_branch_until_zero
4703 #endif
4707 #ifdef HAVE_decrement_and_branch_until_zero
4709 #endif
4710 ))
4713 else
4714 {
4716 {
4724 }
4725 }
4727 /* Combine all giv's for this iv_class. */
4730 /* This will be true at the end, if all givs which depend on this
4731 biv have been strength reduced.
4732 We can't (currently) eliminate the biv unless this is so. */
4735 /* Check each giv in this class to see if we will benefit by reducing
4736 it. Skip giv's combined with others. */
4738 {
4746 /* Reduce benefit if not replaceable, since we will insert
4747 a move-insn to replace the insn that calculates this giv.
4748 Don't do this unless the giv is a user variable, since it
4749 will often be marked non-replaceable because of the duplication
4750 of the exit code outside the loop. In such a case, the copies
4751 we insert are dead and will be deleted. So they don't have
4752 a cost. Similar situations exist. */
4753 /* ??? The new final_[bg]iv_value code does a much better job
4754 of finding replaceable giv's, and hence this code may no longer
4755 be necessary. */
4760 /* Decrease the benefit to count the add-insns that we will
4761 insert to increment the reduced reg for the giv. */
4764 /* Decide whether to strength-reduce this giv or to leave the code
4765 unchanged (recompute it from the biv each time it is used).
4766 This decision can be made independently for each giv. */
4768 #ifdef AUTO_INC_DEC
4769 /* Attempt to guess whether autoincrement will handle some of the
4770 new add insns; if so, increase BENEFIT (undo the subtraction of
4771 add_cost that was done above). */
4774 {
4787 }
4788 #endif
4790 /* If an insn is not to be strength reduced, then set its ignore
4791 flag, and clear all_reduced. */
4793 /* A giv that depends on a reversed biv must be reduced if it is
4794 used after the loop exit, otherwise, it would have the wrong
4795 value after the loop exit. To make it simple, just reduce all
4796 of such giv's whether or not we know they are used after the loop
4797 exit. */
4801 {
4809 }
4810 else
4811 {
4812 /* Check that we can increment the reduced giv without a
4813 multiply insn. If not, reject it. */
4818 {
4826 }
4827 }
4828 }
4830 /* Check for givs whose first use is their definition and whose
4831 last use is the definition of another giv. If so, it is likely
4832 dead and should not be used to derive another giv nor to
4833 eliminate a biv. */
4835 {
4841 {
4847 }
4850 {
4856 }
4857 }
4859 /* Now that we know which givs will be reduced, try to rearrange the
4860 combinations to reduce register pressure.
4861 recombine_givs calls find_life_end, which needs reg_iv_type and
4862 reg_iv_info to be valid for all pseudos. We do the necessary
4863 reallocation here since it allows to check if there are still
4864 more bivs to process. */
4867 {
4868 /* If there are still more bivs to process, allocate some slack
4869 space so that we're not constantly reallocating these arrays. */
4872 /* Reallocate reg_iv_type and reg_iv_info. */
4875 }
4878 /* Reduce each giv that we decided to reduce. */
4881 {
4884 {
4887 /* If the code for derived givs immediately below has already
4888 allocated a new_reg, we must keep it. */
4893 {
4896 /* In case d->dest_reg is not replaceable, we have
4897 to replace it in v->insn now. */
4904 /* For each place where the biv is incremented, add an
4905 insn to set the new, reduced reg for the giv.
4906 We used to do this only for biv_count != 1, but
4907 this fails when there is a giv after a single biv
4908 increment, e.g. when the last giv was expressed as
4909 pre-decrement. */
4911 {
4912 /* We always emit reduced giv increments before the
4913 biv increment when bl->biv_count != 1. So by
4914 emitting the add insns for derived givs after the
4915 biv increment, they pick up the updated value of
4916 the reduced giv.
4917 If the reduced giv is processed with
4918 auto_inc_opt == 1, then it is incremented earlier
4919 than the biv, hence we'll still pick up the right
4920 value.
4921 If it's processed with auto_inc_opt == -1,
4922 that implies that the biv increment is before the
4923 first reduced giv's use. The derived giv's lifetime
4924 is after the reduced giv's lifetime, hence in this
4925 case, the biv increment doesn't matter. */
4927 }
4929 }
4931 #ifdef AUTO_INC_DEC
4932 /* If the target has auto-increment addressing modes, and
4933 this is an address giv, then try to put the increment
4934 immediately after its use, so that flow can create an
4935 auto-increment addressing mode. */
4938 /* We don't handle reversed biv's because bl->biv->insn
4939 does not have a valid INSN_LUID. */
4943 {
4944 /* If other giv's have been combined with this one, then
4945 this will work only if all uses of the other giv's occur
4946 before this giv's insn. This is difficult to check.
4948 We simplify this by looking for the common case where
4949 there is one DEST_REG giv, and this giv's insn is the
4950 last use of the dest_reg of that DEST_REG giv. If the
4951 increment occurs after the address giv, then we can
4952 perform the optimization. (Otherwise, the increment
4953 would have to go before other_giv, and we would not be
4954 able to combine it with the address giv to get an
4955 auto-inc address.) */
4957 {
4962 {
4965 else
4967 }
4974 }
4975 /* Check for case where increment is before the address
4976 giv. Do this test in "loop order". */
4985 else
4988 #ifdef HAVE_cc0
4989 {
4990 rtx prev;
4992 /* We can't put an insn immediately after one setting
4993 cc0, or immediately before one using cc0. */
5000 }
5001 #endif
5005 }
5006 #endif
5008 /* For each place where the biv is incremented, add an insn
5009 to increment the new, reduced reg for the giv. */
5011 {
5012 rtx insert_before;
5018 else
5025 /* A multiply is acceptable here
5026 since this is presumed to be seldom executed. */
5029 }
5031 /* Add code at loop start to initialize giv's reduced reg. */
5035 }
5036 }
5038 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5039 as not reduced.
5041 For each giv register that can be reduced now: if replaceable,
5042 substitute reduced reg wherever the old giv occurs;
5043 else add new move insn "giv_reg = reduced_reg". */
5046 {
5053 /* Update expression if this was combined, in case other giv was
5054 replaced. */
5060 /* Store reduced reg as the address in the memref where we found
5061 this giv. */
5064 {
5067 #if 0
5068 /* I can no longer duplicate the original problem. Perhaps
5069 this is unnecessary now? */
5071 /* Replaceable; it isn't strictly necessary to delete the old
5072 insn and emit a new one, because v->dest_reg is now dead.
5074 However, especially when unrolling loops, the special
5075 handling for (set REG0 REG1) in the second cse pass may
5076 make v->dest_reg live again. To avoid this problem, emit
5077 an insn to set the original giv reg from the reduced giv.
5078 We can not delete the original insn, since it may be part
5079 of a LIBCALL, and the code in flow that eliminates dead
5080 libcalls will fail if it is deleted. */
5083 #endif
5084 }
5085 else
5086 {
5087 /* Not replaceable; emit an insn to set the original giv reg from
5088 the reduced giv, same as above. */
5091 }
5093 /* When a loop is reversed, givs which depend on the reversed
5094 biv, and which are live outside the loop, must be set to their
5095 correct final value. This insn is only needed if the giv is
5096 not replaceable. The correct final value is the same as the
5097 value that the giv starts the reversed loop with. */
5102 {
5103 rtx insert_before;
5105 /* If the loop has multiple exits, emit the insn before the
5106 loop to ensure that it will always be executed no matter
5107 how the loop exits. Otherwise, emit the insn after the loop,
5108 since this is slightly more efficient. */
5111 else
5114 insert_before);
5116 #if 0
5117 /* If the insn to set the final value of the giv was emitted
5118 before the loop, then we must delete the insn inside the loop
5119 that sets it. If this is a LIBCALL, then we must delete
5120 every insn in the libcall. Note, however, that
5121 final_giv_value will only succeed when there are multiple
5122 exits if the giv is dead at each exit, hence it does not
5123 matter that the original insn remains because it is dead
5124 anyways. */
5125 /* Delete the insn inside the loop that sets the giv since
5126 the giv is now set before (or after) the loop. */
5128 #endif
5129 }
5132 {
5137 }
5138 }
5140 /* All the givs based on the biv bl have been reduced if they
5141 merit it. */
5143 /* For each giv not marked as maybe dead that has been combined with a
5144 second giv, clear any "maybe dead" mark on that second giv.
5145 v->new_reg will either be or refer to the register of the giv it
5146 combined with.
5148 Doing this clearing avoids problems in biv elimination where a
5149 giv's new_reg is a complex value that can't be put in the insn but
5150 the giv combined with (with a reg as new_reg) is marked maybe_dead.
5151 Since the register will be used in either case, we'd prefer it be
5152 used from the simpler giv. */
5158 /* Try to eliminate the biv, if it is a candidate.
5159 This won't work if ! all_reduced,
5160 since the givs we planned to use might not have been reduced.
5162 We have to be careful that we didn't initially think we could eliminate
5163 this biv because of a giv that we now think may be dead and shouldn't
5164 be used as a biv replacement.
5166 Also, there is the possibility that we may have a giv that looks
5167 like it can be used to eliminate a biv, but the resulting insn
5168 isn't valid. This can happen, for example, on the 88k, where a
5169 JUMP_INSN can compare a register only with zero. Attempts to
5170 replace it with a compare with a constant will fail.
5172 Note that in cases where this call fails, we may have replaced some
5173 of the occurrences of the biv with a giv, but no harm was done in
5174 doing so in the rare cases where it can occur. */
5180 {
5181 /* ?? If we created a new test to bypass the loop entirely,
5182 or otherwise drop straight in, based on this test, then
5183 we might want to rewrite it also. This way some later
5184 pass has more hope of removing the initialization of this
5185 biv entirely. */
5187 /* If final_value != 0, then the biv may be used after loop end
5188 and we must emit an insn to set it just in case.
5190 Reversed bivs already have an insn after the loop setting their
5191 value, so we don't need another one. We can't calculate the
5192 proper final value for such a biv here anyways. */
5194 {
5195 rtx insert_before;
5197 /* If the loop has multiple exits, emit the insn before the
5198 loop to ensure that it will always be executed no matter
5199 how the loop exits. Otherwise, emit the insn after the
5200 loop, since this is slightly more efficient. */
5203 else
5207 end_insert_before);
5208 }
5210 #if 0
5211 /* Delete all of the instructions inside the loop which set
5212 the biv, as they are all dead. If is safe to delete them,
5213 because an insn setting a biv will never be part of a libcall. */
5214 /* However, deleting them will invalidate the regno_last_uid info,
5215 so keeping them around is more convenient. Final_biv_value
5216 will only succeed when there are multiple exits if the biv
5217 is dead at each exit, hence it does not matter that the original
5218 insn remains, because it is dead anyways. */
5221 #endif
5226 }
5227 }
5229 /* Go through all the instructions in the loop, making all the
5230 register substitutions scheduled in REG_MAP. */
5235 {
5239 }
5242 {
5243 /* When we completely unroll a loop we will likely not need the increment
5244 of the loop BIV and we will not need the conditional branch at the
5245 end of the loop. */
5248 #ifdef HAVE_cc0
5249 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5250 need the comparison before the conditional branch at the end of the
5251 loop. */
5253 #endif
5255 /* We'll need one copy for each loop iteration. */
5258 /* A little slop to account for the ability to remove initialization
5259 code, better CSE, and other secondary benefits of completely
5260 unrolling some loops. */
5263 /* Clamp the value. */
5266 }
5268 /* Unroll loops from within strength reduction so that we can use the
5269 induction variable information that strength_reduce has already
5270 collected. Always unroll loops that would be as small or smaller
5271 unrolled than when rolled. */
5278 #ifdef HAVE_decrement_and_branch_on_count
5279 /* Instrument the loop with BCT insn. */
5288 egress:
5291 }
5292 \f
5293 /* Return 1 if X is a valid source for an initial value (or as value being
5294 compared against in an initial test).
5296 X must be either a register or constant and must not be clobbered between
5297 the current insn and the start of the loop.
5299 INSN is the insn containing X. */
5301 static int
5303 rtx x;
5304 rtx insn;
5306 rtx loop_start;
5307 {
5311 /* Only consider pseudos we know about initialized in insns whose luids
5312 we know. */
5317 /* Don't use call-clobbered registers across a call which clobbers it. On
5318 some machines, don't use any hard registers at all. */
5320 && (SMALL_REGISTER_CLASSES
5324 /* Don't use registers that have been clobbered before the start of the
5325 loop. */
5330 }
5331 \f
5332 /* Scan X for memory refs and check each memory address
5333 as a possible giv. INSN is the insn whose pattern X comes from.
5334 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5335 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5336 more thanonce in each loop iteration. */
5338 static void
5340 loop_end)
5341 rtx x;
5342 rtx insn;
5345 {
5355 {
5371 {
5372 rtx src_reg;
5373 rtx add_val;
5374 rtx mult_val;
5377 /* This code used to disable creating GIVs with mult_val == 1 and
5378 add_val == 0. However, this leads to lost optimizations when
5379 it comes time to combine a set of related DEST_ADDR GIVs, since
5380 this one would not be seen. */
5384 {
5385 /* Found one; record it. */
5394 }
5395 }
5400 }
5402 /* Recursively scan the subexpressions for other mem refs. */
5413 }
5414 \f
5415 /* Fill in the data about one biv update.
5416 V is the `struct induction' in which we record the biv. (It is
5417 allocated by the caller, with alloca.)
5418 INSN is the insn that sets it.
5419 DEST_REG is the biv's reg.
5421 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5422 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5423 being set to INC_VAL.
5425 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5426 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5427 can be executed more than once per iteration. If MAYBE_MULTIPLE
5428 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5429 executed exactly once per iteration. */
5431 static void
5435 rtx insn;
5436 rtx dest_reg;
5437 rtx inc_val;
5438 rtx mult_val;
5442 {
5456 /* Add this to the reg's iv_class, creating a class
5457 if this is the first incrementation of the reg. */
5461 {
5462 /* Create and initialize new iv_class. */
5472 /* Set initial value to the reg itself. */
5474 /* We haven't seen the initializing insn yet */
5484 /* Add this class to loop_iv_list. */
5488 /* Put it in the array of biv register classes. */
5490 }
5492 /* Update IV_CLASS entry for this biv. */
5500 {
5505 {
5509 }
5510 else
5511 {
5515 }
5516 }
5517 }
5518 \f
5519 /* Fill in the data about one giv.
5520 V is the `struct induction' in which we record the giv. (It is
5521 allocated by the caller, with alloca.)
5522 INSN is the insn that sets it.
5523 BENEFIT estimates the savings from deleting this insn.
5524 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5525 into a register or is used as a memory address.
5527 SRC_REG is the biv reg which the giv is computed from.
5528 DEST_REG is the giv's reg (if the giv is stored in a reg).
5529 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5530 LOCATION points to the place where this giv's value appears in INSN. */
5532 static void
5535 loop_end)
5537 rtx insn;
5538 rtx src_reg;
5539 rtx dest_reg;
5546 {
5575 /* The v->always_computable field is used in update_giv_derive, to
5576 determine whether a giv can be used to derive another giv. For a
5577 DEST_REG giv, INSN computes a new value for the giv, so its value
5578 isn't computable if INSN insn't executed every iteration.
5579 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5580 it does not compute a new value. Hence the value is always computable
5581 regardless of whether INSN is executed each iteration. */
5585 else
5591 {
5594 }
5596 {
5602 /* If the lifetime is zero, it means that this register is
5603 really a dead store. So mark this as a giv that can be
5604 ignored. This will not prevent the biv from being eliminated. */
5610 }
5612 /* Add the giv to the class of givs computed from one biv. */
5616 {
5619 /* Don't count DEST_ADDR. This is supposed to count the number of
5620 insns that calculate givs. */
5624 }
5625 else
5626 /* Fatal error, biv missing for this giv? */
5631 else
5632 {
5633 /* The giv can be replaced outright by the reduced register only if all
5634 of the following conditions are true:
5635 - the insn that sets the giv is always executed on any iteration
5636 on which the giv is used at all
5637 (there are two ways to deduce this:
5638 either the insn is executed on every iteration,
5639 or all uses follow that insn in the same basic block),
5640 - the giv is not used outside the loop
5641 - no assignments to the biv occur during the giv's lifetime. */
5644 /* Previous line always fails if INSN was moved by loop opt. */
5646 && (! not_every_iteration
5648 {
5649 /* Now check that there are no assignments to the biv within the
5650 giv's lifetime. This requires two separate checks. */
5652 /* Check each biv update, and fail if any are between the first
5653 and last use of the giv.
5655 If this loop contains an inner loop that was unrolled, then
5656 the insn modifying the biv may have been emitted by the loop
5657 unrolling code, and hence does not have a valid luid. Just
5658 mark the biv as not replaceable in this case. It is not very
5659 useful as a biv, because it is used in two different loops.
5660 It is very unlikely that we would be able to optimize the giv
5661 using this biv anyways. */
5665 {
5671 {
5675 }
5676 }
5678 /* If there are any backwards branches that go from after the
5679 biv update to before it, then this giv is not replaceable. */
5683 {
5687 }
5688 }
5689 else
5690 {
5691 /* May still be replaceable, we don't have enough info here to
5692 decide. */
5695 }
5696 }
5698 /* Record whether the add_val contains a const_int, for later use by
5699 combine_givs. */
5700 {
5705 ;
5709 {
5711 {
5716 else
5718 }
5721 }
5722 }
5725 {
5729 else
5745 {
5748 }
5749 else
5750 {
5753 }
5756 {
5759 }
5760 else
5761 {
5764 }
5765 }
5770 }
5773 /* All this does is determine whether a giv can be made replaceable because
5774 its final value can be calculated. This code can not be part of record_giv
5775 above, because final_giv_value requires that the number of loop iterations
5776 be known, and that can not be accurately calculated until after all givs
5777 have been identified. */
5779 static void
5784 {
5790 /* DEST_ADDR givs will never reach here, because they are always marked
5791 replaceable above in record_giv. */
5793 /* The giv can be replaced outright by the reduced register only if all
5794 of the following conditions are true:
5795 - the insn that sets the giv is always executed on any iteration
5796 on which the giv is used at all
5797 (there are two ways to deduce this:
5798 either the insn is executed on every iteration,
5799 or all uses follow that insn in the same basic block),
5800 - its final value can be calculated (this condition is different
5801 than the one above in record_giv)
5802 - no assignments to the biv occur during the giv's lifetime. */
5804 #if 0
5805 /* This is only called now when replaceable is known to be false. */
5806 /* Clear replaceable, so that it won't confuse final_giv_value. */
5808 #endif
5812 {
5815 rtx last_giv_use;
5819 /* When trying to determine whether or not a biv increment occurs
5820 during the lifetime of the giv, we can ignore uses of the variable
5821 outside the loop because final_value is true. Hence we can not
5822 use regno_last_uid and regno_first_uid as above in record_giv. */
5824 /* Search the loop to determine whether any assignments to the
5825 biv occur during the giv's lifetime. Start with the insn
5826 that sets the giv, and search around the loop until we come
5827 back to that insn again.
5829 Also fail if there is a jump within the giv's lifetime that jumps
5830 to somewhere outside the lifetime but still within the loop. This
5831 catches spaghetti code where the execution order is not linear, and
5832 hence the above test fails. Here we assume that the giv lifetime
5833 does not extend from one iteration of the loop to the next, so as
5834 to make the test easier. Since the lifetime isn't known yet,
5835 this requires two loops. See also record_giv above. */
5840 {
5849 {
5851 {
5853 {
5857 }
5858 }
5863 }
5864 }
5866 /* Now that the lifetime of the giv is known, check for branches
5867 from within the lifetime to outside the lifetime if it is still
5868 replaceable. */
5871 {
5874 {
5887 {
5896 }
5897 }
5898 }
5900 /* If it is replaceable, then save the final value. */
5903 }
5908 }
5909 \f
5910 /* Update the status of whether a giv can derive other givs.
5912 We need to do something special if there is or may be an update to the biv
5913 between the time the giv is defined and the time it is used to derive
5914 another giv.
5916 In addition, a giv that is only conditionally set is not allowed to
5917 derive another giv once a label has been passed.
5919 The cases we look at are when a label or an update to a biv is passed. */
5921 static void
5923 rtx p;
5924 {
5927 rtx tem;
5930 /* Search all IV classes, then all bivs, and finally all givs.
5932 There are three cases we are concerned with. First we have the situation
5933 of a giv that is only updated conditionally. In that case, it may not
5934 derive any givs after a label is passed.
5936 The second case is when a biv update occurs, or may occur, after the
5937 definition of a giv. For certain biv updates (see below) that are
5938 known to occur between the giv definition and use, we can adjust the
5939 giv definition. For others, or when the biv update is conditional,
5940 we must prevent the giv from deriving any other givs. There are two
5941 sub-cases within this case.
5943 If this is a label, we are concerned with any biv update that is done
5944 conditionally, since it may be done after the giv is defined followed by
5945 a branch here (actually, we need to pass both a jump and a label, but
5946 this extra tracking doesn't seem worth it).
5948 If this is a jump, we are concerned about any biv update that may be
5949 executed multiple times. We are actually only concerned about
5950 backward jumps, but it is probably not worth performing the test
5951 on the jump again here.
5953 If this is a biv update, we must adjust the giv status to show that a
5954 subsequent biv update was performed. If this adjustment cannot be done,
5955 the giv cannot derive further givs. */
5961 {
5963 {
5964 /* If cant_derive is already true, there is no point in
5965 checking all of these conditions again. */
5969 /* If this giv is conditionally set and we have passed a label,
5970 it cannot derive anything. */
5974 /* Skip givs that have mult_val == 0, since
5975 they are really invariants. Also skip those that are
5976 replaceable, since we know their lifetime doesn't contain
5977 any biv update. */
5981 /* The only way we can allow this giv to derive another
5982 is if this is a biv increment and we can form the product
5983 of biv->add_val and giv->mult_val. In this case, we will
5984 be able to compute a compensation. */
5986 {
5996 tem = simplify_giv_expr
6002 else
6004 }
6008 }
6009 }
6010 }
6011 \f
6012 /* Check whether an insn is an increment legitimate for a basic induction var.
6013 X is the source of insn P, or a part of it.
6014 MODE is the mode in which X should be interpreted.
6016 DEST_REG is the putative biv, also the destination of the insn.
6017 We accept patterns of these forms:
6018 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6019 REG = INVARIANT + REG
6021 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6022 store the additive term into *INC_VAL, and store the place where
6023 we found the additive term into *LOCATION.
6025 If X is an assignment of an invariant into DEST_REG, we set
6026 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6028 We also want to detect a BIV when it corresponds to a variable
6029 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6030 of the variable may be a PLUS that adds a SUBREG of that variable to
6031 an invariant and then sign- or zero-extends the result of the PLUS
6032 into the variable.
6034 Most GIVs in such cases will be in the promoted mode, since that is the
6035 probably the natural computation mode (and almost certainly the mode
6036 used for addresses) on the machine. So we view the pseudo-reg containing
6037 the variable as the BIV, as if it were simply incremented.
6039 Note that treating the entire pseudo as a BIV will result in making
6040 simple increments to any GIVs based on it. However, if the variable
6041 overflows in its declared mode but not its promoted mode, the result will
6042 be incorrect. This is acceptable if the variable is signed, since
6043 overflows in such cases are undefined, but not if it is unsigned, since
6044 those overflows are defined. So we only check for SIGN_EXTEND and
6045 not ZERO_EXTEND.
6047 If we cannot find a biv, we return 0. */
6049 static int
6053 rtx p;
6054 rtx dest_reg;
6058 {
6066 {
6072 {
6074 }
6079 {
6081 }
6082 else
6095 /* If this is a SUBREG for a promoted variable, check the inner
6096 value. */
6103 /* If this register is assigned in a previous insn, look at its
6104 source, but don't go outside the loop or past a label. */
6108 {
6134 }
6135 /* ... fall through ... */
6137 /* Can accept constant setting of biv only when inside inner most loop.
6138 Otherwise, a biv of an inner loop may be incorrectly recognized
6139 as a biv of the outer loop,
6140 causing code to be moved INTO the inner loop. */
6147 /* convert_modes aborts if we try to convert to or from CCmode, so just
6148 exclude that case. It is very unlikely that a condition code value
6149 would be a useful iterator anyways. */
6153 {
6154 /* Possible bug here? Perhaps we don't know the mode of X. */
6158 }
6159 else
6167 /* Similar, since this can be a sign extension. */
6172 ;
6185 location);
6190 }
6191 }
6192 \f
6193 /* A general induction variable (giv) is any quantity that is a linear
6194 function of a basic induction variable,
6195 i.e. giv = biv * mult_val + add_val.
6196 The coefficients can be any loop invariant quantity.
6197 A giv need not be computed directly from the biv;
6198 it can be computed by way of other givs. */
6200 /* Determine whether X computes a giv.
6201 If it does, return a nonzero value
6202 which is the benefit from eliminating the computation of X;
6203 set *SRC_REG to the register of the biv that it is computed from;
6204 set *ADD_VAL and *MULT_VAL to the coefficients,
6205 such that the value of X is biv * mult + add; */
6207 static int
6209 rtx x;
6215 {
6219 /* If this is an invariant, forget it, it isn't a giv. */
6223 /* See if the expression could be a giv and get its form.
6224 Mark our place on the obstack in case we don't find a giv. */
6229 {
6232 }
6235 {
6238 /* Since this is now an invariant and wasn't before, it must be a giv
6239 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6240 with. */
6247 /* This is equivalent to a BIV. */
6254 /* Either (plus (biv) (invar)) or
6255 (plus (mult (biv) (invar_1)) (invar_2)). */
6257 {
6260 }
6261 else
6262 {
6265 }
6270 /* ADD_VAL is zero. */
6278 }
6280 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6281 unless they are CONST_INT). */
6288 {
6289 #ifdef ADDRESS_COST
6291 #else
6293 #endif
6294 }
6295 else
6298 /* Always return true if this is a giv so it will be detected as such,
6299 even if the benefit is zero or negative. This allows elimination
6300 of bivs that might otherwise not be eliminated. */
6302 }
6303 \f
6304 /* Given an expression, X, try to form it as a linear function of a biv.
6305 We will canonicalize it to be of the form
6306 (plus (mult (BIV) (invar_1))
6307 (invar_2))
6308 with possible degeneracies.
6310 The invariant expressions must each be of a form that can be used as a
6311 machine operand. We surround then with a USE rtx (a hack, but localized
6312 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6313 routine; it is the caller's responsibility to strip them.
6315 If no such canonicalization is possible (i.e., two biv's are used or an
6316 expression that is neither invariant nor a biv or giv), this routine
6317 returns 0.
6319 For a non-zero return, the result will have a code of CONST_INT, USE,
6320 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6322 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6329 static rtx
6331 rtx x;
6333 {
6336 rtx tem;
6338 /* If this is not an integer mode, or if we cannot do arithmetic in this
6339 mode, this can't be a giv. */
6346 {
6353 /* Put constant last, CONST_INT last if both constant. */
6361 /* Handle addition of zero, then addition of an invariant. */
6366 {
6369 /* Adding two invariants must result in an invariant, so enclose
6370 addition operation inside a USE and return it. */
6380 else
6389 /* biv + invar or mult + invar. Return sum. */
6393 /* (a + invar_1) + invar_2. Associate. */
6394 return
6399 arg1)),
6400 benefit);
6404 }
6406 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6407 MULT to reduce cases. */
6413 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6414 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6415 Recurse to associate the second PLUS. */
6420 return
6425 benefit);
6427 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6439 benefit);
6442 /* Handle "a - b" as "a + b * (-1)". */
6447 constm1_rtx)),
6448 benefit);
6456 /* Put constant last, CONST_INT last if both constant. */
6461 /* If second argument is not now constant, not giv. */
6465 /* Handle multiply by 0 or 1. */
6473 {
6475 /* biv * invar. Done. */
6479 /* Product of two constants. */
6483 /* invar * invar. It is a giv, but very few of these will
6484 actually pay off, so limit to simple registers. */
6494 {
6498 }
6499 else
6504 /* (a * invar_1) * invar_2. Associate. */
6509 arg1)),
6510 benefit);
6513 /* (a + invar_1) * invar_2. Distribute. */
6517 arg1),
6520 arg1)),
6521 benefit);
6525 }
6528 /* Shift by constant is multiply by power of two. */
6532 return
6537 benefit);
6540 /* "-a" is "a * (-1)" */
6542 benefit);
6545 /* "~a" is "-a - 1". Silly, but easy. */
6548 const1_rtx),
6549 benefit);
6552 /* Already in proper form for invariant. */
6556 /* If this is a new register, we can't deal with it. */
6560 /* Check for biv or giv. */
6562 {
6566 {
6569 /* Form expression from giv and add benefit. Ensure this giv
6570 can derive another and subtract any needed adjustment if so. */
6582 }
6585 /* If it isn't an induction variable, and it is invariant, we
6586 may be able to simplify things further by looking through
6587 the bits we just moved outside the loop. */
6589 {
6594 {
6595 /* Ok, we found a match. Substitute and simplify. */
6597 /* If we match another movable, we must use that, as
6598 this one is going away. */
6602 /* If consec is non-zero, this is a member of a group of
6603 instructions that were moved together. We handle this
6604 case only to the point of seeking to the last insn and
6605 looking for a REG_EQUAL. Fail if we don't find one. */
6607 {
6615 }
6616 else
6617 {
6621 }
6624 {
6625 /* What we are most interested in is pointer
6626 arithmetic on invariants -- only take
6627 patterns we may be able to do something with. */
6633 {
6637 }
6642 {
6646 }
6647 }
6649 }
6650 }
6652 }
6654 /* Fall through to general case. */
6656 /* If invariant, return as USE (unless CONST_INT).
6657 Otherwise, not giv. */
6662 {
6671 }
6672 else
6674 }
6675 }
6677 /* This routine folds invariants such that there is only ever one
6678 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6680 static rtx
6683 {
6689 {
6692 }
6695 {
6698 }
6699 else
6700 {
6703 }
6704 }
6706 static rtx
6710 {
6712 {
6716 else
6719 }
6722 else
6725 }
6726 \f
6727 /* Help detect a giv that is calculated by several consecutive insns;
6728 for example,
6729 giv = biv * M
6730 giv = giv + A
6731 The caller has already identified the first insn P as having a giv as dest;
6732 we check that all other insns that set the same register follow
6733 immediately after P, that they alter nothing else,
6734 and that the result of the last is still a giv.
6736 The value is 0 if the reg set in P is not really a giv.
6737 Otherwise, the value is the amount gained by eliminating
6738 all the consecutive insns that compute the value.
6740 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6741 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6743 The coefficients of the ultimate giv value are stored in
6744 *MULT_VAL and *ADD_VAL. */
6746 static int
6750 rtx p;
6751 rtx src_reg;
6752 rtx dest_reg;
6756 {
6760 rtx temp;
6761 rtx set;
6763 /* Indicate that this is a giv so that we can update the value produced in
6764 each insn of the multi-insn sequence.
6766 This induction structure will be used only by the call to
6767 general_induction_var below, so we can allocate it on our stack.
6768 If this is a giv, our caller will replace the induct var entry with
6769 a new induction structure. */
6785 {
6789 /* If libcall, skip to end of call sequence. */
6799 /* Giv created by equivalent expression. */
6804 {
6808 count--;
6812 }
6814 {
6815 /* Allow insns that set something other than this giv to a
6816 constant. Such insns are needed on machines which cannot
6817 include long constants and should not disqualify a giv. */
6826 }
6827 }
6831 }
6832 \f
6833 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6834 represented by G1. If no such expression can be found, or it is clear that
6835 it cannot possibly be a valid address, 0 is returned.
6837 To perform the computation, we note that
6838 G1 = x * v + a and
6839 G2 = y * v + b
6840 where `v' is the biv.
6842 So G2 = (y/b) * G1 + (b - a*y/x).
6844 Note that MULT = y/x.
6846 Update: A and B are now allowed to be additive expressions such that
6847 B contains all variables in A. That is, computing B-A will not require
6848 subtracting variables. */
6850 static rtx
6853 {
6854 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6859 /* If MULT is not 1, we cannot handle A with non-constants, since we
6860 would then be required to subtract multiples of the registers in A.
6861 This is theoretically possible, and may even apply to some Fortran
6862 constructs, but it is a lot of work and we do not attempt it here. */
6867 /* In general these structures are sorted top to bottom (down the PLUS
6868 chain), but not left to right across the PLUS. If B is a higher
6869 order giv than A, we can strip one level and recurse. If A is higher
6870 order, we'll eventually bail out, but won't know that until the end.
6871 If they are the same, we'll strip one level around this loop. */
6874 {
6886 /* We matched: remove one reg completely. */
6889 /* An alternate match. */
6892 /* An alternate match. */
6894 else
6895 {
6896 /* Indicates an extra register in B. Strip one level from B and
6897 recurse, hoping B was the higher order expression. */
6902 }
6903 }
6905 /* Here we are at the last level of A, go through the cases hoping to
6906 get rid of everything but a constant. */
6909 {
6922 }
6924 {
6926 }
6928 {
6933 else
6935 }
6940 }
6942 rtx
6945 {
6948 /* The value that G1 will be multiplied by must be a constant integer. Also,
6949 the only chance we have of getting a valid address is if b*c/a (see above
6950 for notation) is also an integer. */
6953 {
6958 }
6961 else
6962 {
6963 /* ??? Find out if the one is a multiple of the other? */
6965 }
6969 {
6970 /* Failed. If we've got a multiplication factor between G1 and G2,
6971 scale G1's addend and try again. */
6973 {
6977 {
6978 HOST_WIDE_INT m;
6982 }
6983 else
6984 {
6986 mult);
6987 }
6990 }
6991 }
6995 /* Form simplified final result. */
7000 else
7005 else
7006 {
7009 {
7013 }
7016 }
7018 }
7019 \f
7020 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7021 represented by G1. This indicates that G2 should be combined with G1 and
7022 that G2 can use (either directly or via an address expression) a register
7023 used to represent G1. */
7025 static rtx
7028 {
7031 /* If these givs are identical, they can be combined. We use the results
7032 of express_from because the addends are not in a canonical form, so
7033 rtx_equal_p is a weaker test. */
7034 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7035 combination to be the other way round. */
7038 {
7040 }
7042 /* If G2 can be expressed as a function of G1 and that function is valid
7043 as an address and no more expensive than using a register for G2,
7044 the expression of G2 in terms of G1 can be used. */
7048 /* ??? Looses, especially with -fforce-addr, where *g2->location
7049 will always be a register, and so anything more complicated
7050 gets discarded. */
7051 #if 0
7052 #ifdef ADDRESS_COST
7054 #else
7056 #endif
7057 #endif
7058 )
7059 {
7061 }
7064 }
7065 \f
7066 struct combine_givs_stats
7067 {
7070 };
7072 static int
7076 {
7083 /* Stabilize the sort. */
7087 }
7089 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7090 any other. If so, point SAME to the giv combined with and set NEW_REG to
7091 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7092 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7094 static void
7097 {
7098 /* Additional benefit to add for being combined multiple times. */
7106 /* Count givs, because bl->giv_count is incorrect here. */
7110 giv_count++;
7112 giv_array
7126 {
7128 rtx single_use;
7133 /* If a DEST_REG GIV is used only once, do not allow it to combine
7134 with anything, for in doing so we will gain nothing that cannot
7135 be had by simply letting the GIV with which we would have combined
7136 to be reduced on its own. The losage shows up in particular with
7137 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7138 be seen elsewhere as well. */
7145 /* Add an additional weight for zero addends. */
7150 {
7151 rtx this_combine;
7156 {
7159 }
7160 }
7162 }
7164 /* Iterate, combining until we can't. */
7165 restart:
7169 {
7172 {
7178 }
7180 }
7183 {
7189 /* If it has already been combined, skip. */
7194 {
7197 /* If it has already been combined, skip. */
7199 {
7209 /* ??? The new final_[bg]iv_value code does a much better job
7210 of finding replaceable giv's, and hence this code may no
7211 longer be necessary. */
7215 /* To help optimize the next set of combinations, remove
7216 this giv from the benefits of other potential mates. */
7218 {
7222 }
7228 }
7229 }
7231 /* To help optimize the next set of combinations, remove
7232 this giv from the benefits of other potential mates. */
7234 {
7236 {
7240 }
7244 /* We've finished with this giv, and everything it touched.
7245 Restart the combination so that proper weights for the
7246 rest of the givs are properly taken into account. */
7247 /* ??? Ideally we would compact the arrays at this point, so
7248 as to not cover old ground. But sanely compacting
7249 can_combine is tricky. */
7251 }
7252 }
7253 }
7254 \f
7255 struct recombine_givs_stats
7256 {
7259 };
7261 /* Used below as comparison function for qsort. We want a ascending luid
7262 when scanning the array starting at the end, thus the arguments are
7263 used in reverse. */
7264 static int
7268 {
7275 /* Stabilize the sort. */
7279 }
7281 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7282 look for the start of life of a giv where the start has not been seen
7283 yet to unlock the search for the end of its life.
7284 Only consider givs that belong to BIV.
7285 Return the total number of lifetime ends that have been found. */
7286 static int
7290 {
7298 {
7300 {
7303 {
7311 {
7312 /* If we see a 0 here for end_luid, it means that we have
7313 scanned the entire loop without finding any use at all.
7314 We must not predicate this code on a start_luid match
7315 since that would make the test fail for givs that have
7316 been hoisted out of inner loops. */
7318 {
7321 }
7324 }
7326 }
7328 }
7330 {
7338 {
7343 }
7345 }
7353 }
7357 {
7364 }
7366 }
7368 /* For each giv that has been combined with another, look if
7369 we can combine it with the most recently used one instead.
7370 This tends to shorten giv lifetimes, and helps the next step:
7371 try to derive givs from other givs. */
7372 static void
7377 {
7385 {
7387 giv_count++;
7388 }
7389 giv_array
7393 /* Initialize stats and set up the ix field for each giv in stats to name
7394 the corresponding index into stats. */
7396 {
7397 rtx p;
7403 /* If this giv has been hoisted out of an inner loop, use the luid of
7404 the previous insn. */
7408 i++;
7409 }
7413 /* Set up the ix field for each giv in stats to name
7414 the corresponding index into stats, and
7415 do the actual most-recently-used recombination. */
7417 {
7421 {
7423 rtx new_combine;
7425 /* combine_givs_p actually says if we can make this transformation.
7426 The other tests are here only to avoid keeping a giv alive
7427 that could otherwise be eliminated. */
7433 {
7438 /* No need to update lifetimes / benefits here since we have
7439 already decided what to reduce. */
7442 {
7448 }
7450 }
7452 }
7460 }
7463 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7464 lifetime ends from regscan info. */
7466 {
7471 {
7472 /* Loop unrolling of an inner loop can even create new DEST_REG
7473 givs. */
7474 rtx p;
7480 }
7482 {
7484 {
7487 }
7489 {
7490 rtx p;
7491 /* This insn has been created by loop optimization on an inner
7492 loop. We don't have a proper start_luid that will match
7493 when we see the first set. But we do know that there will
7494 be no use before the set, so we can set end_luid to 0 so that
7495 we'll start looking for the last use right away. */
7500 ends_need_computing++;
7501 }
7502 else
7503 {
7508 /* Find the first insn that sets the giv, so that we can verify
7509 if this giv's lifetime wraps around the loop. We also need
7510 the luid of the first setting insn in order to detect the
7511 last use properly. */
7513 {
7516 count--;
7517 }
7521 {
7523 ends_need_computing++;
7524 }
7525 else
7526 {
7529 {
7531 ends_need_computing++;
7532 }
7533 }
7534 }
7535 }
7536 }
7538 /* If the regscan information was unconclusive for one or more DEST_REG
7539 givs, scan the all insn in the loop to find out lifetime ends. */
7541 {
7545 do
7546 {
7553 }
7555 }
7557 /* Set start_luid back to the last insn that sets the giv. This allows
7558 more combinations. */
7560 {
7566 }
7568 /* Now adjust lifetime ends by taking combined givs into account. */
7570 {
7578 {
7581 /* Use unsigned arithmetic to model loop wrap-around. */
7585 }
7586 }
7590 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7591 same mult_val and non-overlapping lifetime. This reduces register
7592 pressure.
7593 Once we find a DEST_REG giv that is suitable to derive others from,
7594 we set last_giv to this giv, and try to derive as many other DEST_REG
7595 givs from it without joining overlapping lifetimes. If we then
7596 encounter a DEST_REG giv that we can't derive, we set rescan to the
7597 index for this giv (unless rescan is already set).
7598 When we are finished with the current LAST_GIV (i.e. the inner loop
7599 terminates), we start again with rescan, which then becomes the new
7600 LAST_GIV. */
7602 {
7606 {
7607 rtx sum;
7613 {
7614 /* Don't use a giv that's likely to be dead to derive
7615 others - that would be likely to keep that giv alive. */
7617 {
7621 }
7623 }
7624 /* Use unsigned arithmetic to model loop wrap around. */
7629 /* Check that the giv insn we're about to use for deriving
7630 precedes all uses of that giv. Note that initializing the
7631 derived giv would defeat the purpose of reducing register
7632 pressure.
7633 ??? We could arrange to move the insn. */
7637 /* ??? Could handle libcalls, but would need more logic. */
7639 /* We would really like to know if for any giv that v
7640 is combined with, v->insn or any intervening biv increment
7641 dominates that combined giv. However, we
7642 don't have this detailed control flow information.
7643 N.B. since last_giv will be reduced, it is valid
7644 anywhere in the loop, so we don't need to check the
7645 validity of last_giv.
7646 We rely here on the fact that v->always_executed implies that
7647 there is no jump to someplace else in the loop before the
7648 giv insn, and hence any insn that is executed before the
7649 giv insn in the loop will have a lower luid. */
7652 /* Make sure we don't make the add more expensive. ADD_COST
7653 doesn't take different costs of registers and constants into
7654 account, so compare the cost of the actual SET_SRCs. */
7657 /* ??? unroll can't understand anything but reg + const_int
7658 sums. It would be cleaner to fix unroll. */
7665 {
7670 {
7676 }
7677 }
7680 }
7681 }
7682 }
7683 \f
7684 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7686 void
7692 rtx insert_before;
7693 {
7694 rtx seq;
7695 rtx result;
7697 /* Prevent unexpected sharing of these rtx. */
7701 /* Increase the lifetime of any invariants moved further in code. */
7715 /* It is entirely possible that the expansion created lots of new
7716 registers. Iterate over the sequence we just created and
7717 record them all. */
7720 {
7723 {
7727 }
7728 }
7732 }
7733 \f
7734 /* Test whether A * B can be computed without
7735 an actual multiply insn. Value is 1 if so. */
7737 static int
7739 rtx a;
7740 rtx b;
7741 {
7743 rtx tmp;
7748 /* If only one is constant, make it B. */
7752 /* If first constant, both constant, so don't need multiply. */
7756 /* If second not constant, neither is constant, so would need multiply. */
7760 /* One operand is constant, so might not need multiply insn. Generate the
7761 code for the multiply and see if a call or multiply, or long sequence
7762 of insns is generated. */
7771 {
7776 else
7778 {
7787 {
7790 }
7791 }
7792 }
7801 /* Free any storage we obtained in generating this multiply and restore rtl
7802 allocation to its normal obstack. */
7807 }
7808 \f
7809 /* Check to see if loop can be terminated by a "decrement and branch until
7810 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7811 Also try reversing an increment loop to a decrement loop
7812 to see if the optimization can be performed.
7813 Value is nonzero if optimization was performed. */
7815 /* This is useful even if the architecture doesn't have such an insn,
7816 because it might change a loops which increments from 0 to n to a loop
7817 which decrements from n to 0. A loop that decrements to zero is usually
7818 faster than one that increments from zero. */
7820 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7821 such as approx_final_value, biv_total_increment, loop_iterations, and
7822 final_[bg]iv_value. */
7824 static int
7826 rtx loop_end;
7828 rtx loop_start;
7830 {
7832 rtx reg;
7833 rtx jump_label;
7834 rtx final_value;
7835 rtx start_value;
7836 rtx new_add_val;
7837 rtx comparison;
7838 rtx before_comparison;
7839 rtx p;
7840 rtx jump;
7841 rtx first_compare;
7844 /* If last insn is a conditional branch, and the insn before tests a
7845 register value, try to optimize it. Otherwise, we can't do anything. */
7852 /* Try to compute whether the compare/branch at the loop end is one or
7853 two instructions. */
7859 else
7862 /* Check all of the bivs to see if the compare uses one of them.
7863 Skip biv's set more than once because we can't guarantee that
7864 it will be zero on the last iteration. Also skip if the biv is
7865 used between its update and the test insn. */
7868 {
7872 first_compare))
7874 }
7879 /* Look for the case where the basic induction variable is always
7880 nonnegative, and equals zero on the last iteration.
7881 In this case, add a reg_note REG_NONNEG, which allows the
7882 m68k DBRA instruction to be used. */
7890 {
7891 /* Initial value must be greater than 0,
7892 init_val % -dec_value == 0 to ensure that it equals zero on
7893 the last iteration */
7899 {
7900 /* register always nonnegative, add REG_NOTE to branch */
7907 }
7909 /* If the decrement is 1 and the value was tested as >= 0 before
7910 the loop, then we can safely optimize. */
7912 {
7925 {
7932 }
7933 }
7934 }
7937 {
7938 /* Try to change inc to dec, so can apply above optimization. */
7939 /* Can do this if:
7940 all registers modified are induction variables or invariant,
7941 all memory references have non-overlapping addresses
7942 (obviously true if only one write)
7943 allow 2 insns for the compare/jump at the end of the loop. */
7944 /* Also, we must avoid any instructions which use both the reversed
7945 biv and another biv. Such instructions will fail if the loop is
7946 reversed. We meet this condition by requiring that either
7947 no_use_except_counting is true, or else that there is only
7948 one biv. */
7950 /* 1 if the iteration var is used only to count iterations. */
7952 /* 1 if the loop has no memory store, or it has a single memory store
7953 which is reversible. */
7958 {
7961 /* If there are no givs for this biv, and the only exit is the
7962 fall through at the end of the loop, then
7963 see if perhaps there are no uses except to count. */
7967 {
7972 /* An insn that sets the biv is okay. */
7973 ;
7977 {
7978 /* If either of these insns uses the biv and sets a pseudo
7979 that has more than one usage, then the biv has uses
7980 other than counting since it's used to derive a value
7981 that is used more than one time. */
7986 {
7989 }
7990 }
7992 {
7995 }
7996 }
7997 }
8002 {
8007 /* If the loop has a single store, and the destination address is
8008 invariant, then we can't reverse the loop, because this address
8009 might then have the wrong value at loop exit.
8010 This would work if the source was invariant also, however, in that
8011 case, the insn should have been moved out of the loop. */
8014 {
8017 reversible_mem_store
8018 = (! unknown_address_altered
8019 && ! unknown_constant_address_altered
8022 /* If the store depends on a register that is set after the
8023 store, it depends on the initial value, and is thus not
8024 reversible. */
8026 {
8032 }
8033 }
8034 }
8035 else
8038 /* This code only acts for innermost loops. Also it simplifies
8039 the memory address check by only reversing loops with
8040 zero or one memory access.
8041 Two memory accesses could involve parts of the same array,
8042 and that can't be reversed.
8043 If the biv is used only for counting, than we don't need to worry
8044 about all these things. */
8049 && reversible_mem_store
8054 {
8055 rtx tem;
8057 /* Loop can be reversed. */
8061 /* Now check other conditions:
8063 The increment must be a constant, as must the initial value,
8064 and the comparison code must be LT.
8066 This test can probably be improved since +/- 1 in the constant
8067 can be obtained by changing LT to LE and vice versa; this is
8068 confusing. */
8071 /* for constants, LE gets turned into LT */
8075 {
8086 comparison_const_width
8088 else
8089 comparison_const_width
8093 comparison_sign_mask
8096 /* If the comparison value is not a loop invariant, then we
8097 can not reverse this loop.
8099 ??? If the insns which initialize the comparison value as
8100 a whole compute an invariant result, then we could move
8101 them out of the loop and proceed with loop reversal. */
8109 /* Normalize the initial value if it is an integer and
8110 has no other use except as a counter. This will allow
8111 a few more loops to be reversed. */
8115 {
8117 /* The code below requires comparison_val to be a multiple
8118 of add_val in order to do the loop reversal, so
8119 round up comparison_val to a multiple of add_val.
8120 Since comparison_value is constant, we know that the
8121 current comparison code is LT. */
8123 comparison_val
8125 /* We postpone overflow checks for COMPARISON_VAL here;
8126 even if there is an overflow, we might still be able to
8127 reverse the loop, if converting the loop exit test to
8128 NE is possible. */
8130 }
8132 /* First check if we can do a vanilla loop reversal. */
8134 /* If we have a decrement_and_branch_on_count,
8135 prefer the NE test, since this will allow that
8136 instruction to be generated. Note that we must
8137 use a vanilla loop reversal if the biv is used to
8138 calculate a giv or has a non-counting use. */
8139 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8140 && defined (HAVE_decrement_and_branch_on_count)
8144 #endif
8146 /* Now do postponed overflow checks on COMPARISON_VAL. */
8149 {
8150 /* Register will always be nonnegative, with value
8151 0 on last iteration */
8155 }
8159 {
8162 }
8163 else
8169 /* If the initial value is not zero, or if the comparison
8170 value is not an exact multiple of the increment, then we
8171 can not reverse this loop. */
8174 {
8177 }
8178 else
8179 {
8182 }
8186 /* Reset these in case we normalized the initial value
8187 and comparison value above. */
8190 {
8192 final_value
8194 }
8197 /* Save some info needed to produce the new insns. */
8204 /* Set start_value; if this is not a CONST_INT, we need
8205 to generate a SUB.
8206 Initialize biv to start_value before loop start.
8207 The old initializing insn will be deleted as a
8208 dead store by flow.c. */
8211 {
8214 loop_start);
8215 }
8217 {
8220 enum insn_code icode
8229 start_value
8233 loop_start);
8237 }
8239 {
8241 enum insn_code icode
8249 start_value
8253 loop_start);
8254 }
8255 else
8256 /* We could handle the other cases too, but it'll be
8257 better to have a testcase first. */
8260 /* We may not have a single insn which can increment a reg, so
8261 create a sequence to hold all the insns from expand_inc. */
8270 /* Update biv info to reflect its new status. */
8275 /* Update loop info. */
8284 /* Inc LABEL_NUSES so that delete_insn will
8285 not delete the label. */
8288 /* Emit an insn after the end of the loop to set the biv's
8289 proper exit value if it is used anywhere outside the loop. */
8294 loop_end);
8296 /* Delete compare/branch at end of loop. */
8301 /* Add new compare/branch insn at end of loop. */
8313 ;
8319 {
8321 {
8322 /* Increment of LABEL_NUSES done above. */
8323 /* Register is now always nonnegative,
8324 so add REG_NONNEG note to the branch. */
8327 }
8329 }
8331 /* No insn may reference both the reversed and another biv or it
8332 will fail (see comment near the top of the loop reversal
8333 code).
8334 Earlier on, we have verified that the biv has no use except
8335 counting, or it is the only biv in this function.
8336 However, the code that computes no_use_except_counting does
8337 not verify reg notes. It's possible to have an insn that
8338 references another biv, and has a REG_EQUAL note with an
8339 expression based on the reversed biv. To avoid this case,
8340 remove all REG_EQUAL notes based on the reversed biv
8341 here. */
8344 {
8347 /* If this is a set of a GIV based on the reversed biv, any
8348 REG_EQUAL notes should still be correct. */
8355 {
8360 else
8362 }
8363 }
8365 /* Mark that this biv has been reversed. Each giv which depends
8366 on this biv, and which is also live past the end of the loop
8367 will have to be fixed up. */
8372 {
8376 else
8378 }
8381 }
8382 }
8383 }
8386 }
8387 \f
8388 /* Verify whether the biv BL appears to be eliminable,
8389 based on the insns in the loop that refer to it.
8390 LOOP_START is the first insn of the loop, and END is the end insn.
8392 If ELIMINATE_P is non-zero, actually do the elimination.
8394 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8395 determine whether invariant insns should be placed inside or at the
8396 start of the loop. */
8398 static int
8401 rtx loop_start;
8402 rtx end;
8405 {
8407 rtx p;
8409 /* Scan all insns in the loop, stopping if we find one that uses the
8410 biv in a way that we cannot eliminate. */
8413 {
8417 /* If this is a libcall that sets a giv, skip ahead to its end. */
8419 {
8423 {
8428 {
8435 }
8436 }
8437 }
8441 {
8447 }
8448 }
8451 {
8456 }
8459 }
8460 \f
8461 /* INSN and REFERENCE are instructions in the same insn chain.
8462 Return non-zero if INSN is first. */
8464 int
8467 {
8471 {
8472 /* Start with test for not first so that INSN == REFERENCE yields not
8473 first. */
8479 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8480 previous insn, hence the <= comparison below does not work if
8481 P is a note. */
8492 }
8493 }
8495 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8496 the offset that we have to take into account due to auto-increment /
8497 div derivation is zero. */
8498 static int
8501 rtx insn;
8502 {
8503 /* If the giv V had the auto-inc address optimization applied
8504 to it, and INSN occurs between the giv insn and the biv
8505 insn, then we'd have to adjust the value used here.
8506 This is rare, so we don't bother to make this possible. */
8514 /* If the giv V was derived from another giv, and INSN does
8515 not occur between the giv insn and the biv insn, then we'd
8516 have to adjust the value used here. This is rare, so we don't
8517 bother to make this possible. */
8531 }
8533 /* If BL appears in X (part of the pattern of INSN), see if we can
8534 eliminate its use. If so, return 1. If not, return 0.
8536 If BIV does not appear in X, return 1.
8538 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8539 where extra insns should be added. Depending on how many items have been
8540 moved out of the loop, it will either be before INSN or at the start of
8541 the loop. */
8543 static int
8548 rtx where;
8549 {
8555 #ifdef HAVE_cc0
8557 #endif
8563 {
8565 /* If we haven't already been able to do something with this BIV,
8566 we can't eliminate it. */
8572 /* If this sets the BIV, it is not a problem. */
8576 /* If this is an insn that defines a giv, it is also ok because
8577 it will go away when the giv is reduced. */
8582 #ifdef HAVE_cc0
8584 {
8585 /* Can replace with any giv that was reduced and
8586 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8587 Require a constant for MULT_VAL, so we know it's nonzero.
8588 ??? We disable this optimization to avoid potential
8589 overflows. */
8597 {
8604 /* If the giv has the opposite direction of change,
8605 then reverse the comparison. */
8609 else
8612 /* We can probably test that giv's reduced reg. */
8615 }
8617 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8618 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8619 Require a constant for MULT_VAL, so we know it's nonzero.
8620 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8621 overflow problem. */
8632 {
8639 /* If the giv has the opposite direction of change,
8640 then reverse the comparison. */
8644 else
8648 /* Replace biv with the giv's reduced register. */
8653 /* Insn doesn't support that constant or invariant. Copy it
8654 into a register (it will be a loop invariant.) */
8658 where);
8660 /* Substitute the new register for its invariant value in
8661 the compare expression. */
8665 }
8666 }
8667 #endif
8674 /* See if either argument is the biv. */
8679 else
8683 {
8684 /* First try to replace with any giv that has constant positive
8685 mult_val and constant add_val. We might be able to support
8686 negative mult_val, but it seems complex to do it in general. */
8697 {
8704 /* Replace biv with the giv's reduced reg. */
8707 /* If all constants are actually constant integers and
8708 the derived constant can be directly placed in the COMPARE,
8709 do so. */
8719 /* Otherwise, load it into a register. */
8725 /* If that failed, put back the change we made above. */
8727 }
8729 /* Look for giv with positive constant mult_val and nonconst add_val.
8730 Insert insns to calculate new compare value.
8731 ??? Turn this off due to possible overflow. */
8738 {
8739 rtx tem;
8749 /* Replace biv with giv's reduced register. */
8753 /* Compute value to compare against. */
8755 /* Use it in this insn. */
8759 }
8760 }
8762 {
8764 {
8765 /* Look for giv with constant positive mult_val and nonconst
8766 add_val. Insert insns to compute new compare value.
8767 ??? Turn this off due to possible overflow. */
8774 {
8775 rtx tem;
8785 /* Replace biv with giv's reduced register. */
8789 /* Compute value to compare against. */
8795 }
8796 }
8798 /* This code has problems. Basically, you can't know when
8799 seeing if we will eliminate BL, whether a particular giv
8800 of ARG will be reduced. If it isn't going to be reduced,
8801 we can't eliminate BL. We can try forcing it to be reduced,
8802 but that can generate poor code.
8804 The problem is that the benefit of reducing TV, below should
8805 be increased if BL can actually be eliminated, but this means
8806 we might have to do a topological sort of the order in which
8807 we try to process biv. It doesn't seem worthwhile to do
8808 this sort of thing now. */
8810 #if 0
8811 /* Otherwise the reg compared with had better be a biv. */
8816 /* Look for a pair of givs, one for each biv,
8817 with identical coefficients. */
8819 {
8830 {
8837 /* Replace biv with its giv's reduced reg. */
8839 /* Replace other operand with the other giv's
8840 reduced reg. */
8843 }
8844 }
8845 #endif
8846 }
8848 /* If we get here, the biv can't be eliminated. */
8852 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8853 biv is used in it, since it will be replaced. */
8861 }
8863 /* See if any subexpression fails elimination. */
8866 {
8868 {
8881 }
8882 }
8885 }
8886 \f
8887 /* Return nonzero if the last use of REG
8888 is in an insn following INSN in the same basic block. */
8890 static int
8892 rtx reg;
8893 rtx insn;
8894 {
8895 rtx n;
8899 {
8902 }
8904 }
8905 \f
8906 /* Called via `note_stores' to record the initial value of a biv. Here we
8907 just record the location of the set and process it later. */
8909 static void
8911 rtx dest;
8912 rtx set;
8914 {
8924 /* If this is the first set found, record it. */
8926 {
8929 }
8930 }
8931 \f
8932 /* If any of the registers in X are "old" and currently have a last use earlier
8933 than INSN, update them to have a last use of INSN. Their actual last use
8934 will be the previous insn but it will not have a valid uid_luid so we can't
8935 use it. */
8937 static void
8939 rtx x;
8940 rtx insn;
8941 {
8942 /* Check for the case where INSN does not have a valid luid. In this case,
8943 there is no need to modify the regno_last_uid, as this can only happen
8944 when code is inserted after the loop_end to set a pseudo's final value,
8945 and hence this insn will never be the last use of x. */
8950 else
8951 {
8955 {
8961 }
8962 }
8963 }
8964 \f
8965 /* Given a jump insn JUMP, return the condition that will cause it to branch
8966 to its JUMP_LABEL. If the condition cannot be understood, or is an
8967 inequality floating-point comparison which needs to be reversed, 0 will
8968 be returned.
8970 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8971 insn used in locating the condition was found. If a replacement test
8972 of the condition is desired, it should be placed in front of that
8973 insn and we will be sure that the inputs are still valid.
8975 The condition will be returned in a canonical form to simplify testing by
8976 callers. Specifically:
8978 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8979 (2) Both operands will be machine operands; (cc0) will have been replaced.
8980 (3) If an operand is a constant, it will be the second operand.
8981 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8982 for GE, GEU, and LEU. */
8984 rtx
8986 rtx jump;
8988 {
8991 rtx set;
8992 rtx tem;
8998 /* If this is not a standard conditional jump, we can't parse it. */
9011 /* If this branches to JUMP_LABEL when the condition is false, reverse
9012 the condition. */
9017 /* If we are comparing a register with zero, see if the register is set
9018 in the previous insn to a COMPARE or a comparison operation. Perform
9019 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9020 in cse.c */
9023 {
9024 /* Set non-zero when we find something of interest. */
9027 #ifdef HAVE_cc0
9028 /* If comparison with cc0, import actual comparison from compare
9029 insn. */
9031 {
9042 }
9043 #endif
9045 /* If this is a COMPARE, pick up the two things being compared. */
9047 {
9051 }
9055 /* Go back to the previous insn. Stop if it is not an INSN. We also
9056 stop if it isn't a single set or if it has a REG_INC note because
9057 we don't want to bother dealing with it. */
9065 /* If this is setting OP0, get what it sets it to if it looks
9066 relevant. */
9068 {
9071 /* ??? We may not combine comparisons done in a CCmode with
9072 comparisons not done in a CCmode. This is to aid targets
9073 like Alpha that have an IEEE compliant EQ instruction, and
9074 a non-IEEE compliant BEQ instruction. The use of CCmode is
9075 actually artificial, simply to prevent the combination, but
9076 should not affect other platforms.
9078 However, we must allow VOIDmode comparisons to match either
9079 CCmode or non-CCmode comparison, because some ports have
9080 modeless comparisons inside branch patterns.
9082 ??? This mode check should perhaps look more like the mode check
9083 in simplify_comparison in combine. */
9091 && (STORE_FLAG_VALUE
9094 #ifdef FLOAT_STORE_FLAG_VALUE
9098 #endif
9099 ))
9110 && (STORE_FLAG_VALUE
9113 #ifdef FLOAT_STORE_FLAG_VALUE
9117 #endif
9118 ))
9124 {
9125 /* We might have reversed a LT to get a GE here. But this wasn't
9126 actually the comparison of data, so we don't flag that we
9127 have had to reverse the condition. */
9131 }
9132 else
9134 }
9137 /* If this sets OP0, but not directly, we have to give up. */
9141 {
9145 {
9149 }
9154 }
9155 }
9157 /* If constant is first, put it last. */
9161 /* If OP0 is the result of a comparison, we weren't able to find what
9162 was really being compared, so fail. */
9166 /* Canonicalize any ordered comparison with integers involving equality
9167 if we can do computations in the relevant mode and we do not
9168 overflow. */
9173 {
9176 unsigned HOST_WIDE_INT max_val
9180 {
9186 /* When cross-compiling, const_val might be sign-extended from
9187 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9207 }
9208 }
9210 /* If this was floating-point and we reversed anything other than an
9211 EQ or NE, return zero. */
9214 && ! flag_fast_math
9218 #ifdef HAVE_cc0
9219 /* Never return CC0; return zero instead. */
9222 #endif
9225 }
9227 /* Similar to above routine, except that we also put an invariant last
9228 unless both operands are invariants. */
9230 rtx
9232 rtx x;
9233 {
9243 }
9245 #ifdef HAVE_decrement_and_branch_on_count
9246 /* Instrument loop for insertion of bct instruction. We distinguish between
9247 loops with compile-time bounds and those with run-time bounds.
9248 Information from loop_iterations() is used to compute compile-time bounds.
9249 Run-time bounds should use loop preconditioning, but currently ignored.
9250 */
9252 static void
9256 {
9262 /* If the loop condition is <= or >=, the number of iteration
9263 is 1 more than the range of the bounds of the loop. */
9270 /* It's impossible to instrument a competely unrolled loop. */
9274 /* Make sure that the count register is not in use. */
9276 {
9280 loop_num);
9282 }
9284 /* Make sure that the function has no indirect jumps. */
9286 {
9290 loop_num);
9292 }
9294 /* Make sure that the last loop insn is a conditional jump. */
9298 {
9302 loop_num);
9304 }
9306 /* Make sure that the loop does not contain a function call
9307 (the count register might be altered by the called function). */
9309 {
9313 loop_num);
9315 }
9317 /* Make sure that the loop does not jump via a table.
9318 (the count register might be used to perform the branch on table). */
9320 {
9324 loop_num);
9326 }
9328 /* Account for loop unrolling in instrumented iteration count. */
9331 else
9335 {
9336 /* Allow an enclosing outer loop to benefit if possible. */
9340 loop_num);
9342 }
9344 /* Try to instrument the loop. */
9346 /* Handle the simpler case, where the bounds are known at compile time. */
9348 {
9349 /* Mark all enclosing loops that they cannot use count register. */
9354 }
9356 /* Handle the more complex case, that the bounds are NOT known
9357 at compile time. In this case we generate run_time calculation
9358 of the number of iterations. */
9361 {
9365 loop_num);
9367 }
9371 {
9375 loop_num);
9377 }
9379 /* With runtime bounds, if the compare is of the form '!=' we give up */
9381 {
9385 loop_num);
9387 }
9388 /* Use common loop preconditioning code instead. */
9389 #if 0
9390 else
9391 {
9392 /* We rely on the existence of run-time guard to ensure that the
9393 loop executes at least once. */
9394 rtx sequence;
9395 rtx iterations_num_reg;
9397 unsigned HOST_WIDE_INT increment_value_abs
9400 /* make sure that the increment is a power of two, otherwise (an
9401 expensive) divide is needed. */
9403 {
9408 }
9410 /* compute the number of iterations */
9412 {
9413 rtx temp_reg;
9415 /* Again, the number of iterations is calculated by:
9416 ;
9417 ; compare-val - initial-val + (increment -1) + additional-iteration
9418 ; num_iterations = -----------------------------------------------------------------
9419 ; increment
9420 */
9421 /* ??? Do we have to call copy_rtx here before passing rtx to
9422 expand_binop? */
9424 {
9425 /* <, <= :the loop variable is increasing */
9429 }
9430 else
9431 {
9435 }
9445 temp_reg,
9448 else
9450 }
9455 }
9459 }
9461 /* Instrument loop by inserting a bct in it as follows:
9462 1. A new counter register is created.
9463 2. In the head of the loop the new variable is initialized to the value
9464 passed in the loop_num_iterations parameter.
9465 3. At the end of the loop, comparison of the register with 0 is generated.
9466 The created comparison follows the pattern defined for the
9467 decrement_and_branch_on_count insn, so this insn will be generated.
9468 4. The branch on the old variable are deleted. The compare must remain
9469 because it might be used elsewhere. If the loop-variable or condition
9470 register are used elsewhere, they will be eliminated by flow. */
9472 static void
9475 rtx loop_num_iterations;
9476 {
9477 rtx counter_reg;
9478 rtx start_label;
9479 rtx sequence;
9482 {
9484 {
9489 else
9492 }
9494 /* Discard original jump to continue loop. Original compare result
9495 may still be live, so it cannot be discarded explicitly. */
9498 /* Insert the label which will delimit the start of the loop. */
9502 /* Insert initialization of the count register into the loop header. */
9510 /* Insert new comparison on the count register instead of the
9511 old one, generating the needed BCT pattern (that will be
9512 later recognized by assembly generation phase). */
9514 start_label),
9515 loop_end);
9517 }
9519 }
9522 /* Scan the function and determine whether it has indirect (computed) jumps.
9524 This is taken mostly from flow.c; similar code exists elsewhere
9525 in the compiler. It may be useful to put this into rtlanal.c. */
9526 static int
9528 rtx start;
9529 {
9530 rtx insn;
9537 }
9539 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9540 documentation for LOOP_MEMS for the definition of `appropriate'.
9541 This function is called from prescan_loop via for_each_rtx. */
9543 static int
9547 {
9555 {
9560 /* We're not interested in the MEM associated with a
9561 CONST_DOUBLE, so there's no need to traverse into this. */
9565 /* This is not a MEM. */
9567 }
9569 /* See if we've already seen this MEM. */
9572 {
9574 /* The modes of the two memory accesses are different. If
9575 this happens, something tricky is going on, and we just
9576 don't optimize accesses to this MEM. */
9580 }
9582 /* Resize the array, if necessary. */
9584 {
9587 else
9593 }
9595 /* Actually insert the MEM. */
9597 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9598 because we can't put it in a register. We still store it in the
9599 table, though, so that if we see the same address later, but in a
9600 non-BLK mode, we'll not think we can optimize it at that point. */
9606 }
9608 /* Like load_mems, but also ensures that SET_IN_LOOP,
9609 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9610 values after load_mems. */
9612 static void
9614 insn_count)
9615 rtx scan_start;
9616 rtx end;
9617 rtx loop_top;
9618 rtx start;
9620 {
9625 /* Recalculate set_in_loop and friends since load_mems may have
9626 created new registers. */
9628 {
9636 {
9637 /* Grow all the arrays. */
9642 }
9643 /* Clear the arrays */
9653 {
9656 }
9658 #ifdef AVOID_CCMODE_COPIES
9659 /* Don't try to move insns which set CC registers if we should not
9660 create CCmode register copies. */
9664 #endif
9666 /* Set n_times_set for the new registers. */
9670 }
9671 }
9673 /* Move MEMs into registers for the duration of the loop. SCAN_START
9674 is the first instruction in the loop (as it is executed). The
9675 other parameters are as for next_insn_in_loop. */
9677 static void
9679 rtx scan_start;
9680 rtx end;
9681 rtx loop_top;
9682 rtx start;
9683 {
9686 rtx p;
9691 {
9692 /* Nonzero if the next instruction may never be executed. */
9695 /* Check to see if it's possible that some instructions in the
9696 loop are never executed. */
9700 {
9704 /* If we enter the loop in the middle, and scan
9705 around to the beginning, don't set maybe_never
9706 for that. This must be an unconditional jump,
9707 otherwise the code at the top of the loop might
9708 never be executed. Unconditional jumps are
9709 followed a by barrier then loop end. */
9714 {
9716 /* Something complicated. */
9718 else
9719 /* If there are any more instructions in the loop, they
9720 might not be reached. */
9722 }
9725 }
9727 /* Actually move the MEMs. */
9729 {
9731 rtx reg;
9733 rtx mem_list_entry;
9737 /* There's no telling whether or not MEM is modified. */
9740 /* Go through the MEMs written to in the loop to see if this
9741 one is aliased by one of them. */
9744 {
9749 {
9750 /* MEM is indeed aliased by this store. */
9753 }
9755 }
9757 /* If this MEM is written to, we must be sure that there
9758 are no reads from another MEM that aliases this one. */
9760 {
9764 {
9768 VOIDmode,
9770 rtx_varies_p))
9771 {
9772 /* It's not safe to hoist loop_mems[i] out of
9773 the loop because writes to it might not be
9774 seen by reads from loop_mems[j]. */
9777 }
9778 }
9779 }
9782 /* We can't access the MEM outside the loop; it might
9783 cause a trap that wouldn't have happened otherwise. */
9787 /* We thought we were going to lift this MEM out of the
9788 loop, but later discovered that we could not. */
9791 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9792 order to keep scan_loop from moving stores to this MEM
9793 out of the loop just because this REG is neither a
9794 user-variable nor used in the loop test. */
9799 /* Now, replace all references to the MEM with the
9800 corresponding pesudos. */
9804 {
9805 rtx_and_int ri;
9809 }
9812 /* We couldn't replace all occurrences of the MEM. */
9814 else
9815 {
9816 rtx set;
9818 /* Load the memory immediately before START, which is
9819 the NOTE_LOOP_BEG. */
9824 {
9826 {
9827 /* We must compute the former
9828 right-after-the-end label before we insert
9829 the new one. */
9833 }
9835 /* Store the memory immediately after END, which is
9836 the NOTE_LOOP_END. */
9839 }
9842 {
9847 }
9848 }
9849 }
9850 }
9853 {
9854 /* Now, we need to replace all references to the previous exit
9855 label with the new one. */
9856 rtx_pair rr;
9861 {
9864 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9865 field. This is not handled by for_each_rtx because it doesn't
9866 handle unprinted ('0') fields. We need to update JUMP_LABEL
9867 because the immediately following unroll pass will use it.
9868 replace_label would not work anyways, because that only handles
9869 LABEL_REFs. */
9872 }
9873 }
9874 }
9876 /* Replace MEM with its associated pseudo register. This function is
9877 called from load_mems via for_each_rtx. DATA is actually an
9878 rtx_and_int * describing the instruction currently being scanned
9879 and the MEM we are currently replacing. */
9881 static int
9885 {
9887 rtx insn;
9895 {
9900 /* We're not interested in the MEM associated with a
9901 CONST_DOUBLE, so there's no need to traverse into one. */
9905 /* This is not a MEM. */
9907 }
9913 /* This is not the MEM we are currently replacing. */
9918 /* Actually replace the MEM. */
9922 }
9924 /* Replace occurrences of the old exit label for the loop with the new
9925 one. DATA is an rtx_pair containing the old and new labels,
9926 respectively. */
9928 static int
9932 {
9951 }