| blob | a4902c4e561e6269ba94f149418e82b82073ce1e |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;
27 ;; UNSPEC usage
28 ;;
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
91 (const_string "integer"))
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
110 (const (symbol_ref "rs6000_cpu_attr")))
113 ;; If this instruction is microcoded on the CELL processor
114 ; The default for load and stores is conditional
115 ; The default for load extended and the recorded instructions is always microcoded
116 (define_attr "cell_micro" "not,conditional,always"
117 (if_then_else (ior (ior (eq_attr "type" "load")
118 (eq_attr "type" "store"))
119 (ior (eq_attr "type" "fpload")
120 (eq_attr "type" "fpstore")))
121 (const_string "conditional")
122 (if_then_else (ior (eq_attr "type" "load_ext")
123 (ior (eq_attr "type" "compare")
124 (eq_attr "type" "delayed_compare")))
125 (const_string "always")
126 (const_string "not"))))
129 (automata_option "ndfa")
131 (include "rios1.md")
132 (include "rios2.md")
133 (include "rs64.md")
134 (include "mpc.md")
135 (include "40x.md")
136 (include "440.md")
137 (include "603.md")
138 (include "6xx.md")
139 (include "7xx.md")
140 (include "7450.md")
141 (include "8540.md")
142 (include "power4.md")
143 (include "power5.md")
144 (include "power6.md")
145 (include "cell.md")
147 (include "predicates.md")
148 (include "constraints.md")
150 (include "darwin.md")
152 \f
153 ;; Mode macros
155 ; This mode macro allows :GPR to be used to indicate the allowable size
156 ; of whole values in GPRs.
157 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
159 ; Any supported integer mode.
160 (define_mode_macro INT [QI HI SI DI TI])
162 ; Any supported integer mode that fits in one register.
163 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
165 ; extend modes for DImode
166 (define_mode_macro QHSI [QI HI SI])
168 ; SImode or DImode, even if DImode doesn't fit in GPRs.
169 (define_mode_macro SDI [SI DI])
171 ; The size of a pointer. Also, the size of the value that a record-condition
172 ; (one with a '.') will compare.
173 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
175 ; Any hardware-supported floating-point mode
176 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
177 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
178 (TF "!TARGET_IEEEQUAD
179 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
181 ; Various instructions that come in SI and DI forms.
182 ; A generic w/d attribute, for things like cmpw/cmpd.
183 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
185 ; DImode bits
186 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
188 \f
189 ;; Start with fixed-point load and store insns. Here we put only the more
190 ;; complex forms. Basic data transfer is done later.
192 (define_expand "zero_extend<mode>di2"
193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
194 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
195 "TARGET_POWERPC64"
196 "")
198 (define_insn "*zero_extend<mode>di2_internal1"
199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
200 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
201 "TARGET_POWERPC64"
202 "@
203 l<wd>z%U1%X1 %0,%1
204 rldicl %0,%1,0,<dbits>"
205 [(set_attr "type" "load,*")])
207 (define_insn "*zero_extend<mode>di2_internal2"
208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
209 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
210 (const_int 0)))
211 (clobber (match_scratch:DI 2 "=r,r"))]
212 "TARGET_64BIT"
213 "@
214 rldicl. %2,%1,0,<dbits>
215 #"
216 [(set_attr "type" "compare")
217 (set_attr "length" "4,8")])
219 (define_split
220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
221 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
222 (const_int 0)))
223 (clobber (match_scratch:DI 2 ""))]
224 "TARGET_POWERPC64 && reload_completed"
225 [(set (match_dup 2)
226 (zero_extend:DI (match_dup 1)))
227 (set (match_dup 0)
228 (compare:CC (match_dup 2)
229 (const_int 0)))]
230 "")
232 (define_insn "*zero_extend<mode>di2_internal3"
233 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
234 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
235 (const_int 0)))
236 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
237 (zero_extend:DI (match_dup 1)))]
238 "TARGET_64BIT"
239 "@
240 rldicl. %0,%1,0,<dbits>
241 #"
242 [(set_attr "type" "compare")
243 (set_attr "length" "4,8")])
245 (define_split
246 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
247 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
248 (const_int 0)))
249 (set (match_operand:DI 0 "gpc_reg_operand" "")
250 (zero_extend:DI (match_dup 1)))]
251 "TARGET_POWERPC64 && reload_completed"
252 [(set (match_dup 0)
253 (zero_extend:DI (match_dup 1)))
254 (set (match_dup 2)
255 (compare:CC (match_dup 0)
256 (const_int 0)))]
257 "")
259 (define_insn "extendqidi2"
260 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
261 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
262 "TARGET_POWERPC64"
263 "extsb %0,%1"
264 [(set_attr "type" "exts")])
266 (define_insn ""
267 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
268 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
269 (const_int 0)))
270 (clobber (match_scratch:DI 2 "=r,r"))]
271 "TARGET_64BIT"
272 "@
273 extsb. %2,%1
274 #"
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
278 (define_split
279 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
280 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
281 (const_int 0)))
282 (clobber (match_scratch:DI 2 ""))]
283 "TARGET_POWERPC64 && reload_completed"
284 [(set (match_dup 2)
285 (sign_extend:DI (match_dup 1)))
286 (set (match_dup 0)
287 (compare:CC (match_dup 2)
288 (const_int 0)))]
289 "")
291 (define_insn ""
292 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
293 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
294 (const_int 0)))
295 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
296 (sign_extend:DI (match_dup 1)))]
297 "TARGET_64BIT"
298 "@
299 extsb. %0,%1
300 #"
301 [(set_attr "type" "compare")
302 (set_attr "length" "4,8")])
304 (define_split
305 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
306 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
307 (const_int 0)))
308 (set (match_operand:DI 0 "gpc_reg_operand" "")
309 (sign_extend:DI (match_dup 1)))]
310 "TARGET_POWERPC64 && reload_completed"
311 [(set (match_dup 0)
312 (sign_extend:DI (match_dup 1)))
313 (set (match_dup 2)
314 (compare:CC (match_dup 0)
315 (const_int 0)))]
316 "")
318 (define_expand "extendhidi2"
319 [(set (match_operand:DI 0 "gpc_reg_operand" "")
320 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
321 "TARGET_POWERPC64"
322 "")
324 (define_insn ""
325 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
326 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
327 "TARGET_POWERPC64"
328 "@
329 lha%U1%X1 %0,%1
330 extsh %0,%1"
331 [(set_attr "type" "load_ext,exts")])
333 (define_insn ""
334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
335 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
336 (const_int 0)))
337 (clobber (match_scratch:DI 2 "=r,r"))]
338 "TARGET_64BIT"
339 "@
340 extsh. %2,%1
341 #"
342 [(set_attr "type" "compare")
343 (set_attr "length" "4,8")])
345 (define_split
346 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
347 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
348 (const_int 0)))
349 (clobber (match_scratch:DI 2 ""))]
350 "TARGET_POWERPC64 && reload_completed"
351 [(set (match_dup 2)
352 (sign_extend:DI (match_dup 1)))
353 (set (match_dup 0)
354 (compare:CC (match_dup 2)
355 (const_int 0)))]
356 "")
358 (define_insn ""
359 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
360 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
361 (const_int 0)))
362 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
363 (sign_extend:DI (match_dup 1)))]
364 "TARGET_64BIT"
365 "@
366 extsh. %0,%1
367 #"
368 [(set_attr "type" "compare")
369 (set_attr "length" "4,8")])
371 (define_split
372 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
373 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
374 (const_int 0)))
375 (set (match_operand:DI 0 "gpc_reg_operand" "")
376 (sign_extend:DI (match_dup 1)))]
377 "TARGET_POWERPC64 && reload_completed"
378 [(set (match_dup 0)
379 (sign_extend:DI (match_dup 1)))
380 (set (match_dup 2)
381 (compare:CC (match_dup 0)
382 (const_int 0)))]
383 "")
385 (define_expand "extendsidi2"
386 [(set (match_operand:DI 0 "gpc_reg_operand" "")
387 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
388 "TARGET_POWERPC64"
389 "")
391 (define_insn ""
392 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
393 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
394 "TARGET_POWERPC64"
395 "@
396 lwa%U1%X1 %0,%1
397 extsw %0,%1"
398 [(set_attr "type" "load_ext,exts")])
400 (define_insn ""
401 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
402 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
403 (const_int 0)))
404 (clobber (match_scratch:DI 2 "=r,r"))]
405 "TARGET_64BIT"
406 "@
407 extsw. %2,%1
408 #"
409 [(set_attr "type" "compare")
410 (set_attr "length" "4,8")])
412 (define_split
413 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
414 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
415 (const_int 0)))
416 (clobber (match_scratch:DI 2 ""))]
417 "TARGET_POWERPC64 && reload_completed"
418 [(set (match_dup 2)
419 (sign_extend:DI (match_dup 1)))
420 (set (match_dup 0)
421 (compare:CC (match_dup 2)
422 (const_int 0)))]
423 "")
425 (define_insn ""
426 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
427 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
428 (const_int 0)))
429 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
430 (sign_extend:DI (match_dup 1)))]
431 "TARGET_64BIT"
432 "@
433 extsw. %0,%1
434 #"
435 [(set_attr "type" "compare")
436 (set_attr "length" "4,8")])
438 (define_split
439 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
440 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
441 (const_int 0)))
442 (set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_dup 1)))]
444 "TARGET_POWERPC64 && reload_completed"
445 [(set (match_dup 0)
446 (sign_extend:DI (match_dup 1)))
447 (set (match_dup 2)
448 (compare:CC (match_dup 0)
449 (const_int 0)))]
450 "")
452 (define_expand "zero_extendqisi2"
453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
454 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
455 ""
456 "")
458 (define_insn ""
459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
460 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
461 ""
462 "@
463 lbz%U1%X1 %0,%1
464 {rlinm|rlwinm} %0,%1,0,0xff"
465 [(set_attr "type" "load,*")])
467 (define_insn ""
468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
469 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
470 (const_int 0)))
471 (clobber (match_scratch:SI 2 "=r,r"))]
472 ""
473 "@
474 {andil.|andi.} %2,%1,0xff
475 #"
476 [(set_attr "type" "compare")
477 (set_attr "length" "4,8")])
479 (define_split
480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
481 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
482 (const_int 0)))
483 (clobber (match_scratch:SI 2 ""))]
484 "reload_completed"
485 [(set (match_dup 2)
486 (zero_extend:SI (match_dup 1)))
487 (set (match_dup 0)
488 (compare:CC (match_dup 2)
489 (const_int 0)))]
490 "")
492 (define_insn ""
493 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
494 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
495 (const_int 0)))
496 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
497 (zero_extend:SI (match_dup 1)))]
498 ""
499 "@
500 {andil.|andi.} %0,%1,0xff
501 #"
502 [(set_attr "type" "compare")
503 (set_attr "length" "4,8")])
505 (define_split
506 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
507 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
508 (const_int 0)))
509 (set (match_operand:SI 0 "gpc_reg_operand" "")
510 (zero_extend:SI (match_dup 1)))]
511 "reload_completed"
512 [(set (match_dup 0)
513 (zero_extend:SI (match_dup 1)))
514 (set (match_dup 2)
515 (compare:CC (match_dup 0)
516 (const_int 0)))]
517 "")
519 (define_expand "extendqisi2"
520 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
521 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
522 ""
523 "
524 {
525 if (TARGET_POWERPC)
526 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
527 else if (TARGET_POWER)
528 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
529 else
530 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
531 DONE;
532 }")
534 (define_insn "extendqisi2_ppc"
535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
536 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
537 "TARGET_POWERPC"
538 "extsb %0,%1"
539 [(set_attr "type" "exts")])
541 (define_insn ""
542 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
543 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
544 (const_int 0)))
545 (clobber (match_scratch:SI 2 "=r,r"))]
546 "TARGET_POWERPC"
547 "@
548 extsb. %2,%1
549 #"
550 [(set_attr "type" "compare")
551 (set_attr "length" "4,8")])
553 (define_split
554 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
555 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (const_int 0)))
557 (clobber (match_scratch:SI 2 ""))]
558 "TARGET_POWERPC && reload_completed"
559 [(set (match_dup 2)
560 (sign_extend:SI (match_dup 1)))
561 (set (match_dup 0)
562 (compare:CC (match_dup 2)
563 (const_int 0)))]
564 "")
566 (define_insn ""
567 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
568 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
569 (const_int 0)))
570 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
571 (sign_extend:SI (match_dup 1)))]
572 "TARGET_POWERPC"
573 "@
574 extsb. %0,%1
575 #"
576 [(set_attr "type" "compare")
577 (set_attr "length" "4,8")])
579 (define_split
580 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
581 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
582 (const_int 0)))
583 (set (match_operand:SI 0 "gpc_reg_operand" "")
584 (sign_extend:SI (match_dup 1)))]
585 "TARGET_POWERPC && reload_completed"
586 [(set (match_dup 0)
587 (sign_extend:SI (match_dup 1)))
588 (set (match_dup 2)
589 (compare:CC (match_dup 0)
590 (const_int 0)))]
591 "")
593 (define_expand "extendqisi2_power"
594 [(parallel [(set (match_dup 2)
595 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
596 (const_int 24)))
597 (clobber (scratch:SI))])
598 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
599 (ashiftrt:SI (match_dup 2)
600 (const_int 24)))
601 (clobber (scratch:SI))])]
602 "TARGET_POWER"
603 "
604 { operands[1] = gen_lowpart (SImode, operands[1]);
605 operands[2] = gen_reg_rtx (SImode); }")
607 (define_expand "extendqisi2_no_power"
608 [(set (match_dup 2)
609 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
610 (const_int 24)))
611 (set (match_operand:SI 0 "gpc_reg_operand" "")
612 (ashiftrt:SI (match_dup 2)
613 (const_int 24)))]
614 "! TARGET_POWER && ! TARGET_POWERPC"
615 "
616 { operands[1] = gen_lowpart (SImode, operands[1]);
617 operands[2] = gen_reg_rtx (SImode); }")
619 (define_expand "zero_extendqihi2"
620 [(set (match_operand:HI 0 "gpc_reg_operand" "")
621 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
622 ""
623 "")
625 (define_insn ""
626 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
627 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
628 ""
629 "@
630 lbz%U1%X1 %0,%1
631 {rlinm|rlwinm} %0,%1,0,0xff"
632 [(set_attr "type" "load,*")])
634 (define_insn ""
635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
636 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
637 (const_int 0)))
638 (clobber (match_scratch:HI 2 "=r,r"))]
639 ""
640 "@
641 {andil.|andi.} %2,%1,0xff
642 #"
643 [(set_attr "type" "compare")
644 (set_attr "length" "4,8")])
646 (define_split
647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
648 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
649 (const_int 0)))
650 (clobber (match_scratch:HI 2 ""))]
651 "reload_completed"
652 [(set (match_dup 2)
653 (zero_extend:HI (match_dup 1)))
654 (set (match_dup 0)
655 (compare:CC (match_dup 2)
656 (const_int 0)))]
657 "")
659 (define_insn ""
660 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
661 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
662 (const_int 0)))
663 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
664 (zero_extend:HI (match_dup 1)))]
665 ""
666 "@
667 {andil.|andi.} %0,%1,0xff
668 #"
669 [(set_attr "type" "compare")
670 (set_attr "length" "4,8")])
672 (define_split
673 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
674 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
675 (const_int 0)))
676 (set (match_operand:HI 0 "gpc_reg_operand" "")
677 (zero_extend:HI (match_dup 1)))]
678 "reload_completed"
679 [(set (match_dup 0)
680 (zero_extend:HI (match_dup 1)))
681 (set (match_dup 2)
682 (compare:CC (match_dup 0)
683 (const_int 0)))]
684 "")
686 (define_expand "extendqihi2"
687 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
688 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
689 ""
690 "
691 {
692 if (TARGET_POWERPC)
693 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
694 else if (TARGET_POWER)
695 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
696 else
697 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
698 DONE;
699 }")
701 (define_insn "extendqihi2_ppc"
702 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
703 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
704 "TARGET_POWERPC"
705 "extsb %0,%1"
706 [(set_attr "type" "exts")])
708 (define_insn ""
709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
710 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
711 (const_int 0)))
712 (clobber (match_scratch:HI 2 "=r,r"))]
713 "TARGET_POWERPC"
714 "@
715 extsb. %2,%1
716 #"
717 [(set_attr "type" "compare")
718 (set_attr "length" "4,8")])
720 (define_split
721 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
722 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
723 (const_int 0)))
724 (clobber (match_scratch:HI 2 ""))]
725 "TARGET_POWERPC && reload_completed"
726 [(set (match_dup 2)
727 (sign_extend:HI (match_dup 1)))
728 (set (match_dup 0)
729 (compare:CC (match_dup 2)
730 (const_int 0)))]
731 "")
733 (define_insn ""
734 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
735 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
736 (const_int 0)))
737 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
738 (sign_extend:HI (match_dup 1)))]
739 "TARGET_POWERPC"
740 "@
741 extsb. %0,%1
742 #"
743 [(set_attr "type" "compare")
744 (set_attr "length" "4,8")])
746 (define_split
747 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
748 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
749 (const_int 0)))
750 (set (match_operand:HI 0 "gpc_reg_operand" "")
751 (sign_extend:HI (match_dup 1)))]
752 "TARGET_POWERPC && reload_completed"
753 [(set (match_dup 0)
754 (sign_extend:HI (match_dup 1)))
755 (set (match_dup 2)
756 (compare:CC (match_dup 0)
757 (const_int 0)))]
758 "")
760 (define_expand "extendqihi2_power"
761 [(parallel [(set (match_dup 2)
762 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
763 (const_int 24)))
764 (clobber (scratch:SI))])
765 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
766 (ashiftrt:SI (match_dup 2)
767 (const_int 24)))
768 (clobber (scratch:SI))])]
769 "TARGET_POWER"
770 "
771 { operands[0] = gen_lowpart (SImode, operands[0]);
772 operands[1] = gen_lowpart (SImode, operands[1]);
773 operands[2] = gen_reg_rtx (SImode); }")
775 (define_expand "extendqihi2_no_power"
776 [(set (match_dup 2)
777 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
778 (const_int 24)))
779 (set (match_operand:HI 0 "gpc_reg_operand" "")
780 (ashiftrt:SI (match_dup 2)
781 (const_int 24)))]
782 "! TARGET_POWER && ! TARGET_POWERPC"
783 "
784 { operands[0] = gen_lowpart (SImode, operands[0]);
785 operands[1] = gen_lowpart (SImode, operands[1]);
786 operands[2] = gen_reg_rtx (SImode); }")
788 (define_expand "zero_extendhisi2"
789 [(set (match_operand:SI 0 "gpc_reg_operand" "")
790 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
791 ""
792 "")
794 (define_insn ""
795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
796 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
797 ""
798 "@
799 lhz%U1%X1 %0,%1
800 {rlinm|rlwinm} %0,%1,0,0xffff"
801 [(set_attr "type" "load,*")])
803 (define_insn ""
804 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
805 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
806 (const_int 0)))
807 (clobber (match_scratch:SI 2 "=r,r"))]
808 ""
809 "@
810 {andil.|andi.} %2,%1,0xffff
811 #"
812 [(set_attr "type" "compare")
813 (set_attr "length" "4,8")])
815 (define_split
816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
817 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
818 (const_int 0)))
819 (clobber (match_scratch:SI 2 ""))]
820 "reload_completed"
821 [(set (match_dup 2)
822 (zero_extend:SI (match_dup 1)))
823 (set (match_dup 0)
824 (compare:CC (match_dup 2)
825 (const_int 0)))]
826 "")
828 (define_insn ""
829 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
830 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
831 (const_int 0)))
832 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
833 (zero_extend:SI (match_dup 1)))]
834 ""
835 "@
836 {andil.|andi.} %0,%1,0xffff
837 #"
838 [(set_attr "type" "compare")
839 (set_attr "length" "4,8")])
841 (define_split
842 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
843 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
844 (const_int 0)))
845 (set (match_operand:SI 0 "gpc_reg_operand" "")
846 (zero_extend:SI (match_dup 1)))]
847 "reload_completed"
848 [(set (match_dup 0)
849 (zero_extend:SI (match_dup 1)))
850 (set (match_dup 2)
851 (compare:CC (match_dup 0)
852 (const_int 0)))]
853 "")
855 (define_expand "extendhisi2"
856 [(set (match_operand:SI 0 "gpc_reg_operand" "")
857 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
858 ""
859 "")
861 (define_insn ""
862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
863 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
864 ""
865 "@
866 lha%U1%X1 %0,%1
867 {exts|extsh} %0,%1"
868 [(set_attr "type" "load_ext,exts")])
870 (define_insn ""
871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
872 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
873 (const_int 0)))
874 (clobber (match_scratch:SI 2 "=r,r"))]
875 ""
876 "@
877 {exts.|extsh.} %2,%1
878 #"
879 [(set_attr "type" "compare")
880 (set_attr "length" "4,8")])
882 (define_split
883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
884 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
885 (const_int 0)))
886 (clobber (match_scratch:SI 2 ""))]
887 "reload_completed"
888 [(set (match_dup 2)
889 (sign_extend:SI (match_dup 1)))
890 (set (match_dup 0)
891 (compare:CC (match_dup 2)
892 (const_int 0)))]
893 "")
895 (define_insn ""
896 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
897 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
898 (const_int 0)))
899 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
900 (sign_extend:SI (match_dup 1)))]
901 ""
902 "@
903 {exts.|extsh.} %0,%1
904 #"
905 [(set_attr "type" "compare")
906 (set_attr "length" "4,8")])
907 \f
908 ;; IBM 405 and 440 half-word multiplication operations.
910 (define_insn "*macchwc"
911 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
912 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
913 (match_operand:SI 2 "gpc_reg_operand" "r")
914 (const_int 16))
915 (sign_extend:SI
916 (match_operand:HI 1 "gpc_reg_operand" "r")))
917 (match_operand:SI 4 "gpc_reg_operand" "0"))
918 (const_int 0)))
919 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
920 (plus:SI (mult:SI (ashiftrt:SI
921 (match_dup 2)
922 (const_int 16))
923 (sign_extend:SI
924 (match_dup 1)))
925 (match_dup 4)))]
926 "TARGET_MULHW"
927 "macchw. %0, %1, %2"
928 [(set_attr "type" "imul3")])
930 (define_insn "*macchw"
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
932 (plus:SI (mult:SI (ashiftrt:SI
933 (match_operand:SI 2 "gpc_reg_operand" "r")
934 (const_int 16))
935 (sign_extend:SI
936 (match_operand:HI 1 "gpc_reg_operand" "r")))
937 (match_operand:SI 3 "gpc_reg_operand" "0")))]
938 "TARGET_MULHW"
939 "macchw %0, %1, %2"
940 [(set_attr "type" "imul3")])
942 (define_insn "*macchwuc"
943 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
944 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
945 (match_operand:SI 2 "gpc_reg_operand" "r")
946 (const_int 16))
947 (zero_extend:SI
948 (match_operand:HI 1 "gpc_reg_operand" "r")))
949 (match_operand:SI 4 "gpc_reg_operand" "0"))
950 (const_int 0)))
951 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
952 (plus:SI (mult:SI (lshiftrt:SI
953 (match_dup 2)
954 (const_int 16))
955 (zero_extend:SI
956 (match_dup 1)))
957 (match_dup 4)))]
958 "TARGET_MULHW"
959 "macchwu. %0, %1, %2"
960 [(set_attr "type" "imul3")])
962 (define_insn "*macchwu"
963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
964 (plus:SI (mult:SI (lshiftrt:SI
965 (match_operand:SI 2 "gpc_reg_operand" "r")
966 (const_int 16))
967 (zero_extend:SI
968 (match_operand:HI 1 "gpc_reg_operand" "r")))
969 (match_operand:SI 3 "gpc_reg_operand" "0")))]
970 "TARGET_MULHW"
971 "macchwu %0, %1, %2"
972 [(set_attr "type" "imul3")])
974 (define_insn "*machhwc"
975 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
976 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
977 (match_operand:SI 1 "gpc_reg_operand" "%r")
978 (const_int 16))
979 (ashiftrt:SI
980 (match_operand:SI 2 "gpc_reg_operand" "r")
981 (const_int 16)))
982 (match_operand:SI 4 "gpc_reg_operand" "0"))
983 (const_int 0)))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (plus:SI (mult:SI (ashiftrt:SI
986 (match_dup 1)
987 (const_int 16))
988 (ashiftrt:SI
989 (match_dup 2)
990 (const_int 16)))
991 (match_dup 4)))]
992 "TARGET_MULHW"
993 "machhw. %0, %1, %2"
994 [(set_attr "type" "imul3")])
996 (define_insn "*machhw"
997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
998 (plus:SI (mult:SI (ashiftrt:SI
999 (match_operand:SI 1 "gpc_reg_operand" "%r")
1000 (const_int 16))
1001 (ashiftrt:SI
1002 (match_operand:SI 2 "gpc_reg_operand" "r")
1003 (const_int 16)))
1004 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1005 "TARGET_MULHW"
1006 "machhw %0, %1, %2"
1007 [(set_attr "type" "imul3")])
1009 (define_insn "*machhwuc"
1010 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1011 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 1 "gpc_reg_operand" "%r")
1013 (const_int 16))
1014 (lshiftrt:SI
1015 (match_operand:SI 2 "gpc_reg_operand" "r")
1016 (const_int 16)))
1017 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (const_int 0)))
1019 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1020 (plus:SI (mult:SI (lshiftrt:SI
1021 (match_dup 1)
1022 (const_int 16))
1023 (lshiftrt:SI
1024 (match_dup 2)
1025 (const_int 16)))
1026 (match_dup 4)))]
1027 "TARGET_MULHW"
1028 "machhwu. %0, %1, %2"
1029 [(set_attr "type" "imul3")])
1031 (define_insn "*machhwu"
1032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1033 (plus:SI (mult:SI (lshiftrt:SI
1034 (match_operand:SI 1 "gpc_reg_operand" "%r")
1035 (const_int 16))
1036 (lshiftrt:SI
1037 (match_operand:SI 2 "gpc_reg_operand" "r")
1038 (const_int 16)))
1039 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1040 "TARGET_MULHW"
1041 "machhwu %0, %1, %2"
1042 [(set_attr "type" "imul3")])
1044 (define_insn "*maclhwc"
1045 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1046 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1047 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1048 (sign_extend:SI
1049 (match_operand:HI 2 "gpc_reg_operand" "r")))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (sign_extend:SI
1054 (match_dup 1))
1055 (sign_extend:SI
1056 (match_dup 2)))
1057 (match_dup 4)))]
1058 "TARGET_MULHW"
1059 "maclhw. %0, %1, %2"
1060 [(set_attr "type" "imul3")])
1062 (define_insn "*maclhw"
1063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1064 (plus:SI (mult:SI (sign_extend:SI
1065 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1066 (sign_extend:SI
1067 (match_operand:HI 2 "gpc_reg_operand" "r")))
1068 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1069 "TARGET_MULHW"
1070 "maclhw %0, %1, %2"
1071 [(set_attr "type" "imul3")])
1073 (define_insn "*maclhwuc"
1074 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1075 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1076 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1077 (zero_extend:SI
1078 (match_operand:HI 2 "gpc_reg_operand" "r")))
1079 (match_operand:SI 4 "gpc_reg_operand" "0"))
1080 (const_int 0)))
1081 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (zero_extend:SI
1083 (match_dup 1))
1084 (zero_extend:SI
1085 (match_dup 2)))
1086 (match_dup 4)))]
1087 "TARGET_MULHW"
1088 "maclhwu. %0, %1, %2"
1089 [(set_attr "type" "imul3")])
1091 (define_insn "*maclhwu"
1092 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1093 (plus:SI (mult:SI (zero_extend:SI
1094 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1095 (zero_extend:SI
1096 (match_operand:HI 2 "gpc_reg_operand" "r")))
1097 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1098 "TARGET_MULHW"
1099 "maclhwu %0, %1, %2"
1100 [(set_attr "type" "imul3")])
1102 (define_insn "*nmacchwc"
1103 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1104 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1105 (mult:SI (ashiftrt:SI
1106 (match_operand:SI 2 "gpc_reg_operand" "r")
1107 (const_int 16))
1108 (sign_extend:SI
1109 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1110 (const_int 0)))
1111 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1112 (minus:SI (match_dup 4)
1113 (mult:SI (ashiftrt:SI
1114 (match_dup 2)
1115 (const_int 16))
1116 (sign_extend:SI
1117 (match_dup 1)))))]
1118 "TARGET_MULHW"
1119 "nmacchw. %0, %1, %2"
1120 [(set_attr "type" "imul3")])
1122 (define_insn "*nmacchw"
1123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1124 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1125 (mult:SI (ashiftrt:SI
1126 (match_operand:SI 2 "gpc_reg_operand" "r")
1127 (const_int 16))
1128 (sign_extend:SI
1129 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1130 "TARGET_MULHW"
1131 "nmacchw %0, %1, %2"
1132 [(set_attr "type" "imul3")])
1134 (define_insn "*nmachhwc"
1135 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1136 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1137 (mult:SI (ashiftrt:SI
1138 (match_operand:SI 1 "gpc_reg_operand" "%r")
1139 (const_int 16))
1140 (ashiftrt:SI
1141 (match_operand:SI 2 "gpc_reg_operand" "r")
1142 (const_int 16))))
1143 (const_int 0)))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1145 (minus:SI (match_dup 4)
1146 (mult:SI (ashiftrt:SI
1147 (match_dup 1)
1148 (const_int 16))
1149 (ashiftrt:SI
1150 (match_dup 2)
1151 (const_int 16)))))]
1152 "TARGET_MULHW"
1153 "nmachhw. %0, %1, %2"
1154 [(set_attr "type" "imul3")])
1156 (define_insn "*nmachhw"
1157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1158 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1159 (mult:SI (ashiftrt:SI
1160 (match_operand:SI 1 "gpc_reg_operand" "%r")
1161 (const_int 16))
1162 (ashiftrt:SI
1163 (match_operand:SI 2 "gpc_reg_operand" "r")
1164 (const_int 16)))))]
1165 "TARGET_MULHW"
1166 "nmachhw %0, %1, %2"
1167 [(set_attr "type" "imul3")])
1169 (define_insn "*nmaclhwc"
1170 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1171 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1172 (mult:SI (sign_extend:SI
1173 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1174 (sign_extend:SI
1175 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1176 (const_int 0)))
1177 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_dup 4)
1179 (mult:SI (sign_extend:SI
1180 (match_dup 1))
1181 (sign_extend:SI
1182 (match_dup 2)))))]
1183 "TARGET_MULHW"
1184 "nmaclhw. %0, %1, %2"
1185 [(set_attr "type" "imul3")])
1187 (define_insn "*nmaclhw"
1188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1189 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1190 (mult:SI (sign_extend:SI
1191 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1192 (sign_extend:SI
1193 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1194 "TARGET_MULHW"
1195 "nmaclhw %0, %1, %2"
1196 [(set_attr "type" "imul3")])
1198 (define_insn "*mulchwc"
1199 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1200 (compare:CC (mult:SI (ashiftrt:SI
1201 (match_operand:SI 2 "gpc_reg_operand" "r")
1202 (const_int 16))
1203 (sign_extend:SI
1204 (match_operand:HI 1 "gpc_reg_operand" "r")))
1205 (const_int 0)))
1206 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1207 (mult:SI (ashiftrt:SI
1208 (match_dup 2)
1209 (const_int 16))
1210 (sign_extend:SI
1211 (match_dup 1))))]
1212 "TARGET_MULHW"
1213 "mulchw. %0, %1, %2"
1214 [(set_attr "type" "imul3")])
1216 (define_insn "*mulchw"
1217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1218 (mult:SI (ashiftrt:SI
1219 (match_operand:SI 2 "gpc_reg_operand" "r")
1220 (const_int 16))
1221 (sign_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1223 "TARGET_MULHW"
1224 "mulchw %0, %1, %2"
1225 [(set_attr "type" "imul3")])
1227 (define_insn "*mulchwuc"
1228 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1229 (compare:CC (mult:SI (lshiftrt:SI
1230 (match_operand:SI 2 "gpc_reg_operand" "r")
1231 (const_int 16))
1232 (zero_extend:SI
1233 (match_operand:HI 1 "gpc_reg_operand" "r")))
1234 (const_int 0)))
1235 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1236 (mult:SI (lshiftrt:SI
1237 (match_dup 2)
1238 (const_int 16))
1239 (zero_extend:SI
1240 (match_dup 1))))]
1241 "TARGET_MULHW"
1242 "mulchwu. %0, %1, %2"
1243 [(set_attr "type" "imul3")])
1245 (define_insn "*mulchwu"
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1247 (mult:SI (lshiftrt:SI
1248 (match_operand:SI 2 "gpc_reg_operand" "r")
1249 (const_int 16))
1250 (zero_extend:SI
1251 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1252 "TARGET_MULHW"
1253 "mulchwu %0, %1, %2"
1254 [(set_attr "type" "imul3")])
1256 (define_insn "*mulhhwc"
1257 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1258 (compare:CC (mult:SI (ashiftrt:SI
1259 (match_operand:SI 1 "gpc_reg_operand" "%r")
1260 (const_int 16))
1261 (ashiftrt:SI
1262 (match_operand:SI 2 "gpc_reg_operand" "r")
1263 (const_int 16)))
1264 (const_int 0)))
1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (mult:SI (ashiftrt:SI
1267 (match_dup 1)
1268 (const_int 16))
1269 (ashiftrt:SI
1270 (match_dup 2)
1271 (const_int 16))))]
1272 "TARGET_MULHW"
1273 "mulhhw. %0, %1, %2"
1274 [(set_attr "type" "imul3")])
1276 (define_insn "*mulhhw"
1277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1278 (mult:SI (ashiftrt:SI
1279 (match_operand:SI 1 "gpc_reg_operand" "%r")
1280 (const_int 16))
1281 (ashiftrt:SI
1282 (match_operand:SI 2 "gpc_reg_operand" "r")
1283 (const_int 16))))]
1284 "TARGET_MULHW"
1285 "mulhhw %0, %1, %2"
1286 [(set_attr "type" "imul3")])
1288 (define_insn "*mulhhwuc"
1289 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1290 (compare:CC (mult:SI (lshiftrt:SI
1291 (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (const_int 16))
1293 (lshiftrt:SI
1294 (match_operand:SI 2 "gpc_reg_operand" "r")
1295 (const_int 16)))
1296 (const_int 0)))
1297 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1298 (mult:SI (lshiftrt:SI
1299 (match_dup 1)
1300 (const_int 16))
1301 (lshiftrt:SI
1302 (match_dup 2)
1303 (const_int 16))))]
1304 "TARGET_MULHW"
1305 "mulhhwu. %0, %1, %2"
1306 [(set_attr "type" "imul3")])
1308 (define_insn "*mulhhwu"
1309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1310 (mult:SI (lshiftrt:SI
1311 (match_operand:SI 1 "gpc_reg_operand" "%r")
1312 (const_int 16))
1313 (lshiftrt:SI
1314 (match_operand:SI 2 "gpc_reg_operand" "r")
1315 (const_int 16))))]
1316 "TARGET_MULHW"
1317 "mulhhwu %0, %1, %2"
1318 [(set_attr "type" "imul3")])
1320 (define_insn "*mullhwc"
1321 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (sign_extend:SI
1323 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1324 (sign_extend:SI
1325 (match_operand:HI 2 "gpc_reg_operand" "r")))
1326 (const_int 0)))
1327 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (mult:SI (sign_extend:SI
1329 (match_dup 1))
1330 (sign_extend:SI
1331 (match_dup 2))))]
1332 "TARGET_MULHW"
1333 "mullhw. %0, %1, %2"
1334 [(set_attr "type" "imul3")])
1336 (define_insn "*mullhw"
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1338 (mult:SI (sign_extend:SI
1339 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1340 (sign_extend:SI
1341 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1342 "TARGET_MULHW"
1343 "mullhw %0, %1, %2"
1344 [(set_attr "type" "imul3")])
1346 (define_insn "*mullhwuc"
1347 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1348 (compare:CC (mult:SI (zero_extend:SI
1349 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1350 (zero_extend:SI
1351 (match_operand:HI 2 "gpc_reg_operand" "r")))
1352 (const_int 0)))
1353 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1354 (mult:SI (zero_extend:SI
1355 (match_dup 1))
1356 (zero_extend:SI
1357 (match_dup 2))))]
1358 "TARGET_MULHW"
1359 "mullhwu. %0, %1, %2"
1360 [(set_attr "type" "imul3")])
1362 (define_insn "*mullhwu"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (zero_extend:SI
1365 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1366 (zero_extend:SI
1367 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1368 "TARGET_MULHW"
1369 "mullhwu %0, %1, %2"
1370 [(set_attr "type" "imul3")])
1371 \f
1372 ;; IBM 405 and 440 string-search dlmzb instruction support.
1373 (define_insn "dlmzb"
1374 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1375 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1376 (match_operand:SI 2 "gpc_reg_operand" "r")]
1377 UNSPEC_DLMZB_CR))
1378 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1379 (unspec:SI [(match_dup 1)
1380 (match_dup 2)]
1381 UNSPEC_DLMZB))]
1382 "TARGET_DLMZB"
1383 "dlmzb. %0, %1, %2")
1385 (define_expand "strlensi"
1386 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1387 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1388 (match_operand:QI 2 "const_int_operand" "")
1389 (match_operand 3 "const_int_operand" "")]
1390 UNSPEC_DLMZB_STRLEN))
1391 (clobber (match_scratch:CC 4 "=x"))]
1392 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1393 {
1394 rtx result = operands[0];
1395 rtx src = operands[1];
1396 rtx search_char = operands[2];
1397 rtx align = operands[3];
1398 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1399 rtx loop_label, end_label, mem, cr0, cond;
1400 if (search_char != const0_rtx
1401 || GET_CODE (align) != CONST_INT
1402 || INTVAL (align) < 8)
1403 FAIL;
1404 word1 = gen_reg_rtx (SImode);
1405 word2 = gen_reg_rtx (SImode);
1406 scratch_dlmzb = gen_reg_rtx (SImode);
1407 scratch_string = gen_reg_rtx (Pmode);
1408 loop_label = gen_label_rtx ();
1409 end_label = gen_label_rtx ();
1410 addr = force_reg (Pmode, XEXP (src, 0));
1411 emit_move_insn (scratch_string, addr);
1412 emit_label (loop_label);
1413 mem = change_address (src, SImode, scratch_string);
1414 emit_move_insn (word1, mem);
1415 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1416 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1417 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1418 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1419 emit_jump_insn (gen_rtx_SET (VOIDmode,
1420 pc_rtx,
1421 gen_rtx_IF_THEN_ELSE (VOIDmode,
1422 cond,
1423 gen_rtx_LABEL_REF
1424 (VOIDmode,
1425 end_label),
1426 pc_rtx)));
1427 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1428 emit_jump_insn (gen_rtx_SET (VOIDmode,
1429 pc_rtx,
1430 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1431 emit_barrier ();
1432 emit_label (end_label);
1433 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1434 emit_insn (gen_subsi3 (result, scratch_string, addr));
1435 emit_insn (gen_subsi3 (result, result, const1_rtx));
1436 DONE;
1437 })
1438 \f
1439 (define_split
1440 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1441 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1442 (const_int 0)))
1443 (set (match_operand:SI 0 "gpc_reg_operand" "")
1444 (sign_extend:SI (match_dup 1)))]
1445 "reload_completed"
1446 [(set (match_dup 0)
1447 (sign_extend:SI (match_dup 1)))
1448 (set (match_dup 2)
1449 (compare:CC (match_dup 0)
1450 (const_int 0)))]
1451 "")
1453 ;; Fixed-point arithmetic insns.
1455 (define_expand "add<mode>3"
1456 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1457 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1458 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1459 ""
1460 {
1461 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1462 {
1463 if (non_short_cint_operand (operands[2], DImode))
1464 FAIL;
1465 }
1466 else if (GET_CODE (operands[2]) == CONST_INT
1467 && ! add_operand (operands[2], <MODE>mode))
1468 {
1469 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1470 ? operands[0] : gen_reg_rtx (<MODE>mode));
1472 HOST_WIDE_INT val = INTVAL (operands[2]);
1473 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1474 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1476 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1477 FAIL;
1479 /* The ordering here is important for the prolog expander.
1480 When space is allocated from the stack, adding 'low' first may
1481 produce a temporary deallocation (which would be bad). */
1482 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1483 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1484 DONE;
1485 }
1486 })
1488 ;; Discourage ai/addic because of carry but provide it in an alternative
1489 ;; allowing register zero as source.
1490 (define_insn "*add<mode>3_internal1"
1491 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1492 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1493 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1494 ""
1495 "@
1496 {cax|add} %0,%1,%2
1497 {cal %0,%2(%1)|addi %0,%1,%2}
1498 {ai|addic} %0,%1,%2
1499 {cau|addis} %0,%1,%v2"
1500 [(set_attr "length" "4,4,4,4")])
1502 (define_insn "addsi3_high"
1503 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1504 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1505 (high:SI (match_operand 2 "" ""))))]
1506 "TARGET_MACHO && !TARGET_64BIT"
1507 "{cau|addis} %0,%1,ha16(%2)"
1508 [(set_attr "length" "4")])
1510 (define_insn "*add<mode>3_internal2"
1511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1512 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1513 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1514 (const_int 0)))
1515 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1516 ""
1517 "@
1518 {cax.|add.} %3,%1,%2
1519 {ai.|addic.} %3,%1,%2
1520 #
1521 #"
1522 [(set_attr "type" "fast_compare,compare,compare,compare")
1523 (set_attr "length" "4,4,8,8")])
1525 (define_split
1526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1527 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1528 (match_operand:GPR 2 "reg_or_short_operand" ""))
1529 (const_int 0)))
1530 (clobber (match_scratch:GPR 3 ""))]
1531 "reload_completed"
1532 [(set (match_dup 3)
1533 (plus:GPR (match_dup 1)
1534 (match_dup 2)))
1535 (set (match_dup 0)
1536 (compare:CC (match_dup 3)
1537 (const_int 0)))]
1538 "")
1540 (define_insn "*add<mode>3_internal3"
1541 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1542 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1543 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1544 (const_int 0)))
1545 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1546 (plus:P (match_dup 1)
1547 (match_dup 2)))]
1548 ""
1549 "@
1550 {cax.|add.} %0,%1,%2
1551 {ai.|addic.} %0,%1,%2
1552 #
1553 #"
1554 [(set_attr "type" "fast_compare,compare,compare,compare")
1555 (set_attr "length" "4,4,8,8")])
1557 (define_split
1558 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1559 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1560 (match_operand:P 2 "reg_or_short_operand" ""))
1561 (const_int 0)))
1562 (set (match_operand:P 0 "gpc_reg_operand" "")
1563 (plus:P (match_dup 1) (match_dup 2)))]
1564 "reload_completed"
1565 [(set (match_dup 0)
1566 (plus:P (match_dup 1)
1567 (match_dup 2)))
1568 (set (match_dup 3)
1569 (compare:CC (match_dup 0)
1570 (const_int 0)))]
1571 "")
1573 ;; Split an add that we can't do in one insn into two insns, each of which
1574 ;; does one 16-bit part. This is used by combine. Note that the low-order
1575 ;; add should be last in case the result gets used in an address.
1577 (define_split
1578 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1579 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1580 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1581 ""
1582 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1583 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1584 {
1585 HOST_WIDE_INT val = INTVAL (operands[2]);
1586 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1587 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1589 operands[4] = GEN_INT (low);
1590 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1591 operands[3] = GEN_INT (rest);
1592 else if (! no_new_pseudos)
1593 {
1594 operands[3] = gen_reg_rtx (DImode);
1595 emit_move_insn (operands[3], operands[2]);
1596 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1597 DONE;
1598 }
1599 else
1600 FAIL;
1601 })
1603 (define_insn "one_cmpl<mode>2"
1604 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1605 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1606 ""
1607 "nor %0,%1,%1")
1609 (define_insn ""
1610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1611 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1612 (const_int 0)))
1613 (clobber (match_scratch:P 2 "=r,r"))]
1614 ""
1615 "@
1616 nor. %2,%1,%1
1617 #"
1618 [(set_attr "type" "compare")
1619 (set_attr "length" "4,8")])
1621 (define_split
1622 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1623 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1624 (const_int 0)))
1625 (clobber (match_scratch:P 2 ""))]
1626 "reload_completed"
1627 [(set (match_dup 2)
1628 (not:P (match_dup 1)))
1629 (set (match_dup 0)
1630 (compare:CC (match_dup 2)
1631 (const_int 0)))]
1632 "")
1634 (define_insn ""
1635 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1636 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1637 (const_int 0)))
1638 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1639 (not:P (match_dup 1)))]
1640 ""
1641 "@
1642 nor. %0,%1,%1
1643 #"
1644 [(set_attr "type" "compare")
1645 (set_attr "length" "4,8")])
1647 (define_split
1648 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1649 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1650 (const_int 0)))
1651 (set (match_operand:P 0 "gpc_reg_operand" "")
1652 (not:P (match_dup 1)))]
1653 "reload_completed"
1654 [(set (match_dup 0)
1655 (not:P (match_dup 1)))
1656 (set (match_dup 2)
1657 (compare:CC (match_dup 0)
1658 (const_int 0)))]
1659 "")
1661 (define_insn ""
1662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1663 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1664 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1665 "! TARGET_POWERPC"
1666 "{sf%I1|subf%I1c} %0,%2,%1")
1668 (define_insn ""
1669 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1670 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1671 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1672 "TARGET_POWERPC"
1673 "@
1674 subf %0,%2,%1
1675 subfic %0,%2,%1")
1677 (define_insn ""
1678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1679 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1680 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1681 (const_int 0)))
1682 (clobber (match_scratch:SI 3 "=r,r"))]
1683 "! TARGET_POWERPC"
1684 "@
1685 {sf.|subfc.} %3,%2,%1
1686 #"
1687 [(set_attr "type" "compare")
1688 (set_attr "length" "4,8")])
1690 (define_insn ""
1691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1692 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1693 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1694 (const_int 0)))
1695 (clobber (match_scratch:P 3 "=r,r"))]
1696 "TARGET_POWERPC"
1697 "@
1698 subf. %3,%2,%1
1699 #"
1700 [(set_attr "type" "fast_compare")
1701 (set_attr "length" "4,8")])
1703 (define_split
1704 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1705 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1706 (match_operand:P 2 "gpc_reg_operand" ""))
1707 (const_int 0)))
1708 (clobber (match_scratch:P 3 ""))]
1709 "reload_completed"
1710 [(set (match_dup 3)
1711 (minus:P (match_dup 1)
1712 (match_dup 2)))
1713 (set (match_dup 0)
1714 (compare:CC (match_dup 3)
1715 (const_int 0)))]
1716 "")
1718 (define_insn ""
1719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1720 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1721 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1722 (const_int 0)))
1723 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1724 (minus:SI (match_dup 1) (match_dup 2)))]
1725 "! TARGET_POWERPC"
1726 "@
1727 {sf.|subfc.} %0,%2,%1
1728 #"
1729 [(set_attr "type" "compare")
1730 (set_attr "length" "4,8")])
1732 (define_insn ""
1733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1734 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1735 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1736 (const_int 0)))
1737 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1738 (minus:P (match_dup 1)
1739 (match_dup 2)))]
1740 "TARGET_POWERPC"
1741 "@
1742 subf. %0,%2,%1
1743 #"
1744 [(set_attr "type" "fast_compare")
1745 (set_attr "length" "4,8")])
1747 (define_split
1748 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1749 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1750 (match_operand:P 2 "gpc_reg_operand" ""))
1751 (const_int 0)))
1752 (set (match_operand:P 0 "gpc_reg_operand" "")
1753 (minus:P (match_dup 1)
1754 (match_dup 2)))]
1755 "reload_completed"
1756 [(set (match_dup 0)
1757 (minus:P (match_dup 1)
1758 (match_dup 2)))
1759 (set (match_dup 3)
1760 (compare:CC (match_dup 0)
1761 (const_int 0)))]
1762 "")
1764 (define_expand "sub<mode>3"
1765 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1766 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1767 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1768 ""
1769 "
1770 {
1771 if (GET_CODE (operands[2]) == CONST_INT)
1772 {
1773 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1774 negate_rtx (<MODE>mode, operands[2])));
1775 DONE;
1776 }
1777 }")
1779 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1780 ;; instruction and some auxiliary computations. Then we just have a single
1781 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1782 ;; combine.
1784 (define_expand "sminsi3"
1785 [(set (match_dup 3)
1786 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1787 (match_operand:SI 2 "reg_or_short_operand" ""))
1788 (const_int 0)
1789 (minus:SI (match_dup 2) (match_dup 1))))
1790 (set (match_operand:SI 0 "gpc_reg_operand" "")
1791 (minus:SI (match_dup 2) (match_dup 3)))]
1792 "TARGET_POWER || TARGET_ISEL"
1793 "
1794 {
1795 if (TARGET_ISEL)
1796 {
1797 operands[2] = force_reg (SImode, operands[2]);
1798 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1799 DONE;
1800 }
1802 operands[3] = gen_reg_rtx (SImode);
1803 }")
1805 (define_split
1806 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1807 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1808 (match_operand:SI 2 "reg_or_short_operand" "")))
1809 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1810 "TARGET_POWER"
1811 [(set (match_dup 3)
1812 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1813 (const_int 0)
1814 (minus:SI (match_dup 2) (match_dup 1))))
1815 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1816 "")
1818 (define_expand "smaxsi3"
1819 [(set (match_dup 3)
1820 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1821 (match_operand:SI 2 "reg_or_short_operand" ""))
1822 (const_int 0)
1823 (minus:SI (match_dup 2) (match_dup 1))))
1824 (set (match_operand:SI 0 "gpc_reg_operand" "")
1825 (plus:SI (match_dup 3) (match_dup 1)))]
1826 "TARGET_POWER || TARGET_ISEL"
1827 "
1828 {
1829 if (TARGET_ISEL)
1830 {
1831 operands[2] = force_reg (SImode, operands[2]);
1832 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1833 DONE;
1834 }
1835 operands[3] = gen_reg_rtx (SImode);
1836 }")
1838 (define_split
1839 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1840 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1841 (match_operand:SI 2 "reg_or_short_operand" "")))
1842 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1843 "TARGET_POWER"
1844 [(set (match_dup 3)
1845 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1846 (const_int 0)
1847 (minus:SI (match_dup 2) (match_dup 1))))
1848 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1849 "")
1851 (define_expand "uminsi3"
1852 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1853 (match_dup 5)))
1854 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1855 (match_dup 5)))
1856 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1857 (const_int 0)
1858 (minus:SI (match_dup 4) (match_dup 3))))
1859 (set (match_operand:SI 0 "gpc_reg_operand" "")
1860 (minus:SI (match_dup 2) (match_dup 3)))]
1861 "TARGET_POWER || TARGET_ISEL"
1862 "
1863 {
1864 if (TARGET_ISEL)
1865 {
1866 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1867 DONE;
1868 }
1869 operands[3] = gen_reg_rtx (SImode);
1870 operands[4] = gen_reg_rtx (SImode);
1871 operands[5] = GEN_INT (-2147483647 - 1);
1872 }")
1874 (define_expand "umaxsi3"
1875 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_dup 5)))
1877 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1878 (match_dup 5)))
1879 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1880 (const_int 0)
1881 (minus:SI (match_dup 4) (match_dup 3))))
1882 (set (match_operand:SI 0 "gpc_reg_operand" "")
1883 (plus:SI (match_dup 3) (match_dup 1)))]
1884 "TARGET_POWER || TARGET_ISEL"
1885 "
1886 {
1887 if (TARGET_ISEL)
1888 {
1889 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1890 DONE;
1891 }
1892 operands[3] = gen_reg_rtx (SImode);
1893 operands[4] = gen_reg_rtx (SImode);
1894 operands[5] = GEN_INT (-2147483647 - 1);
1895 }")
1897 (define_insn ""
1898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1899 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1900 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1901 (const_int 0)
1902 (minus:SI (match_dup 2) (match_dup 1))))]
1903 "TARGET_POWER"
1904 "doz%I2 %0,%1,%2")
1906 (define_insn ""
1907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1908 (compare:CC
1909 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1910 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1911 (const_int 0)
1912 (minus:SI (match_dup 2) (match_dup 1)))
1913 (const_int 0)))
1914 (clobber (match_scratch:SI 3 "=r,r"))]
1915 "TARGET_POWER"
1916 "@
1917 doz%I2. %3,%1,%2
1918 #"
1919 [(set_attr "type" "delayed_compare")
1920 (set_attr "length" "4,8")])
1922 (define_split
1923 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1924 (compare:CC
1925 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1926 (match_operand:SI 2 "reg_or_short_operand" ""))
1927 (const_int 0)
1928 (minus:SI (match_dup 2) (match_dup 1)))
1929 (const_int 0)))
1930 (clobber (match_scratch:SI 3 ""))]
1931 "TARGET_POWER && reload_completed"
1932 [(set (match_dup 3)
1933 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1934 (const_int 0)
1935 (minus:SI (match_dup 2) (match_dup 1))))
1936 (set (match_dup 0)
1937 (compare:CC (match_dup 3)
1938 (const_int 0)))]
1939 "")
1941 (define_insn ""
1942 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1943 (compare:CC
1944 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1945 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1946 (const_int 0)
1947 (minus:SI (match_dup 2) (match_dup 1)))
1948 (const_int 0)))
1949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1950 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1951 (const_int 0)
1952 (minus:SI (match_dup 2) (match_dup 1))))]
1953 "TARGET_POWER"
1954 "@
1955 doz%I2. %0,%1,%2
1956 #"
1957 [(set_attr "type" "delayed_compare")
1958 (set_attr "length" "4,8")])
1960 (define_split
1961 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1962 (compare:CC
1963 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1964 (match_operand:SI 2 "reg_or_short_operand" ""))
1965 (const_int 0)
1966 (minus:SI (match_dup 2) (match_dup 1)))
1967 (const_int 0)))
1968 (set (match_operand:SI 0 "gpc_reg_operand" "")
1969 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1970 (const_int 0)
1971 (minus:SI (match_dup 2) (match_dup 1))))]
1972 "TARGET_POWER && reload_completed"
1973 [(set (match_dup 0)
1974 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1975 (const_int 0)
1976 (minus:SI (match_dup 2) (match_dup 1))))
1977 (set (match_dup 3)
1978 (compare:CC (match_dup 0)
1979 (const_int 0)))]
1980 "")
1982 ;; We don't need abs with condition code because such comparisons should
1983 ;; never be done.
1984 (define_expand "abssi2"
1985 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1986 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1987 ""
1988 "
1989 {
1990 if (TARGET_ISEL)
1991 {
1992 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1993 DONE;
1994 }
1995 else if (! TARGET_POWER)
1996 {
1997 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1998 DONE;
1999 }
2000 }")
2002 (define_insn "*abssi2_power"
2003 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2004 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2005 "TARGET_POWER"
2006 "abs %0,%1")
2008 (define_insn_and_split "abssi2_isel"
2009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2010 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2011 (clobber (match_scratch:SI 2 "=&b"))
2012 (clobber (match_scratch:CC 3 "=y"))]
2013 "TARGET_ISEL"
2014 "#"
2015 "&& reload_completed"
2016 [(set (match_dup 2) (neg:SI (match_dup 1)))
2017 (set (match_dup 3)
2018 (compare:CC (match_dup 1)
2019 (const_int 0)))
2020 (set (match_dup 0)
2021 (if_then_else:SI (ge (match_dup 3)
2022 (const_int 0))
2023 (match_dup 1)
2024 (match_dup 2)))]
2025 "")
2027 (define_insn_and_split "abssi2_nopower"
2028 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2029 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2030 (clobber (match_scratch:SI 2 "=&r,&r"))]
2031 "! TARGET_POWER && ! TARGET_ISEL"
2032 "#"
2033 "&& reload_completed"
2034 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2035 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2036 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2037 "")
2039 (define_insn "*nabs_power"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2041 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2042 "TARGET_POWER"
2043 "nabs %0,%1")
2045 (define_insn_and_split "*nabs_nopower"
2046 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2047 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2048 (clobber (match_scratch:SI 2 "=&r,&r"))]
2049 "! TARGET_POWER"
2050 "#"
2051 "&& reload_completed"
2052 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2053 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2054 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2055 "")
2057 (define_expand "neg<mode>2"
2058 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2059 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2060 ""
2061 "")
2063 (define_insn "*neg<mode>2_internal"
2064 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2065 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2066 ""
2067 "neg %0,%1")
2069 (define_insn ""
2070 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2071 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2072 (const_int 0)))
2073 (clobber (match_scratch:P 2 "=r,r"))]
2074 ""
2075 "@
2076 neg. %2,%1
2077 #"
2078 [(set_attr "type" "fast_compare")
2079 (set_attr "length" "4,8")])
2081 (define_split
2082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2083 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2084 (const_int 0)))
2085 (clobber (match_scratch:P 2 ""))]
2086 "reload_completed"
2087 [(set (match_dup 2)
2088 (neg:P (match_dup 1)))
2089 (set (match_dup 0)
2090 (compare:CC (match_dup 2)
2091 (const_int 0)))]
2092 "")
2094 (define_insn ""
2095 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2096 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2097 (const_int 0)))
2098 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2099 (neg:P (match_dup 1)))]
2100 ""
2101 "@
2102 neg. %0,%1
2103 #"
2104 [(set_attr "type" "fast_compare")
2105 (set_attr "length" "4,8")])
2107 (define_split
2108 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2109 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2110 (const_int 0)))
2111 (set (match_operand:P 0 "gpc_reg_operand" "")
2112 (neg:P (match_dup 1)))]
2113 "reload_completed"
2114 [(set (match_dup 0)
2115 (neg:P (match_dup 1)))
2116 (set (match_dup 2)
2117 (compare:CC (match_dup 0)
2118 (const_int 0)))]
2119 "")
2121 (define_insn "clz<mode>2"
2122 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2123 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2124 ""
2125 "{cntlz|cntlz<wd>} %0,%1"
2126 [(set_attr "type" "cntlz")])
2128 (define_expand "ctz<mode>2"
2129 [(set (match_dup 2)
2130 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2131 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2132 (match_dup 2)))
2133 (clobber (scratch:CC))])
2134 (set (match_dup 4) (clz:GPR (match_dup 3)))
2135 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2136 (minus:GPR (match_dup 5) (match_dup 4)))]
2137 ""
2138 {
2139 operands[2] = gen_reg_rtx (<MODE>mode);
2140 operands[3] = gen_reg_rtx (<MODE>mode);
2141 operands[4] = gen_reg_rtx (<MODE>mode);
2142 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2143 })
2145 (define_expand "ffs<mode>2"
2146 [(set (match_dup 2)
2147 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2148 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2149 (match_dup 2)))
2150 (clobber (scratch:CC))])
2151 (set (match_dup 4) (clz:GPR (match_dup 3)))
2152 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2153 (minus:GPR (match_dup 5) (match_dup 4)))]
2154 ""
2155 {
2156 operands[2] = gen_reg_rtx (<MODE>mode);
2157 operands[3] = gen_reg_rtx (<MODE>mode);
2158 operands[4] = gen_reg_rtx (<MODE>mode);
2159 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2160 })
2162 (define_expand "popcount<mode>2"
2163 [(set (match_dup 2)
2164 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2165 UNSPEC_POPCNTB))
2166 (set (match_dup 3)
2167 (mult:GPR (match_dup 2) (match_dup 4)))
2168 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2169 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2170 "TARGET_POPCNTB"
2171 {
2172 operands[2] = gen_reg_rtx (<MODE>mode);
2173 operands[3] = gen_reg_rtx (<MODE>mode);
2174 operands[4] = force_reg (<MODE>mode,
2175 <MODE>mode == SImode
2176 ? GEN_INT (0x01010101)
2177 : GEN_INT ((HOST_WIDE_INT)
2178 0x01010101 << 32 | 0x01010101));
2179 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2180 })
2182 (define_insn "popcntb<mode>2"
2183 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2184 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2185 UNSPEC_POPCNTB))]
2186 "TARGET_POPCNTB"
2187 "popcntb %0,%1")
2189 (define_expand "mulsi3"
2190 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2191 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2192 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2193 ""
2194 "
2195 {
2196 if (TARGET_POWER)
2197 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2198 else
2199 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2200 DONE;
2201 }")
2203 (define_insn "mulsi3_mq"
2204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2205 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2206 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2207 (clobber (match_scratch:SI 3 "=q,q"))]
2208 "TARGET_POWER"
2209 "@
2210 {muls|mullw} %0,%1,%2
2211 {muli|mulli} %0,%1,%2"
2212 [(set (attr "type")
2213 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2214 (const_string "imul3")
2215 (match_operand:SI 2 "short_cint_operand" "")
2216 (const_string "imul2")]
2217 (const_string "imul")))])
2219 (define_insn "mulsi3_no_mq"
2220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2221 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2222 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2223 "! TARGET_POWER"
2224 "@
2225 {muls|mullw} %0,%1,%2
2226 {muli|mulli} %0,%1,%2"
2227 [(set (attr "type")
2228 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2229 (const_string "imul3")
2230 (match_operand:SI 2 "short_cint_operand" "")
2231 (const_string "imul2")]
2232 (const_string "imul")))])
2234 (define_insn "*mulsi3_mq_internal1"
2235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2236 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2237 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2238 (const_int 0)))
2239 (clobber (match_scratch:SI 3 "=r,r"))
2240 (clobber (match_scratch:SI 4 "=q,q"))]
2241 "TARGET_POWER"
2242 "@
2243 {muls.|mullw.} %3,%1,%2
2244 #"
2245 [(set_attr "type" "imul_compare")
2246 (set_attr "length" "4,8")])
2248 (define_split
2249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2250 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2251 (match_operand:SI 2 "gpc_reg_operand" ""))
2252 (const_int 0)))
2253 (clobber (match_scratch:SI 3 ""))
2254 (clobber (match_scratch:SI 4 ""))]
2255 "TARGET_POWER && reload_completed"
2256 [(parallel [(set (match_dup 3)
2257 (mult:SI (match_dup 1) (match_dup 2)))
2258 (clobber (match_dup 4))])
2259 (set (match_dup 0)
2260 (compare:CC (match_dup 3)
2261 (const_int 0)))]
2262 "")
2264 (define_insn "*mulsi3_no_mq_internal1"
2265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2266 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2267 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2268 (const_int 0)))
2269 (clobber (match_scratch:SI 3 "=r,r"))]
2270 "! TARGET_POWER"
2271 "@
2272 {muls.|mullw.} %3,%1,%2
2273 #"
2274 [(set_attr "type" "imul_compare")
2275 (set_attr "length" "4,8")])
2277 (define_split
2278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2279 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2280 (match_operand:SI 2 "gpc_reg_operand" ""))
2281 (const_int 0)))
2282 (clobber (match_scratch:SI 3 ""))]
2283 "! TARGET_POWER && reload_completed"
2284 [(set (match_dup 3)
2285 (mult:SI (match_dup 1) (match_dup 2)))
2286 (set (match_dup 0)
2287 (compare:CC (match_dup 3)
2288 (const_int 0)))]
2289 "")
2291 (define_insn "*mulsi3_mq_internal2"
2292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2295 (const_int 0)))
2296 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2297 (mult:SI (match_dup 1) (match_dup 2)))
2298 (clobber (match_scratch:SI 4 "=q,q"))]
2299 "TARGET_POWER"
2300 "@
2301 {muls.|mullw.} %0,%1,%2
2302 #"
2303 [(set_attr "type" "imul_compare")
2304 (set_attr "length" "4,8")])
2306 (define_split
2307 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2308 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2309 (match_operand:SI 2 "gpc_reg_operand" ""))
2310 (const_int 0)))
2311 (set (match_operand:SI 0 "gpc_reg_operand" "")
2312 (mult:SI (match_dup 1) (match_dup 2)))
2313 (clobber (match_scratch:SI 4 ""))]
2314 "TARGET_POWER && reload_completed"
2315 [(parallel [(set (match_dup 0)
2316 (mult:SI (match_dup 1) (match_dup 2)))
2317 (clobber (match_dup 4))])
2318 (set (match_dup 3)
2319 (compare:CC (match_dup 0)
2320 (const_int 0)))]
2321 "")
2323 (define_insn "*mulsi3_no_mq_internal2"
2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2325 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2326 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2327 (const_int 0)))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2329 (mult:SI (match_dup 1) (match_dup 2)))]
2330 "! TARGET_POWER"
2331 "@
2332 {muls.|mullw.} %0,%1,%2
2333 #"
2334 [(set_attr "type" "imul_compare")
2335 (set_attr "length" "4,8")])
2337 (define_split
2338 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2339 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2340 (match_operand:SI 2 "gpc_reg_operand" ""))
2341 (const_int 0)))
2342 (set (match_operand:SI 0 "gpc_reg_operand" "")
2343 (mult:SI (match_dup 1) (match_dup 2)))]
2344 "! TARGET_POWER && reload_completed"
2345 [(set (match_dup 0)
2346 (mult:SI (match_dup 1) (match_dup 2)))
2347 (set (match_dup 3)
2348 (compare:CC (match_dup 0)
2349 (const_int 0)))]
2350 "")
2352 ;; Operand 1 is divided by operand 2; quotient goes to operand
2353 ;; 0 and remainder to operand 3.
2354 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2356 (define_expand "divmodsi4"
2357 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2359 (match_operand:SI 2 "gpc_reg_operand" "")))
2360 (set (match_operand:SI 3 "register_operand" "")
2361 (mod:SI (match_dup 1) (match_dup 2)))])]
2362 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2363 "
2364 {
2365 if (! TARGET_POWER && ! TARGET_POWERPC)
2366 {
2367 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2368 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2369 emit_insn (gen_divss_call ());
2370 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2371 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2372 DONE;
2373 }
2374 }")
2376 (define_insn "*divmodsi4_internal"
2377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2378 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2379 (match_operand:SI 2 "gpc_reg_operand" "r")))
2380 (set (match_operand:SI 3 "register_operand" "=q")
2381 (mod:SI (match_dup 1) (match_dup 2)))]
2382 "TARGET_POWER"
2383 "divs %0,%1,%2"
2384 [(set_attr "type" "idiv")])
2386 (define_expand "udiv<mode>3"
2387 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2388 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2389 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2390 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2391 "
2392 {
2393 if (! TARGET_POWER && ! TARGET_POWERPC)
2394 {
2395 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2396 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2397 emit_insn (gen_quous_call ());
2398 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2399 DONE;
2400 }
2401 else if (TARGET_POWER)
2402 {
2403 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2404 DONE;
2405 }
2406 }")
2408 (define_insn "udivsi3_mq"
2409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2410 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2411 (match_operand:SI 2 "gpc_reg_operand" "r")))
2412 (clobber (match_scratch:SI 3 "=q"))]
2413 "TARGET_POWERPC && TARGET_POWER"
2414 "divwu %0,%1,%2"
2415 [(set_attr "type" "idiv")])
2417 (define_insn "*udivsi3_no_mq"
2418 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2419 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2420 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2421 "TARGET_POWERPC && ! TARGET_POWER"
2422 "div<wd>u %0,%1,%2"
2423 [(set (attr "type")
2424 (cond [(match_operand:SI 0 "" "")
2425 (const_string "idiv")]
2426 (const_string "ldiv")))])
2429 ;; For powers of two we can do srai/aze for divide and then adjust for
2430 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2431 ;; used; for PowerPC, force operands into register and do a normal divide;
2432 ;; for AIX common-mode, use quoss call on register operands.
2433 (define_expand "div<mode>3"
2434 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2435 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2436 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2437 ""
2438 "
2439 {
2440 if (GET_CODE (operands[2]) == CONST_INT
2441 && INTVAL (operands[2]) > 0
2442 && exact_log2 (INTVAL (operands[2])) >= 0)
2443 ;
2444 else if (TARGET_POWERPC)
2445 {
2446 operands[2] = force_reg (<MODE>mode, operands[2]);
2447 if (TARGET_POWER)
2448 {
2449 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2450 DONE;
2451 }
2452 }
2453 else if (TARGET_POWER)
2454 FAIL;
2455 else
2456 {
2457 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2458 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2459 emit_insn (gen_quoss_call ());
2460 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2461 DONE;
2462 }
2463 }")
2465 (define_insn "divsi3_mq"
2466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2467 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2468 (match_operand:SI 2 "gpc_reg_operand" "r")))
2469 (clobber (match_scratch:SI 3 "=q"))]
2470 "TARGET_POWERPC && TARGET_POWER"
2471 "divw %0,%1,%2"
2472 [(set_attr "type" "idiv")])
2474 (define_insn "*div<mode>3_no_mq"
2475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2476 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2477 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2478 "TARGET_POWERPC && ! TARGET_POWER"
2479 "div<wd> %0,%1,%2"
2480 [(set (attr "type")
2481 (cond [(match_operand:SI 0 "" "")
2482 (const_string "idiv")]
2483 (const_string "ldiv")))])
2485 (define_expand "mod<mode>3"
2486 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2487 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2488 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2489 ""
2490 "
2491 {
2492 int i;
2493 rtx temp1;
2494 rtx temp2;
2496 if (GET_CODE (operands[2]) != CONST_INT
2497 || INTVAL (operands[2]) <= 0
2498 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2499 FAIL;
2501 temp1 = gen_reg_rtx (<MODE>mode);
2502 temp2 = gen_reg_rtx (<MODE>mode);
2504 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2505 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2506 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2507 DONE;
2508 }")
2510 (define_insn ""
2511 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2512 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2513 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2514 ""
2515 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2516 [(set_attr "type" "two")
2517 (set_attr "length" "8")])
2519 (define_insn ""
2520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2521 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2522 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2523 (const_int 0)))
2524 (clobber (match_scratch:P 3 "=r,r"))]
2525 ""
2526 "@
2527 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2528 #"
2529 [(set_attr "type" "compare")
2530 (set_attr "length" "8,12")])
2532 (define_split
2533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2534 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2535 (match_operand:GPR 2 "exact_log2_cint_operand"
2536 ""))
2537 (const_int 0)))
2538 (clobber (match_scratch:GPR 3 ""))]
2539 "reload_completed"
2540 [(set (match_dup 3)
2541 (div:<MODE> (match_dup 1) (match_dup 2)))
2542 (set (match_dup 0)
2543 (compare:CC (match_dup 3)
2544 (const_int 0)))]
2545 "")
2547 (define_insn ""
2548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2549 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2550 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2551 (const_int 0)))
2552 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2553 (div:P (match_dup 1) (match_dup 2)))]
2554 ""
2555 "@
2556 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2557 #"
2558 [(set_attr "type" "compare")
2559 (set_attr "length" "8,12")])
2561 (define_split
2562 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2563 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2564 (match_operand:GPR 2 "exact_log2_cint_operand"
2565 ""))
2566 (const_int 0)))
2567 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2568 (div:GPR (match_dup 1) (match_dup 2)))]
2569 "reload_completed"
2570 [(set (match_dup 0)
2571 (div:<MODE> (match_dup 1) (match_dup 2)))
2572 (set (match_dup 3)
2573 (compare:CC (match_dup 0)
2574 (const_int 0)))]
2575 "")
2577 (define_insn ""
2578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2579 (udiv:SI
2580 (plus:DI (ashift:DI
2581 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2582 (const_int 32))
2583 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2584 (match_operand:SI 3 "gpc_reg_operand" "r")))
2585 (set (match_operand:SI 2 "register_operand" "=*q")
2586 (umod:SI
2587 (plus:DI (ashift:DI
2588 (zero_extend:DI (match_dup 1)) (const_int 32))
2589 (zero_extend:DI (match_dup 4)))
2590 (match_dup 3)))]
2591 "TARGET_POWER"
2592 "div %0,%1,%3"
2593 [(set_attr "type" "idiv")])
2595 ;; To do unsigned divide we handle the cases of the divisor looking like a
2596 ;; negative number. If it is a constant that is less than 2**31, we don't
2597 ;; have to worry about the branches. So make a few subroutines here.
2598 ;;
2599 ;; First comes the normal case.
2600 (define_expand "udivmodsi4_normal"
2601 [(set (match_dup 4) (const_int 0))
2602 (parallel [(set (match_operand:SI 0 "" "")
2603 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2604 (const_int 32))
2605 (zero_extend:DI (match_operand:SI 1 "" "")))
2606 (match_operand:SI 2 "" "")))
2607 (set (match_operand:SI 3 "" "")
2608 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2609 (const_int 32))
2610 (zero_extend:DI (match_dup 1)))
2611 (match_dup 2)))])]
2612 "TARGET_POWER"
2613 "
2614 { operands[4] = gen_reg_rtx (SImode); }")
2616 ;; This handles the branches.
2617 (define_expand "udivmodsi4_tests"
2618 [(set (match_operand:SI 0 "" "") (const_int 0))
2619 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2620 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2621 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2622 (label_ref (match_operand:SI 4 "" "")) (pc)))
2623 (set (match_dup 0) (const_int 1))
2624 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2625 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2626 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2627 (label_ref (match_dup 4)) (pc)))]
2628 "TARGET_POWER"
2629 "
2630 { operands[5] = gen_reg_rtx (CCUNSmode);
2631 operands[6] = gen_reg_rtx (CCmode);
2632 }")
2634 (define_expand "udivmodsi4"
2635 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2636 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2637 (match_operand:SI 2 "reg_or_cint_operand" "")))
2638 (set (match_operand:SI 3 "gpc_reg_operand" "")
2639 (umod:SI (match_dup 1) (match_dup 2)))])]
2640 ""
2641 "
2642 {
2643 rtx label = 0;
2645 if (! TARGET_POWER)
2646 {
2647 if (! TARGET_POWERPC)
2648 {
2649 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2650 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2651 emit_insn (gen_divus_call ());
2652 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2653 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2654 DONE;
2655 }
2656 else
2657 FAIL;
2658 }
2660 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2661 {
2662 operands[2] = force_reg (SImode, operands[2]);
2663 label = gen_label_rtx ();
2664 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2665 operands[3], label));
2666 }
2667 else
2668 operands[2] = force_reg (SImode, operands[2]);
2670 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2671 operands[3]));
2672 if (label)
2673 emit_label (label);
2675 DONE;
2676 }")
2678 ;; AIX architecture-independent common-mode multiply (DImode),
2679 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2680 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2681 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2682 ;; assumed unused if generating common-mode, so ignore.
2683 (define_insn "mulh_call"
2684 [(set (reg:SI 3)
2685 (truncate:SI
2686 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2687 (sign_extend:DI (reg:SI 4)))
2688 (const_int 32))))
2689 (clobber (match_scratch:SI 0 "=l"))]
2690 "! TARGET_POWER && ! TARGET_POWERPC"
2691 "bla __mulh"
2692 [(set_attr "type" "imul")])
2694 (define_insn "mull_call"
2695 [(set (reg:DI 3)
2696 (mult:DI (sign_extend:DI (reg:SI 3))
2697 (sign_extend:DI (reg:SI 4))))
2698 (clobber (match_scratch:SI 0 "=l"))
2699 (clobber (reg:SI 0))]
2700 "! TARGET_POWER && ! TARGET_POWERPC"
2701 "bla __mull"
2702 [(set_attr "type" "imul")])
2704 (define_insn "divss_call"
2705 [(set (reg:SI 3)
2706 (div:SI (reg:SI 3) (reg:SI 4)))
2707 (set (reg:SI 4)
2708 (mod:SI (reg:SI 3) (reg:SI 4)))
2709 (clobber (match_scratch:SI 0 "=l"))
2710 (clobber (reg:SI 0))]
2711 "! TARGET_POWER && ! TARGET_POWERPC"
2712 "bla __divss"
2713 [(set_attr "type" "idiv")])
2715 (define_insn "divus_call"
2716 [(set (reg:SI 3)
2717 (udiv:SI (reg:SI 3) (reg:SI 4)))
2718 (set (reg:SI 4)
2719 (umod:SI (reg:SI 3) (reg:SI 4)))
2720 (clobber (match_scratch:SI 0 "=l"))
2721 (clobber (reg:SI 0))
2722 (clobber (match_scratch:CC 1 "=x"))
2723 (clobber (reg:CC 69))]
2724 "! TARGET_POWER && ! TARGET_POWERPC"
2725 "bla __divus"
2726 [(set_attr "type" "idiv")])
2728 (define_insn "quoss_call"
2729 [(set (reg:SI 3)
2730 (div:SI (reg:SI 3) (reg:SI 4)))
2731 (clobber (match_scratch:SI 0 "=l"))]
2732 "! TARGET_POWER && ! TARGET_POWERPC"
2733 "bla __quoss"
2734 [(set_attr "type" "idiv")])
2736 (define_insn "quous_call"
2737 [(set (reg:SI 3)
2738 (udiv:SI (reg:SI 3) (reg:SI 4)))
2739 (clobber (match_scratch:SI 0 "=l"))
2740 (clobber (reg:SI 0))
2741 (clobber (match_scratch:CC 1 "=x"))
2742 (clobber (reg:CC 69))]
2743 "! TARGET_POWER && ! TARGET_POWERPC"
2744 "bla __quous"
2745 [(set_attr "type" "idiv")])
2746 \f
2747 ;; Logical instructions
2748 ;; The logical instructions are mostly combined by using match_operator,
2749 ;; but the plain AND insns are somewhat different because there is no
2750 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2751 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2753 (define_insn "andsi3"
2754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2755 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2756 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2757 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2758 ""
2759 "@
2760 and %0,%1,%2
2761 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2762 {andil.|andi.} %0,%1,%b2
2763 {andiu.|andis.} %0,%1,%u2"
2764 [(set_attr "type" "*,*,compare,compare")])
2766 ;; Note to set cr's other than cr0 we do the and immediate and then
2767 ;; the test again -- this avoids a mfcr which on the higher end
2768 ;; machines causes an execution serialization
2770 (define_insn "*andsi3_internal2"
2771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2772 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2773 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2774 (const_int 0)))
2775 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2776 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2777 "TARGET_32BIT"
2778 "@
2779 and. %3,%1,%2
2780 {andil.|andi.} %3,%1,%b2
2781 {andiu.|andis.} %3,%1,%u2
2782 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2783 #
2784 #
2785 #
2786 #"
2787 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2788 (set_attr "length" "4,4,4,4,8,8,8,8")])
2790 (define_insn "*andsi3_internal3"
2791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2792 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2793 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2794 (const_int 0)))
2795 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2796 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2797 "TARGET_64BIT"
2798 "@
2799 #
2800 {andil.|andi.} %3,%1,%b2
2801 {andiu.|andis.} %3,%1,%u2
2802 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2803 #
2804 #
2805 #
2806 #"
2807 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2808 (set_attr "length" "8,4,4,4,8,8,8,8")])
2810 (define_split
2811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2812 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2813 (match_operand:GPR 2 "and_operand" ""))
2814 (const_int 0)))
2815 (clobber (match_scratch:GPR 3 ""))
2816 (clobber (match_scratch:CC 4 ""))]
2817 "reload_completed"
2818 [(parallel [(set (match_dup 3)
2819 (and:<MODE> (match_dup 1)
2820 (match_dup 2)))
2821 (clobber (match_dup 4))])
2822 (set (match_dup 0)
2823 (compare:CC (match_dup 3)
2824 (const_int 0)))]
2825 "")
2827 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2828 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2830 (define_split
2831 [(set (match_operand:CC 0 "cc_reg_operand" "")
2832 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2833 (match_operand:SI 2 "gpc_reg_operand" ""))
2834 (const_int 0)))
2835 (clobber (match_scratch:SI 3 ""))
2836 (clobber (match_scratch:CC 4 ""))]
2837 "TARGET_POWERPC64 && reload_completed"
2838 [(parallel [(set (match_dup 3)
2839 (and:SI (match_dup 1)
2840 (match_dup 2)))
2841 (clobber (match_dup 4))])
2842 (set (match_dup 0)
2843 (compare:CC (match_dup 3)
2844 (const_int 0)))]
2845 "")
2847 (define_insn "*andsi3_internal4"
2848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2850 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2851 (const_int 0)))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2853 (and:SI (match_dup 1)
2854 (match_dup 2)))
2855 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2856 "TARGET_32BIT"
2857 "@
2858 and. %0,%1,%2
2859 {andil.|andi.} %0,%1,%b2
2860 {andiu.|andis.} %0,%1,%u2
2861 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2862 #
2863 #
2864 #
2865 #"
2866 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2867 (set_attr "length" "4,4,4,4,8,8,8,8")])
2869 (define_insn "*andsi3_internal5"
2870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2871 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2872 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2873 (const_int 0)))
2874 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2875 (and:SI (match_dup 1)
2876 (match_dup 2)))
2877 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2878 "TARGET_64BIT"
2879 "@
2880 #
2881 {andil.|andi.} %0,%1,%b2
2882 {andiu.|andis.} %0,%1,%u2
2883 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2884 #
2885 #
2886 #
2887 #"
2888 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2889 (set_attr "length" "8,4,4,4,8,8,8,8")])
2891 (define_split
2892 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2893 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2894 (match_operand:SI 2 "and_operand" ""))
2895 (const_int 0)))
2896 (set (match_operand:SI 0 "gpc_reg_operand" "")
2897 (and:SI (match_dup 1)
2898 (match_dup 2)))
2899 (clobber (match_scratch:CC 4 ""))]
2900 "reload_completed"
2901 [(parallel [(set (match_dup 0)
2902 (and:SI (match_dup 1)
2903 (match_dup 2)))
2904 (clobber (match_dup 4))])
2905 (set (match_dup 3)
2906 (compare:CC (match_dup 0)
2907 (const_int 0)))]
2908 "")
2910 (define_split
2911 [(set (match_operand:CC 3 "cc_reg_operand" "")
2912 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2913 (match_operand:SI 2 "gpc_reg_operand" ""))
2914 (const_int 0)))
2915 (set (match_operand:SI 0 "gpc_reg_operand" "")
2916 (and:SI (match_dup 1)
2917 (match_dup 2)))
2918 (clobber (match_scratch:CC 4 ""))]
2919 "TARGET_POWERPC64 && reload_completed"
2920 [(parallel [(set (match_dup 0)
2921 (and:SI (match_dup 1)
2922 (match_dup 2)))
2923 (clobber (match_dup 4))])
2924 (set (match_dup 3)
2925 (compare:CC (match_dup 0)
2926 (const_int 0)))]
2927 "")
2929 ;; Handle the PowerPC64 rlwinm corner case
2931 (define_insn_and_split "*andsi3_internal6"
2932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2933 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2934 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2935 "TARGET_POWERPC64"
2936 "#"
2937 "TARGET_POWERPC64"
2938 [(set (match_dup 0)
2939 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2940 (match_dup 4)))
2941 (set (match_dup 0)
2942 (rotate:SI (match_dup 0) (match_dup 5)))]
2943 "
2944 {
2945 int mb = extract_MB (operands[2]);
2946 int me = extract_ME (operands[2]);
2947 operands[3] = GEN_INT (me + 1);
2948 operands[5] = GEN_INT (32 - (me + 1));
2949 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2950 }"
2951 [(set_attr "length" "8")])
2953 (define_expand "iorsi3"
2954 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2955 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2956 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2957 ""
2958 "
2959 {
2960 if (GET_CODE (operands[2]) == CONST_INT
2961 && ! logical_operand (operands[2], SImode))
2962 {
2963 HOST_WIDE_INT value = INTVAL (operands[2]);
2964 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2965 ? operands[0] : gen_reg_rtx (SImode));
2967 emit_insn (gen_iorsi3 (tmp, operands[1],
2968 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2969 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2970 DONE;
2971 }
2972 }")
2974 (define_expand "xorsi3"
2975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2976 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2977 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2978 ""
2979 "
2980 {
2981 if (GET_CODE (operands[2]) == CONST_INT
2982 && ! logical_operand (operands[2], SImode))
2983 {
2984 HOST_WIDE_INT value = INTVAL (operands[2]);
2985 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2986 ? operands[0] : gen_reg_rtx (SImode));
2988 emit_insn (gen_xorsi3 (tmp, operands[1],
2989 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2990 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2991 DONE;
2992 }
2993 }")
2995 (define_insn "*boolsi3_internal1"
2996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2997 (match_operator:SI 3 "boolean_or_operator"
2998 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2999 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3000 ""
3001 "@
3002 %q3 %0,%1,%2
3003 {%q3il|%q3i} %0,%1,%b2
3004 {%q3iu|%q3is} %0,%1,%u2")
3006 (define_insn "*boolsi3_internal2"
3007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3008 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3009 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3010 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3011 (const_int 0)))
3012 (clobber (match_scratch:SI 3 "=r,r"))]
3013 "TARGET_32BIT"
3014 "@
3015 %q4. %3,%1,%2
3016 #"
3017 [(set_attr "type" "compare")
3018 (set_attr "length" "4,8")])
3020 (define_split
3021 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3022 (compare:CC (match_operator:SI 4 "boolean_operator"
3023 [(match_operand:SI 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "gpc_reg_operand" "")])
3025 (const_int 0)))
3026 (clobber (match_scratch:SI 3 ""))]
3027 "TARGET_32BIT && reload_completed"
3028 [(set (match_dup 3) (match_dup 4))
3029 (set (match_dup 0)
3030 (compare:CC (match_dup 3)
3031 (const_int 0)))]
3032 "")
3034 (define_insn "*boolsi3_internal3"
3035 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3036 (compare:CC (match_operator:SI 4 "boolean_operator"
3037 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3038 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3039 (const_int 0)))
3040 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3041 (match_dup 4))]
3042 "TARGET_32BIT"
3043 "@
3044 %q4. %0,%1,%2
3045 #"
3046 [(set_attr "type" "compare")
3047 (set_attr "length" "4,8")])
3049 (define_split
3050 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3051 (compare:CC (match_operator:SI 4 "boolean_operator"
3052 [(match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "gpc_reg_operand" "")])
3054 (const_int 0)))
3055 (set (match_operand:SI 0 "gpc_reg_operand" "")
3056 (match_dup 4))]
3057 "TARGET_32BIT && reload_completed"
3058 [(set (match_dup 0) (match_dup 4))
3059 (set (match_dup 3)
3060 (compare:CC (match_dup 0)
3061 (const_int 0)))]
3062 "")
3064 ;; Split a logical operation that we can't do in one insn into two insns,
3065 ;; each of which does one 16-bit part. This is used by combine.
3067 (define_split
3068 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3069 (match_operator:SI 3 "boolean_or_operator"
3070 [(match_operand:SI 1 "gpc_reg_operand" "")
3071 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3072 ""
3073 [(set (match_dup 0) (match_dup 4))
3074 (set (match_dup 0) (match_dup 5))]
3075 "
3076 {
3077 rtx i;
3078 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3079 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3080 operands[1], i);
3081 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3082 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3083 operands[0], i);
3084 }")
3086 (define_insn "*boolcsi3_internal1"
3087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3088 (match_operator:SI 3 "boolean_operator"
3089 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3090 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3091 ""
3092 "%q3 %0,%2,%1")
3094 (define_insn "*boolcsi3_internal2"
3095 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3096 (compare:CC (match_operator:SI 4 "boolean_operator"
3097 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3098 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3099 (const_int 0)))
3100 (clobber (match_scratch:SI 3 "=r,r"))]
3101 "TARGET_32BIT"
3102 "@
3103 %q4. %3,%2,%1
3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "4,8")])
3108 (define_split
3109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3110 (compare:CC (match_operator:SI 4 "boolean_operator"
3111 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3112 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (const_int 0)))
3114 (clobber (match_scratch:SI 3 ""))]
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 3) (match_dup 4))
3117 (set (match_dup 0)
3118 (compare:CC (match_dup 3)
3119 (const_int 0)))]
3120 "")
3122 (define_insn "*boolcsi3_internal3"
3123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3124 (compare:CC (match_operator:SI 4 "boolean_operator"
3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3126 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3127 (const_int 0)))
3128 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3129 (match_dup 4))]
3130 "TARGET_32BIT"
3131 "@
3132 %q4. %0,%2,%1
3133 #"
3134 [(set_attr "type" "compare")
3135 (set_attr "length" "4,8")])
3137 (define_split
3138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3139 (compare:CC (match_operator:SI 4 "boolean_operator"
3140 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3141 (match_operand:SI 2 "gpc_reg_operand" "")])
3142 (const_int 0)))
3143 (set (match_operand:SI 0 "gpc_reg_operand" "")
3144 (match_dup 4))]
3145 "TARGET_32BIT && reload_completed"
3146 [(set (match_dup 0) (match_dup 4))
3147 (set (match_dup 3)
3148 (compare:CC (match_dup 0)
3149 (const_int 0)))]
3150 "")
3152 (define_insn "*boolccsi3_internal1"
3153 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3154 (match_operator:SI 3 "boolean_operator"
3155 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3156 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3157 ""
3158 "%q3 %0,%1,%2")
3160 (define_insn "*boolccsi3_internal2"
3161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3162 (compare:CC (match_operator:SI 4 "boolean_operator"
3163 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3164 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3165 (const_int 0)))
3166 (clobber (match_scratch:SI 3 "=r,r"))]
3167 "TARGET_32BIT"
3168 "@
3169 %q4. %3,%1,%2
3170 #"
3171 [(set_attr "type" "compare")
3172 (set_attr "length" "4,8")])
3174 (define_split
3175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3176 (compare:CC (match_operator:SI 4 "boolean_operator"
3177 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3178 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3179 (const_int 0)))
3180 (clobber (match_scratch:SI 3 ""))]
3181 "TARGET_32BIT && reload_completed"
3182 [(set (match_dup 3) (match_dup 4))
3183 (set (match_dup 0)
3184 (compare:CC (match_dup 3)
3185 (const_int 0)))]
3186 "")
3188 (define_insn "*boolccsi3_internal3"
3189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3190 (compare:CC (match_operator:SI 4 "boolean_operator"
3191 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3192 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3193 (const_int 0)))
3194 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3195 (match_dup 4))]
3196 "TARGET_32BIT"
3197 "@
3198 %q4. %0,%1,%2
3199 #"
3200 [(set_attr "type" "compare")
3201 (set_attr "length" "4,8")])
3203 (define_split
3204 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3205 (compare:CC (match_operator:SI 4 "boolean_operator"
3206 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3207 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3208 (const_int 0)))
3209 (set (match_operand:SI 0 "gpc_reg_operand" "")
3210 (match_dup 4))]
3211 "TARGET_32BIT && reload_completed"
3212 [(set (match_dup 0) (match_dup 4))
3213 (set (match_dup 3)
3214 (compare:CC (match_dup 0)
3215 (const_int 0)))]
3216 "")
3218 ;; maskir insn. We need four forms because things might be in arbitrary
3219 ;; orders. Don't define forms that only set CR fields because these
3220 ;; would modify an input register.
3222 (define_insn "*maskir_internal1"
3223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3224 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3225 (match_operand:SI 1 "gpc_reg_operand" "0"))
3226 (and:SI (match_dup 2)
3227 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3228 "TARGET_POWER"
3229 "maskir %0,%3,%2")
3231 (define_insn "*maskir_internal2"
3232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3233 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3234 (match_operand:SI 1 "gpc_reg_operand" "0"))
3235 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3236 (match_dup 2))))]
3237 "TARGET_POWER"
3238 "maskir %0,%3,%2")
3240 (define_insn "*maskir_internal3"
3241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3242 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3243 (match_operand:SI 3 "gpc_reg_operand" "r"))
3244 (and:SI (not:SI (match_dup 2))
3245 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3246 "TARGET_POWER"
3247 "maskir %0,%3,%2")
3249 (define_insn "*maskir_internal4"
3250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3251 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3252 (match_operand:SI 2 "gpc_reg_operand" "r"))
3253 (and:SI (not:SI (match_dup 2))
3254 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3255 "TARGET_POWER"
3256 "maskir %0,%3,%2")
3258 (define_insn "*maskir_internal5"
3259 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3260 (compare:CC
3261 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3262 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3263 (and:SI (match_dup 2)
3264 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3265 (const_int 0)))
3266 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3267 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3268 (and:SI (match_dup 2) (match_dup 3))))]
3269 "TARGET_POWER"
3270 "@
3271 maskir. %0,%3,%2
3272 #"
3273 [(set_attr "type" "compare")
3274 (set_attr "length" "4,8")])
3276 (define_split
3277 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3278 (compare:CC
3279 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3280 (match_operand:SI 1 "gpc_reg_operand" ""))
3281 (and:SI (match_dup 2)
3282 (match_operand:SI 3 "gpc_reg_operand" "")))
3283 (const_int 0)))
3284 (set (match_operand:SI 0 "gpc_reg_operand" "")
3285 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3286 (and:SI (match_dup 2) (match_dup 3))))]
3287 "TARGET_POWER && reload_completed"
3288 [(set (match_dup 0)
3289 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3290 (and:SI (match_dup 2) (match_dup 3))))
3291 (set (match_dup 4)
3292 (compare:CC (match_dup 0)
3293 (const_int 0)))]
3294 "")
3296 (define_insn "*maskir_internal6"
3297 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3298 (compare:CC
3299 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3300 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3301 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3302 (match_dup 2)))
3303 (const_int 0)))
3304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3305 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3306 (and:SI (match_dup 3) (match_dup 2))))]
3307 "TARGET_POWER"
3308 "@
3309 maskir. %0,%3,%2
3310 #"
3311 [(set_attr "type" "compare")
3312 (set_attr "length" "4,8")])
3314 (define_split
3315 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3316 (compare:CC
3317 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3318 (match_operand:SI 1 "gpc_reg_operand" ""))
3319 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3320 (match_dup 2)))
3321 (const_int 0)))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3324 (and:SI (match_dup 3) (match_dup 2))))]
3325 "TARGET_POWER && reload_completed"
3326 [(set (match_dup 0)
3327 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3328 (and:SI (match_dup 3) (match_dup 2))))
3329 (set (match_dup 4)
3330 (compare:CC (match_dup 0)
3331 (const_int 0)))]
3332 "")
3334 (define_insn "*maskir_internal7"
3335 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3336 (compare:CC
3337 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3339 (and:SI (not:SI (match_dup 2))
3340 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3341 (const_int 0)))
3342 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3343 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3344 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3345 "TARGET_POWER"
3346 "@
3347 maskir. %0,%3,%2
3348 #"
3349 [(set_attr "type" "compare")
3350 (set_attr "length" "4,8")])
3352 (define_split
3353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3354 (compare:CC
3355 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3356 (match_operand:SI 3 "gpc_reg_operand" ""))
3357 (and:SI (not:SI (match_dup 2))
3358 (match_operand:SI 1 "gpc_reg_operand" "")))
3359 (const_int 0)))
3360 (set (match_operand:SI 0 "gpc_reg_operand" "")
3361 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3362 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3363 "TARGET_POWER && reload_completed"
3364 [(set (match_dup 0)
3365 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3366 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3367 (set (match_dup 4)
3368 (compare:CC (match_dup 0)
3369 (const_int 0)))]
3370 "")
3372 (define_insn "*maskir_internal8"
3373 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3374 (compare:CC
3375 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3376 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3377 (and:SI (not:SI (match_dup 2))
3378 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3379 (const_int 0)))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3381 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3382 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3383 "TARGET_POWER"
3384 "@
3385 maskir. %0,%3,%2
3386 #"
3387 [(set_attr "type" "compare")
3388 (set_attr "length" "4,8")])
3390 (define_split
3391 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3392 (compare:CC
3393 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3394 (match_operand:SI 2 "gpc_reg_operand" ""))
3395 (and:SI (not:SI (match_dup 2))
3396 (match_operand:SI 1 "gpc_reg_operand" "")))
3397 (const_int 0)))
3398 (set (match_operand:SI 0 "gpc_reg_operand" "")
3399 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3400 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3401 "TARGET_POWER && reload_completed"
3402 [(set (match_dup 0)
3403 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3404 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3405 (set (match_dup 4)
3406 (compare:CC (match_dup 0)
3407 (const_int 0)))]
3408 "")
3409 \f
3410 ;; Rotate and shift insns, in all their variants. These support shifts,
3411 ;; field inserts and extracts, and various combinations thereof.
3412 (define_expand "insv"
3413 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3414 (match_operand:SI 1 "const_int_operand" "")
3415 (match_operand:SI 2 "const_int_operand" ""))
3416 (match_operand 3 "gpc_reg_operand" ""))]
3417 ""
3418 "
3419 {
3420 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3421 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3422 compiler if the address of the structure is taken later. Likewise, do
3423 not handle invalid E500 subregs. */
3424 if (GET_CODE (operands[0]) == SUBREG
3425 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3426 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3427 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3428 FAIL;
3430 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3431 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3432 else
3433 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3434 DONE;
3435 }")
3437 (define_insn "insvsi"
3438 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3439 (match_operand:SI 1 "const_int_operand" "i")
3440 (match_operand:SI 2 "const_int_operand" "i"))
3441 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3442 ""
3443 "*
3444 {
3445 int start = INTVAL (operands[2]) & 31;
3446 int size = INTVAL (operands[1]) & 31;
3448 operands[4] = GEN_INT (32 - start - size);
3449 operands[1] = GEN_INT (start + size - 1);
3450 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3451 }"
3452 [(set_attr "type" "insert_word")])
3454 (define_insn "*insvsi_internal1"
3455 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3456 (match_operand:SI 1 "const_int_operand" "i")
3457 (match_operand:SI 2 "const_int_operand" "i"))
3458 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3459 (match_operand:SI 4 "const_int_operand" "i")))]
3460 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3461 "*
3462 {
3463 int shift = INTVAL (operands[4]) & 31;
3464 int start = INTVAL (operands[2]) & 31;
3465 int size = INTVAL (operands[1]) & 31;
3467 operands[4] = GEN_INT (shift - start - size);
3468 operands[1] = GEN_INT (start + size - 1);
3469 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3470 }"
3471 [(set_attr "type" "insert_word")])
3473 (define_insn "*insvsi_internal2"
3474 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3475 (match_operand:SI 1 "const_int_operand" "i")
3476 (match_operand:SI 2 "const_int_operand" "i"))
3477 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3478 (match_operand:SI 4 "const_int_operand" "i")))]
3479 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3480 "*
3481 {
3482 int shift = INTVAL (operands[4]) & 31;
3483 int start = INTVAL (operands[2]) & 31;
3484 int size = INTVAL (operands[1]) & 31;
3486 operands[4] = GEN_INT (32 - shift - start - size);
3487 operands[1] = GEN_INT (start + size - 1);
3488 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3489 }"
3490 [(set_attr "type" "insert_word")])
3492 (define_insn "*insvsi_internal3"
3493 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3494 (match_operand:SI 1 "const_int_operand" "i")
3495 (match_operand:SI 2 "const_int_operand" "i"))
3496 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3497 (match_operand:SI 4 "const_int_operand" "i")))]
3498 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3499 "*
3500 {
3501 int shift = INTVAL (operands[4]) & 31;
3502 int start = INTVAL (operands[2]) & 31;
3503 int size = INTVAL (operands[1]) & 31;
3505 operands[4] = GEN_INT (32 - shift - start - size);
3506 operands[1] = GEN_INT (start + size - 1);
3507 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3508 }"
3509 [(set_attr "type" "insert_word")])
3511 (define_insn "*insvsi_internal4"
3512 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3513 (match_operand:SI 1 "const_int_operand" "i")
3514 (match_operand:SI 2 "const_int_operand" "i"))
3515 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3516 (match_operand:SI 4 "const_int_operand" "i")
3517 (match_operand:SI 5 "const_int_operand" "i")))]
3518 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3519 "*
3520 {
3521 int extract_start = INTVAL (operands[5]) & 31;
3522 int extract_size = INTVAL (operands[4]) & 31;
3523 int insert_start = INTVAL (operands[2]) & 31;
3524 int insert_size = INTVAL (operands[1]) & 31;
3526 /* Align extract field with insert field */
3527 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3528 operands[1] = GEN_INT (insert_start + insert_size - 1);
3529 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3530 }"
3531 [(set_attr "type" "insert_word")])
3533 ;; combine patterns for rlwimi
3534 (define_insn "*insvsi_internal5"
3535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3536 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3537 (match_operand:SI 1 "mask_operand" "i"))
3538 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3539 (match_operand:SI 2 "const_int_operand" "i"))
3540 (match_operand:SI 5 "mask_operand" "i"))))]
3541 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3542 "*
3543 {
3544 int me = extract_ME(operands[5]);
3545 int mb = extract_MB(operands[5]);
3546 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3547 operands[2] = GEN_INT(mb);
3548 operands[1] = GEN_INT(me);
3549 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3550 }"
3551 [(set_attr "type" "insert_word")])
3553 (define_insn "*insvsi_internal6"
3554 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3555 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 2 "const_int_operand" "i"))
3557 (match_operand:SI 5 "mask_operand" "i"))
3558 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3559 (match_operand:SI 1 "mask_operand" "i"))))]
3560 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3561 "*
3562 {
3563 int me = extract_ME(operands[5]);
3564 int mb = extract_MB(operands[5]);
3565 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3566 operands[2] = GEN_INT(mb);
3567 operands[1] = GEN_INT(me);
3568 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3569 }"
3570 [(set_attr "type" "insert_word")])
3572 (define_insn "insvdi"
3573 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3574 (match_operand:SI 1 "const_int_operand" "i")
3575 (match_operand:SI 2 "const_int_operand" "i"))
3576 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3577 "TARGET_POWERPC64"
3578 "*
3579 {
3580 int start = INTVAL (operands[2]) & 63;
3581 int size = INTVAL (operands[1]) & 63;
3583 operands[1] = GEN_INT (64 - start - size);
3584 return \"rldimi %0,%3,%H1,%H2\";
3585 }"
3586 [(set_attr "type" "insert_dword")])
3588 (define_insn "*insvdi_internal2"
3589 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3590 (match_operand:SI 1 "const_int_operand" "i")
3591 (match_operand:SI 2 "const_int_operand" "i"))
3592 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3593 (match_operand:SI 4 "const_int_operand" "i")))]
3594 "TARGET_POWERPC64
3595 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3596 "*
3597 {
3598 int shift = INTVAL (operands[4]) & 63;
3599 int start = (INTVAL (operands[2]) & 63) - 32;
3600 int size = INTVAL (operands[1]) & 63;
3602 operands[4] = GEN_INT (64 - shift - start - size);
3603 operands[2] = GEN_INT (start);
3604 operands[1] = GEN_INT (start + size - 1);
3605 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3606 }")
3608 (define_insn "*insvdi_internal3"
3609 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3610 (match_operand:SI 1 "const_int_operand" "i")
3611 (match_operand:SI 2 "const_int_operand" "i"))
3612 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3613 (match_operand:SI 4 "const_int_operand" "i")))]
3614 "TARGET_POWERPC64
3615 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3616 "*
3617 {
3618 int shift = INTVAL (operands[4]) & 63;
3619 int start = (INTVAL (operands[2]) & 63) - 32;
3620 int size = INTVAL (operands[1]) & 63;
3622 operands[4] = GEN_INT (64 - shift - start - size);
3623 operands[2] = GEN_INT (start);
3624 operands[1] = GEN_INT (start + size - 1);
3625 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3626 }")
3628 (define_expand "extzv"
3629 [(set (match_operand 0 "gpc_reg_operand" "")
3630 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3631 (match_operand:SI 2 "const_int_operand" "")
3632 (match_operand:SI 3 "const_int_operand" "")))]
3633 ""
3634 "
3635 {
3636 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3637 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3638 compiler if the address of the structure is taken later. */
3639 if (GET_CODE (operands[0]) == SUBREG
3640 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3641 FAIL;
3643 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3644 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3645 else
3646 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3647 DONE;
3648 }")
3650 (define_insn "extzvsi"
3651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3652 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3653 (match_operand:SI 2 "const_int_operand" "i")
3654 (match_operand:SI 3 "const_int_operand" "i")))]
3655 ""
3656 "*
3657 {
3658 int start = INTVAL (operands[3]) & 31;
3659 int size = INTVAL (operands[2]) & 31;
3661 if (start + size >= 32)
3662 operands[3] = const0_rtx;
3663 else
3664 operands[3] = GEN_INT (start + size);
3665 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3666 }")
3668 (define_insn "*extzvsi_internal1"
3669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3670 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3671 (match_operand:SI 2 "const_int_operand" "i,i")
3672 (match_operand:SI 3 "const_int_operand" "i,i"))
3673 (const_int 0)))
3674 (clobber (match_scratch:SI 4 "=r,r"))]
3675 ""
3676 "*
3677 {
3678 int start = INTVAL (operands[3]) & 31;
3679 int size = INTVAL (operands[2]) & 31;
3681 /* Force split for non-cc0 compare. */
3682 if (which_alternative == 1)
3683 return \"#\";
3685 /* If the bit-field being tested fits in the upper or lower half of a
3686 word, it is possible to use andiu. or andil. to test it. This is
3687 useful because the condition register set-use delay is smaller for
3688 andi[ul]. than for rlinm. This doesn't work when the starting bit
3689 position is 0 because the LT and GT bits may be set wrong. */
3691 if ((start > 0 && start + size <= 16) || start >= 16)
3692 {
3693 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3694 - (1 << (16 - (start & 15) - size))));
3695 if (start < 16)
3696 return \"{andiu.|andis.} %4,%1,%3\";
3697 else
3698 return \"{andil.|andi.} %4,%1,%3\";
3699 }
3701 if (start + size >= 32)
3702 operands[3] = const0_rtx;
3703 else
3704 operands[3] = GEN_INT (start + size);
3705 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3706 }"
3707 [(set_attr "type" "delayed_compare")
3708 (set_attr "length" "4,8")])
3710 (define_split
3711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3712 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3713 (match_operand:SI 2 "const_int_operand" "")
3714 (match_operand:SI 3 "const_int_operand" ""))
3715 (const_int 0)))
3716 (clobber (match_scratch:SI 4 ""))]
3717 "reload_completed"
3718 [(set (match_dup 4)
3719 (zero_extract:SI (match_dup 1) (match_dup 2)
3720 (match_dup 3)))
3721 (set (match_dup 0)
3722 (compare:CC (match_dup 4)
3723 (const_int 0)))]
3724 "")
3726 (define_insn "*extzvsi_internal2"
3727 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3728 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3729 (match_operand:SI 2 "const_int_operand" "i,i")
3730 (match_operand:SI 3 "const_int_operand" "i,i"))
3731 (const_int 0)))
3732 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3733 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3734 ""
3735 "*
3736 {
3737 int start = INTVAL (operands[3]) & 31;
3738 int size = INTVAL (operands[2]) & 31;
3740 /* Force split for non-cc0 compare. */
3741 if (which_alternative == 1)
3742 return \"#\";
3744 /* Since we are using the output value, we can't ignore any need for
3745 a shift. The bit-field must end at the LSB. */
3746 if (start >= 16 && start + size == 32)
3747 {
3748 operands[3] = GEN_INT ((1 << size) - 1);
3749 return \"{andil.|andi.} %0,%1,%3\";
3750 }
3752 if (start + size >= 32)
3753 operands[3] = const0_rtx;
3754 else
3755 operands[3] = GEN_INT (start + size);
3756 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3757 }"
3758 [(set_attr "type" "delayed_compare")
3759 (set_attr "length" "4,8")])
3761 (define_split
3762 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3763 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3764 (match_operand:SI 2 "const_int_operand" "")
3765 (match_operand:SI 3 "const_int_operand" ""))
3766 (const_int 0)))
3767 (set (match_operand:SI 0 "gpc_reg_operand" "")
3768 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3769 "reload_completed"
3770 [(set (match_dup 0)
3771 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3772 (set (match_dup 4)
3773 (compare:CC (match_dup 0)
3774 (const_int 0)))]
3775 "")
3777 (define_insn "extzvdi"
3778 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3779 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3780 (match_operand:SI 2 "const_int_operand" "i")
3781 (match_operand:SI 3 "const_int_operand" "i")))]
3782 "TARGET_POWERPC64"
3783 "*
3784 {
3785 int start = INTVAL (operands[3]) & 63;
3786 int size = INTVAL (operands[2]) & 63;
3788 if (start + size >= 64)
3789 operands[3] = const0_rtx;
3790 else
3791 operands[3] = GEN_INT (start + size);
3792 operands[2] = GEN_INT (64 - size);
3793 return \"rldicl %0,%1,%3,%2\";
3794 }")
3796 (define_insn "*extzvdi_internal1"
3797 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3798 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3799 (match_operand:SI 2 "const_int_operand" "i")
3800 (match_operand:SI 3 "const_int_operand" "i"))
3801 (const_int 0)))
3802 (clobber (match_scratch:DI 4 "=r"))]
3803 "TARGET_64BIT"
3804 "*
3805 {
3806 int start = INTVAL (operands[3]) & 63;
3807 int size = INTVAL (operands[2]) & 63;
3809 if (start + size >= 64)
3810 operands[3] = const0_rtx;
3811 else
3812 operands[3] = GEN_INT (start + size);
3813 operands[2] = GEN_INT (64 - size);
3814 return \"rldicl. %4,%1,%3,%2\";
3815 }"
3816 [(set_attr "type" "compare")])
3818 (define_insn "*extzvdi_internal2"
3819 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3820 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3821 (match_operand:SI 2 "const_int_operand" "i")
3822 (match_operand:SI 3 "const_int_operand" "i"))
3823 (const_int 0)))
3824 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3825 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3826 "TARGET_64BIT"
3827 "*
3828 {
3829 int start = INTVAL (operands[3]) & 63;
3830 int size = INTVAL (operands[2]) & 63;
3832 if (start + size >= 64)
3833 operands[3] = const0_rtx;
3834 else
3835 operands[3] = GEN_INT (start + size);
3836 operands[2] = GEN_INT (64 - size);
3837 return \"rldicl. %0,%1,%3,%2\";
3838 }"
3839 [(set_attr "type" "compare")])
3841 (define_insn "rotlsi3"
3842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3843 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3845 ""
3846 "@
3847 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3848 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3849 [(set_attr "type" "var_shift_rotate,integer")])
3851 (define_insn "*rotlsi3_internal2"
3852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3853 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3854 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3855 (const_int 0)))
3856 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3857 ""
3858 "@
3859 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3860 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3861 #
3862 #"
3863 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3864 (set_attr "length" "4,4,8,8")])
3866 (define_split
3867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3868 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" ""))
3870 (const_int 0)))
3871 (clobber (match_scratch:SI 3 ""))]
3872 "reload_completed"
3873 [(set (match_dup 3)
3874 (rotate:SI (match_dup 1) (match_dup 2)))
3875 (set (match_dup 0)
3876 (compare:CC (match_dup 3)
3877 (const_int 0)))]
3878 "")
3880 (define_insn "*rotlsi3_internal3"
3881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3882 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3883 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3884 (const_int 0)))
3885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3886 (rotate:SI (match_dup 1) (match_dup 2)))]
3887 ""
3888 "@
3889 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3890 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3891 #
3892 #"
3893 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3894 (set_attr "length" "4,4,8,8")])
3896 (define_split
3897 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3898 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3899 (match_operand:SI 2 "reg_or_cint_operand" ""))
3900 (const_int 0)))
3901 (set (match_operand:SI 0 "gpc_reg_operand" "")
3902 (rotate:SI (match_dup 1) (match_dup 2)))]
3903 "reload_completed"
3904 [(set (match_dup 0)
3905 (rotate:SI (match_dup 1) (match_dup 2)))
3906 (set (match_dup 3)
3907 (compare:CC (match_dup 0)
3908 (const_int 0)))]
3909 "")
3911 (define_insn "*rotlsi3_internal4"
3912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3913 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3915 (match_operand:SI 3 "mask_operand" "n,n")))]
3916 ""
3917 "@
3918 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3919 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3920 [(set_attr "type" "var_shift_rotate,integer")])
3922 (define_insn "*rotlsi3_internal5"
3923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3924 (compare:CC (and:SI
3925 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3926 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3927 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3928 (const_int 0)))
3929 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3930 ""
3931 "@
3932 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3933 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3934 #
3935 #"
3936 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3937 (set_attr "length" "4,4,8,8")])
3939 (define_split
3940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3941 (compare:CC (and:SI
3942 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3943 (match_operand:SI 2 "reg_or_cint_operand" ""))
3944 (match_operand:SI 3 "mask_operand" ""))
3945 (const_int 0)))
3946 (clobber (match_scratch:SI 4 ""))]
3947 "reload_completed"
3948 [(set (match_dup 4)
3949 (and:SI (rotate:SI (match_dup 1)
3950 (match_dup 2))
3951 (match_dup 3)))
3952 (set (match_dup 0)
3953 (compare:CC (match_dup 4)
3954 (const_int 0)))]
3955 "")
3957 (define_insn "*rotlsi3_internal6"
3958 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3959 (compare:CC (and:SI
3960 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3961 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3962 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3963 (const_int 0)))
3964 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3965 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3966 ""
3967 "@
3968 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
3969 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3970 #
3971 #"
3972 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3973 (set_attr "length" "4,4,8,8")])
3975 (define_split
3976 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3977 (compare:CC (and:SI
3978 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3979 (match_operand:SI 2 "reg_or_cint_operand" ""))
3980 (match_operand:SI 3 "mask_operand" ""))
3981 (const_int 0)))
3982 (set (match_operand:SI 0 "gpc_reg_operand" "")
3983 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3984 "reload_completed"
3985 [(set (match_dup 0)
3986 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3987 (set (match_dup 4)
3988 (compare:CC (match_dup 0)
3989 (const_int 0)))]
3990 "")
3992 (define_insn "*rotlsi3_internal7"
3993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3994 (zero_extend:SI
3995 (subreg:QI
3996 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3997 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3998 ""
3999 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4001 (define_insn "*rotlsi3_internal8"
4002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4003 (compare:CC (zero_extend:SI
4004 (subreg:QI
4005 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4006 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4007 (const_int 0)))
4008 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4009 ""
4010 "@
4011 {rlnm.|rlwnm.} %3,%1,%2,0xff
4012 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4013 #
4014 #"
4015 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4016 (set_attr "length" "4,4,8,8")])
4018 (define_split
4019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4020 (compare:CC (zero_extend:SI
4021 (subreg:QI
4022 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4023 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4024 (const_int 0)))
4025 (clobber (match_scratch:SI 3 ""))]
4026 "reload_completed"
4027 [(set (match_dup 3)
4028 (zero_extend:SI (subreg:QI
4029 (rotate:SI (match_dup 1)
4030 (match_dup 2)) 0)))
4031 (set (match_dup 0)
4032 (compare:CC (match_dup 3)
4033 (const_int 0)))]
4034 "")
4036 (define_insn "*rotlsi3_internal9"
4037 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4038 (compare:CC (zero_extend:SI
4039 (subreg:QI
4040 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4041 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4044 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4045 ""
4046 "@
4047 {rlnm.|rlwnm.} %0,%1,%2,0xff
4048 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4049 #
4050 #"
4051 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4052 (set_attr "length" "4,4,8,8")])
4054 (define_split
4055 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4056 (compare:CC (zero_extend:SI
4057 (subreg:QI
4058 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4059 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4060 (const_int 0)))
4061 (set (match_operand:SI 0 "gpc_reg_operand" "")
4062 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4063 "reload_completed"
4064 [(set (match_dup 0)
4065 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4066 (set (match_dup 3)
4067 (compare:CC (match_dup 0)
4068 (const_int 0)))]
4069 "")
4071 (define_insn "*rotlsi3_internal10"
4072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4073 (zero_extend:SI
4074 (subreg:HI
4075 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4076 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4077 ""
4078 "@
4079 {rlnm|rlwnm} %0,%1,%2,0xffff
4080 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4081 [(set_attr "type" "var_shift_rotate,integer")])
4084 (define_insn "*rotlsi3_internal11"
4085 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4086 (compare:CC (zero_extend:SI
4087 (subreg:HI
4088 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4089 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4090 (const_int 0)))
4091 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4092 ""
4093 "@
4094 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4095 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4096 #
4097 #"
4098 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4099 (set_attr "length" "4,4,8,8")])
4101 (define_split
4102 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4103 (compare:CC (zero_extend:SI
4104 (subreg:HI
4105 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4106 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4107 (const_int 0)))
4108 (clobber (match_scratch:SI 3 ""))]
4109 "reload_completed"
4110 [(set (match_dup 3)
4111 (zero_extend:SI (subreg:HI
4112 (rotate:SI (match_dup 1)
4113 (match_dup 2)) 0)))
4114 (set (match_dup 0)
4115 (compare:CC (match_dup 3)
4116 (const_int 0)))]
4117 "")
4119 (define_insn "*rotlsi3_internal12"
4120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4121 (compare:CC (zero_extend:SI
4122 (subreg:HI
4123 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4125 (const_int 0)))
4126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4127 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4128 ""
4129 "@
4130 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4131 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4132 #
4133 #"
4134 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4135 (set_attr "length" "4,4,8,8")])
4137 (define_split
4138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4139 (compare:CC (zero_extend:SI
4140 (subreg:HI
4141 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4142 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4143 (const_int 0)))
4144 (set (match_operand:SI 0 "gpc_reg_operand" "")
4145 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4146 "reload_completed"
4147 [(set (match_dup 0)
4148 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4149 (set (match_dup 3)
4150 (compare:CC (match_dup 0)
4151 (const_int 0)))]
4152 "")
4154 ;; Note that we use "sle." instead of "sl." so that we can set
4155 ;; SHIFT_COUNT_TRUNCATED.
4157 (define_expand "ashlsi3"
4158 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4159 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4160 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4161 ""
4162 "
4163 {
4164 if (TARGET_POWER)
4165 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4166 else
4167 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4168 DONE;
4169 }")
4171 (define_insn "ashlsi3_power"
4172 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4173 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4174 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4175 (clobber (match_scratch:SI 3 "=q,X"))]
4176 "TARGET_POWER"
4177 "@
4178 sle %0,%1,%2
4179 {sli|slwi} %0,%1,%h2")
4181 (define_insn "ashlsi3_no_power"
4182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4183 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4184 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4185 "! TARGET_POWER"
4186 "@
4187 {sl|slw} %0,%1,%2
4188 {sli|slwi} %0,%1,%h2"
4189 [(set_attr "type" "var_shift_rotate,shift")])
4191 (define_insn ""
4192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4193 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4194 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4195 (const_int 0)))
4196 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4197 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4198 "TARGET_POWER"
4199 "@
4200 sle. %3,%1,%2
4201 {sli.|slwi.} %3,%1,%h2
4202 #
4203 #"
4204 [(set_attr "type" "delayed_compare")
4205 (set_attr "length" "4,4,8,8")])
4207 (define_split
4208 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4209 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4210 (match_operand:SI 2 "reg_or_cint_operand" ""))
4211 (const_int 0)))
4212 (clobber (match_scratch:SI 3 ""))
4213 (clobber (match_scratch:SI 4 ""))]
4214 "TARGET_POWER && reload_completed"
4215 [(parallel [(set (match_dup 3)
4216 (ashift:SI (match_dup 1) (match_dup 2)))
4217 (clobber (match_dup 4))])
4218 (set (match_dup 0)
4219 (compare:CC (match_dup 3)
4220 (const_int 0)))]
4221 "")
4223 (define_insn ""
4224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4225 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4226 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4227 (const_int 0)))
4228 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4229 "! TARGET_POWER && TARGET_32BIT"
4230 "@
4231 {sl.|slw.} %3,%1,%2
4232 {sli.|slwi.} %3,%1,%h2
4233 #
4234 #"
4235 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4236 (set_attr "length" "4,4,8,8")])
4238 (define_split
4239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4240 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4241 (match_operand:SI 2 "reg_or_cint_operand" ""))
4242 (const_int 0)))
4243 (clobber (match_scratch:SI 3 ""))]
4244 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4245 [(set (match_dup 3)
4246 (ashift:SI (match_dup 1) (match_dup 2)))
4247 (set (match_dup 0)
4248 (compare:CC (match_dup 3)
4249 (const_int 0)))]
4250 "")
4252 (define_insn ""
4253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4254 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4256 (const_int 0)))
4257 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4258 (ashift:SI (match_dup 1) (match_dup 2)))
4259 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4260 "TARGET_POWER"
4261 "@
4262 sle. %0,%1,%2
4263 {sli.|slwi.} %0,%1,%h2
4264 #
4265 #"
4266 [(set_attr "type" "delayed_compare")
4267 (set_attr "length" "4,4,8,8")])
4269 (define_split
4270 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4271 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4272 (match_operand:SI 2 "reg_or_cint_operand" ""))
4273 (const_int 0)))
4274 (set (match_operand:SI 0 "gpc_reg_operand" "")
4275 (ashift:SI (match_dup 1) (match_dup 2)))
4276 (clobber (match_scratch:SI 4 ""))]
4277 "TARGET_POWER && reload_completed"
4278 [(parallel [(set (match_dup 0)
4279 (ashift:SI (match_dup 1) (match_dup 2)))
4280 (clobber (match_dup 4))])
4281 (set (match_dup 3)
4282 (compare:CC (match_dup 0)
4283 (const_int 0)))]
4284 "")
4286 (define_insn ""
4287 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4288 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4289 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4290 (const_int 0)))
4291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4292 (ashift:SI (match_dup 1) (match_dup 2)))]
4293 "! TARGET_POWER && TARGET_32BIT"
4294 "@
4295 {sl.|slw.} %0,%1,%2
4296 {sli.|slwi.} %0,%1,%h2
4297 #
4298 #"
4299 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4300 (set_attr "length" "4,4,8,8")])
4302 (define_split
4303 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4304 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4305 (match_operand:SI 2 "reg_or_cint_operand" ""))
4306 (const_int 0)))
4307 (set (match_operand:SI 0 "gpc_reg_operand" "")
4308 (ashift:SI (match_dup 1) (match_dup 2)))]
4309 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4310 [(set (match_dup 0)
4311 (ashift:SI (match_dup 1) (match_dup 2)))
4312 (set (match_dup 3)
4313 (compare:CC (match_dup 0)
4314 (const_int 0)))]
4315 "")
4317 (define_insn "rlwinm"
4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4319 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4320 (match_operand:SI 2 "const_int_operand" "i"))
4321 (match_operand:SI 3 "mask_operand" "n")))]
4322 "includes_lshift_p (operands[2], operands[3])"
4323 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4325 (define_insn ""
4326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4327 (compare:CC
4328 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4329 (match_operand:SI 2 "const_int_operand" "i,i"))
4330 (match_operand:SI 3 "mask_operand" "n,n"))
4331 (const_int 0)))
4332 (clobber (match_scratch:SI 4 "=r,r"))]
4333 "includes_lshift_p (operands[2], operands[3])"
4334 "@
4335 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4336 #"
4337 [(set_attr "type" "delayed_compare")
4338 (set_attr "length" "4,8")])
4340 (define_split
4341 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4342 (compare:CC
4343 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "const_int_operand" ""))
4345 (match_operand:SI 3 "mask_operand" ""))
4346 (const_int 0)))
4347 (clobber (match_scratch:SI 4 ""))]
4348 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4349 [(set (match_dup 4)
4350 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4351 (match_dup 3)))
4352 (set (match_dup 0)
4353 (compare:CC (match_dup 4)
4354 (const_int 0)))]
4355 "")
4357 (define_insn ""
4358 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4359 (compare:CC
4360 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4361 (match_operand:SI 2 "const_int_operand" "i,i"))
4362 (match_operand:SI 3 "mask_operand" "n,n"))
4363 (const_int 0)))
4364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4365 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4366 "includes_lshift_p (operands[2], operands[3])"
4367 "@
4368 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4369 #"
4370 [(set_attr "type" "delayed_compare")
4371 (set_attr "length" "4,8")])
4373 (define_split
4374 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4375 (compare:CC
4376 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4377 (match_operand:SI 2 "const_int_operand" ""))
4378 (match_operand:SI 3 "mask_operand" ""))
4379 (const_int 0)))
4380 (set (match_operand:SI 0 "gpc_reg_operand" "")
4381 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4382 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4383 [(set (match_dup 0)
4384 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4385 (set (match_dup 4)
4386 (compare:CC (match_dup 0)
4387 (const_int 0)))]
4388 "")
4390 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4391 ;; "sli x,x,0".
4392 (define_expand "lshrsi3"
4393 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4394 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4395 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4396 ""
4397 "
4398 {
4399 if (TARGET_POWER)
4400 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4401 else
4402 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4403 DONE;
4404 }")
4406 (define_insn "lshrsi3_power"
4407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4408 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4409 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4410 (clobber (match_scratch:SI 3 "=q,X,X"))]
4411 "TARGET_POWER"
4412 "@
4413 sre %0,%1,%2
4414 mr %0,%1
4415 {s%A2i|s%A2wi} %0,%1,%h2")
4417 (define_insn "lshrsi3_no_power"
4418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4419 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4420 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4421 "! TARGET_POWER"
4422 "@
4423 mr %0,%1
4424 {sr|srw} %0,%1,%2
4425 {sri|srwi} %0,%1,%h2"
4426 [(set_attr "type" "integer,var_shift_rotate,shift")])
4428 (define_insn ""
4429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4430 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4431 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4432 (const_int 0)))
4433 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4434 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4435 "TARGET_POWER"
4436 "@
4437 sre. %3,%1,%2
4438 mr. %1,%1
4439 {s%A2i.|s%A2wi.} %3,%1,%h2
4440 #
4441 #
4442 #"
4443 [(set_attr "type" "delayed_compare")
4444 (set_attr "length" "4,4,4,8,8,8")])
4446 (define_split
4447 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4448 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4449 (match_operand:SI 2 "reg_or_cint_operand" ""))
4450 (const_int 0)))
4451 (clobber (match_scratch:SI 3 ""))
4452 (clobber (match_scratch:SI 4 ""))]
4453 "TARGET_POWER && reload_completed"
4454 [(parallel [(set (match_dup 3)
4455 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4456 (clobber (match_dup 4))])
4457 (set (match_dup 0)
4458 (compare:CC (match_dup 3)
4459 (const_int 0)))]
4460 "")
4462 (define_insn ""
4463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4464 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4466 (const_int 0)))
4467 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4468 "! TARGET_POWER && TARGET_32BIT"
4469 "@
4470 mr. %1,%1
4471 {sr.|srw.} %3,%1,%2
4472 {sri.|srwi.} %3,%1,%h2
4473 #
4474 #
4475 #"
4476 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4477 (set_attr "length" "4,4,4,8,8,8")])
4479 (define_split
4480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4481 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4482 (match_operand:SI 2 "reg_or_cint_operand" ""))
4483 (const_int 0)))
4484 (clobber (match_scratch:SI 3 ""))]
4485 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4486 [(set (match_dup 3)
4487 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4488 (set (match_dup 0)
4489 (compare:CC (match_dup 3)
4490 (const_int 0)))]
4491 "")
4493 (define_insn ""
4494 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4495 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4496 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4497 (const_int 0)))
4498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4499 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4500 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4501 "TARGET_POWER"
4502 "@
4503 sre. %0,%1,%2
4504 mr. %0,%1
4505 {s%A2i.|s%A2wi.} %0,%1,%h2
4506 #
4507 #
4508 #"
4509 [(set_attr "type" "delayed_compare")
4510 (set_attr "length" "4,4,4,8,8,8")])
4512 (define_split
4513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4514 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4515 (match_operand:SI 2 "reg_or_cint_operand" ""))
4516 (const_int 0)))
4517 (set (match_operand:SI 0 "gpc_reg_operand" "")
4518 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4519 (clobber (match_scratch:SI 4 ""))]
4520 "TARGET_POWER && reload_completed"
4521 [(parallel [(set (match_dup 0)
4522 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4523 (clobber (match_dup 4))])
4524 (set (match_dup 3)
4525 (compare:CC (match_dup 0)
4526 (const_int 0)))]
4527 "")
4529 (define_insn ""
4530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4531 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4532 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4533 (const_int 0)))
4534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4535 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4536 "! TARGET_POWER && TARGET_32BIT"
4537 "@
4538 mr. %0,%1
4539 {sr.|srw.} %0,%1,%2
4540 {sri.|srwi.} %0,%1,%h2
4541 #
4542 #
4543 #"
4544 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4545 (set_attr "length" "4,4,4,8,8,8")])
4547 (define_split
4548 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4549 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4550 (match_operand:SI 2 "reg_or_cint_operand" ""))
4551 (const_int 0)))
4552 (set (match_operand:SI 0 "gpc_reg_operand" "")
4553 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4554 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4555 [(set (match_dup 0)
4556 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4557 (set (match_dup 3)
4558 (compare:CC (match_dup 0)
4559 (const_int 0)))]
4560 "")
4562 (define_insn ""
4563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4564 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4565 (match_operand:SI 2 "const_int_operand" "i"))
4566 (match_operand:SI 3 "mask_operand" "n")))]
4567 "includes_rshift_p (operands[2], operands[3])"
4568 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4570 (define_insn ""
4571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4572 (compare:CC
4573 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4574 (match_operand:SI 2 "const_int_operand" "i,i"))
4575 (match_operand:SI 3 "mask_operand" "n,n"))
4576 (const_int 0)))
4577 (clobber (match_scratch:SI 4 "=r,r"))]
4578 "includes_rshift_p (operands[2], operands[3])"
4579 "@
4580 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4581 #"
4582 [(set_attr "type" "delayed_compare")
4583 (set_attr "length" "4,8")])
4585 (define_split
4586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4587 (compare:CC
4588 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4589 (match_operand:SI 2 "const_int_operand" ""))
4590 (match_operand:SI 3 "mask_operand" ""))
4591 (const_int 0)))
4592 (clobber (match_scratch:SI 4 ""))]
4593 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4594 [(set (match_dup 4)
4595 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4596 (match_dup 3)))
4597 (set (match_dup 0)
4598 (compare:CC (match_dup 4)
4599 (const_int 0)))]
4600 "")
4602 (define_insn ""
4603 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4604 (compare:CC
4605 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4606 (match_operand:SI 2 "const_int_operand" "i,i"))
4607 (match_operand:SI 3 "mask_operand" "n,n"))
4608 (const_int 0)))
4609 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4610 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4611 "includes_rshift_p (operands[2], operands[3])"
4612 "@
4613 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4614 #"
4615 [(set_attr "type" "delayed_compare")
4616 (set_attr "length" "4,8")])
4618 (define_split
4619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4620 (compare:CC
4621 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4622 (match_operand:SI 2 "const_int_operand" ""))
4623 (match_operand:SI 3 "mask_operand" ""))
4624 (const_int 0)))
4625 (set (match_operand:SI 0 "gpc_reg_operand" "")
4626 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4627 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4628 [(set (match_dup 0)
4629 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4630 (set (match_dup 4)
4631 (compare:CC (match_dup 0)
4632 (const_int 0)))]
4633 "")
4635 (define_insn ""
4636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4637 (zero_extend:SI
4638 (subreg:QI
4639 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4640 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4641 "includes_rshift_p (operands[2], GEN_INT (255))"
4642 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4644 (define_insn ""
4645 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4646 (compare:CC
4647 (zero_extend:SI
4648 (subreg:QI
4649 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4650 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4651 (const_int 0)))
4652 (clobber (match_scratch:SI 3 "=r,r"))]
4653 "includes_rshift_p (operands[2], GEN_INT (255))"
4654 "@
4655 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4656 #"
4657 [(set_attr "type" "delayed_compare")
4658 (set_attr "length" "4,8")])
4660 (define_split
4661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4662 (compare:CC
4663 (zero_extend:SI
4664 (subreg:QI
4665 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4666 (match_operand:SI 2 "const_int_operand" "")) 0))
4667 (const_int 0)))
4668 (clobber (match_scratch:SI 3 ""))]
4669 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4670 [(set (match_dup 3)
4671 (zero_extend:SI (subreg:QI
4672 (lshiftrt:SI (match_dup 1)
4673 (match_dup 2)) 0)))
4674 (set (match_dup 0)
4675 (compare:CC (match_dup 3)
4676 (const_int 0)))]
4677 "")
4679 (define_insn ""
4680 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4681 (compare:CC
4682 (zero_extend:SI
4683 (subreg:QI
4684 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4685 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4686 (const_int 0)))
4687 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4688 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4689 "includes_rshift_p (operands[2], GEN_INT (255))"
4690 "@
4691 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4692 #"
4693 [(set_attr "type" "delayed_compare")
4694 (set_attr "length" "4,8")])
4696 (define_split
4697 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4698 (compare:CC
4699 (zero_extend:SI
4700 (subreg:QI
4701 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4702 (match_operand:SI 2 "const_int_operand" "")) 0))
4703 (const_int 0)))
4704 (set (match_operand:SI 0 "gpc_reg_operand" "")
4705 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4706 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4707 [(set (match_dup 0)
4708 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4709 (set (match_dup 3)
4710 (compare:CC (match_dup 0)
4711 (const_int 0)))]
4712 "")
4714 (define_insn ""
4715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4716 (zero_extend:SI
4717 (subreg:HI
4718 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4719 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4720 "includes_rshift_p (operands[2], GEN_INT (65535))"
4721 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4723 (define_insn ""
4724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4725 (compare:CC
4726 (zero_extend:SI
4727 (subreg:HI
4728 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4729 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4730 (const_int 0)))
4731 (clobber (match_scratch:SI 3 "=r,r"))]
4732 "includes_rshift_p (operands[2], GEN_INT (65535))"
4733 "@
4734 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4735 #"
4736 [(set_attr "type" "delayed_compare")
4737 (set_attr "length" "4,8")])
4739 (define_split
4740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4741 (compare:CC
4742 (zero_extend:SI
4743 (subreg:HI
4744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4745 (match_operand:SI 2 "const_int_operand" "")) 0))
4746 (const_int 0)))
4747 (clobber (match_scratch:SI 3 ""))]
4748 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4749 [(set (match_dup 3)
4750 (zero_extend:SI (subreg:HI
4751 (lshiftrt:SI (match_dup 1)
4752 (match_dup 2)) 0)))
4753 (set (match_dup 0)
4754 (compare:CC (match_dup 3)
4755 (const_int 0)))]
4756 "")
4758 (define_insn ""
4759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4760 (compare:CC
4761 (zero_extend:SI
4762 (subreg:HI
4763 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4764 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4765 (const_int 0)))
4766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4767 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4768 "includes_rshift_p (operands[2], GEN_INT (65535))"
4769 "@
4770 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4771 #"
4772 [(set_attr "type" "delayed_compare")
4773 (set_attr "length" "4,8")])
4775 (define_split
4776 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4777 (compare:CC
4778 (zero_extend:SI
4779 (subreg:HI
4780 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4781 (match_operand:SI 2 "const_int_operand" "")) 0))
4782 (const_int 0)))
4783 (set (match_operand:SI 0 "gpc_reg_operand" "")
4784 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4785 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4786 [(set (match_dup 0)
4787 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4788 (set (match_dup 3)
4789 (compare:CC (match_dup 0)
4790 (const_int 0)))]
4791 "")
4793 (define_insn ""
4794 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4795 (const_int 1)
4796 (match_operand:SI 1 "gpc_reg_operand" "r"))
4797 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4798 (const_int 31)))]
4799 "TARGET_POWER"
4800 "rrib %0,%1,%2")
4802 (define_insn ""
4803 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4804 (const_int 1)
4805 (match_operand:SI 1 "gpc_reg_operand" "r"))
4806 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4807 (const_int 31)))]
4808 "TARGET_POWER"
4809 "rrib %0,%1,%2")
4811 (define_insn ""
4812 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4813 (const_int 1)
4814 (match_operand:SI 1 "gpc_reg_operand" "r"))
4815 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4816 (const_int 1)
4817 (const_int 0)))]
4818 "TARGET_POWER"
4819 "rrib %0,%1,%2")
4821 (define_expand "ashrsi3"
4822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4823 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4824 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4825 ""
4826 "
4827 {
4828 if (TARGET_POWER)
4829 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4830 else
4831 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4832 DONE;
4833 }")
4835 (define_insn "ashrsi3_power"
4836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4837 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4838 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4839 (clobber (match_scratch:SI 3 "=q,X"))]
4840 "TARGET_POWER"
4841 "@
4842 srea %0,%1,%2
4843 {srai|srawi} %0,%1,%h2"
4844 [(set_attr "type" "shift")])
4846 (define_insn "ashrsi3_no_power"
4847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4848 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4849 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4850 "! TARGET_POWER"
4851 "@
4852 {sra|sraw} %0,%1,%2
4853 {srai|srawi} %0,%1,%h2"
4854 [(set_attr "type" "var_shift_rotate,shift")])
4856 (define_insn ""
4857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4858 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4859 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4860 (const_int 0)))
4861 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4862 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4863 "TARGET_POWER"
4864 "@
4865 srea. %3,%1,%2
4866 {srai.|srawi.} %3,%1,%h2
4867 #
4868 #"
4869 [(set_attr "type" "delayed_compare")
4870 (set_attr "length" "4,4,8,8")])
4872 (define_split
4873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4874 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4875 (match_operand:SI 2 "reg_or_cint_operand" ""))
4876 (const_int 0)))
4877 (clobber (match_scratch:SI 3 ""))
4878 (clobber (match_scratch:SI 4 ""))]
4879 "TARGET_POWER && reload_completed"
4880 [(parallel [(set (match_dup 3)
4881 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4882 (clobber (match_dup 4))])
4883 (set (match_dup 0)
4884 (compare:CC (match_dup 3)
4885 (const_int 0)))]
4886 "")
4888 (define_insn ""
4889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4890 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4891 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4892 (const_int 0)))
4893 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4894 "! TARGET_POWER"
4895 "@
4896 {sra.|sraw.} %3,%1,%2
4897 {srai.|srawi.} %3,%1,%h2
4898 #
4899 #"
4900 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4901 (set_attr "length" "4,4,8,8")])
4903 (define_split
4904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4905 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4906 (match_operand:SI 2 "reg_or_cint_operand" ""))
4907 (const_int 0)))
4908 (clobber (match_scratch:SI 3 ""))]
4909 "! TARGET_POWER && reload_completed"
4910 [(set (match_dup 3)
4911 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4912 (set (match_dup 0)
4913 (compare:CC (match_dup 3)
4914 (const_int 0)))]
4915 "")
4917 (define_insn ""
4918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4919 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4921 (const_int 0)))
4922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4923 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4924 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4925 "TARGET_POWER"
4926 "@
4927 srea. %0,%1,%2
4928 {srai.|srawi.} %0,%1,%h2
4929 #
4930 #"
4931 [(set_attr "type" "delayed_compare")
4932 (set_attr "length" "4,4,8,8")])
4934 (define_split
4935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4936 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4937 (match_operand:SI 2 "reg_or_cint_operand" ""))
4938 (const_int 0)))
4939 (set (match_operand:SI 0 "gpc_reg_operand" "")
4940 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4941 (clobber (match_scratch:SI 4 ""))]
4942 "TARGET_POWER && reload_completed"
4943 [(parallel [(set (match_dup 0)
4944 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4945 (clobber (match_dup 4))])
4946 (set (match_dup 3)
4947 (compare:CC (match_dup 0)
4948 (const_int 0)))]
4949 "")
4951 (define_insn ""
4952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4953 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4954 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4955 (const_int 0)))
4956 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4957 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4958 "! TARGET_POWER"
4959 "@
4960 {sra.|sraw.} %0,%1,%2
4961 {srai.|srawi.} %0,%1,%h2
4962 #
4963 #"
4964 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4965 (set_attr "length" "4,4,8,8")])
4966 \f
4967 (define_split
4968 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4969 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" ""))
4971 (const_int 0)))
4972 (set (match_operand:SI 0 "gpc_reg_operand" "")
4973 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4974 "! TARGET_POWER && reload_completed"
4975 [(set (match_dup 0)
4976 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4977 (set (match_dup 3)
4978 (compare:CC (match_dup 0)
4979 (const_int 0)))]
4980 "")
4982 ;; Floating-point insns, excluding normal data motion.
4983 ;;
4984 ;; PowerPC has a full set of single-precision floating point instructions.
4985 ;;
4986 ;; For the POWER architecture, we pretend that we have both SFmode and
4987 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4988 ;; The only conversions we will do will be when storing to memory. In that
4989 ;; case, we will use the "frsp" instruction before storing.
4990 ;;
4991 ;; Note that when we store into a single-precision memory location, we need to
4992 ;; use the frsp insn first. If the register being stored isn't dead, we
4993 ;; need a scratch register for the frsp. But this is difficult when the store
4994 ;; is done by reload. It is not incorrect to do the frsp on the register in
4995 ;; this case, we just lose precision that we would have otherwise gotten but
4996 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4998 (define_expand "extendsfdf2"
4999 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5000 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5001 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5002 "")
5004 (define_insn_and_split "*extendsfdf2_fpr"
5005 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5006 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5007 "TARGET_HARD_FLOAT && TARGET_FPRS"
5008 "@
5009 #
5010 fmr %0,%1
5011 lfs%U1%X1 %0,%1"
5012 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5013 [(const_int 0)]
5014 {
5015 emit_note (NOTE_INSN_DELETED);
5016 DONE;
5017 }
5018 [(set_attr "type" "fp,fp,fpload")])
5020 (define_expand "truncdfsf2"
5021 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5022 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5023 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5024 "")
5026 (define_insn "*truncdfsf2_fpr"
5027 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5028 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5029 "TARGET_HARD_FLOAT && TARGET_FPRS"
5030 "frsp %0,%1"
5031 [(set_attr "type" "fp")])
5033 (define_insn "aux_truncdfsf2"
5034 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5035 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5036 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5037 "frsp %0,%1"
5038 [(set_attr "type" "fp")])
5040 (define_expand "negsf2"
5041 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5042 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5043 "TARGET_HARD_FLOAT"
5044 "")
5046 (define_insn "*negsf2"
5047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5048 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5049 "TARGET_HARD_FLOAT && TARGET_FPRS"
5050 "fneg %0,%1"
5051 [(set_attr "type" "fp")])
5053 (define_expand "abssf2"
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5055 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT"
5057 "")
5059 (define_insn "*abssf2"
5060 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5061 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5062 "TARGET_HARD_FLOAT && TARGET_FPRS"
5063 "fabs %0,%1"
5064 [(set_attr "type" "fp")])
5066 (define_insn ""
5067 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5068 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5069 "TARGET_HARD_FLOAT && TARGET_FPRS"
5070 "fnabs %0,%1"
5071 [(set_attr "type" "fp")])
5073 (define_expand "addsf3"
5074 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5075 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5076 (match_operand:SF 2 "gpc_reg_operand" "")))]
5077 "TARGET_HARD_FLOAT"
5078 "")
5080 (define_insn ""
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5082 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5083 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5084 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5085 "fadds %0,%1,%2"
5086 [(set_attr "type" "fp")])
5088 (define_insn ""
5089 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5090 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5091 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5092 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5093 "{fa|fadd} %0,%1,%2"
5094 [(set_attr "type" "fp")])
5096 (define_expand "subsf3"
5097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5098 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5099 (match_operand:SF 2 "gpc_reg_operand" "")))]
5100 "TARGET_HARD_FLOAT"
5101 "")
5103 (define_insn ""
5104 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5105 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5106 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5107 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5108 "fsubs %0,%1,%2"
5109 [(set_attr "type" "fp")])
5111 (define_insn ""
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5113 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5114 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5115 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5116 "{fs|fsub} %0,%1,%2"
5117 [(set_attr "type" "fp")])
5119 (define_expand "mulsf3"
5120 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5121 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5122 (match_operand:SF 2 "gpc_reg_operand" "")))]
5123 "TARGET_HARD_FLOAT"
5124 "")
5126 (define_insn ""
5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5129 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5130 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5131 "fmuls %0,%1,%2"
5132 [(set_attr "type" "fp")])
5134 (define_insn ""
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5136 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5137 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5138 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5139 "{fm|fmul} %0,%1,%2"
5140 [(set_attr "type" "dmul")])
5142 (define_insn "fres"
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5144 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5145 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5146 "fres %0,%1"
5147 [(set_attr "type" "fp")])
5149 (define_expand "divsf3"
5150 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5151 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5152 (match_operand:SF 2 "gpc_reg_operand" "")))]
5153 "TARGET_HARD_FLOAT"
5154 {
5155 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5156 && flag_finite_math_only && !flag_trapping_math)
5157 {
5158 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5159 DONE;
5160 }
5161 })
5163 (define_insn ""
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5166 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5167 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5168 "fdivs %0,%1,%2"
5169 [(set_attr "type" "sdiv")])
5171 (define_insn ""
5172 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5173 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5174 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5175 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5176 "{fd|fdiv} %0,%1,%2"
5177 [(set_attr "type" "ddiv")])
5179 (define_insn ""
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5181 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5182 (match_operand:SF 2 "gpc_reg_operand" "f"))
5183 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5184 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5185 "fmadds %0,%1,%2,%3"
5186 [(set_attr "type" "fp")])
5188 (define_insn ""
5189 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5190 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5191 (match_operand:SF 2 "gpc_reg_operand" "f"))
5192 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5193 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5194 "{fma|fmadd} %0,%1,%2,%3"
5195 [(set_attr "type" "dmul")])
5197 (define_insn ""
5198 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5199 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5200 (match_operand:SF 2 "gpc_reg_operand" "f"))
5201 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5202 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5203 "fmsubs %0,%1,%2,%3"
5204 [(set_attr "type" "fp")])
5206 (define_insn ""
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f"))
5210 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5211 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5212 "{fms|fmsub} %0,%1,%2,%3"
5213 [(set_attr "type" "dmul")])
5215 (define_insn ""
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5217 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5218 (match_operand:SF 2 "gpc_reg_operand" "f"))
5219 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5220 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5221 && HONOR_SIGNED_ZEROS (SFmode)"
5222 "fnmadds %0,%1,%2,%3"
5223 [(set_attr "type" "fp")])
5225 (define_insn ""
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5228 (match_operand:SF 2 "gpc_reg_operand" "f"))
5229 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5230 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5231 && ! HONOR_SIGNED_ZEROS (SFmode)"
5232 "fnmadds %0,%1,%2,%3"
5233 [(set_attr "type" "fp")])
5235 (define_insn ""
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f"))
5239 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5240 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5241 "{fnma|fnmadd} %0,%1,%2,%3"
5242 [(set_attr "type" "dmul")])
5244 (define_insn ""
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5249 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5250 && ! HONOR_SIGNED_ZEROS (SFmode)"
5251 "{fnma|fnmadd} %0,%1,%2,%3"
5252 [(set_attr "type" "dmul")])
5254 (define_insn ""
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f"))
5258 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5259 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5260 && HONOR_SIGNED_ZEROS (SFmode)"
5261 "fnmsubs %0,%1,%2,%3"
5262 [(set_attr "type" "fp")])
5264 (define_insn ""
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5266 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5267 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5268 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5269 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5270 && ! HONOR_SIGNED_ZEROS (SFmode)"
5271 "fnmsubs %0,%1,%2,%3"
5272 [(set_attr "type" "fp")])
5274 (define_insn ""
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5276 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5277 (match_operand:SF 2 "gpc_reg_operand" "f"))
5278 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5279 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5280 "{fnms|fnmsub} %0,%1,%2,%3"
5281 [(set_attr "type" "dmul")])
5283 (define_insn ""
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5286 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5287 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5288 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5289 && ! HONOR_SIGNED_ZEROS (SFmode)"
5290 "{fnms|fnmsub} %0,%1,%2,%3"
5291 [(set_attr "type" "dmul")])
5293 (define_expand "sqrtsf2"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5296 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5297 "")
5299 (define_insn ""
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5302 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5303 "fsqrts %0,%1"
5304 [(set_attr "type" "ssqrt")])
5306 (define_insn ""
5307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5308 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5309 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5310 "fsqrt %0,%1"
5311 [(set_attr "type" "dsqrt")])
5313 (define_expand "copysignsf3"
5314 [(set (match_dup 3)
5315 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5316 (set (match_dup 4)
5317 (neg:SF (abs:SF (match_dup 1))))
5318 (set (match_operand:SF 0 "gpc_reg_operand" "")
5319 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5320 (match_dup 5))
5321 (match_dup 3)
5322 (match_dup 4)))]
5323 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5324 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5325 {
5326 operands[3] = gen_reg_rtx (SFmode);
5327 operands[4] = gen_reg_rtx (SFmode);
5328 operands[5] = CONST0_RTX (SFmode);
5329 })
5331 (define_expand "copysigndf3"
5332 [(set (match_dup 3)
5333 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5334 (set (match_dup 4)
5335 (neg:DF (abs:DF (match_dup 1))))
5336 (set (match_operand:DF 0 "gpc_reg_operand" "")
5337 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5338 (match_dup 5))
5339 (match_dup 3)
5340 (match_dup 4)))]
5341 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5342 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5343 {
5344 operands[3] = gen_reg_rtx (DFmode);
5345 operands[4] = gen_reg_rtx (DFmode);
5346 operands[5] = CONST0_RTX (DFmode);
5347 })
5349 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5350 ;; fsel instruction and some auxiliary computations. Then we just have a
5351 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5352 ;; combine.
5353 (define_expand "smaxsf3"
5354 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5355 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5356 (match_operand:SF 2 "gpc_reg_operand" ""))
5357 (match_dup 1)
5358 (match_dup 2)))]
5359 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5360 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5362 (define_expand "sminsf3"
5363 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5364 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5365 (match_operand:SF 2 "gpc_reg_operand" ""))
5366 (match_dup 2)
5367 (match_dup 1)))]
5368 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5369 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5371 (define_split
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5373 (match_operator:SF 3 "min_max_operator"
5374 [(match_operand:SF 1 "gpc_reg_operand" "")
5375 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5376 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5377 [(const_int 0)]
5378 "
5379 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5380 operands[1], operands[2]);
5381 DONE;
5382 }")
5384 (define_expand "movsicc"
5385 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5386 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5387 (match_operand:SI 2 "gpc_reg_operand" "")
5388 (match_operand:SI 3 "gpc_reg_operand" "")))]
5389 "TARGET_ISEL"
5390 "
5391 {
5392 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5393 DONE;
5394 else
5395 FAIL;
5396 }")
5398 ;; We use the BASE_REGS for the isel input operands because, if rA is
5399 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5400 ;; because we may switch the operands and rB may end up being rA.
5401 ;;
5402 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5403 ;; leave out the mode in operand 4 and use one pattern, but reload can
5404 ;; change the mode underneath our feet and then gets confused trying
5405 ;; to reload the value.
5406 (define_insn "isel_signed"
5407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5408 (if_then_else:SI
5409 (match_operator 1 "comparison_operator"
5410 [(match_operand:CC 4 "cc_reg_operand" "y")
5411 (const_int 0)])
5412 (match_operand:SI 2 "gpc_reg_operand" "b")
5413 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5414 "TARGET_ISEL"
5415 "*
5416 { return output_isel (operands); }"
5417 [(set_attr "length" "4")])
5419 (define_insn "isel_unsigned"
5420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5421 (if_then_else:SI
5422 (match_operator 1 "comparison_operator"
5423 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5424 (const_int 0)])
5425 (match_operand:SI 2 "gpc_reg_operand" "b")
5426 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5427 "TARGET_ISEL"
5428 "*
5429 { return output_isel (operands); }"
5430 [(set_attr "length" "4")])
5432 (define_expand "movsfcc"
5433 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5434 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5435 (match_operand:SF 2 "gpc_reg_operand" "")
5436 (match_operand:SF 3 "gpc_reg_operand" "")))]
5437 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5438 "
5439 {
5440 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5441 DONE;
5442 else
5443 FAIL;
5444 }")
5446 (define_insn "*fselsfsf4"
5447 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5448 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5449 (match_operand:SF 4 "zero_fp_constant" "F"))
5450 (match_operand:SF 2 "gpc_reg_operand" "f")
5451 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5452 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5453 "fsel %0,%1,%2,%3"
5454 [(set_attr "type" "fp")])
5456 (define_insn "*fseldfsf4"
5457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5458 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5459 (match_operand:DF 4 "zero_fp_constant" "F"))
5460 (match_operand:SF 2 "gpc_reg_operand" "f")
5461 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5462 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5463 "fsel %0,%1,%2,%3"
5464 [(set_attr "type" "fp")])
5466 (define_expand "negdf2"
5467 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5468 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5469 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5470 "")
5472 (define_insn "*negdf2_fpr"
5473 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5474 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5475 "TARGET_HARD_FLOAT && TARGET_FPRS"
5476 "fneg %0,%1"
5477 [(set_attr "type" "fp")])
5479 (define_expand "absdf2"
5480 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5481 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5482 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5483 "")
5485 (define_insn "*absdf2_fpr"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5487 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5488 "TARGET_HARD_FLOAT && TARGET_FPRS"
5489 "fabs %0,%1"
5490 [(set_attr "type" "fp")])
5492 (define_insn "*nabsdf2_fpr"
5493 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5494 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5495 "TARGET_HARD_FLOAT && TARGET_FPRS"
5496 "fnabs %0,%1"
5497 [(set_attr "type" "fp")])
5499 (define_expand "adddf3"
5500 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5501 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5502 (match_operand:DF 2 "gpc_reg_operand" "")))]
5503 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5504 "")
5506 (define_insn "*adddf3_fpr"
5507 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5508 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5509 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5510 "TARGET_HARD_FLOAT && TARGET_FPRS"
5511 "{fa|fadd} %0,%1,%2"
5512 [(set_attr "type" "fp")])
5514 (define_expand "subdf3"
5515 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5516 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5517 (match_operand:DF 2 "gpc_reg_operand" "")))]
5518 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5519 "")
5521 (define_insn "*subdf3_fpr"
5522 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5523 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5524 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5525 "TARGET_HARD_FLOAT && TARGET_FPRS"
5526 "{fs|fsub} %0,%1,%2"
5527 [(set_attr "type" "fp")])
5529 (define_expand "muldf3"
5530 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5531 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5532 (match_operand:DF 2 "gpc_reg_operand" "")))]
5533 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5534 "")
5536 (define_insn "*muldf3_fpr"
5537 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5538 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5539 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5540 "TARGET_HARD_FLOAT && TARGET_FPRS"
5541 "{fm|fmul} %0,%1,%2"
5542 [(set_attr "type" "dmul")])
5544 (define_insn "fred"
5545 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5546 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5547 "TARGET_POPCNTB && flag_finite_math_only"
5548 "fre %0,%1"
5549 [(set_attr "type" "fp")])
5551 (define_expand "divdf3"
5552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5553 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5554 (match_operand:DF 2 "gpc_reg_operand" "")))]
5555 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5556 {
5557 if (swdiv && !optimize_size && TARGET_POPCNTB
5558 && flag_finite_math_only && !flag_trapping_math)
5559 {
5560 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5561 DONE;
5562 }
5563 })
5565 (define_insn "*divdf3_fpr"
5566 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5567 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5568 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5569 "TARGET_HARD_FLOAT && TARGET_FPRS"
5570 "{fd|fdiv} %0,%1,%2"
5571 [(set_attr "type" "ddiv")])
5573 (define_insn ""
5574 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5575 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5576 (match_operand:DF 2 "gpc_reg_operand" "f"))
5577 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5579 "{fma|fmadd} %0,%1,%2,%3"
5580 [(set_attr "type" "dmul")])
5582 (define_insn ""
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5584 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5585 (match_operand:DF 2 "gpc_reg_operand" "f"))
5586 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5587 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5588 "{fms|fmsub} %0,%1,%2,%3"
5589 [(set_attr "type" "dmul")])
5591 (define_insn ""
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5593 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5594 (match_operand:DF 2 "gpc_reg_operand" "f"))
5595 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5596 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5597 && HONOR_SIGNED_ZEROS (DFmode)"
5598 "{fnma|fnmadd} %0,%1,%2,%3"
5599 [(set_attr "type" "dmul")])
5601 (define_insn ""
5602 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5603 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5604 (match_operand:DF 2 "gpc_reg_operand" "f"))
5605 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5606 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5607 && ! HONOR_SIGNED_ZEROS (DFmode)"
5608 "{fnma|fnmadd} %0,%1,%2,%3"
5609 [(set_attr "type" "dmul")])
5611 (define_insn ""
5612 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5613 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5614 (match_operand:DF 2 "gpc_reg_operand" "f"))
5615 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5617 && HONOR_SIGNED_ZEROS (DFmode)"
5618 "{fnms|fnmsub} %0,%1,%2,%3"
5619 [(set_attr "type" "dmul")])
5621 (define_insn ""
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5624 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5625 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5626 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5627 && ! HONOR_SIGNED_ZEROS (DFmode)"
5628 "{fnms|fnmsub} %0,%1,%2,%3"
5629 [(set_attr "type" "dmul")])
5631 (define_insn "sqrtdf2"
5632 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5633 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5634 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5635 "fsqrt %0,%1"
5636 [(set_attr "type" "dsqrt")])
5638 ;; The conditional move instructions allow us to perform max and min
5639 ;; operations even when
5641 (define_expand "smaxdf3"
5642 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5643 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5644 (match_operand:DF 2 "gpc_reg_operand" ""))
5645 (match_dup 1)
5646 (match_dup 2)))]
5647 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5648 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5650 (define_expand "smindf3"
5651 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5652 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5653 (match_operand:DF 2 "gpc_reg_operand" ""))
5654 (match_dup 2)
5655 (match_dup 1)))]
5656 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5657 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5659 (define_split
5660 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5661 (match_operator:DF 3 "min_max_operator"
5662 [(match_operand:DF 1 "gpc_reg_operand" "")
5663 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5664 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5665 [(const_int 0)]
5666 "
5667 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5668 operands[1], operands[2]);
5669 DONE;
5670 }")
5672 (define_expand "movdfcc"
5673 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5674 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5675 (match_operand:DF 2 "gpc_reg_operand" "")
5676 (match_operand:DF 3 "gpc_reg_operand" "")))]
5677 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5678 "
5679 {
5680 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5681 DONE;
5682 else
5683 FAIL;
5684 }")
5686 (define_insn "*fseldfdf4"
5687 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5688 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5689 (match_operand:DF 4 "zero_fp_constant" "F"))
5690 (match_operand:DF 2 "gpc_reg_operand" "f")
5691 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5692 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5693 "fsel %0,%1,%2,%3"
5694 [(set_attr "type" "fp")])
5696 (define_insn "*fselsfdf4"
5697 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5698 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5699 (match_operand:SF 4 "zero_fp_constant" "F"))
5700 (match_operand:DF 2 "gpc_reg_operand" "f")
5701 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5702 "TARGET_PPC_GFXOPT"
5703 "fsel %0,%1,%2,%3"
5704 [(set_attr "type" "fp")])
5705 \f
5706 ;; Conversions to and from floating-point.
5708 (define_expand "fixuns_truncsfsi2"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5710 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5711 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5712 "")
5714 (define_expand "fix_truncsfsi2"
5715 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5716 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5717 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5718 "")
5720 ; For each of these conversions, there is a define_expand, a define_insn
5721 ; with a '#' template, and a define_split (with C code). The idea is
5722 ; to allow constant folding with the template of the define_insn,
5723 ; then to have the insns split later (between sched1 and final).
5725 (define_expand "floatsidf2"
5726 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5727 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5728 (use (match_dup 2))
5729 (use (match_dup 3))
5730 (clobber (match_dup 4))
5731 (clobber (match_dup 5))
5732 (clobber (match_dup 6))])]
5733 "TARGET_HARD_FLOAT && TARGET_FPRS"
5734 "
5735 {
5736 if (TARGET_E500_DOUBLE)
5737 {
5738 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5739 DONE;
5740 }
5741 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5742 {
5743 rtx t1 = gen_reg_rtx (DImode);
5744 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5745 DONE;
5746 }
5747 if (TARGET_POWERPC64)
5748 {
5749 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5750 rtx t1 = gen_reg_rtx (DImode);
5751 rtx t2 = gen_reg_rtx (DImode);
5752 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5753 DONE;
5754 }
5756 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5757 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5758 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5759 operands[5] = gen_reg_rtx (DFmode);
5760 operands[6] = gen_reg_rtx (SImode);
5761 }")
5763 (define_insn_and_split "*floatsidf2_internal"
5764 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5765 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5766 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5767 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5768 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5769 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5770 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5771 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5772 "#"
5773 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5774 [(pc)]
5775 "
5776 {
5777 rtx lowword, highword;
5778 gcc_assert (MEM_P (operands[4]));
5779 highword = adjust_address (operands[4], SImode, 0);
5780 lowword = adjust_address (operands[4], SImode, 4);
5781 if (! WORDS_BIG_ENDIAN)
5782 {
5783 rtx tmp;
5784 tmp = highword; highword = lowword; lowword = tmp;
5785 }
5787 emit_insn (gen_xorsi3 (operands[6], operands[1],
5788 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5789 emit_move_insn (lowword, operands[6]);
5790 emit_move_insn (highword, operands[2]);
5791 emit_move_insn (operands[5], operands[4]);
5792 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5793 DONE;
5794 }"
5795 [(set_attr "length" "24")])
5797 (define_expand "floatunssisf2"
5798 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5799 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5800 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5801 "")
5803 (define_expand "floatunssidf2"
5804 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5805 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5806 (use (match_dup 2))
5807 (use (match_dup 3))
5808 (clobber (match_dup 4))
5809 (clobber (match_dup 5))])]
5810 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5811 "
5812 {
5813 if (TARGET_E500_DOUBLE)
5814 {
5815 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5816 DONE;
5817 }
5818 if (TARGET_POWERPC64)
5819 {
5820 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5821 rtx t1 = gen_reg_rtx (DImode);
5822 rtx t2 = gen_reg_rtx (DImode);
5823 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5824 t1, t2));
5825 DONE;
5826 }
5828 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5829 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5830 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5831 operands[5] = gen_reg_rtx (DFmode);
5832 }")
5834 (define_insn_and_split "*floatunssidf2_internal"
5835 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5836 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5837 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5838 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5839 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5840 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5841 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5842 "#"
5843 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5844 [(pc)]
5845 "
5846 {
5847 rtx lowword, highword;
5848 gcc_assert (MEM_P (operands[4]));
5849 highword = adjust_address (operands[4], SImode, 0);
5850 lowword = adjust_address (operands[4], SImode, 4);
5851 if (! WORDS_BIG_ENDIAN)
5852 {
5853 rtx tmp;
5854 tmp = highword; highword = lowword; lowword = tmp;
5855 }
5857 emit_move_insn (lowword, operands[1]);
5858 emit_move_insn (highword, operands[2]);
5859 emit_move_insn (operands[5], operands[4]);
5860 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5861 DONE;
5862 }"
5863 [(set_attr "length" "20")])
5865 (define_expand "fix_truncdfsi2"
5866 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5867 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5868 (clobber (match_dup 2))
5869 (clobber (match_dup 3))])]
5870 "(TARGET_POWER2 || TARGET_POWERPC)
5871 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5872 "
5873 {
5874 if (TARGET_E500_DOUBLE)
5875 {
5876 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5877 DONE;
5878 }
5879 operands[2] = gen_reg_rtx (DImode);
5880 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5881 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5882 {
5883 operands[3] = gen_reg_rtx (DImode);
5884 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5885 operands[2], operands[3]));
5886 DONE;
5887 }
5888 if (TARGET_PPC_GFXOPT)
5889 {
5890 rtx orig_dest = operands[0];
5891 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5892 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5893 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5894 operands[2]));
5895 if (operands[0] != orig_dest)
5896 emit_move_insn (orig_dest, operands[0]);
5897 DONE;
5898 }
5899 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5900 }")
5902 (define_insn_and_split "*fix_truncdfsi2_internal"
5903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5904 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5905 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5906 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5907 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5908 "#"
5909 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5910 [(pc)]
5911 "
5912 {
5913 rtx lowword;
5914 gcc_assert (MEM_P (operands[3]));
5915 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5917 emit_insn (gen_fctiwz (operands[2], operands[1]));
5918 emit_move_insn (operands[3], operands[2]);
5919 emit_move_insn (operands[0], lowword);
5920 DONE;
5921 }"
5922 [(set_attr "length" "16")])
5924 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5925 [(set (match_operand:SI 0 "memory_operand" "=Z")
5926 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5927 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5928 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5929 && TARGET_PPC_GFXOPT"
5930 "#"
5931 "&& 1"
5932 [(pc)]
5933 "
5934 {
5935 emit_insn (gen_fctiwz (operands[2], operands[1]));
5936 emit_insn (gen_stfiwx (operands[0], operands[2]));
5937 DONE;
5938 }"
5939 [(set_attr "length" "16")])
5941 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
5942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5943 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5944 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5945 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
5946 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
5947 "#"
5948 "&& 1"
5949 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
5950 (set (match_dup 3) (match_dup 2))
5951 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
5952 ""
5953 [(set_attr "length" "12")])
5955 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5956 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5957 ; because the first makes it clear that operand 0 is not live
5958 ; before the instruction.
5959 (define_insn "fctiwz"
5960 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5961 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5962 UNSPEC_FCTIWZ))]
5963 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5964 "{fcirz|fctiwz} %0,%1"
5965 [(set_attr "type" "fp")])
5967 (define_insn "btruncdf2"
5968 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5969 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5970 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5971 "friz %0,%1"
5972 [(set_attr "type" "fp")])
5974 (define_insn "btruncsf2"
5975 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5976 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5977 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5978 "friz %0,%1"
5979 [(set_attr "type" "fp")])
5981 (define_insn "ceildf2"
5982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5983 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5984 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5985 "frip %0,%1"
5986 [(set_attr "type" "fp")])
5988 (define_insn "ceilsf2"
5989 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5990 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5991 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5992 "frip %0,%1"
5993 [(set_attr "type" "fp")])
5995 (define_insn "floordf2"
5996 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5997 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5998 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "frim %0,%1"
6000 [(set_attr "type" "fp")])
6002 (define_insn "floorsf2"
6003 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6004 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6005 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6006 "frim %0,%1"
6007 [(set_attr "type" "fp")])
6009 (define_insn "rounddf2"
6010 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6011 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6012 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6013 "frin %0,%1"
6014 [(set_attr "type" "fp")])
6016 (define_insn "roundsf2"
6017 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6018 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6019 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6020 "frin %0,%1"
6021 [(set_attr "type" "fp")])
6023 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6024 (define_insn "stfiwx"
6025 [(set (match_operand:SI 0 "memory_operand" "=Z")
6026 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6027 UNSPEC_STFIWX))]
6028 "TARGET_PPC_GFXOPT"
6029 "stfiwx %1,%y0"
6030 [(set_attr "type" "fpstore")])
6032 (define_expand "floatsisf2"
6033 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6034 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6035 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6036 "")
6038 (define_insn "floatdidf2"
6039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6040 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6041 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6042 "fcfid %0,%1"
6043 [(set_attr "type" "fp")])
6045 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6046 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6047 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6048 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6049 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6050 "#"
6051 "&& 1"
6052 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6053 (set (match_dup 0) (float:DF (match_dup 2)))]
6054 "")
6056 (define_insn_and_split "floatsidf_ppc64"
6057 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6058 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6059 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6060 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6061 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6062 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6063 "#"
6064 "&& 1"
6065 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6066 (set (match_dup 2) (match_dup 3))
6067 (set (match_dup 4) (match_dup 2))
6068 (set (match_dup 0) (float:DF (match_dup 4)))]
6069 "")
6071 (define_insn_and_split "floatunssidf_ppc64"
6072 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6073 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6074 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6075 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6076 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6077 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6078 "#"
6079 "&& 1"
6080 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6081 (set (match_dup 2) (match_dup 3))
6082 (set (match_dup 4) (match_dup 2))
6083 (set (match_dup 0) (float:DF (match_dup 4)))]
6084 "")
6086 (define_insn "fix_truncdfdi2"
6087 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6088 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6089 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6090 "fctidz %0,%1"
6091 [(set_attr "type" "fp")])
6093 (define_expand "floatdisf2"
6094 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6095 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6096 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6097 "
6098 {
6099 rtx val = operands[1];
6100 if (!flag_unsafe_math_optimizations)
6101 {
6102 rtx label = gen_label_rtx ();
6103 val = gen_reg_rtx (DImode);
6104 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6105 emit_label (label);
6106 }
6107 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6108 DONE;
6109 }")
6111 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6112 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6113 ;; from double rounding.
6114 (define_insn_and_split "floatdisf2_internal1"
6115 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6116 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6117 (clobber (match_scratch:DF 2 "=f"))]
6118 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6119 "#"
6120 "&& reload_completed"
6121 [(set (match_dup 2)
6122 (float:DF (match_dup 1)))
6123 (set (match_dup 0)
6124 (float_truncate:SF (match_dup 2)))]
6125 "")
6127 ;; Twiddles bits to avoid double rounding.
6128 ;; Bits that might be truncated when converting to DFmode are replaced
6129 ;; by a bit that won't be lost at that stage, but is below the SFmode
6130 ;; rounding position.
6131 (define_expand "floatdisf2_internal2"
6132 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6133 (const_int 53)))
6134 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6135 (const_int 2047)))
6136 (clobber (scratch:CC))])
6137 (set (match_dup 3) (plus:DI (match_dup 3)
6138 (const_int 1)))
6139 (set (match_dup 0) (plus:DI (match_dup 0)
6140 (const_int 2047)))
6141 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6142 (const_int 2)))
6143 (set (match_dup 0) (ior:DI (match_dup 0)
6144 (match_dup 1)))
6145 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6146 (const_int -2048)))
6147 (clobber (scratch:CC))])
6148 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6149 (label_ref (match_operand:DI 2 "" ""))
6150 (pc)))
6151 (set (match_dup 0) (match_dup 1))]
6152 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6153 "
6154 {
6155 operands[3] = gen_reg_rtx (DImode);
6156 operands[4] = gen_reg_rtx (CCUNSmode);
6157 }")
6158 \f
6159 ;; Define the DImode operations that can be done in a small number
6160 ;; of instructions. The & constraints are to prevent the register
6161 ;; allocator from allocating registers that overlap with the inputs
6162 ;; (for example, having an input in 7,8 and an output in 6,7). We
6163 ;; also allow for the output being the same as one of the inputs.
6165 (define_insn "*adddi3_noppc64"
6166 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6167 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6168 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6169 "! TARGET_POWERPC64"
6170 "*
6171 {
6172 if (WORDS_BIG_ENDIAN)
6173 return (GET_CODE (operands[2])) != CONST_INT
6174 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6175 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6176 else
6177 return (GET_CODE (operands[2])) != CONST_INT
6178 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6179 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6180 }"
6181 [(set_attr "type" "two")
6182 (set_attr "length" "8")])
6184 (define_insn "*subdi3_noppc64"
6185 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6186 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6187 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6188 "! TARGET_POWERPC64"
6189 "*
6190 {
6191 if (WORDS_BIG_ENDIAN)
6192 return (GET_CODE (operands[1]) != CONST_INT)
6193 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6194 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6195 else
6196 return (GET_CODE (operands[1]) != CONST_INT)
6197 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6198 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6199 }"
6200 [(set_attr "type" "two")
6201 (set_attr "length" "8")])
6203 (define_insn "*negdi2_noppc64"
6204 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6205 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6206 "! TARGET_POWERPC64"
6207 "*
6208 {
6209 return (WORDS_BIG_ENDIAN)
6210 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6211 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6212 }"
6213 [(set_attr "type" "two")
6214 (set_attr "length" "8")])
6216 (define_expand "mulsidi3"
6217 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6218 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6219 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6220 "! TARGET_POWERPC64"
6221 "
6222 {
6223 if (! TARGET_POWER && ! TARGET_POWERPC)
6224 {
6225 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6226 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6227 emit_insn (gen_mull_call ());
6228 if (WORDS_BIG_ENDIAN)
6229 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6230 else
6231 {
6232 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6233 gen_rtx_REG (SImode, 3));
6234 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6235 gen_rtx_REG (SImode, 4));
6236 }
6237 DONE;
6238 }
6239 else if (TARGET_POWER)
6240 {
6241 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6242 DONE;
6243 }
6244 }")
6246 (define_insn "mulsidi3_mq"
6247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6248 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6249 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6250 (clobber (match_scratch:SI 3 "=q"))]
6251 "TARGET_POWER"
6252 "mul %0,%1,%2\;mfmq %L0"
6253 [(set_attr "type" "imul")
6254 (set_attr "length" "8")])
6256 (define_insn "*mulsidi3_no_mq"
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6258 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6259 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6260 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6261 "*
6262 {
6263 return (WORDS_BIG_ENDIAN)
6264 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6265 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6266 }"
6267 [(set_attr "type" "imul")
6268 (set_attr "length" "8")])
6270 (define_split
6271 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6272 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6273 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6274 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6275 [(set (match_dup 3)
6276 (truncate:SI
6277 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6278 (sign_extend:DI (match_dup 2)))
6279 (const_int 32))))
6280 (set (match_dup 4)
6281 (mult:SI (match_dup 1)
6282 (match_dup 2)))]
6283 "
6284 {
6285 int endian = (WORDS_BIG_ENDIAN == 0);
6286 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6287 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6288 }")
6290 (define_expand "umulsidi3"
6291 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6292 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6293 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6294 "TARGET_POWERPC && ! TARGET_POWERPC64"
6295 "
6296 {
6297 if (TARGET_POWER)
6298 {
6299 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6300 DONE;
6301 }
6302 }")
6304 (define_insn "umulsidi3_mq"
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6306 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6307 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6308 (clobber (match_scratch:SI 3 "=q"))]
6309 "TARGET_POWERPC && TARGET_POWER"
6310 "*
6311 {
6312 return (WORDS_BIG_ENDIAN)
6313 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6314 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6315 }"
6316 [(set_attr "type" "imul")
6317 (set_attr "length" "8")])
6319 (define_insn "*umulsidi3_no_mq"
6320 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6321 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6322 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6323 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6324 "*
6325 {
6326 return (WORDS_BIG_ENDIAN)
6327 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6328 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6329 }"
6330 [(set_attr "type" "imul")
6331 (set_attr "length" "8")])
6333 (define_split
6334 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6335 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6336 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6337 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6338 [(set (match_dup 3)
6339 (truncate:SI
6340 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6341 (zero_extend:DI (match_dup 2)))
6342 (const_int 32))))
6343 (set (match_dup 4)
6344 (mult:SI (match_dup 1)
6345 (match_dup 2)))]
6346 "
6347 {
6348 int endian = (WORDS_BIG_ENDIAN == 0);
6349 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6350 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6351 }")
6353 (define_expand "smulsi3_highpart"
6354 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6355 (truncate:SI
6356 (lshiftrt:DI (mult:DI (sign_extend:DI
6357 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6358 (sign_extend:DI
6359 (match_operand:SI 2 "gpc_reg_operand" "r")))
6360 (const_int 32))))]
6361 ""
6362 "
6363 {
6364 if (! TARGET_POWER && ! TARGET_POWERPC)
6365 {
6366 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6367 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6368 emit_insn (gen_mulh_call ());
6369 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6370 DONE;
6371 }
6372 else if (TARGET_POWER)
6373 {
6374 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6375 DONE;
6376 }
6377 }")
6379 (define_insn "smulsi3_highpart_mq"
6380 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6381 (truncate:SI
6382 (lshiftrt:DI (mult:DI (sign_extend:DI
6383 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6384 (sign_extend:DI
6385 (match_operand:SI 2 "gpc_reg_operand" "r")))
6386 (const_int 32))))
6387 (clobber (match_scratch:SI 3 "=q"))]
6388 "TARGET_POWER"
6389 "mul %0,%1,%2"
6390 [(set_attr "type" "imul")])
6392 (define_insn "*smulsi3_highpart_no_mq"
6393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6394 (truncate:SI
6395 (lshiftrt:DI (mult:DI (sign_extend:DI
6396 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6397 (sign_extend:DI
6398 (match_operand:SI 2 "gpc_reg_operand" "r")))
6399 (const_int 32))))]
6400 "TARGET_POWERPC && ! TARGET_POWER"
6401 "mulhw %0,%1,%2"
6402 [(set_attr "type" "imul")])
6404 (define_expand "umulsi3_highpart"
6405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6406 (truncate:SI
6407 (lshiftrt:DI (mult:DI (zero_extend:DI
6408 (match_operand:SI 1 "gpc_reg_operand" ""))
6409 (zero_extend:DI
6410 (match_operand:SI 2 "gpc_reg_operand" "")))
6411 (const_int 32))))]
6412 "TARGET_POWERPC"
6413 "
6414 {
6415 if (TARGET_POWER)
6416 {
6417 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6418 DONE;
6419 }
6420 }")
6422 (define_insn "umulsi3_highpart_mq"
6423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6424 (truncate:SI
6425 (lshiftrt:DI (mult:DI (zero_extend:DI
6426 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6427 (zero_extend:DI
6428 (match_operand:SI 2 "gpc_reg_operand" "r")))
6429 (const_int 32))))
6430 (clobber (match_scratch:SI 3 "=q"))]
6431 "TARGET_POWERPC && TARGET_POWER"
6432 "mulhwu %0,%1,%2"
6433 [(set_attr "type" "imul")])
6435 (define_insn "*umulsi3_highpart_no_mq"
6436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6437 (truncate:SI
6438 (lshiftrt:DI (mult:DI (zero_extend:DI
6439 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6440 (zero_extend:DI
6441 (match_operand:SI 2 "gpc_reg_operand" "r")))
6442 (const_int 32))))]
6443 "TARGET_POWERPC && ! TARGET_POWER"
6444 "mulhwu %0,%1,%2"
6445 [(set_attr "type" "imul")])
6447 ;; If operands 0 and 2 are in the same register, we have a problem. But
6448 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6449 ;; why we have the strange constraints below.
6450 (define_insn "ashldi3_power"
6451 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6452 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6453 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6454 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6455 "TARGET_POWER"
6456 "@
6457 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6458 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6459 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6460 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6461 [(set_attr "length" "8")])
6463 (define_insn "lshrdi3_power"
6464 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6465 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6466 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6467 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6468 "TARGET_POWER"
6469 "@
6470 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6471 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6472 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6473 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6474 [(set_attr "length" "8")])
6476 ;; Shift by a variable amount is too complex to be worth open-coding. We
6477 ;; just handle shifts by constants.
6478 (define_insn "ashrdi3_power"
6479 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6480 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6481 (match_operand:SI 2 "const_int_operand" "M,i")))
6482 (clobber (match_scratch:SI 3 "=X,q"))]
6483 "TARGET_POWER"
6484 "@
6485 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6486 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6487 [(set_attr "type" "shift")
6488 (set_attr "length" "8")])
6490 (define_insn "ashrdi3_no_power"
6491 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6492 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:SI 2 "const_int_operand" "M,i")))]
6494 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6495 "@
6496 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6497 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6498 [(set_attr "type" "two,three")
6499 (set_attr "length" "8,12")])
6501 (define_insn "*ashrdisi3_noppc64"
6502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6503 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6504 (const_int 32)) 4))]
6505 "TARGET_32BIT && !TARGET_POWERPC64"
6506 "*
6507 {
6508 if (REGNO (operands[0]) == REGNO (operands[1]))
6509 return \"\";
6510 else
6511 return \"mr %0,%1\";
6512 }"
6513 [(set_attr "length" "4")])
6515 \f
6516 ;; PowerPC64 DImode operations.
6518 (define_insn_and_split "absdi2"
6519 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6520 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6521 (clobber (match_scratch:DI 2 "=&r,&r"))]
6522 "TARGET_POWERPC64"
6523 "#"
6524 "&& reload_completed"
6525 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6526 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6527 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6528 "")
6530 (define_insn_and_split "*nabsdi2"
6531 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6532 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6533 (clobber (match_scratch:DI 2 "=&r,&r"))]
6534 "TARGET_POWERPC64"
6535 "#"
6536 "&& reload_completed"
6537 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6538 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6539 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6540 "")
6542 (define_insn "muldi3"
6543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6544 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6545 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6546 "TARGET_POWERPC64"
6547 "@
6548 mulld %0,%1,%2
6549 mulli %0,%1,%2"
6550 [(set (attr "type")
6551 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6552 (const_string "imul3")
6553 (match_operand:SI 2 "short_cint_operand" "")
6554 (const_string "imul2")]
6555 (const_string "lmul")))])
6557 (define_insn "*muldi3_internal1"
6558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6559 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6560 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6561 (const_int 0)))
6562 (clobber (match_scratch:DI 3 "=r,r"))]
6563 "TARGET_POWERPC64"
6564 "@
6565 mulld. %3,%1,%2
6566 #"
6567 [(set_attr "type" "lmul_compare")
6568 (set_attr "length" "4,8")])
6570 (define_split
6571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6572 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6573 (match_operand:DI 2 "gpc_reg_operand" ""))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 ""))]
6576 "TARGET_POWERPC64 && reload_completed"
6577 [(set (match_dup 3)
6578 (mult:DI (match_dup 1) (match_dup 2)))
6579 (set (match_dup 0)
6580 (compare:CC (match_dup 3)
6581 (const_int 0)))]
6582 "")
6584 (define_insn "*muldi3_internal2"
6585 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6586 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6588 (const_int 0)))
6589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6590 (mult:DI (match_dup 1) (match_dup 2)))]
6591 "TARGET_POWERPC64"
6592 "@
6593 mulld. %0,%1,%2
6594 #"
6595 [(set_attr "type" "lmul_compare")
6596 (set_attr "length" "4,8")])
6598 (define_split
6599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6600 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6601 (match_operand:DI 2 "gpc_reg_operand" ""))
6602 (const_int 0)))
6603 (set (match_operand:DI 0 "gpc_reg_operand" "")
6604 (mult:DI (match_dup 1) (match_dup 2)))]
6605 "TARGET_POWERPC64 && reload_completed"
6606 [(set (match_dup 0)
6607 (mult:DI (match_dup 1) (match_dup 2)))
6608 (set (match_dup 3)
6609 (compare:CC (match_dup 0)
6610 (const_int 0)))]
6611 "")
6613 (define_insn "smuldi3_highpart"
6614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6615 (truncate:DI
6616 (lshiftrt:TI (mult:TI (sign_extend:TI
6617 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6618 (sign_extend:TI
6619 (match_operand:DI 2 "gpc_reg_operand" "r")))
6620 (const_int 64))))]
6621 "TARGET_POWERPC64"
6622 "mulhd %0,%1,%2"
6623 [(set_attr "type" "lmul")])
6625 (define_insn "umuldi3_highpart"
6626 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6627 (truncate:DI
6628 (lshiftrt:TI (mult:TI (zero_extend:TI
6629 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6630 (zero_extend:TI
6631 (match_operand:DI 2 "gpc_reg_operand" "r")))
6632 (const_int 64))))]
6633 "TARGET_POWERPC64"
6634 "mulhdu %0,%1,%2"
6635 [(set_attr "type" "lmul")])
6637 (define_insn "rotldi3"
6638 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6639 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6640 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6641 "TARGET_POWERPC64"
6642 "@
6643 rldcl %0,%1,%2,0
6644 rldicl %0,%1,%H2,0"
6645 [(set_attr "type" "var_shift_rotate,integer")])
6647 (define_insn "*rotldi3_internal2"
6648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6649 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6650 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6651 (const_int 0)))
6652 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6653 "TARGET_64BIT"
6654 "@
6655 rldcl. %3,%1,%2,0
6656 rldicl. %3,%1,%H2,0
6657 #
6658 #"
6659 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6660 (set_attr "length" "4,4,8,8")])
6662 (define_split
6663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6664 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6665 (match_operand:DI 2 "reg_or_cint_operand" ""))
6666 (const_int 0)))
6667 (clobber (match_scratch:DI 3 ""))]
6668 "TARGET_POWERPC64 && reload_completed"
6669 [(set (match_dup 3)
6670 (rotate:DI (match_dup 1) (match_dup 2)))
6671 (set (match_dup 0)
6672 (compare:CC (match_dup 3)
6673 (const_int 0)))]
6674 "")
6676 (define_insn "*rotldi3_internal3"
6677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6678 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6679 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6680 (const_int 0)))
6681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6682 (rotate:DI (match_dup 1) (match_dup 2)))]
6683 "TARGET_64BIT"
6684 "@
6685 rldcl. %0,%1,%2,0
6686 rldicl. %0,%1,%H2,0
6687 #
6688 #"
6689 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6690 (set_attr "length" "4,4,8,8")])
6692 (define_split
6693 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6694 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6695 (match_operand:DI 2 "reg_or_cint_operand" ""))
6696 (const_int 0)))
6697 (set (match_operand:DI 0 "gpc_reg_operand" "")
6698 (rotate:DI (match_dup 1) (match_dup 2)))]
6699 "TARGET_POWERPC64 && reload_completed"
6700 [(set (match_dup 0)
6701 (rotate:DI (match_dup 1) (match_dup 2)))
6702 (set (match_dup 3)
6703 (compare:CC (match_dup 0)
6704 (const_int 0)))]
6705 "")
6707 (define_insn "*rotldi3_internal4"
6708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6709 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6710 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6711 (match_operand:DI 3 "mask64_operand" "n,n")))]
6712 "TARGET_POWERPC64"
6713 "@
6714 rldc%B3 %0,%1,%2,%S3
6715 rldic%B3 %0,%1,%H2,%S3"
6716 [(set_attr "type" "var_shift_rotate,integer")])
6718 (define_insn "*rotldi3_internal5"
6719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6720 (compare:CC (and:DI
6721 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6722 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6723 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6724 (const_int 0)))
6725 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6726 "TARGET_64BIT"
6727 "@
6728 rldc%B3. %4,%1,%2,%S3
6729 rldic%B3. %4,%1,%H2,%S3
6730 #
6731 #"
6732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6733 (set_attr "length" "4,4,8,8")])
6735 (define_split
6736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6737 (compare:CC (and:DI
6738 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6739 (match_operand:DI 2 "reg_or_cint_operand" ""))
6740 (match_operand:DI 3 "mask64_operand" ""))
6741 (const_int 0)))
6742 (clobber (match_scratch:DI 4 ""))]
6743 "TARGET_POWERPC64 && reload_completed"
6744 [(set (match_dup 4)
6745 (and:DI (rotate:DI (match_dup 1)
6746 (match_dup 2))
6747 (match_dup 3)))
6748 (set (match_dup 0)
6749 (compare:CC (match_dup 4)
6750 (const_int 0)))]
6751 "")
6753 (define_insn "*rotldi3_internal6"
6754 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6755 (compare:CC (and:DI
6756 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6757 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6758 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6759 (const_int 0)))
6760 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6761 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6762 "TARGET_64BIT"
6763 "@
6764 rldc%B3. %0,%1,%2,%S3
6765 rldic%B3. %0,%1,%H2,%S3
6766 #
6767 #"
6768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6769 (set_attr "length" "4,4,8,8")])
6771 (define_split
6772 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6773 (compare:CC (and:DI
6774 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6775 (match_operand:DI 2 "reg_or_cint_operand" ""))
6776 (match_operand:DI 3 "mask64_operand" ""))
6777 (const_int 0)))
6778 (set (match_operand:DI 0 "gpc_reg_operand" "")
6779 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6780 "TARGET_POWERPC64 && reload_completed"
6781 [(set (match_dup 0)
6782 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6783 (set (match_dup 4)
6784 (compare:CC (match_dup 0)
6785 (const_int 0)))]
6786 "")
6788 (define_insn "*rotldi3_internal7"
6789 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6790 (zero_extend:DI
6791 (subreg:QI
6792 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6793 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6794 "TARGET_POWERPC64"
6795 "@
6796 rldcl %0,%1,%2,56
6797 rldicl %0,%1,%H2,56"
6798 [(set_attr "type" "var_shift_rotate,integer")])
6800 (define_insn "*rotldi3_internal8"
6801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6802 (compare:CC (zero_extend:DI
6803 (subreg:QI
6804 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6805 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6808 "TARGET_64BIT"
6809 "@
6810 rldcl. %3,%1,%2,56
6811 rldicl. %3,%1,%H2,56
6812 #
6813 #"
6814 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6815 (set_attr "length" "4,4,8,8")])
6817 (define_split
6818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6819 (compare:CC (zero_extend:DI
6820 (subreg:QI
6821 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6822 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6823 (const_int 0)))
6824 (clobber (match_scratch:DI 3 ""))]
6825 "TARGET_POWERPC64 && reload_completed"
6826 [(set (match_dup 3)
6827 (zero_extend:DI (subreg:QI
6828 (rotate:DI (match_dup 1)
6829 (match_dup 2)) 0)))
6830 (set (match_dup 0)
6831 (compare:CC (match_dup 3)
6832 (const_int 0)))]
6833 "")
6835 (define_insn "*rotldi3_internal9"
6836 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6837 (compare:CC (zero_extend:DI
6838 (subreg:QI
6839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6840 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6841 (const_int 0)))
6842 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6843 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6844 "TARGET_64BIT"
6845 "@
6846 rldcl. %0,%1,%2,56
6847 rldicl. %0,%1,%H2,56
6848 #
6849 #"
6850 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6851 (set_attr "length" "4,4,8,8")])
6853 (define_split
6854 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6855 (compare:CC (zero_extend:DI
6856 (subreg:QI
6857 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6858 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6859 (const_int 0)))
6860 (set (match_operand:DI 0 "gpc_reg_operand" "")
6861 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6862 "TARGET_POWERPC64 && reload_completed"
6863 [(set (match_dup 0)
6864 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6865 (set (match_dup 3)
6866 (compare:CC (match_dup 0)
6867 (const_int 0)))]
6868 "")
6870 (define_insn "*rotldi3_internal10"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6872 (zero_extend:DI
6873 (subreg:HI
6874 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6876 "TARGET_POWERPC64"
6877 "@
6878 rldcl %0,%1,%2,48
6879 rldicl %0,%1,%H2,48"
6880 [(set_attr "type" "var_shift_rotate,integer")])
6882 (define_insn "*rotldi3_internal11"
6883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6884 (compare:CC (zero_extend:DI
6885 (subreg:HI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6887 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6890 "TARGET_64BIT"
6891 "@
6892 rldcl. %3,%1,%2,48
6893 rldicl. %3,%1,%H2,48
6894 #
6895 #"
6896 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6897 (set_attr "length" "4,4,8,8")])
6899 (define_split
6900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6901 (compare:CC (zero_extend:DI
6902 (subreg:HI
6903 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6904 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6905 (const_int 0)))
6906 (clobber (match_scratch:DI 3 ""))]
6907 "TARGET_POWERPC64 && reload_completed"
6908 [(set (match_dup 3)
6909 (zero_extend:DI (subreg:HI
6910 (rotate:DI (match_dup 1)
6911 (match_dup 2)) 0)))
6912 (set (match_dup 0)
6913 (compare:CC (match_dup 3)
6914 (const_int 0)))]
6915 "")
6917 (define_insn "*rotldi3_internal12"
6918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6919 (compare:CC (zero_extend:DI
6920 (subreg:HI
6921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6922 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6923 (const_int 0)))
6924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6925 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6926 "TARGET_64BIT"
6927 "@
6928 rldcl. %0,%1,%2,48
6929 rldicl. %0,%1,%H2,48
6930 #
6931 #"
6932 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6933 (set_attr "length" "4,4,8,8")])
6935 (define_split
6936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6937 (compare:CC (zero_extend:DI
6938 (subreg:HI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6941 (const_int 0)))
6942 (set (match_operand:DI 0 "gpc_reg_operand" "")
6943 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6944 "TARGET_POWERPC64 && reload_completed"
6945 [(set (match_dup 0)
6946 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6947 (set (match_dup 3)
6948 (compare:CC (match_dup 0)
6949 (const_int 0)))]
6950 "")
6952 (define_insn "*rotldi3_internal13"
6953 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6954 (zero_extend:DI
6955 (subreg:SI
6956 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6957 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6958 "TARGET_POWERPC64"
6959 "@
6960 rldcl %0,%1,%2,32
6961 rldicl %0,%1,%H2,32"
6962 [(set_attr "type" "var_shift_rotate,integer")])
6964 (define_insn "*rotldi3_internal14"
6965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6966 (compare:CC (zero_extend:DI
6967 (subreg:SI
6968 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6969 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6970 (const_int 0)))
6971 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6972 "TARGET_64BIT"
6973 "@
6974 rldcl. %3,%1,%2,32
6975 rldicl. %3,%1,%H2,32
6976 #
6977 #"
6978 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6979 (set_attr "length" "4,4,8,8")])
6981 (define_split
6982 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6983 (compare:CC (zero_extend:DI
6984 (subreg:SI
6985 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6987 (const_int 0)))
6988 (clobber (match_scratch:DI 3 ""))]
6989 "TARGET_POWERPC64 && reload_completed"
6990 [(set (match_dup 3)
6991 (zero_extend:DI (subreg:SI
6992 (rotate:DI (match_dup 1)
6993 (match_dup 2)) 0)))
6994 (set (match_dup 0)
6995 (compare:CC (match_dup 3)
6996 (const_int 0)))]
6997 "")
6999 (define_insn "*rotldi3_internal15"
7000 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7001 (compare:CC (zero_extend:DI
7002 (subreg:SI
7003 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7004 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7005 (const_int 0)))
7006 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7007 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7008 "TARGET_64BIT"
7009 "@
7010 rldcl. %0,%1,%2,32
7011 rldicl. %0,%1,%H2,32
7012 #
7013 #"
7014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7015 (set_attr "length" "4,4,8,8")])
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7019 (compare:CC (zero_extend:DI
7020 (subreg:SI
7021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7022 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7023 (const_int 0)))
7024 (set (match_operand:DI 0 "gpc_reg_operand" "")
7025 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7026 "TARGET_POWERPC64 && reload_completed"
7027 [(set (match_dup 0)
7028 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7029 (set (match_dup 3)
7030 (compare:CC (match_dup 0)
7031 (const_int 0)))]
7032 "")
7034 (define_expand "ashldi3"
7035 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7036 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7037 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7038 "TARGET_POWERPC64 || TARGET_POWER"
7039 "
7040 {
7041 if (TARGET_POWERPC64)
7042 ;
7043 else if (TARGET_POWER)
7044 {
7045 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7046 DONE;
7047 }
7048 else
7049 FAIL;
7050 }")
7052 (define_insn "*ashldi3_internal1"
7053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7054 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7055 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7056 "TARGET_POWERPC64"
7057 "@
7058 sld %0,%1,%2
7059 sldi %0,%1,%H2"
7060 [(set_attr "type" "var_shift_rotate,shift")])
7062 (define_insn "*ashldi3_internal2"
7063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7064 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7065 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7066 (const_int 0)))
7067 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7068 "TARGET_64BIT"
7069 "@
7070 sld. %3,%1,%2
7071 sldi. %3,%1,%H2
7072 #
7073 #"
7074 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7075 (set_attr "length" "4,4,8,8")])
7077 (define_split
7078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7079 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7080 (match_operand:SI 2 "reg_or_cint_operand" ""))
7081 (const_int 0)))
7082 (clobber (match_scratch:DI 3 ""))]
7083 "TARGET_POWERPC64 && reload_completed"
7084 [(set (match_dup 3)
7085 (ashift:DI (match_dup 1) (match_dup 2)))
7086 (set (match_dup 0)
7087 (compare:CC (match_dup 3)
7088 (const_int 0)))]
7089 "")
7091 (define_insn "*ashldi3_internal3"
7092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7093 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7094 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7095 (const_int 0)))
7096 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7097 (ashift:DI (match_dup 1) (match_dup 2)))]
7098 "TARGET_64BIT"
7099 "@
7100 sld. %0,%1,%2
7101 sldi. %0,%1,%H2
7102 #
7103 #"
7104 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7105 (set_attr "length" "4,4,8,8")])
7107 (define_split
7108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7109 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:SI 2 "reg_or_cint_operand" ""))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (ashift:DI (match_dup 1) (match_dup 2)))]
7114 "TARGET_POWERPC64 && reload_completed"
7115 [(set (match_dup 0)
7116 (ashift:DI (match_dup 1) (match_dup 2)))
7117 (set (match_dup 3)
7118 (compare:CC (match_dup 0)
7119 (const_int 0)))]
7120 "")
7122 (define_insn "*ashldi3_internal4"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7124 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7125 (match_operand:SI 2 "const_int_operand" "i"))
7126 (match_operand:DI 3 "const_int_operand" "n")))]
7127 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7128 "rldic %0,%1,%H2,%W3")
7130 (define_insn "ashldi3_internal5"
7131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7132 (compare:CC
7133 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7134 (match_operand:SI 2 "const_int_operand" "i,i"))
7135 (match_operand:DI 3 "const_int_operand" "n,n"))
7136 (const_int 0)))
7137 (clobber (match_scratch:DI 4 "=r,r"))]
7138 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7139 "@
7140 rldic. %4,%1,%H2,%W3
7141 #"
7142 [(set_attr "type" "compare")
7143 (set_attr "length" "4,8")])
7145 (define_split
7146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7147 (compare:CC
7148 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7149 (match_operand:SI 2 "const_int_operand" ""))
7150 (match_operand:DI 3 "const_int_operand" ""))
7151 (const_int 0)))
7152 (clobber (match_scratch:DI 4 ""))]
7153 "TARGET_POWERPC64 && reload_completed
7154 && includes_rldic_lshift_p (operands[2], operands[3])"
7155 [(set (match_dup 4)
7156 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7157 (match_dup 3)))
7158 (set (match_dup 0)
7159 (compare:CC (match_dup 4)
7160 (const_int 0)))]
7161 "")
7163 (define_insn "*ashldi3_internal6"
7164 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7165 (compare:CC
7166 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7167 (match_operand:SI 2 "const_int_operand" "i,i"))
7168 (match_operand:DI 3 "const_int_operand" "n,n"))
7169 (const_int 0)))
7170 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7171 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7172 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7173 "@
7174 rldic. %0,%1,%H2,%W3
7175 #"
7176 [(set_attr "type" "compare")
7177 (set_attr "length" "4,8")])
7179 (define_split
7180 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7181 (compare:CC
7182 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7183 (match_operand:SI 2 "const_int_operand" ""))
7184 (match_operand:DI 3 "const_int_operand" ""))
7185 (const_int 0)))
7186 (set (match_operand:DI 0 "gpc_reg_operand" "")
7187 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7188 "TARGET_POWERPC64 && reload_completed
7189 && includes_rldic_lshift_p (operands[2], operands[3])"
7190 [(set (match_dup 0)
7191 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7192 (match_dup 3)))
7193 (set (match_dup 4)
7194 (compare:CC (match_dup 0)
7195 (const_int 0)))]
7196 "")
7198 (define_insn "*ashldi3_internal7"
7199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7200 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7201 (match_operand:SI 2 "const_int_operand" "i"))
7202 (match_operand:DI 3 "mask64_operand" "n")))]
7203 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7204 "rldicr %0,%1,%H2,%S3")
7206 (define_insn "ashldi3_internal8"
7207 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7208 (compare:CC
7209 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7210 (match_operand:SI 2 "const_int_operand" "i,i"))
7211 (match_operand:DI 3 "mask64_operand" "n,n"))
7212 (const_int 0)))
7213 (clobber (match_scratch:DI 4 "=r,r"))]
7214 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7215 "@
7216 rldicr. %4,%1,%H2,%S3
7217 #"
7218 [(set_attr "type" "compare")
7219 (set_attr "length" "4,8")])
7221 (define_split
7222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7223 (compare:CC
7224 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7225 (match_operand:SI 2 "const_int_operand" ""))
7226 (match_operand:DI 3 "mask64_operand" ""))
7227 (const_int 0)))
7228 (clobber (match_scratch:DI 4 ""))]
7229 "TARGET_POWERPC64 && reload_completed
7230 && includes_rldicr_lshift_p (operands[2], operands[3])"
7231 [(set (match_dup 4)
7232 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7233 (match_dup 3)))
7234 (set (match_dup 0)
7235 (compare:CC (match_dup 4)
7236 (const_int 0)))]
7237 "")
7239 (define_insn "*ashldi3_internal9"
7240 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7241 (compare:CC
7242 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7243 (match_operand:SI 2 "const_int_operand" "i,i"))
7244 (match_operand:DI 3 "mask64_operand" "n,n"))
7245 (const_int 0)))
7246 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7247 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7248 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7249 "@
7250 rldicr. %0,%1,%H2,%S3
7251 #"
7252 [(set_attr "type" "compare")
7253 (set_attr "length" "4,8")])
7255 (define_split
7256 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7257 (compare:CC
7258 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7259 (match_operand:SI 2 "const_int_operand" ""))
7260 (match_operand:DI 3 "mask64_operand" ""))
7261 (const_int 0)))
7262 (set (match_operand:DI 0 "gpc_reg_operand" "")
7263 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7264 "TARGET_POWERPC64 && reload_completed
7265 && includes_rldicr_lshift_p (operands[2], operands[3])"
7266 [(set (match_dup 0)
7267 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7268 (match_dup 3)))
7269 (set (match_dup 4)
7270 (compare:CC (match_dup 0)
7271 (const_int 0)))]
7272 "")
7274 (define_expand "lshrdi3"
7275 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7276 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7277 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7278 "TARGET_POWERPC64 || TARGET_POWER"
7279 "
7280 {
7281 if (TARGET_POWERPC64)
7282 ;
7283 else if (TARGET_POWER)
7284 {
7285 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7286 DONE;
7287 }
7288 else
7289 FAIL;
7290 }")
7292 (define_insn "*lshrdi3_internal1"
7293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7294 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7295 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7296 "TARGET_POWERPC64"
7297 "@
7298 srd %0,%1,%2
7299 srdi %0,%1,%H2"
7300 [(set_attr "type" "var_shift_rotate,shift")])
7302 (define_insn "*lshrdi3_internal2"
7303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7304 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7305 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7306 (const_int 0)))
7307 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7308 "TARGET_64BIT "
7309 "@
7310 srd. %3,%1,%2
7311 srdi. %3,%1,%H2
7312 #
7313 #"
7314 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7315 (set_attr "length" "4,4,8,8")])
7317 (define_split
7318 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7319 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7320 (match_operand:SI 2 "reg_or_cint_operand" ""))
7321 (const_int 0)))
7322 (clobber (match_scratch:DI 3 ""))]
7323 "TARGET_POWERPC64 && reload_completed"
7324 [(set (match_dup 3)
7325 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7326 (set (match_dup 0)
7327 (compare:CC (match_dup 3)
7328 (const_int 0)))]
7329 "")
7331 (define_insn "*lshrdi3_internal3"
7332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7333 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7334 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7335 (const_int 0)))
7336 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7337 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7338 "TARGET_64BIT"
7339 "@
7340 srd. %0,%1,%2
7341 srdi. %0,%1,%H2
7342 #
7343 #"
7344 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7345 (set_attr "length" "4,4,8,8")])
7347 (define_split
7348 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7349 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7350 (match_operand:SI 2 "reg_or_cint_operand" ""))
7351 (const_int 0)))
7352 (set (match_operand:DI 0 "gpc_reg_operand" "")
7353 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7354 "TARGET_POWERPC64 && reload_completed"
7355 [(set (match_dup 0)
7356 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7357 (set (match_dup 3)
7358 (compare:CC (match_dup 0)
7359 (const_int 0)))]
7360 "")
7362 (define_expand "ashrdi3"
7363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7364 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7365 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7366 "WORDS_BIG_ENDIAN"
7367 "
7368 {
7369 if (TARGET_POWERPC64)
7370 ;
7371 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7372 {
7373 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7374 DONE;
7375 }
7376 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7377 && WORDS_BIG_ENDIAN)
7378 {
7379 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7380 DONE;
7381 }
7382 else
7383 FAIL;
7384 }")
7386 (define_insn "*ashrdi3_internal1"
7387 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7388 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7389 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7390 "TARGET_POWERPC64"
7391 "@
7392 srad %0,%1,%2
7393 sradi %0,%1,%H2"
7394 [(set_attr "type" "var_shift_rotate,shift")])
7396 (define_insn "*ashrdi3_internal2"
7397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7398 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7399 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7400 (const_int 0)))
7401 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7402 "TARGET_64BIT"
7403 "@
7404 srad. %3,%1,%2
7405 sradi. %3,%1,%H2
7406 #
7407 #"
7408 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7409 (set_attr "length" "4,4,8,8")])
7411 (define_split
7412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7413 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7414 (match_operand:SI 2 "reg_or_cint_operand" ""))
7415 (const_int 0)))
7416 (clobber (match_scratch:DI 3 ""))]
7417 "TARGET_POWERPC64 && reload_completed"
7418 [(set (match_dup 3)
7419 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7420 (set (match_dup 0)
7421 (compare:CC (match_dup 3)
7422 (const_int 0)))]
7423 "")
7425 (define_insn "*ashrdi3_internal3"
7426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7427 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7428 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7429 (const_int 0)))
7430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7431 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7432 "TARGET_64BIT"
7433 "@
7434 srad. %0,%1,%2
7435 sradi. %0,%1,%H2
7436 #
7437 #"
7438 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7439 (set_attr "length" "4,4,8,8")])
7441 (define_split
7442 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7443 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7444 (match_operand:SI 2 "reg_or_cint_operand" ""))
7445 (const_int 0)))
7446 (set (match_operand:DI 0 "gpc_reg_operand" "")
7447 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7448 "TARGET_POWERPC64 && reload_completed"
7449 [(set (match_dup 0)
7450 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7451 (set (match_dup 3)
7452 (compare:CC (match_dup 0)
7453 (const_int 0)))]
7454 "")
7456 (define_insn "anddi3"
7457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7458 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7459 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7460 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7461 "TARGET_POWERPC64"
7462 "@
7463 and %0,%1,%2
7464 rldic%B2 %0,%1,0,%S2
7465 rlwinm %0,%1,0,%m2,%M2
7466 andi. %0,%1,%b2
7467 andis. %0,%1,%u2
7468 #"
7469 [(set_attr "type" "*,*,*,compare,compare,*")
7470 (set_attr "length" "4,4,4,4,4,8")])
7472 (define_split
7473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7474 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7475 (match_operand:DI 2 "mask64_2_operand" "")))
7476 (clobber (match_scratch:CC 3 ""))]
7477 "TARGET_POWERPC64
7478 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7479 && !mask_operand (operands[2], DImode)
7480 && !mask64_operand (operands[2], DImode)"
7481 [(set (match_dup 0)
7482 (and:DI (rotate:DI (match_dup 1)
7483 (match_dup 4))
7484 (match_dup 5)))
7485 (set (match_dup 0)
7486 (and:DI (rotate:DI (match_dup 0)
7487 (match_dup 6))
7488 (match_dup 7)))]
7489 {
7490 build_mask64_2_operands (operands[2], &operands[4]);
7491 })
7493 (define_insn "*anddi3_internal2"
7494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7495 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7496 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7497 (const_int 0)))
7498 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7499 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7500 "TARGET_64BIT"
7501 "@
7502 and. %3,%1,%2
7503 rldic%B2. %3,%1,0,%S2
7504 rlwinm. %3,%1,0,%m2,%M2
7505 andi. %3,%1,%b2
7506 andis. %3,%1,%u2
7507 #
7508 #
7509 #
7510 #
7511 #
7512 #
7513 #"
7514 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7515 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7517 (define_split
7518 [(set (match_operand:CC 0 "cc_reg_operand" "")
7519 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7520 (match_operand:DI 2 "mask64_2_operand" ""))
7521 (const_int 0)))
7522 (clobber (match_scratch:DI 3 ""))
7523 (clobber (match_scratch:CC 4 ""))]
7524 "TARGET_64BIT && reload_completed
7525 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7526 && !mask_operand (operands[2], DImode)
7527 && !mask64_operand (operands[2], DImode)"
7528 [(set (match_dup 3)
7529 (and:DI (rotate:DI (match_dup 1)
7530 (match_dup 5))
7531 (match_dup 6)))
7532 (parallel [(set (match_dup 0)
7533 (compare:CC (and:DI (rotate:DI (match_dup 3)
7534 (match_dup 7))
7535 (match_dup 8))
7536 (const_int 0)))
7537 (clobber (match_dup 3))])]
7538 "
7539 {
7540 build_mask64_2_operands (operands[2], &operands[5]);
7541 }")
7543 (define_insn "*anddi3_internal3"
7544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7545 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7546 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7547 (const_int 0)))
7548 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7549 (and:DI (match_dup 1) (match_dup 2)))
7550 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7551 "TARGET_64BIT"
7552 "@
7553 and. %0,%1,%2
7554 rldic%B2. %0,%1,0,%S2
7555 rlwinm. %0,%1,0,%m2,%M2
7556 andi. %0,%1,%b2
7557 andis. %0,%1,%u2
7558 #
7559 #
7560 #
7561 #
7562 #
7563 #
7564 #"
7565 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7566 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7568 (define_split
7569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7570 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7571 (match_operand:DI 2 "and64_2_operand" ""))
7572 (const_int 0)))
7573 (set (match_operand:DI 0 "gpc_reg_operand" "")
7574 (and:DI (match_dup 1) (match_dup 2)))
7575 (clobber (match_scratch:CC 4 ""))]
7576 "TARGET_64BIT && reload_completed"
7577 [(parallel [(set (match_dup 0)
7578 (and:DI (match_dup 1) (match_dup 2)))
7579 (clobber (match_dup 4))])
7580 (set (match_dup 3)
7581 (compare:CC (match_dup 0)
7582 (const_int 0)))]
7583 "")
7585 (define_split
7586 [(set (match_operand:CC 3 "cc_reg_operand" "")
7587 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7588 (match_operand:DI 2 "mask64_2_operand" ""))
7589 (const_int 0)))
7590 (set (match_operand:DI 0 "gpc_reg_operand" "")
7591 (and:DI (match_dup 1) (match_dup 2)))
7592 (clobber (match_scratch:CC 4 ""))]
7593 "TARGET_64BIT && reload_completed
7594 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7595 && !mask_operand (operands[2], DImode)
7596 && !mask64_operand (operands[2], DImode)"
7597 [(set (match_dup 0)
7598 (and:DI (rotate:DI (match_dup 1)
7599 (match_dup 5))
7600 (match_dup 6)))
7601 (parallel [(set (match_dup 3)
7602 (compare:CC (and:DI (rotate:DI (match_dup 0)
7603 (match_dup 7))
7604 (match_dup 8))
7605 (const_int 0)))
7606 (set (match_dup 0)
7607 (and:DI (rotate:DI (match_dup 0)
7608 (match_dup 7))
7609 (match_dup 8)))])]
7610 "
7611 {
7612 build_mask64_2_operands (operands[2], &operands[5]);
7613 }")
7615 (define_expand "iordi3"
7616 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7617 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7618 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7619 "TARGET_POWERPC64"
7620 "
7621 {
7622 if (non_logical_cint_operand (operands[2], DImode))
7623 {
7624 HOST_WIDE_INT value;
7625 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7626 ? operands[0] : gen_reg_rtx (DImode));
7628 if (GET_CODE (operands[2]) == CONST_INT)
7629 {
7630 value = INTVAL (operands[2]);
7631 emit_insn (gen_iordi3 (tmp, operands[1],
7632 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7633 }
7634 else
7635 {
7636 value = CONST_DOUBLE_LOW (operands[2]);
7637 emit_insn (gen_iordi3 (tmp, operands[1],
7638 immed_double_const (value
7639 & (~ (HOST_WIDE_INT) 0xffff),
7640 0, DImode)));
7641 }
7643 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7644 DONE;
7645 }
7646 }")
7648 (define_expand "xordi3"
7649 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7650 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7651 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7652 "TARGET_POWERPC64"
7653 "
7654 {
7655 if (non_logical_cint_operand (operands[2], DImode))
7656 {
7657 HOST_WIDE_INT value;
7658 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7659 ? operands[0] : gen_reg_rtx (DImode));
7661 if (GET_CODE (operands[2]) == CONST_INT)
7662 {
7663 value = INTVAL (operands[2]);
7664 emit_insn (gen_xordi3 (tmp, operands[1],
7665 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7666 }
7667 else
7668 {
7669 value = CONST_DOUBLE_LOW (operands[2]);
7670 emit_insn (gen_xordi3 (tmp, operands[1],
7671 immed_double_const (value
7672 & (~ (HOST_WIDE_INT) 0xffff),
7673 0, DImode)));
7674 }
7676 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7677 DONE;
7678 }
7679 }")
7681 (define_insn "*booldi3_internal1"
7682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7683 (match_operator:DI 3 "boolean_or_operator"
7684 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7685 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7686 "TARGET_POWERPC64"
7687 "@
7688 %q3 %0,%1,%2
7689 %q3i %0,%1,%b2
7690 %q3is %0,%1,%u2")
7692 (define_insn "*booldi3_internal2"
7693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7694 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7695 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7696 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7697 (const_int 0)))
7698 (clobber (match_scratch:DI 3 "=r,r"))]
7699 "TARGET_64BIT"
7700 "@
7701 %q4. %3,%1,%2
7702 #"
7703 [(set_attr "type" "compare")
7704 (set_attr "length" "4,8")])
7706 (define_split
7707 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7708 (compare:CC (match_operator:DI 4 "boolean_operator"
7709 [(match_operand:DI 1 "gpc_reg_operand" "")
7710 (match_operand:DI 2 "gpc_reg_operand" "")])
7711 (const_int 0)))
7712 (clobber (match_scratch:DI 3 ""))]
7713 "TARGET_POWERPC64 && reload_completed"
7714 [(set (match_dup 3) (match_dup 4))
7715 (set (match_dup 0)
7716 (compare:CC (match_dup 3)
7717 (const_int 0)))]
7718 "")
7720 (define_insn "*booldi3_internal3"
7721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7722 (compare:CC (match_operator:DI 4 "boolean_operator"
7723 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7724 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7725 (const_int 0)))
7726 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7727 (match_dup 4))]
7728 "TARGET_64BIT"
7729 "@
7730 %q4. %0,%1,%2
7731 #"
7732 [(set_attr "type" "compare")
7733 (set_attr "length" "4,8")])
7735 (define_split
7736 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7737 (compare:CC (match_operator:DI 4 "boolean_operator"
7738 [(match_operand:DI 1 "gpc_reg_operand" "")
7739 (match_operand:DI 2 "gpc_reg_operand" "")])
7740 (const_int 0)))
7741 (set (match_operand:DI 0 "gpc_reg_operand" "")
7742 (match_dup 4))]
7743 "TARGET_POWERPC64 && reload_completed"
7744 [(set (match_dup 0) (match_dup 4))
7745 (set (match_dup 3)
7746 (compare:CC (match_dup 0)
7747 (const_int 0)))]
7748 "")
7750 ;; Split a logical operation that we can't do in one insn into two insns,
7751 ;; each of which does one 16-bit part. This is used by combine.
7753 (define_split
7754 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7755 (match_operator:DI 3 "boolean_or_operator"
7756 [(match_operand:DI 1 "gpc_reg_operand" "")
7757 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7758 "TARGET_POWERPC64"
7759 [(set (match_dup 0) (match_dup 4))
7760 (set (match_dup 0) (match_dup 5))]
7761 "
7762 {
7763 rtx i3,i4;
7765 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7766 {
7767 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7768 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7769 0, DImode);
7770 i4 = GEN_INT (value & 0xffff);
7771 }
7772 else
7773 {
7774 i3 = GEN_INT (INTVAL (operands[2])
7775 & (~ (HOST_WIDE_INT) 0xffff));
7776 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7777 }
7778 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7779 operands[1], i3);
7780 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7781 operands[0], i4);
7782 }")
7784 (define_insn "*boolcdi3_internal1"
7785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7786 (match_operator:DI 3 "boolean_operator"
7787 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7788 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7789 "TARGET_POWERPC64"
7790 "%q3 %0,%2,%1")
7792 (define_insn "*boolcdi3_internal2"
7793 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7794 (compare:CC (match_operator:DI 4 "boolean_operator"
7795 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7796 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7797 (const_int 0)))
7798 (clobber (match_scratch:DI 3 "=r,r"))]
7799 "TARGET_64BIT"
7800 "@
7801 %q4. %3,%2,%1
7802 #"
7803 [(set_attr "type" "compare")
7804 (set_attr "length" "4,8")])
7806 (define_split
7807 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7808 (compare:CC (match_operator:DI 4 "boolean_operator"
7809 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7810 (match_operand:DI 2 "gpc_reg_operand" "")])
7811 (const_int 0)))
7812 (clobber (match_scratch:DI 3 ""))]
7813 "TARGET_POWERPC64 && reload_completed"
7814 [(set (match_dup 3) (match_dup 4))
7815 (set (match_dup 0)
7816 (compare:CC (match_dup 3)
7817 (const_int 0)))]
7818 "")
7820 (define_insn "*boolcdi3_internal3"
7821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7822 (compare:CC (match_operator:DI 4 "boolean_operator"
7823 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7824 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7825 (const_int 0)))
7826 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7827 (match_dup 4))]
7828 "TARGET_64BIT"
7829 "@
7830 %q4. %0,%2,%1
7831 #"
7832 [(set_attr "type" "compare")
7833 (set_attr "length" "4,8")])
7835 (define_split
7836 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7837 (compare:CC (match_operator:DI 4 "boolean_operator"
7838 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7839 (match_operand:DI 2 "gpc_reg_operand" "")])
7840 (const_int 0)))
7841 (set (match_operand:DI 0 "gpc_reg_operand" "")
7842 (match_dup 4))]
7843 "TARGET_POWERPC64 && reload_completed"
7844 [(set (match_dup 0) (match_dup 4))
7845 (set (match_dup 3)
7846 (compare:CC (match_dup 0)
7847 (const_int 0)))]
7848 "")
7850 (define_insn "*boolccdi3_internal1"
7851 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7852 (match_operator:DI 3 "boolean_operator"
7853 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7854 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7855 "TARGET_POWERPC64"
7856 "%q3 %0,%1,%2")
7858 (define_insn "*boolccdi3_internal2"
7859 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7860 (compare:CC (match_operator:DI 4 "boolean_operator"
7861 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7862 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7863 (const_int 0)))
7864 (clobber (match_scratch:DI 3 "=r,r"))]
7865 "TARGET_64BIT"
7866 "@
7867 %q4. %3,%1,%2
7868 #"
7869 [(set_attr "type" "compare")
7870 (set_attr "length" "4,8")])
7872 (define_split
7873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7874 (compare:CC (match_operator:DI 4 "boolean_operator"
7875 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7876 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7877 (const_int 0)))
7878 (clobber (match_scratch:DI 3 ""))]
7879 "TARGET_POWERPC64 && reload_completed"
7880 [(set (match_dup 3) (match_dup 4))
7881 (set (match_dup 0)
7882 (compare:CC (match_dup 3)
7883 (const_int 0)))]
7884 "")
7886 (define_insn "*boolccdi3_internal3"
7887 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7888 (compare:CC (match_operator:DI 4 "boolean_operator"
7889 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7890 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7891 (const_int 0)))
7892 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7893 (match_dup 4))]
7894 "TARGET_64BIT"
7895 "@
7896 %q4. %0,%1,%2
7897 #"
7898 [(set_attr "type" "compare")
7899 (set_attr "length" "4,8")])
7901 (define_split
7902 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7903 (compare:CC (match_operator:DI 4 "boolean_operator"
7904 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7905 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7906 (const_int 0)))
7907 (set (match_operand:DI 0 "gpc_reg_operand" "")
7908 (match_dup 4))]
7909 "TARGET_POWERPC64 && reload_completed"
7910 [(set (match_dup 0) (match_dup 4))
7911 (set (match_dup 3)
7912 (compare:CC (match_dup 0)
7913 (const_int 0)))]
7914 "")
7915 \f
7916 ;; Now define ways of moving data around.
7918 ;; Set up a register with a value from the GOT table
7920 (define_expand "movsi_got"
7921 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7922 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7923 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7924 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7925 "
7926 {
7927 if (GET_CODE (operands[1]) == CONST)
7928 {
7929 rtx offset = const0_rtx;
7930 HOST_WIDE_INT value;
7932 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7933 value = INTVAL (offset);
7934 if (value != 0)
7935 {
7936 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7937 emit_insn (gen_movsi_got (tmp, operands[1]));
7938 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7939 DONE;
7940 }
7941 }
7943 operands[2] = rs6000_got_register (operands[1]);
7944 }")
7946 (define_insn "*movsi_got_internal"
7947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7948 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7949 (match_operand:SI 2 "gpc_reg_operand" "b")]
7950 UNSPEC_MOVSI_GOT))]
7951 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7952 "{l|lwz} %0,%a1@got(%2)"
7953 [(set_attr "type" "load")])
7955 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7956 ;; didn't get allocated to a hard register.
7957 (define_split
7958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7959 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7960 (match_operand:SI 2 "memory_operand" "")]
7961 UNSPEC_MOVSI_GOT))]
7962 "DEFAULT_ABI == ABI_V4
7963 && flag_pic == 1
7964 && (reload_in_progress || reload_completed)"
7965 [(set (match_dup 0) (match_dup 2))
7966 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7967 UNSPEC_MOVSI_GOT))]
7968 "")
7970 ;; For SI, we special-case integers that can't be loaded in one insn. We
7971 ;; do the load 16-bits at a time. We could do this by loading from memory,
7972 ;; and this is even supposed to be faster, but it is simpler not to get
7973 ;; integers in the TOC.
7974 (define_insn "movsi_low"
7975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7976 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7977 (match_operand 2 "" ""))))]
7978 "TARGET_MACHO && ! TARGET_64BIT"
7979 "{l|lwz} %0,lo16(%2)(%1)"
7980 [(set_attr "type" "load")
7981 (set_attr "length" "4")])
7983 (define_insn "*movsi_internal1"
7984 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7985 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7986 "gpc_reg_operand (operands[0], SImode)
7987 || gpc_reg_operand (operands[1], SImode)"
7988 "@
7989 mr %0,%1
7990 {cal|la} %0,%a1
7991 {l%U1%X1|lwz%U1%X1} %0,%1
7992 {st%U0%X0|stw%U0%X0} %1,%0
7993 {lil|li} %0,%1
7994 {liu|lis} %0,%v1
7995 #
7996 {cal|la} %0,%a1
7997 mf%1 %0
7998 mt%0 %1
7999 mt%0 %1
8000 mt%0 %1
8001 {cror 0,0,0|nop}"
8002 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8003 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8005 ;; Split a load of a large constant into the appropriate two-insn
8006 ;; sequence.
8008 (define_split
8009 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8010 (match_operand:SI 1 "const_int_operand" ""))]
8011 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8012 && (INTVAL (operands[1]) & 0xffff) != 0"
8013 [(set (match_dup 0)
8014 (match_dup 2))
8015 (set (match_dup 0)
8016 (ior:SI (match_dup 0)
8017 (match_dup 3)))]
8018 "
8019 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8021 if (tem == operands[0])
8022 DONE;
8023 else
8024 FAIL;
8025 }")
8027 (define_insn "*mov<mode>_internal2"
8028 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8029 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8030 (const_int 0)))
8031 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8032 ""
8033 "@
8034 {cmpi|cmp<wd>i} %2,%0,0
8035 mr. %0,%1
8036 #"
8037 [(set_attr "type" "cmp,compare,cmp")
8038 (set_attr "length" "4,4,8")])
8040 (define_split
8041 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8042 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8043 (const_int 0)))
8044 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8045 "reload_completed"
8046 [(set (match_dup 0) (match_dup 1))
8047 (set (match_dup 2)
8048 (compare:CC (match_dup 0)
8049 (const_int 0)))]
8050 "")
8051 \f
8052 (define_insn "*movhi_internal"
8053 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8054 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8055 "gpc_reg_operand (operands[0], HImode)
8056 || gpc_reg_operand (operands[1], HImode)"
8057 "@
8058 mr %0,%1
8059 lhz%U1%X1 %0,%1
8060 sth%U0%X0 %1,%0
8061 {lil|li} %0,%w1
8062 mf%1 %0
8063 mt%0 %1
8064 mt%0 %1
8065 {cror 0,0,0|nop}"
8066 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8068 (define_expand "mov<mode>"
8069 [(set (match_operand:INT 0 "general_operand" "")
8070 (match_operand:INT 1 "any_operand" ""))]
8071 ""
8072 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8074 (define_insn "*movqi_internal"
8075 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8076 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8077 "gpc_reg_operand (operands[0], QImode)
8078 || gpc_reg_operand (operands[1], QImode)"
8079 "@
8080 mr %0,%1
8081 lbz%U1%X1 %0,%1
8082 stb%U0%X0 %1,%0
8083 {lil|li} %0,%1
8084 mf%1 %0
8085 mt%0 %1
8086 mt%0 %1
8087 {cror 0,0,0|nop}"
8088 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8089 \f
8090 ;; Here is how to move condition codes around. When we store CC data in
8091 ;; an integer register or memory, we store just the high-order 4 bits.
8092 ;; This lets us not shift in the most common case of CR0.
8093 (define_expand "movcc"
8094 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8095 (match_operand:CC 1 "nonimmediate_operand" ""))]
8096 ""
8097 "")
8099 (define_insn "*movcc_internal1"
8100 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8101 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8102 "register_operand (operands[0], CCmode)
8103 || register_operand (operands[1], CCmode)"
8104 "@
8105 mcrf %0,%1
8106 mtcrf 128,%1
8107 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8108 crxor %0,%0,%0
8109 mfcr %0%Q1
8110 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8111 mr %0,%1
8112 {lil|li} %0,%1
8113 mf%1 %0
8114 mt%0 %1
8115 mt%0 %1
8116 {l%U1%X1|lwz%U1%X1} %0,%1
8117 {st%U0%U1|stw%U0%U1} %1,%0"
8118 [(set (attr "type")
8119 (cond [(eq_attr "alternative" "0,3")
8120 (const_string "cr_logical")
8121 (eq_attr "alternative" "1,2")
8122 (const_string "mtcr")
8123 (eq_attr "alternative" "6,7,9")
8124 (const_string "integer")
8125 (eq_attr "alternative" "8")
8126 (const_string "mfjmpr")
8127 (eq_attr "alternative" "10")
8128 (const_string "mtjmpr")
8129 (eq_attr "alternative" "11")
8130 (const_string "load")
8131 (eq_attr "alternative" "12")
8132 (const_string "store")
8133 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8134 (const_string "mfcrf")
8135 ]
8136 (const_string "mfcr")))
8137 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8138 \f
8139 ;; For floating-point, we normally deal with the floating-point registers
8140 ;; unless -msoft-float is used. The sole exception is that parameter passing
8141 ;; can produce floating-point values in fixed-point registers. Unless the
8142 ;; value is a simple constant or already in memory, we deal with this by
8143 ;; allocating memory and copying the value explicitly via that memory location.
8144 (define_expand "movsf"
8145 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8146 (match_operand:SF 1 "any_operand" ""))]
8147 ""
8148 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8150 (define_split
8151 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8152 (match_operand:SF 1 "const_double_operand" ""))]
8153 "reload_completed
8154 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8155 || (GET_CODE (operands[0]) == SUBREG
8156 && GET_CODE (SUBREG_REG (operands[0])) == REG
8157 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8158 [(set (match_dup 2) (match_dup 3))]
8159 "
8160 {
8161 long l;
8162 REAL_VALUE_TYPE rv;
8164 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8165 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8167 if (! TARGET_POWERPC64)
8168 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8169 else
8170 operands[2] = gen_lowpart (SImode, operands[0]);
8172 operands[3] = gen_int_mode (l, SImode);
8173 }")
8175 (define_insn "*movsf_hardfloat"
8176 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8177 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8178 "(gpc_reg_operand (operands[0], SFmode)
8179 || gpc_reg_operand (operands[1], SFmode))
8180 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8181 "@
8182 mr %0,%1
8183 {l%U1%X1|lwz%U1%X1} %0,%1
8184 {st%U0%X0|stw%U0%X0} %1,%0
8185 fmr %0,%1
8186 lfs%U1%X1 %0,%1
8187 stfs%U0%X0 %1,%0
8188 mt%0 %1
8189 mt%0 %1
8190 mf%1 %0
8191 {cror 0,0,0|nop}
8192 #
8193 #"
8194 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8195 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8197 (define_insn "*movsf_softfloat"
8198 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8199 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8200 "(gpc_reg_operand (operands[0], SFmode)
8201 || gpc_reg_operand (operands[1], SFmode))
8202 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8203 "@
8204 mr %0,%1
8205 mt%0 %1
8206 mt%0 %1
8207 mf%1 %0
8208 {l%U1%X1|lwz%U1%X1} %0,%1
8209 {st%U0%X0|stw%U0%X0} %1,%0
8210 {lil|li} %0,%1
8211 {liu|lis} %0,%v1
8212 {cal|la} %0,%a1
8213 #
8214 #
8215 {cror 0,0,0|nop}"
8216 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8217 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8219 \f
8220 (define_expand "movdf"
8221 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8222 (match_operand:DF 1 "any_operand" ""))]
8223 ""
8224 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8226 (define_split
8227 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8228 (match_operand:DF 1 "const_int_operand" ""))]
8229 "! TARGET_POWERPC64 && reload_completed
8230 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8231 || (GET_CODE (operands[0]) == SUBREG
8232 && GET_CODE (SUBREG_REG (operands[0])) == REG
8233 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8234 [(set (match_dup 2) (match_dup 4))
8235 (set (match_dup 3) (match_dup 1))]
8236 "
8237 {
8238 int endian = (WORDS_BIG_ENDIAN == 0);
8239 HOST_WIDE_INT value = INTVAL (operands[1]);
8241 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8242 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8243 #if HOST_BITS_PER_WIDE_INT == 32
8244 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8245 #else
8246 operands[4] = GEN_INT (value >> 32);
8247 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8248 #endif
8249 }")
8251 (define_split
8252 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8253 (match_operand:DF 1 "const_double_operand" ""))]
8254 "! TARGET_POWERPC64 && reload_completed
8255 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8256 || (GET_CODE (operands[0]) == SUBREG
8257 && GET_CODE (SUBREG_REG (operands[0])) == REG
8258 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8259 [(set (match_dup 2) (match_dup 4))
8260 (set (match_dup 3) (match_dup 5))]
8261 "
8262 {
8263 int endian = (WORDS_BIG_ENDIAN == 0);
8264 long l[2];
8265 REAL_VALUE_TYPE rv;
8267 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8268 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8270 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8271 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8272 operands[4] = gen_int_mode (l[endian], SImode);
8273 operands[5] = gen_int_mode (l[1 - endian], SImode);
8274 }")
8276 (define_split
8277 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8278 (match_operand:DF 1 "const_double_operand" ""))]
8279 "TARGET_POWERPC64 && reload_completed
8280 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8281 || (GET_CODE (operands[0]) == SUBREG
8282 && GET_CODE (SUBREG_REG (operands[0])) == REG
8283 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8284 [(set (match_dup 2) (match_dup 3))]
8285 "
8286 {
8287 int endian = (WORDS_BIG_ENDIAN == 0);
8288 long l[2];
8289 REAL_VALUE_TYPE rv;
8290 #if HOST_BITS_PER_WIDE_INT >= 64
8291 HOST_WIDE_INT val;
8292 #endif
8294 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8295 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8297 operands[2] = gen_lowpart (DImode, operands[0]);
8298 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8299 #if HOST_BITS_PER_WIDE_INT >= 64
8300 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8301 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8303 operands[3] = gen_int_mode (val, DImode);
8304 #else
8305 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8306 #endif
8307 }")
8309 ;; Don't have reload use general registers to load a constant. First,
8310 ;; it might not work if the output operand is the equivalent of
8311 ;; a non-offsettable memref, but also it is less efficient than loading
8312 ;; the constant into an FP register, since it will probably be used there.
8313 ;; The "??" is a kludge until we can figure out a more reasonable way
8314 ;; of handling these non-offsettable values.
8315 (define_insn "*movdf_hardfloat32"
8316 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8317 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8318 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8319 && (gpc_reg_operand (operands[0], DFmode)
8320 || gpc_reg_operand (operands[1], DFmode))"
8321 "*
8322 {
8323 switch (which_alternative)
8324 {
8325 default:
8326 gcc_unreachable ();
8327 case 0:
8328 /* We normally copy the low-numbered register first. However, if
8329 the first register operand 0 is the same as the second register
8330 of operand 1, we must copy in the opposite order. */
8331 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8332 return \"mr %L0,%L1\;mr %0,%1\";
8333 else
8334 return \"mr %0,%1\;mr %L0,%L1\";
8335 case 1:
8336 if (rs6000_offsettable_memref_p (operands[1])
8337 || (GET_CODE (operands[1]) == MEM
8338 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8339 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8340 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8341 {
8342 /* If the low-address word is used in the address, we must load
8343 it last. Otherwise, load it first. Note that we cannot have
8344 auto-increment in that case since the address register is
8345 known to be dead. */
8346 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8347 operands[1], 0))
8348 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8349 else
8350 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8351 }
8352 else
8353 {
8354 rtx addreg;
8356 addreg = find_addr_reg (XEXP (operands[1], 0));
8357 if (refers_to_regno_p (REGNO (operands[0]),
8358 REGNO (operands[0]) + 1,
8359 operands[1], 0))
8360 {
8361 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8362 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8363 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8364 return \"{l%X1|lwz%X1} %0,%1\";
8365 }
8366 else
8367 {
8368 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8369 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8370 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8371 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8372 return \"\";
8373 }
8374 }
8375 case 2:
8376 if (rs6000_offsettable_memref_p (operands[0])
8377 || (GET_CODE (operands[0]) == MEM
8378 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8379 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8380 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8381 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8382 else
8383 {
8384 rtx addreg;
8386 addreg = find_addr_reg (XEXP (operands[0], 0));
8387 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8388 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8389 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8390 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8391 return \"\";
8392 }
8393 case 3:
8394 return \"fmr %0,%1\";
8395 case 4:
8396 return \"lfd%U1%X1 %0,%1\";
8397 case 5:
8398 return \"stfd%U0%X0 %1,%0\";
8399 case 6:
8400 case 7:
8401 case 8:
8402 return \"#\";
8403 }
8404 }"
8405 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8406 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8408 (define_insn "*movdf_softfloat32"
8409 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8410 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8411 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8412 && (gpc_reg_operand (operands[0], DFmode)
8413 || gpc_reg_operand (operands[1], DFmode))"
8414 "*
8415 {
8416 switch (which_alternative)
8417 {
8418 default:
8419 gcc_unreachable ();
8420 case 0:
8421 /* We normally copy the low-numbered register first. However, if
8422 the first register operand 0 is the same as the second register of
8423 operand 1, we must copy in the opposite order. */
8424 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8425 return \"mr %L0,%L1\;mr %0,%1\";
8426 else
8427 return \"mr %0,%1\;mr %L0,%L1\";
8428 case 1:
8429 /* If the low-address word is used in the address, we must load
8430 it last. Otherwise, load it first. Note that we cannot have
8431 auto-increment in that case since the address register is
8432 known to be dead. */
8433 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8434 operands[1], 0))
8435 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8436 else
8437 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8438 case 2:
8439 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8440 case 3:
8441 case 4:
8442 case 5:
8443 return \"#\";
8444 }
8445 }"
8446 [(set_attr "type" "two,load,store,*,*,*")
8447 (set_attr "length" "8,8,8,8,12,16")])
8449 ; ld/std require word-aligned displacements -> 'Y' constraint.
8450 ; List Y->r and r->Y before r->r for reload.
8451 (define_insn "*movdf_hardfloat64_mfpgpr"
8452 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8453 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8454 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8455 && (gpc_reg_operand (operands[0], DFmode)
8456 || gpc_reg_operand (operands[1], DFmode))"
8457 "@
8458 std%U0%X0 %1,%0
8459 ld%U1%X1 %0,%1
8460 mr %0,%1
8461 fmr %0,%1
8462 lfd%U1%X1 %0,%1
8463 stfd%U0%X0 %1,%0
8464 mt%0 %1
8465 mf%1 %0
8466 {cror 0,0,0|nop}
8467 #
8468 #
8469 #
8470 mftgpr %0,%1
8471 mffgpr %0,%1"
8472 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8473 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8475 ; ld/std require word-aligned displacements -> 'Y' constraint.
8476 ; List Y->r and r->Y before r->r for reload.
8477 (define_insn "*movdf_hardfloat64"
8478 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8479 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8480 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8481 && (gpc_reg_operand (operands[0], DFmode)
8482 || gpc_reg_operand (operands[1], DFmode))"
8483 "@
8484 std%U0%X0 %1,%0
8485 ld%U1%X1 %0,%1
8486 mr %0,%1
8487 fmr %0,%1
8488 lfd%U1%X1 %0,%1
8489 stfd%U0%X0 %1,%0
8490 mt%0 %1
8491 mf%1 %0
8492 {cror 0,0,0|nop}
8493 #
8494 #
8495 #"
8496 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8497 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8499 (define_insn "*movdf_softfloat64"
8500 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8501 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8502 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8503 && (gpc_reg_operand (operands[0], DFmode)
8504 || gpc_reg_operand (operands[1], DFmode))"
8505 "@
8506 ld%U1%X1 %0,%1
8507 std%U0%X0 %1,%0
8508 mr %0,%1
8509 mt%0 %1
8510 mf%1 %0
8511 #
8512 #
8513 #
8514 {cror 0,0,0|nop}"
8515 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8516 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8517 \f
8518 (define_expand "movtf"
8519 [(set (match_operand:TF 0 "general_operand" "")
8520 (match_operand:TF 1 "any_operand" ""))]
8521 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8522 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8524 ; It's important to list the o->f and f->o moves before f->f because
8525 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8526 ; which doesn't make progress. Likewise r->Y must be before r->r.
8527 (define_insn_and_split "*movtf_internal"
8528 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8529 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8530 "!TARGET_IEEEQUAD
8531 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8532 && (gpc_reg_operand (operands[0], TFmode)
8533 || gpc_reg_operand (operands[1], TFmode))"
8534 "#"
8535 "&& reload_completed"
8536 [(pc)]
8537 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8538 [(set_attr "length" "8,8,8,20,20,16")])
8540 (define_insn_and_split "*movtf_softfloat"
8541 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,Y,r")
8542 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8543 "!TARGET_IEEEQUAD
8544 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8545 && (gpc_reg_operand (operands[0], TFmode)
8546 || gpc_reg_operand (operands[1], TFmode))"
8547 "#"
8548 "&& reload_completed"
8549 [(pc)]
8550 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8551 [(set_attr "length" "20,20,16")])
8553 (define_expand "extenddftf2"
8554 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8555 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8556 (use (match_dup 2))])]
8557 "!TARGET_IEEEQUAD
8558 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8559 {
8560 operands[2] = CONST0_RTX (DFmode);
8561 /* Generate GOT reference early for SVR4 PIC. */
8562 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8563 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8564 })
8566 (define_insn_and_split "*extenddftf2_internal"
8567 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8568 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8569 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8570 "!TARGET_IEEEQUAD
8571 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8572 "#"
8573 "&& reload_completed"
8574 [(pc)]
8575 {
8576 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8577 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8578 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8579 operands[1]);
8580 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8581 operands[2]);
8582 DONE;
8583 })
8585 (define_expand "extendsftf2"
8586 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8587 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8588 "!TARGET_IEEEQUAD
8589 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8590 {
8591 rtx tmp = gen_reg_rtx (DFmode);
8592 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8593 emit_insn (gen_extenddftf2 (operands[0], tmp));
8594 DONE;
8595 })
8597 (define_expand "trunctfdf2"
8598 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8599 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8600 "!TARGET_IEEEQUAD
8601 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8602 "")
8604 (define_insn_and_split "trunctfdf2_internal1"
8605 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8606 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8607 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8608 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8609 "@
8610 #
8611 fmr %0,%1"
8612 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8613 [(const_int 0)]
8614 {
8615 emit_note (NOTE_INSN_DELETED);
8616 DONE;
8617 }
8618 [(set_attr "type" "fp")])
8620 (define_insn "trunctfdf2_internal2"
8621 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8622 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8623 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8624 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8625 "fadd %0,%1,%L1"
8626 [(set_attr "type" "fp")])
8628 (define_insn_and_split "trunctfsf2"
8629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8630 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8631 (clobber (match_scratch:DF 2 "=f"))]
8632 "!TARGET_IEEEQUAD
8633 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8634 "#"
8635 "&& reload_completed"
8636 [(set (match_dup 2)
8637 (float_truncate:DF (match_dup 1)))
8638 (set (match_dup 0)
8639 (float_truncate:SF (match_dup 2)))]
8640 "")
8642 (define_expand "floatsitf2"
8643 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8644 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8645 "!TARGET_IEEEQUAD
8646 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8647 {
8648 rtx tmp = gen_reg_rtx (DFmode);
8649 expand_float (tmp, operands[1], false);
8650 emit_insn (gen_extenddftf2 (operands[0], tmp));
8651 DONE;
8652 })
8654 ; fadd, but rounding towards zero.
8655 ; This is probably not the optimal code sequence.
8656 (define_insn "fix_trunc_helper"
8657 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8658 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8659 UNSPEC_FIX_TRUNC_TF))
8660 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8661 "TARGET_HARD_FLOAT && TARGET_FPRS"
8662 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8663 [(set_attr "type" "fp")
8664 (set_attr "length" "20")])
8666 (define_expand "fix_trunctfsi2"
8667 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8668 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8669 (clobber (match_dup 2))
8670 (clobber (match_dup 3))
8671 (clobber (match_dup 4))
8672 (clobber (match_dup 5))])]
8673 "!TARGET_IEEEQUAD
8674 && (TARGET_POWER2 || TARGET_POWERPC)
8675 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8676 {
8677 operands[2] = gen_reg_rtx (DFmode);
8678 operands[3] = gen_reg_rtx (DFmode);
8679 operands[4] = gen_reg_rtx (DImode);
8680 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8681 })
8683 (define_insn_and_split "*fix_trunctfsi2_internal"
8684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8685 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8686 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8687 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8688 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8689 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8690 "!TARGET_IEEEQUAD
8691 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8692 "#"
8693 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8694 [(pc)]
8695 {
8696 rtx lowword;
8697 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8699 gcc_assert (MEM_P (operands[5]));
8700 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8702 emit_insn (gen_fctiwz (operands[4], operands[2]));
8703 emit_move_insn (operands[5], operands[4]);
8704 emit_move_insn (operands[0], lowword);
8705 DONE;
8706 })
8708 (define_insn "negtf2"
8709 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8710 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8711 "!TARGET_IEEEQUAD
8712 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8713 "*
8714 {
8715 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8716 return \"fneg %L0,%L1\;fneg %0,%1\";
8717 else
8718 return \"fneg %0,%1\;fneg %L0,%L1\";
8719 }"
8720 [(set_attr "type" "fp")
8721 (set_attr "length" "8")])
8723 (define_expand "abstf2"
8724 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8725 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8726 "!TARGET_IEEEQUAD
8727 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8728 "
8729 {
8730 rtx label = gen_label_rtx ();
8731 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8732 emit_label (label);
8733 DONE;
8734 }")
8736 (define_expand "abstf2_internal"
8737 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8738 (match_operand:TF 1 "gpc_reg_operand" "f"))
8739 (set (match_dup 3) (match_dup 5))
8740 (set (match_dup 5) (abs:DF (match_dup 5)))
8741 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8742 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8743 (label_ref (match_operand 2 "" ""))
8744 (pc)))
8745 (set (match_dup 6) (neg:DF (match_dup 6)))]
8746 "!TARGET_IEEEQUAD
8747 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8748 "
8749 {
8750 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8751 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8752 operands[3] = gen_reg_rtx (DFmode);
8753 operands[4] = gen_reg_rtx (CCFPmode);
8754 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8755 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8756 }")
8757 \f
8758 ;; Next come the multi-word integer load and store and the load and store
8759 ;; multiple insns.
8761 ; List r->r after r->"o<>", otherwise reload will try to reload a
8762 ; non-offsettable address by using r->r which won't make progress.
8763 (define_insn "*movdi_internal32"
8764 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8765 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8766 "! TARGET_POWERPC64
8767 && (gpc_reg_operand (operands[0], DImode)
8768 || gpc_reg_operand (operands[1], DImode))"
8769 "@
8770 #
8771 #
8772 #
8773 fmr %0,%1
8774 lfd%U1%X1 %0,%1
8775 stfd%U0%X0 %1,%0
8776 #"
8777 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8779 (define_split
8780 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8781 (match_operand:DI 1 "const_int_operand" ""))]
8782 "! TARGET_POWERPC64 && reload_completed"
8783 [(set (match_dup 2) (match_dup 4))
8784 (set (match_dup 3) (match_dup 1))]
8785 "
8786 {
8787 HOST_WIDE_INT value = INTVAL (operands[1]);
8788 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8789 DImode);
8790 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8791 DImode);
8792 #if HOST_BITS_PER_WIDE_INT == 32
8793 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8794 #else
8795 operands[4] = GEN_INT (value >> 32);
8796 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8797 #endif
8798 }")
8800 (define_split
8801 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8802 (match_operand:DI 1 "input_operand" ""))]
8803 "reload_completed && !TARGET_POWERPC64
8804 && gpr_or_gpr_p (operands[0], operands[1])"
8805 [(pc)]
8806 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8808 (define_insn "*movdi_mfpgpr"
8809 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8810 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8811 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8812 && (gpc_reg_operand (operands[0], DImode)
8813 || gpc_reg_operand (operands[1], DImode))"
8814 "@
8815 mr %0,%1
8816 ld%U1%X1 %0,%1
8817 std%U0%X0 %1,%0
8818 li %0,%1
8819 lis %0,%v1
8820 #
8821 {cal|la} %0,%a1
8822 fmr %0,%1
8823 lfd%U1%X1 %0,%1
8824 stfd%U0%X0 %1,%0
8825 mf%1 %0
8826 mt%0 %1
8827 {cror 0,0,0|nop}
8828 mftgpr %0,%1
8829 mffgpr %0,%1"
8830 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8831 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8833 (define_insn "*movdi_internal64"
8834 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8835 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8836 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8837 && (gpc_reg_operand (operands[0], DImode)
8838 || gpc_reg_operand (operands[1], DImode))"
8839 "@
8840 mr %0,%1
8841 ld%U1%X1 %0,%1
8842 std%U0%X0 %1,%0
8843 li %0,%1
8844 lis %0,%v1
8845 #
8846 {cal|la} %0,%a1
8847 fmr %0,%1
8848 lfd%U1%X1 %0,%1
8849 stfd%U0%X0 %1,%0
8850 mf%1 %0
8851 mt%0 %1
8852 {cror 0,0,0|nop}"
8853 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8854 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8856 ;; immediate value valid for a single instruction hiding in a const_double
8857 (define_insn ""
8858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8859 (match_operand:DI 1 "const_double_operand" "F"))]
8860 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8861 && GET_CODE (operands[1]) == CONST_DOUBLE
8862 && num_insns_constant (operands[1], DImode) == 1"
8863 "*
8864 {
8865 return ((unsigned HOST_WIDE_INT)
8866 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8867 ? \"li %0,%1\" : \"lis %0,%v1\";
8868 }")
8870 ;; Generate all one-bits and clear left or right.
8871 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8872 (define_split
8873 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8874 (match_operand:DI 1 "mask64_operand" ""))]
8875 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8876 [(set (match_dup 0) (const_int -1))
8877 (set (match_dup 0)
8878 (and:DI (rotate:DI (match_dup 0)
8879 (const_int 0))
8880 (match_dup 1)))]
8881 "")
8883 ;; Split a load of a large constant into the appropriate five-instruction
8884 ;; sequence. Handle anything in a constant number of insns.
8885 ;; When non-easy constants can go in the TOC, this should use
8886 ;; easy_fp_constant predicate.
8887 (define_split
8888 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8889 (match_operand:DI 1 "const_int_operand" ""))]
8890 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8891 [(set (match_dup 0) (match_dup 2))
8892 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8893 "
8894 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8896 if (tem == operands[0])
8897 DONE;
8898 else
8899 FAIL;
8900 }")
8902 (define_split
8903 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8904 (match_operand:DI 1 "const_double_operand" ""))]
8905 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8906 [(set (match_dup 0) (match_dup 2))
8907 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8908 "
8909 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8911 if (tem == operands[0])
8912 DONE;
8913 else
8914 FAIL;
8915 }")
8916 \f
8917 ;; TImode is similar, except that we usually want to compute the address into
8918 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8919 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8921 ;; We say that MQ is clobbered in the last alternative because the first
8922 ;; alternative would never get used otherwise since it would need a reload
8923 ;; while the 2nd alternative would not. We put memory cases first so they
8924 ;; are preferred. Otherwise, we'd try to reload the output instead of
8925 ;; giving the SCRATCH mq.
8927 (define_insn "*movti_power"
8928 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8929 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8930 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8931 "TARGET_POWER && ! TARGET_POWERPC64
8932 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8933 "*
8934 {
8935 switch (which_alternative)
8936 {
8937 default:
8938 gcc_unreachable ();
8940 case 0:
8941 if (TARGET_STRING)
8942 return \"{stsi|stswi} %1,%P0,16\";
8943 case 1:
8944 case 2:
8945 return \"#\";
8946 case 3:
8947 /* If the address is not used in the output, we can use lsi. Otherwise,
8948 fall through to generating four loads. */
8949 if (TARGET_STRING
8950 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8951 return \"{lsi|lswi} %0,%P1,16\";
8952 /* ... fall through ... */
8953 case 4:
8954 case 5:
8955 return \"#\";
8956 }
8957 }"
8958 [(set_attr "type" "store,store,*,load,load,*")])
8960 (define_insn "*movti_string"
8961 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8962 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8963 "! TARGET_POWER && ! TARGET_POWERPC64
8964 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8965 "*
8966 {
8967 switch (which_alternative)
8968 {
8969 default:
8970 gcc_unreachable ();
8971 case 0:
8972 if (TARGET_STRING)
8973 return \"{stsi|stswi} %1,%P0,16\";
8974 case 1:
8975 case 2:
8976 return \"#\";
8977 case 3:
8978 /* If the address is not used in the output, we can use lsi. Otherwise,
8979 fall through to generating four loads. */
8980 if (TARGET_STRING
8981 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8982 return \"{lsi|lswi} %0,%P1,16\";
8983 /* ... fall through ... */
8984 case 4:
8985 case 5:
8986 return \"#\";
8987 }
8988 }"
8989 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8991 (define_insn "*movti_ppc64"
8992 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8993 (match_operand:TI 1 "input_operand" "r,r,m"))]
8994 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8995 || gpc_reg_operand (operands[1], TImode))"
8996 "#"
8997 [(set_attr "type" "*,load,store")])
8999 (define_split
9000 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9001 (match_operand:TI 1 "const_double_operand" ""))]
9002 "TARGET_POWERPC64"
9003 [(set (match_dup 2) (match_dup 4))
9004 (set (match_dup 3) (match_dup 5))]
9005 "
9006 {
9007 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9008 TImode);
9009 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9010 TImode);
9011 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9012 {
9013 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9014 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9015 }
9016 else if (GET_CODE (operands[1]) == CONST_INT)
9017 {
9018 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9019 operands[5] = operands[1];
9020 }
9021 else
9022 FAIL;
9023 }")
9025 (define_split
9026 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9027 (match_operand:TI 1 "input_operand" ""))]
9028 "reload_completed
9029 && gpr_or_gpr_p (operands[0], operands[1])"
9030 [(pc)]
9031 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9032 \f
9033 (define_expand "load_multiple"
9034 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9035 (match_operand:SI 1 "" ""))
9036 (use (match_operand:SI 2 "" ""))])]
9037 "TARGET_STRING && !TARGET_POWERPC64"
9038 "
9039 {
9040 int regno;
9041 int count;
9042 rtx op1;
9043 int i;
9045 /* Support only loading a constant number of fixed-point registers from
9046 memory and only bother with this if more than two; the machine
9047 doesn't support more than eight. */
9048 if (GET_CODE (operands[2]) != CONST_INT
9049 || INTVAL (operands[2]) <= 2
9050 || INTVAL (operands[2]) > 8
9051 || GET_CODE (operands[1]) != MEM
9052 || GET_CODE (operands[0]) != REG
9053 || REGNO (operands[0]) >= 32)
9054 FAIL;
9056 count = INTVAL (operands[2]);
9057 regno = REGNO (operands[0]);
9059 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9060 op1 = replace_equiv_address (operands[1],
9061 force_reg (SImode, XEXP (operands[1], 0)));
9063 for (i = 0; i < count; i++)
9064 XVECEXP (operands[3], 0, i)
9065 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9066 adjust_address_nv (op1, SImode, i * 4));
9067 }")
9069 (define_insn "*ldmsi8"
9070 [(match_parallel 0 "load_multiple_operation"
9071 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9072 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9073 (set (match_operand:SI 3 "gpc_reg_operand" "")
9074 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9075 (set (match_operand:SI 4 "gpc_reg_operand" "")
9076 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9077 (set (match_operand:SI 5 "gpc_reg_operand" "")
9078 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9079 (set (match_operand:SI 6 "gpc_reg_operand" "")
9080 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9081 (set (match_operand:SI 7 "gpc_reg_operand" "")
9082 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9083 (set (match_operand:SI 8 "gpc_reg_operand" "")
9084 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9085 (set (match_operand:SI 9 "gpc_reg_operand" "")
9086 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9087 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9088 "*
9089 { return rs6000_output_load_multiple (operands); }"
9090 [(set_attr "type" "load_ux")
9091 (set_attr "length" "32")])
9093 (define_insn "*ldmsi7"
9094 [(match_parallel 0 "load_multiple_operation"
9095 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9096 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9097 (set (match_operand:SI 3 "gpc_reg_operand" "")
9098 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9099 (set (match_operand:SI 4 "gpc_reg_operand" "")
9100 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9101 (set (match_operand:SI 5 "gpc_reg_operand" "")
9102 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9103 (set (match_operand:SI 6 "gpc_reg_operand" "")
9104 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9105 (set (match_operand:SI 7 "gpc_reg_operand" "")
9106 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9107 (set (match_operand:SI 8 "gpc_reg_operand" "")
9108 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9109 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9110 "*
9111 { return rs6000_output_load_multiple (operands); }"
9112 [(set_attr "type" "load_ux")
9113 (set_attr "length" "32")])
9115 (define_insn "*ldmsi6"
9116 [(match_parallel 0 "load_multiple_operation"
9117 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9118 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9119 (set (match_operand:SI 3 "gpc_reg_operand" "")
9120 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9121 (set (match_operand:SI 4 "gpc_reg_operand" "")
9122 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9123 (set (match_operand:SI 5 "gpc_reg_operand" "")
9124 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9125 (set (match_operand:SI 6 "gpc_reg_operand" "")
9126 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9127 (set (match_operand:SI 7 "gpc_reg_operand" "")
9128 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9129 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9130 "*
9131 { return rs6000_output_load_multiple (operands); }"
9132 [(set_attr "type" "load_ux")
9133 (set_attr "length" "32")])
9135 (define_insn "*ldmsi5"
9136 [(match_parallel 0 "load_multiple_operation"
9137 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9138 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9139 (set (match_operand:SI 3 "gpc_reg_operand" "")
9140 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9141 (set (match_operand:SI 4 "gpc_reg_operand" "")
9142 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9143 (set (match_operand:SI 5 "gpc_reg_operand" "")
9144 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9145 (set (match_operand:SI 6 "gpc_reg_operand" "")
9146 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9147 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9148 "*
9149 { return rs6000_output_load_multiple (operands); }"
9150 [(set_attr "type" "load_ux")
9151 (set_attr "length" "32")])
9153 (define_insn "*ldmsi4"
9154 [(match_parallel 0 "load_multiple_operation"
9155 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9156 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9157 (set (match_operand:SI 3 "gpc_reg_operand" "")
9158 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9159 (set (match_operand:SI 4 "gpc_reg_operand" "")
9160 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9161 (set (match_operand:SI 5 "gpc_reg_operand" "")
9162 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9163 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9164 "*
9165 { return rs6000_output_load_multiple (operands); }"
9166 [(set_attr "type" "load_ux")
9167 (set_attr "length" "32")])
9169 (define_insn "*ldmsi3"
9170 [(match_parallel 0 "load_multiple_operation"
9171 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9172 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9173 (set (match_operand:SI 3 "gpc_reg_operand" "")
9174 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9175 (set (match_operand:SI 4 "gpc_reg_operand" "")
9176 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9177 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9178 "*
9179 { return rs6000_output_load_multiple (operands); }"
9180 [(set_attr "type" "load_ux")
9181 (set_attr "length" "32")])
9183 (define_expand "store_multiple"
9184 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9185 (match_operand:SI 1 "" ""))
9186 (clobber (scratch:SI))
9187 (use (match_operand:SI 2 "" ""))])]
9188 "TARGET_STRING && !TARGET_POWERPC64"
9189 "
9190 {
9191 int regno;
9192 int count;
9193 rtx to;
9194 rtx op0;
9195 int i;
9197 /* Support only storing a constant number of fixed-point registers to
9198 memory and only bother with this if more than two; the machine
9199 doesn't support more than eight. */
9200 if (GET_CODE (operands[2]) != CONST_INT
9201 || INTVAL (operands[2]) <= 2
9202 || INTVAL (operands[2]) > 8
9203 || GET_CODE (operands[0]) != MEM
9204 || GET_CODE (operands[1]) != REG
9205 || REGNO (operands[1]) >= 32)
9206 FAIL;
9208 count = INTVAL (operands[2]);
9209 regno = REGNO (operands[1]);
9211 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9212 to = force_reg (SImode, XEXP (operands[0], 0));
9213 op0 = replace_equiv_address (operands[0], to);
9215 XVECEXP (operands[3], 0, 0)
9216 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9217 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9218 gen_rtx_SCRATCH (SImode));
9220 for (i = 1; i < count; i++)
9221 XVECEXP (operands[3], 0, i + 1)
9222 = gen_rtx_SET (VOIDmode,
9223 adjust_address_nv (op0, SImode, i * 4),
9224 gen_rtx_REG (SImode, regno + i));
9225 }")
9227 (define_insn "*stmsi8"
9228 [(match_parallel 0 "store_multiple_operation"
9229 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9230 (match_operand:SI 2 "gpc_reg_operand" "r"))
9231 (clobber (match_scratch:SI 3 "=X"))
9232 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9233 (match_operand:SI 4 "gpc_reg_operand" "r"))
9234 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9235 (match_operand:SI 5 "gpc_reg_operand" "r"))
9236 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9237 (match_operand:SI 6 "gpc_reg_operand" "r"))
9238 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9239 (match_operand:SI 7 "gpc_reg_operand" "r"))
9240 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9241 (match_operand:SI 8 "gpc_reg_operand" "r"))
9242 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9243 (match_operand:SI 9 "gpc_reg_operand" "r"))
9244 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9245 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9246 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9247 "{stsi|stswi} %2,%1,%O0"
9248 [(set_attr "type" "store_ux")])
9250 (define_insn "*stmsi7"
9251 [(match_parallel 0 "store_multiple_operation"
9252 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9253 (match_operand:SI 2 "gpc_reg_operand" "r"))
9254 (clobber (match_scratch:SI 3 "=X"))
9255 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9256 (match_operand:SI 4 "gpc_reg_operand" "r"))
9257 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9258 (match_operand:SI 5 "gpc_reg_operand" "r"))
9259 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9260 (match_operand:SI 6 "gpc_reg_operand" "r"))
9261 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9262 (match_operand:SI 7 "gpc_reg_operand" "r"))
9263 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9264 (match_operand:SI 8 "gpc_reg_operand" "r"))
9265 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9266 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9267 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9268 "{stsi|stswi} %2,%1,%O0"
9269 [(set_attr "type" "store_ux")])
9271 (define_insn "*stmsi6"
9272 [(match_parallel 0 "store_multiple_operation"
9273 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9274 (match_operand:SI 2 "gpc_reg_operand" "r"))
9275 (clobber (match_scratch:SI 3 "=X"))
9276 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9277 (match_operand:SI 4 "gpc_reg_operand" "r"))
9278 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9279 (match_operand:SI 5 "gpc_reg_operand" "r"))
9280 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9281 (match_operand:SI 6 "gpc_reg_operand" "r"))
9282 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9283 (match_operand:SI 7 "gpc_reg_operand" "r"))
9284 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9285 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9286 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9287 "{stsi|stswi} %2,%1,%O0"
9288 [(set_attr "type" "store_ux")])
9290 (define_insn "*stmsi5"
9291 [(match_parallel 0 "store_multiple_operation"
9292 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9293 (match_operand:SI 2 "gpc_reg_operand" "r"))
9294 (clobber (match_scratch:SI 3 "=X"))
9295 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9296 (match_operand:SI 4 "gpc_reg_operand" "r"))
9297 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9298 (match_operand:SI 5 "gpc_reg_operand" "r"))
9299 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9300 (match_operand:SI 6 "gpc_reg_operand" "r"))
9301 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9302 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9303 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9304 "{stsi|stswi} %2,%1,%O0"
9305 [(set_attr "type" "store_ux")])
9307 (define_insn "*stmsi4"
9308 [(match_parallel 0 "store_multiple_operation"
9309 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9310 (match_operand:SI 2 "gpc_reg_operand" "r"))
9311 (clobber (match_scratch:SI 3 "=X"))
9312 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9313 (match_operand:SI 4 "gpc_reg_operand" "r"))
9314 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9315 (match_operand:SI 5 "gpc_reg_operand" "r"))
9316 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9317 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9318 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9319 "{stsi|stswi} %2,%1,%O0"
9320 [(set_attr "type" "store_ux")])
9322 (define_insn "*stmsi3"
9323 [(match_parallel 0 "store_multiple_operation"
9324 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9325 (match_operand:SI 2 "gpc_reg_operand" "r"))
9326 (clobber (match_scratch:SI 3 "=X"))
9327 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9328 (match_operand:SI 4 "gpc_reg_operand" "r"))
9329 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9330 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9331 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9332 "{stsi|stswi} %2,%1,%O0"
9333 [(set_attr "type" "store_ux")])
9335 (define_insn "*stmsi8_power"
9336 [(match_parallel 0 "store_multiple_operation"
9337 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9338 (match_operand:SI 2 "gpc_reg_operand" "r"))
9339 (clobber (match_scratch:SI 3 "=q"))
9340 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9341 (match_operand:SI 4 "gpc_reg_operand" "r"))
9342 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9343 (match_operand:SI 5 "gpc_reg_operand" "r"))
9344 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9345 (match_operand:SI 6 "gpc_reg_operand" "r"))
9346 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9347 (match_operand:SI 7 "gpc_reg_operand" "r"))
9348 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9349 (match_operand:SI 8 "gpc_reg_operand" "r"))
9350 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9351 (match_operand:SI 9 "gpc_reg_operand" "r"))
9352 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9353 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9354 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9355 "{stsi|stswi} %2,%1,%O0"
9356 [(set_attr "type" "store_ux")])
9358 (define_insn "*stmsi7_power"
9359 [(match_parallel 0 "store_multiple_operation"
9360 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9361 (match_operand:SI 2 "gpc_reg_operand" "r"))
9362 (clobber (match_scratch:SI 3 "=q"))
9363 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9364 (match_operand:SI 4 "gpc_reg_operand" "r"))
9365 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9366 (match_operand:SI 5 "gpc_reg_operand" "r"))
9367 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9368 (match_operand:SI 6 "gpc_reg_operand" "r"))
9369 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9370 (match_operand:SI 7 "gpc_reg_operand" "r"))
9371 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9372 (match_operand:SI 8 "gpc_reg_operand" "r"))
9373 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9374 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9375 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9376 "{stsi|stswi} %2,%1,%O0"
9377 [(set_attr "type" "store_ux")])
9379 (define_insn "*stmsi6_power"
9380 [(match_parallel 0 "store_multiple_operation"
9381 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9382 (match_operand:SI 2 "gpc_reg_operand" "r"))
9383 (clobber (match_scratch:SI 3 "=q"))
9384 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9385 (match_operand:SI 4 "gpc_reg_operand" "r"))
9386 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9387 (match_operand:SI 5 "gpc_reg_operand" "r"))
9388 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9389 (match_operand:SI 6 "gpc_reg_operand" "r"))
9390 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9391 (match_operand:SI 7 "gpc_reg_operand" "r"))
9392 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9393 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9394 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9395 "{stsi|stswi} %2,%1,%O0"
9396 [(set_attr "type" "store_ux")])
9398 (define_insn "*stmsi5_power"
9399 [(match_parallel 0 "store_multiple_operation"
9400 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9401 (match_operand:SI 2 "gpc_reg_operand" "r"))
9402 (clobber (match_scratch:SI 3 "=q"))
9403 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9404 (match_operand:SI 4 "gpc_reg_operand" "r"))
9405 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9406 (match_operand:SI 5 "gpc_reg_operand" "r"))
9407 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9408 (match_operand:SI 6 "gpc_reg_operand" "r"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9410 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9411 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9412 "{stsi|stswi} %2,%1,%O0"
9413 [(set_attr "type" "store_ux")])
9415 (define_insn "*stmsi4_power"
9416 [(match_parallel 0 "store_multiple_operation"
9417 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9418 (match_operand:SI 2 "gpc_reg_operand" "r"))
9419 (clobber (match_scratch:SI 3 "=q"))
9420 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9421 (match_operand:SI 4 "gpc_reg_operand" "r"))
9422 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9423 (match_operand:SI 5 "gpc_reg_operand" "r"))
9424 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9425 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9426 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9427 "{stsi|stswi} %2,%1,%O0"
9428 [(set_attr "type" "store_ux")])
9430 (define_insn "*stmsi3_power"
9431 [(match_parallel 0 "store_multiple_operation"
9432 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9433 (match_operand:SI 2 "gpc_reg_operand" "r"))
9434 (clobber (match_scratch:SI 3 "=q"))
9435 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9436 (match_operand:SI 4 "gpc_reg_operand" "r"))
9437 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9438 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9439 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9440 "{stsi|stswi} %2,%1,%O0"
9441 [(set_attr "type" "store_ux")])
9442 \f
9443 (define_expand "setmemsi"
9444 [(parallel [(set (match_operand:BLK 0 "" "")
9445 (match_operand 2 "const_int_operand" ""))
9446 (use (match_operand:SI 1 "" ""))
9447 (use (match_operand:SI 3 "" ""))])]
9448 ""
9449 "
9450 {
9451 /* If value to set is not zero, use the library routine. */
9452 if (operands[2] != const0_rtx)
9453 FAIL;
9455 if (expand_block_clear (operands))
9456 DONE;
9457 else
9458 FAIL;
9459 }")
9461 ;; String/block move insn.
9462 ;; Argument 0 is the destination
9463 ;; Argument 1 is the source
9464 ;; Argument 2 is the length
9465 ;; Argument 3 is the alignment
9467 (define_expand "movmemsi"
9468 [(parallel [(set (match_operand:BLK 0 "" "")
9469 (match_operand:BLK 1 "" ""))
9470 (use (match_operand:SI 2 "" ""))
9471 (use (match_operand:SI 3 "" ""))])]
9472 ""
9473 "
9474 {
9475 if (expand_block_move (operands))
9476 DONE;
9477 else
9478 FAIL;
9479 }")
9481 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9482 ;; register allocator doesn't have a clue about allocating 8 word registers.
9483 ;; rD/rS = r5 is preferred, efficient form.
9484 (define_expand "movmemsi_8reg"
9485 [(parallel [(set (match_operand 0 "" "")
9486 (match_operand 1 "" ""))
9487 (use (match_operand 2 "" ""))
9488 (use (match_operand 3 "" ""))
9489 (clobber (reg:SI 5))
9490 (clobber (reg:SI 6))
9491 (clobber (reg:SI 7))
9492 (clobber (reg:SI 8))
9493 (clobber (reg:SI 9))
9494 (clobber (reg:SI 10))
9495 (clobber (reg:SI 11))
9496 (clobber (reg:SI 12))
9497 (clobber (match_scratch:SI 4 ""))])]
9498 "TARGET_STRING"
9499 "")
9501 (define_insn ""
9502 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9503 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9504 (use (match_operand:SI 2 "immediate_operand" "i"))
9505 (use (match_operand:SI 3 "immediate_operand" "i"))
9506 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9507 (clobber (reg:SI 6))
9508 (clobber (reg:SI 7))
9509 (clobber (reg:SI 8))
9510 (clobber (reg:SI 9))
9511 (clobber (reg:SI 10))
9512 (clobber (reg:SI 11))
9513 (clobber (reg:SI 12))
9514 (clobber (match_scratch:SI 5 "=q"))]
9515 "TARGET_STRING && TARGET_POWER
9516 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9517 || INTVAL (operands[2]) == 0)
9518 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9519 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9520 && REGNO (operands[4]) == 5"
9521 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9522 [(set_attr "type" "store_ux")
9523 (set_attr "length" "8")])
9525 (define_insn ""
9526 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9527 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9528 (use (match_operand:SI 2 "immediate_operand" "i"))
9529 (use (match_operand:SI 3 "immediate_operand" "i"))
9530 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9531 (clobber (reg:SI 6))
9532 (clobber (reg:SI 7))
9533 (clobber (reg:SI 8))
9534 (clobber (reg:SI 9))
9535 (clobber (reg:SI 10))
9536 (clobber (reg:SI 11))
9537 (clobber (reg:SI 12))
9538 (clobber (match_scratch:SI 5 "=X"))]
9539 "TARGET_STRING && ! TARGET_POWER
9540 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9541 || INTVAL (operands[2]) == 0)
9542 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9543 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9544 && REGNO (operands[4]) == 5"
9545 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9546 [(set_attr "type" "store_ux")
9547 (set_attr "length" "8")])
9549 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9550 ;; register allocator doesn't have a clue about allocating 6 word registers.
9551 ;; rD/rS = r5 is preferred, efficient form.
9552 (define_expand "movmemsi_6reg"
9553 [(parallel [(set (match_operand 0 "" "")
9554 (match_operand 1 "" ""))
9555 (use (match_operand 2 "" ""))
9556 (use (match_operand 3 "" ""))
9557 (clobber (reg:SI 5))
9558 (clobber (reg:SI 6))
9559 (clobber (reg:SI 7))
9560 (clobber (reg:SI 8))
9561 (clobber (reg:SI 9))
9562 (clobber (reg:SI 10))
9563 (clobber (match_scratch:SI 4 ""))])]
9564 "TARGET_STRING"
9565 "")
9567 (define_insn ""
9568 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9569 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9570 (use (match_operand:SI 2 "immediate_operand" "i"))
9571 (use (match_operand:SI 3 "immediate_operand" "i"))
9572 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9573 (clobber (reg:SI 6))
9574 (clobber (reg:SI 7))
9575 (clobber (reg:SI 8))
9576 (clobber (reg:SI 9))
9577 (clobber (reg:SI 10))
9578 (clobber (match_scratch:SI 5 "=q"))]
9579 "TARGET_STRING && TARGET_POWER
9580 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9581 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9582 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9583 && REGNO (operands[4]) == 5"
9584 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9585 [(set_attr "type" "store_ux")
9586 (set_attr "length" "8")])
9588 (define_insn ""
9589 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9590 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9591 (use (match_operand:SI 2 "immediate_operand" "i"))
9592 (use (match_operand:SI 3 "immediate_operand" "i"))
9593 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9594 (clobber (reg:SI 6))
9595 (clobber (reg:SI 7))
9596 (clobber (reg:SI 8))
9597 (clobber (reg:SI 9))
9598 (clobber (reg:SI 10))
9599 (clobber (match_scratch:SI 5 "=X"))]
9600 "TARGET_STRING && ! TARGET_POWER
9601 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9602 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9603 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9604 && REGNO (operands[4]) == 5"
9605 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9606 [(set_attr "type" "store_ux")
9607 (set_attr "length" "8")])
9609 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9610 ;; problems with TImode.
9611 ;; rD/rS = r5 is preferred, efficient form.
9612 (define_expand "movmemsi_4reg"
9613 [(parallel [(set (match_operand 0 "" "")
9614 (match_operand 1 "" ""))
9615 (use (match_operand 2 "" ""))
9616 (use (match_operand 3 "" ""))
9617 (clobber (reg:SI 5))
9618 (clobber (reg:SI 6))
9619 (clobber (reg:SI 7))
9620 (clobber (reg:SI 8))
9621 (clobber (match_scratch:SI 4 ""))])]
9622 "TARGET_STRING"
9623 "")
9625 (define_insn ""
9626 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9627 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9628 (use (match_operand:SI 2 "immediate_operand" "i"))
9629 (use (match_operand:SI 3 "immediate_operand" "i"))
9630 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9631 (clobber (reg:SI 6))
9632 (clobber (reg:SI 7))
9633 (clobber (reg:SI 8))
9634 (clobber (match_scratch:SI 5 "=q"))]
9635 "TARGET_STRING && TARGET_POWER
9636 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9637 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9638 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9639 && REGNO (operands[4]) == 5"
9640 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9641 [(set_attr "type" "store_ux")
9642 (set_attr "length" "8")])
9644 (define_insn ""
9645 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9646 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9647 (use (match_operand:SI 2 "immediate_operand" "i"))
9648 (use (match_operand:SI 3 "immediate_operand" "i"))
9649 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9650 (clobber (reg:SI 6))
9651 (clobber (reg:SI 7))
9652 (clobber (reg:SI 8))
9653 (clobber (match_scratch:SI 5 "=X"))]
9654 "TARGET_STRING && ! TARGET_POWER
9655 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9656 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9657 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9658 && REGNO (operands[4]) == 5"
9659 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9660 [(set_attr "type" "store_ux")
9661 (set_attr "length" "8")])
9663 ;; Move up to 8 bytes at a time.
9664 (define_expand "movmemsi_2reg"
9665 [(parallel [(set (match_operand 0 "" "")
9666 (match_operand 1 "" ""))
9667 (use (match_operand 2 "" ""))
9668 (use (match_operand 3 "" ""))
9669 (clobber (match_scratch:DI 4 ""))
9670 (clobber (match_scratch:SI 5 ""))])]
9671 "TARGET_STRING && ! TARGET_POWERPC64"
9672 "")
9674 (define_insn ""
9675 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9676 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9677 (use (match_operand:SI 2 "immediate_operand" "i"))
9678 (use (match_operand:SI 3 "immediate_operand" "i"))
9679 (clobber (match_scratch:DI 4 "=&r"))
9680 (clobber (match_scratch:SI 5 "=q"))]
9681 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9682 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9683 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9684 [(set_attr "type" "store_ux")
9685 (set_attr "length" "8")])
9687 (define_insn ""
9688 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9689 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9690 (use (match_operand:SI 2 "immediate_operand" "i"))
9691 (use (match_operand:SI 3 "immediate_operand" "i"))
9692 (clobber (match_scratch:DI 4 "=&r"))
9693 (clobber (match_scratch:SI 5 "=X"))]
9694 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9695 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9696 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9697 [(set_attr "type" "store_ux")
9698 (set_attr "length" "8")])
9700 ;; Move up to 4 bytes at a time.
9701 (define_expand "movmemsi_1reg"
9702 [(parallel [(set (match_operand 0 "" "")
9703 (match_operand 1 "" ""))
9704 (use (match_operand 2 "" ""))
9705 (use (match_operand 3 "" ""))
9706 (clobber (match_scratch:SI 4 ""))
9707 (clobber (match_scratch:SI 5 ""))])]
9708 "TARGET_STRING"
9709 "")
9711 (define_insn ""
9712 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9713 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9714 (use (match_operand:SI 2 "immediate_operand" "i"))
9715 (use (match_operand:SI 3 "immediate_operand" "i"))
9716 (clobber (match_scratch:SI 4 "=&r"))
9717 (clobber (match_scratch:SI 5 "=q"))]
9718 "TARGET_STRING && TARGET_POWER
9719 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9720 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9721 [(set_attr "type" "store_ux")
9722 (set_attr "length" "8")])
9724 (define_insn ""
9725 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9726 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9727 (use (match_operand:SI 2 "immediate_operand" "i"))
9728 (use (match_operand:SI 3 "immediate_operand" "i"))
9729 (clobber (match_scratch:SI 4 "=&r"))
9730 (clobber (match_scratch:SI 5 "=X"))]
9731 "TARGET_STRING && ! TARGET_POWER
9732 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9733 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9734 [(set_attr "type" "store_ux")
9735 (set_attr "length" "8")])
9736 \f
9737 ;; Define insns that do load or store with update. Some of these we can
9738 ;; get by using pre-decrement or pre-increment, but the hardware can also
9739 ;; do cases where the increment is not the size of the object.
9740 ;;
9741 ;; In all these cases, we use operands 0 and 1 for the register being
9742 ;; incremented because those are the operands that local-alloc will
9743 ;; tie and these are the pair most likely to be tieable (and the ones
9744 ;; that will benefit the most).
9746 (define_insn "*movdi_update1"
9747 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9748 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9749 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9750 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9751 (plus:DI (match_dup 1) (match_dup 2)))]
9752 "TARGET_POWERPC64 && TARGET_UPDATE"
9753 "@
9754 ldux %3,%0,%2
9755 ldu %3,%2(%0)"
9756 [(set_attr "type" "load_ux,load_u")])
9758 (define_insn "movdi_<mode>_update"
9759 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9760 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9761 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9762 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9763 (plus:P (match_dup 1) (match_dup 2)))]
9764 "TARGET_POWERPC64 && TARGET_UPDATE"
9765 "@
9766 stdux %3,%0,%2
9767 stdu %3,%2(%0)"
9768 [(set_attr "type" "store_ux,store_u")])
9770 (define_insn "*movsi_update1"
9771 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9772 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9773 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9774 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9775 (plus:SI (match_dup 1) (match_dup 2)))]
9776 "TARGET_UPDATE"
9777 "@
9778 {lux|lwzux} %3,%0,%2
9779 {lu|lwzu} %3,%2(%0)"
9780 [(set_attr "type" "load_ux,load_u")])
9782 (define_insn "*movsi_update2"
9783 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9784 (sign_extend:DI
9785 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9786 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9787 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9788 (plus:DI (match_dup 1) (match_dup 2)))]
9789 "TARGET_POWERPC64"
9790 "lwaux %3,%0,%2"
9791 [(set_attr "type" "load_ext_ux")])
9793 (define_insn "movsi_update"
9794 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9795 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9796 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9797 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9798 (plus:SI (match_dup 1) (match_dup 2)))]
9799 "TARGET_UPDATE"
9800 "@
9801 {stux|stwux} %3,%0,%2
9802 {stu|stwu} %3,%2(%0)"
9803 [(set_attr "type" "store_ux,store_u")])
9805 (define_insn "*movhi_update1"
9806 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9807 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9808 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9809 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9810 (plus:SI (match_dup 1) (match_dup 2)))]
9811 "TARGET_UPDATE"
9812 "@
9813 lhzux %3,%0,%2
9814 lhzu %3,%2(%0)"
9815 [(set_attr "type" "load_ux,load_u")])
9817 (define_insn "*movhi_update2"
9818 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9819 (zero_extend:SI
9820 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9821 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9822 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9823 (plus:SI (match_dup 1) (match_dup 2)))]
9824 "TARGET_UPDATE"
9825 "@
9826 lhzux %3,%0,%2
9827 lhzu %3,%2(%0)"
9828 [(set_attr "type" "load_ux,load_u")])
9830 (define_insn "*movhi_update3"
9831 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9832 (sign_extend:SI
9833 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9834 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9835 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9836 (plus:SI (match_dup 1) (match_dup 2)))]
9837 "TARGET_UPDATE"
9838 "@
9839 lhaux %3,%0,%2
9840 lhau %3,%2(%0)"
9841 [(set_attr "type" "load_ext_ux,load_ext_u")])
9843 (define_insn "*movhi_update4"
9844 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9845 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9846 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9847 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9848 (plus:SI (match_dup 1) (match_dup 2)))]
9849 "TARGET_UPDATE"
9850 "@
9851 sthux %3,%0,%2
9852 sthu %3,%2(%0)"
9853 [(set_attr "type" "store_ux,store_u")])
9855 (define_insn "*movqi_update1"
9856 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9857 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9858 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9859 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9860 (plus:SI (match_dup 1) (match_dup 2)))]
9861 "TARGET_UPDATE"
9862 "@
9863 lbzux %3,%0,%2
9864 lbzu %3,%2(%0)"
9865 [(set_attr "type" "load_ux,load_u")])
9867 (define_insn "*movqi_update2"
9868 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9869 (zero_extend:SI
9870 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9871 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9872 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9873 (plus:SI (match_dup 1) (match_dup 2)))]
9874 "TARGET_UPDATE"
9875 "@
9876 lbzux %3,%0,%2
9877 lbzu %3,%2(%0)"
9878 [(set_attr "type" "load_ux,load_u")])
9880 (define_insn "*movqi_update3"
9881 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9882 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9883 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9884 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9885 (plus:SI (match_dup 1) (match_dup 2)))]
9886 "TARGET_UPDATE"
9887 "@
9888 stbux %3,%0,%2
9889 stbu %3,%2(%0)"
9890 [(set_attr "type" "store_ux,store_u")])
9892 (define_insn "*movsf_update1"
9893 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9894 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9895 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9896 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9897 (plus:SI (match_dup 1) (match_dup 2)))]
9898 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9899 "@
9900 lfsux %3,%0,%2
9901 lfsu %3,%2(%0)"
9902 [(set_attr "type" "fpload_ux,fpload_u")])
9904 (define_insn "*movsf_update2"
9905 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9906 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9907 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9908 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9909 (plus:SI (match_dup 1) (match_dup 2)))]
9910 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9911 "@
9912 stfsux %3,%0,%2
9913 stfsu %3,%2(%0)"
9914 [(set_attr "type" "fpstore_ux,fpstore_u")])
9916 (define_insn "*movsf_update3"
9917 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9918 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9919 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9920 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9921 (plus:SI (match_dup 1) (match_dup 2)))]
9922 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9923 "@
9924 {lux|lwzux} %3,%0,%2
9925 {lu|lwzu} %3,%2(%0)"
9926 [(set_attr "type" "load_ux,load_u")])
9928 (define_insn "*movsf_update4"
9929 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9930 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9931 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9932 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9933 (plus:SI (match_dup 1) (match_dup 2)))]
9934 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9935 "@
9936 {stux|stwux} %3,%0,%2
9937 {stu|stwu} %3,%2(%0)"
9938 [(set_attr "type" "store_ux,store_u")])
9940 (define_insn "*movdf_update1"
9941 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9942 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9943 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9944 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9945 (plus:SI (match_dup 1) (match_dup 2)))]
9946 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9947 "@
9948 lfdux %3,%0,%2
9949 lfdu %3,%2(%0)"
9950 [(set_attr "type" "fpload_ux,fpload_u")])
9952 (define_insn "*movdf_update2"
9953 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9954 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9955 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9956 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9957 (plus:SI (match_dup 1) (match_dup 2)))]
9958 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9959 "@
9960 stfdux %3,%0,%2
9961 stfdu %3,%2(%0)"
9962 [(set_attr "type" "fpstore_ux,fpstore_u")])
9964 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9966 (define_insn "*lfq_power2"
9967 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9968 (match_operand:V2DF 1 "memory_operand" ""))]
9969 "TARGET_POWER2
9970 && TARGET_HARD_FLOAT && TARGET_FPRS"
9971 "lfq%U1%X1 %0,%1")
9973 (define_peephole2
9974 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9975 (match_operand:DF 1 "memory_operand" ""))
9976 (set (match_operand:DF 2 "gpc_reg_operand" "")
9977 (match_operand:DF 3 "memory_operand" ""))]
9978 "TARGET_POWER2
9979 && TARGET_HARD_FLOAT && TARGET_FPRS
9980 && registers_ok_for_quad_peep (operands[0], operands[2])
9981 && mems_ok_for_quad_peep (operands[1], operands[3])"
9982 [(set (match_dup 0)
9983 (match_dup 1))]
9984 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9985 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9987 (define_insn "*stfq_power2"
9988 [(set (match_operand:V2DF 0 "memory_operand" "")
9989 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9990 "TARGET_POWER2
9991 && TARGET_HARD_FLOAT && TARGET_FPRS"
9992 "stfq%U0%X0 %1,%0")
9995 (define_peephole2
9996 [(set (match_operand:DF 0 "memory_operand" "")
9997 (match_operand:DF 1 "gpc_reg_operand" ""))
9998 (set (match_operand:DF 2 "memory_operand" "")
9999 (match_operand:DF 3 "gpc_reg_operand" ""))]
10000 "TARGET_POWER2
10001 && TARGET_HARD_FLOAT && TARGET_FPRS
10002 && registers_ok_for_quad_peep (operands[1], operands[3])
10003 && mems_ok_for_quad_peep (operands[0], operands[2])"
10004 [(set (match_dup 0)
10005 (match_dup 1))]
10006 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10007 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10009 ;; After inserting conditional returns we can sometimes have
10010 ;; unnecessary register moves. Unfortunately we cannot have a
10011 ;; modeless peephole here, because some single SImode sets have early
10012 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10013 ;; sequences, using get_attr_length here will smash the operands
10014 ;; array. Neither is there an early_cobbler_p predicate.
10015 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10016 (define_peephole2
10017 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10018 (match_operand:DF 1 "any_operand" ""))
10019 (set (match_operand:DF 2 "gpc_reg_operand" "")
10020 (match_dup 0))]
10021 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10022 && peep2_reg_dead_p (2, operands[0])"
10023 [(set (match_dup 2) (match_dup 1))])
10025 (define_peephole2
10026 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10027 (match_operand:SF 1 "any_operand" ""))
10028 (set (match_operand:SF 2 "gpc_reg_operand" "")
10029 (match_dup 0))]
10030 "peep2_reg_dead_p (2, operands[0])"
10031 [(set (match_dup 2) (match_dup 1))])
10033 \f
10034 ;; TLS support.
10036 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10037 (define_insn "tls_gd_32"
10038 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10039 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10040 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10041 UNSPEC_TLSGD))]
10042 "HAVE_AS_TLS && !TARGET_64BIT"
10043 "addi %0,%1,%2@got@tlsgd")
10045 (define_insn "tls_gd_64"
10046 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10047 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10048 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10049 UNSPEC_TLSGD))]
10050 "HAVE_AS_TLS && TARGET_64BIT"
10051 "addi %0,%1,%2@got@tlsgd")
10053 (define_insn "tls_ld_32"
10054 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10055 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10056 UNSPEC_TLSLD))]
10057 "HAVE_AS_TLS && !TARGET_64BIT"
10058 "addi %0,%1,%&@got@tlsld")
10060 (define_insn "tls_ld_64"
10061 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10062 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10063 UNSPEC_TLSLD))]
10064 "HAVE_AS_TLS && TARGET_64BIT"
10065 "addi %0,%1,%&@got@tlsld")
10067 (define_insn "tls_dtprel_32"
10068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10069 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10070 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10071 UNSPEC_TLSDTPREL))]
10072 "HAVE_AS_TLS && !TARGET_64BIT"
10073 "addi %0,%1,%2@dtprel")
10075 (define_insn "tls_dtprel_64"
10076 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10077 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10078 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10079 UNSPEC_TLSDTPREL))]
10080 "HAVE_AS_TLS && TARGET_64BIT"
10081 "addi %0,%1,%2@dtprel")
10083 (define_insn "tls_dtprel_ha_32"
10084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10085 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10086 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10087 UNSPEC_TLSDTPRELHA))]
10088 "HAVE_AS_TLS && !TARGET_64BIT"
10089 "addis %0,%1,%2@dtprel@ha")
10091 (define_insn "tls_dtprel_ha_64"
10092 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10093 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10094 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10095 UNSPEC_TLSDTPRELHA))]
10096 "HAVE_AS_TLS && TARGET_64BIT"
10097 "addis %0,%1,%2@dtprel@ha")
10099 (define_insn "tls_dtprel_lo_32"
10100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10101 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10102 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10103 UNSPEC_TLSDTPRELLO))]
10104 "HAVE_AS_TLS && !TARGET_64BIT"
10105 "addi %0,%1,%2@dtprel@l")
10107 (define_insn "tls_dtprel_lo_64"
10108 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10109 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10110 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10111 UNSPEC_TLSDTPRELLO))]
10112 "HAVE_AS_TLS && TARGET_64BIT"
10113 "addi %0,%1,%2@dtprel@l")
10115 (define_insn "tls_got_dtprel_32"
10116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10117 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10118 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10119 UNSPEC_TLSGOTDTPREL))]
10120 "HAVE_AS_TLS && !TARGET_64BIT"
10121 "lwz %0,%2@got@dtprel(%1)")
10123 (define_insn "tls_got_dtprel_64"
10124 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10125 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10126 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10127 UNSPEC_TLSGOTDTPREL))]
10128 "HAVE_AS_TLS && TARGET_64BIT"
10129 "ld %0,%2@got@dtprel(%1)")
10131 (define_insn "tls_tprel_32"
10132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10133 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10134 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10135 UNSPEC_TLSTPREL))]
10136 "HAVE_AS_TLS && !TARGET_64BIT"
10137 "addi %0,%1,%2@tprel")
10139 (define_insn "tls_tprel_64"
10140 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10141 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10142 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10143 UNSPEC_TLSTPREL))]
10144 "HAVE_AS_TLS && TARGET_64BIT"
10145 "addi %0,%1,%2@tprel")
10147 (define_insn "tls_tprel_ha_32"
10148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10149 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10150 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10151 UNSPEC_TLSTPRELHA))]
10152 "HAVE_AS_TLS && !TARGET_64BIT"
10153 "addis %0,%1,%2@tprel@ha")
10155 (define_insn "tls_tprel_ha_64"
10156 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10157 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10158 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10159 UNSPEC_TLSTPRELHA))]
10160 "HAVE_AS_TLS && TARGET_64BIT"
10161 "addis %0,%1,%2@tprel@ha")
10163 (define_insn "tls_tprel_lo_32"
10164 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10165 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10166 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10167 UNSPEC_TLSTPRELLO))]
10168 "HAVE_AS_TLS && !TARGET_64BIT"
10169 "addi %0,%1,%2@tprel@l")
10171 (define_insn "tls_tprel_lo_64"
10172 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10173 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10174 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10175 UNSPEC_TLSTPRELLO))]
10176 "HAVE_AS_TLS && TARGET_64BIT"
10177 "addi %0,%1,%2@tprel@l")
10179 ;; "b" output constraint here and on tls_tls input to support linker tls
10180 ;; optimization. The linker may edit the instructions emitted by a
10181 ;; tls_got_tprel/tls_tls pair to addis,addi.
10182 (define_insn "tls_got_tprel_32"
10183 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10184 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10185 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10186 UNSPEC_TLSGOTTPREL))]
10187 "HAVE_AS_TLS && !TARGET_64BIT"
10188 "lwz %0,%2@got@tprel(%1)")
10190 (define_insn "tls_got_tprel_64"
10191 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10192 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10193 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10194 UNSPEC_TLSGOTTPREL))]
10195 "HAVE_AS_TLS && TARGET_64BIT"
10196 "ld %0,%2@got@tprel(%1)")
10198 (define_insn "tls_tls_32"
10199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10200 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10201 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10202 UNSPEC_TLSTLS))]
10203 "HAVE_AS_TLS && !TARGET_64BIT"
10204 "add %0,%1,%2@tls")
10206 (define_insn "tls_tls_64"
10207 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10208 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10209 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10210 UNSPEC_TLSTLS))]
10211 "HAVE_AS_TLS && TARGET_64BIT"
10212 "add %0,%1,%2@tls")
10213 \f
10214 ;; Next come insns related to the calling sequence.
10215 ;;
10216 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10217 ;; We move the back-chain and decrement the stack pointer.
10219 (define_expand "allocate_stack"
10220 [(set (match_operand 0 "gpc_reg_operand" "=r")
10221 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10222 (set (reg 1)
10223 (minus (reg 1) (match_dup 1)))]
10224 ""
10225 "
10226 { rtx chain = gen_reg_rtx (Pmode);
10227 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10228 rtx neg_op0;
10230 emit_move_insn (chain, stack_bot);
10232 /* Check stack bounds if necessary. */
10233 if (current_function_limit_stack)
10234 {
10235 rtx available;
10236 available = expand_binop (Pmode, sub_optab,
10237 stack_pointer_rtx, stack_limit_rtx,
10238 NULL_RTX, 1, OPTAB_WIDEN);
10239 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10240 }
10242 if (GET_CODE (operands[1]) != CONST_INT
10243 || INTVAL (operands[1]) < -32767
10244 || INTVAL (operands[1]) > 32768)
10245 {
10246 neg_op0 = gen_reg_rtx (Pmode);
10247 if (TARGET_32BIT)
10248 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10249 else
10250 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10251 }
10252 else
10253 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10255 if (TARGET_UPDATE)
10256 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10257 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10259 else
10260 {
10261 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10262 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10263 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10264 }
10266 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10267 DONE;
10268 }")
10270 ;; These patterns say how to save and restore the stack pointer. We need not
10271 ;; save the stack pointer at function level since we are careful to
10272 ;; preserve the backchain. At block level, we have to restore the backchain
10273 ;; when we restore the stack pointer.
10274 ;;
10275 ;; For nonlocal gotos, we must save both the stack pointer and its
10276 ;; backchain and restore both. Note that in the nonlocal case, the
10277 ;; save area is a memory location.
10279 (define_expand "save_stack_function"
10280 [(match_operand 0 "any_operand" "")
10281 (match_operand 1 "any_operand" "")]
10282 ""
10283 "DONE;")
10285 (define_expand "restore_stack_function"
10286 [(match_operand 0 "any_operand" "")
10287 (match_operand 1 "any_operand" "")]
10288 ""
10289 "DONE;")
10291 ;; Adjust stack pointer (op0) to a new value (op1).
10292 ;; First copy old stack backchain to new location, and ensure that the
10293 ;; scheduler won't reorder the sp assignment before the backchain write.
10294 (define_expand "restore_stack_block"
10295 [(set (match_dup 2) (match_dup 3))
10296 (set (match_dup 4) (match_dup 2))
10297 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10298 (set (match_operand 0 "register_operand" "")
10299 (match_operand 1 "register_operand" ""))]
10300 ""
10301 "
10302 {
10303 operands[2] = gen_reg_rtx (Pmode);
10304 operands[3] = gen_frame_mem (Pmode, operands[0]);
10305 operands[4] = gen_frame_mem (Pmode, operands[1]);
10306 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10307 }")
10309 (define_expand "save_stack_nonlocal"
10310 [(set (match_dup 3) (match_dup 4))
10311 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10312 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10313 ""
10314 "
10315 {
10316 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10318 /* Copy the backchain to the first word, sp to the second. */
10319 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10320 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10321 operands[3] = gen_reg_rtx (Pmode);
10322 operands[4] = gen_frame_mem (Pmode, operands[1]);
10323 }")
10325 (define_expand "restore_stack_nonlocal"
10326 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10327 (set (match_dup 3) (match_dup 4))
10328 (set (match_dup 5) (match_dup 2))
10329 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10330 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10331 ""
10332 "
10333 {
10334 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10336 /* Restore the backchain from the first word, sp from the second. */
10337 operands[2] = gen_reg_rtx (Pmode);
10338 operands[3] = gen_reg_rtx (Pmode);
10339 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10340 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10341 operands[5] = gen_frame_mem (Pmode, operands[3]);
10342 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10343 }")
10344 \f
10345 ;; TOC register handling.
10347 ;; Code to initialize the TOC register...
10349 (define_insn "load_toc_aix_si"
10350 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10351 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10352 (use (reg:SI 2))])]
10353 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10354 "*
10355 {
10356 char buf[30];
10357 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10358 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10359 operands[2] = gen_rtx_REG (Pmode, 2);
10360 return \"{l|lwz} %0,%1(%2)\";
10361 }"
10362 [(set_attr "type" "load")])
10364 (define_insn "load_toc_aix_di"
10365 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10366 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10367 (use (reg:DI 2))])]
10368 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10369 "*
10370 {
10371 char buf[30];
10372 #ifdef TARGET_RELOCATABLE
10373 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10374 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10375 #else
10376 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10377 #endif
10378 if (TARGET_ELF)
10379 strcat (buf, \"@toc\");
10380 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10381 operands[2] = gen_rtx_REG (Pmode, 2);
10382 return \"ld %0,%1(%2)\";
10383 }"
10384 [(set_attr "type" "load")])
10386 (define_insn "load_toc_v4_pic_si"
10387 [(set (match_operand:SI 0 "register_operand" "=l")
10388 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10389 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10390 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10391 [(set_attr "type" "branch")
10392 (set_attr "length" "4")])
10394 (define_insn "load_toc_v4_PIC_1"
10395 [(set (match_operand:SI 0 "register_operand" "=l")
10396 (match_operand:SI 1 "immediate_operand" "s"))
10397 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10398 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10399 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10400 "bcl 20,31,%1\\n%1:"
10401 [(set_attr "type" "branch")
10402 (set_attr "length" "4")])
10404 (define_insn "load_toc_v4_PIC_1b"
10405 [(set (match_operand:SI 0 "register_operand" "=l")
10406 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10407 UNSPEC_TOCPTR))]
10408 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10409 "bcl 20,31,$+8\\n\\t.long %1-$"
10410 [(set_attr "type" "branch")
10411 (set_attr "length" "8")])
10413 (define_insn "load_toc_v4_PIC_2"
10414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10415 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10416 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10417 (match_operand:SI 3 "immediate_operand" "s")))))]
10418 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10419 "{l|lwz} %0,%2-%3(%1)"
10420 [(set_attr "type" "load")])
10422 (define_insn "load_toc_v4_PIC_3b"
10423 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10424 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10425 (high:SI
10426 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10427 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10428 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10429 "{cau|addis} %0,%1,%2-%3@ha")
10431 (define_insn "load_toc_v4_PIC_3c"
10432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10433 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10434 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10435 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10436 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10437 "{cal|addi} %0,%1,%2-%3@l")
10439 ;; If the TOC is shared over a translation unit, as happens with all
10440 ;; the kinds of PIC that we support, we need to restore the TOC
10441 ;; pointer only when jumping over units of translation.
10442 ;; On Darwin, we need to reload the picbase.
10444 (define_expand "builtin_setjmp_receiver"
10445 [(use (label_ref (match_operand 0 "" "")))]
10446 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10447 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10448 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10449 "
10450 {
10451 #if TARGET_MACHO
10452 if (DEFAULT_ABI == ABI_DARWIN)
10453 {
10454 const char *picbase = machopic_function_base_name ();
10455 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10456 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10457 rtx tmplabrtx;
10458 char tmplab[20];
10460 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10461 CODE_LABEL_NUMBER (operands[0]));
10462 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10464 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10465 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10466 }
10467 else
10468 #endif
10469 rs6000_emit_load_toc_table (FALSE);
10470 DONE;
10471 }")
10473 ;; Elf specific ways of loading addresses for non-PIC code.
10474 ;; The output of this could be r0, but we make a very strong
10475 ;; preference for a base register because it will usually
10476 ;; be needed there.
10477 (define_insn "elf_high"
10478 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10479 (high:SI (match_operand 1 "" "")))]
10480 "TARGET_ELF && ! TARGET_64BIT"
10481 "{liu|lis} %0,%1@ha")
10483 (define_insn "elf_low"
10484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10485 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10486 (match_operand 2 "" "")))]
10487 "TARGET_ELF && ! TARGET_64BIT"
10488 "@
10489 {cal|la} %0,%2@l(%1)
10490 {ai|addic} %0,%1,%K2")
10491 \f
10492 ;; A function pointer under AIX is a pointer to a data area whose first word
10493 ;; contains the actual address of the function, whose second word contains a
10494 ;; pointer to its TOC, and whose third word contains a value to place in the
10495 ;; static chain register (r11). Note that if we load the static chain, our
10496 ;; "trampoline" need not have any executable code.
10498 (define_expand "call_indirect_aix32"
10499 [(set (match_dup 2)
10500 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10501 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10502 (reg:SI 2))
10503 (set (reg:SI 2)
10504 (mem:SI (plus:SI (match_dup 0)
10505 (const_int 4))))
10506 (set (reg:SI 11)
10507 (mem:SI (plus:SI (match_dup 0)
10508 (const_int 8))))
10509 (parallel [(call (mem:SI (match_dup 2))
10510 (match_operand 1 "" ""))
10511 (use (reg:SI 2))
10512 (use (reg:SI 11))
10513 (set (reg:SI 2)
10514 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10515 (clobber (scratch:SI))])]
10516 "TARGET_32BIT"
10517 "
10518 { operands[2] = gen_reg_rtx (SImode); }")
10520 (define_expand "call_indirect_aix64"
10521 [(set (match_dup 2)
10522 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10523 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10524 (reg:DI 2))
10525 (set (reg:DI 2)
10526 (mem:DI (plus:DI (match_dup 0)
10527 (const_int 8))))
10528 (set (reg:DI 11)
10529 (mem:DI (plus:DI (match_dup 0)
10530 (const_int 16))))
10531 (parallel [(call (mem:SI (match_dup 2))
10532 (match_operand 1 "" ""))
10533 (use (reg:DI 2))
10534 (use (reg:DI 11))
10535 (set (reg:DI 2)
10536 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10537 (clobber (scratch:SI))])]
10538 "TARGET_64BIT"
10539 "
10540 { operands[2] = gen_reg_rtx (DImode); }")
10542 (define_expand "call_value_indirect_aix32"
10543 [(set (match_dup 3)
10544 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10545 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10546 (reg:SI 2))
10547 (set (reg:SI 2)
10548 (mem:SI (plus:SI (match_dup 1)
10549 (const_int 4))))
10550 (set (reg:SI 11)
10551 (mem:SI (plus:SI (match_dup 1)
10552 (const_int 8))))
10553 (parallel [(set (match_operand 0 "" "")
10554 (call (mem:SI (match_dup 3))
10555 (match_operand 2 "" "")))
10556 (use (reg:SI 2))
10557 (use (reg:SI 11))
10558 (set (reg:SI 2)
10559 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10560 (clobber (scratch:SI))])]
10561 "TARGET_32BIT"
10562 "
10563 { operands[3] = gen_reg_rtx (SImode); }")
10565 (define_expand "call_value_indirect_aix64"
10566 [(set (match_dup 3)
10567 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10568 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10569 (reg:DI 2))
10570 (set (reg:DI 2)
10571 (mem:DI (plus:DI (match_dup 1)
10572 (const_int 8))))
10573 (set (reg:DI 11)
10574 (mem:DI (plus:DI (match_dup 1)
10575 (const_int 16))))
10576 (parallel [(set (match_operand 0 "" "")
10577 (call (mem:SI (match_dup 3))
10578 (match_operand 2 "" "")))
10579 (use (reg:DI 2))
10580 (use (reg:DI 11))
10581 (set (reg:DI 2)
10582 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10583 (clobber (scratch:SI))])]
10584 "TARGET_64BIT"
10585 "
10586 { operands[3] = gen_reg_rtx (DImode); }")
10588 ;; Now the definitions for the call and call_value insns
10589 (define_expand "call"
10590 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10591 (match_operand 1 "" ""))
10592 (use (match_operand 2 "" ""))
10593 (clobber (scratch:SI))])]
10594 ""
10595 "
10596 {
10597 #if TARGET_MACHO
10598 if (MACHOPIC_INDIRECT)
10599 operands[0] = machopic_indirect_call_target (operands[0]);
10600 #endif
10602 gcc_assert (GET_CODE (operands[0]) == MEM);
10603 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10605 operands[0] = XEXP (operands[0], 0);
10607 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10608 && flag_pic
10609 && GET_CODE (operands[0]) == SYMBOL_REF
10610 && !SYMBOL_REF_LOCAL_P (operands[0]))
10611 {
10612 rtx call;
10613 rtvec tmp;
10615 tmp = gen_rtvec (3,
10616 gen_rtx_CALL (VOIDmode,
10617 gen_rtx_MEM (SImode, operands[0]),
10618 operands[1]),
10619 gen_rtx_USE (VOIDmode, operands[2]),
10620 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10621 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10622 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10623 DONE;
10624 }
10626 if (GET_CODE (operands[0]) != SYMBOL_REF
10627 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10628 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10629 {
10630 if (INTVAL (operands[2]) & CALL_LONG)
10631 operands[0] = rs6000_longcall_ref (operands[0]);
10633 switch (DEFAULT_ABI)
10634 {
10635 case ABI_V4:
10636 case ABI_DARWIN:
10637 operands[0] = force_reg (Pmode, operands[0]);
10638 break;
10640 case ABI_AIX:
10641 /* AIX function pointers are really pointers to a three word
10642 area. */
10643 emit_call_insn (TARGET_32BIT
10644 ? gen_call_indirect_aix32 (force_reg (SImode,
10645 operands[0]),
10646 operands[1])
10647 : gen_call_indirect_aix64 (force_reg (DImode,
10648 operands[0]),
10649 operands[1]));
10650 DONE;
10652 default:
10653 gcc_unreachable ();
10654 }
10655 }
10656 }")
10658 (define_expand "call_value"
10659 [(parallel [(set (match_operand 0 "" "")
10660 (call (mem:SI (match_operand 1 "address_operand" ""))
10661 (match_operand 2 "" "")))
10662 (use (match_operand 3 "" ""))
10663 (clobber (scratch:SI))])]
10664 ""
10665 "
10666 {
10667 #if TARGET_MACHO
10668 if (MACHOPIC_INDIRECT)
10669 operands[1] = machopic_indirect_call_target (operands[1]);
10670 #endif
10672 gcc_assert (GET_CODE (operands[1]) == MEM);
10673 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10675 operands[1] = XEXP (operands[1], 0);
10677 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10678 && flag_pic
10679 && GET_CODE (operands[1]) == SYMBOL_REF
10680 && !SYMBOL_REF_LOCAL_P (operands[1]))
10681 {
10682 rtx call;
10683 rtvec tmp;
10685 tmp = gen_rtvec (3,
10686 gen_rtx_SET (VOIDmode,
10687 operands[0],
10688 gen_rtx_CALL (VOIDmode,
10689 gen_rtx_MEM (SImode,
10690 operands[1]),
10691 operands[2])),
10692 gen_rtx_USE (VOIDmode, operands[3]),
10693 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10694 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10695 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10696 DONE;
10697 }
10699 if (GET_CODE (operands[1]) != SYMBOL_REF
10700 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10701 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10702 {
10703 if (INTVAL (operands[3]) & CALL_LONG)
10704 operands[1] = rs6000_longcall_ref (operands[1]);
10706 switch (DEFAULT_ABI)
10707 {
10708 case ABI_V4:
10709 case ABI_DARWIN:
10710 operands[1] = force_reg (Pmode, operands[1]);
10711 break;
10713 case ABI_AIX:
10714 /* AIX function pointers are really pointers to a three word
10715 area. */
10716 emit_call_insn (TARGET_32BIT
10717 ? gen_call_value_indirect_aix32 (operands[0],
10718 force_reg (SImode,
10719 operands[1]),
10720 operands[2])
10721 : gen_call_value_indirect_aix64 (operands[0],
10722 force_reg (DImode,
10723 operands[1]),
10724 operands[2]));
10725 DONE;
10727 default:
10728 gcc_unreachable ();
10729 }
10730 }
10731 }")
10733 ;; Call to function in current module. No TOC pointer reload needed.
10734 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10735 ;; either the function was not prototyped, or it was prototyped as a
10736 ;; variable argument function. It is > 0 if FP registers were passed
10737 ;; and < 0 if they were not.
10739 (define_insn "*call_local32"
10740 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10741 (match_operand 1 "" "g,g"))
10742 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10743 (clobber (match_scratch:SI 3 "=l,l"))]
10744 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10745 "*
10746 {
10747 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10748 output_asm_insn (\"crxor 6,6,6\", operands);
10750 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10751 output_asm_insn (\"creqv 6,6,6\", operands);
10753 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10754 }"
10755 [(set_attr "type" "branch")
10756 (set_attr "length" "4,8")])
10758 (define_insn "*call_local64"
10759 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10760 (match_operand 1 "" "g,g"))
10761 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10762 (clobber (match_scratch:SI 3 "=l,l"))]
10763 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10764 "*
10765 {
10766 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10767 output_asm_insn (\"crxor 6,6,6\", operands);
10769 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10770 output_asm_insn (\"creqv 6,6,6\", operands);
10772 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10773 }"
10774 [(set_attr "type" "branch")
10775 (set_attr "length" "4,8")])
10777 (define_insn "*call_value_local32"
10778 [(set (match_operand 0 "" "")
10779 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10780 (match_operand 2 "" "g,g")))
10781 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10782 (clobber (match_scratch:SI 4 "=l,l"))]
10783 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10784 "*
10785 {
10786 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10787 output_asm_insn (\"crxor 6,6,6\", operands);
10789 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10790 output_asm_insn (\"creqv 6,6,6\", operands);
10792 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10793 }"
10794 [(set_attr "type" "branch")
10795 (set_attr "length" "4,8")])
10798 (define_insn "*call_value_local64"
10799 [(set (match_operand 0 "" "")
10800 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10801 (match_operand 2 "" "g,g")))
10802 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10803 (clobber (match_scratch:SI 4 "=l,l"))]
10804 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10805 "*
10806 {
10807 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10808 output_asm_insn (\"crxor 6,6,6\", operands);
10810 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10811 output_asm_insn (\"creqv 6,6,6\", operands);
10813 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10814 }"
10815 [(set_attr "type" "branch")
10816 (set_attr "length" "4,8")])
10818 ;; Call to function which may be in another module. Restore the TOC
10819 ;; pointer (r2) after the call unless this is System V.
10820 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10821 ;; either the function was not prototyped, or it was prototyped as a
10822 ;; variable argument function. It is > 0 if FP registers were passed
10823 ;; and < 0 if they were not.
10825 (define_insn "*call_indirect_nonlocal_aix32"
10826 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10827 (match_operand 1 "" "g,g"))
10828 (use (reg:SI 2))
10829 (use (reg:SI 11))
10830 (set (reg:SI 2)
10831 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10832 (clobber (match_scratch:SI 2 "=l,l"))]
10833 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10834 "b%T0l\;{l|lwz} 2,20(1)"
10835 [(set_attr "type" "jmpreg")
10836 (set_attr "length" "8")])
10838 (define_insn "*call_nonlocal_aix32"
10839 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10840 (match_operand 1 "" "g"))
10841 (use (match_operand:SI 2 "immediate_operand" "O"))
10842 (clobber (match_scratch:SI 3 "=l"))]
10843 "TARGET_32BIT
10844 && DEFAULT_ABI == ABI_AIX
10845 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10846 "bl %z0\;%."
10847 [(set_attr "type" "branch")
10848 (set_attr "length" "8")])
10850 (define_insn "*call_indirect_nonlocal_aix64"
10851 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10852 (match_operand 1 "" "g,g"))
10853 (use (reg:DI 2))
10854 (use (reg:DI 11))
10855 (set (reg:DI 2)
10856 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10857 (clobber (match_scratch:SI 2 "=l,l"))]
10858 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10859 "b%T0l\;ld 2,40(1)"
10860 [(set_attr "type" "jmpreg")
10861 (set_attr "length" "8")])
10863 (define_insn "*call_nonlocal_aix64"
10864 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10865 (match_operand 1 "" "g"))
10866 (use (match_operand:SI 2 "immediate_operand" "O"))
10867 (clobber (match_scratch:SI 3 "=l"))]
10868 "TARGET_64BIT
10869 && DEFAULT_ABI == ABI_AIX
10870 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10871 "bl %z0\;%."
10872 [(set_attr "type" "branch")
10873 (set_attr "length" "8")])
10875 (define_insn "*call_value_indirect_nonlocal_aix32"
10876 [(set (match_operand 0 "" "")
10877 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10878 (match_operand 2 "" "g,g")))
10879 (use (reg:SI 2))
10880 (use (reg:SI 11))
10881 (set (reg:SI 2)
10882 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10883 (clobber (match_scratch:SI 3 "=l,l"))]
10884 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10885 "b%T1l\;{l|lwz} 2,20(1)"
10886 [(set_attr "type" "jmpreg")
10887 (set_attr "length" "8")])
10889 (define_insn "*call_value_nonlocal_aix32"
10890 [(set (match_operand 0 "" "")
10891 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10892 (match_operand 2 "" "g")))
10893 (use (match_operand:SI 3 "immediate_operand" "O"))
10894 (clobber (match_scratch:SI 4 "=l"))]
10895 "TARGET_32BIT
10896 && DEFAULT_ABI == ABI_AIX
10897 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10898 "bl %z1\;%."
10899 [(set_attr "type" "branch")
10900 (set_attr "length" "8")])
10902 (define_insn "*call_value_indirect_nonlocal_aix64"
10903 [(set (match_operand 0 "" "")
10904 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10905 (match_operand 2 "" "g,g")))
10906 (use (reg:DI 2))
10907 (use (reg:DI 11))
10908 (set (reg:DI 2)
10909 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10910 (clobber (match_scratch:SI 3 "=l,l"))]
10911 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10912 "b%T1l\;ld 2,40(1)"
10913 [(set_attr "type" "jmpreg")
10914 (set_attr "length" "8")])
10916 (define_insn "*call_value_nonlocal_aix64"
10917 [(set (match_operand 0 "" "")
10918 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10919 (match_operand 2 "" "g")))
10920 (use (match_operand:SI 3 "immediate_operand" "O"))
10921 (clobber (match_scratch:SI 4 "=l"))]
10922 "TARGET_64BIT
10923 && DEFAULT_ABI == ABI_AIX
10924 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10925 "bl %z1\;%."
10926 [(set_attr "type" "branch")
10927 (set_attr "length" "8")])
10929 ;; A function pointer under System V is just a normal pointer
10930 ;; operands[0] is the function pointer
10931 ;; operands[1] is the stack size to clean up
10932 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10933 ;; which indicates how to set cr1
10935 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10936 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10937 (match_operand 1 "" "g,g,g,g"))
10938 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10939 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10940 "DEFAULT_ABI == ABI_V4
10941 || DEFAULT_ABI == ABI_DARWIN"
10942 {
10943 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10944 output_asm_insn ("crxor 6,6,6", operands);
10946 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10947 output_asm_insn ("creqv 6,6,6", operands);
10949 return "b%T0l";
10950 }
10951 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10952 (set_attr "length" "4,4,8,8")])
10954 (define_insn "*call_nonlocal_sysv<mode>"
10955 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10956 (match_operand 1 "" "g,g"))
10957 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10958 (clobber (match_scratch:SI 3 "=l,l"))]
10959 "(DEFAULT_ABI == ABI_DARWIN
10960 || (DEFAULT_ABI == ABI_V4
10961 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10962 {
10963 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10964 output_asm_insn ("crxor 6,6,6", operands);
10966 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10967 output_asm_insn ("creqv 6,6,6", operands);
10969 #if TARGET_MACHO
10970 return output_call(insn, operands, 0, 2);
10971 #else
10972 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10973 {
10974 if (TARGET_SECURE_PLT && flag_pic == 2)
10975 /* The magic 32768 offset here and in the other sysv call insns
10976 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10977 See sysv4.h:toc_section. */
10978 return "bl %z0+32768@plt";
10979 else
10980 return "bl %z0@plt";
10981 }
10982 else
10983 return "bl %z0";
10984 #endif
10985 }
10986 [(set_attr "type" "branch,branch")
10987 (set_attr "length" "4,8")])
10989 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10990 [(set (match_operand 0 "" "")
10991 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10992 (match_operand 2 "" "g,g,g,g")))
10993 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10994 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10995 "DEFAULT_ABI == ABI_V4
10996 || DEFAULT_ABI == ABI_DARWIN"
10997 {
10998 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10999 output_asm_insn ("crxor 6,6,6", operands);
11001 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11002 output_asm_insn ("creqv 6,6,6", operands);
11004 return "b%T1l";
11005 }
11006 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11007 (set_attr "length" "4,4,8,8")])
11009 (define_insn "*call_value_nonlocal_sysv<mode>"
11010 [(set (match_operand 0 "" "")
11011 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11012 (match_operand 2 "" "g,g")))
11013 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11014 (clobber (match_scratch:SI 4 "=l,l"))]
11015 "(DEFAULT_ABI == ABI_DARWIN
11016 || (DEFAULT_ABI == ABI_V4
11017 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11018 {
11019 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11020 output_asm_insn ("crxor 6,6,6", operands);
11022 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11023 output_asm_insn ("creqv 6,6,6", operands);
11025 #if TARGET_MACHO
11026 return output_call(insn, operands, 1, 3);
11027 #else
11028 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11029 {
11030 if (TARGET_SECURE_PLT && flag_pic == 2)
11031 return "bl %z1+32768@plt";
11032 else
11033 return "bl %z1@plt";
11034 }
11035 else
11036 return "bl %z1";
11037 #endif
11038 }
11039 [(set_attr "type" "branch,branch")
11040 (set_attr "length" "4,8")])
11042 ;; Call subroutine returning any type.
11043 (define_expand "untyped_call"
11044 [(parallel [(call (match_operand 0 "" "")
11045 (const_int 0))
11046 (match_operand 1 "" "")
11047 (match_operand 2 "" "")])]
11048 ""
11049 "
11050 {
11051 int i;
11053 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11055 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11056 {
11057 rtx set = XVECEXP (operands[2], 0, i);
11058 emit_move_insn (SET_DEST (set), SET_SRC (set));
11059 }
11061 /* The optimizer does not know that the call sets the function value
11062 registers we stored in the result block. We avoid problems by
11063 claiming that all hard registers are used and clobbered at this
11064 point. */
11065 emit_insn (gen_blockage ());
11067 DONE;
11068 }")
11070 ;; sibling call patterns
11071 (define_expand "sibcall"
11072 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11073 (match_operand 1 "" ""))
11074 (use (match_operand 2 "" ""))
11075 (use (match_operand 3 "" ""))
11076 (return)])]
11077 ""
11078 "
11079 {
11080 #if TARGET_MACHO
11081 if (MACHOPIC_INDIRECT)
11082 operands[0] = machopic_indirect_call_target (operands[0]);
11083 #endif
11085 gcc_assert (GET_CODE (operands[0]) == MEM);
11086 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11088 operands[0] = XEXP (operands[0], 0);
11089 operands[3] = gen_reg_rtx (SImode);
11091 }")
11093 ;; this and similar patterns must be marked as using LR, otherwise
11094 ;; dataflow will try to delete the store into it. This is true
11095 ;; even when the actual reg to jump to is in CTR, when LR was
11096 ;; saved and restored around the PIC-setting BCL.
11097 (define_insn "*sibcall_local32"
11098 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11099 (match_operand 1 "" "g,g"))
11100 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11101 (use (match_operand:SI 3 "register_operand" "l,l"))
11102 (return)]
11103 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11104 "*
11105 {
11106 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11107 output_asm_insn (\"crxor 6,6,6\", operands);
11109 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11110 output_asm_insn (\"creqv 6,6,6\", operands);
11112 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11113 }"
11114 [(set_attr "type" "branch")
11115 (set_attr "length" "4,8")])
11117 (define_insn "*sibcall_local64"
11118 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11119 (match_operand 1 "" "g,g"))
11120 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11121 (use (match_operand:SI 3 "register_operand" "l,l"))
11122 (return)]
11123 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11124 "*
11125 {
11126 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11127 output_asm_insn (\"crxor 6,6,6\", operands);
11129 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11130 output_asm_insn (\"creqv 6,6,6\", operands);
11132 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11133 }"
11134 [(set_attr "type" "branch")
11135 (set_attr "length" "4,8")])
11137 (define_insn "*sibcall_value_local32"
11138 [(set (match_operand 0 "" "")
11139 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11140 (match_operand 2 "" "g,g")))
11141 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11142 (use (match_operand:SI 4 "register_operand" "l,l"))
11143 (return)]
11144 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11145 "*
11146 {
11147 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11148 output_asm_insn (\"crxor 6,6,6\", operands);
11150 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11151 output_asm_insn (\"creqv 6,6,6\", operands);
11153 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11154 }"
11155 [(set_attr "type" "branch")
11156 (set_attr "length" "4,8")])
11159 (define_insn "*sibcall_value_local64"
11160 [(set (match_operand 0 "" "")
11161 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11162 (match_operand 2 "" "g,g")))
11163 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11164 (use (match_operand:SI 4 "register_operand" "l,l"))
11165 (return)]
11166 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11167 "*
11168 {
11169 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11170 output_asm_insn (\"crxor 6,6,6\", operands);
11172 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11173 output_asm_insn (\"creqv 6,6,6\", operands);
11175 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11176 }"
11177 [(set_attr "type" "branch")
11178 (set_attr "length" "4,8")])
11180 (define_insn "*sibcall_nonlocal_aix32"
11181 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11182 (match_operand 1 "" "g"))
11183 (use (match_operand:SI 2 "immediate_operand" "O"))
11184 (use (match_operand:SI 3 "register_operand" "l"))
11185 (return)]
11186 "TARGET_32BIT
11187 && DEFAULT_ABI == ABI_AIX
11188 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11189 "b %z0"
11190 [(set_attr "type" "branch")
11191 (set_attr "length" "4")])
11193 (define_insn "*sibcall_nonlocal_aix64"
11194 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11195 (match_operand 1 "" "g"))
11196 (use (match_operand:SI 2 "immediate_operand" "O"))
11197 (use (match_operand:SI 3 "register_operand" "l"))
11198 (return)]
11199 "TARGET_64BIT
11200 && DEFAULT_ABI == ABI_AIX
11201 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11202 "b %z0"
11203 [(set_attr "type" "branch")
11204 (set_attr "length" "4")])
11206 (define_insn "*sibcall_value_nonlocal_aix32"
11207 [(set (match_operand 0 "" "")
11208 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11209 (match_operand 2 "" "g")))
11210 (use (match_operand:SI 3 "immediate_operand" "O"))
11211 (use (match_operand:SI 4 "register_operand" "l"))
11212 (return)]
11213 "TARGET_32BIT
11214 && DEFAULT_ABI == ABI_AIX
11215 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11216 "b %z1"
11217 [(set_attr "type" "branch")
11218 (set_attr "length" "4")])
11220 (define_insn "*sibcall_value_nonlocal_aix64"
11221 [(set (match_operand 0 "" "")
11222 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11223 (match_operand 2 "" "g")))
11224 (use (match_operand:SI 3 "immediate_operand" "O"))
11225 (use (match_operand:SI 4 "register_operand" "l"))
11226 (return)]
11227 "TARGET_64BIT
11228 && DEFAULT_ABI == ABI_AIX
11229 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11230 "b %z1"
11231 [(set_attr "type" "branch")
11232 (set_attr "length" "4")])
11234 (define_insn "*sibcall_nonlocal_sysv<mode>"
11235 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11236 (match_operand 1 "" ""))
11237 (use (match_operand 2 "immediate_operand" "O,n"))
11238 (use (match_operand:SI 3 "register_operand" "l,l"))
11239 (return)]
11240 "(DEFAULT_ABI == ABI_DARWIN
11241 || DEFAULT_ABI == ABI_V4)
11242 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11243 "*
11244 {
11245 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11246 output_asm_insn (\"crxor 6,6,6\", operands);
11248 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11249 output_asm_insn (\"creqv 6,6,6\", operands);
11251 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11252 {
11253 if (TARGET_SECURE_PLT && flag_pic == 2)
11254 return \"b %z0+32768@plt\";
11255 else
11256 return \"b %z0@plt\";
11257 }
11258 else
11259 return \"b %z0\";
11260 }"
11261 [(set_attr "type" "branch,branch")
11262 (set_attr "length" "4,8")])
11264 (define_expand "sibcall_value"
11265 [(parallel [(set (match_operand 0 "register_operand" "")
11266 (call (mem:SI (match_operand 1 "address_operand" ""))
11267 (match_operand 2 "" "")))
11268 (use (match_operand 3 "" ""))
11269 (use (match_operand 4 "" ""))
11270 (return)])]
11271 ""
11272 "
11273 {
11274 #if TARGET_MACHO
11275 if (MACHOPIC_INDIRECT)
11276 operands[1] = machopic_indirect_call_target (operands[1]);
11277 #endif
11279 gcc_assert (GET_CODE (operands[1]) == MEM);
11280 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11282 operands[1] = XEXP (operands[1], 0);
11283 operands[4] = gen_reg_rtx (SImode);
11285 }")
11287 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11288 [(set (match_operand 0 "" "")
11289 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11290 (match_operand 2 "" "")))
11291 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11292 (use (match_operand:SI 4 "register_operand" "l,l"))
11293 (return)]
11294 "(DEFAULT_ABI == ABI_DARWIN
11295 || DEFAULT_ABI == ABI_V4)
11296 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11297 "*
11298 {
11299 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11300 output_asm_insn (\"crxor 6,6,6\", operands);
11302 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11303 output_asm_insn (\"creqv 6,6,6\", operands);
11305 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11306 {
11307 if (TARGET_SECURE_PLT && flag_pic == 2)
11308 return \"b %z1+32768@plt\";
11309 else
11310 return \"b %z1@plt\";
11311 }
11312 else
11313 return \"b %z1\";
11314 }"
11315 [(set_attr "type" "branch,branch")
11316 (set_attr "length" "4,8")])
11318 (define_expand "sibcall_epilogue"
11319 [(use (const_int 0))]
11320 "TARGET_SCHED_PROLOG"
11321 "
11322 {
11323 rs6000_emit_epilogue (TRUE);
11324 DONE;
11325 }")
11327 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11328 ;; all of memory. This blocks insns from being moved across this point.
11330 (define_insn "blockage"
11331 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11332 ""
11333 "")
11334 \f
11335 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11336 ;; signed & unsigned, and one type of branch.
11337 ;;
11338 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11339 ;; insns, and branches. We store the operands of compares until we see
11340 ;; how it is used.
11341 (define_expand "cmp<mode>"
11342 [(set (cc0)
11343 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11344 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11345 ""
11346 "
11347 {
11348 /* Take care of the possibility that operands[1] might be negative but
11349 this might be a logical operation. That insn doesn't exist. */
11350 if (GET_CODE (operands[1]) == CONST_INT
11351 && INTVAL (operands[1]) < 0)
11352 operands[1] = force_reg (<MODE>mode, operands[1]);
11354 rs6000_compare_op0 = operands[0];
11355 rs6000_compare_op1 = operands[1];
11356 rs6000_compare_fp_p = 0;
11357 DONE;
11358 }")
11360 (define_expand "cmp<mode>"
11361 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11362 (match_operand:FP 1 "gpc_reg_operand" "")))]
11363 ""
11364 "
11365 {
11366 rs6000_compare_op0 = operands[0];
11367 rs6000_compare_op1 = operands[1];
11368 rs6000_compare_fp_p = 1;
11369 DONE;
11370 }")
11372 (define_expand "beq"
11373 [(use (match_operand 0 "" ""))]
11374 ""
11375 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11377 (define_expand "bne"
11378 [(use (match_operand 0 "" ""))]
11379 ""
11380 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11382 (define_expand "bge"
11383 [(use (match_operand 0 "" ""))]
11384 ""
11385 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11387 (define_expand "bgt"
11388 [(use (match_operand 0 "" ""))]
11389 ""
11390 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11392 (define_expand "ble"
11393 [(use (match_operand 0 "" ""))]
11394 ""
11395 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11397 (define_expand "blt"
11398 [(use (match_operand 0 "" ""))]
11399 ""
11400 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11402 (define_expand "bgeu"
11403 [(use (match_operand 0 "" ""))]
11404 ""
11405 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11407 (define_expand "bgtu"
11408 [(use (match_operand 0 "" ""))]
11409 ""
11410 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11412 (define_expand "bleu"
11413 [(use (match_operand 0 "" ""))]
11414 ""
11415 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11417 (define_expand "bltu"
11418 [(use (match_operand 0 "" ""))]
11419 ""
11420 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11422 (define_expand "bunordered"
11423 [(use (match_operand 0 "" ""))]
11424 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11425 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11427 (define_expand "bordered"
11428 [(use (match_operand 0 "" ""))]
11429 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11430 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11432 (define_expand "buneq"
11433 [(use (match_operand 0 "" ""))]
11434 ""
11435 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11437 (define_expand "bunge"
11438 [(use (match_operand 0 "" ""))]
11439 ""
11440 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11442 (define_expand "bungt"
11443 [(use (match_operand 0 "" ""))]
11444 ""
11445 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11447 (define_expand "bunle"
11448 [(use (match_operand 0 "" ""))]
11449 ""
11450 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11452 (define_expand "bunlt"
11453 [(use (match_operand 0 "" ""))]
11454 ""
11455 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11457 (define_expand "bltgt"
11458 [(use (match_operand 0 "" ""))]
11459 ""
11460 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11462 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11463 ;; For SEQ, likewise, except that comparisons with zero should be done
11464 ;; with an scc insns. However, due to the order that combine see the
11465 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11466 ;; the cases we don't want to handle.
11467 (define_expand "seq"
11468 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11469 ""
11470 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11472 (define_expand "sne"
11473 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11474 ""
11475 "
11476 {
11477 if (! rs6000_compare_fp_p)
11478 FAIL;
11480 rs6000_emit_sCOND (NE, operands[0]);
11481 DONE;
11482 }")
11484 ;; A >= 0 is best done the portable way for A an integer.
11485 (define_expand "sge"
11486 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11487 ""
11488 "
11489 {
11490 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11491 FAIL;
11493 rs6000_emit_sCOND (GE, operands[0]);
11494 DONE;
11495 }")
11497 ;; A > 0 is best done using the portable sequence, so fail in that case.
11498 (define_expand "sgt"
11499 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11500 ""
11501 "
11502 {
11503 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11504 FAIL;
11506 rs6000_emit_sCOND (GT, operands[0]);
11507 DONE;
11508 }")
11510 ;; A <= 0 is best done the portable way for A an integer.
11511 (define_expand "sle"
11512 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11513 ""
11514 "
11515 {
11516 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11517 FAIL;
11519 rs6000_emit_sCOND (LE, operands[0]);
11520 DONE;
11521 }")
11523 ;; A < 0 is best done in the portable way for A an integer.
11524 (define_expand "slt"
11525 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11526 ""
11527 "
11528 {
11529 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11530 FAIL;
11532 rs6000_emit_sCOND (LT, operands[0]);
11533 DONE;
11534 }")
11536 (define_expand "sgeu"
11537 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11538 ""
11539 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11541 (define_expand "sgtu"
11542 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11543 ""
11544 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11546 (define_expand "sleu"
11547 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11548 ""
11549 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11551 (define_expand "sltu"
11552 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11553 ""
11554 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11556 (define_expand "sunordered"
11557 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11558 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11559 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11561 (define_expand "sordered"
11562 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11563 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11564 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11566 (define_expand "suneq"
11567 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11568 ""
11569 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11571 (define_expand "sunge"
11572 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11573 ""
11574 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11576 (define_expand "sungt"
11577 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11578 ""
11579 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11581 (define_expand "sunle"
11582 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11583 ""
11584 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11586 (define_expand "sunlt"
11587 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11588 ""
11589 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11591 (define_expand "sltgt"
11592 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11593 ""
11594 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11596 (define_expand "stack_protect_set"
11597 [(match_operand 0 "memory_operand" "")
11598 (match_operand 1 "memory_operand" "")]
11599 ""
11600 {
11601 #ifdef TARGET_THREAD_SSP_OFFSET
11602 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11603 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11604 operands[1] = gen_rtx_MEM (Pmode, addr);
11605 #endif
11606 if (TARGET_64BIT)
11607 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11608 else
11609 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11610 DONE;
11611 })
11613 (define_insn "stack_protect_setsi"
11614 [(set (match_operand:SI 0 "memory_operand" "=m")
11615 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11616 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11617 "TARGET_32BIT"
11618 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11619 [(set_attr "type" "three")
11620 (set_attr "length" "12")])
11622 (define_insn "stack_protect_setdi"
11623 [(set (match_operand:DI 0 "memory_operand" "=m")
11624 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11625 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11626 "TARGET_64BIT"
11627 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11628 [(set_attr "type" "three")
11629 (set_attr "length" "12")])
11631 (define_expand "stack_protect_test"
11632 [(match_operand 0 "memory_operand" "")
11633 (match_operand 1 "memory_operand" "")
11634 (match_operand 2 "" "")]
11635 ""
11636 {
11637 #ifdef TARGET_THREAD_SSP_OFFSET
11638 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11639 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11640 operands[1] = gen_rtx_MEM (Pmode, addr);
11641 #endif
11642 rs6000_compare_op0 = operands[0];
11643 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11644 UNSPEC_SP_TEST);
11645 rs6000_compare_fp_p = 0;
11646 emit_jump_insn (gen_beq (operands[2]));
11647 DONE;
11648 })
11650 (define_insn "stack_protect_testsi"
11651 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11652 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11653 (match_operand:SI 2 "memory_operand" "m,m")]
11654 UNSPEC_SP_TEST))
11655 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11656 (clobber (match_scratch:SI 3 "=&r,&r"))]
11657 "TARGET_32BIT"
11658 "@
11659 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11660 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11661 [(set_attr "length" "16,20")])
11663 (define_insn "stack_protect_testdi"
11664 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11665 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11666 (match_operand:DI 2 "memory_operand" "m,m")]
11667 UNSPEC_SP_TEST))
11668 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11669 (clobber (match_scratch:DI 3 "=&r,&r"))]
11670 "TARGET_64BIT"
11671 "@
11672 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11673 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11674 [(set_attr "length" "16,20")])
11676 \f
11677 ;; Here are the actual compare insns.
11678 (define_insn "*cmp<mode>_internal1"
11679 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11680 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11681 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11682 ""
11683 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11684 [(set_attr "type" "cmp")])
11686 ;; If we are comparing a register for equality with a large constant,
11687 ;; we can do this with an XOR followed by a compare. But this is profitable
11688 ;; only if the large constant is only used for the comparison (and in this
11689 ;; case we already have a register to reuse as scratch).
11690 ;;
11691 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11692 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11694 (define_peephole2
11695 [(set (match_operand:SI 0 "register_operand")
11696 (match_operand:SI 1 "logical_const_operand" ""))
11697 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11698 [(match_dup 0)
11699 (match_operand:SI 2 "logical_const_operand" "")]))
11700 (set (match_operand:CC 4 "cc_reg_operand" "")
11701 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11702 (match_dup 0)))
11703 (set (pc)
11704 (if_then_else (match_operator 6 "equality_operator"
11705 [(match_dup 4) (const_int 0)])
11706 (match_operand 7 "" "")
11707 (match_operand 8 "" "")))]
11708 "peep2_reg_dead_p (3, operands[0])
11709 && peep2_reg_dead_p (4, operands[4])"
11710 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11711 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11712 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11714 {
11715 /* Get the constant we are comparing against, and see what it looks like
11716 when sign-extended from 16 to 32 bits. Then see what constant we could
11717 XOR with SEXTC to get the sign-extended value. */
11718 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11719 SImode,
11720 operands[1], operands[2]);
11721 HOST_WIDE_INT c = INTVAL (cnst);
11722 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11723 HOST_WIDE_INT xorv = c ^ sextc;
11725 operands[9] = GEN_INT (xorv);
11726 operands[10] = GEN_INT (sextc);
11727 })
11729 (define_insn "*cmpsi_internal2"
11730 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11731 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11732 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11733 ""
11734 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11735 [(set_attr "type" "cmp")])
11737 (define_insn "*cmpdi_internal2"
11738 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11739 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11740 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11741 ""
11742 "cmpld%I2 %0,%1,%b2"
11743 [(set_attr "type" "cmp")])
11745 ;; The following two insns don't exist as single insns, but if we provide
11746 ;; them, we can swap an add and compare, which will enable us to overlap more
11747 ;; of the required delay between a compare and branch. We generate code for
11748 ;; them by splitting.
11750 (define_insn ""
11751 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11752 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11753 (match_operand:SI 2 "short_cint_operand" "i")))
11754 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11755 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11756 ""
11757 "#"
11758 [(set_attr "length" "8")])
11760 (define_insn ""
11761 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11762 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11763 (match_operand:SI 2 "u_short_cint_operand" "i")))
11764 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11765 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11766 ""
11767 "#"
11768 [(set_attr "length" "8")])
11770 (define_split
11771 [(set (match_operand:CC 3 "cc_reg_operand" "")
11772 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11773 (match_operand:SI 2 "short_cint_operand" "")))
11774 (set (match_operand:SI 0 "gpc_reg_operand" "")
11775 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11776 ""
11777 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11778 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11780 (define_split
11781 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11782 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11783 (match_operand:SI 2 "u_short_cint_operand" "")))
11784 (set (match_operand:SI 0 "gpc_reg_operand" "")
11785 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11786 ""
11787 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11788 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11790 (define_insn "*cmpsf_internal1"
11791 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11792 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11793 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11794 "TARGET_HARD_FLOAT && TARGET_FPRS"
11795 "fcmpu %0,%1,%2"
11796 [(set_attr "type" "fpcompare")])
11798 (define_insn "*cmpdf_internal1"
11799 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11800 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11801 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11802 "TARGET_HARD_FLOAT && TARGET_FPRS"
11803 "fcmpu %0,%1,%2"
11804 [(set_attr "type" "fpcompare")])
11806 ;; Only need to compare second words if first words equal
11807 (define_insn "*cmptf_internal1"
11808 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11809 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11810 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11811 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11812 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11813 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11814 [(set_attr "type" "fpcompare")
11815 (set_attr "length" "12")])
11817 (define_insn_and_split "*cmptf_internal2"
11818 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11819 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11820 (match_operand:TF 2 "gpc_reg_operand" "f")))
11821 (clobber (match_scratch:DF 3 "=f"))
11822 (clobber (match_scratch:DF 4 "=f"))
11823 (clobber (match_scratch:DF 5 "=f"))
11824 (clobber (match_scratch:DF 6 "=f"))
11825 (clobber (match_scratch:DF 7 "=f"))
11826 (clobber (match_scratch:DF 8 "=f"))
11827 (clobber (match_scratch:DF 9 "=f"))
11828 (clobber (match_scratch:DF 10 "=f"))]
11829 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11830 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11831 "#"
11832 "&& reload_completed"
11833 [(set (match_dup 3) (match_dup 13))
11834 (set (match_dup 4) (match_dup 14))
11835 (set (match_dup 9) (abs:DF (match_dup 5)))
11836 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11837 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11838 (label_ref (match_dup 11))
11839 (pc)))
11840 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11841 (set (pc) (label_ref (match_dup 12)))
11842 (match_dup 11)
11843 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11844 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11845 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11846 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11847 (match_dup 12)]
11848 {
11849 REAL_VALUE_TYPE rv;
11850 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11851 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11853 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11854 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11855 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11856 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11857 operands[11] = gen_label_rtx ();
11858 operands[12] = gen_label_rtx ();
11859 real_inf (&rv);
11860 operands[13] = force_const_mem (DFmode,
11861 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11862 operands[14] = force_const_mem (DFmode,
11863 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11864 DFmode));
11865 if (TARGET_TOC)
11866 {
11867 operands[13] = gen_const_mem (DFmode,
11868 create_TOC_reference (XEXP (operands[13], 0)));
11869 operands[14] = gen_const_mem (DFmode,
11870 create_TOC_reference (XEXP (operands[14], 0)));
11871 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11872 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11873 }
11874 })
11875 \f
11876 ;; Now we have the scc insns. We can do some combinations because of the
11877 ;; way the machine works.
11878 ;;
11879 ;; Note that this is probably faster if we can put an insn between the
11880 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11881 ;; cases the insns below which don't use an intermediate CR field will
11882 ;; be used instead.
11883 (define_insn ""
11884 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11885 (match_operator:SI 1 "scc_comparison_operator"
11886 [(match_operand 2 "cc_reg_operand" "y")
11887 (const_int 0)]))]
11888 ""
11889 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11890 [(set (attr "type")
11891 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11892 (const_string "mfcrf")
11893 ]
11894 (const_string "mfcr")))
11895 (set_attr "length" "8")])
11897 ;; Same as above, but get the GT bit.
11898 (define_insn "move_from_CR_gt_bit"
11899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11900 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11901 "TARGET_E500"
11902 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11903 [(set_attr "type" "mfcr")
11904 (set_attr "length" "8")])
11906 ;; Same as above, but get the OV/ORDERED bit.
11907 (define_insn "move_from_CR_ov_bit"
11908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11909 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11910 "TARGET_ISEL"
11911 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11912 [(set_attr "type" "mfcr")
11913 (set_attr "length" "8")])
11915 (define_insn ""
11916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11917 (match_operator:DI 1 "scc_comparison_operator"
11918 [(match_operand 2 "cc_reg_operand" "y")
11919 (const_int 0)]))]
11920 "TARGET_POWERPC64"
11921 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11922 [(set (attr "type")
11923 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11924 (const_string "mfcrf")
11925 ]
11926 (const_string "mfcr")))
11927 (set_attr "length" "8")])
11929 (define_insn ""
11930 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11931 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11932 [(match_operand 2 "cc_reg_operand" "y,y")
11933 (const_int 0)])
11934 (const_int 0)))
11935 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11936 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11937 "TARGET_32BIT"
11938 "@
11939 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11940 #"
11941 [(set_attr "type" "delayed_compare")
11942 (set_attr "length" "8,16")])
11944 (define_split
11945 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11946 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11947 [(match_operand 2 "cc_reg_operand" "")
11948 (const_int 0)])
11949 (const_int 0)))
11950 (set (match_operand:SI 3 "gpc_reg_operand" "")
11951 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11952 "TARGET_32BIT && reload_completed"
11953 [(set (match_dup 3)
11954 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11955 (set (match_dup 0)
11956 (compare:CC (match_dup 3)
11957 (const_int 0)))]
11958 "")
11960 (define_insn ""
11961 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11962 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11963 [(match_operand 2 "cc_reg_operand" "y")
11964 (const_int 0)])
11965 (match_operand:SI 3 "const_int_operand" "n")))]
11966 ""
11967 "*
11968 {
11969 int is_bit = ccr_bit (operands[1], 1);
11970 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11971 int count;
11973 if (is_bit >= put_bit)
11974 count = is_bit - put_bit;
11975 else
11976 count = 32 - (put_bit - is_bit);
11978 operands[4] = GEN_INT (count);
11979 operands[5] = GEN_INT (put_bit);
11981 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11982 }"
11983 [(set (attr "type")
11984 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11985 (const_string "mfcrf")
11986 ]
11987 (const_string "mfcr")))
11988 (set_attr "length" "8")])
11990 (define_insn ""
11991 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11992 (compare:CC
11993 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11994 [(match_operand 2 "cc_reg_operand" "y,y")
11995 (const_int 0)])
11996 (match_operand:SI 3 "const_int_operand" "n,n"))
11997 (const_int 0)))
11998 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11999 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12000 (match_dup 3)))]
12001 ""
12002 "*
12003 {
12004 int is_bit = ccr_bit (operands[1], 1);
12005 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12006 int count;
12008 /* Force split for non-cc0 compare. */
12009 if (which_alternative == 1)
12010 return \"#\";
12012 if (is_bit >= put_bit)
12013 count = is_bit - put_bit;
12014 else
12015 count = 32 - (put_bit - is_bit);
12017 operands[5] = GEN_INT (count);
12018 operands[6] = GEN_INT (put_bit);
12020 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12021 }"
12022 [(set_attr "type" "delayed_compare")
12023 (set_attr "length" "8,16")])
12025 (define_split
12026 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12027 (compare:CC
12028 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12029 [(match_operand 2 "cc_reg_operand" "")
12030 (const_int 0)])
12031 (match_operand:SI 3 "const_int_operand" ""))
12032 (const_int 0)))
12033 (set (match_operand:SI 4 "gpc_reg_operand" "")
12034 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12035 (match_dup 3)))]
12036 "reload_completed"
12037 [(set (match_dup 4)
12038 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12039 (match_dup 3)))
12040 (set (match_dup 0)
12041 (compare:CC (match_dup 4)
12042 (const_int 0)))]
12043 "")
12045 ;; There is a 3 cycle delay between consecutive mfcr instructions
12046 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12048 (define_peephole
12049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12050 (match_operator:SI 1 "scc_comparison_operator"
12051 [(match_operand 2 "cc_reg_operand" "y")
12052 (const_int 0)]))
12053 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12054 (match_operator:SI 4 "scc_comparison_operator"
12055 [(match_operand 5 "cc_reg_operand" "y")
12056 (const_int 0)]))]
12057 "REGNO (operands[2]) != REGNO (operands[5])"
12058 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12059 [(set_attr "type" "mfcr")
12060 (set_attr "length" "12")])
12062 (define_peephole
12063 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12064 (match_operator:DI 1 "scc_comparison_operator"
12065 [(match_operand 2 "cc_reg_operand" "y")
12066 (const_int 0)]))
12067 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12068 (match_operator:DI 4 "scc_comparison_operator"
12069 [(match_operand 5 "cc_reg_operand" "y")
12070 (const_int 0)]))]
12071 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12072 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12073 [(set_attr "type" "mfcr")
12074 (set_attr "length" "12")])
12076 ;; There are some scc insns that can be done directly, without a compare.
12077 ;; These are faster because they don't involve the communications between
12078 ;; the FXU and branch units. In fact, we will be replacing all of the
12079 ;; integer scc insns here or in the portable methods in emit_store_flag.
12080 ;;
12081 ;; Also support (neg (scc ..)) since that construct is used to replace
12082 ;; branches, (plus (scc ..) ..) since that construct is common and
12083 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12084 ;; cases where it is no more expensive than (neg (scc ..)).
12086 ;; Have reload force a constant into a register for the simple insns that
12087 ;; otherwise won't accept constants. We do this because it is faster than
12088 ;; the cmp/mfcr sequence we would otherwise generate.
12090 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12091 (DI "rKJI")])
12093 (define_insn_and_split "*eq<mode>"
12094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12095 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12096 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12097 "!TARGET_POWER"
12098 "#"
12099 "!TARGET_POWER"
12100 [(set (match_dup 0)
12101 (clz:GPR (match_dup 3)))
12102 (set (match_dup 0)
12103 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12104 {
12105 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12106 {
12107 /* Use output operand as intermediate. */
12108 operands[3] = operands[0];
12110 if (logical_operand (operands[2], <MODE>mode))
12111 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12112 gen_rtx_XOR (<MODE>mode,
12113 operands[1], operands[2])));
12114 else
12115 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12116 gen_rtx_PLUS (<MODE>mode, operands[1],
12117 negate_rtx (<MODE>mode,
12118 operands[2]))));
12119 }
12120 else
12121 operands[3] = operands[1];
12123 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12124 })
12126 (define_insn_and_split "*eq<mode>_compare"
12127 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12128 (compare:CC
12129 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12130 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12131 (const_int 0)))
12132 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12133 (eq:P (match_dup 1) (match_dup 2)))]
12134 "!TARGET_POWER && optimize_size"
12135 "#"
12136 "!TARGET_POWER && optimize_size"
12137 [(set (match_dup 0)
12138 (clz:P (match_dup 4)))
12139 (parallel [(set (match_dup 3)
12140 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12141 (const_int 0)))
12142 (set (match_dup 0)
12143 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12144 {
12145 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12146 {
12147 /* Use output operand as intermediate. */
12148 operands[4] = operands[0];
12150 if (logical_operand (operands[2], <MODE>mode))
12151 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12152 gen_rtx_XOR (<MODE>mode,
12153 operands[1], operands[2])));
12154 else
12155 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12156 gen_rtx_PLUS (<MODE>mode, operands[1],
12157 negate_rtx (<MODE>mode,
12158 operands[2]))));
12159 }
12160 else
12161 operands[4] = operands[1];
12163 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12164 })
12166 (define_insn "*eqsi_power"
12167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12168 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12169 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12170 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12171 "TARGET_POWER"
12172 "@
12173 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12174 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12175 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12176 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12177 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12178 [(set_attr "type" "three,two,three,three,three")
12179 (set_attr "length" "12,8,12,12,12")])
12181 ;; We have insns of the form shown by the first define_insn below. If
12182 ;; there is something inside the comparison operation, we must split it.
12183 (define_split
12184 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12185 (plus:SI (match_operator 1 "comparison_operator"
12186 [(match_operand:SI 2 "" "")
12187 (match_operand:SI 3
12188 "reg_or_cint_operand" "")])
12189 (match_operand:SI 4 "gpc_reg_operand" "")))
12190 (clobber (match_operand:SI 5 "register_operand" ""))]
12191 "! gpc_reg_operand (operands[2], SImode)"
12192 [(set (match_dup 5) (match_dup 2))
12193 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12194 (match_dup 4)))])
12196 (define_insn "*plus_eqsi"
12197 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12198 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12199 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12200 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12201 "TARGET_32BIT"
12202 "@
12203 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12204 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12205 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12206 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12207 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12208 [(set_attr "type" "three,two,three,three,three")
12209 (set_attr "length" "12,8,12,12,12")])
12211 (define_insn "*compare_plus_eqsi"
12212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12213 (compare:CC
12214 (plus:SI
12215 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12216 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12217 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12218 (const_int 0)))
12219 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12220 "TARGET_32BIT && optimize_size"
12221 "@
12222 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12223 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12224 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12225 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12226 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12227 #
12228 #
12229 #
12230 #
12231 #"
12232 [(set_attr "type" "compare")
12233 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12235 (define_split
12236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12237 (compare:CC
12238 (plus:SI
12239 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12240 (match_operand:SI 2 "scc_eq_operand" ""))
12241 (match_operand:SI 3 "gpc_reg_operand" ""))
12242 (const_int 0)))
12243 (clobber (match_scratch:SI 4 ""))]
12244 "TARGET_32BIT && optimize_size && reload_completed"
12245 [(set (match_dup 4)
12246 (plus:SI (eq:SI (match_dup 1)
12247 (match_dup 2))
12248 (match_dup 3)))
12249 (set (match_dup 0)
12250 (compare:CC (match_dup 4)
12251 (const_int 0)))]
12252 "")
12254 (define_insn "*plus_eqsi_compare"
12255 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12256 (compare:CC
12257 (plus:SI
12258 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12259 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12260 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12261 (const_int 0)))
12262 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12263 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12264 "TARGET_32BIT && optimize_size"
12265 "@
12266 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12267 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12268 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12269 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12270 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12271 #
12272 #
12273 #
12274 #
12275 #"
12276 [(set_attr "type" "compare")
12277 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12279 (define_split
12280 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12281 (compare:CC
12282 (plus:SI
12283 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12284 (match_operand:SI 2 "scc_eq_operand" ""))
12285 (match_operand:SI 3 "gpc_reg_operand" ""))
12286 (const_int 0)))
12287 (set (match_operand:SI 0 "gpc_reg_operand" "")
12288 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12289 "TARGET_32BIT && optimize_size && reload_completed"
12290 [(set (match_dup 0)
12291 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12292 (set (match_dup 4)
12293 (compare:CC (match_dup 0)
12294 (const_int 0)))]
12295 "")
12297 (define_insn "*neg_eq0<mode>"
12298 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12299 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12300 (const_int 0))))]
12301 ""
12302 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12303 [(set_attr "type" "two")
12304 (set_attr "length" "8")])
12306 (define_insn_and_split "*neg_eq<mode>"
12307 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12308 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12309 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12310 ""
12311 "#"
12312 ""
12313 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12314 {
12315 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12316 {
12317 /* Use output operand as intermediate. */
12318 operands[3] = operands[0];
12320 if (logical_operand (operands[2], <MODE>mode))
12321 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12322 gen_rtx_XOR (<MODE>mode,
12323 operands[1], operands[2])));
12324 else
12325 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12326 gen_rtx_PLUS (<MODE>mode, operands[1],
12327 negate_rtx (<MODE>mode,
12328 operands[2]))));
12329 }
12330 else
12331 operands[3] = operands[1];
12332 })
12334 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12335 ;; since it nabs/sr is just as fast.
12336 (define_insn "*ne0si"
12337 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12338 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12339 (const_int 31)))
12340 (clobber (match_scratch:SI 2 "=&r"))]
12341 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12342 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12343 [(set_attr "type" "two")
12344 (set_attr "length" "8")])
12346 (define_insn "*ne0di"
12347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12348 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12349 (const_int 63)))
12350 (clobber (match_scratch:DI 2 "=&r"))]
12351 "TARGET_64BIT"
12352 "addic %2,%1,-1\;subfe %0,%2,%1"
12353 [(set_attr "type" "two")
12354 (set_attr "length" "8")])
12356 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12357 (define_insn "*plus_ne0si"
12358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12359 (plus:SI (lshiftrt:SI
12360 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12361 (const_int 31))
12362 (match_operand:SI 2 "gpc_reg_operand" "r")))
12363 (clobber (match_scratch:SI 3 "=&r"))]
12364 "TARGET_32BIT"
12365 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12366 [(set_attr "type" "two")
12367 (set_attr "length" "8")])
12369 (define_insn "*plus_ne0di"
12370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12371 (plus:DI (lshiftrt:DI
12372 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12373 (const_int 63))
12374 (match_operand:DI 2 "gpc_reg_operand" "r")))
12375 (clobber (match_scratch:DI 3 "=&r"))]
12376 "TARGET_64BIT"
12377 "addic %3,%1,-1\;addze %0,%2"
12378 [(set_attr "type" "two")
12379 (set_attr "length" "8")])
12381 (define_insn "*compare_plus_ne0si"
12382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12383 (compare:CC
12384 (plus:SI (lshiftrt:SI
12385 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12386 (const_int 31))
12387 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12388 (const_int 0)))
12389 (clobber (match_scratch:SI 3 "=&r,&r"))
12390 (clobber (match_scratch:SI 4 "=X,&r"))]
12391 "TARGET_32BIT"
12392 "@
12393 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12394 #"
12395 [(set_attr "type" "compare")
12396 (set_attr "length" "8,12")])
12398 (define_split
12399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (plus:SI (lshiftrt:SI
12402 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12403 (const_int 31))
12404 (match_operand:SI 2 "gpc_reg_operand" ""))
12405 (const_int 0)))
12406 (clobber (match_scratch:SI 3 ""))
12407 (clobber (match_scratch:SI 4 ""))]
12408 "TARGET_32BIT && reload_completed"
12409 [(parallel [(set (match_dup 3)
12410 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12411 (const_int 31))
12412 (match_dup 2)))
12413 (clobber (match_dup 4))])
12414 (set (match_dup 0)
12415 (compare:CC (match_dup 3)
12416 (const_int 0)))]
12417 "")
12419 (define_insn "*compare_plus_ne0di"
12420 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12421 (compare:CC
12422 (plus:DI (lshiftrt:DI
12423 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12424 (const_int 63))
12425 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12426 (const_int 0)))
12427 (clobber (match_scratch:DI 3 "=&r,&r"))]
12428 "TARGET_64BIT"
12429 "@
12430 addic %3,%1,-1\;addze. %3,%2
12431 #"
12432 [(set_attr "type" "compare")
12433 (set_attr "length" "8,12")])
12435 (define_split
12436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12437 (compare:CC
12438 (plus:DI (lshiftrt:DI
12439 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12440 (const_int 63))
12441 (match_operand:DI 2 "gpc_reg_operand" ""))
12442 (const_int 0)))
12443 (clobber (match_scratch:DI 3 ""))]
12444 "TARGET_64BIT && reload_completed"
12445 [(set (match_dup 3)
12446 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12447 (const_int 63))
12448 (match_dup 2)))
12449 (set (match_dup 0)
12450 (compare:CC (match_dup 3)
12451 (const_int 0)))]
12452 "")
12454 (define_insn "*plus_ne0si_compare"
12455 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12456 (compare:CC
12457 (plus:SI (lshiftrt:SI
12458 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12459 (const_int 31))
12460 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12461 (const_int 0)))
12462 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12463 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12464 (match_dup 2)))
12465 (clobber (match_scratch:SI 3 "=&r,&r"))]
12466 "TARGET_32BIT"
12467 "@
12468 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12469 #"
12470 [(set_attr "type" "compare")
12471 (set_attr "length" "8,12")])
12473 (define_split
12474 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12475 (compare:CC
12476 (plus:SI (lshiftrt:SI
12477 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12478 (const_int 31))
12479 (match_operand:SI 2 "gpc_reg_operand" ""))
12480 (const_int 0)))
12481 (set (match_operand:SI 0 "gpc_reg_operand" "")
12482 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12483 (match_dup 2)))
12484 (clobber (match_scratch:SI 3 ""))]
12485 "TARGET_32BIT && reload_completed"
12486 [(parallel [(set (match_dup 0)
12487 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12488 (match_dup 2)))
12489 (clobber (match_dup 3))])
12490 (set (match_dup 4)
12491 (compare:CC (match_dup 0)
12492 (const_int 0)))]
12493 "")
12495 (define_insn "*plus_ne0di_compare"
12496 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12497 (compare:CC
12498 (plus:DI (lshiftrt:DI
12499 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12500 (const_int 63))
12501 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12502 (const_int 0)))
12503 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12504 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12505 (match_dup 2)))
12506 (clobber (match_scratch:DI 3 "=&r,&r"))]
12507 "TARGET_64BIT"
12508 "@
12509 addic %3,%1,-1\;addze. %0,%2
12510 #"
12511 [(set_attr "type" "compare")
12512 (set_attr "length" "8,12")])
12514 (define_split
12515 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12516 (compare:CC
12517 (plus:DI (lshiftrt:DI
12518 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12519 (const_int 63))
12520 (match_operand:DI 2 "gpc_reg_operand" ""))
12521 (const_int 0)))
12522 (set (match_operand:DI 0 "gpc_reg_operand" "")
12523 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12524 (match_dup 2)))
12525 (clobber (match_scratch:DI 3 ""))]
12526 "TARGET_64BIT && reload_completed"
12527 [(parallel [(set (match_dup 0)
12528 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12529 (match_dup 2)))
12530 (clobber (match_dup 3))])
12531 (set (match_dup 4)
12532 (compare:CC (match_dup 0)
12533 (const_int 0)))]
12534 "")
12536 (define_insn ""
12537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12538 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12539 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12540 (clobber (match_scratch:SI 3 "=r,X"))]
12541 "TARGET_POWER"
12542 "@
12543 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12544 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12545 [(set_attr "length" "12")])
12547 (define_insn ""
12548 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12549 (compare:CC
12550 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12551 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12552 (const_int 0)))
12553 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12554 (le:SI (match_dup 1) (match_dup 2)))
12555 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12556 "TARGET_POWER"
12557 "@
12558 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12559 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12560 #
12561 #"
12562 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12563 (set_attr "length" "12,12,16,16")])
12565 (define_split
12566 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12567 (compare:CC
12568 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12569 (match_operand:SI 2 "reg_or_short_operand" ""))
12570 (const_int 0)))
12571 (set (match_operand:SI 0 "gpc_reg_operand" "")
12572 (le:SI (match_dup 1) (match_dup 2)))
12573 (clobber (match_scratch:SI 3 ""))]
12574 "TARGET_POWER && reload_completed"
12575 [(parallel [(set (match_dup 0)
12576 (le:SI (match_dup 1) (match_dup 2)))
12577 (clobber (match_dup 3))])
12578 (set (match_dup 4)
12579 (compare:CC (match_dup 0)
12580 (const_int 0)))]
12581 "")
12583 (define_insn ""
12584 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12585 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12586 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12587 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12588 "TARGET_POWER"
12589 "@
12590 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12591 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12592 [(set_attr "length" "12")])
12594 (define_insn ""
12595 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12596 (compare:CC
12597 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12598 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12599 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12600 (const_int 0)))
12601 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12602 "TARGET_POWER"
12603 "@
12604 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12605 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12606 #
12607 #"
12608 [(set_attr "type" "compare")
12609 (set_attr "length" "12,12,16,16")])
12611 (define_split
12612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12613 (compare:CC
12614 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12615 (match_operand:SI 2 "reg_or_short_operand" ""))
12616 (match_operand:SI 3 "gpc_reg_operand" ""))
12617 (const_int 0)))
12618 (clobber (match_scratch:SI 4 ""))]
12619 "TARGET_POWER && reload_completed"
12620 [(set (match_dup 4)
12621 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12622 (match_dup 3)))
12623 (set (match_dup 0)
12624 (compare:CC (match_dup 4)
12625 (const_int 0)))]
12626 "")
12628 (define_insn ""
12629 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12630 (compare:CC
12631 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12632 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12633 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12634 (const_int 0)))
12635 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12636 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12637 "TARGET_POWER"
12638 "@
12639 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12640 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12641 #
12642 #"
12643 [(set_attr "type" "compare")
12644 (set_attr "length" "12,12,16,16")])
12646 (define_split
12647 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12648 (compare:CC
12649 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12650 (match_operand:SI 2 "reg_or_short_operand" ""))
12651 (match_operand:SI 3 "gpc_reg_operand" ""))
12652 (const_int 0)))
12653 (set (match_operand:SI 0 "gpc_reg_operand" "")
12654 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12655 "TARGET_POWER && reload_completed"
12656 [(set (match_dup 0)
12657 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12658 (set (match_dup 4)
12659 (compare:CC (match_dup 0)
12660 (const_int 0)))]
12661 "")
12663 (define_insn ""
12664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12665 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12666 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12667 "TARGET_POWER"
12668 "@
12669 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12670 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12671 [(set_attr "length" "12")])
12673 (define_insn "*leu<mode>"
12674 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12675 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12676 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12677 ""
12678 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12679 [(set_attr "type" "three")
12680 (set_attr "length" "12")])
12682 (define_insn "*leu<mode>_compare"
12683 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12684 (compare:CC
12685 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12686 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12687 (const_int 0)))
12688 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12689 (leu:P (match_dup 1) (match_dup 2)))]
12690 ""
12691 "@
12692 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12693 #"
12694 [(set_attr "type" "compare")
12695 (set_attr "length" "12,16")])
12697 (define_split
12698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12699 (compare:CC
12700 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12701 (match_operand:P 2 "reg_or_short_operand" ""))
12702 (const_int 0)))
12703 (set (match_operand:P 0 "gpc_reg_operand" "")
12704 (leu:P (match_dup 1) (match_dup 2)))]
12705 "reload_completed"
12706 [(set (match_dup 0)
12707 (leu:P (match_dup 1) (match_dup 2)))
12708 (set (match_dup 3)
12709 (compare:CC (match_dup 0)
12710 (const_int 0)))]
12711 "")
12713 (define_insn "*plus_leu<mode>"
12714 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12715 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12716 (match_operand:P 2 "reg_or_short_operand" "rI"))
12717 (match_operand:P 3 "gpc_reg_operand" "r")))]
12718 ""
12719 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12720 [(set_attr "type" "two")
12721 (set_attr "length" "8")])
12723 (define_insn ""
12724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12725 (compare:CC
12726 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12727 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12728 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12729 (const_int 0)))
12730 (clobber (match_scratch:SI 4 "=&r,&r"))]
12731 "TARGET_32BIT"
12732 "@
12733 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12734 #"
12735 [(set_attr "type" "compare")
12736 (set_attr "length" "8,12")])
12738 (define_split
12739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12740 (compare:CC
12741 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12742 (match_operand:SI 2 "reg_or_short_operand" ""))
12743 (match_operand:SI 3 "gpc_reg_operand" ""))
12744 (const_int 0)))
12745 (clobber (match_scratch:SI 4 ""))]
12746 "TARGET_32BIT && reload_completed"
12747 [(set (match_dup 4)
12748 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12749 (match_dup 3)))
12750 (set (match_dup 0)
12751 (compare:CC (match_dup 4)
12752 (const_int 0)))]
12753 "")
12755 (define_insn ""
12756 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12757 (compare:CC
12758 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12759 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12760 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12761 (const_int 0)))
12762 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12763 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12764 "TARGET_32BIT"
12765 "@
12766 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12767 #"
12768 [(set_attr "type" "compare")
12769 (set_attr "length" "8,12")])
12771 (define_split
12772 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12773 (compare:CC
12774 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12775 (match_operand:SI 2 "reg_or_short_operand" ""))
12776 (match_operand:SI 3 "gpc_reg_operand" ""))
12777 (const_int 0)))
12778 (set (match_operand:SI 0 "gpc_reg_operand" "")
12779 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12780 "TARGET_32BIT && reload_completed"
12781 [(set (match_dup 0)
12782 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12783 (set (match_dup 4)
12784 (compare:CC (match_dup 0)
12785 (const_int 0)))]
12786 "")
12788 (define_insn "*neg_leu<mode>"
12789 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12790 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12791 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12792 ""
12793 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12794 [(set_attr "type" "three")
12795 (set_attr "length" "12")])
12797 (define_insn "*and_neg_leu<mode>"
12798 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12799 (and:P (neg:P
12800 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12801 (match_operand:P 2 "reg_or_short_operand" "rI")))
12802 (match_operand:P 3 "gpc_reg_operand" "r")))]
12803 ""
12804 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12805 [(set_attr "type" "three")
12806 (set_attr "length" "12")])
12808 (define_insn ""
12809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12810 (compare:CC
12811 (and:SI (neg:SI
12812 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12813 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12814 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12815 (const_int 0)))
12816 (clobber (match_scratch:SI 4 "=&r,&r"))]
12817 "TARGET_32BIT"
12818 "@
12819 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12820 #"
12821 [(set_attr "type" "compare")
12822 (set_attr "length" "12,16")])
12824 (define_split
12825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12826 (compare:CC
12827 (and:SI (neg:SI
12828 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12829 (match_operand:SI 2 "reg_or_short_operand" "")))
12830 (match_operand:SI 3 "gpc_reg_operand" ""))
12831 (const_int 0)))
12832 (clobber (match_scratch:SI 4 ""))]
12833 "TARGET_32BIT && reload_completed"
12834 [(set (match_dup 4)
12835 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12836 (match_dup 3)))
12837 (set (match_dup 0)
12838 (compare:CC (match_dup 4)
12839 (const_int 0)))]
12840 "")
12842 (define_insn ""
12843 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12844 (compare:CC
12845 (and:SI (neg:SI
12846 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12847 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12848 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12849 (const_int 0)))
12850 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12851 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12852 "TARGET_32BIT"
12853 "@
12854 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12855 #"
12856 [(set_attr "type" "compare")
12857 (set_attr "length" "12,16")])
12859 (define_split
12860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12861 (compare:CC
12862 (and:SI (neg:SI
12863 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12864 (match_operand:SI 2 "reg_or_short_operand" "")))
12865 (match_operand:SI 3 "gpc_reg_operand" ""))
12866 (const_int 0)))
12867 (set (match_operand:SI 0 "gpc_reg_operand" "")
12868 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12869 "TARGET_32BIT && reload_completed"
12870 [(set (match_dup 0)
12871 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12872 (match_dup 3)))
12873 (set (match_dup 4)
12874 (compare:CC (match_dup 0)
12875 (const_int 0)))]
12876 "")
12878 (define_insn ""
12879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12880 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12881 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12882 "TARGET_POWER"
12883 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12884 [(set_attr "length" "12")])
12886 (define_insn ""
12887 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12888 (compare:CC
12889 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12890 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12891 (const_int 0)))
12892 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12893 (lt:SI (match_dup 1) (match_dup 2)))]
12894 "TARGET_POWER"
12895 "@
12896 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12897 #"
12898 [(set_attr "type" "delayed_compare")
12899 (set_attr "length" "12,16")])
12901 (define_split
12902 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12903 (compare:CC
12904 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12905 (match_operand:SI 2 "reg_or_short_operand" ""))
12906 (const_int 0)))
12907 (set (match_operand:SI 0 "gpc_reg_operand" "")
12908 (lt:SI (match_dup 1) (match_dup 2)))]
12909 "TARGET_POWER && reload_completed"
12910 [(set (match_dup 0)
12911 (lt:SI (match_dup 1) (match_dup 2)))
12912 (set (match_dup 3)
12913 (compare:CC (match_dup 0)
12914 (const_int 0)))]
12915 "")
12917 (define_insn ""
12918 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12919 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12920 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12921 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12922 "TARGET_POWER"
12923 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12924 [(set_attr "length" "12")])
12926 (define_insn ""
12927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12928 (compare:CC
12929 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12930 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12931 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12932 (const_int 0)))
12933 (clobber (match_scratch:SI 4 "=&r,&r"))]
12934 "TARGET_POWER"
12935 "@
12936 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12937 #"
12938 [(set_attr "type" "compare")
12939 (set_attr "length" "12,16")])
12941 (define_split
12942 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12943 (compare:CC
12944 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12945 (match_operand:SI 2 "reg_or_short_operand" ""))
12946 (match_operand:SI 3 "gpc_reg_operand" ""))
12947 (const_int 0)))
12948 (clobber (match_scratch:SI 4 ""))]
12949 "TARGET_POWER && reload_completed"
12950 [(set (match_dup 4)
12951 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12952 (match_dup 3)))
12953 (set (match_dup 0)
12954 (compare:CC (match_dup 4)
12955 (const_int 0)))]
12956 "")
12958 (define_insn ""
12959 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12960 (compare:CC
12961 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12962 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12963 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12964 (const_int 0)))
12965 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12966 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12967 "TARGET_POWER"
12968 "@
12969 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12970 #"
12971 [(set_attr "type" "compare")
12972 (set_attr "length" "12,16")])
12974 (define_split
12975 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12976 (compare:CC
12977 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12978 (match_operand:SI 2 "reg_or_short_operand" ""))
12979 (match_operand:SI 3 "gpc_reg_operand" ""))
12980 (const_int 0)))
12981 (set (match_operand:SI 0 "gpc_reg_operand" "")
12982 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12983 "TARGET_POWER && reload_completed"
12984 [(set (match_dup 0)
12985 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12986 (set (match_dup 4)
12987 (compare:CC (match_dup 0)
12988 (const_int 0)))]
12989 "")
12991 (define_insn ""
12992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12993 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12994 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12995 "TARGET_POWER"
12996 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12997 [(set_attr "length" "12")])
12999 (define_insn_and_split "*ltu<mode>"
13000 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13001 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13002 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13003 ""
13004 "#"
13005 ""
13006 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13007 (set (match_dup 0) (neg:P (match_dup 0)))]
13008 "")
13010 (define_insn_and_split "*ltu<mode>_compare"
13011 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13012 (compare:CC
13013 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13014 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13015 (const_int 0)))
13016 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13017 (ltu:P (match_dup 1) (match_dup 2)))]
13018 ""
13019 "#"
13020 ""
13021 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13022 (parallel [(set (match_dup 3)
13023 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13024 (set (match_dup 0) (neg:P (match_dup 0)))])]
13025 "")
13027 (define_insn_and_split "*plus_ltu<mode>"
13028 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13029 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13030 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13031 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13032 ""
13033 "#"
13034 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13035 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13036 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13037 "")
13039 (define_insn_and_split "*plus_ltu<mode>_compare"
13040 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13041 (compare:CC
13042 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13043 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13044 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13045 (const_int 0)))
13046 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13047 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13048 ""
13049 "#"
13050 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13051 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13052 (parallel [(set (match_dup 4)
13053 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13054 (const_int 0)))
13055 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13056 "")
13058 (define_insn "*neg_ltu<mode>"
13059 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13060 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13061 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13062 ""
13063 "@
13064 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13065 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13066 [(set_attr "type" "two")
13067 (set_attr "length" "8")])
13069 (define_insn ""
13070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13071 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13072 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13073 (clobber (match_scratch:SI 3 "=r"))]
13074 "TARGET_POWER"
13075 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13076 [(set_attr "length" "12")])
13078 (define_insn ""
13079 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13080 (compare:CC
13081 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13082 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13083 (const_int 0)))
13084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13085 (ge:SI (match_dup 1) (match_dup 2)))
13086 (clobber (match_scratch:SI 3 "=r,r"))]
13087 "TARGET_POWER"
13088 "@
13089 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13090 #"
13091 [(set_attr "type" "compare")
13092 (set_attr "length" "12,16")])
13094 (define_split
13095 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13096 (compare:CC
13097 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13098 (match_operand:SI 2 "reg_or_short_operand" ""))
13099 (const_int 0)))
13100 (set (match_operand:SI 0 "gpc_reg_operand" "")
13101 (ge:SI (match_dup 1) (match_dup 2)))
13102 (clobber (match_scratch:SI 3 ""))]
13103 "TARGET_POWER && reload_completed"
13104 [(parallel [(set (match_dup 0)
13105 (ge:SI (match_dup 1) (match_dup 2)))
13106 (clobber (match_dup 3))])
13107 (set (match_dup 4)
13108 (compare:CC (match_dup 0)
13109 (const_int 0)))]
13110 "")
13112 (define_insn ""
13113 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13114 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13115 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13116 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13117 "TARGET_POWER"
13118 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13119 [(set_attr "length" "12")])
13121 (define_insn ""
13122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13123 (compare:CC
13124 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13125 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13126 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13127 (const_int 0)))
13128 (clobber (match_scratch:SI 4 "=&r,&r"))]
13129 "TARGET_POWER"
13130 "@
13131 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13132 #"
13133 [(set_attr "type" "compare")
13134 (set_attr "length" "12,16")])
13136 (define_split
13137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13138 (compare:CC
13139 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13140 (match_operand:SI 2 "reg_or_short_operand" ""))
13141 (match_operand:SI 3 "gpc_reg_operand" ""))
13142 (const_int 0)))
13143 (clobber (match_scratch:SI 4 ""))]
13144 "TARGET_POWER && reload_completed"
13145 [(set (match_dup 4)
13146 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13147 (match_dup 3)))
13148 (set (match_dup 0)
13149 (compare:CC (match_dup 4)
13150 (const_int 0)))]
13151 "")
13153 (define_insn ""
13154 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13155 (compare:CC
13156 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13157 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13158 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13159 (const_int 0)))
13160 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13161 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13162 "TARGET_POWER"
13163 "@
13164 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13165 #"
13166 [(set_attr "type" "compare")
13167 (set_attr "length" "12,16")])
13169 (define_split
13170 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13171 (compare:CC
13172 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13173 (match_operand:SI 2 "reg_or_short_operand" ""))
13174 (match_operand:SI 3 "gpc_reg_operand" ""))
13175 (const_int 0)))
13176 (set (match_operand:SI 0 "gpc_reg_operand" "")
13177 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13178 "TARGET_POWER && reload_completed"
13179 [(set (match_dup 0)
13180 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13181 (set (match_dup 4)
13182 (compare:CC (match_dup 0)
13183 (const_int 0)))]
13184 "")
13186 (define_insn ""
13187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13188 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13189 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13190 "TARGET_POWER"
13191 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13192 [(set_attr "length" "12")])
13194 (define_insn "*geu<mode>"
13195 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13196 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13197 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13198 ""
13199 "@
13200 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13201 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13202 [(set_attr "type" "three")
13203 (set_attr "length" "12")])
13205 (define_insn "*geu<mode>_compare"
13206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13207 (compare:CC
13208 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13209 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13210 (const_int 0)))
13211 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13212 (geu:P (match_dup 1) (match_dup 2)))]
13213 ""
13214 "@
13215 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13216 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13217 #
13218 #"
13219 [(set_attr "type" "compare")
13220 (set_attr "length" "12,12,16,16")])
13222 (define_split
13223 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13224 (compare:CC
13225 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13226 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13227 (const_int 0)))
13228 (set (match_operand:P 0 "gpc_reg_operand" "")
13229 (geu:P (match_dup 1) (match_dup 2)))]
13230 "reload_completed"
13231 [(set (match_dup 0)
13232 (geu:P (match_dup 1) (match_dup 2)))
13233 (set (match_dup 3)
13234 (compare:CC (match_dup 0)
13235 (const_int 0)))]
13236 "")
13238 (define_insn "*plus_geu<mode>"
13239 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13240 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13241 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13242 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13243 ""
13244 "@
13245 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13246 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13247 [(set_attr "type" "two")
13248 (set_attr "length" "8")])
13250 (define_insn ""
13251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13252 (compare:CC
13253 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13254 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13255 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13256 (const_int 0)))
13257 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13258 "TARGET_32BIT"
13259 "@
13260 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13261 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13262 #
13263 #"
13264 [(set_attr "type" "compare")
13265 (set_attr "length" "8,8,12,12")])
13267 (define_split
13268 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13269 (compare:CC
13270 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13271 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13272 (match_operand:SI 3 "gpc_reg_operand" ""))
13273 (const_int 0)))
13274 (clobber (match_scratch:SI 4 ""))]
13275 "TARGET_32BIT && reload_completed"
13276 [(set (match_dup 4)
13277 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13278 (match_dup 3)))
13279 (set (match_dup 0)
13280 (compare:CC (match_dup 4)
13281 (const_int 0)))]
13282 "")
13284 (define_insn ""
13285 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13286 (compare:CC
13287 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13288 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13289 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13290 (const_int 0)))
13291 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13292 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13293 "TARGET_32BIT"
13294 "@
13295 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13296 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13297 #
13298 #"
13299 [(set_attr "type" "compare")
13300 (set_attr "length" "8,8,12,12")])
13302 (define_split
13303 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13304 (compare:CC
13305 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13306 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13307 (match_operand:SI 3 "gpc_reg_operand" ""))
13308 (const_int 0)))
13309 (set (match_operand:SI 0 "gpc_reg_operand" "")
13310 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13311 "TARGET_32BIT && reload_completed"
13312 [(set (match_dup 0)
13313 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13314 (set (match_dup 4)
13315 (compare:CC (match_dup 0)
13316 (const_int 0)))]
13317 "")
13319 (define_insn "*neg_geu<mode>"
13320 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13321 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13322 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13323 ""
13324 "@
13325 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13326 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13327 [(set_attr "type" "three")
13328 (set_attr "length" "12")])
13330 (define_insn "*and_neg_geu<mode>"
13331 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13332 (and:P (neg:P
13333 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13334 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13335 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13336 ""
13337 "@
13338 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13339 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13340 [(set_attr "type" "three")
13341 (set_attr "length" "12")])
13343 (define_insn ""
13344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13345 (compare:CC
13346 (and:SI (neg:SI
13347 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13348 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13349 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13350 (const_int 0)))
13351 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13352 "TARGET_32BIT"
13353 "@
13354 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13355 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13356 #
13357 #"
13358 [(set_attr "type" "compare")
13359 (set_attr "length" "12,12,16,16")])
13361 (define_split
13362 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13363 (compare:CC
13364 (and:SI (neg:SI
13365 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13366 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13367 (match_operand:SI 3 "gpc_reg_operand" ""))
13368 (const_int 0)))
13369 (clobber (match_scratch:SI 4 ""))]
13370 "TARGET_32BIT && reload_completed"
13371 [(set (match_dup 4)
13372 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13373 (match_dup 3)))
13374 (set (match_dup 0)
13375 (compare:CC (match_dup 4)
13376 (const_int 0)))]
13377 "")
13379 (define_insn ""
13380 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13381 (compare:CC
13382 (and:SI (neg:SI
13383 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13384 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13385 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13386 (const_int 0)))
13387 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13388 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13389 "TARGET_32BIT"
13390 "@
13391 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13392 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13393 #
13394 #"
13395 [(set_attr "type" "compare")
13396 (set_attr "length" "12,12,16,16")])
13398 (define_split
13399 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13400 (compare:CC
13401 (and:SI (neg:SI
13402 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13403 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13404 (match_operand:SI 3 "gpc_reg_operand" ""))
13405 (const_int 0)))
13406 (set (match_operand:SI 0 "gpc_reg_operand" "")
13407 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13408 "TARGET_32BIT && reload_completed"
13409 [(set (match_dup 0)
13410 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13411 (set (match_dup 4)
13412 (compare:CC (match_dup 0)
13413 (const_int 0)))]
13414 "")
13416 (define_insn ""
13417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13418 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13419 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13420 "TARGET_POWER"
13421 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13422 [(set_attr "length" "12")])
13424 (define_insn ""
13425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13426 (compare:CC
13427 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13428 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13429 (const_int 0)))
13430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13431 (gt:SI (match_dup 1) (match_dup 2)))]
13432 "TARGET_POWER"
13433 "@
13434 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13435 #"
13436 [(set_attr "type" "delayed_compare")
13437 (set_attr "length" "12,16")])
13439 (define_split
13440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13441 (compare:CC
13442 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13443 (match_operand:SI 2 "reg_or_short_operand" ""))
13444 (const_int 0)))
13445 (set (match_operand:SI 0 "gpc_reg_operand" "")
13446 (gt:SI (match_dup 1) (match_dup 2)))]
13447 "TARGET_POWER && reload_completed"
13448 [(set (match_dup 0)
13449 (gt:SI (match_dup 1) (match_dup 2)))
13450 (set (match_dup 3)
13451 (compare:CC (match_dup 0)
13452 (const_int 0)))]
13453 "")
13455 (define_insn "*plus_gt0<mode>"
13456 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13457 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13458 (const_int 0))
13459 (match_operand:P 2 "gpc_reg_operand" "r")))]
13460 ""
13461 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13462 [(set_attr "type" "three")
13463 (set_attr "length" "12")])
13465 (define_insn ""
13466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13467 (compare:CC
13468 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13469 (const_int 0))
13470 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13471 (const_int 0)))
13472 (clobber (match_scratch:SI 3 "=&r,&r"))]
13473 "TARGET_32BIT"
13474 "@
13475 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13476 #"
13477 [(set_attr "type" "compare")
13478 (set_attr "length" "12,16")])
13480 (define_split
13481 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13482 (compare:CC
13483 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13484 (const_int 0))
13485 (match_operand:SI 2 "gpc_reg_operand" ""))
13486 (const_int 0)))
13487 (clobber (match_scratch:SI 3 ""))]
13488 "TARGET_32BIT && reload_completed"
13489 [(set (match_dup 3)
13490 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13491 (match_dup 2)))
13492 (set (match_dup 0)
13493 (compare:CC (match_dup 3)
13494 (const_int 0)))]
13495 "")
13497 (define_insn ""
13498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13499 (compare:CC
13500 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13501 (const_int 0))
13502 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13503 (const_int 0)))
13504 (clobber (match_scratch:DI 3 "=&r,&r"))]
13505 "TARGET_64BIT"
13506 "@
13507 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13508 #"
13509 [(set_attr "type" "compare")
13510 (set_attr "length" "12,16")])
13512 (define_split
13513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13514 (compare:CC
13515 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13516 (const_int 0))
13517 (match_operand:DI 2 "gpc_reg_operand" ""))
13518 (const_int 0)))
13519 (clobber (match_scratch:DI 3 ""))]
13520 "TARGET_64BIT && reload_completed"
13521 [(set (match_dup 3)
13522 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13523 (match_dup 2)))
13524 (set (match_dup 0)
13525 (compare:CC (match_dup 3)
13526 (const_int 0)))]
13527 "")
13529 (define_insn ""
13530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13531 (compare:CC
13532 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13533 (const_int 0))
13534 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13535 (const_int 0)))
13536 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13537 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13538 "TARGET_32BIT"
13539 "@
13540 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13541 #"
13542 [(set_attr "type" "compare")
13543 (set_attr "length" "12,16")])
13545 (define_split
13546 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13547 (compare:CC
13548 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13549 (const_int 0))
13550 (match_operand:SI 2 "gpc_reg_operand" ""))
13551 (const_int 0)))
13552 (set (match_operand:SI 0 "gpc_reg_operand" "")
13553 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13554 "TARGET_32BIT && reload_completed"
13555 [(set (match_dup 0)
13556 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13557 (set (match_dup 3)
13558 (compare:CC (match_dup 0)
13559 (const_int 0)))]
13560 "")
13562 (define_insn ""
13563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13564 (compare:CC
13565 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13566 (const_int 0))
13567 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13568 (const_int 0)))
13569 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13570 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13571 "TARGET_64BIT"
13572 "@
13573 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13574 #"
13575 [(set_attr "type" "compare")
13576 (set_attr "length" "12,16")])
13578 (define_split
13579 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13580 (compare:CC
13581 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13582 (const_int 0))
13583 (match_operand:DI 2 "gpc_reg_operand" ""))
13584 (const_int 0)))
13585 (set (match_operand:DI 0 "gpc_reg_operand" "")
13586 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13587 "TARGET_64BIT && reload_completed"
13588 [(set (match_dup 0)
13589 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13590 (set (match_dup 3)
13591 (compare:CC (match_dup 0)
13592 (const_int 0)))]
13593 "")
13595 (define_insn ""
13596 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13597 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13598 (match_operand:SI 2 "reg_or_short_operand" "r"))
13599 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13600 "TARGET_POWER"
13601 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13602 [(set_attr "length" "12")])
13604 (define_insn ""
13605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13606 (compare:CC
13607 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13608 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13609 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13610 (const_int 0)))
13611 (clobber (match_scratch:SI 4 "=&r,&r"))]
13612 "TARGET_POWER"
13613 "@
13614 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13615 #"
13616 [(set_attr "type" "compare")
13617 (set_attr "length" "12,16")])
13619 (define_split
13620 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13621 (compare:CC
13622 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13623 (match_operand:SI 2 "reg_or_short_operand" ""))
13624 (match_operand:SI 3 "gpc_reg_operand" ""))
13625 (const_int 0)))
13626 (clobber (match_scratch:SI 4 ""))]
13627 "TARGET_POWER && reload_completed"
13628 [(set (match_dup 4)
13629 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13630 (set (match_dup 0)
13631 (compare:CC (match_dup 4)
13632 (const_int 0)))]
13633 "")
13635 (define_insn ""
13636 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13637 (compare:CC
13638 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13639 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13640 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13641 (const_int 0)))
13642 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13643 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13644 "TARGET_POWER"
13645 "@
13646 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13647 #"
13648 [(set_attr "type" "compare")
13649 (set_attr "length" "12,16")])
13651 (define_split
13652 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13653 (compare:CC
13654 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13655 (match_operand:SI 2 "reg_or_short_operand" ""))
13656 (match_operand:SI 3 "gpc_reg_operand" ""))
13657 (const_int 0)))
13658 (set (match_operand:SI 0 "gpc_reg_operand" "")
13659 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13660 "TARGET_POWER && reload_completed"
13661 [(set (match_dup 0)
13662 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13663 (set (match_dup 4)
13664 (compare:CC (match_dup 0)
13665 (const_int 0)))]
13666 "")
13668 (define_insn ""
13669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13670 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13671 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13672 "TARGET_POWER"
13673 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13674 [(set_attr "length" "12")])
13676 (define_insn_and_split "*gtu<mode>"
13677 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13678 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13679 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13680 ""
13681 "#"
13682 ""
13683 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13684 (set (match_dup 0) (neg:P (match_dup 0)))]
13685 "")
13687 (define_insn_and_split "*gtu<mode>_compare"
13688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13689 (compare:CC
13690 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13691 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13692 (const_int 0)))
13693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13694 (gtu:P (match_dup 1) (match_dup 2)))]
13695 ""
13696 "#"
13697 ""
13698 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13699 (parallel [(set (match_dup 3)
13700 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13701 (set (match_dup 0) (neg:P (match_dup 0)))])]
13702 "")
13704 (define_insn_and_split "*plus_gtu<mode>"
13705 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13706 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13707 (match_operand:P 2 "reg_or_short_operand" "rI"))
13708 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13709 ""
13710 "#"
13711 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13712 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13713 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13714 "")
13716 (define_insn_and_split "*plus_gtu<mode>_compare"
13717 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13718 (compare:CC
13719 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13720 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13721 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13722 (const_int 0)))
13723 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13724 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13725 ""
13726 "#"
13727 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13728 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13729 (parallel [(set (match_dup 4)
13730 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13731 (const_int 0)))
13732 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13733 "")
13735 (define_insn "*neg_gtu<mode>"
13736 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13737 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13738 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13739 ""
13740 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13741 [(set_attr "type" "two")
13742 (set_attr "length" "8")])
13744 \f
13745 ;; Define both directions of branch and return. If we need a reload
13746 ;; register, we'd rather use CR0 since it is much easier to copy a
13747 ;; register CC value to there.
13749 (define_insn ""
13750 [(set (pc)
13751 (if_then_else (match_operator 1 "branch_comparison_operator"
13752 [(match_operand 2
13753 "cc_reg_operand" "y")
13754 (const_int 0)])
13755 (label_ref (match_operand 0 "" ""))
13756 (pc)))]
13757 ""
13758 "*
13759 {
13760 return output_cbranch (operands[1], \"%l0\", 0, insn);
13761 }"
13762 [(set_attr "type" "branch")])
13764 (define_insn ""
13765 [(set (pc)
13766 (if_then_else (match_operator 0 "branch_comparison_operator"
13767 [(match_operand 1
13768 "cc_reg_operand" "y")
13769 (const_int 0)])
13770 (return)
13771 (pc)))]
13772 "direct_return ()"
13773 "*
13774 {
13775 return output_cbranch (operands[0], NULL, 0, insn);
13776 }"
13777 [(set_attr "type" "jmpreg")
13778 (set_attr "length" "4")])
13780 (define_insn ""
13781 [(set (pc)
13782 (if_then_else (match_operator 1 "branch_comparison_operator"
13783 [(match_operand 2
13784 "cc_reg_operand" "y")
13785 (const_int 0)])
13786 (pc)
13787 (label_ref (match_operand 0 "" ""))))]
13788 ""
13789 "*
13790 {
13791 return output_cbranch (operands[1], \"%l0\", 1, insn);
13792 }"
13793 [(set_attr "type" "branch")])
13795 (define_insn ""
13796 [(set (pc)
13797 (if_then_else (match_operator 0 "branch_comparison_operator"
13798 [(match_operand 1
13799 "cc_reg_operand" "y")
13800 (const_int 0)])
13801 (pc)
13802 (return)))]
13803 "direct_return ()"
13804 "*
13805 {
13806 return output_cbranch (operands[0], NULL, 1, insn);
13807 }"
13808 [(set_attr "type" "jmpreg")
13809 (set_attr "length" "4")])
13811 ;; Logic on condition register values.
13813 ; This pattern matches things like
13814 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13815 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13816 ; (const_int 1)))
13817 ; which are generated by the branch logic.
13818 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13820 (define_insn "*cceq_ior_compare"
13821 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13822 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13823 [(match_operator:SI 2
13824 "branch_positive_comparison_operator"
13825 [(match_operand 3
13826 "cc_reg_operand" "y,y")
13827 (const_int 0)])
13828 (match_operator:SI 4
13829 "branch_positive_comparison_operator"
13830 [(match_operand 5
13831 "cc_reg_operand" "0,y")
13832 (const_int 0)])])
13833 (const_int 1)))]
13834 ""
13835 "cr%q1 %E0,%j2,%j4"
13836 [(set_attr "type" "cr_logical,delayed_cr")])
13838 ; Why is the constant -1 here, but 1 in the previous pattern?
13839 ; Because ~1 has all but the low bit set.
13840 (define_insn ""
13841 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13842 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13843 [(not:SI (match_operator:SI 2
13844 "branch_positive_comparison_operator"
13845 [(match_operand 3
13846 "cc_reg_operand" "y,y")
13847 (const_int 0)]))
13848 (match_operator:SI 4
13849 "branch_positive_comparison_operator"
13850 [(match_operand 5
13851 "cc_reg_operand" "0,y")
13852 (const_int 0)])])
13853 (const_int -1)))]
13854 ""
13855 "cr%q1 %E0,%j2,%j4"
13856 [(set_attr "type" "cr_logical,delayed_cr")])
13858 (define_insn "*cceq_rev_compare"
13859 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13860 (compare:CCEQ (match_operator:SI 1
13861 "branch_positive_comparison_operator"
13862 [(match_operand 2
13863 "cc_reg_operand" "0,y")
13864 (const_int 0)])
13865 (const_int 0)))]
13866 ""
13867 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13868 [(set_attr "type" "cr_logical,delayed_cr")])
13870 ;; If we are comparing the result of two comparisons, this can be done
13871 ;; using creqv or crxor.
13873 (define_insn_and_split ""
13874 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13875 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13876 [(match_operand 2 "cc_reg_operand" "y")
13877 (const_int 0)])
13878 (match_operator 3 "branch_comparison_operator"
13879 [(match_operand 4 "cc_reg_operand" "y")
13880 (const_int 0)])))]
13881 ""
13882 "#"
13883 ""
13884 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13885 (match_dup 5)))]
13886 "
13887 {
13888 int positive_1, positive_2;
13890 positive_1 = branch_positive_comparison_operator (operands[1],
13891 GET_MODE (operands[1]));
13892 positive_2 = branch_positive_comparison_operator (operands[3],
13893 GET_MODE (operands[3]));
13895 if (! positive_1)
13896 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13897 GET_CODE (operands[1])),
13898 SImode,
13899 operands[2], const0_rtx);
13900 else if (GET_MODE (operands[1]) != SImode)
13901 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13902 operands[2], const0_rtx);
13904 if (! positive_2)
13905 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13906 GET_CODE (operands[3])),
13907 SImode,
13908 operands[4], const0_rtx);
13909 else if (GET_MODE (operands[3]) != SImode)
13910 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13911 operands[4], const0_rtx);
13913 if (positive_1 == positive_2)
13914 {
13915 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13916 operands[5] = constm1_rtx;
13917 }
13918 else
13919 {
13920 operands[5] = const1_rtx;
13921 }
13922 }")
13924 ;; Unconditional branch and return.
13926 (define_insn "jump"
13927 [(set (pc)
13928 (label_ref (match_operand 0 "" "")))]
13929 ""
13930 "b %l0"
13931 [(set_attr "type" "branch")])
13933 (define_insn "return"
13934 [(return)]
13935 "direct_return ()"
13936 "{br|blr}"
13937 [(set_attr "type" "jmpreg")])
13939 (define_expand "indirect_jump"
13940 [(set (pc) (match_operand 0 "register_operand" ""))])
13942 (define_insn "*indirect_jump<mode>"
13943 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13944 ""
13945 "@
13946 bctr
13947 {br|blr}"
13948 [(set_attr "type" "jmpreg")])
13950 ;; Table jump for switch statements:
13951 (define_expand "tablejump"
13952 [(use (match_operand 0 "" ""))
13953 (use (label_ref (match_operand 1 "" "")))]
13954 ""
13955 "
13956 {
13957 if (TARGET_32BIT)
13958 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13959 else
13960 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13961 DONE;
13962 }")
13964 (define_expand "tablejumpsi"
13965 [(set (match_dup 3)
13966 (plus:SI (match_operand:SI 0 "" "")
13967 (match_dup 2)))
13968 (parallel [(set (pc) (match_dup 3))
13969 (use (label_ref (match_operand 1 "" "")))])]
13970 "TARGET_32BIT"
13971 "
13972 { operands[0] = force_reg (SImode, operands[0]);
13973 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13974 operands[3] = gen_reg_rtx (SImode);
13975 }")
13977 (define_expand "tablejumpdi"
13978 [(set (match_dup 4)
13979 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13980 (set (match_dup 3)
13981 (plus:DI (match_dup 4)
13982 (match_dup 2)))
13983 (parallel [(set (pc) (match_dup 3))
13984 (use (label_ref (match_operand 1 "" "")))])]
13985 "TARGET_64BIT"
13986 "
13987 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13988 operands[3] = gen_reg_rtx (DImode);
13989 operands[4] = gen_reg_rtx (DImode);
13990 }")
13992 (define_insn "*tablejump<mode>_internal1"
13993 [(set (pc)
13994 (match_operand:P 0 "register_operand" "c,*l"))
13995 (use (label_ref (match_operand 1 "" "")))]
13996 ""
13997 "@
13998 bctr
13999 {br|blr}"
14000 [(set_attr "type" "jmpreg")])
14002 (define_insn "nop"
14003 [(const_int 0)]
14004 ""
14005 "{cror 0,0,0|nop}")
14006 \f
14007 ;; Define the subtract-one-and-jump insns, starting with the template
14008 ;; so loop.c knows what to generate.
14010 (define_expand "doloop_end"
14011 [(use (match_operand 0 "" "")) ; loop pseudo
14012 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14013 (use (match_operand 2 "" "")) ; max iterations
14014 (use (match_operand 3 "" "")) ; loop level
14015 (use (match_operand 4 "" ""))] ; label
14016 ""
14017 "
14018 {
14019 /* Only use this on innermost loops. */
14020 if (INTVAL (operands[3]) > 1)
14021 FAIL;
14022 if (TARGET_64BIT)
14023 {
14024 if (GET_MODE (operands[0]) != DImode)
14025 FAIL;
14026 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14027 }
14028 else
14029 {
14030 if (GET_MODE (operands[0]) != SImode)
14031 FAIL;
14032 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14033 }
14034 DONE;
14035 }")
14037 (define_expand "ctr<mode>"
14038 [(parallel [(set (pc)
14039 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14040 (const_int 1))
14041 (label_ref (match_operand 1 "" ""))
14042 (pc)))
14043 (set (match_dup 0)
14044 (plus:P (match_dup 0)
14045 (const_int -1)))
14046 (clobber (match_scratch:CC 2 ""))
14047 (clobber (match_scratch:P 3 ""))])]
14048 ""
14049 "")
14051 ;; We need to be able to do this for any operand, including MEM, or we
14052 ;; will cause reload to blow up since we don't allow output reloads on
14053 ;; JUMP_INSNs.
14054 ;; For the length attribute to be calculated correctly, the
14055 ;; label MUST be operand 0.
14057 (define_insn "*ctr<mode>_internal1"
14058 [(set (pc)
14059 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14060 (const_int 1))
14061 (label_ref (match_operand 0 "" ""))
14062 (pc)))
14063 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14064 (plus:P (match_dup 1)
14065 (const_int -1)))
14066 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14067 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14068 ""
14069 "*
14070 {
14071 if (which_alternative != 0)
14072 return \"#\";
14073 else if (get_attr_length (insn) == 4)
14074 return \"{bdn|bdnz} %l0\";
14075 else
14076 return \"bdz $+8\;b %l0\";
14077 }"
14078 [(set_attr "type" "branch")
14079 (set_attr "length" "*,12,16,16")])
14081 (define_insn "*ctr<mode>_internal2"
14082 [(set (pc)
14083 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14084 (const_int 1))
14085 (pc)
14086 (label_ref (match_operand 0 "" ""))))
14087 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14088 (plus:P (match_dup 1)
14089 (const_int -1)))
14090 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14091 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14092 ""
14093 "*
14094 {
14095 if (which_alternative != 0)
14096 return \"#\";
14097 else if (get_attr_length (insn) == 4)
14098 return \"bdz %l0\";
14099 else
14100 return \"{bdn|bdnz} $+8\;b %l0\";
14101 }"
14102 [(set_attr "type" "branch")
14103 (set_attr "length" "*,12,16,16")])
14105 ;; Similar but use EQ
14107 (define_insn "*ctr<mode>_internal5"
14108 [(set (pc)
14109 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14110 (const_int 1))
14111 (label_ref (match_operand 0 "" ""))
14112 (pc)))
14113 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14114 (plus:P (match_dup 1)
14115 (const_int -1)))
14116 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14117 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14118 ""
14119 "*
14120 {
14121 if (which_alternative != 0)
14122 return \"#\";
14123 else if (get_attr_length (insn) == 4)
14124 return \"bdz %l0\";
14125 else
14126 return \"{bdn|bdnz} $+8\;b %l0\";
14127 }"
14128 [(set_attr "type" "branch")
14129 (set_attr "length" "*,12,16,16")])
14131 (define_insn "*ctr<mode>_internal6"
14132 [(set (pc)
14133 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14134 (const_int 1))
14135 (pc)
14136 (label_ref (match_operand 0 "" ""))))
14137 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14138 (plus:P (match_dup 1)
14139 (const_int -1)))
14140 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14141 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14142 ""
14143 "*
14144 {
14145 if (which_alternative != 0)
14146 return \"#\";
14147 else if (get_attr_length (insn) == 4)
14148 return \"{bdn|bdnz} %l0\";
14149 else
14150 return \"bdz $+8\;b %l0\";
14151 }"
14152 [(set_attr "type" "branch")
14153 (set_attr "length" "*,12,16,16")])
14155 ;; Now the splitters if we could not allocate the CTR register
14157 (define_split
14158 [(set (pc)
14159 (if_then_else (match_operator 2 "comparison_operator"
14160 [(match_operand:P 1 "gpc_reg_operand" "")
14161 (const_int 1)])
14162 (match_operand 5 "" "")
14163 (match_operand 6 "" "")))
14164 (set (match_operand:P 0 "gpc_reg_operand" "")
14165 (plus:P (match_dup 1) (const_int -1)))
14166 (clobber (match_scratch:CC 3 ""))
14167 (clobber (match_scratch:P 4 ""))]
14168 "reload_completed"
14169 [(parallel [(set (match_dup 3)
14170 (compare:CC (plus:P (match_dup 1)
14171 (const_int -1))
14172 (const_int 0)))
14173 (set (match_dup 0)
14174 (plus:P (match_dup 1)
14175 (const_int -1)))])
14176 (set (pc) (if_then_else (match_dup 7)
14177 (match_dup 5)
14178 (match_dup 6)))]
14179 "
14180 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14181 operands[3], const0_rtx); }")
14183 (define_split
14184 [(set (pc)
14185 (if_then_else (match_operator 2 "comparison_operator"
14186 [(match_operand:P 1 "gpc_reg_operand" "")
14187 (const_int 1)])
14188 (match_operand 5 "" "")
14189 (match_operand 6 "" "")))
14190 (set (match_operand:P 0 "nonimmediate_operand" "")
14191 (plus:P (match_dup 1) (const_int -1)))
14192 (clobber (match_scratch:CC 3 ""))
14193 (clobber (match_scratch:P 4 ""))]
14194 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14195 [(parallel [(set (match_dup 3)
14196 (compare:CC (plus:P (match_dup 1)
14197 (const_int -1))
14198 (const_int 0)))
14199 (set (match_dup 4)
14200 (plus:P (match_dup 1)
14201 (const_int -1)))])
14202 (set (match_dup 0)
14203 (match_dup 4))
14204 (set (pc) (if_then_else (match_dup 7)
14205 (match_dup 5)
14206 (match_dup 6)))]
14207 "
14208 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14209 operands[3], const0_rtx); }")
14210 \f
14211 (define_insn "trap"
14212 [(trap_if (const_int 1) (const_int 0))]
14213 ""
14214 "{t 31,0,0|trap}"
14215 [(set_attr "type" "trap")])
14217 (define_expand "conditional_trap"
14218 [(trap_if (match_operator 0 "trap_comparison_operator"
14219 [(match_dup 2) (match_dup 3)])
14220 (match_operand 1 "const_int_operand" ""))]
14221 ""
14222 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14223 operands[2] = rs6000_compare_op0;
14224 operands[3] = rs6000_compare_op1;")
14226 (define_insn ""
14227 [(trap_if (match_operator 0 "trap_comparison_operator"
14228 [(match_operand:GPR 1 "register_operand" "r")
14229 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14230 (const_int 0))]
14231 ""
14232 "{t|t<wd>}%V0%I2 %1,%2"
14233 [(set_attr "type" "trap")])
14234 \f
14235 ;; Insns related to generating the function prologue and epilogue.
14237 (define_expand "prologue"
14238 [(use (const_int 0))]
14239 "TARGET_SCHED_PROLOG"
14240 "
14241 {
14242 rs6000_emit_prologue ();
14243 DONE;
14244 }")
14246 (define_insn "*movesi_from_cr_one"
14247 [(match_parallel 0 "mfcr_operation"
14248 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14249 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14250 (match_operand 3 "immediate_operand" "n")]
14251 UNSPEC_MOVESI_FROM_CR))])]
14252 "TARGET_MFCRF"
14253 "*
14254 {
14255 int mask = 0;
14256 int i;
14257 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14258 {
14259 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14260 operands[4] = GEN_INT (mask);
14261 output_asm_insn (\"mfcr %1,%4\", operands);
14262 }
14263 return \"\";
14264 }"
14265 [(set_attr "type" "mfcrf")])
14267 (define_insn "movesi_from_cr"
14268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14269 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14270 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14271 UNSPEC_MOVESI_FROM_CR))]
14272 ""
14273 "mfcr %0"
14274 [(set_attr "type" "mfcr")])
14276 (define_insn "*stmw"
14277 [(match_parallel 0 "stmw_operation"
14278 [(set (match_operand:SI 1 "memory_operand" "=m")
14279 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14280 "TARGET_MULTIPLE"
14281 "{stm|stmw} %2,%1"
14282 [(set_attr "type" "store_ux")])
14284 (define_insn "*save_fpregs_<mode>"
14285 [(match_parallel 0 "any_parallel_operand"
14286 [(clobber (match_operand:P 1 "register_operand" "=l"))
14287 (use (match_operand:P 2 "call_operand" "s"))
14288 (set (match_operand:DF 3 "memory_operand" "=m")
14289 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14290 ""
14291 "bl %z2"
14292 [(set_attr "type" "branch")
14293 (set_attr "length" "4")])
14295 ; These are to explain that changes to the stack pointer should
14296 ; not be moved over stores to stack memory.
14297 (define_insn "stack_tie"
14298 [(set (match_operand:BLK 0 "memory_operand" "+m")
14299 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14300 ""
14301 ""
14302 [(set_attr "length" "0")])
14305 (define_expand "epilogue"
14306 [(use (const_int 0))]
14307 "TARGET_SCHED_PROLOG"
14308 "
14309 {
14310 rs6000_emit_epilogue (FALSE);
14311 DONE;
14312 }")
14314 ; On some processors, doing the mtcrf one CC register at a time is
14315 ; faster (like on the 604e). On others, doing them all at once is
14316 ; faster; for instance, on the 601 and 750.
14318 (define_expand "movsi_to_cr_one"
14319 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14320 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14321 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14322 ""
14323 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14325 (define_insn "*movsi_to_cr"
14326 [(match_parallel 0 "mtcrf_operation"
14327 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14328 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14329 (match_operand 3 "immediate_operand" "n")]
14330 UNSPEC_MOVESI_TO_CR))])]
14331 ""
14332 "*
14333 {
14334 int mask = 0;
14335 int i;
14336 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14337 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14338 operands[4] = GEN_INT (mask);
14339 return \"mtcrf %4,%2\";
14340 }"
14341 [(set_attr "type" "mtcr")])
14343 (define_insn "*mtcrfsi"
14344 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14345 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14346 (match_operand 2 "immediate_operand" "n")]
14347 UNSPEC_MOVESI_TO_CR))]
14348 "GET_CODE (operands[0]) == REG
14349 && CR_REGNO_P (REGNO (operands[0]))
14350 && GET_CODE (operands[2]) == CONST_INT
14351 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14352 "mtcrf %R0,%1"
14353 [(set_attr "type" "mtcr")])
14355 ; The load-multiple instructions have similar properties.
14356 ; Note that "load_multiple" is a name known to the machine-independent
14357 ; code that actually corresponds to the PowerPC load-string.
14359 (define_insn "*lmw"
14360 [(match_parallel 0 "lmw_operation"
14361 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14362 (match_operand:SI 2 "memory_operand" "m"))])]
14363 "TARGET_MULTIPLE"
14364 "{lm|lmw} %1,%2"
14365 [(set_attr "type" "load_ux")])
14367 (define_insn "*return_internal_<mode>"
14368 [(return)
14369 (use (match_operand:P 0 "register_operand" "lc"))]
14370 ""
14371 "b%T0"
14372 [(set_attr "type" "jmpreg")])
14374 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14375 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14377 (define_insn "*return_and_restore_fpregs_<mode>"
14378 [(match_parallel 0 "any_parallel_operand"
14379 [(return)
14380 (use (match_operand:P 1 "register_operand" "l"))
14381 (use (match_operand:P 2 "call_operand" "s"))
14382 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14383 (match_operand:DF 4 "memory_operand" "m"))])]
14384 ""
14385 "b %z2")
14387 ; This is used in compiling the unwind routines.
14388 (define_expand "eh_return"
14389 [(use (match_operand 0 "general_operand" ""))]
14390 ""
14391 "
14392 {
14393 if (TARGET_32BIT)
14394 emit_insn (gen_eh_set_lr_si (operands[0]));
14395 else
14396 emit_insn (gen_eh_set_lr_di (operands[0]));
14397 DONE;
14398 }")
14400 ; We can't expand this before we know where the link register is stored.
14401 (define_insn "eh_set_lr_<mode>"
14402 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14403 UNSPECV_EH_RR)
14404 (clobber (match_scratch:P 1 "=&b"))]
14405 ""
14406 "#")
14408 (define_split
14409 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14410 (clobber (match_scratch 1 ""))]
14411 "reload_completed"
14412 [(const_int 0)]
14413 "
14414 {
14415 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14416 DONE;
14417 }")
14419 (define_insn "prefetch"
14420 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14421 (match_operand:SI 1 "const_int_operand" "n")
14422 (match_operand:SI 2 "const_int_operand" "n"))]
14423 "TARGET_POWERPC"
14424 "*
14425 {
14426 if (GET_CODE (operands[0]) == REG)
14427 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14428 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14429 }"
14430 [(set_attr "type" "load")])
14431 \f
14433 (include "sync.md")
14434 (include "altivec.md")
14435 (include "spe.md")