gcc/config/m32c/shift.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 2, or (at your
  11 ;; option) any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21 ;; 02110-1301, USA.
  22
  23 ;; bit shifting
  24
  25 ; Shifts are unusual for m32c.  We only support shifting in one
  26 ; "direction" but the shift count is signed.  Also, immediate shift
  27 ; counts have a limited range, and variable shift counts have to be in
  28 ; $r1h which GCC normally doesn't even know about.
  29
  30 ; Other than compensating for the above, the patterns below are pretty
  31 ; straightforward.
  32
  33 (define_insn "ashlqi3_i"
  34   [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
  35         (ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
  36                    (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
  37    (clobber (match_scratch:HI 3 "=X,R1w"))]
  38   ""
  39   "@
  40    sha.b\t%2,%0
  41    mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  42   [(set_attr "flags" "oszc,oszc")]
  43   )
  44
  45 (define_insn "ashrqi3_i"
  46   [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
  47         (ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
  48                      (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
  49    (clobber (match_scratch:HI 3 "=X,R1w"))]
  50   ""
  51   "@
  52    sha.b\t%2,%0
  53    mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
  54   [(set_attr "flags" "oszc,oszc")]
  55   )
  56
  57 (define_insn "lshrqi3_i"
  58   [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
  59         (lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
  60                      (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
  61    (clobber (match_scratch:HI 3 "=X,R1w"))]
  62   ""
  63   "@
  64    shl.b\t%2,%0
  65    mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
  66   [(set_attr "flags" "szc,szc")]
  67   )
  68
  69
  70 (define_expand "ashlqi3"
  71   [(parallel [(set (match_operand:QI 0 "mra_operand" "")
  72         (ashift:QI (match_operand:QI 1 "mra_operand" "")
  73                    (match_operand:QI 2 "general_operand" "")))
  74    (clobber (match_scratch:HI 3 ""))])]
  75   ""
  76   "if (m32c_prepare_shift (operands, 1, ASHIFT))
  77      DONE;"
  78   )
  79
  80 (define_expand "ashrqi3"
  81   [(parallel [(set (match_operand:QI 0 "mra_operand" "")
  82         (ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
  83                      (neg:QI (match_operand:QI 2 "general_operand" ""))))
  84    (clobber (match_scratch:HI 3 ""))])]
  85   ""
  86   "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
  87      DONE;"
  88   )
  89
  90 (define_expand "lshrqi3"
  91   [(parallel [(set (match_operand:QI 0 "mra_operand" "")
  92                    (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
  93                                 (neg:QI (match_operand:QI 2 "general_operand" ""))))
  94               (clobber (match_scratch:HI 3 ""))])]
  95   ""
  96   "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
  97      DONE;"
  98   )
  99
 100 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 101
 102 (define_insn "ashlhi3_i"
 103   [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
 104         (ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
 105                    (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
 106    (clobber (match_scratch:HI 3 "=X,R1w"))]
 107   ""
 108   "@
 109    sha.w\t%2,%0
 110    mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
 111   [(set_attr "flags" "oszc,oszc")]
 112   )
 113
 114 (define_insn "ashrhi3_i"
 115   [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
 116         (ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
 117                      (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
 118    (clobber (match_scratch:HI 3 "=X,R1w"))]
 119   ""
 120   "@
 121    sha.w\t%2,%0
 122    mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
 123   [(set_attr "flags" "oszc,oszc")]
 124   )
 125
 126 (define_insn "lshrhi3_i"
 127   [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
 128         (lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
 129                      (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
 130    (clobber (match_scratch:HI 3 "=X,R1w"))]
 131   ""
 132   "@
 133    shl.w\t%2,%0
 134    mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
 135   [(set_attr "flags" "szc,szc")]
 136   )
 137
 138
 139 (define_expand "ashlhi3"
 140   [(parallel [(set (match_operand:HI 0 "mra_operand" "")
 141                    (ashift:HI (match_operand:HI 1 "mra_operand" "")
 142                               (match_operand:QI 2 "general_operand" "")))
 143               (clobber (match_scratch:HI 3 ""))])]
 144   ""
 145   "if (m32c_prepare_shift (operands, 1, ASHIFT))
 146      DONE;"
 147   )
 148
 149 (define_expand "ashrhi3"
 150   [(parallel [(set (match_operand:HI 0 "mra_operand" "")
 151                    (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
 152                                 (neg:QI (match_operand:QI 2 "general_operand" ""))))
 153               (clobber (match_scratch:HI 3 ""))])]
 154   ""
 155   "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
 156      DONE;"
 157   )
 158
 159 (define_expand "lshrhi3"
 160   [(parallel [(set (match_operand:HI 0 "mra_operand" "")
 161                    (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
 162                                 (neg:QI (match_operand:QI 2 "general_operand" ""))))
 163               (clobber (match_scratch:HI 3 ""))])]
 164   ""
 165   "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
 166      DONE;"
 167   )
 168
 169
 170
 171
 172 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 173
 174
 175 (define_insn "ashlpsi3_i"
 176   [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
 177         (ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
 178                     (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
 179    (clobber (match_scratch:HI 3 "=X,R1w"))]
 180   "TARGET_A24"
 181   "@
 182    sha.l\t%2,%0
 183    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 184   [(set_attr "flags" "oszc,oszc")]
 185   )
 186
 187 (define_insn "ashrpsi3_i"
 188   [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
 189         (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
 190                       (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
 191    (clobber (match_scratch:HI 3 "=X,R1w"))]
 192   "TARGET_A24"
 193   "@
 194    sha.l\t%2,%0
 195    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 196   [(set_attr "flags" "oszc,oszc")]
 197   )
 198
 199 (define_insn "lshrpsi3_i"
 200   [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
 201         (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
 202                       (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
 203    (clobber (match_scratch:HI 3 "=X,R1w"))]
 204   "TARGET_A24"
 205   "@
 206    shl.l\t%2,%0
 207    mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
 208   [(set_attr "flags" "szc,szc")]
 209   )
 210
 211
 212 (define_expand "ashlpsi3"
 213   [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
 214                    (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
 215                                (match_operand:QI 2 "mrai_operand" "")))
 216               (clobber (match_scratch:HI 3 ""))])]
 217   "TARGET_A24"
 218   "if (m32c_prepare_shift (operands, 1, ASHIFT))
 219      DONE;"
 220   )
 221
 222 (define_expand "ashrpsi3"
 223   [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
 224                    (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
 225                                  (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
 226               (clobber (match_scratch:HI 3 ""))])]
 227   "TARGET_A24"
 228   "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
 229      DONE;"
 230   )
 231
 232 (define_expand "lshrpsi3"
 233   [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
 234                    (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
 235                                  (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
 236               (clobber (match_scratch:HI 3 ""))])]
 237   "TARGET_A24"
 238   "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
 239      DONE;"
 240   )
 241
 242 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 243
 244 ; The m16c has a maximum shift count of -16..16, even when in a
 245 ; register.  It's optimal to use multiple shifts of -8..8 rather than
 246 ; loading larger constants into R1H multiple time.  The m32c can shift
 247 ; -32..32 either via immediates or in registers.  Hence, separate
 248 ; patterns.
 249
 250
 251 (define_insn "ashlsi3_16"
 252   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 253         (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
 254                    (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
 255    (clobber (match_scratch:HI 3 "=X,R1w"))]
 256   "TARGET_A16"
 257   "@
 258    sha.l\t%2,%0
 259    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 260   [(set_attr "flags" "oszc,oszc")]
 261   )
 262
 263 (define_insn "ashrsi3_16"
 264   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 265         (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
 266                      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
 267    (clobber (match_scratch:HI 3 "=X,R1w"))]
 268   "TARGET_A16"
 269   "@
 270    sha.l\t%2,%0
 271    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 272   [(set_attr "flags" "oszc,oszc")]
 273   )
 274
 275 (define_insn "lshrsi3_16"
 276   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 277         (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
 278                      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
 279    (clobber (match_scratch:HI 3 "=X,R1w"))]
 280   "TARGET_A16"
 281   "@
 282    shl.l\t%2,%0
 283    mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
 284   [(set_attr "flags" "szc,szc")]
 285   )
 286
 287
 288
 289 (define_insn "ashlsi3_24"
 290   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 291         (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
 292                    (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
 293    (clobber (match_scratch:HI 3 "=X,R1w"))]
 294   "TARGET_A24"
 295   "@
 296    sha.l\t%2,%0
 297    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 298   )
 299
 300 (define_insn "ashrsi3_24"
 301   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 302         (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
 303                      (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
 304    (clobber (match_scratch:HI 3 "=X,R1w"))]
 305   "TARGET_A24"
 306   "@
 307    sha.l\t%2,%0
 308    mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
 309   )
 310
 311 (define_insn "lshrsi3_24"
 312   [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
 313         (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
 314                      (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
 315    (clobber (match_scratch:HI 3 "=X,R1w"))]
 316   "TARGET_A24"
 317   "@
 318    shl.l\t%2,%0
 319    mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
 320   )
 321
 322
 323
 324
 325 (define_expand "ashlsi3"
 326   [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
 327                    (ashift:SI (match_operand:SI 1 "r0123_operand" "")
 328                               (match_operand:QI 2 "mrai_operand" "")))
 329               (clobber (match_scratch:HI 3 ""))])]
 330   ""
 331   "if (m32c_prepare_shift (operands, 1, ASHIFT))
 332      DONE;"
 333   )
 334
 335 (define_expand "ashrsi3"
 336   [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
 337                    (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
 338                                 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
 339               (clobber (match_scratch:HI 3 ""))])]
 340   ""
 341   "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
 342      DONE;"
 343   )
 344
 345 (define_expand "lshrsi3"
 346   [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
 347                    (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
 348                                 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
 349               (clobber (match_scratch:HI 3 ""))])]
 350   ""
 351   "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
 352      DONE;"
 353   )