| blob | ab502ad13c23ca4422bed352d0a0b14ae1fbcf88 |
1 ;; ARM VFP instruction patterns
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; SImode moves
22 ;; ??? For now do not allow loading constants into vfp regs. This causes
23 ;; problems because small constants get converted into adds.
24 (define_insn "*arm_movsi_vfp"
25 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
26 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
27 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
28 && ( s_register_operand (operands[0], SImode)
29 || s_register_operand (operands[1], SImode))"
30 "*
31 switch (which_alternative)
32 {
33 case 0: case 1:
34 return \"mov%?\\t%0, %1\";
35 case 2:
36 return \"mvn%?\\t%0, #%B1\";
37 case 3:
38 return \"movw%?\\t%0, %1\";
39 case 4:
40 return \"ldr%?\\t%0, %1\";
41 case 5:
42 return \"str%?\\t%1, %0\";
43 case 6:
44 return \"fmsr%?\\t%0, %1\\t%@ int\";
45 case 7:
46 return \"fmrs%?\\t%0, %1\\t%@ int\";
47 case 8:
48 return \"fcpys%?\\t%0, %1\\t%@ int\";
49 case 9: case 10:
50 return output_move_vfp (operands);
51 default:
52 gcc_unreachable ();
53 }
54 "
55 [(set_attr "predicable" "yes")
56 (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
57 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
58 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
59 )
61 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
62 ;; high/low register alternatives for loads and stores here.
63 ;; The l/Py alternative should come after r/I to ensure that the short variant
64 ;; is chosen with length 2 when the instruction is predicated for
65 ;; arm_restrict_it.
66 (define_insn "*thumb2_movsi_vfp"
67 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv")
68 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
69 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
70 && ( s_register_operand (operands[0], SImode)
71 || s_register_operand (operands[1], SImode))"
72 "*
73 switch (which_alternative)
74 {
75 case 0:
76 case 1:
77 case 2:
78 return \"mov%?\\t%0, %1\";
79 case 3:
80 return \"mvn%?\\t%0, #%B1\";
81 case 4:
82 return \"movw%?\\t%0, %1\";
83 case 5:
84 case 6:
85 return \"ldr%?\\t%0, %1\";
86 case 7:
87 case 8:
88 return \"str%?\\t%1, %0\";
89 case 9:
90 return \"fmsr%?\\t%0, %1\\t%@ int\";
91 case 10:
92 return \"fmrs%?\\t%0, %1\\t%@ int\";
93 case 11:
94 return \"fcpys%?\\t%0, %1\\t%@ int\";
95 case 12: case 13:
96 return output_move_vfp (operands);
97 default:
98 gcc_unreachable ();
99 }
100 "
101 [(set_attr "predicable" "yes")
102 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
103 (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
104 (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
105 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
106 (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
107 )
110 ;; DImode moves
112 (define_insn "*movdi_vfp"
113 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
114 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
115 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
116 && ( register_operand (operands[0], DImode)
117 || register_operand (operands[1], DImode))
118 && !(TARGET_NEON && CONST_INT_P (operands[1])
119 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
120 "*
121 switch (which_alternative)
122 {
123 case 0:
124 case 1:
125 case 2:
126 case 3:
127 return \"#\";
128 case 4:
129 case 5:
130 case 6:
131 return output_move_double (operands, true, NULL);
132 case 7:
133 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
134 case 8:
135 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
136 case 9:
137 if (TARGET_VFP_SINGLE)
138 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
139 else
140 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
141 case 10: case 11:
142 return output_move_vfp (operands);
143 default:
144 gcc_unreachable ();
145 }
146 "
147 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
148 (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
149 (eq_attr "alternative" "2") (const_int 12)
150 (eq_attr "alternative" "3") (const_int 16)
151 (eq_attr "alternative" "9")
152 (if_then_else
153 (match_test "TARGET_VFP_SINGLE")
154 (const_int 8)
155 (const_int 4))]
156 (const_int 4)))
157 (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*")
158 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
159 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
160 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
161 )
163 (define_insn "*movdi_vfp_cortexa8"
164 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
165 (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
166 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
167 && ( register_operand (operands[0], DImode)
168 || register_operand (operands[1], DImode))
169 && !(TARGET_NEON && CONST_INT_P (operands[1])
170 && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
171 "*
172 switch (which_alternative)
173 {
174 case 0:
175 case 1:
176 case 2:
177 case 3:
178 return \"#\";
179 case 4:
180 case 5:
181 case 6:
182 return output_move_double (operands, true, NULL);
183 case 7:
184 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
185 case 8:
186 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
187 case 9:
188 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
189 case 10: case 11:
190 return output_move_vfp (operands);
191 default:
192 gcc_unreachable ();
193 }
194 "
195 [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
196 (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
197 (eq_attr "alternative" "2") (const_int 12)
198 (eq_attr "alternative" "3") (const_int 16)
199 (eq_attr "alternative" "4,5,6")
200 (symbol_ref
201 "arm_count_output_move_double_insns (operands) \
202 * 4")]
203 (const_int 4)))
204 (set_attr "predicable" "yes")
205 (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
206 (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
207 (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
208 (set (attr "ce_count")
209 (symbol_ref "get_attr_length (insn) / 4"))
210 (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
211 )
213 ;; HFmode moves
214 (define_insn "*movhf_vfp_neon"
215 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
216 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
217 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
218 && ( s_register_operand (operands[0], HFmode)
219 || s_register_operand (operands[1], HFmode))"
220 "*
221 switch (which_alternative)
222 {
223 case 0: /* S register from memory */
224 return \"vld1.16\\t{%z0}, %A1\";
225 case 1: /* memory from S register */
226 return \"vst1.16\\t{%z1}, %A0\";
227 case 2: /* ARM register from memory */
228 return \"ldrh\\t%0, %1\\t%@ __fp16\";
229 case 3: /* memory from ARM register */
230 return \"strh\\t%1, %0\\t%@ __fp16\";
231 case 4: /* S register from S register */
232 return \"fcpys\\t%0, %1\";
233 case 5: /* ARM register from ARM register */
234 return \"mov\\t%0, %1\\t%@ __fp16\";
235 case 6: /* S register from ARM register */
236 return \"fmsr\\t%0, %1\";
237 case 7: /* ARM register from S register */
238 return \"fmrs\\t%0, %1\";
239 case 8: /* ARM register from constant */
240 {
241 REAL_VALUE_TYPE r;
242 long bits;
243 rtx ops[4];
245 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
246 bits = real_to_target (NULL, &r, HFmode);
247 ops[0] = operands[0];
248 ops[1] = GEN_INT (bits);
249 ops[2] = GEN_INT (bits & 0xff00);
250 ops[3] = GEN_INT (bits & 0x00ff);
252 if (arm_arch_thumb2)
253 output_asm_insn (\"movw\\t%0, %1\", ops);
254 else
255 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
256 return \"\";
257 }
258 default:
259 gcc_unreachable ();
260 }
261 "
262 [(set_attr "conds" "unconditional")
263 (set_attr "type" "neon_load1_1reg,neon_store1_1reg,\
264 load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
265 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
266 )
268 ;; FP16 without element load/store instructions.
269 (define_insn "*movhf_vfp"
270 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
271 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
272 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
273 && ( s_register_operand (operands[0], HFmode)
274 || s_register_operand (operands[1], HFmode))"
275 "*
276 switch (which_alternative)
277 {
278 case 0: /* ARM register from memory */
279 return \"ldrh\\t%0, %1\\t%@ __fp16\";
280 case 1: /* memory from ARM register */
281 return \"strh\\t%1, %0\\t%@ __fp16\";
282 case 2: /* S register from S register */
283 return \"fcpys\\t%0, %1\";
284 case 3: /* ARM register from ARM register */
285 return \"mov\\t%0, %1\\t%@ __fp16\";
286 case 4: /* S register from ARM register */
287 return \"fmsr\\t%0, %1\";
288 case 5: /* ARM register from S register */
289 return \"fmrs\\t%0, %1\";
290 case 6: /* ARM register from constant */
291 {
292 REAL_VALUE_TYPE r;
293 long bits;
294 rtx ops[4];
296 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
297 bits = real_to_target (NULL, &r, HFmode);
298 ops[0] = operands[0];
299 ops[1] = GEN_INT (bits);
300 ops[2] = GEN_INT (bits & 0xff00);
301 ops[3] = GEN_INT (bits & 0x00ff);
303 if (arm_arch_thumb2)
304 output_asm_insn (\"movw\\t%0, %1\", ops);
305 else
306 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
307 return \"\";
308 }
309 default:
310 gcc_unreachable ();
311 }
312 "
313 [(set_attr "conds" "unconditional")
314 (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
315 (set_attr "length" "4,4,4,4,4,4,8")]
316 )
319 ;; SFmode moves
320 ;; Disparage the w<->r cases because reloading an invalid address is
321 ;; preferable to loading the value via integer registers.
323 (define_insn "*movsf_vfp"
324 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
325 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
326 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
327 && ( s_register_operand (operands[0], SFmode)
328 || s_register_operand (operands[1], SFmode))"
329 "*
330 switch (which_alternative)
331 {
332 case 0:
333 return \"fmsr%?\\t%0, %1\";
334 case 1:
335 return \"fmrs%?\\t%0, %1\";
336 case 2:
337 return \"fconsts%?\\t%0, #%G1\";
338 case 3: case 4:
339 return output_move_vfp (operands);
340 case 5:
341 return \"ldr%?\\t%0, %1\\t%@ float\";
342 case 6:
343 return \"str%?\\t%1, %0\\t%@ float\";
344 case 7:
345 return \"fcpys%?\\t%0, %1\";
346 case 8:
347 return \"mov%?\\t%0, %1\\t%@ float\";
348 default:
349 gcc_unreachable ();
350 }
351 "
352 [(set_attr "predicable" "yes")
353 (set_attr "type"
354 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
355 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
356 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
357 )
359 (define_insn "*thumb2_movsf_vfp"
360 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
361 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
362 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
363 && ( s_register_operand (operands[0], SFmode)
364 || s_register_operand (operands[1], SFmode))"
365 "*
366 switch (which_alternative)
367 {
368 case 0:
369 return \"fmsr%?\\t%0, %1\";
370 case 1:
371 return \"fmrs%?\\t%0, %1\";
372 case 2:
373 return \"fconsts%?\\t%0, #%G1\";
374 case 3: case 4:
375 return output_move_vfp (operands);
376 case 5:
377 return \"ldr%?\\t%0, %1\\t%@ float\";
378 case 6:
379 return \"str%?\\t%1, %0\\t%@ float\";
380 case 7:
381 return \"fcpys%?\\t%0, %1\";
382 case 8:
383 return \"mov%?\\t%0, %1\\t%@ float\";
384 default:
385 gcc_unreachable ();
386 }
387 "
388 [(set_attr "predicable" "yes")
389 (set_attr "predicable_short_it" "no")
390 (set_attr "type"
391 "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
392 (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
393 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
394 )
396 ;; DFmode moves
398 (define_insn "*movdf_vfp"
399 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
400 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
401 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
402 && ( register_operand (operands[0], DFmode)
403 || register_operand (operands[1], DFmode))"
404 "*
405 {
406 switch (which_alternative)
407 {
408 case 0:
409 return \"fmdrr%?\\t%P0, %Q1, %R1\";
410 case 1:
411 return \"fmrrd%?\\t%Q0, %R0, %P1\";
412 case 2:
413 gcc_assert (TARGET_VFP_DOUBLE);
414 return \"fconstd%?\\t%P0, #%G1\";
415 case 3: case 4:
416 return output_move_vfp (operands);
417 case 5: case 6:
418 return output_move_double (operands, true, NULL);
419 case 7:
420 if (TARGET_VFP_SINGLE)
421 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
422 else
423 return \"fcpyd%?\\t%P0, %P1\";
424 case 8:
425 return \"#\";
426 default:
427 gcc_unreachable ();
428 }
429 }
430 "
431 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
432 load2,store2,ffarithd,multiple")
433 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
434 (eq_attr "alternative" "7")
435 (if_then_else
436 (match_test "TARGET_VFP_SINGLE")
437 (const_int 8)
438 (const_int 4))]
439 (const_int 4)))
440 (set_attr "predicable" "yes")
441 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
442 (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
443 )
445 (define_insn "*thumb2_movdf_vfp"
446 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
447 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
448 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
449 && ( register_operand (operands[0], DFmode)
450 || register_operand (operands[1], DFmode))"
451 "*
452 {
453 switch (which_alternative)
454 {
455 case 0:
456 return \"fmdrr%?\\t%P0, %Q1, %R1\";
457 case 1:
458 return \"fmrrd%?\\t%Q0, %R0, %P1\";
459 case 2:
460 gcc_assert (TARGET_VFP_DOUBLE);
461 return \"fconstd%?\\t%P0, #%G1\";
462 case 3: case 4:
463 return output_move_vfp (operands);
464 case 5: case 6: case 8:
465 return output_move_double (operands, true, NULL);
466 case 7:
467 if (TARGET_VFP_SINGLE)
468 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
469 else
470 return \"fcpyd%?\\t%P0, %P1\";
471 default:
472 abort ();
473 }
474 }
475 "
476 [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
477 f_stored,load2,store2,ffarithd,multiple")
478 (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
479 (eq_attr "alternative" "7")
480 (if_then_else
481 (match_test "TARGET_VFP_SINGLE")
482 (const_int 8)
483 (const_int 4))]
484 (const_int 4)))
485 (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
486 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
487 )
490 ;; Conditional move patterns
492 (define_insn "*movsfcc_vfp"
493 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
494 (if_then_else:SF
495 (match_operator 3 "arm_comparison_operator"
496 [(match_operand 4 "cc_register" "") (const_int 0)])
497 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
498 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
499 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
500 "@
501 fcpys%D3\\t%0, %2
502 fcpys%d3\\t%0, %1
503 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
504 fmsr%D3\\t%0, %2
505 fmsr%d3\\t%0, %1
506 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
507 fmrs%D3\\t%0, %2
508 fmrs%d3\\t%0, %1
509 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
510 [(set_attr "conds" "use")
511 (set_attr "length" "4,4,8,4,4,8,4,4,8")
512 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
513 )
515 (define_insn "*thumb2_movsfcc_vfp"
516 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
517 (if_then_else:SF
518 (match_operator 3 "arm_comparison_operator"
519 [(match_operand 4 "cc_register" "") (const_int 0)])
520 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
521 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
522 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
523 "@
524 it\\t%D3\;fcpys%D3\\t%0, %2
525 it\\t%d3\;fcpys%d3\\t%0, %1
526 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
527 it\\t%D3\;fmsr%D3\\t%0, %2
528 it\\t%d3\;fmsr%d3\\t%0, %1
529 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
530 it\\t%D3\;fmrs%D3\\t%0, %2
531 it\\t%d3\;fmrs%d3\\t%0, %1
532 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
533 [(set_attr "conds" "use")
534 (set_attr "length" "6,6,10,6,6,10,6,6,10")
535 (set_attr "type" "fmov,fmov,fmov,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")]
536 )
538 (define_insn "*movdfcc_vfp"
539 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
540 (if_then_else:DF
541 (match_operator 3 "arm_comparison_operator"
542 [(match_operand 4 "cc_register" "") (const_int 0)])
543 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
544 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
545 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
546 "@
547 fcpyd%D3\\t%P0, %P2
548 fcpyd%d3\\t%P0, %P1
549 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
550 fmdrr%D3\\t%P0, %Q2, %R2
551 fmdrr%d3\\t%P0, %Q1, %R1
552 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
553 fmrrd%D3\\t%Q0, %R0, %P2
554 fmrrd%d3\\t%Q0, %R0, %P1
555 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
556 [(set_attr "conds" "use")
557 (set_attr "length" "4,4,8,4,4,8,4,4,8")
558 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
559 )
561 (define_insn "*thumb2_movdfcc_vfp"
562 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
563 (if_then_else:DF
564 (match_operator 3 "arm_comparison_operator"
565 [(match_operand 4 "cc_register" "") (const_int 0)])
566 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
567 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
568 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it"
569 "@
570 it\\t%D3\;fcpyd%D3\\t%P0, %P2
571 it\\t%d3\;fcpyd%d3\\t%P0, %P1
572 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
573 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
574 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
575 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
576 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
577 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
578 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
579 [(set_attr "conds" "use")
580 (set_attr "length" "6,6,10,6,6,10,6,6,10")
581 (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
582 )
585 ;; Sign manipulation functions
587 (define_insn "*abssf2_vfp"
588 [(set (match_operand:SF 0 "s_register_operand" "=t")
589 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
590 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
591 "fabss%?\\t%0, %1"
592 [(set_attr "predicable" "yes")
593 (set_attr "predicable_short_it" "no")
594 (set_attr "type" "ffariths")]
595 )
597 (define_insn "*absdf2_vfp"
598 [(set (match_operand:DF 0 "s_register_operand" "=w")
599 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
600 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
601 "fabsd%?\\t%P0, %P1"
602 [(set_attr "predicable" "yes")
603 (set_attr "predicable_short_it" "no")
604 (set_attr "type" "ffarithd")]
605 )
607 (define_insn "*negsf2_vfp"
608 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
609 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
610 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
611 "@
612 fnegs%?\\t%0, %1
613 eor%?\\t%0, %1, #-2147483648"
614 [(set_attr "predicable" "yes")
615 (set_attr "predicable_short_it" "no")
616 (set_attr "type" "ffariths")]
617 )
619 (define_insn_and_split "*negdf2_vfp"
620 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
621 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
622 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
623 "@
624 fnegd%?\\t%P0, %P1
625 #
626 #"
627 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
628 && arm_general_register_operand (operands[0], DFmode)"
629 [(set (match_dup 0) (match_dup 1))]
630 "
631 if (REGNO (operands[0]) == REGNO (operands[1]))
632 {
633 operands[0] = gen_highpart (SImode, operands[0]);
634 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
635 }
636 else
637 {
638 rtx in_hi, in_lo, out_hi, out_lo;
640 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
641 GEN_INT (0x80000000));
642 in_lo = gen_lowpart (SImode, operands[1]);
643 out_hi = gen_highpart (SImode, operands[0]);
644 out_lo = gen_lowpart (SImode, operands[0]);
646 if (REGNO (in_lo) == REGNO (out_hi))
647 {
648 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
649 operands[0] = out_hi;
650 operands[1] = in_hi;
651 }
652 else
653 {
654 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
655 operands[0] = out_lo;
656 operands[1] = in_lo;
657 }
658 }
659 "
660 [(set_attr "predicable" "yes")
661 (set_attr "predicable_short_it" "no")
662 (set_attr "length" "4,4,8")
663 (set_attr "type" "ffarithd")]
664 )
667 ;; Arithmetic insns
669 (define_insn "*addsf3_vfp"
670 [(set (match_operand:SF 0 "s_register_operand" "=t")
671 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
672 (match_operand:SF 2 "s_register_operand" "t")))]
673 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
674 "fadds%?\\t%0, %1, %2"
675 [(set_attr "predicable" "yes")
676 (set_attr "predicable_short_it" "no")
677 (set_attr "type" "fadds")]
678 )
680 (define_insn "*adddf3_vfp"
681 [(set (match_operand:DF 0 "s_register_operand" "=w")
682 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
683 (match_operand:DF 2 "s_register_operand" "w")))]
684 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
685 "faddd%?\\t%P0, %P1, %P2"
686 [(set_attr "predicable" "yes")
687 (set_attr "predicable_short_it" "no")
688 (set_attr "type" "faddd")]
689 )
692 (define_insn "*subsf3_vfp"
693 [(set (match_operand:SF 0 "s_register_operand" "=t")
694 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
695 (match_operand:SF 2 "s_register_operand" "t")))]
696 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
697 "fsubs%?\\t%0, %1, %2"
698 [(set_attr "predicable" "yes")
699 (set_attr "predicable_short_it" "no")
700 (set_attr "type" "fadds")]
701 )
703 (define_insn "*subdf3_vfp"
704 [(set (match_operand:DF 0 "s_register_operand" "=w")
705 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
706 (match_operand:DF 2 "s_register_operand" "w")))]
707 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
708 "fsubd%?\\t%P0, %P1, %P2"
709 [(set_attr "predicable" "yes")
710 (set_attr "predicable_short_it" "no")
711 (set_attr "type" "faddd")]
712 )
715 ;; Division insns
717 ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
718 ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
719 ; earlier.
720 (define_insn "*divsf3_vfp"
721 [(set (match_operand:SF 0 "s_register_operand" "=&t,t")
722 (div:SF (match_operand:SF 1 "s_register_operand" "t,t")
723 (match_operand:SF 2 "s_register_operand" "t,t")))]
724 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
725 "fdivs%?\\t%0, %1, %2"
726 [(set_attr "predicable" "yes")
727 (set_attr "predicable_short_it" "no")
728 (set_attr "arch" "*,armv6_or_vfpv3")
729 (set_attr "type" "fdivs")]
730 )
732 (define_insn "*divdf3_vfp"
733 [(set (match_operand:DF 0 "s_register_operand" "=&w,w")
734 (div:DF (match_operand:DF 1 "s_register_operand" "w,w")
735 (match_operand:DF 2 "s_register_operand" "w,w")))]
736 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
737 "fdivd%?\\t%P0, %P1, %P2"
738 [(set_attr "predicable" "yes")
739 (set_attr "predicable_short_it" "no")
740 (set_attr "arch" "*,armv6_or_vfpv3")
741 (set_attr "type" "fdivd")]
742 )
745 ;; Multiplication insns
747 (define_insn "*mulsf3_vfp"
748 [(set (match_operand:SF 0 "s_register_operand" "=t")
749 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
750 (match_operand:SF 2 "s_register_operand" "t")))]
751 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
752 "fmuls%?\\t%0, %1, %2"
753 [(set_attr "predicable" "yes")
754 (set_attr "predicable_short_it" "no")
755 (set_attr "type" "fmuls")]
756 )
758 (define_insn "*muldf3_vfp"
759 [(set (match_operand:DF 0 "s_register_operand" "=w")
760 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
761 (match_operand:DF 2 "s_register_operand" "w")))]
762 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
763 "fmuld%?\\t%P0, %P1, %P2"
764 [(set_attr "predicable" "yes")
765 (set_attr "predicable_short_it" "no")
766 (set_attr "type" "fmuld")]
767 )
769 (define_insn "*mulsf3negsf_vfp"
770 [(set (match_operand:SF 0 "s_register_operand" "=t")
771 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
772 (match_operand:SF 2 "s_register_operand" "t")))]
773 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
774 "fnmuls%?\\t%0, %1, %2"
775 [(set_attr "predicable" "yes")
776 (set_attr "predicable_short_it" "no")
777 (set_attr "type" "fmuls")]
778 )
780 (define_insn "*muldf3negdf_vfp"
781 [(set (match_operand:DF 0 "s_register_operand" "=w")
782 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
783 (match_operand:DF 2 "s_register_operand" "w")))]
784 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
785 "fnmuld%?\\t%P0, %P1, %P2"
786 [(set_attr "predicable" "yes")
787 (set_attr "predicable_short_it" "no")
788 (set_attr "type" "fmuld")]
789 )
792 ;; Multiply-accumulate insns
794 ;; 0 = 1 * 2 + 0
795 (define_insn "*mulsf3addsf_vfp"
796 [(set (match_operand:SF 0 "s_register_operand" "=t")
797 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
798 (match_operand:SF 3 "s_register_operand" "t"))
799 (match_operand:SF 1 "s_register_operand" "0")))]
800 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
801 "fmacs%?\\t%0, %2, %3"
802 [(set_attr "predicable" "yes")
803 (set_attr "predicable_short_it" "no")
804 (set_attr "type" "fmacs")]
805 )
807 (define_insn "*muldf3adddf_vfp"
808 [(set (match_operand:DF 0 "s_register_operand" "=w")
809 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
810 (match_operand:DF 3 "s_register_operand" "w"))
811 (match_operand:DF 1 "s_register_operand" "0")))]
812 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
813 "fmacd%?\\t%P0, %P2, %P3"
814 [(set_attr "predicable" "yes")
815 (set_attr "predicable_short_it" "no")
816 (set_attr "type" "fmacd")]
817 )
819 ;; 0 = 1 * 2 - 0
820 (define_insn "*mulsf3subsf_vfp"
821 [(set (match_operand:SF 0 "s_register_operand" "=t")
822 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
823 (match_operand:SF 3 "s_register_operand" "t"))
824 (match_operand:SF 1 "s_register_operand" "0")))]
825 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
826 "fmscs%?\\t%0, %2, %3"
827 [(set_attr "predicable" "yes")
828 (set_attr "predicable_short_it" "no")
829 (set_attr "type" "fmacs")]
830 )
832 (define_insn "*muldf3subdf_vfp"
833 [(set (match_operand:DF 0 "s_register_operand" "=w")
834 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
835 (match_operand:DF 3 "s_register_operand" "w"))
836 (match_operand:DF 1 "s_register_operand" "0")))]
837 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
838 "fmscd%?\\t%P0, %P2, %P3"
839 [(set_attr "predicable" "yes")
840 (set_attr "predicable_short_it" "no")
841 (set_attr "type" "fmacd")]
842 )
844 ;; 0 = -(1 * 2) + 0
845 (define_insn "*mulsf3negsfaddsf_vfp"
846 [(set (match_operand:SF 0 "s_register_operand" "=t")
847 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
848 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
849 (match_operand:SF 3 "s_register_operand" "t"))))]
850 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
851 "fnmacs%?\\t%0, %2, %3"
852 [(set_attr "predicable" "yes")
853 (set_attr "predicable_short_it" "no")
854 (set_attr "type" "fmacs")]
855 )
857 (define_insn "*fmuldf3negdfadddf_vfp"
858 [(set (match_operand:DF 0 "s_register_operand" "=w")
859 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
860 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
861 (match_operand:DF 3 "s_register_operand" "w"))))]
862 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
863 "fnmacd%?\\t%P0, %P2, %P3"
864 [(set_attr "predicable" "yes")
865 (set_attr "predicable_short_it" "no")
866 (set_attr "type" "fmacd")]
867 )
870 ;; 0 = -(1 * 2) - 0
871 (define_insn "*mulsf3negsfsubsf_vfp"
872 [(set (match_operand:SF 0 "s_register_operand" "=t")
873 (minus:SF (mult:SF
874 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
875 (match_operand:SF 3 "s_register_operand" "t"))
876 (match_operand:SF 1 "s_register_operand" "0")))]
877 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
878 "fnmscs%?\\t%0, %2, %3"
879 [(set_attr "predicable" "yes")
880 (set_attr "predicable_short_it" "no")
881 (set_attr "type" "fmacs")]
882 )
884 (define_insn "*muldf3negdfsubdf_vfp"
885 [(set (match_operand:DF 0 "s_register_operand" "=w")
886 (minus:DF (mult:DF
887 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
888 (match_operand:DF 3 "s_register_operand" "w"))
889 (match_operand:DF 1 "s_register_operand" "0")))]
890 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
891 "fnmscd%?\\t%P0, %P2, %P3"
892 [(set_attr "predicable" "yes")
893 (set_attr "predicable_short_it" "no")
894 (set_attr "type" "fmacd")]
895 )
897 ;; Fused-multiply-accumulate
899 (define_insn "fma<SDF:mode>4"
900 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
901 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
902 (match_operand:SDF 2 "register_operand" "<F_constraint>")
903 (match_operand:SDF 3 "register_operand" "0")))]
904 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
905 "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
906 [(set_attr "predicable" "yes")
907 (set_attr "predicable_short_it" "no")
908 (set_attr "type" "ffma<vfp_type>")]
909 )
911 (define_insn "*fmsub<SDF:mode>4"
912 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
913 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
914 "<F_constraint>"))
915 (match_operand:SDF 2 "register_operand" "<F_constraint>")
916 (match_operand:SDF 3 "register_operand" "0")))]
917 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
918 "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
919 [(set_attr "predicable" "yes")
920 (set_attr "predicable_short_it" "no")
921 (set_attr "type" "ffma<vfp_type>")]
922 )
924 (define_insn "*fnmsub<SDF:mode>4"
925 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
926 (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
927 (match_operand:SDF 2 "register_operand" "<F_constraint>")
928 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
929 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
930 "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
931 [(set_attr "predicable" "yes")
932 (set_attr "predicable_short_it" "no")
933 (set_attr "type" "ffma<vfp_type>")]
934 )
936 (define_insn "*fnmadd<SDF:mode>4"
937 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
938 (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
939 "<F_constraint>"))
940 (match_operand:SDF 2 "register_operand" "<F_constraint>")
941 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
942 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
943 "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
944 [(set_attr "predicable" "yes")
945 (set_attr "predicable_short_it" "no")
946 (set_attr "type" "ffma<vfp_type>")]
947 )
950 ;; Conversion routines
952 (define_insn "*extendsfdf2_vfp"
953 [(set (match_operand:DF 0 "s_register_operand" "=w")
954 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
955 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
956 "fcvtds%?\\t%P0, %1"
957 [(set_attr "predicable" "yes")
958 (set_attr "predicable_short_it" "no")
959 (set_attr "type" "f_cvt")]
960 )
962 (define_insn "*truncdfsf2_vfp"
963 [(set (match_operand:SF 0 "s_register_operand" "=t")
964 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
965 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
966 "fcvtsd%?\\t%0, %P1"
967 [(set_attr "predicable" "yes")
968 (set_attr "predicable_short_it" "no")
969 (set_attr "type" "f_cvt")]
970 )
972 (define_insn "extendhfsf2"
973 [(set (match_operand:SF 0 "s_register_operand" "=t")
974 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
975 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
976 "vcvtb%?.f32.f16\\t%0, %1"
977 [(set_attr "predicable" "yes")
978 (set_attr "predicable_short_it" "no")
979 (set_attr "type" "f_cvt")]
980 )
982 (define_insn "truncsfhf2"
983 [(set (match_operand:HF 0 "s_register_operand" "=t")
984 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
985 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
986 "vcvtb%?.f16.f32\\t%0, %1"
987 [(set_attr "predicable" "yes")
988 (set_attr "predicable_short_it" "no")
989 (set_attr "type" "f_cvt")]
990 )
992 (define_insn "*truncsisf2_vfp"
993 [(set (match_operand:SI 0 "s_register_operand" "=t")
994 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
995 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
996 "ftosizs%?\\t%0, %1"
997 [(set_attr "predicable" "yes")
998 (set_attr "predicable_short_it" "no")
999 (set_attr "type" "f_cvtf2i")]
1000 )
1002 (define_insn "*truncsidf2_vfp"
1003 [(set (match_operand:SI 0 "s_register_operand" "=t")
1004 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
1005 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1006 "ftosizd%?\\t%0, %P1"
1007 [(set_attr "predicable" "yes")
1008 (set_attr "predicable_short_it" "no")
1009 (set_attr "type" "f_cvtf2i")]
1010 )
1013 (define_insn "fixuns_truncsfsi2"
1014 [(set (match_operand:SI 0 "s_register_operand" "=t")
1015 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1016 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1017 "ftouizs%?\\t%0, %1"
1018 [(set_attr "predicable" "yes")
1019 (set_attr "predicable_short_it" "no")
1020 (set_attr "type" "f_cvtf2i")]
1021 )
1023 (define_insn "fixuns_truncdfsi2"
1024 [(set (match_operand:SI 0 "s_register_operand" "=t")
1025 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1026 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1027 "ftouizd%?\\t%0, %P1"
1028 [(set_attr "predicable" "yes")
1029 (set_attr "predicable_short_it" "no")
1030 (set_attr "type" "f_cvtf2i")]
1031 )
1034 (define_insn "*floatsisf2_vfp"
1035 [(set (match_operand:SF 0 "s_register_operand" "=t")
1036 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1037 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1038 "fsitos%?\\t%0, %1"
1039 [(set_attr "predicable" "yes")
1040 (set_attr "predicable_short_it" "no")
1041 (set_attr "type" "f_cvti2f")]
1042 )
1044 (define_insn "*floatsidf2_vfp"
1045 [(set (match_operand:DF 0 "s_register_operand" "=w")
1046 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1047 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1048 "fsitod%?\\t%P0, %1"
1049 [(set_attr "predicable" "yes")
1050 (set_attr "predicable_short_it" "no")
1051 (set_attr "type" "f_cvti2f")]
1052 )
1055 (define_insn "floatunssisf2"
1056 [(set (match_operand:SF 0 "s_register_operand" "=t")
1057 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1058 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1059 "fuitos%?\\t%0, %1"
1060 [(set_attr "predicable" "yes")
1061 (set_attr "predicable_short_it" "no")
1062 (set_attr "type" "f_cvti2f")]
1063 )
1065 (define_insn "floatunssidf2"
1066 [(set (match_operand:DF 0 "s_register_operand" "=w")
1067 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1068 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1069 "fuitod%?\\t%P0, %1"
1070 [(set_attr "predicable" "yes")
1071 (set_attr "predicable_short_it" "no")
1072 (set_attr "type" "f_cvti2f")]
1073 )
1076 ;; Sqrt insns.
1078 ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
1079 ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
1080 ; earlier.
1081 (define_insn "*sqrtsf2_vfp"
1082 [(set (match_operand:SF 0 "s_register_operand" "=&t,t")
1083 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
1084 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1085 "fsqrts%?\\t%0, %1"
1086 [(set_attr "predicable" "yes")
1087 (set_attr "predicable_short_it" "no")
1088 (set_attr "arch" "*,armv6_or_vfpv3")
1089 (set_attr "type" "fsqrts")]
1090 )
1092 (define_insn "*sqrtdf2_vfp"
1093 [(set (match_operand:DF 0 "s_register_operand" "=&w,w")
1094 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))]
1095 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1096 "fsqrtd%?\\t%P0, %P1"
1097 [(set_attr "predicable" "yes")
1098 (set_attr "predicable_short_it" "no")
1099 (set_attr "arch" "*,armv6_or_vfpv3")
1100 (set_attr "type" "fsqrtd")]
1101 )
1104 ;; Patterns to split/copy vfp condition flags.
1106 (define_insn "*movcc_vfp"
1107 [(set (reg CC_REGNUM)
1108 (reg VFPCC_REGNUM))]
1109 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1110 "fmstat%?"
1111 [(set_attr "conds" "set")
1112 (set_attr "type" "f_flag")]
1113 )
1115 (define_insn_and_split "*cmpsf_split_vfp"
1116 [(set (reg:CCFP CC_REGNUM)
1117 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
1118 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1119 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1120 "#"
1121 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1122 [(set (reg:CCFP VFPCC_REGNUM)
1123 (compare:CCFP (match_dup 0)
1124 (match_dup 1)))
1125 (set (reg:CCFP CC_REGNUM)
1126 (reg:CCFP VFPCC_REGNUM))]
1127 ""
1128 )
1130 (define_insn_and_split "*cmpsf_trap_split_vfp"
1131 [(set (reg:CCFPE CC_REGNUM)
1132 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
1133 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1134 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1135 "#"
1136 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1137 [(set (reg:CCFPE VFPCC_REGNUM)
1138 (compare:CCFPE (match_dup 0)
1139 (match_dup 1)))
1140 (set (reg:CCFPE CC_REGNUM)
1141 (reg:CCFPE VFPCC_REGNUM))]
1142 ""
1143 )
1145 (define_insn_and_split "*cmpdf_split_vfp"
1146 [(set (reg:CCFP CC_REGNUM)
1147 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
1148 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1149 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1150 "#"
1151 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1152 [(set (reg:CCFP VFPCC_REGNUM)
1153 (compare:CCFP (match_dup 0)
1154 (match_dup 1)))
1155 (set (reg:CCFP CC_REGNUM)
1156 (reg:CCFP VFPCC_REGNUM))]
1157 ""
1158 )
1160 (define_insn_and_split "*cmpdf_trap_split_vfp"
1161 [(set (reg:CCFPE CC_REGNUM)
1162 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
1163 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1164 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1165 "#"
1166 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1167 [(set (reg:CCFPE VFPCC_REGNUM)
1168 (compare:CCFPE (match_dup 0)
1169 (match_dup 1)))
1170 (set (reg:CCFPE CC_REGNUM)
1171 (reg:CCFPE VFPCC_REGNUM))]
1172 ""
1173 )
1176 ;; Comparison patterns
1178 (define_insn "*cmpsf_vfp"
1179 [(set (reg:CCFP VFPCC_REGNUM)
1180 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
1181 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1182 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1183 "@
1184 fcmps%?\\t%0, %1
1185 fcmpzs%?\\t%0"
1186 [(set_attr "predicable" "yes")
1187 (set_attr "predicable_short_it" "no")
1188 (set_attr "type" "fcmps")]
1189 )
1191 (define_insn "*cmpsf_trap_vfp"
1192 [(set (reg:CCFPE VFPCC_REGNUM)
1193 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
1194 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1195 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1196 "@
1197 fcmpes%?\\t%0, %1
1198 fcmpezs%?\\t%0"
1199 [(set_attr "predicable" "yes")
1200 (set_attr "predicable_short_it" "no")
1201 (set_attr "type" "fcmps")]
1202 )
1204 (define_insn "*cmpdf_vfp"
1205 [(set (reg:CCFP VFPCC_REGNUM)
1206 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
1207 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1208 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1209 "@
1210 fcmpd%?\\t%P0, %P1
1211 fcmpzd%?\\t%P0"
1212 [(set_attr "predicable" "yes")
1213 (set_attr "predicable_short_it" "no")
1214 (set_attr "type" "fcmpd")]
1215 )
1217 (define_insn "*cmpdf_trap_vfp"
1218 [(set (reg:CCFPE VFPCC_REGNUM)
1219 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
1220 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1221 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1222 "@
1223 fcmped%?\\t%P0, %P1
1224 fcmpezd%?\\t%P0"
1225 [(set_attr "predicable" "yes")
1226 (set_attr "predicable_short_it" "no")
1227 (set_attr "type" "fcmpd")]
1228 )
1230 ;; Fixed point to floating point conversions.
1231 (define_code_iterator FCVT [unsigned_float float])
1232 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1234 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1235 [(set (match_operand:SF 0 "s_register_operand" "=t")
1236 (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1237 (match_operand 2
1238 "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1239 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1240 "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
1241 [(set_attr "predicable" "yes")
1242 (set_attr "predicable_short_it" "no")
1243 (set_attr "type" "f_cvti2f")]
1244 )
1246 ;; Not the ideal way of implementing this. Ideally we would be able to split
1247 ;; this into a move to a DP register and then a vcvt.f64.i32
1248 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1249 [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1250 (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1251 (match_operand 2
1252 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1253 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1254 && !TARGET_VFP_SINGLE"
1255 "@
1256 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1257 vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1258 vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1259 [(set_attr "predicable" "yes")
1260 (set_attr "ce_count" "2")
1261 (set_attr "predicable_short_it" "no")
1262 (set_attr "type" "f_cvti2f")
1263 (set_attr "length" "8")]
1264 )
1266 (define_insn "*combine_vcvtf2i"
1267 [(set (match_operand:SI 0 "s_register_operand" "=r")
1268 (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
1269 (match_operand 2
1270 "const_double_vcvt_power_of_two" "Dp")))))]
1271 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1272 "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
1273 [(set_attr "predicable" "yes")
1274 (set_attr "predicable_short_it" "no")
1275 (set_attr "ce_count" "2")
1276 (set_attr "type" "f_cvtf2i")
1277 (set_attr "length" "8")]
1278 )
1280 ;; Store multiple insn used in function prologue.
1281 (define_insn "*push_multi_vfp"
1282 [(match_parallel 2 "multi_register_push"
1283 [(set (match_operand:BLK 0 "memory_operand" "=m")
1284 (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1285 UNSPEC_PUSH_MULT))])]
1286 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1287 "* return vfp_output_fstmd (operands);"
1288 [(set_attr "type" "f_stored")]
1289 )
1291 ;; VRINT round to integral instructions.
1292 ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
1293 ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
1294 ;; rintsf2, rintdf2.
1295 (define_insn "<vrint_pattern><SDF:mode>2"
1296 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1297 (unspec:SDF [(match_operand:SDF 1
1298 "register_operand" "<F_constraint>")]
1299 VRINT))]
1300 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1301 "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1302 [(set_attr "predicable" "<vrint_predicable>")
1303 (set_attr "predicable_short_it" "no")
1304 (set_attr "type" "f_rint<vfp_type>")
1305 (set_attr "conds" "<vrint_conds>")]
1306 )
1308 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
1309 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
1310 ;; operand will be returned when both operands are zero (i.e. they may not
1311 ;; honour signed zeroes), or when either operand is NaN. Therefore GCC
1312 ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
1313 ;; NaNs.
1315 (define_insn "smax<mode>3"
1316 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1317 (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1318 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1319 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1320 "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1321 [(set_attr "type" "f_minmax<vfp_type>")
1322 (set_attr "conds" "unconditional")]
1323 )
1325 (define_insn "smin<mode>3"
1326 [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1327 (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1328 (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1329 "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1330 "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1331 [(set_attr "type" "f_minmax<vfp_type>")
1332 (set_attr "conds" "unconditional")]
1333 )
1335 ;; Write Floating-point Status and Control Register.
1336 (define_insn "set_fpscr"
1337 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
1338 "TARGET_VFP && TARGET_HARD_FLOAT"
1339 "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
1340 [(set_attr "type" "mrs")])
1342 ;; Read Floating-point Status and Control Register.
1343 (define_insn "get_fpscr"
1344 [(set (match_operand:SI 0 "register_operand" "=r")
1345 (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
1346 "TARGET_VFP && TARGET_HARD_FLOAT"
1347 "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
1348 [(set_attr "type" "mrs")])
1351 ;; Unimplemented insns:
1352 ;; fldm*
1353 ;; fstm*
1354 ;; fmdhr et al (VFPv1)
1355 ;; Support for xD (single precision only) variants.
1356 ;; fmrrs, fmsrr