1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts
;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges
;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras
;
119 /* Number of instructions combined in this function. */
121 static int combine_successes
;
123 /* Totals over entire compilation. */
125 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs
;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs
;
144 typedef struct reg_stat_struct
{
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label
;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
253 DEF_VEC_O(reg_stat_type
);
254 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
256 static VEC(reg_stat_type
,heap
) *reg_stat
;
258 /* Record the luid of the last insn that invalidated memory
259 (anything that writes memory, and subroutine calls, but not pushes). */
261 static int mem_last_set
;
263 /* Record the luid of the last CALL_INSN
264 so we can tell whether a potential combination crosses any calls. */
266 static int last_call_luid
;
268 /* When `subst' is called, this is the insn that is being modified
269 (by combining in a previous insn). The PATTERN of this insn
270 is still the old pattern partially modified and it should not be
271 looked at, but this may be used to examine the successors of the insn
272 to judge whether a simplification is valid. */
274 static rtx subst_insn
;
276 /* This is the lowest LUID that `subst' is currently dealing with.
277 get_last_value will not return a value if the register was set at or
278 after this LUID. If not for this mechanism, we could get confused if
279 I2 or I1 in try_combine were an insn that used the old value of a register
280 to obtain a new value. In that case, we might erroneously get the
281 new value of the register when we wanted the old one. */
283 static int subst_low_luid
;
285 /* This contains any hard registers that are used in newpat; reg_dead_at_p
286 must consider all these registers to be always live. */
288 static HARD_REG_SET newpat_used_regs
;
290 /* This is an insn to which a LOG_LINKS entry has been added. If this
291 insn is the earlier than I2 or I3, combine should rescan starting at
294 static rtx added_links_insn
;
296 /* Basic block in which we are performing combines. */
297 static basic_block this_basic_block
;
298 static bool optimize_this_for_speed_p
;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int max_uid_known
;
305 /* The following array records the insn_rtx_cost for every insn
306 in the instruction stream. */
308 static int *uid_insn_cost
;
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
315 struct insn_link
*next
;
318 static struct insn_link
**uid_log_links
;
320 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
321 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
323 #define FOR_EACH_LOG_LINK(L, INSN) \
324 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
326 /* Links for LOG_LINKS are allocated from this obstack. */
328 static struct obstack insn_link_obstack
;
330 /* Allocate a link. */
332 static inline struct insn_link
*
333 alloc_insn_link (rtx insn
, struct insn_link
*next
)
336 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
337 sizeof (struct insn_link
));
343 /* Incremented for each basic block. */
345 static int label_tick
;
347 /* Reset to label_tick for each extended basic block in scanning order. */
349 static int label_tick_ebb_start
;
351 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
352 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
354 static enum machine_mode nonzero_bits_mode
;
356 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
357 be safely used. It is zero while computing them and after combine has
358 completed. This former test prevents propagating values based on
359 previously set values, which can be incorrect if a variable is modified
362 static int nonzero_sign_valid
;
365 /* Record one modification to rtl structure
366 to be undone by storing old_contents into *where. */
368 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
374 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
375 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
378 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
379 num_undo says how many are currently recorded.
381 other_insn is nonzero if we have modified some other insn in the process
382 of working on subst_insn. It must be verified too. */
391 static struct undobuf undobuf
;
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences
;
398 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
400 unsigned HOST_WIDE_INT
,
401 unsigned HOST_WIDE_INT
*);
402 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
404 unsigned int, unsigned int *);
405 static void do_SUBST (rtx
*, rtx
);
406 static void do_SUBST_INT (int *, int);
407 static void init_reg_last (void);
408 static void setup_incoming_promotions (rtx
);
409 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
410 static int cant_combine_insn_p (rtx
);
411 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
412 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
413 static int contains_muldiv (rtx
);
414 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
415 static void undo_all (void);
416 static void undo_commit (void);
417 static rtx
*find_split_point (rtx
*, rtx
, bool);
418 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
419 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
420 static rtx
simplify_if_then_else (rtx
);
421 static rtx
simplify_set (rtx
);
422 static rtx
simplify_logical (rtx
);
423 static rtx
expand_compound_operation (rtx
);
424 static const_rtx
expand_field_assignment (const_rtx
);
425 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
426 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
427 static rtx
extract_left_shift (rtx
, int);
428 static rtx
make_compound_operation (rtx
, enum rtx_code
);
429 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
430 unsigned HOST_WIDE_INT
*);
431 static rtx
canon_reg_for_combine (rtx
, rtx
);
432 static rtx
force_to_mode (rtx
, enum machine_mode
,
433 unsigned HOST_WIDE_INT
, int);
434 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
435 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
436 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
437 static rtx
make_field_assignment (rtx
);
438 static rtx
apply_distributive_law (rtx
);
439 static rtx
distribute_and_simplify_rtx (rtx
, int);
440 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
441 unsigned HOST_WIDE_INT
);
442 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
443 unsigned HOST_WIDE_INT
);
444 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
445 HOST_WIDE_INT
, enum machine_mode
, int *);
446 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
447 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
449 static int recog_for_combine (rtx
*, rtx
, rtx
*);
450 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
451 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
452 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
453 static void update_table_tick (rtx
);
454 static void record_value_for_reg (rtx
, rtx
, rtx
);
455 static void check_promoted_subreg (rtx
, rtx
);
456 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
457 static void record_dead_and_set_regs (rtx
);
458 static int get_last_value_validate (rtx
*, rtx
, int, int);
459 static rtx
get_last_value (const_rtx
);
460 static int use_crosses_set_p (const_rtx
, int);
461 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
462 static int reg_dead_at_p (rtx
, rtx
);
463 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
464 static int reg_bitfield_target_p (rtx
, rtx
);
465 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
466 static void distribute_links (struct insn_link
*);
467 static void mark_used_regs_combine (rtx
);
468 static void record_promoted_value (rtx
, rtx
);
469 static int unmentioned_reg_p_1 (rtx
*, void *);
470 static bool unmentioned_reg_p (rtx
, rtx
);
471 static int record_truncated_value (rtx
*, void *);
472 static void record_truncated_values (rtx
*, void *);
473 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
474 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
477 /* It is not safe to use ordinary gen_lowpart in combine.
478 See comments in gen_lowpart_for_combine. */
479 #undef RTL_HOOKS_GEN_LOWPART
480 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
482 /* Our implementation of gen_lowpart never emits a new pseudo. */
483 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
484 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
486 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
487 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
489 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
490 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
492 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
493 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
495 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
498 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
499 PATTERN can not be split. Otherwise, it returns an insn sequence.
500 This is a wrapper around split_insns which ensures that the
501 reg_stat vector is made larger if the splitter creates a new
505 combine_split_insns (rtx pattern
, rtx insn
)
510 ret
= split_insns (pattern
, insn
);
511 nregs
= max_reg_num ();
512 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
513 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
517 /* This is used by find_single_use to locate an rtx in LOC that
518 contains exactly one use of DEST, which is typically either a REG
519 or CC0. It returns a pointer to the innermost rtx expression
520 containing DEST. Appearances of DEST that are being used to
521 totally replace it are not counted. */
524 find_single_use_1 (rtx dest
, rtx
*loc
)
527 enum rtx_code code
= GET_CODE (x
);
545 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
546 of a REG that occupies all of the REG, the insn uses DEST if
547 it is mentioned in the destination or the source. Otherwise, we
548 need just check the source. */
549 if (GET_CODE (SET_DEST (x
)) != CC0
550 && GET_CODE (SET_DEST (x
)) != PC
551 && !REG_P (SET_DEST (x
))
552 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
553 && REG_P (SUBREG_REG (SET_DEST (x
)))
554 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
555 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
556 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
557 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
560 return find_single_use_1 (dest
, &SET_SRC (x
));
564 return find_single_use_1 (dest
, &XEXP (x
, 0));
570 /* If it wasn't one of the common cases above, check each expression and
571 vector of this code. Look for a unique usage of DEST. */
573 fmt
= GET_RTX_FORMAT (code
);
574 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
578 if (dest
== XEXP (x
, i
)
579 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
580 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
583 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
586 result
= this_result
;
587 else if (this_result
)
588 /* Duplicate usage. */
591 else if (fmt
[i
] == 'E')
595 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
597 if (XVECEXP (x
, i
, j
) == dest
599 && REG_P (XVECEXP (x
, i
, j
))
600 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
603 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
606 result
= this_result
;
607 else if (this_result
)
617 /* See if DEST, produced in INSN, is used only a single time in the
618 sequel. If so, return a pointer to the innermost rtx expression in which
621 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
623 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
624 care about REG_DEAD notes or LOG_LINKS.
626 Otherwise, we find the single use by finding an insn that has a
627 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
628 only referenced once in that insn, we know that it must be the first
629 and last insn referencing DEST. */
632 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
637 struct insn_link
*link
;
642 next
= NEXT_INSN (insn
);
644 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
647 result
= find_single_use_1 (dest
, &PATTERN (next
));
657 bb
= BLOCK_FOR_INSN (insn
);
658 for (next
= NEXT_INSN (insn
);
659 next
&& BLOCK_FOR_INSN (next
) == bb
;
660 next
= NEXT_INSN (next
))
661 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
663 FOR_EACH_LOG_LINK (link
, next
)
664 if (link
->insn
== insn
)
669 result
= find_single_use_1 (dest
, &PATTERN (next
));
679 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
680 insn. The substitution can be undone by undo_all. If INTO is already
681 set to NEWVAL, do not record this change. Because computing NEWVAL might
682 also call SUBST, we have to compute it before we put anything into
686 do_SUBST (rtx
*into
, rtx newval
)
691 if (oldval
== newval
)
694 /* We'd like to catch as many invalid transformations here as
695 possible. Unfortunately, there are way too many mode changes
696 that are perfectly valid, so we'd waste too much effort for
697 little gain doing the checks here. Focus on catching invalid
698 transformations involving integer constants. */
699 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
700 && CONST_INT_P (newval
))
702 /* Sanity check that we're replacing oldval with a CONST_INT
703 that is a valid sign-extension for the original mode. */
704 gcc_assert (INTVAL (newval
)
705 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
707 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
708 CONST_INT is not valid, because after the replacement, the
709 original mode would be gone. Unfortunately, we can't tell
710 when do_SUBST is called to replace the operand thereof, so we
711 perform this test on oldval instead, checking whether an
712 invalid replacement took place before we got here. */
713 gcc_assert (!(GET_CODE (oldval
) == SUBREG
714 && CONST_INT_P (SUBREG_REG (oldval
))));
715 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
716 && CONST_INT_P (XEXP (oldval
, 0))));
720 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
722 buf
= XNEW (struct undo
);
724 buf
->kind
= UNDO_RTX
;
726 buf
->old_contents
.r
= oldval
;
729 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
732 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
734 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
735 for the value of a HOST_WIDE_INT value (including CONST_INT) is
739 do_SUBST_INT (int *into
, int newval
)
744 if (oldval
== newval
)
748 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
750 buf
= XNEW (struct undo
);
752 buf
->kind
= UNDO_INT
;
754 buf
->old_contents
.i
= oldval
;
757 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
760 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
762 /* Similar to SUBST, but just substitute the mode. This is used when
763 changing the mode of a pseudo-register, so that any other
764 references to the entry in the regno_reg_rtx array will change as
768 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
771 enum machine_mode oldval
= GET_MODE (*into
);
773 if (oldval
== newval
)
777 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
779 buf
= XNEW (struct undo
);
781 buf
->kind
= UNDO_MODE
;
783 buf
->old_contents
.m
= oldval
;
784 adjust_reg_mode (*into
, newval
);
786 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
789 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
792 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
795 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
798 struct insn_link
* oldval
= *into
;
800 if (oldval
== newval
)
804 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
806 buf
= XNEW (struct undo
);
808 buf
->kind
= UNDO_LINKS
;
810 buf
->old_contents
.l
= oldval
;
813 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
816 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
819 /* Subroutine of try_combine. Determine whether the replacement patterns
820 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
821 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
822 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
823 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
824 of all the instructions can be estimated and the replacements are more
825 expensive than the original sequence. */
828 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
829 rtx newi2pat
, rtx newotherpat
)
831 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
832 int new_i2_cost
, new_i3_cost
;
833 int old_cost
, new_cost
;
835 /* Lookup the original insn_rtx_costs. */
836 i2_cost
= INSN_COST (i2
);
837 i3_cost
= INSN_COST (i3
);
841 i1_cost
= INSN_COST (i1
);
844 i0_cost
= INSN_COST (i0
);
845 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
846 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
850 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
851 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
857 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
858 i1_cost
= i0_cost
= 0;
861 /* Calculate the replacement insn_rtx_costs. */
862 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
865 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
866 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
867 ? new_i2_cost
+ new_i3_cost
: 0;
871 new_cost
= new_i3_cost
;
875 if (undobuf
.other_insn
)
877 int old_other_cost
, new_other_cost
;
879 old_other_cost
= INSN_COST (undobuf
.other_insn
);
880 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
881 if (old_other_cost
> 0 && new_other_cost
> 0)
883 old_cost
+= old_other_cost
;
884 new_cost
+= new_other_cost
;
890 /* Disallow this combination if both new_cost and old_cost are greater than
891 zero, and new_cost is greater than old cost. */
892 if (old_cost
> 0 && new_cost
> old_cost
)
899 "rejecting combination of insns %d, %d, %d and %d\n",
900 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
902 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
903 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
908 "rejecting combination of insns %d, %d and %d\n",
909 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
910 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
911 i1_cost
, i2_cost
, i3_cost
, old_cost
);
916 "rejecting combination of insns %d and %d\n",
917 INSN_UID (i2
), INSN_UID (i3
));
918 fprintf (dump_file
, "original costs %d + %d = %d\n",
919 i2_cost
, i3_cost
, old_cost
);
924 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
925 new_i2_cost
, new_i3_cost
, new_cost
);
928 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
934 /* Update the uid_insn_cost array with the replacement costs. */
935 INSN_COST (i2
) = new_i2_cost
;
936 INSN_COST (i3
) = new_i3_cost
;
948 /* Delete any insns that copy a register to itself. */
951 delete_noop_moves (void)
958 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
960 next
= NEXT_INSN (insn
);
961 if (INSN_P (insn
) && noop_move_p (insn
))
964 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
966 delete_insn_and_edges (insn
);
973 /* Fill in log links field for all insns. */
976 create_log_links (void)
980 df_ref
*def_vec
, *use_vec
;
982 next_use
= XCNEWVEC (rtx
, max_reg_num ());
984 /* Pass through each block from the end, recording the uses of each
985 register and establishing log links when def is encountered.
986 Note that we do not clear next_use array in order to save time,
987 so we have to test whether the use is in the same basic block as def.
989 There are a few cases below when we do not consider the definition or
990 usage -- these are taken from original flow.c did. Don't ask me why it is
991 done this way; I don't know and if it works, I don't want to know. */
995 FOR_BB_INSNS_REVERSE (bb
, insn
)
997 if (!NONDEBUG_INSN_P (insn
))
1000 /* Log links are created only once. */
1001 gcc_assert (!LOG_LINKS (insn
));
1003 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1005 df_ref def
= *def_vec
;
1006 int regno
= DF_REF_REGNO (def
);
1009 if (!next_use
[regno
])
1012 /* Do not consider if it is pre/post modification in MEM. */
1013 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1016 /* Do not make the log link for frame pointer. */
1017 if ((regno
== FRAME_POINTER_REGNUM
1018 && (! reload_completed
|| frame_pointer_needed
))
1019 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1020 || (regno
== HARD_FRAME_POINTER_REGNUM
1021 && (! reload_completed
|| frame_pointer_needed
))
1023 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1024 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1029 use_insn
= next_use
[regno
];
1030 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1034 We don't build a LOG_LINK for hard registers contained
1035 in ASM_OPERANDs. If these registers get replaced,
1036 we might wind up changing the semantics of the insn,
1037 even if reload can make what appear to be valid
1038 assignments later. */
1039 if (regno
>= FIRST_PSEUDO_REGISTER
1040 || asm_noperands (PATTERN (use_insn
)) < 0)
1042 /* Don't add duplicate links between instructions. */
1043 struct insn_link
*links
;
1044 FOR_EACH_LOG_LINK (links
, use_insn
)
1045 if (insn
== links
->insn
)
1049 LOG_LINKS (use_insn
)
1050 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1053 next_use
[regno
] = NULL_RTX
;
1056 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1058 df_ref use
= *use_vec
;
1059 int regno
= DF_REF_REGNO (use
);
1061 /* Do not consider the usage of the stack pointer
1062 by function call. */
1063 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1066 next_use
[regno
] = insn
;
1074 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1075 true if we found a LOG_LINK that proves that A feeds B. This only works
1076 if there are no instructions between A and B which could have a link
1077 depending on A, since in that case we would not record a link for B.
1078 We also check the implicit dependency created by a cc0 setter/user
1082 insn_a_feeds_b (rtx a
, rtx b
)
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, b
)
1086 if (links
->insn
== a
)
1095 /* Main entry point for combiner. F is the first insn of the function.
1096 NREGS is the first unused pseudo-reg number.
1098 Return nonzero if the combiner has turned an indirect jump
1099 instruction into a direct jump. */
1101 combine_instructions (rtx f
, unsigned int nregs
)
1107 struct insn_link
*links
, *nextlinks
;
1109 basic_block last_bb
;
1111 int new_direct_jump_p
= 0;
1113 for (first
= f
; first
&& !INSN_P (first
); )
1114 first
= NEXT_INSN (first
);
1118 combine_attempts
= 0;
1121 combine_successes
= 0;
1123 rtl_hooks
= combine_rtl_hooks
;
1125 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1127 init_recog_no_volatile ();
1129 /* Allocate array for insn info. */
1130 max_uid_known
= get_max_uid ();
1131 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1132 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1133 gcc_obstack_init (&insn_link_obstack
);
1135 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1137 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1138 problems when, for example, we have j <<= 1 in a loop. */
1140 nonzero_sign_valid
= 0;
1141 label_tick
= label_tick_ebb_start
= 1;
1143 /* Scan all SETs and see if we can deduce anything about what
1144 bits are known to be zero for some registers and how many copies
1145 of the sign bit are known to exist for those registers.
1147 Also set any known values so that we can use it while searching
1148 for what bits are known to be set. */
1150 setup_incoming_promotions (first
);
1151 /* Allow the entry block and the first block to fall into the same EBB.
1152 Conceptually the incoming promotions are assigned to the entry block. */
1153 last_bb
= ENTRY_BLOCK_PTR
;
1155 create_log_links ();
1156 FOR_EACH_BB (this_basic_block
)
1158 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1163 if (!single_pred_p (this_basic_block
)
1164 || single_pred (this_basic_block
) != last_bb
)
1165 label_tick_ebb_start
= label_tick
;
1166 last_bb
= this_basic_block
;
1168 FOR_BB_INSNS (this_basic_block
, insn
)
1169 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1175 subst_low_luid
= DF_INSN_LUID (insn
);
1178 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1180 record_dead_and_set_regs (insn
);
1183 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1184 if (REG_NOTE_KIND (links
) == REG_INC
)
1185 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1189 /* Record the current insn_rtx_cost of this instruction. */
1190 if (NONJUMP_INSN_P (insn
))
1191 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1192 optimize_this_for_speed_p
);
1194 fprintf(dump_file
, "insn_cost %d: %d\n",
1195 INSN_UID (insn
), INSN_COST (insn
));
1199 nonzero_sign_valid
= 1;
1201 /* Now scan all the insns in forward order. */
1202 label_tick
= label_tick_ebb_start
= 1;
1204 setup_incoming_promotions (first
);
1205 last_bb
= ENTRY_BLOCK_PTR
;
1207 FOR_EACH_BB (this_basic_block
)
1209 rtx last_combined_insn
= NULL_RTX
;
1210 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1215 if (!single_pred_p (this_basic_block
)
1216 || single_pred (this_basic_block
) != last_bb
)
1217 label_tick_ebb_start
= label_tick
;
1218 last_bb
= this_basic_block
;
1220 rtl_profile_for_bb (this_basic_block
);
1221 for (insn
= BB_HEAD (this_basic_block
);
1222 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1223 insn
= next
? next
: NEXT_INSN (insn
))
1226 if (NONDEBUG_INSN_P (insn
))
1228 while (last_combined_insn
1229 && INSN_DELETED_P (last_combined_insn
))
1230 last_combined_insn
= PREV_INSN (last_combined_insn
);
1231 if (last_combined_insn
== NULL_RTX
1232 || BARRIER_P (last_combined_insn
)
1233 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1234 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1235 last_combined_insn
= insn
;
1237 /* See if we know about function return values before this
1238 insn based upon SUBREG flags. */
1239 check_promoted_subreg (insn
, PATTERN (insn
));
1241 /* See if we can find hardregs and subreg of pseudos in
1242 narrower modes. This could help turning TRUNCATEs
1244 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1246 /* Try this insn with each insn it links back to. */
1248 FOR_EACH_LOG_LINK (links
, insn
)
1249 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1250 NULL_RTX
, &new_direct_jump_p
,
1251 last_combined_insn
)) != 0)
1254 /* Try each sequence of three linked insns ending with this one. */
1256 FOR_EACH_LOG_LINK (links
, insn
)
1258 rtx link
= links
->insn
;
1260 /* If the linked insn has been replaced by a note, then there
1261 is no point in pursuing this chain any further. */
1265 FOR_EACH_LOG_LINK (nextlinks
, link
)
1266 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1267 NULL_RTX
, &new_direct_jump_p
,
1268 last_combined_insn
)) != 0)
1273 /* Try to combine a jump insn that uses CC0
1274 with a preceding insn that sets CC0, and maybe with its
1275 logical predecessor as well.
1276 This is how we make decrement-and-branch insns.
1277 We need this special code because data flow connections
1278 via CC0 do not get entered in LOG_LINKS. */
1281 && (prev
= prev_nonnote_insn (insn
)) != 0
1282 && NONJUMP_INSN_P (prev
)
1283 && sets_cc0_p (PATTERN (prev
)))
1285 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1287 last_combined_insn
)) != 0)
1290 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1291 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1292 NULL_RTX
, &new_direct_jump_p
,
1293 last_combined_insn
)) != 0)
1297 /* Do the same for an insn that explicitly references CC0. */
1298 if (NONJUMP_INSN_P (insn
)
1299 && (prev
= prev_nonnote_insn (insn
)) != 0
1300 && NONJUMP_INSN_P (prev
)
1301 && sets_cc0_p (PATTERN (prev
))
1302 && GET_CODE (PATTERN (insn
)) == SET
1303 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1305 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1307 last_combined_insn
)) != 0)
1310 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1311 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1312 NULL_RTX
, &new_direct_jump_p
,
1313 last_combined_insn
)) != 0)
1317 /* Finally, see if any of the insns that this insn links to
1318 explicitly references CC0. If so, try this insn, that insn,
1319 and its predecessor if it sets CC0. */
1320 FOR_EACH_LOG_LINK (links
, insn
)
1321 if (NONJUMP_INSN_P (links
->insn
)
1322 && GET_CODE (PATTERN (links
->insn
)) == SET
1323 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1324 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1325 && NONJUMP_INSN_P (prev
)
1326 && sets_cc0_p (PATTERN (prev
))
1327 && (next
= try_combine (insn
, links
->insn
,
1328 prev
, NULL_RTX
, &new_direct_jump_p
,
1329 last_combined_insn
)) != 0)
1333 /* Try combining an insn with two different insns whose results it
1335 FOR_EACH_LOG_LINK (links
, insn
)
1336 for (nextlinks
= links
->next
; nextlinks
;
1337 nextlinks
= nextlinks
->next
)
1338 if ((next
= try_combine (insn
, links
->insn
,
1339 nextlinks
->insn
, NULL_RTX
,
1341 last_combined_insn
)) != 0)
1344 /* Try four-instruction combinations. */
1345 FOR_EACH_LOG_LINK (links
, insn
)
1347 struct insn_link
*next1
;
1348 rtx link
= links
->insn
;
1350 /* If the linked insn has been replaced by a note, then there
1351 is no point in pursuing this chain any further. */
1355 FOR_EACH_LOG_LINK (next1
, link
)
1357 rtx link1
= next1
->insn
;
1360 /* I0 -> I1 -> I2 -> I3. */
1361 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1362 if ((next
= try_combine (insn
, link
, link1
,
1365 last_combined_insn
)) != 0)
1367 /* I0, I1 -> I2, I2 -> I3. */
1368 for (nextlinks
= next1
->next
; nextlinks
;
1369 nextlinks
= nextlinks
->next
)
1370 if ((next
= try_combine (insn
, link
, link1
,
1373 last_combined_insn
)) != 0)
1377 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1379 rtx link1
= next1
->insn
;
1382 /* I0 -> I2; I1, I2 -> I3. */
1383 FOR_EACH_LOG_LINK (nextlinks
, link
)
1384 if ((next
= try_combine (insn
, link
, link1
,
1387 last_combined_insn
)) != 0)
1389 /* I0 -> I1; I1, I2 -> I3. */
1390 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1391 if ((next
= try_combine (insn
, link
, link1
,
1394 last_combined_insn
)) != 0)
1399 /* Try this insn with each REG_EQUAL note it links back to. */
1400 FOR_EACH_LOG_LINK (links
, insn
)
1403 rtx temp
= links
->insn
;
1404 if ((set
= single_set (temp
)) != 0
1405 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1406 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1407 /* Avoid using a register that may already been marked
1408 dead by an earlier instruction. */
1409 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1410 && (GET_MODE (note
) == VOIDmode
1411 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1412 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1414 /* Temporarily replace the set's source with the
1415 contents of the REG_EQUAL note. The insn will
1416 be deleted or recognized by try_combine. */
1417 rtx orig
= SET_SRC (set
);
1418 SET_SRC (set
) = note
;
1420 i2mod_old_rhs
= copy_rtx (orig
);
1421 i2mod_new_rhs
= copy_rtx (note
);
1422 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1424 last_combined_insn
);
1428 SET_SRC (set
) = orig
;
1433 record_dead_and_set_regs (insn
);
1441 default_rtl_profile ();
1443 new_direct_jump_p
|= purge_all_dead_edges ();
1444 delete_noop_moves ();
1447 obstack_free (&insn_link_obstack
, NULL
);
1448 free (uid_log_links
);
1449 free (uid_insn_cost
);
1450 VEC_free (reg_stat_type
, heap
, reg_stat
);
1453 struct undo
*undo
, *next
;
1454 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1462 total_attempts
+= combine_attempts
;
1463 total_merges
+= combine_merges
;
1464 total_extras
+= combine_extras
;
1465 total_successes
+= combine_successes
;
1467 nonzero_sign_valid
= 0;
1468 rtl_hooks
= general_rtl_hooks
;
1470 /* Make recognizer allow volatile MEMs again. */
1473 return new_direct_jump_p
;
1476 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1479 init_reg_last (void)
1484 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1485 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1488 /* Set up any promoted values for incoming argument registers. */
1491 setup_incoming_promotions (rtx first
)
1494 bool strictly_local
= false;
1496 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1497 arg
= DECL_CHAIN (arg
))
1499 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1501 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1503 /* Only continue if the incoming argument is in a register. */
1507 /* Determine, if possible, whether all call sites of the current
1508 function lie within the current compilation unit. (This does
1509 take into account the exporting of a function via taking its
1510 address, and so forth.) */
1511 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1513 /* The mode and signedness of the argument before any promotions happen
1514 (equal to the mode of the pseudo holding it at that stage). */
1515 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1516 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1518 /* The mode and signedness of the argument after any source language and
1519 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1520 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1521 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1523 /* The mode and signedness of the argument as it is actually passed,
1524 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1525 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1526 TREE_TYPE (cfun
->decl
), 0);
1528 /* The mode of the register in which the argument is being passed. */
1529 mode4
= GET_MODE (reg
);
1531 /* Eliminate sign extensions in the callee when:
1532 (a) A mode promotion has occurred; */
1535 /* (b) The mode of the register is the same as the mode of
1536 the argument as it is passed; */
1539 /* (c) There's no language level extension; */
1542 /* (c.1) All callers are from the current compilation unit. If that's
1543 the case we don't have to rely on an ABI, we only have to know
1544 what we're generating right now, and we know that we will do the
1545 mode1 to mode2 promotion with the given sign. */
1546 else if (!strictly_local
)
1548 /* (c.2) The combination of the two promotions is useful. This is
1549 true when the signs match, or if the first promotion is unsigned.
1550 In the later case, (sign_extend (zero_extend x)) is the same as
1551 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1557 /* Record that the value was promoted from mode1 to mode3,
1558 so that any sign extension at the head of the current
1559 function may be eliminated. */
1560 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1561 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1562 record_value_for_reg (reg
, first
, x
);
1566 /* Called via note_stores. If X is a pseudo that is narrower than
1567 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1569 If we are setting only a portion of X and we can't figure out what
1570 portion, assume all bits will be used since we don't know what will
1573 Similarly, set how many bits of X are known to be copies of the sign bit
1574 at all locations in the function. This is the smallest number implied
1578 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1580 rtx insn
= (rtx
) data
;
1584 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1585 /* If this register is undefined at the start of the file, we can't
1586 say what its contents were. */
1587 && ! REGNO_REG_SET_P
1588 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1589 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1591 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1593 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1595 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1596 rsp
->sign_bit_copies
= 1;
1600 /* If this register is being initialized using itself, and the
1601 register is uninitialized in this basic block, and there are
1602 no LOG_LINKS which set the register, then part of the
1603 register is uninitialized. In that case we can't assume
1604 anything about the number of nonzero bits.
1606 ??? We could do better if we checked this in
1607 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1608 could avoid making assumptions about the insn which initially
1609 sets the register, while still using the information in other
1610 insns. We would have to be careful to check every insn
1611 involved in the combination. */
1614 && reg_referenced_p (x
, PATTERN (insn
))
1615 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1618 struct insn_link
*link
;
1620 FOR_EACH_LOG_LINK (link
, insn
)
1621 if (dead_or_set_p (link
->insn
, x
))
1625 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1626 rsp
->sign_bit_copies
= 1;
1631 /* If this is a complex assignment, see if we can convert it into a
1632 simple assignment. */
1633 set
= expand_field_assignment (set
);
1635 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1636 set what we know about X. */
1638 if (SET_DEST (set
) == x
1639 || (paradoxical_subreg_p (SET_DEST (set
))
1640 && SUBREG_REG (SET_DEST (set
)) == x
))
1642 rtx src
= SET_SRC (set
);
1644 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1645 /* If X is narrower than a word and SRC is a non-negative
1646 constant that would appear negative in the mode of X,
1647 sign-extend it for use in reg_stat[].nonzero_bits because some
1648 machines (maybe most) will actually do the sign-extension
1649 and this is the conservative approach.
1651 ??? For 2.5, try to tighten up the MD files in this regard
1652 instead of this kludge. */
1654 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1655 && CONST_INT_P (src
)
1657 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1658 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1661 /* Don't call nonzero_bits if it cannot change anything. */
1662 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1663 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1664 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1665 if (rsp
->sign_bit_copies
== 0
1666 || rsp
->sign_bit_copies
> num
)
1667 rsp
->sign_bit_copies
= num
;
1671 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1672 rsp
->sign_bit_copies
= 1;
1677 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1678 optionally insns that were previously combined into I3 or that will be
1679 combined into the merger of INSN and I3. The order is PRED, PRED2,
1680 INSN, SUCC, SUCC2, I3.
1682 Return 0 if the combination is not allowed for any reason.
1684 If the combination is allowed, *PDEST will be set to the single
1685 destination of INSN and *PSRC to the single source, and this function
1689 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1690 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1691 rtx
*pdest
, rtx
*psrc
)
1700 bool all_adjacent
= true;
1701 int (*is_volatile_p
) (const_rtx
);
1707 if (next_active_insn (succ2
) != i3
)
1708 all_adjacent
= false;
1709 if (next_active_insn (succ
) != succ2
)
1710 all_adjacent
= false;
1712 else if (next_active_insn (succ
) != i3
)
1713 all_adjacent
= false;
1714 if (next_active_insn (insn
) != succ
)
1715 all_adjacent
= false;
1717 else if (next_active_insn (insn
) != i3
)
1718 all_adjacent
= false;
1720 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1721 or a PARALLEL consisting of such a SET and CLOBBERs.
1723 If INSN has CLOBBER parallel parts, ignore them for our processing.
1724 By definition, these happen during the execution of the insn. When it
1725 is merged with another insn, all bets are off. If they are, in fact,
1726 needed and aren't also supplied in I3, they may be added by
1727 recog_for_combine. Otherwise, it won't match.
1729 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1732 Get the source and destination of INSN. If more than one, can't
1735 if (GET_CODE (PATTERN (insn
)) == SET
)
1736 set
= PATTERN (insn
);
1737 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1738 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1740 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1742 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1744 switch (GET_CODE (elt
))
1746 /* This is important to combine floating point insns
1747 for the SH4 port. */
1749 /* Combining an isolated USE doesn't make sense.
1750 We depend here on combinable_i3pat to reject them. */
1751 /* The code below this loop only verifies that the inputs of
1752 the SET in INSN do not change. We call reg_set_between_p
1753 to verify that the REG in the USE does not change between
1755 If the USE in INSN was for a pseudo register, the matching
1756 insn pattern will likely match any register; combining this
1757 with any other USE would only be safe if we knew that the
1758 used registers have identical values, or if there was
1759 something to tell them apart, e.g. different modes. For
1760 now, we forgo such complicated tests and simply disallow
1761 combining of USES of pseudo registers with any other USE. */
1762 if (REG_P (XEXP (elt
, 0))
1763 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1765 rtx i3pat
= PATTERN (i3
);
1766 int i
= XVECLEN (i3pat
, 0) - 1;
1767 unsigned int regno
= REGNO (XEXP (elt
, 0));
1771 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1773 if (GET_CODE (i3elt
) == USE
1774 && REG_P (XEXP (i3elt
, 0))
1775 && (REGNO (XEXP (i3elt
, 0)) == regno
1776 ? reg_set_between_p (XEXP (elt
, 0),
1777 PREV_INSN (insn
), i3
)
1778 : regno
>= FIRST_PSEUDO_REGISTER
))
1785 /* We can ignore CLOBBERs. */
1790 /* Ignore SETs whose result isn't used but not those that
1791 have side-effects. */
1792 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1793 && insn_nothrow_p (insn
)
1794 && !side_effects_p (elt
))
1797 /* If we have already found a SET, this is a second one and
1798 so we cannot combine with this insn. */
1806 /* Anything else means we can't combine. */
1812 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1813 so don't do anything with it. */
1814 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1823 /* The simplification in expand_field_assignment may call back to
1824 get_last_value, so set safe guard here. */
1825 subst_low_luid
= DF_INSN_LUID (insn
);
1827 set
= expand_field_assignment (set
);
1828 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1830 /* Don't eliminate a store in the stack pointer. */
1831 if (dest
== stack_pointer_rtx
1832 /* Don't combine with an insn that sets a register to itself if it has
1833 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1834 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1835 /* Can't merge an ASM_OPERANDS. */
1836 || GET_CODE (src
) == ASM_OPERANDS
1837 /* Can't merge a function call. */
1838 || GET_CODE (src
) == CALL
1839 /* Don't eliminate a function call argument. */
1841 && (find_reg_fusage (i3
, USE
, dest
)
1843 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1844 && global_regs
[REGNO (dest
)])))
1845 /* Don't substitute into an incremented register. */
1846 || FIND_REG_INC_NOTE (i3
, dest
)
1847 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1848 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1849 /* Don't substitute into a non-local goto, this confuses CFG. */
1850 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1851 /* Make sure that DEST is not used after SUCC but before I3. */
1854 && (reg_used_between_p (dest
, succ2
, i3
)
1855 || reg_used_between_p (dest
, succ
, succ2
)))
1856 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1857 /* Make sure that the value that is to be substituted for the register
1858 does not use any registers whose values alter in between. However,
1859 If the insns are adjacent, a use can't cross a set even though we
1860 think it might (this can happen for a sequence of insns each setting
1861 the same destination; last_set of that register might point to
1862 a NOTE). If INSN has a REG_EQUIV note, the register is always
1863 equivalent to the memory so the substitution is valid even if there
1864 are intervening stores. Also, don't move a volatile asm or
1865 UNSPEC_VOLATILE across any other insns. */
1868 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1869 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1870 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1871 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1872 /* Don't combine across a CALL_INSN, because that would possibly
1873 change whether the life span of some REGs crosses calls or not,
1874 and it is a pain to update that information.
1875 Exception: if source is a constant, moving it later can't hurt.
1876 Accept that as a special case. */
1877 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1880 /* DEST must either be a REG or CC0. */
1883 /* If register alignment is being enforced for multi-word items in all
1884 cases except for parameters, it is possible to have a register copy
1885 insn referencing a hard register that is not allowed to contain the
1886 mode being copied and which would not be valid as an operand of most
1887 insns. Eliminate this problem by not combining with such an insn.
1889 Also, on some machines we don't want to extend the life of a hard
1893 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1894 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1895 /* Don't extend the life of a hard register unless it is
1896 user variable (if we have few registers) or it can't
1897 fit into the desired register (meaning something special
1899 Also avoid substituting a return register into I3, because
1900 reload can't handle a conflict with constraints of other
1902 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1903 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1906 else if (GET_CODE (dest
) != CC0
)
1910 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1911 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1912 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1914 /* Don't substitute for a register intended as a clobberable
1916 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1917 if (rtx_equal_p (reg
, dest
))
1920 /* If the clobber represents an earlyclobber operand, we must not
1921 substitute an expression containing the clobbered register.
1922 As we do not analyze the constraint strings here, we have to
1923 make the conservative assumption. However, if the register is
1924 a fixed hard reg, the clobber cannot represent any operand;
1925 we leave it up to the machine description to either accept or
1926 reject use-and-clobber patterns. */
1928 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1929 || !fixed_regs
[REGNO (reg
)])
1930 if (reg_overlap_mentioned_p (reg
, src
))
1934 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1935 or not), reject, unless nothing volatile comes between it and I3 */
1937 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1939 /* Make sure neither succ nor succ2 contains a volatile reference. */
1940 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1942 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1944 /* We'll check insns between INSN and I3 below. */
1947 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1948 to be an explicit register variable, and was chosen for a reason. */
1950 if (GET_CODE (src
) == ASM_OPERANDS
1951 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1954 /* If INSN contains volatile references (specifically volatile MEMs),
1955 we cannot combine across any other volatile references.
1956 Even if INSN doesn't contain volatile references, any intervening
1957 volatile insn might affect machine state. */
1959 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1963 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1964 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1967 /* If INSN contains an autoincrement or autodecrement, make sure that
1968 register is not used between there and I3, and not already used in
1969 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1970 Also insist that I3 not be a jump; if it were one
1971 and the incremented register were spilled, we would lose. */
1974 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1975 if (REG_NOTE_KIND (link
) == REG_INC
1977 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1978 || (pred
!= NULL_RTX
1979 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1980 || (pred2
!= NULL_RTX
1981 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1982 || (succ
!= NULL_RTX
1983 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1984 || (succ2
!= NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1986 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1991 /* Don't combine an insn that follows a CC0-setting insn.
1992 An insn that uses CC0 must not be separated from the one that sets it.
1993 We do, however, allow I2 to follow a CC0-setting insn if that insn
1994 is passed as I1; in that case it will be deleted also.
1995 We also allow combining in this case if all the insns are adjacent
1996 because that would leave the two CC0 insns adjacent as well.
1997 It would be more logical to test whether CC0 occurs inside I1 or I2,
1998 but that would be much slower, and this ought to be equivalent. */
2000 p
= prev_nonnote_insn (insn
);
2001 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2006 /* If we get here, we have passed all the tests and the combination is
2015 /* LOC is the location within I3 that contains its pattern or the component
2016 of a PARALLEL of the pattern. We validate that it is valid for combining.
2018 One problem is if I3 modifies its output, as opposed to replacing it
2019 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2020 doing so would produce an insn that is not equivalent to the original insns.
2024 (set (reg:DI 101) (reg:DI 100))
2025 (set (subreg:SI (reg:DI 101) 0) <foo>)
2027 This is NOT equivalent to:
2029 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2030 (set (reg:DI 101) (reg:DI 100))])
2032 Not only does this modify 100 (in which case it might still be valid
2033 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2035 We can also run into a problem if I2 sets a register that I1
2036 uses and I1 gets directly substituted into I3 (not via I2). In that
2037 case, we would be getting the wrong value of I2DEST into I3, so we
2038 must reject the combination. This case occurs when I2 and I1 both
2039 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2040 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2041 of a SET must prevent combination from occurring. The same situation
2042 can occur for I0, in which case I0_NOT_IN_SRC is set.
2044 Before doing the above check, we first try to expand a field assignment
2045 into a set of logical operations.
2047 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2048 we place a register that is both set and used within I3. If more than one
2049 such register is detected, we fail.
2051 Return 1 if the combination is valid, zero otherwise. */
2054 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2055 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2059 if (GET_CODE (x
) == SET
)
2062 rtx dest
= SET_DEST (set
);
2063 rtx src
= SET_SRC (set
);
2064 rtx inner_dest
= dest
;
2067 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2068 || GET_CODE (inner_dest
) == SUBREG
2069 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2070 inner_dest
= XEXP (inner_dest
, 0);
2072 /* Check for the case where I3 modifies its output, as discussed
2073 above. We don't want to prevent pseudos from being combined
2074 into the address of a MEM, so only prevent the combination if
2075 i1 or i2 set the same MEM. */
2076 if ((inner_dest
!= dest
&&
2077 (!MEM_P (inner_dest
)
2078 || rtx_equal_p (i2dest
, inner_dest
)
2079 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2080 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2081 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2082 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2083 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2085 /* This is the same test done in can_combine_p except we can't test
2086 all_adjacent; we don't have to, since this instruction will stay
2087 in place, thus we are not considering increasing the lifetime of
2090 Also, if this insn sets a function argument, combining it with
2091 something that might need a spill could clobber a previous
2092 function argument; the all_adjacent test in can_combine_p also
2093 checks this; here, we do a more specific test for this case. */
2095 || (REG_P (inner_dest
)
2096 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2097 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2098 GET_MODE (inner_dest
))))
2099 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2100 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2103 /* If DEST is used in I3, it is being killed in this insn, so
2104 record that for later. We have to consider paradoxical
2105 subregs here, since they kill the whole register, but we
2106 ignore partial subregs, STRICT_LOW_PART, etc.
2107 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2108 STACK_POINTER_REGNUM, since these are always considered to be
2109 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2111 if (GET_CODE (subdest
) == SUBREG
2112 && (GET_MODE_SIZE (GET_MODE (subdest
))
2113 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2114 subdest
= SUBREG_REG (subdest
);
2117 && reg_referenced_p (subdest
, PATTERN (i3
))
2118 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2119 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2120 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2122 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2123 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2124 || ! fixed_regs
[REGNO (subdest
)])
2126 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2128 if (*pi3dest_killed
)
2131 *pi3dest_killed
= subdest
;
2135 else if (GET_CODE (x
) == PARALLEL
)
2139 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2140 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2141 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2148 /* Return 1 if X is an arithmetic expression that contains a multiplication
2149 and division. We don't count multiplications by powers of two here. */
2152 contains_muldiv (rtx x
)
2154 switch (GET_CODE (x
))
2156 case MOD
: case DIV
: case UMOD
: case UDIV
:
2160 return ! (CONST_INT_P (XEXP (x
, 1))
2161 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2164 return contains_muldiv (XEXP (x
, 0))
2165 || contains_muldiv (XEXP (x
, 1));
2168 return contains_muldiv (XEXP (x
, 0));
2174 /* Determine whether INSN can be used in a combination. Return nonzero if
2175 not. This is used in try_combine to detect early some cases where we
2176 can't perform combinations. */
2179 cant_combine_insn_p (rtx insn
)
2184 /* If this isn't really an insn, we can't do anything.
2185 This can occur when flow deletes an insn that it has merged into an
2186 auto-increment address. */
2187 if (! INSN_P (insn
))
2190 /* Never combine loads and stores involving hard regs that are likely
2191 to be spilled. The register allocator can usually handle such
2192 reg-reg moves by tying. If we allow the combiner to make
2193 substitutions of likely-spilled regs, reload might die.
2194 As an exception, we allow combinations involving fixed regs; these are
2195 not available to the register allocator so there's no risk involved. */
2197 set
= single_set (insn
);
2200 src
= SET_SRC (set
);
2201 dest
= SET_DEST (set
);
2202 if (GET_CODE (src
) == SUBREG
)
2203 src
= SUBREG_REG (src
);
2204 if (GET_CODE (dest
) == SUBREG
)
2205 dest
= SUBREG_REG (dest
);
2206 if (REG_P (src
) && REG_P (dest
)
2207 && ((HARD_REGISTER_P (src
)
2208 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2209 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2210 || (HARD_REGISTER_P (dest
)
2211 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2212 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2218 struct likely_spilled_retval_info
2220 unsigned regno
, nregs
;
2224 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2225 hard registers that are known to be written to / clobbered in full. */
2227 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2229 struct likely_spilled_retval_info
*const info
=
2230 (struct likely_spilled_retval_info
*) data
;
2231 unsigned regno
, nregs
;
2234 if (!REG_P (XEXP (set
, 0)))
2237 if (regno
>= info
->regno
+ info
->nregs
)
2239 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2240 if (regno
+ nregs
<= info
->regno
)
2242 new_mask
= (2U << (nregs
- 1)) - 1;
2243 if (regno
< info
->regno
)
2244 new_mask
>>= info
->regno
- regno
;
2246 new_mask
<<= regno
- info
->regno
;
2247 info
->mask
&= ~new_mask
;
2250 /* Return nonzero iff part of the return value is live during INSN, and
2251 it is likely spilled. This can happen when more than one insn is needed
2252 to copy the return value, e.g. when we consider to combine into the
2253 second copy insn for a complex value. */
2256 likely_spilled_retval_p (rtx insn
)
2258 rtx use
= BB_END (this_basic_block
);
2260 unsigned regno
, nregs
;
2261 /* We assume here that no machine mode needs more than
2262 32 hard registers when the value overlaps with a register
2263 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2265 struct likely_spilled_retval_info info
;
2267 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2269 reg
= XEXP (PATTERN (use
), 0);
2270 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2272 regno
= REGNO (reg
);
2273 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2276 mask
= (2U << (nregs
- 1)) - 1;
2278 /* Disregard parts of the return value that are set later. */
2282 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2284 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2287 /* Check if any of the (probably) live return value registers is
2292 if ((mask
& 1 << nregs
)
2293 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2299 /* Adjust INSN after we made a change to its destination.
2301 Changing the destination can invalidate notes that say something about
2302 the results of the insn and a LOG_LINK pointing to the insn. */
2305 adjust_for_new_dest (rtx insn
)
2307 /* For notes, be conservative and simply remove them. */
2308 remove_reg_equal_equiv_notes (insn
);
2310 /* The new insn will have a destination that was previously the destination
2311 of an insn just above it. Call distribute_links to make a LOG_LINK from
2312 the next use of that destination. */
2313 distribute_links (alloc_insn_link (insn
, NULL
));
2315 df_insn_rescan (insn
);
2318 /* Return TRUE if combine can reuse reg X in mode MODE.
2319 ADDED_SETS is nonzero if the original set is still required. */
2321 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2329 /* Allow hard registers if the new mode is legal, and occupies no more
2330 registers than the old mode. */
2331 if (regno
< FIRST_PSEUDO_REGISTER
)
2332 return (HARD_REGNO_MODE_OK (regno
, mode
)
2333 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2334 >= hard_regno_nregs
[regno
][mode
]));
2336 /* Or a pseudo that is only used once. */
2337 return (REG_N_SETS (regno
) == 1 && !added_sets
2338 && !REG_USERVAR_P (x
));
2342 /* Check whether X, the destination of a set, refers to part of
2343 the register specified by REG. */
2346 reg_subword_p (rtx x
, rtx reg
)
2348 /* Check that reg is an integer mode register. */
2349 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2352 if (GET_CODE (x
) == STRICT_LOW_PART
2353 || GET_CODE (x
) == ZERO_EXTRACT
)
2356 return GET_CODE (x
) == SUBREG
2357 && SUBREG_REG (x
) == reg
2358 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2362 /* Replace auto-increment addressing modes with explicit operations to access
2363 the same addresses without modifying the corresponding registers. */
2366 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2369 const RTX_CODE code
= GET_CODE (x
);
2385 /* SCRATCH must be shared because they represent distinct values. */
2388 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2393 if (shared_const_p (x
))
2398 mem_mode
= GET_MODE (x
);
2403 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2404 return gen_rtx_PLUS (GET_MODE (x
),
2405 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2406 GEN_INT (code
== PRE_INC
2407 ? GET_MODE_SIZE (mem_mode
)
2408 : -GET_MODE_SIZE (mem_mode
)));
2414 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2415 ? XEXP (x
, 1) : XEXP (x
, 0),
2422 /* Copy the various flags, fields, and other information. We assume
2423 that all fields need copying, and then clear the fields that should
2424 not be copied. That is the sensible default behavior, and forces
2425 us to explicitly document why we are *not* copying a flag. */
2426 x
= shallow_copy_rtx (x
);
2428 /* We do not copy the USED flag, which is used as a mark bit during
2429 walks over the RTL. */
2430 RTX_FLAG (x
, used
) = 0;
2432 /* We do not copy FRAME_RELATED for INSNs. */
2434 RTX_FLAG (x
, frame_related
) = 0;
2436 fmt
= GET_RTX_FORMAT (code
);
2437 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2439 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2440 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2443 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2444 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2446 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2453 /* Auxiliary data structure for propagate_for_debug_stmt. */
2455 struct rtx_subst_pair
2461 /* DATA points to an rtx_subst_pair. Return the value that should be
2465 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2467 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2469 if (!rtx_equal_p (from
, old_rtx
))
2471 if (!pair
->adjusted
)
2473 pair
->adjusted
= true;
2475 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2477 pair
->to
= copy_rtx (pair
->to
);
2479 pair
->to
= make_compound_operation (pair
->to
, SET
);
2482 return copy_rtx (pair
->to
);
2485 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2486 and LAST, not including INSN, but including LAST. Also stop at the end
2487 of THIS_BASIC_BLOCK. */
2490 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2492 rtx next
, loc
, end
= NEXT_INSN (BB_END (this_basic_block
));
2494 struct rtx_subst_pair p
;
2498 next
= NEXT_INSN (insn
);
2499 last
= NEXT_INSN (last
);
2500 while (next
!= last
&& next
!= end
)
2503 next
= NEXT_INSN (insn
);
2504 if (DEBUG_INSN_P (insn
))
2506 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2507 dest
, propagate_for_debug_subst
, &p
);
2508 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2510 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2511 df_insn_rescan (insn
);
2516 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2517 Note that the INSN should be deleted *after* removing dead edges, so
2518 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2519 but not for a (set (pc) (label_ref FOO)). */
2522 update_cfg_for_uncondjump (rtx insn
)
2524 basic_block bb
= BLOCK_FOR_INSN (insn
);
2525 gcc_assert (BB_END (bb
) == insn
);
2527 purge_dead_edges (bb
);
2530 if (EDGE_COUNT (bb
->succs
) == 1)
2534 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2536 /* Remove barriers from the footer if there are any. */
2537 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2538 if (BARRIER_P (insn
))
2540 if (PREV_INSN (insn
))
2541 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2543 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2544 if (NEXT_INSN (insn
))
2545 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2547 else if (LABEL_P (insn
))
2552 /* Try to combine the insns I0, I1 and I2 into I3.
2553 Here I0, I1 and I2 appear earlier than I3.
2554 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2557 If we are combining more than two insns and the resulting insn is not
2558 recognized, try splitting it into two insns. If that happens, I2 and I3
2559 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2560 Otherwise, I0, I1 and I2 are pseudo-deleted.
2562 Return 0 if the combination does not work. Then nothing is changed.
2563 If we did the combination, return the insn at which combine should
2566 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2567 new direct jump instruction.
2569 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2570 been I3 passed to an earlier try_combine within the same basic
2574 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2575 rtx last_combined_insn
)
2577 /* New patterns for I3 and I2, respectively. */
2578 rtx newpat
, newi2pat
= 0;
2579 rtvec newpat_vec_with_clobbers
= 0;
2580 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2581 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2583 int added_sets_0
, added_sets_1
, added_sets_2
;
2584 /* Total number of SETs to put into I3. */
2586 /* Nonzero if I2's or I1's body now appears in I3. */
2587 int i2_is_used
= 0, i1_is_used
= 0;
2588 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2589 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2590 /* Contains I3 if the destination of I3 is used in its source, which means
2591 that the old life of I3 is being killed. If that usage is placed into
2592 I2 and not in I3, a REG_DEAD note must be made. */
2593 rtx i3dest_killed
= 0;
2594 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2595 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2596 /* Copy of SET_SRC of I1 and I0, if needed. */
2597 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2598 /* Set if I2DEST was reused as a scratch register. */
2599 bool i2scratch
= false;
2600 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2601 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2602 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2603 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2604 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2605 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2606 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2607 /* Notes that must be added to REG_NOTES in I3 and I2. */
2608 rtx new_i3_notes
, new_i2_notes
;
2609 /* Notes that we substituted I3 into I2 instead of the normal case. */
2610 int i3_subst_into_i2
= 0;
2611 /* Notes that I1, I2 or I3 is a MULT operation. */
2614 int changed_i3_dest
= 0;
2618 struct insn_link
*link
;
2620 rtx new_other_notes
;
2623 /* Only try four-insn combinations when there's high likelihood of
2624 success. Look for simple insns, such as loads of constants or
2625 binary operations involving a constant. */
2632 if (!flag_expensive_optimizations
)
2635 for (i
= 0; i
< 4; i
++)
2637 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2638 rtx set
= single_set (insn
);
2642 src
= SET_SRC (set
);
2643 if (CONSTANT_P (src
))
2648 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2650 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2651 || GET_CODE (src
) == LSHIFTRT
)
2654 if (ngood
< 2 && nshift
< 2)
2658 /* Exit early if one of the insns involved can't be used for
2660 if (cant_combine_insn_p (i3
)
2661 || cant_combine_insn_p (i2
)
2662 || (i1
&& cant_combine_insn_p (i1
))
2663 || (i0
&& cant_combine_insn_p (i0
))
2664 || likely_spilled_retval_p (i3
))
2668 undobuf
.other_insn
= 0;
2670 /* Reset the hard register usage information. */
2671 CLEAR_HARD_REG_SET (newpat_used_regs
);
2673 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2676 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2677 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2679 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2680 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2682 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2683 INSN_UID (i2
), INSN_UID (i3
));
2686 /* If multiple insns feed into one of I2 or I3, they can be in any
2687 order. To simplify the code below, reorder them in sequence. */
2688 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2689 temp
= i2
, i2
= i0
, i0
= temp
;
2690 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2691 temp
= i1
, i1
= i0
, i0
= temp
;
2692 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2693 temp
= i1
, i1
= i2
, i2
= temp
;
2695 added_links_insn
= 0;
2697 /* First check for one important special case that the code below will
2698 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2699 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2700 we may be able to replace that destination with the destination of I3.
2701 This occurs in the common code where we compute both a quotient and
2702 remainder into a structure, in which case we want to do the computation
2703 directly into the structure to avoid register-register copies.
2705 Note that this case handles both multiple sets in I2 and also cases
2706 where I2 has a number of CLOBBERs inside the PARALLEL.
2708 We make very conservative checks below and only try to handle the
2709 most common cases of this. For example, we only handle the case
2710 where I2 and I3 are adjacent to avoid making difficult register
2713 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2714 && REG_P (SET_SRC (PATTERN (i3
)))
2715 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2716 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2717 && GET_CODE (PATTERN (i2
)) == PARALLEL
2718 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2719 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2720 below would need to check what is inside (and reg_overlap_mentioned_p
2721 doesn't support those codes anyway). Don't allow those destinations;
2722 the resulting insn isn't likely to be recognized anyway. */
2723 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2724 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2725 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2726 SET_DEST (PATTERN (i3
)))
2727 && next_active_insn (i2
) == i3
)
2729 rtx p2
= PATTERN (i2
);
2731 /* Make sure that the destination of I3,
2732 which we are going to substitute into one output of I2,
2733 is not used within another output of I2. We must avoid making this:
2734 (parallel [(set (mem (reg 69)) ...)
2735 (set (reg 69) ...)])
2736 which is not well-defined as to order of actions.
2737 (Besides, reload can't handle output reloads for this.)
2739 The problem can also happen if the dest of I3 is a memory ref,
2740 if another dest in I2 is an indirect memory ref. */
2741 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2742 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2743 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2744 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2745 SET_DEST (XVECEXP (p2
, 0, i
))))
2748 if (i
== XVECLEN (p2
, 0))
2749 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2750 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2751 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2756 subst_low_luid
= DF_INSN_LUID (i2
);
2758 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2759 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2760 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2761 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2763 /* Replace the dest in I2 with our dest and make the resulting
2764 insn the new pattern for I3. Then skip to where we validate
2765 the pattern. Everything was set up above. */
2766 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2768 i3_subst_into_i2
= 1;
2769 goto validate_replacement
;
2773 /* If I2 is setting a pseudo to a constant and I3 is setting some
2774 sub-part of it to another constant, merge them by making a new
2777 && (temp
= single_set (i2
)) != 0
2778 && (CONST_INT_P (SET_SRC (temp
))
2779 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2780 && GET_CODE (PATTERN (i3
)) == SET
2781 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2782 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2783 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2785 rtx dest
= SET_DEST (PATTERN (i3
));
2789 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2791 if (CONST_INT_P (XEXP (dest
, 1))
2792 && CONST_INT_P (XEXP (dest
, 2)))
2794 width
= INTVAL (XEXP (dest
, 1));
2795 offset
= INTVAL (XEXP (dest
, 2));
2796 dest
= XEXP (dest
, 0);
2797 if (BITS_BIG_ENDIAN
)
2798 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2803 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2804 dest
= XEXP (dest
, 0);
2805 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2811 /* If this is the low part, we're done. */
2812 if (subreg_lowpart_p (dest
))
2814 /* Handle the case where inner is twice the size of outer. */
2815 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2816 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2817 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2818 /* Otherwise give up for now. */
2824 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2825 <= HOST_BITS_PER_DOUBLE_INT
))
2828 rtx inner
= SET_SRC (PATTERN (i3
));
2829 rtx outer
= SET_SRC (temp
);
2831 o
= rtx_to_double_int (outer
);
2832 i
= rtx_to_double_int (inner
);
2834 m
= double_int_mask (width
);
2835 i
= double_int_and (i
, m
);
2836 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2837 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2838 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2842 subst_low_luid
= DF_INSN_LUID (i2
);
2843 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2844 i2dest
= SET_DEST (temp
);
2845 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2847 /* Replace the source in I2 with the new constant and make the
2848 resulting insn the new pattern for I3. Then skip to where we
2849 validate the pattern. Everything was set up above. */
2850 SUBST (SET_SRC (temp
),
2851 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2853 newpat
= PATTERN (i2
);
2855 /* The dest of I3 has been replaced with the dest of I2. */
2856 changed_i3_dest
= 1;
2857 goto validate_replacement
;
2862 /* If we have no I1 and I2 looks like:
2863 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2865 make up a dummy I1 that is
2868 (set (reg:CC X) (compare:CC Y (const_int 0)))
2870 (We can ignore any trailing CLOBBERs.)
2872 This undoes a previous combination and allows us to match a branch-and-
2875 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2876 && XVECLEN (PATTERN (i2
), 0) >= 2
2877 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2878 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2880 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2881 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2882 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2883 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2884 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2885 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2887 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2888 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2893 /* We make I1 with the same INSN_UID as I2. This gives it
2894 the same DF_INSN_LUID for value tracking. Our fake I1 will
2895 never appear in the insn stream so giving it the same INSN_UID
2896 as I2 will not cause a problem. */
2898 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2899 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2900 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2902 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2903 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2904 SET_DEST (PATTERN (i1
)));
2905 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2910 /* Verify that I2 and I1 are valid for combining. */
2911 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2912 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2914 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2921 /* Record whether I2DEST is used in I2SRC and similarly for the other
2922 cases. Knowing this will help in register status updating below. */
2923 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2924 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2925 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2926 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2927 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2928 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2929 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2930 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2931 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2933 /* For the earlier insns, determine which of the subsequent ones they
2935 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2936 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2937 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2938 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2939 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2941 /* Ensure that I3's pattern can be the destination of combines. */
2942 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2943 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2944 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2945 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2952 /* See if any of the insns is a MULT operation. Unless one is, we will
2953 reject a combination that is, since it must be slower. Be conservative
2955 if (GET_CODE (i2src
) == MULT
2956 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2957 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2958 || (GET_CODE (PATTERN (i3
)) == SET
2959 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2962 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2963 We used to do this EXCEPT in one case: I3 has a post-inc in an
2964 output operand. However, that exception can give rise to insns like
2966 which is a famous insn on the PDP-11 where the value of r3 used as the
2967 source was model-dependent. Avoid this sort of thing. */
2970 if (!(GET_CODE (PATTERN (i3
)) == SET
2971 && REG_P (SET_SRC (PATTERN (i3
)))
2972 && MEM_P (SET_DEST (PATTERN (i3
)))
2973 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2974 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2975 /* It's not the exception. */
2980 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2981 if (REG_NOTE_KIND (link
) == REG_INC
2982 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2984 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2992 /* See if the SETs in I1 or I2 need to be kept around in the merged
2993 instruction: whenever the value set there is still needed past I3.
2994 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2996 For the SET in I1, we have two cases: If I1 and I2 independently
2997 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2998 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2999 in I1 needs to be kept around unless I1DEST dies or is set in either
3000 I2 or I3. The same consideration applies to I0. */
3002 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3005 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3006 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3011 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3012 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3013 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
3017 /* We are about to copy insns for the case where they need to be kept
3018 around. Check that they can be copied in the merged instruction. */
3020 if (targetm
.cannot_copy_insn_p
3021 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3022 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3023 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3029 /* If the set in I2 needs to be kept around, we must make a copy of
3030 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3031 PATTERN (I2), we are only substituting for the original I1DEST, not into
3032 an already-substituted copy. This also prevents making self-referential
3033 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3038 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3039 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
3041 i2pat
= copy_rtx (PATTERN (i2
));
3046 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3047 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
3049 i1pat
= copy_rtx (PATTERN (i1
));
3054 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3055 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
3057 i0pat
= copy_rtx (PATTERN (i0
));
3062 /* Substitute in the latest insn for the regs set by the earlier ones. */
3064 maxreg
= max_reg_num ();
3069 /* Many machines that don't use CC0 have insns that can both perform an
3070 arithmetic operation and set the condition code. These operations will
3071 be represented as a PARALLEL with the first element of the vector
3072 being a COMPARE of an arithmetic operation with the constant zero.
3073 The second element of the vector will set some pseudo to the result
3074 of the same arithmetic operation. If we simplify the COMPARE, we won't
3075 match such a pattern and so will generate an extra insn. Here we test
3076 for this case, where both the comparison and the operation result are
3077 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3078 I2SRC. Later we will make the PARALLEL that contains I2. */
3080 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3081 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3082 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3083 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3086 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
3087 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3088 enum machine_mode compare_mode
, orig_compare_mode
;
3089 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3091 newpat
= PATTERN (i3
);
3092 newpat_dest
= SET_DEST (newpat
);
3093 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3095 if (undobuf
.other_insn
== 0
3096 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3099 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3100 compare_code
= simplify_compare_const (compare_code
,
3102 #ifdef CANONICALIZE_COMPARISON
3103 CANONICALIZE_COMPARISON (compare_code
, op0
, op1
);
3107 /* Do the rest only if op1 is const0_rtx, which may be the
3108 result of simplification. */
3109 if (op1
== const0_rtx
)
3111 /* If a single use of the CC is found, prepare to modify it
3112 when SELECT_CC_MODE returns a new CC-class mode, or when
3113 the above simplify_compare_const() returned a new comparison
3114 operator. undobuf.other_insn is assigned the CC use insn
3115 when modifying it. */
3118 #ifdef SELECT_CC_MODE
3119 enum machine_mode new_mode
3120 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3121 if (new_mode
!= orig_compare_mode
3122 && can_change_dest_mode (SET_DEST (newpat
),
3123 added_sets_2
, new_mode
))
3125 unsigned int regno
= REGNO (newpat_dest
);
3126 compare_mode
= new_mode
;
3127 if (regno
< FIRST_PSEUDO_REGISTER
)
3128 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3131 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3132 newpat_dest
= regno_reg_rtx
[regno
];
3136 /* Cases for modifying the CC-using comparison. */
3137 if (compare_code
!= orig_compare_code
3138 /* ??? Do we need to verify the zero rtx? */
3139 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3141 /* Replace cc_use_loc with entire new RTX. */
3143 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3144 newpat_dest
, const0_rtx
));
3145 undobuf
.other_insn
= cc_use_insn
;
3147 else if (compare_mode
!= orig_compare_mode
)
3149 /* Just replace the CC reg with a new mode. */
3150 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3151 undobuf
.other_insn
= cc_use_insn
;
3155 /* Now we modify the current newpat:
3156 First, SET_DEST(newpat) is updated if the CC mode has been
3157 altered. For targets without SELECT_CC_MODE, this should be
3159 if (compare_mode
!= orig_compare_mode
)
3160 SUBST (SET_DEST (newpat
), newpat_dest
);
3161 /* This is always done to propagate i2src into newpat. */
3162 SUBST (SET_SRC (newpat
),
3163 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3164 /* Create new version of i2pat if needed; the below PARALLEL
3165 creation needs this to work correctly. */
3166 if (! rtx_equal_p (i2src
, op0
))
3167 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3173 if (i2_is_used
== 0)
3175 /* It is possible that the source of I2 or I1 may be performing
3176 an unneeded operation, such as a ZERO_EXTEND of something
3177 that is known to have the high part zero. Handle that case
3178 by letting subst look at the inner insns.
3180 Another way to do this would be to have a function that tries
3181 to simplify a single insn instead of merging two or more
3182 insns. We don't do this because of the potential of infinite
3183 loops and because of the potential extra memory required.
3184 However, doing it the way we are is a bit of a kludge and
3185 doesn't catch all cases.
3187 But only do this if -fexpensive-optimizations since it slows
3188 things down and doesn't usually win.
3190 This is not done in the COMPARE case above because the
3191 unmodified I2PAT is used in the PARALLEL and so a pattern
3192 with a modified I2SRC would not match. */
3194 if (flag_expensive_optimizations
)
3196 /* Pass pc_rtx so no substitutions are done, just
3200 subst_low_luid
= DF_INSN_LUID (i1
);
3201 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3204 subst_low_luid
= DF_INSN_LUID (i2
);
3205 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3208 n_occurrences
= 0; /* `subst' counts here */
3209 subst_low_luid
= DF_INSN_LUID (i2
);
3211 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3212 copy of I2SRC each time we substitute it, in order to avoid creating
3213 self-referential RTL when we will be substituting I1SRC for I1DEST
3214 later. Likewise if I0 feeds into I2, either directly or indirectly
3215 through I1, and I0DEST is in I0SRC. */
3216 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3217 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3218 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3219 && i0dest_in_i0src
));
3222 /* Record whether I2's body now appears within I3's body. */
3223 i2_is_used
= n_occurrences
;
3226 /* If we already got a failure, don't try to do more. Otherwise, try to
3227 substitute I1 if we have it. */
3229 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3231 /* Check that an autoincrement side-effect on I1 has not been lost.
3232 This happens if I1DEST is mentioned in I2 and dies there, and
3233 has disappeared from the new pattern. */
3234 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3236 && dead_or_set_p (i2
, i1dest
)
3237 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3238 /* Before we can do this substitution, we must redo the test done
3239 above (see detailed comments there) that ensures I1DEST isn't
3240 mentioned in any SETs in NEWPAT that are field assignments. */
3241 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3249 subst_low_luid
= DF_INSN_LUID (i1
);
3251 /* If the following substitution will modify I1SRC, make a copy of it
3252 for the case where it is substituted for I1DEST in I2PAT later. */
3253 if (added_sets_2
&& i1_feeds_i2_n
)
3254 i1src_copy
= copy_rtx (i1src
);
3256 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3257 copy of I1SRC each time we substitute it, in order to avoid creating
3258 self-referential RTL when we will be substituting I0SRC for I0DEST
3260 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3261 i0_feeds_i1_n
&& i0dest_in_i0src
);
3264 /* Record whether I1's body now appears within I3's body. */
3265 i1_is_used
= n_occurrences
;
3268 /* Likewise for I0 if we have it. */
3270 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3272 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3273 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3274 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3275 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3276 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3283 /* If the following substitution will modify I0SRC, make a copy of it
3284 for the case where it is substituted for I0DEST in I1PAT later. */
3285 if (added_sets_1
&& i0_feeds_i1_n
)
3286 i0src_copy
= copy_rtx (i0src
);
3287 /* And a copy for I0DEST in I2PAT substitution. */
3288 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3289 || (i0_feeds_i2_n
)))
3290 i0src_copy2
= copy_rtx (i0src
);
3293 subst_low_luid
= DF_INSN_LUID (i0
);
3294 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3298 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3299 to count all the ways that I2SRC and I1SRC can be used. */
3300 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3301 && i2_is_used
+ added_sets_2
> 1)
3302 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3303 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3305 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3306 && (n_occurrences
+ added_sets_0
3307 + (added_sets_1
&& i0_feeds_i1_n
)
3308 + (added_sets_2
&& i0_feeds_i2_n
)
3310 /* Fail if we tried to make a new register. */
3311 || max_reg_num () != maxreg
3312 /* Fail if we couldn't do something and have a CLOBBER. */
3313 || GET_CODE (newpat
) == CLOBBER
3314 /* Fail if this new pattern is a MULT and we didn't have one before
3315 at the outer level. */
3316 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3323 /* If the actions of the earlier insns must be kept
3324 in addition to substituting them into the latest one,
3325 we must make a new PARALLEL for the latest insn
3326 to hold additional the SETs. */
3328 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3330 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3333 if (GET_CODE (newpat
) == PARALLEL
)
3335 rtvec old
= XVEC (newpat
, 0);
3336 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3337 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3338 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3339 sizeof (old
->elem
[0]) * old
->num_elem
);
3344 total_sets
= 1 + extra_sets
;
3345 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3346 XVECEXP (newpat
, 0, 0) = old
;
3350 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3356 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3358 XVECEXP (newpat
, 0, --total_sets
) = t
;
3364 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3365 i0_feeds_i1_n
&& i0dest_in_i0src
);
3366 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3367 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3369 XVECEXP (newpat
, 0, --total_sets
) = t
;
3373 validate_replacement
:
3375 /* Note which hard regs this insn has as inputs. */
3376 mark_used_regs_combine (newpat
);
3378 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3379 consider splitting this pattern, we might need these clobbers. */
3380 if (i1
&& GET_CODE (newpat
) == PARALLEL
3381 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3383 int len
= XVECLEN (newpat
, 0);
3385 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3386 for (i
= 0; i
< len
; i
++)
3387 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3390 /* Is the result of combination a valid instruction? */
3391 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3393 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3394 the second SET's destination is a register that is unused and isn't
3395 marked as an instruction that might trap in an EH region. In that case,
3396 we just need the first SET. This can occur when simplifying a divmod
3397 insn. We *must* test for this case here because the code below that
3398 splits two independent SETs doesn't handle this case correctly when it
3399 updates the register status.
3401 It's pointless doing this if we originally had two sets, one from
3402 i3, and one from i2. Combining then splitting the parallel results
3403 in the original i2 again plus an invalid insn (which we delete).
3404 The net effect is only to move instructions around, which makes
3405 debug info less accurate.
3407 Also check the case where the first SET's destination is unused.
3408 That would not cause incorrect code, but does cause an unneeded
3411 if (insn_code_number
< 0
3412 && !(added_sets_2
&& i1
== 0)
3413 && GET_CODE (newpat
) == PARALLEL
3414 && XVECLEN (newpat
, 0) == 2
3415 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3416 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3417 && asm_noperands (newpat
) < 0)
3419 rtx set0
= XVECEXP (newpat
, 0, 0);
3420 rtx set1
= XVECEXP (newpat
, 0, 1);
3422 if (((REG_P (SET_DEST (set1
))
3423 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3424 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3425 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3426 && insn_nothrow_p (i3
)
3427 && !side_effects_p (SET_SRC (set1
)))
3430 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3433 else if (((REG_P (SET_DEST (set0
))
3434 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3435 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3436 && find_reg_note (i3
, REG_UNUSED
,
3437 SUBREG_REG (SET_DEST (set0
)))))
3438 && insn_nothrow_p (i3
)
3439 && !side_effects_p (SET_SRC (set0
)))
3442 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3444 if (insn_code_number
>= 0)
3445 changed_i3_dest
= 1;
3449 /* If we were combining three insns and the result is a simple SET
3450 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3451 insns. There are two ways to do this. It can be split using a
3452 machine-specific method (like when you have an addition of a large
3453 constant) or by combine in the function find_split_point. */
3455 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3456 && asm_noperands (newpat
) < 0)
3458 rtx parallel
, m_split
, *split
;
3460 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3461 use I2DEST as a scratch register will help. In the latter case,
3462 convert I2DEST to the mode of the source of NEWPAT if we can. */
3464 m_split
= combine_split_insns (newpat
, i3
);
3466 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3467 inputs of NEWPAT. */
3469 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3470 possible to try that as a scratch reg. This would require adding
3471 more code to make it work though. */
3473 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3475 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3477 /* First try to split using the original register as a
3478 scratch register. */
3479 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3480 gen_rtvec (2, newpat
,
3481 gen_rtx_CLOBBER (VOIDmode
,
3483 m_split
= combine_split_insns (parallel
, i3
);
3485 /* If that didn't work, try changing the mode of I2DEST if
3488 && new_mode
!= GET_MODE (i2dest
)
3489 && new_mode
!= VOIDmode
3490 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3492 enum machine_mode old_mode
= GET_MODE (i2dest
);
3495 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3496 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3499 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3500 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3503 parallel
= (gen_rtx_PARALLEL
3505 gen_rtvec (2, newpat
,
3506 gen_rtx_CLOBBER (VOIDmode
,
3508 m_split
= combine_split_insns (parallel
, i3
);
3511 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3515 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3516 buf
= undobuf
.undos
;
3517 undobuf
.undos
= buf
->next
;
3518 buf
->next
= undobuf
.frees
;
3519 undobuf
.frees
= buf
;
3523 i2scratch
= m_split
!= 0;
3526 /* If recog_for_combine has discarded clobbers, try to use them
3527 again for the split. */
3528 if (m_split
== 0 && newpat_vec_with_clobbers
)
3530 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3531 m_split
= combine_split_insns (parallel
, i3
);
3534 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3536 m_split
= PATTERN (m_split
);
3537 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3538 if (insn_code_number
>= 0)
3541 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3542 && (next_nonnote_nondebug_insn (i2
) == i3
3543 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3546 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3547 newi2pat
= PATTERN (m_split
);
3549 i3set
= single_set (NEXT_INSN (m_split
));
3550 i2set
= single_set (m_split
);
3552 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3554 /* If I2 or I3 has multiple SETs, we won't know how to track
3555 register status, so don't use these insns. If I2's destination
3556 is used between I2 and I3, we also can't use these insns. */
3558 if (i2_code_number
>= 0 && i2set
&& i3set
3559 && (next_nonnote_nondebug_insn (i2
) == i3
3560 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3561 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3563 if (insn_code_number
>= 0)
3566 /* It is possible that both insns now set the destination of I3.
3567 If so, we must show an extra use of it. */
3569 if (insn_code_number
>= 0)
3571 rtx new_i3_dest
= SET_DEST (i3set
);
3572 rtx new_i2_dest
= SET_DEST (i2set
);
3574 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3575 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3576 || GET_CODE (new_i3_dest
) == SUBREG
)
3577 new_i3_dest
= XEXP (new_i3_dest
, 0);
3579 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3580 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3581 || GET_CODE (new_i2_dest
) == SUBREG
)
3582 new_i2_dest
= XEXP (new_i2_dest
, 0);
3584 if (REG_P (new_i3_dest
)
3585 && REG_P (new_i2_dest
)
3586 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3587 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3591 /* If we can split it and use I2DEST, go ahead and see if that
3592 helps things be recognized. Verify that none of the registers
3593 are set between I2 and I3. */
3594 if (insn_code_number
< 0
3595 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3599 /* We need I2DEST in the proper mode. If it is a hard register
3600 or the only use of a pseudo, we can change its mode.
3601 Make sure we don't change a hard register to have a mode that
3602 isn't valid for it, or change the number of registers. */
3603 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3604 || GET_MODE (*split
) == VOIDmode
3605 || can_change_dest_mode (i2dest
, added_sets_2
,
3607 && (next_nonnote_nondebug_insn (i2
) == i3
3608 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3609 /* We can't overwrite I2DEST if its value is still used by
3611 && ! reg_referenced_p (i2dest
, newpat
))
3613 rtx newdest
= i2dest
;
3614 enum rtx_code split_code
= GET_CODE (*split
);
3615 enum machine_mode split_mode
= GET_MODE (*split
);
3616 bool subst_done
= false;
3617 newi2pat
= NULL_RTX
;
3621 /* *SPLIT may be part of I2SRC, so make sure we have the
3622 original expression around for later debug processing.
3623 We should not need I2SRC any more in other cases. */
3624 if (MAY_HAVE_DEBUG_INSNS
)
3625 i2src
= copy_rtx (i2src
);
3629 /* Get NEWDEST as a register in the proper mode. We have already
3630 validated that we can do this. */
3631 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3633 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3634 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3637 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3638 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3642 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3643 an ASHIFT. This can occur if it was inside a PLUS and hence
3644 appeared to be a memory address. This is a kludge. */
3645 if (split_code
== MULT
3646 && CONST_INT_P (XEXP (*split
, 1))
3647 && INTVAL (XEXP (*split
, 1)) > 0
3648 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3650 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3651 XEXP (*split
, 0), GEN_INT (i
)));
3652 /* Update split_code because we may not have a multiply
3654 split_code
= GET_CODE (*split
);
3657 #ifdef INSN_SCHEDULING
3658 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3659 be written as a ZERO_EXTEND. */
3660 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3662 #ifdef LOAD_EXTEND_OP
3663 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3664 what it really is. */
3665 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3667 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3668 SUBREG_REG (*split
)));
3671 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3672 SUBREG_REG (*split
)));
3676 /* Attempt to split binary operators using arithmetic identities. */
3677 if (BINARY_P (SET_SRC (newpat
))
3678 && split_mode
== GET_MODE (SET_SRC (newpat
))
3679 && ! side_effects_p (SET_SRC (newpat
)))
3681 rtx setsrc
= SET_SRC (newpat
);
3682 enum machine_mode mode
= GET_MODE (setsrc
);
3683 enum rtx_code code
= GET_CODE (setsrc
);
3684 rtx src_op0
= XEXP (setsrc
, 0);
3685 rtx src_op1
= XEXP (setsrc
, 1);
3687 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3688 if (rtx_equal_p (src_op0
, src_op1
))
3690 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3691 SUBST (XEXP (setsrc
, 0), newdest
);
3692 SUBST (XEXP (setsrc
, 1), newdest
);
3695 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3696 else if ((code
== PLUS
|| code
== MULT
)
3697 && GET_CODE (src_op0
) == code
3698 && GET_CODE (XEXP (src_op0
, 0)) == code
3699 && (INTEGRAL_MODE_P (mode
)
3700 || (FLOAT_MODE_P (mode
)
3701 && flag_unsafe_math_optimizations
)))
3703 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3704 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3705 rtx r
= XEXP (src_op0
, 1);
3708 /* Split both "((X op Y) op X) op Y" and
3709 "((X op Y) op Y) op X" as "T op T" where T is
3711 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3712 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3714 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3716 SUBST (XEXP (setsrc
, 0), newdest
);
3717 SUBST (XEXP (setsrc
, 1), newdest
);
3720 /* Split "((X op X) op Y) op Y)" as "T op T" where
3722 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3724 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3725 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3726 SUBST (XEXP (setsrc
, 0), newdest
);
3727 SUBST (XEXP (setsrc
, 1), newdest
);
3735 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3736 SUBST (*split
, newdest
);
3739 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3741 /* recog_for_combine might have added CLOBBERs to newi2pat.
3742 Make sure NEWPAT does not depend on the clobbered regs. */
3743 if (GET_CODE (newi2pat
) == PARALLEL
)
3744 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3745 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3747 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3748 if (reg_overlap_mentioned_p (reg
, newpat
))
3755 /* If the split point was a MULT and we didn't have one before,
3756 don't use one now. */
3757 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3758 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3762 /* Check for a case where we loaded from memory in a narrow mode and
3763 then sign extended it, but we need both registers. In that case,
3764 we have a PARALLEL with both loads from the same memory location.
3765 We can split this into a load from memory followed by a register-register
3766 copy. This saves at least one insn, more if register allocation can
3769 We cannot do this if the destination of the first assignment is a
3770 condition code register or cc0. We eliminate this case by making sure
3771 the SET_DEST and SET_SRC have the same mode.
3773 We cannot do this if the destination of the second assignment is
3774 a register that we have already assumed is zero-extended. Similarly
3775 for a SUBREG of such a register. */
3777 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3778 && GET_CODE (newpat
) == PARALLEL
3779 && XVECLEN (newpat
, 0) == 2
3780 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3781 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3782 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3783 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3784 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3785 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3786 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3787 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3789 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3790 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3791 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3793 && VEC_index (reg_stat_type
, reg_stat
,
3794 REGNO (temp
))->nonzero_bits
!= 0
3795 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3796 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3797 && (VEC_index (reg_stat_type
, reg_stat
,
3798 REGNO (temp
))->nonzero_bits
3799 != GET_MODE_MASK (word_mode
))))
3800 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3801 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3803 && VEC_index (reg_stat_type
, reg_stat
,
3804 REGNO (temp
))->nonzero_bits
!= 0
3805 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3806 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3807 && (VEC_index (reg_stat_type
, reg_stat
,
3808 REGNO (temp
))->nonzero_bits
3809 != GET_MODE_MASK (word_mode
)))))
3810 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3811 SET_SRC (XVECEXP (newpat
, 0, 1)))
3812 && ! find_reg_note (i3
, REG_UNUSED
,
3813 SET_DEST (XVECEXP (newpat
, 0, 0))))
3817 newi2pat
= XVECEXP (newpat
, 0, 0);
3818 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3819 newpat
= XVECEXP (newpat
, 0, 1);
3820 SUBST (SET_SRC (newpat
),
3821 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3822 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3824 if (i2_code_number
>= 0)
3825 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3827 if (insn_code_number
>= 0)
3831 /* Similarly, check for a case where we have a PARALLEL of two independent
3832 SETs but we started with three insns. In this case, we can do the sets
3833 as two separate insns. This case occurs when some SET allows two
3834 other insns to combine, but the destination of that SET is still live. */
3836 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3837 && GET_CODE (newpat
) == PARALLEL
3838 && XVECLEN (newpat
, 0) == 2
3839 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3840 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3841 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3842 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3843 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3844 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3845 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3846 XVECEXP (newpat
, 0, 0))
3847 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3848 XVECEXP (newpat
, 0, 1))
3849 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3850 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3852 /* Normally, it doesn't matter which of the two is done first,
3853 but the one that references cc0 can't be the second, and
3854 one which uses any regs/memory set in between i2 and i3 can't
3856 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3859 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3863 newi2pat
= XVECEXP (newpat
, 0, 1);
3864 newpat
= XVECEXP (newpat
, 0, 0);
3866 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3869 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3873 newi2pat
= XVECEXP (newpat
, 0, 0);
3874 newpat
= XVECEXP (newpat
, 0, 1);
3882 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3884 if (i2_code_number
>= 0)
3886 /* recog_for_combine might have added CLOBBERs to newi2pat.
3887 Make sure NEWPAT does not depend on the clobbered regs. */
3888 if (GET_CODE (newi2pat
) == PARALLEL
)
3890 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3891 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3893 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3894 if (reg_overlap_mentioned_p (reg
, newpat
))
3902 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3906 /* If it still isn't recognized, fail and change things back the way they
3908 if ((insn_code_number
< 0
3909 /* Is the result a reasonable ASM_OPERANDS? */
3910 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3916 /* If we had to change another insn, make sure it is valid also. */
3917 if (undobuf
.other_insn
)
3919 CLEAR_HARD_REG_SET (newpat_used_regs
);
3921 other_pat
= PATTERN (undobuf
.other_insn
);
3922 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3925 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3933 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3934 they are adjacent to each other or not. */
3936 rtx p
= prev_nonnote_insn (i3
);
3937 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3938 && sets_cc0_p (newi2pat
))
3946 /* Only allow this combination if insn_rtx_costs reports that the
3947 replacement instructions are cheaper than the originals. */
3948 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3954 if (MAY_HAVE_DEBUG_INSNS
)
3958 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3959 if (undo
->kind
== UNDO_MODE
)
3961 rtx reg
= *undo
->where
.r
;
3962 enum machine_mode new_mode
= GET_MODE (reg
);
3963 enum machine_mode old_mode
= undo
->old_contents
.m
;
3965 /* Temporarily revert mode back. */
3966 adjust_reg_mode (reg
, old_mode
);
3968 if (reg
== i2dest
&& i2scratch
)
3970 /* If we used i2dest as a scratch register with a
3971 different mode, substitute it for the original
3972 i2src while its original mode is temporarily
3973 restored, and then clear i2scratch so that we don't
3974 do it again later. */
3975 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
);
3977 /* Put back the new mode. */
3978 adjust_reg_mode (reg
, new_mode
);
3982 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3988 last
= last_combined_insn
;
3993 last
= undobuf
.other_insn
;
3995 if (DF_INSN_LUID (last
)
3996 < DF_INSN_LUID (last_combined_insn
))
3997 last
= last_combined_insn
;
4000 /* We're dealing with a reg that changed mode but not
4001 meaning, so we want to turn it into a subreg for
4002 the new mode. However, because of REG sharing and
4003 because its mode had already changed, we have to do
4004 it in two steps. First, replace any debug uses of
4005 reg, with its original mode temporarily restored,
4006 with this copy we have created; then, replace the
4007 copy with the SUBREG of the original shared reg,
4008 once again changed to the new mode. */
4009 propagate_for_debug (first
, last
, reg
, tempreg
);
4010 adjust_reg_mode (reg
, new_mode
);
4011 propagate_for_debug (first
, last
, tempreg
,
4012 lowpart_subreg (old_mode
, reg
, new_mode
));
4017 /* If we will be able to accept this, we have made a
4018 change to the destination of I3. This requires us to
4019 do a few adjustments. */
4021 if (changed_i3_dest
)
4023 PATTERN (i3
) = newpat
;
4024 adjust_for_new_dest (i3
);
4027 /* We now know that we can do this combination. Merge the insns and
4028 update the status of registers and LOG_LINKS. */
4030 if (undobuf
.other_insn
)
4034 PATTERN (undobuf
.other_insn
) = other_pat
;
4036 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4037 are still valid. Then add any non-duplicate notes added by
4038 recog_for_combine. */
4039 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4041 next
= XEXP (note
, 1);
4043 if (REG_NOTE_KIND (note
) == REG_UNUSED
4044 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
4045 remove_note (undobuf
.other_insn
, note
);
4048 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4049 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4056 struct insn_link
*link
;
4059 /* I3 now uses what used to be its destination and which is now
4060 I2's destination. This requires us to do a few adjustments. */
4061 PATTERN (i3
) = newpat
;
4062 adjust_for_new_dest (i3
);
4064 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4067 However, some later insn might be using I2's dest and have
4068 a LOG_LINK pointing at I3. We must remove this link.
4069 The simplest way to remove the link is to point it at I1,
4070 which we know will be a NOTE. */
4072 /* newi2pat is usually a SET here; however, recog_for_combine might
4073 have added some clobbers. */
4074 if (GET_CODE (newi2pat
) == PARALLEL
)
4075 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4077 ni2dest
= SET_DEST (newi2pat
);
4079 for (insn
= NEXT_INSN (i3
);
4080 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4081 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4082 insn
= NEXT_INSN (insn
))
4084 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4086 FOR_EACH_LOG_LINK (link
, insn
)
4087 if (link
->insn
== i3
)
4096 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4097 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4100 /* Compute which registers we expect to eliminate. newi2pat may be setting
4101 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4102 same as i3dest, in which case newi2pat may be setting i1dest. */
4103 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4104 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4107 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4108 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4111 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4112 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4116 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4118 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4119 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4121 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4123 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4125 /* Ensure that we do not have something that should not be shared but
4126 occurs multiple times in the new insns. Check this by first
4127 resetting all the `used' flags and then copying anything is shared. */
4129 reset_used_flags (i3notes
);
4130 reset_used_flags (i2notes
);
4131 reset_used_flags (i1notes
);
4132 reset_used_flags (i0notes
);
4133 reset_used_flags (newpat
);
4134 reset_used_flags (newi2pat
);
4135 if (undobuf
.other_insn
)
4136 reset_used_flags (PATTERN (undobuf
.other_insn
));
4138 i3notes
= copy_rtx_if_shared (i3notes
);
4139 i2notes
= copy_rtx_if_shared (i2notes
);
4140 i1notes
= copy_rtx_if_shared (i1notes
);
4141 i0notes
= copy_rtx_if_shared (i0notes
);
4142 newpat
= copy_rtx_if_shared (newpat
);
4143 newi2pat
= copy_rtx_if_shared (newi2pat
);
4144 if (undobuf
.other_insn
)
4145 reset_used_flags (PATTERN (undobuf
.other_insn
));
4147 INSN_CODE (i3
) = insn_code_number
;
4148 PATTERN (i3
) = newpat
;
4150 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4152 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4154 reset_used_flags (call_usage
);
4155 call_usage
= copy_rtx (call_usage
);
4159 /* I2SRC must still be meaningful at this point. Some splitting
4160 operations can invalidate I2SRC, but those operations do not
4163 replace_rtx (call_usage
, i2dest
, i2src
);
4167 replace_rtx (call_usage
, i1dest
, i1src
);
4169 replace_rtx (call_usage
, i0dest
, i0src
);
4171 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4174 if (undobuf
.other_insn
)
4175 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4177 /* We had one special case above where I2 had more than one set and
4178 we replaced a destination of one of those sets with the destination
4179 of I3. In that case, we have to update LOG_LINKS of insns later
4180 in this basic block. Note that this (expensive) case is rare.
4182 Also, in this case, we must pretend that all REG_NOTEs for I2
4183 actually came from I3, so that REG_UNUSED notes from I2 will be
4184 properly handled. */
4186 if (i3_subst_into_i2
)
4188 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4189 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4190 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4191 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4192 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4193 && ! find_reg_note (i2
, REG_UNUSED
,
4194 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4195 for (temp
= NEXT_INSN (i2
);
4196 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4197 || BB_HEAD (this_basic_block
) != temp
);
4198 temp
= NEXT_INSN (temp
))
4199 if (temp
!= i3
&& INSN_P (temp
))
4200 FOR_EACH_LOG_LINK (link
, temp
)
4201 if (link
->insn
== i2
)
4207 while (XEXP (link
, 1))
4208 link
= XEXP (link
, 1);
4209 XEXP (link
, 1) = i2notes
;
4216 LOG_LINKS (i3
) = NULL
;
4218 LOG_LINKS (i2
) = NULL
;
4223 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4224 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
);
4225 INSN_CODE (i2
) = i2_code_number
;
4226 PATTERN (i2
) = newi2pat
;
4230 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4231 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
);
4232 SET_INSN_DELETED (i2
);
4237 LOG_LINKS (i1
) = NULL
;
4239 if (MAY_HAVE_DEBUG_INSNS
)
4240 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
);
4241 SET_INSN_DELETED (i1
);
4246 LOG_LINKS (i0
) = NULL
;
4248 if (MAY_HAVE_DEBUG_INSNS
)
4249 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
);
4250 SET_INSN_DELETED (i0
);
4253 /* Get death notes for everything that is now used in either I3 or
4254 I2 and used to die in a previous insn. If we built two new
4255 patterns, move from I1 to I2 then I2 to I3 so that we get the
4256 proper movement on registers that I2 modifies. */
4259 from_luid
= DF_INSN_LUID (i0
);
4261 from_luid
= DF_INSN_LUID (i1
);
4263 from_luid
= DF_INSN_LUID (i2
);
4265 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4266 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4268 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4270 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4271 elim_i2
, elim_i1
, elim_i0
);
4273 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4274 elim_i2
, elim_i1
, elim_i0
);
4276 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4277 elim_i2
, elim_i1
, elim_i0
);
4279 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4280 elim_i2
, elim_i1
, elim_i0
);
4282 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4283 elim_i2
, elim_i1
, elim_i0
);
4285 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4286 know these are REG_UNUSED and want them to go to the desired insn,
4287 so we always pass it as i3. */
4289 if (newi2pat
&& new_i2_notes
)
4290 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4294 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4297 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4298 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4299 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4300 in that case, it might delete I2. Similarly for I2 and I1.
4301 Show an additional death due to the REG_DEAD note we make here. If
4302 we discard it in distribute_notes, we will decrement it again. */
4306 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4307 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4309 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4311 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4313 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4314 elim_i2
, elim_i1
, elim_i0
);
4317 if (i2dest_in_i2src
)
4319 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4320 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4321 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4322 NULL_RTX
, NULL_RTX
);
4324 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4325 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4328 if (i1dest_in_i1src
)
4330 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4331 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4332 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4333 NULL_RTX
, NULL_RTX
);
4335 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4336 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4339 if (i0dest_in_i0src
)
4341 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4342 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4343 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4344 NULL_RTX
, NULL_RTX
);
4346 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4347 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4350 distribute_links (i3links
);
4351 distribute_links (i2links
);
4352 distribute_links (i1links
);
4353 distribute_links (i0links
);
4357 struct insn_link
*link
;
4358 rtx i2_insn
= 0, i2_val
= 0, set
;
4360 /* The insn that used to set this register doesn't exist, and
4361 this life of the register may not exist either. See if one of
4362 I3's links points to an insn that sets I2DEST. If it does,
4363 that is now the last known value for I2DEST. If we don't update
4364 this and I2 set the register to a value that depended on its old
4365 contents, we will get confused. If this insn is used, thing
4366 will be set correctly in combine_instructions. */
4367 FOR_EACH_LOG_LINK (link
, i3
)
4368 if ((set
= single_set (link
->insn
)) != 0
4369 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4370 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4372 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4374 /* If the reg formerly set in I2 died only once and that was in I3,
4375 zero its use count so it won't make `reload' do any work. */
4377 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4378 && ! i2dest_in_i2src
)
4379 INC_REG_N_SETS (REGNO (i2dest
), -1);
4382 if (i1
&& REG_P (i1dest
))
4384 struct insn_link
*link
;
4385 rtx i1_insn
= 0, i1_val
= 0, set
;
4387 FOR_EACH_LOG_LINK (link
, i3
)
4388 if ((set
= single_set (link
->insn
)) != 0
4389 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4390 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4392 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4394 if (! added_sets_1
&& ! i1dest_in_i1src
)
4395 INC_REG_N_SETS (REGNO (i1dest
), -1);
4398 if (i0
&& REG_P (i0dest
))
4400 struct insn_link
*link
;
4401 rtx i0_insn
= 0, i0_val
= 0, set
;
4403 FOR_EACH_LOG_LINK (link
, i3
)
4404 if ((set
= single_set (link
->insn
)) != 0
4405 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4406 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4408 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4410 if (! added_sets_0
&& ! i0dest_in_i0src
)
4411 INC_REG_N_SETS (REGNO (i0dest
), -1);
4414 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4415 been made to this insn. The order of
4416 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4417 can affect nonzero_bits of newpat */
4419 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4420 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4423 if (undobuf
.other_insn
!= NULL_RTX
)
4427 fprintf (dump_file
, "modifying other_insn ");
4428 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4430 df_insn_rescan (undobuf
.other_insn
);
4433 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4437 fprintf (dump_file
, "modifying insn i1 ");
4438 dump_insn_slim (dump_file
, i0
);
4440 df_insn_rescan (i0
);
4443 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4447 fprintf (dump_file
, "modifying insn i1 ");
4448 dump_insn_slim (dump_file
, i1
);
4450 df_insn_rescan (i1
);
4453 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4457 fprintf (dump_file
, "modifying insn i2 ");
4458 dump_insn_slim (dump_file
, i2
);
4460 df_insn_rescan (i2
);
4463 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4467 fprintf (dump_file
, "modifying insn i3 ");
4468 dump_insn_slim (dump_file
, i3
);
4470 df_insn_rescan (i3
);
4473 /* Set new_direct_jump_p if a new return or simple jump instruction
4474 has been created. Adjust the CFG accordingly. */
4476 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4478 *new_direct_jump_p
= 1;
4479 mark_jump_label (PATTERN (i3
), i3
, 0);
4480 update_cfg_for_uncondjump (i3
);
4483 if (undobuf
.other_insn
!= NULL_RTX
4484 && (returnjump_p (undobuf
.other_insn
)
4485 || any_uncondjump_p (undobuf
.other_insn
)))
4487 *new_direct_jump_p
= 1;
4488 update_cfg_for_uncondjump (undobuf
.other_insn
);
4491 /* A noop might also need cleaning up of CFG, if it comes from the
4492 simplification of a jump. */
4494 && GET_CODE (newpat
) == SET
4495 && SET_SRC (newpat
) == pc_rtx
4496 && SET_DEST (newpat
) == pc_rtx
)
4498 *new_direct_jump_p
= 1;
4499 update_cfg_for_uncondjump (i3
);
4502 if (undobuf
.other_insn
!= NULL_RTX
4503 && JUMP_P (undobuf
.other_insn
)
4504 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4505 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4506 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4508 *new_direct_jump_p
= 1;
4509 update_cfg_for_uncondjump (undobuf
.other_insn
);
4512 combine_successes
++;
4515 if (added_links_insn
4516 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4517 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4518 return added_links_insn
;
4520 return newi2pat
? i2
: i3
;
4523 /* Undo all the modifications recorded in undobuf. */
4528 struct undo
*undo
, *next
;
4530 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4536 *undo
->where
.r
= undo
->old_contents
.r
;
4539 *undo
->where
.i
= undo
->old_contents
.i
;
4542 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4545 *undo
->where
.l
= undo
->old_contents
.l
;
4551 undo
->next
= undobuf
.frees
;
4552 undobuf
.frees
= undo
;
4558 /* We've committed to accepting the changes we made. Move all
4559 of the undos to the free list. */
4564 struct undo
*undo
, *next
;
4566 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4569 undo
->next
= undobuf
.frees
;
4570 undobuf
.frees
= undo
;
4575 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4576 where we have an arithmetic expression and return that point. LOC will
4579 try_combine will call this function to see if an insn can be split into
4583 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4586 enum rtx_code code
= GET_CODE (x
);
4588 unsigned HOST_WIDE_INT len
= 0;
4589 HOST_WIDE_INT pos
= 0;
4591 rtx inner
= NULL_RTX
;
4593 /* First special-case some codes. */
4597 #ifdef INSN_SCHEDULING
4598 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4600 if (MEM_P (SUBREG_REG (x
)))
4603 return find_split_point (&SUBREG_REG (x
), insn
, false);
4607 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4608 using LO_SUM and HIGH. */
4609 if (GET_CODE (XEXP (x
, 0)) == CONST
4610 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4612 enum machine_mode address_mode
= get_address_mode (x
);
4615 gen_rtx_LO_SUM (address_mode
,
4616 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4618 return &XEXP (XEXP (x
, 0), 0);
4622 /* If we have a PLUS whose second operand is a constant and the
4623 address is not valid, perhaps will can split it up using
4624 the machine-specific way to split large constants. We use
4625 the first pseudo-reg (one of the virtual regs) as a placeholder;
4626 it will not remain in the result. */
4627 if (GET_CODE (XEXP (x
, 0)) == PLUS
4628 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4629 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4630 MEM_ADDR_SPACE (x
)))
4632 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4633 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4637 /* This should have produced two insns, each of which sets our
4638 placeholder. If the source of the second is a valid address,
4639 we can make put both sources together and make a split point
4643 && NEXT_INSN (seq
) != NULL_RTX
4644 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4645 && NONJUMP_INSN_P (seq
)
4646 && GET_CODE (PATTERN (seq
)) == SET
4647 && SET_DEST (PATTERN (seq
)) == reg
4648 && ! reg_mentioned_p (reg
,
4649 SET_SRC (PATTERN (seq
)))
4650 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4651 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4652 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4653 && memory_address_addr_space_p
4654 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4655 MEM_ADDR_SPACE (x
)))
4657 rtx src1
= SET_SRC (PATTERN (seq
));
4658 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4660 /* Replace the placeholder in SRC2 with SRC1. If we can
4661 find where in SRC2 it was placed, that can become our
4662 split point and we can replace this address with SRC2.
4663 Just try two obvious places. */
4665 src2
= replace_rtx (src2
, reg
, src1
);
4667 if (XEXP (src2
, 0) == src1
)
4668 split
= &XEXP (src2
, 0);
4669 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4670 && XEXP (XEXP (src2
, 0), 0) == src1
)
4671 split
= &XEXP (XEXP (src2
, 0), 0);
4675 SUBST (XEXP (x
, 0), src2
);
4680 /* If that didn't work, perhaps the first operand is complex and
4681 needs to be computed separately, so make a split point there.
4682 This will occur on machines that just support REG + CONST
4683 and have a constant moved through some previous computation. */
4685 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4686 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4687 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4688 return &XEXP (XEXP (x
, 0), 0);
4691 /* If we have a PLUS whose first operand is complex, try computing it
4692 separately by making a split there. */
4693 if (GET_CODE (XEXP (x
, 0)) == PLUS
4694 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4696 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4697 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4698 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4699 return &XEXP (XEXP (x
, 0), 0);
4704 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4705 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4706 we need to put the operand into a register. So split at that
4709 if (SET_DEST (x
) == cc0_rtx
4710 && GET_CODE (SET_SRC (x
)) != COMPARE
4711 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4712 && !OBJECT_P (SET_SRC (x
))
4713 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4714 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4715 return &SET_SRC (x
);
4718 /* See if we can split SET_SRC as it stands. */
4719 split
= find_split_point (&SET_SRC (x
), insn
, true);
4720 if (split
&& split
!= &SET_SRC (x
))
4723 /* See if we can split SET_DEST as it stands. */
4724 split
= find_split_point (&SET_DEST (x
), insn
, false);
4725 if (split
&& split
!= &SET_DEST (x
))
4728 /* See if this is a bitfield assignment with everything constant. If
4729 so, this is an IOR of an AND, so split it into that. */
4730 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4731 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4732 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4733 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4734 && CONST_INT_P (SET_SRC (x
))
4735 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4736 + INTVAL (XEXP (SET_DEST (x
), 2)))
4737 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4738 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4740 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4741 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4742 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4743 rtx dest
= XEXP (SET_DEST (x
), 0);
4744 enum machine_mode mode
= GET_MODE (dest
);
4745 unsigned HOST_WIDE_INT mask
4746 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4749 if (BITS_BIG_ENDIAN
)
4750 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4752 or_mask
= gen_int_mode (src
<< pos
, mode
);
4755 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4758 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4760 simplify_gen_binary (IOR
, mode
,
4761 simplify_gen_binary (AND
, mode
,
4766 SUBST (SET_DEST (x
), dest
);
4768 split
= find_split_point (&SET_SRC (x
), insn
, true);
4769 if (split
&& split
!= &SET_SRC (x
))
4773 /* Otherwise, see if this is an operation that we can split into two.
4774 If so, try to split that. */
4775 code
= GET_CODE (SET_SRC (x
));
4780 /* If we are AND'ing with a large constant that is only a single
4781 bit and the result is only being used in a context where we
4782 need to know if it is zero or nonzero, replace it with a bit
4783 extraction. This will avoid the large constant, which might
4784 have taken more than one insn to make. If the constant were
4785 not a valid argument to the AND but took only one insn to make,
4786 this is no worse, but if it took more than one insn, it will
4789 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4790 && REG_P (XEXP (SET_SRC (x
), 0))
4791 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4792 && REG_P (SET_DEST (x
))
4793 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4794 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4795 && XEXP (*split
, 0) == SET_DEST (x
)
4796 && XEXP (*split
, 1) == const0_rtx
)
4798 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4799 XEXP (SET_SRC (x
), 0),
4800 pos
, NULL_RTX
, 1, 1, 0, 0);
4801 if (extraction
!= 0)
4803 SUBST (SET_SRC (x
), extraction
);
4804 return find_split_point (loc
, insn
, false);
4810 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4811 is known to be on, this can be converted into a NEG of a shift. */
4812 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4813 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4814 && 1 <= (pos
= exact_log2
4815 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4816 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4818 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4822 gen_rtx_LSHIFTRT (mode
,
4823 XEXP (SET_SRC (x
), 0),
4826 split
= find_split_point (&SET_SRC (x
), insn
, true);
4827 if (split
&& split
!= &SET_SRC (x
))
4833 inner
= XEXP (SET_SRC (x
), 0);
4835 /* We can't optimize if either mode is a partial integer
4836 mode as we don't know how many bits are significant
4838 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4839 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4843 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4849 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4850 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4852 inner
= XEXP (SET_SRC (x
), 0);
4853 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4854 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4856 if (BITS_BIG_ENDIAN
)
4857 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4858 unsignedp
= (code
== ZERO_EXTRACT
);
4867 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4869 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4871 /* For unsigned, we have a choice of a shift followed by an
4872 AND or two shifts. Use two shifts for field sizes where the
4873 constant might be too large. We assume here that we can
4874 always at least get 8-bit constants in an AND insn, which is
4875 true for every current RISC. */
4877 if (unsignedp
&& len
<= 8)
4882 (mode
, gen_lowpart (mode
, inner
),
4884 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4887 split
= find_split_point (&SET_SRC (x
), insn
, true);
4888 if (split
&& split
!= &SET_SRC (x
))
4895 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4896 gen_rtx_ASHIFT (mode
,
4897 gen_lowpart (mode
, inner
),
4898 GEN_INT (GET_MODE_PRECISION (mode
)
4900 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4902 split
= find_split_point (&SET_SRC (x
), insn
, true);
4903 if (split
&& split
!= &SET_SRC (x
))
4908 /* See if this is a simple operation with a constant as the second
4909 operand. It might be that this constant is out of range and hence
4910 could be used as a split point. */
4911 if (BINARY_P (SET_SRC (x
))
4912 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4913 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4914 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4915 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4916 return &XEXP (SET_SRC (x
), 1);
4918 /* Finally, see if this is a simple operation with its first operand
4919 not in a register. The operation might require this operand in a
4920 register, so return it as a split point. We can always do this
4921 because if the first operand were another operation, we would have
4922 already found it as a split point. */
4923 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4924 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4925 return &XEXP (SET_SRC (x
), 0);
4931 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4932 it is better to write this as (not (ior A B)) so we can split it.
4933 Similarly for IOR. */
4934 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4937 gen_rtx_NOT (GET_MODE (x
),
4938 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4940 XEXP (XEXP (x
, 0), 0),
4941 XEXP (XEXP (x
, 1), 0))));
4942 return find_split_point (loc
, insn
, set_src
);
4945 /* Many RISC machines have a large set of logical insns. If the
4946 second operand is a NOT, put it first so we will try to split the
4947 other operand first. */
4948 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4950 rtx tem
= XEXP (x
, 0);
4951 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4952 SUBST (XEXP (x
, 1), tem
);
4958 /* Canonicalization can produce (minus A (mult B C)), where C is a
4959 constant. It may be better to try splitting (plus (mult B -C) A)
4960 instead if this isn't a multiply by a power of two. */
4961 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4962 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4963 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4965 enum machine_mode mode
= GET_MODE (x
);
4966 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4967 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4968 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4969 XEXP (XEXP (x
, 1), 0),
4970 GEN_INT (other_int
)),
4972 return find_split_point (loc
, insn
, set_src
);
4975 /* Split at a multiply-accumulate instruction. However if this is
4976 the SET_SRC, we likely do not have such an instruction and it's
4977 worthless to try this split. */
4978 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4985 /* Otherwise, select our actions depending on our rtx class. */
4986 switch (GET_RTX_CLASS (code
))
4988 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4990 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4993 /* ... fall through ... */
4995 case RTX_COMM_ARITH
:
4997 case RTX_COMM_COMPARE
:
4998 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5001 /* ... fall through ... */
5003 /* Some machines have (and (shift ...) ...) insns. If X is not
5004 an AND, but XEXP (X, 0) is, use it as our split point. */
5005 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5006 return &XEXP (x
, 0);
5008 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5014 /* Otherwise, we don't have a split point. */
5019 /* Throughout X, replace FROM with TO, and return the result.
5020 The result is TO if X is FROM;
5021 otherwise the result is X, but its contents may have been modified.
5022 If they were modified, a record was made in undobuf so that
5023 undo_all will (among other things) return X to its original state.
5025 If the number of changes necessary is too much to record to undo,
5026 the excess changes are not made, so the result is invalid.
5027 The changes already made can still be undone.
5028 undobuf.num_undo is incremented for such changes, so by testing that
5029 the caller can tell whether the result is valid.
5031 `n_occurrences' is incremented each time FROM is replaced.
5033 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5035 IN_COND is nonzero if we are at the top level of a condition.
5037 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5038 by copying if `n_occurrences' is nonzero. */
5041 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5043 enum rtx_code code
= GET_CODE (x
);
5044 enum machine_mode op0_mode
= VOIDmode
;
5049 /* Two expressions are equal if they are identical copies of a shared
5050 RTX or if they are both registers with the same register number
5053 #define COMBINE_RTX_EQUAL_P(X,Y) \
5055 || (REG_P (X) && REG_P (Y) \
5056 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5058 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5061 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5064 /* If X and FROM are the same register but different modes, they
5065 will not have been seen as equal above. However, the log links code
5066 will make a LOG_LINKS entry for that case. If we do nothing, we
5067 will try to rerecognize our original insn and, when it succeeds,
5068 we will delete the feeding insn, which is incorrect.
5070 So force this insn not to match in this (rare) case. */
5071 if (! in_dest
&& code
== REG
&& REG_P (from
)
5072 && reg_overlap_mentioned_p (x
, from
))
5073 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5075 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5076 of which may contain things that can be combined. */
5077 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5080 /* It is possible to have a subexpression appear twice in the insn.
5081 Suppose that FROM is a register that appears within TO.
5082 Then, after that subexpression has been scanned once by `subst',
5083 the second time it is scanned, TO may be found. If we were
5084 to scan TO here, we would find FROM within it and create a
5085 self-referent rtl structure which is completely wrong. */
5086 if (COMBINE_RTX_EQUAL_P (x
, to
))
5089 /* Parallel asm_operands need special attention because all of the
5090 inputs are shared across the arms. Furthermore, unsharing the
5091 rtl results in recognition failures. Failure to handle this case
5092 specially can result in circular rtl.
5094 Solve this by doing a normal pass across the first entry of the
5095 parallel, and only processing the SET_DESTs of the subsequent
5098 if (code
== PARALLEL
5099 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5100 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5102 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5104 /* If this substitution failed, this whole thing fails. */
5105 if (GET_CODE (new_rtx
) == CLOBBER
5106 && XEXP (new_rtx
, 0) == const0_rtx
)
5109 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5111 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5113 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5116 && GET_CODE (dest
) != CC0
5117 && GET_CODE (dest
) != PC
)
5119 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5121 /* If this substitution failed, this whole thing fails. */
5122 if (GET_CODE (new_rtx
) == CLOBBER
5123 && XEXP (new_rtx
, 0) == const0_rtx
)
5126 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5132 len
= GET_RTX_LENGTH (code
);
5133 fmt
= GET_RTX_FORMAT (code
);
5135 /* We don't need to process a SET_DEST that is a register, CC0,
5136 or PC, so set up to skip this common case. All other cases
5137 where we want to suppress replacing something inside a
5138 SET_SRC are handled via the IN_DEST operand. */
5140 && (REG_P (SET_DEST (x
))
5141 || GET_CODE (SET_DEST (x
)) == CC0
5142 || GET_CODE (SET_DEST (x
)) == PC
))
5145 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5148 op0_mode
= GET_MODE (XEXP (x
, 0));
5150 for (i
= 0; i
< len
; i
++)
5155 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5157 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5159 new_rtx
= (unique_copy
&& n_occurrences
5160 ? copy_rtx (to
) : to
);
5165 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5168 /* If this substitution failed, this whole thing
5170 if (GET_CODE (new_rtx
) == CLOBBER
5171 && XEXP (new_rtx
, 0) == const0_rtx
)
5175 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5178 else if (fmt
[i
] == 'e')
5180 /* If this is a register being set, ignore it. */
5181 new_rtx
= XEXP (x
, i
);
5184 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5186 || code
== STRICT_LOW_PART
))
5189 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5191 /* In general, don't install a subreg involving two
5192 modes not tieable. It can worsen register
5193 allocation, and can even make invalid reload
5194 insns, since the reg inside may need to be copied
5195 from in the outside mode, and that may be invalid
5196 if it is an fp reg copied in integer mode.
5198 We allow two exceptions to this: It is valid if
5199 it is inside another SUBREG and the mode of that
5200 SUBREG and the mode of the inside of TO is
5201 tieable and it is valid if X is a SET that copies
5204 if (GET_CODE (to
) == SUBREG
5205 && ! MODES_TIEABLE_P (GET_MODE (to
),
5206 GET_MODE (SUBREG_REG (to
)))
5207 && ! (code
== SUBREG
5208 && MODES_TIEABLE_P (GET_MODE (x
),
5209 GET_MODE (SUBREG_REG (to
))))
5211 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5214 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5216 #ifdef CANNOT_CHANGE_MODE_CLASS
5219 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5220 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5223 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5226 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5230 /* If we are in a SET_DEST, suppress most cases unless we
5231 have gone inside a MEM, in which case we want to
5232 simplify the address. We assume here that things that
5233 are actually part of the destination have their inner
5234 parts in the first expression. This is true for SUBREG,
5235 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5236 things aside from REG and MEM that should appear in a
5238 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5240 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5241 || code
== ZERO_EXTRACT
))
5244 code
== IF_THEN_ELSE
&& i
== 0,
5247 /* If we found that we will have to reject this combination,
5248 indicate that by returning the CLOBBER ourselves, rather than
5249 an expression containing it. This will speed things up as
5250 well as prevent accidents where two CLOBBERs are considered
5251 to be equal, thus producing an incorrect simplification. */
5253 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5256 if (GET_CODE (x
) == SUBREG
5257 && (CONST_INT_P (new_rtx
)
5258 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5260 enum machine_mode mode
= GET_MODE (x
);
5262 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5263 GET_MODE (SUBREG_REG (x
)),
5266 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5268 else if (CONST_INT_P (new_rtx
)
5269 && GET_CODE (x
) == ZERO_EXTEND
)
5271 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5272 new_rtx
, GET_MODE (XEXP (x
, 0)));
5276 SUBST (XEXP (x
, i
), new_rtx
);
5281 /* Check if we are loading something from the constant pool via float
5282 extension; in this case we would undo compress_float_constant
5283 optimization and degenerate constant load to an immediate value. */
5284 if (GET_CODE (x
) == FLOAT_EXTEND
5285 && MEM_P (XEXP (x
, 0))
5286 && MEM_READONLY_P (XEXP (x
, 0)))
5288 rtx tmp
= avoid_constant_pool_reference (x
);
5293 /* Try to simplify X. If the simplification changed the code, it is likely
5294 that further simplification will help, so loop, but limit the number
5295 of repetitions that will be performed. */
5297 for (i
= 0; i
< 4; i
++)
5299 /* If X is sufficiently simple, don't bother trying to do anything
5301 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5302 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5304 if (GET_CODE (x
) == code
)
5307 code
= GET_CODE (x
);
5309 /* We no longer know the original mode of operand 0 since we
5310 have changed the form of X) */
5311 op0_mode
= VOIDmode
;
5317 /* Simplify X, a piece of RTL. We just operate on the expression at the
5318 outer level; call `subst' to simplify recursively. Return the new
5321 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5322 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5326 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5329 enum rtx_code code
= GET_CODE (x
);
5330 enum machine_mode mode
= GET_MODE (x
);
5334 /* If this is a commutative operation, put a constant last and a complex
5335 expression first. We don't need to do this for comparisons here. */
5336 if (COMMUTATIVE_ARITH_P (x
)
5337 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5340 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5341 SUBST (XEXP (x
, 1), temp
);
5344 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5345 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5346 things. Check for cases where both arms are testing the same
5349 Don't do anything if all operands are very simple. */
5352 && ((!OBJECT_P (XEXP (x
, 0))
5353 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5354 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5355 || (!OBJECT_P (XEXP (x
, 1))
5356 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5357 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5359 && (!OBJECT_P (XEXP (x
, 0))
5360 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5361 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5363 rtx cond
, true_rtx
, false_rtx
;
5365 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5367 /* If everything is a comparison, what we have is highly unlikely
5368 to be simpler, so don't use it. */
5369 && ! (COMPARISON_P (x
)
5370 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5372 rtx cop1
= const0_rtx
;
5373 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5375 if (cond_code
== NE
&& COMPARISON_P (cond
))
5378 /* Simplify the alternative arms; this may collapse the true and
5379 false arms to store-flag values. Be careful to use copy_rtx
5380 here since true_rtx or false_rtx might share RTL with x as a
5381 result of the if_then_else_cond call above. */
5382 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5383 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5385 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5386 is unlikely to be simpler. */
5387 if (general_operand (true_rtx
, VOIDmode
)
5388 && general_operand (false_rtx
, VOIDmode
))
5390 enum rtx_code reversed
;
5392 /* Restarting if we generate a store-flag expression will cause
5393 us to loop. Just drop through in this case. */
5395 /* If the result values are STORE_FLAG_VALUE and zero, we can
5396 just make the comparison operation. */
5397 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5398 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5400 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5401 && ((reversed
= reversed_comparison_code_parts
5402 (cond_code
, cond
, cop1
, NULL
))
5404 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5407 /* Likewise, we can make the negate of a comparison operation
5408 if the result values are - STORE_FLAG_VALUE and zero. */
5409 else if (CONST_INT_P (true_rtx
)
5410 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5411 && false_rtx
== const0_rtx
)
5412 x
= simplify_gen_unary (NEG
, mode
,
5413 simplify_gen_relational (cond_code
,
5417 else if (CONST_INT_P (false_rtx
)
5418 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5419 && true_rtx
== const0_rtx
5420 && ((reversed
= reversed_comparison_code_parts
5421 (cond_code
, cond
, cop1
, NULL
))
5423 x
= simplify_gen_unary (NEG
, mode
,
5424 simplify_gen_relational (reversed
,
5429 return gen_rtx_IF_THEN_ELSE (mode
,
5430 simplify_gen_relational (cond_code
,
5435 true_rtx
, false_rtx
);
5437 code
= GET_CODE (x
);
5438 op0_mode
= VOIDmode
;
5443 /* Try to fold this expression in case we have constants that weren't
5446 switch (GET_RTX_CLASS (code
))
5449 if (op0_mode
== VOIDmode
)
5450 op0_mode
= GET_MODE (XEXP (x
, 0));
5451 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5454 case RTX_COMM_COMPARE
:
5456 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5457 if (cmp_mode
== VOIDmode
)
5459 cmp_mode
= GET_MODE (XEXP (x
, 1));
5460 if (cmp_mode
== VOIDmode
)
5461 cmp_mode
= op0_mode
;
5463 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5464 XEXP (x
, 0), XEXP (x
, 1));
5467 case RTX_COMM_ARITH
:
5469 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5471 case RTX_BITFIELD_OPS
:
5473 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5474 XEXP (x
, 1), XEXP (x
, 2));
5483 code
= GET_CODE (temp
);
5484 op0_mode
= VOIDmode
;
5485 mode
= GET_MODE (temp
);
5488 /* First see if we can apply the inverse distributive law. */
5489 if (code
== PLUS
|| code
== MINUS
5490 || code
== AND
|| code
== IOR
|| code
== XOR
)
5492 x
= apply_distributive_law (x
);
5493 code
= GET_CODE (x
);
5494 op0_mode
= VOIDmode
;
5497 /* If CODE is an associative operation not otherwise handled, see if we
5498 can associate some operands. This can win if they are constants or
5499 if they are logically related (i.e. (a & b) & a). */
5500 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5501 || code
== AND
|| code
== IOR
|| code
== XOR
5502 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5503 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5504 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5506 if (GET_CODE (XEXP (x
, 0)) == code
)
5508 rtx other
= XEXP (XEXP (x
, 0), 0);
5509 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5510 rtx inner_op1
= XEXP (x
, 1);
5513 /* Make sure we pass the constant operand if any as the second
5514 one if this is a commutative operation. */
5515 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5517 rtx tem
= inner_op0
;
5518 inner_op0
= inner_op1
;
5521 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5522 : code
== DIV
? MULT
5524 mode
, inner_op0
, inner_op1
);
5526 /* For commutative operations, try the other pair if that one
5528 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5530 other
= XEXP (XEXP (x
, 0), 1);
5531 inner
= simplify_binary_operation (code
, mode
,
5532 XEXP (XEXP (x
, 0), 0),
5537 return simplify_gen_binary (code
, mode
, other
, inner
);
5541 /* A little bit of algebraic simplification here. */
5545 /* Ensure that our address has any ASHIFTs converted to MULT in case
5546 address-recognizing predicates are called later. */
5547 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5548 SUBST (XEXP (x
, 0), temp
);
5552 if (op0_mode
== VOIDmode
)
5553 op0_mode
= GET_MODE (SUBREG_REG (x
));
5555 /* See if this can be moved to simplify_subreg. */
5556 if (CONSTANT_P (SUBREG_REG (x
))
5557 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5558 /* Don't call gen_lowpart if the inner mode
5559 is VOIDmode and we cannot simplify it, as SUBREG without
5560 inner mode is invalid. */
5561 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5562 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5563 return gen_lowpart (mode
, SUBREG_REG (x
));
5565 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5569 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5575 /* Don't change the mode of the MEM if that would change the meaning
5577 if (MEM_P (SUBREG_REG (x
))
5578 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5579 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5580 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5582 /* Note that we cannot do any narrowing for non-constants since
5583 we might have been counting on using the fact that some bits were
5584 zero. We now do this in the SET. */
5589 temp
= expand_compound_operation (XEXP (x
, 0));
5591 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5592 replaced by (lshiftrt X C). This will convert
5593 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5595 if (GET_CODE (temp
) == ASHIFTRT
5596 && CONST_INT_P (XEXP (temp
, 1))
5597 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5598 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5599 INTVAL (XEXP (temp
, 1)));
5601 /* If X has only a single bit that might be nonzero, say, bit I, convert
5602 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5603 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5604 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5605 or a SUBREG of one since we'd be making the expression more
5606 complex if it was just a register. */
5609 && ! (GET_CODE (temp
) == SUBREG
5610 && REG_P (SUBREG_REG (temp
)))
5611 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5613 rtx temp1
= simplify_shift_const
5614 (NULL_RTX
, ASHIFTRT
, mode
,
5615 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5616 GET_MODE_PRECISION (mode
) - 1 - i
),
5617 GET_MODE_PRECISION (mode
) - 1 - i
);
5619 /* If all we did was surround TEMP with the two shifts, we
5620 haven't improved anything, so don't use it. Otherwise,
5621 we are better off with TEMP1. */
5622 if (GET_CODE (temp1
) != ASHIFTRT
5623 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5624 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5630 /* We can't handle truncation to a partial integer mode here
5631 because we don't know the real bitsize of the partial
5633 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5636 if (HWI_COMPUTABLE_MODE_P (mode
))
5638 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5639 GET_MODE_MASK (mode
), 0));
5641 /* We can truncate a constant value and return it. */
5642 if (CONST_INT_P (XEXP (x
, 0)))
5643 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5645 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5646 whose value is a comparison can be replaced with a subreg if
5647 STORE_FLAG_VALUE permits. */
5648 if (HWI_COMPUTABLE_MODE_P (mode
)
5649 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5650 && (temp
= get_last_value (XEXP (x
, 0)))
5651 && COMPARISON_P (temp
))
5652 return gen_lowpart (mode
, XEXP (x
, 0));
5656 /* (const (const X)) can become (const X). Do it this way rather than
5657 returning the inner CONST since CONST can be shared with a
5659 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5660 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5665 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5666 can add in an offset. find_split_point will split this address up
5667 again if it doesn't match. */
5668 if (GET_CODE (XEXP (x
, 0)) == HIGH
5669 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5675 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5676 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5677 bit-field and can be replaced by either a sign_extend or a
5678 sign_extract. The `and' may be a zero_extend and the two
5679 <c>, -<c> constants may be reversed. */
5680 if (GET_CODE (XEXP (x
, 0)) == XOR
5681 && CONST_INT_P (XEXP (x
, 1))
5682 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5683 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5684 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5685 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5686 && HWI_COMPUTABLE_MODE_P (mode
)
5687 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5688 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5689 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5690 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5691 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5692 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5693 == (unsigned int) i
+ 1))))
5694 return simplify_shift_const
5695 (NULL_RTX
, ASHIFTRT
, mode
,
5696 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5697 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5698 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5699 GET_MODE_PRECISION (mode
) - (i
+ 1));
5701 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5702 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5703 the bitsize of the mode - 1. This allows simplification of
5704 "a = (b & 8) == 0;" */
5705 if (XEXP (x
, 1) == constm1_rtx
5706 && !REG_P (XEXP (x
, 0))
5707 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5708 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5709 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5710 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5711 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5712 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5713 GET_MODE_PRECISION (mode
) - 1),
5714 GET_MODE_PRECISION (mode
) - 1);
5716 /* If we are adding two things that have no bits in common, convert
5717 the addition into an IOR. This will often be further simplified,
5718 for example in cases like ((a & 1) + (a & 2)), which can
5721 if (HWI_COMPUTABLE_MODE_P (mode
)
5722 && (nonzero_bits (XEXP (x
, 0), mode
)
5723 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5725 /* Try to simplify the expression further. */
5726 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5727 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5729 /* If we could, great. If not, do not go ahead with the IOR
5730 replacement, since PLUS appears in many special purpose
5731 address arithmetic instructions. */
5732 if (GET_CODE (temp
) != CLOBBER
5733 && (GET_CODE (temp
) != IOR
5734 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5735 || XEXP (temp
, 1) != XEXP (x
, 1))
5736 && (XEXP (temp
, 0) != XEXP (x
, 1)
5737 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5743 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5744 (and <foo> (const_int pow2-1)) */
5745 if (GET_CODE (XEXP (x
, 1)) == AND
5746 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5747 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5748 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5749 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5750 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5754 /* If we have (mult (plus A B) C), apply the distributive law and then
5755 the inverse distributive law to see if things simplify. This
5756 occurs mostly in addresses, often when unrolling loops. */
5758 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5760 rtx result
= distribute_and_simplify_rtx (x
, 0);
5765 /* Try simplify a*(b/c) as (a*b)/c. */
5766 if (FLOAT_MODE_P (mode
) && flag_associative_math
5767 && GET_CODE (XEXP (x
, 0)) == DIV
)
5769 rtx tem
= simplify_binary_operation (MULT
, mode
,
5770 XEXP (XEXP (x
, 0), 0),
5773 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5778 /* If this is a divide by a power of two, treat it as a shift if
5779 its first operand is a shift. */
5780 if (CONST_INT_P (XEXP (x
, 1))
5781 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5782 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5783 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5784 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5785 || GET_CODE (XEXP (x
, 0)) == ROTATE
5786 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5787 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5791 case GT
: case GTU
: case GE
: case GEU
:
5792 case LT
: case LTU
: case LE
: case LEU
:
5793 case UNEQ
: case LTGT
:
5794 case UNGT
: case UNGE
:
5795 case UNLT
: case UNLE
:
5796 case UNORDERED
: case ORDERED
:
5797 /* If the first operand is a condition code, we can't do anything
5799 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5800 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5801 && ! CC0_P (XEXP (x
, 0))))
5803 rtx op0
= XEXP (x
, 0);
5804 rtx op1
= XEXP (x
, 1);
5805 enum rtx_code new_code
;
5807 if (GET_CODE (op0
) == COMPARE
)
5808 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5810 /* Simplify our comparison, if possible. */
5811 new_code
= simplify_comparison (code
, &op0
, &op1
);
5813 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5814 if only the low-order bit is possibly nonzero in X (such as when
5815 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5816 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5817 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5820 Remove any ZERO_EXTRACT we made when thinking this was a
5821 comparison. It may now be simpler to use, e.g., an AND. If a
5822 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5823 the call to make_compound_operation in the SET case.
5825 Don't apply these optimizations if the caller would
5826 prefer a comparison rather than a value.
5827 E.g., for the condition in an IF_THEN_ELSE most targets need
5828 an explicit comparison. */
5833 else if (STORE_FLAG_VALUE
== 1
5834 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5835 && op1
== const0_rtx
5836 && mode
== GET_MODE (op0
)
5837 && nonzero_bits (op0
, mode
) == 1)
5838 return gen_lowpart (mode
,
5839 expand_compound_operation (op0
));
5841 else if (STORE_FLAG_VALUE
== 1
5842 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5843 && op1
== const0_rtx
5844 && mode
== GET_MODE (op0
)
5845 && (num_sign_bit_copies (op0
, mode
)
5846 == GET_MODE_PRECISION (mode
)))
5848 op0
= expand_compound_operation (op0
);
5849 return simplify_gen_unary (NEG
, mode
,
5850 gen_lowpart (mode
, op0
),
5854 else if (STORE_FLAG_VALUE
== 1
5855 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5856 && op1
== const0_rtx
5857 && mode
== GET_MODE (op0
)
5858 && nonzero_bits (op0
, mode
) == 1)
5860 op0
= expand_compound_operation (op0
);
5861 return simplify_gen_binary (XOR
, mode
,
5862 gen_lowpart (mode
, op0
),
5866 else if (STORE_FLAG_VALUE
== 1
5867 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5868 && op1
== const0_rtx
5869 && mode
== GET_MODE (op0
)
5870 && (num_sign_bit_copies (op0
, mode
)
5871 == GET_MODE_PRECISION (mode
)))
5873 op0
= expand_compound_operation (op0
);
5874 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5877 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5882 else if (STORE_FLAG_VALUE
== -1
5883 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5884 && op1
== const0_rtx
5885 && (num_sign_bit_copies (op0
, mode
)
5886 == GET_MODE_PRECISION (mode
)))
5887 return gen_lowpart (mode
,
5888 expand_compound_operation (op0
));
5890 else if (STORE_FLAG_VALUE
== -1
5891 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5892 && op1
== const0_rtx
5893 && mode
== GET_MODE (op0
)
5894 && nonzero_bits (op0
, mode
) == 1)
5896 op0
= expand_compound_operation (op0
);
5897 return simplify_gen_unary (NEG
, mode
,
5898 gen_lowpart (mode
, op0
),
5902 else if (STORE_FLAG_VALUE
== -1
5903 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5904 && op1
== const0_rtx
5905 && mode
== GET_MODE (op0
)
5906 && (num_sign_bit_copies (op0
, mode
)
5907 == GET_MODE_PRECISION (mode
)))
5909 op0
= expand_compound_operation (op0
);
5910 return simplify_gen_unary (NOT
, mode
,
5911 gen_lowpart (mode
, op0
),
5915 /* If X is 0/1, (eq X 0) is X-1. */
5916 else if (STORE_FLAG_VALUE
== -1
5917 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5918 && op1
== const0_rtx
5919 && mode
== GET_MODE (op0
)
5920 && nonzero_bits (op0
, mode
) == 1)
5922 op0
= expand_compound_operation (op0
);
5923 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5926 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5927 one bit that might be nonzero, we can convert (ne x 0) to
5928 (ashift x c) where C puts the bit in the sign bit. Remove any
5929 AND with STORE_FLAG_VALUE when we are done, since we are only
5930 going to test the sign bit. */
5931 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5932 && HWI_COMPUTABLE_MODE_P (mode
)
5933 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5934 && op1
== const0_rtx
5935 && mode
== GET_MODE (op0
)
5936 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5938 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5939 expand_compound_operation (op0
),
5940 GET_MODE_PRECISION (mode
) - 1 - i
);
5941 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5947 /* If the code changed, return a whole new comparison. */
5948 if (new_code
!= code
)
5949 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5951 /* Otherwise, keep this operation, but maybe change its operands.
5952 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5953 SUBST (XEXP (x
, 0), op0
);
5954 SUBST (XEXP (x
, 1), op1
);
5959 return simplify_if_then_else (x
);
5965 /* If we are processing SET_DEST, we are done. */
5969 return expand_compound_operation (x
);
5972 return simplify_set (x
);
5976 return simplify_logical (x
);
5983 /* If this is a shift by a constant amount, simplify it. */
5984 if (CONST_INT_P (XEXP (x
, 1)))
5985 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5986 INTVAL (XEXP (x
, 1)));
5988 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5990 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5991 ((unsigned HOST_WIDE_INT
) 1
5992 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6004 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6007 simplify_if_then_else (rtx x
)
6009 enum machine_mode mode
= GET_MODE (x
);
6010 rtx cond
= XEXP (x
, 0);
6011 rtx true_rtx
= XEXP (x
, 1);
6012 rtx false_rtx
= XEXP (x
, 2);
6013 enum rtx_code true_code
= GET_CODE (cond
);
6014 int comparison_p
= COMPARISON_P (cond
);
6017 enum rtx_code false_code
;
6020 /* Simplify storing of the truth value. */
6021 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6022 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6023 XEXP (cond
, 0), XEXP (cond
, 1));
6025 /* Also when the truth value has to be reversed. */
6027 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6028 && (reversed
= reversed_comparison (cond
, mode
)))
6031 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6032 in it is being compared against certain values. Get the true and false
6033 comparisons and see if that says anything about the value of each arm. */
6036 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6038 && REG_P (XEXP (cond
, 0)))
6041 rtx from
= XEXP (cond
, 0);
6042 rtx true_val
= XEXP (cond
, 1);
6043 rtx false_val
= true_val
;
6046 /* If FALSE_CODE is EQ, swap the codes and arms. */
6048 if (false_code
== EQ
)
6050 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6051 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6054 /* If we are comparing against zero and the expression being tested has
6055 only a single bit that might be nonzero, that is its value when it is
6056 not equal to zero. Similarly if it is known to be -1 or 0. */
6058 if (true_code
== EQ
&& true_val
== const0_rtx
6059 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6062 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6064 else if (true_code
== EQ
&& true_val
== const0_rtx
6065 && (num_sign_bit_copies (from
, GET_MODE (from
))
6066 == GET_MODE_PRECISION (GET_MODE (from
))))
6069 false_val
= constm1_rtx
;
6072 /* Now simplify an arm if we know the value of the register in the
6073 branch and it is used in the arm. Be careful due to the potential
6074 of locally-shared RTL. */
6076 if (reg_mentioned_p (from
, true_rtx
))
6077 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6079 pc_rtx
, pc_rtx
, 0, 0, 0);
6080 if (reg_mentioned_p (from
, false_rtx
))
6081 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6083 pc_rtx
, pc_rtx
, 0, 0, 0);
6085 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6086 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6088 true_rtx
= XEXP (x
, 1);
6089 false_rtx
= XEXP (x
, 2);
6090 true_code
= GET_CODE (cond
);
6093 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6094 reversed, do so to avoid needing two sets of patterns for
6095 subtract-and-branch insns. Similarly if we have a constant in the true
6096 arm, the false arm is the same as the first operand of the comparison, or
6097 the false arm is more complicated than the true arm. */
6100 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6101 && (true_rtx
== pc_rtx
6102 || (CONSTANT_P (true_rtx
)
6103 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6104 || true_rtx
== const0_rtx
6105 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6106 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6107 && !OBJECT_P (false_rtx
))
6108 || reg_mentioned_p (true_rtx
, false_rtx
)
6109 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6111 true_code
= reversed_comparison_code (cond
, NULL
);
6112 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6113 SUBST (XEXP (x
, 1), false_rtx
);
6114 SUBST (XEXP (x
, 2), true_rtx
);
6116 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6119 /* It is possible that the conditional has been simplified out. */
6120 true_code
= GET_CODE (cond
);
6121 comparison_p
= COMPARISON_P (cond
);
6124 /* If the two arms are identical, we don't need the comparison. */
6126 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6129 /* Convert a == b ? b : a to "a". */
6130 if (true_code
== EQ
&& ! side_effects_p (cond
)
6131 && !HONOR_NANS (mode
)
6132 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6133 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6135 else if (true_code
== NE
&& ! side_effects_p (cond
)
6136 && !HONOR_NANS (mode
)
6137 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6138 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6141 /* Look for cases where we have (abs x) or (neg (abs X)). */
6143 if (GET_MODE_CLASS (mode
) == MODE_INT
6145 && XEXP (cond
, 1) == const0_rtx
6146 && GET_CODE (false_rtx
) == NEG
6147 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6148 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6149 && ! side_effects_p (true_rtx
))
6154 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6158 simplify_gen_unary (NEG
, mode
,
6159 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6165 /* Look for MIN or MAX. */
6167 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6169 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6170 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6171 && ! side_effects_p (cond
))
6176 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6179 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6182 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6185 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6190 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6191 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6192 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6193 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6194 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6195 neither 1 or -1, but it isn't worth checking for. */
6197 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6199 && GET_MODE_CLASS (mode
) == MODE_INT
6200 && ! side_effects_p (x
))
6202 rtx t
= make_compound_operation (true_rtx
, SET
);
6203 rtx f
= make_compound_operation (false_rtx
, SET
);
6204 rtx cond_op0
= XEXP (cond
, 0);
6205 rtx cond_op1
= XEXP (cond
, 1);
6206 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6207 enum machine_mode m
= mode
;
6208 rtx z
= 0, c1
= NULL_RTX
;
6210 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6211 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6212 || GET_CODE (t
) == ASHIFT
6213 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6214 && rtx_equal_p (XEXP (t
, 0), f
))
6215 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6217 /* If an identity-zero op is commutative, check whether there
6218 would be a match if we swapped the operands. */
6219 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6220 || GET_CODE (t
) == XOR
)
6221 && rtx_equal_p (XEXP (t
, 1), f
))
6222 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6223 else if (GET_CODE (t
) == SIGN_EXTEND
6224 && (GET_CODE (XEXP (t
, 0)) == PLUS
6225 || GET_CODE (XEXP (t
, 0)) == MINUS
6226 || GET_CODE (XEXP (t
, 0)) == IOR
6227 || GET_CODE (XEXP (t
, 0)) == XOR
6228 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6229 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6230 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6231 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6232 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6233 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6234 && (num_sign_bit_copies (f
, GET_MODE (f
))
6236 (GET_MODE_PRECISION (mode
)
6237 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6239 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6240 extend_op
= SIGN_EXTEND
;
6241 m
= GET_MODE (XEXP (t
, 0));
6243 else if (GET_CODE (t
) == SIGN_EXTEND
6244 && (GET_CODE (XEXP (t
, 0)) == PLUS
6245 || GET_CODE (XEXP (t
, 0)) == IOR
6246 || GET_CODE (XEXP (t
, 0)) == XOR
)
6247 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6248 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6249 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6250 && (num_sign_bit_copies (f
, GET_MODE (f
))
6252 (GET_MODE_PRECISION (mode
)
6253 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6255 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6256 extend_op
= SIGN_EXTEND
;
6257 m
= GET_MODE (XEXP (t
, 0));
6259 else if (GET_CODE (t
) == ZERO_EXTEND
6260 && (GET_CODE (XEXP (t
, 0)) == PLUS
6261 || GET_CODE (XEXP (t
, 0)) == MINUS
6262 || GET_CODE (XEXP (t
, 0)) == IOR
6263 || GET_CODE (XEXP (t
, 0)) == XOR
6264 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6265 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6266 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6267 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6268 && HWI_COMPUTABLE_MODE_P (mode
)
6269 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6270 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6271 && ((nonzero_bits (f
, GET_MODE (f
))
6272 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6275 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6276 extend_op
= ZERO_EXTEND
;
6277 m
= GET_MODE (XEXP (t
, 0));
6279 else if (GET_CODE (t
) == ZERO_EXTEND
6280 && (GET_CODE (XEXP (t
, 0)) == PLUS
6281 || GET_CODE (XEXP (t
, 0)) == IOR
6282 || GET_CODE (XEXP (t
, 0)) == XOR
)
6283 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6284 && HWI_COMPUTABLE_MODE_P (mode
)
6285 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6286 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6287 && ((nonzero_bits (f
, GET_MODE (f
))
6288 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6291 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6292 extend_op
= ZERO_EXTEND
;
6293 m
= GET_MODE (XEXP (t
, 0));
6298 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6299 cond_op0
, cond_op1
),
6300 pc_rtx
, pc_rtx
, 0, 0, 0);
6301 temp
= simplify_gen_binary (MULT
, m
, temp
,
6302 simplify_gen_binary (MULT
, m
, c1
,
6304 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6305 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6307 if (extend_op
!= UNKNOWN
)
6308 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6314 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6315 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6316 negation of a single bit, we can convert this operation to a shift. We
6317 can actually do this more generally, but it doesn't seem worth it. */
6319 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6320 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6321 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6322 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6323 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6324 == GET_MODE_PRECISION (mode
))
6325 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6327 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6328 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6330 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6331 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6332 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6333 && GET_MODE (XEXP (cond
, 0)) == mode
6334 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6335 == nonzero_bits (XEXP (cond
, 0), mode
)
6336 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6337 return XEXP (cond
, 0);
6342 /* Simplify X, a SET expression. Return the new expression. */
6345 simplify_set (rtx x
)
6347 rtx src
= SET_SRC (x
);
6348 rtx dest
= SET_DEST (x
);
6349 enum machine_mode mode
6350 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6354 /* (set (pc) (return)) gets written as (return). */
6355 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6358 /* Now that we know for sure which bits of SRC we are using, see if we can
6359 simplify the expression for the object knowing that we only need the
6362 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6364 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6365 SUBST (SET_SRC (x
), src
);
6368 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6369 the comparison result and try to simplify it unless we already have used
6370 undobuf.other_insn. */
6371 if ((GET_MODE_CLASS (mode
) == MODE_CC
6372 || GET_CODE (src
) == COMPARE
6374 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6375 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6376 && COMPARISON_P (*cc_use
)
6377 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6379 enum rtx_code old_code
= GET_CODE (*cc_use
);
6380 enum rtx_code new_code
;
6382 int other_changed
= 0;
6383 rtx inner_compare
= NULL_RTX
;
6384 enum machine_mode compare_mode
= GET_MODE (dest
);
6386 if (GET_CODE (src
) == COMPARE
)
6388 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6389 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6391 inner_compare
= op0
;
6392 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6396 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6398 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6401 new_code
= old_code
;
6402 else if (!CONSTANT_P (tmp
))
6404 new_code
= GET_CODE (tmp
);
6405 op0
= XEXP (tmp
, 0);
6406 op1
= XEXP (tmp
, 1);
6410 rtx pat
= PATTERN (other_insn
);
6411 undobuf
.other_insn
= other_insn
;
6412 SUBST (*cc_use
, tmp
);
6414 /* Attempt to simplify CC user. */
6415 if (GET_CODE (pat
) == SET
)
6417 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6418 if (new_rtx
!= NULL_RTX
)
6419 SUBST (SET_SRC (pat
), new_rtx
);
6422 /* Convert X into a no-op move. */
6423 SUBST (SET_DEST (x
), pc_rtx
);
6424 SUBST (SET_SRC (x
), pc_rtx
);
6428 /* Simplify our comparison, if possible. */
6429 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6431 #ifdef SELECT_CC_MODE
6432 /* If this machine has CC modes other than CCmode, check to see if we
6433 need to use a different CC mode here. */
6434 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6435 compare_mode
= GET_MODE (op0
);
6436 else if (inner_compare
6437 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6438 && new_code
== old_code
6439 && op0
== XEXP (inner_compare
, 0)
6440 && op1
== XEXP (inner_compare
, 1))
6441 compare_mode
= GET_MODE (inner_compare
);
6443 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6446 /* If the mode changed, we have to change SET_DEST, the mode in the
6447 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6448 a hard register, just build new versions with the proper mode. If it
6449 is a pseudo, we lose unless it is only time we set the pseudo, in
6450 which case we can safely change its mode. */
6451 if (compare_mode
!= GET_MODE (dest
))
6453 if (can_change_dest_mode (dest
, 0, compare_mode
))
6455 unsigned int regno
= REGNO (dest
);
6458 if (regno
< FIRST_PSEUDO_REGISTER
)
6459 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6462 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6463 new_dest
= regno_reg_rtx
[regno
];
6466 SUBST (SET_DEST (x
), new_dest
);
6467 SUBST (XEXP (*cc_use
, 0), new_dest
);
6474 #endif /* SELECT_CC_MODE */
6476 /* If the code changed, we have to build a new comparison in
6477 undobuf.other_insn. */
6478 if (new_code
!= old_code
)
6480 int other_changed_previously
= other_changed
;
6481 unsigned HOST_WIDE_INT mask
;
6482 rtx old_cc_use
= *cc_use
;
6484 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6488 /* If the only change we made was to change an EQ into an NE or
6489 vice versa, OP0 has only one bit that might be nonzero, and OP1
6490 is zero, check if changing the user of the condition code will
6491 produce a valid insn. If it won't, we can keep the original code
6492 in that insn by surrounding our operation with an XOR. */
6494 if (((old_code
== NE
&& new_code
== EQ
)
6495 || (old_code
== EQ
&& new_code
== NE
))
6496 && ! other_changed_previously
&& op1
== const0_rtx
6497 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6498 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6500 rtx pat
= PATTERN (other_insn
), note
= 0;
6502 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6503 && ! check_asm_operands (pat
)))
6505 *cc_use
= old_cc_use
;
6508 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6509 op0
, GEN_INT (mask
));
6515 undobuf
.other_insn
= other_insn
;
6517 /* Otherwise, if we didn't previously have a COMPARE in the
6518 correct mode, we need one. */
6519 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6521 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6524 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6526 SUBST (SET_SRC (x
), op0
);
6529 /* Otherwise, update the COMPARE if needed. */
6530 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6532 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6538 /* Get SET_SRC in a form where we have placed back any
6539 compound expressions. Then do the checks below. */
6540 src
= make_compound_operation (src
, SET
);
6541 SUBST (SET_SRC (x
), src
);
6544 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6545 and X being a REG or (subreg (reg)), we may be able to convert this to
6546 (set (subreg:m2 x) (op)).
6548 We can always do this if M1 is narrower than M2 because that means that
6549 we only care about the low bits of the result.
6551 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6552 perform a narrower operation than requested since the high-order bits will
6553 be undefined. On machine where it is defined, this transformation is safe
6554 as long as M1 and M2 have the same number of words. */
6556 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6557 && !OBJECT_P (SUBREG_REG (src
))
6558 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6560 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6561 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6562 #ifndef WORD_REGISTER_OPERATIONS
6563 && (GET_MODE_SIZE (GET_MODE (src
))
6564 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6566 #ifdef CANNOT_CHANGE_MODE_CLASS
6567 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6568 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6569 GET_MODE (SUBREG_REG (src
)),
6573 || (GET_CODE (dest
) == SUBREG
6574 && REG_P (SUBREG_REG (dest
)))))
6576 SUBST (SET_DEST (x
),
6577 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6579 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6581 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6585 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6588 && GET_CODE (src
) == SUBREG
6589 && subreg_lowpart_p (src
)
6590 && (GET_MODE_PRECISION (GET_MODE (src
))
6591 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6593 rtx inner
= SUBREG_REG (src
);
6594 enum machine_mode inner_mode
= GET_MODE (inner
);
6596 /* Here we make sure that we don't have a sign bit on. */
6597 if (val_signbit_known_clear_p (GET_MODE (src
),
6598 nonzero_bits (inner
, inner_mode
)))
6600 SUBST (SET_SRC (x
), inner
);
6606 #ifdef LOAD_EXTEND_OP
6607 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6608 would require a paradoxical subreg. Replace the subreg with a
6609 zero_extend to avoid the reload that would otherwise be required. */
6611 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6612 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6613 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6614 && SUBREG_BYTE (src
) == 0
6615 && paradoxical_subreg_p (src
)
6616 && MEM_P (SUBREG_REG (src
)))
6619 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6620 GET_MODE (src
), SUBREG_REG (src
)));
6626 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6627 are comparing an item known to be 0 or -1 against 0, use a logical
6628 operation instead. Check for one of the arms being an IOR of the other
6629 arm with some value. We compute three terms to be IOR'ed together. In
6630 practice, at most two will be nonzero. Then we do the IOR's. */
6632 if (GET_CODE (dest
) != PC
6633 && GET_CODE (src
) == IF_THEN_ELSE
6634 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6635 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6636 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6637 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6638 #ifdef HAVE_conditional_move
6639 && ! can_conditionally_move_p (GET_MODE (src
))
6641 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6642 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6643 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6644 && ! side_effects_p (src
))
6646 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6647 ? XEXP (src
, 1) : XEXP (src
, 2));
6648 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6649 ? XEXP (src
, 2) : XEXP (src
, 1));
6650 rtx term1
= const0_rtx
, term2
, term3
;
6652 if (GET_CODE (true_rtx
) == IOR
6653 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6654 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6655 else if (GET_CODE (true_rtx
) == IOR
6656 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6657 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6658 else if (GET_CODE (false_rtx
) == IOR
6659 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6660 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6661 else if (GET_CODE (false_rtx
) == IOR
6662 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6663 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6665 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6666 XEXP (XEXP (src
, 0), 0), true_rtx
);
6667 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6668 simplify_gen_unary (NOT
, GET_MODE (src
),
6669 XEXP (XEXP (src
, 0), 0),
6674 simplify_gen_binary (IOR
, GET_MODE (src
),
6675 simplify_gen_binary (IOR
, GET_MODE (src
),
6682 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6683 whole thing fail. */
6684 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6686 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6689 /* Convert this into a field assignment operation, if possible. */
6690 return make_field_assignment (x
);
6693 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6697 simplify_logical (rtx x
)
6699 enum machine_mode mode
= GET_MODE (x
);
6700 rtx op0
= XEXP (x
, 0);
6701 rtx op1
= XEXP (x
, 1);
6703 switch (GET_CODE (x
))
6706 /* We can call simplify_and_const_int only if we don't lose
6707 any (sign) bits when converting INTVAL (op1) to
6708 "unsigned HOST_WIDE_INT". */
6709 if (CONST_INT_P (op1
)
6710 && (HWI_COMPUTABLE_MODE_P (mode
)
6711 || INTVAL (op1
) > 0))
6713 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6714 if (GET_CODE (x
) != AND
)
6721 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6722 apply the distributive law and then the inverse distributive
6723 law to see if things simplify. */
6724 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6726 rtx result
= distribute_and_simplify_rtx (x
, 0);
6730 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6732 rtx result
= distribute_and_simplify_rtx (x
, 1);
6739 /* If we have (ior (and A B) C), apply the distributive law and then
6740 the inverse distributive law to see if things simplify. */
6742 if (GET_CODE (op0
) == AND
)
6744 rtx result
= distribute_and_simplify_rtx (x
, 0);
6749 if (GET_CODE (op1
) == AND
)
6751 rtx result
= distribute_and_simplify_rtx (x
, 1);
6764 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6765 operations" because they can be replaced with two more basic operations.
6766 ZERO_EXTEND is also considered "compound" because it can be replaced with
6767 an AND operation, which is simpler, though only one operation.
6769 The function expand_compound_operation is called with an rtx expression
6770 and will convert it to the appropriate shifts and AND operations,
6771 simplifying at each stage.
6773 The function make_compound_operation is called to convert an expression
6774 consisting of shifts and ANDs into the equivalent compound expression.
6775 It is the inverse of this function, loosely speaking. */
6778 expand_compound_operation (rtx x
)
6780 unsigned HOST_WIDE_INT pos
= 0, len
;
6782 unsigned int modewidth
;
6785 switch (GET_CODE (x
))
6790 /* We can't necessarily use a const_int for a multiword mode;
6791 it depends on implicitly extending the value.
6792 Since we don't know the right way to extend it,
6793 we can't tell whether the implicit way is right.
6795 Even for a mode that is no wider than a const_int,
6796 we can't win, because we need to sign extend one of its bits through
6797 the rest of it, and we don't know which bit. */
6798 if (CONST_INT_P (XEXP (x
, 0)))
6801 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6802 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6803 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6804 reloaded. If not for that, MEM's would very rarely be safe.
6806 Reject MODEs bigger than a word, because we might not be able
6807 to reference a two-register group starting with an arbitrary register
6808 (and currently gen_lowpart might crash for a SUBREG). */
6810 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6813 /* Reject MODEs that aren't scalar integers because turning vector
6814 or complex modes into shifts causes problems. */
6816 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6819 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6820 /* If the inner object has VOIDmode (the only way this can happen
6821 is if it is an ASM_OPERANDS), we can't do anything since we don't
6822 know how much masking to do. */
6831 /* ... fall through ... */
6834 /* If the operand is a CLOBBER, just return it. */
6835 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6838 if (!CONST_INT_P (XEXP (x
, 1))
6839 || !CONST_INT_P (XEXP (x
, 2))
6840 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6843 /* Reject MODEs that aren't scalar integers because turning vector
6844 or complex modes into shifts causes problems. */
6846 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6849 len
= INTVAL (XEXP (x
, 1));
6850 pos
= INTVAL (XEXP (x
, 2));
6852 /* This should stay within the object being extracted, fail otherwise. */
6853 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6856 if (BITS_BIG_ENDIAN
)
6857 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6864 /* Convert sign extension to zero extension, if we know that the high
6865 bit is not set, as this is easier to optimize. It will be converted
6866 back to cheaper alternative in make_extraction. */
6867 if (GET_CODE (x
) == SIGN_EXTEND
6868 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6869 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6870 & ~(((unsigned HOST_WIDE_INT
)
6871 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6875 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6876 rtx temp2
= expand_compound_operation (temp
);
6878 /* Make sure this is a profitable operation. */
6879 if (set_src_cost (x
, optimize_this_for_speed_p
)
6880 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6882 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6883 > set_src_cost (temp
, optimize_this_for_speed_p
))
6889 /* We can optimize some special cases of ZERO_EXTEND. */
6890 if (GET_CODE (x
) == ZERO_EXTEND
)
6892 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6893 know that the last value didn't have any inappropriate bits
6895 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6896 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6897 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6898 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6899 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6900 return XEXP (XEXP (x
, 0), 0);
6902 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6903 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6904 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6905 && subreg_lowpart_p (XEXP (x
, 0))
6906 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6907 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6908 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6909 return SUBREG_REG (XEXP (x
, 0));
6911 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6912 is a comparison and STORE_FLAG_VALUE permits. This is like
6913 the first case, but it works even when GET_MODE (x) is larger
6914 than HOST_WIDE_INT. */
6915 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6916 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6917 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6918 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6919 <= HOST_BITS_PER_WIDE_INT
)
6920 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6921 return XEXP (XEXP (x
, 0), 0);
6923 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6924 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6925 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6926 && subreg_lowpart_p (XEXP (x
, 0))
6927 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6928 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6929 <= HOST_BITS_PER_WIDE_INT
)
6930 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6931 return SUBREG_REG (XEXP (x
, 0));
6935 /* If we reach here, we want to return a pair of shifts. The inner
6936 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6937 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6938 logical depending on the value of UNSIGNEDP.
6940 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6941 converted into an AND of a shift.
6943 We must check for the case where the left shift would have a negative
6944 count. This can happen in a case like (x >> 31) & 255 on machines
6945 that can't shift by a constant. On those machines, we would first
6946 combine the shift with the AND to produce a variable-position
6947 extraction. Then the constant of 31 would be substituted in
6948 to produce such a position. */
6950 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6951 if (modewidth
>= pos
+ len
)
6953 enum machine_mode mode
= GET_MODE (x
);
6954 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6955 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6957 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6958 tem
, modewidth
- pos
- len
);
6959 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6960 mode
, tem
, modewidth
- len
);
6962 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6963 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6964 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6967 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6969 /* Any other cases we can't handle. */
6972 /* If we couldn't do this for some reason, return the original
6974 if (GET_CODE (tem
) == CLOBBER
)
6980 /* X is a SET which contains an assignment of one object into
6981 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6982 or certain SUBREGS). If possible, convert it into a series of
6985 We half-heartedly support variable positions, but do not at all
6986 support variable lengths. */
6989 expand_field_assignment (const_rtx x
)
6992 rtx pos
; /* Always counts from low bit. */
6994 rtx mask
, cleared
, masked
;
6995 enum machine_mode compute_mode
;
6997 /* Loop until we find something we can't simplify. */
7000 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7001 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7003 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7004 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7005 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7007 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7008 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7010 inner
= XEXP (SET_DEST (x
), 0);
7011 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7012 pos
= XEXP (SET_DEST (x
), 2);
7014 /* A constant position should stay within the width of INNER. */
7015 if (CONST_INT_P (pos
)
7016 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7019 if (BITS_BIG_ENDIAN
)
7021 if (CONST_INT_P (pos
))
7022 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7024 else if (GET_CODE (pos
) == MINUS
7025 && CONST_INT_P (XEXP (pos
, 1))
7026 && (INTVAL (XEXP (pos
, 1))
7027 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7028 /* If position is ADJUST - X, new position is X. */
7029 pos
= XEXP (pos
, 0);
7031 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7032 GEN_INT (GET_MODE_PRECISION (
7039 /* A SUBREG between two modes that occupy the same numbers of words
7040 can be done by moving the SUBREG to the source. */
7041 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7042 /* We need SUBREGs to compute nonzero_bits properly. */
7043 && nonzero_sign_valid
7044 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7045 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7046 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7047 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7049 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
7051 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7058 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7059 inner
= SUBREG_REG (inner
);
7061 compute_mode
= GET_MODE (inner
);
7063 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7064 if (! SCALAR_INT_MODE_P (compute_mode
))
7066 enum machine_mode imode
;
7068 /* Don't do anything for vector or complex integral types. */
7069 if (! FLOAT_MODE_P (compute_mode
))
7072 /* Try to find an integral mode to pun with. */
7073 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7074 if (imode
== BLKmode
)
7077 compute_mode
= imode
;
7078 inner
= gen_lowpart (imode
, inner
);
7081 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7082 if (len
>= HOST_BITS_PER_WIDE_INT
)
7085 /* Now compute the equivalent expression. Make a copy of INNER
7086 for the SET_DEST in case it is a MEM into which we will substitute;
7087 we don't want shared RTL in that case. */
7088 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7089 cleared
= simplify_gen_binary (AND
, compute_mode
,
7090 simplify_gen_unary (NOT
, compute_mode
,
7091 simplify_gen_binary (ASHIFT
,
7096 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7097 simplify_gen_binary (
7099 gen_lowpart (compute_mode
, SET_SRC (x
)),
7103 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7104 simplify_gen_binary (IOR
, compute_mode
,
7111 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7112 it is an RTX that represents a variable starting position; otherwise,
7113 POS is the (constant) starting bit position (counted from the LSB).
7115 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7118 IN_DEST is nonzero if this is a reference in the destination of a
7119 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7120 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7123 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7124 ZERO_EXTRACT should be built even for bits starting at bit 0.
7126 MODE is the desired mode of the result (if IN_DEST == 0).
7128 The result is an RTX for the extraction or NULL_RTX if the target
7132 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7133 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7134 int in_dest
, int in_compare
)
7136 /* This mode describes the size of the storage area
7137 to fetch the overall value from. Within that, we
7138 ignore the POS lowest bits, etc. */
7139 enum machine_mode is_mode
= GET_MODE (inner
);
7140 enum machine_mode inner_mode
;
7141 enum machine_mode wanted_inner_mode
;
7142 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7143 enum machine_mode pos_mode
= word_mode
;
7144 enum machine_mode extraction_mode
= word_mode
;
7145 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7147 rtx orig_pos_rtx
= pos_rtx
;
7148 HOST_WIDE_INT orig_pos
;
7150 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7152 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7153 consider just the QI as the memory to extract from.
7154 The subreg adds or removes high bits; its mode is
7155 irrelevant to the meaning of this extraction,
7156 since POS and LEN count from the lsb. */
7157 if (MEM_P (SUBREG_REG (inner
)))
7158 is_mode
= GET_MODE (SUBREG_REG (inner
));
7159 inner
= SUBREG_REG (inner
);
7161 else if (GET_CODE (inner
) == ASHIFT
7162 && CONST_INT_P (XEXP (inner
, 1))
7163 && pos_rtx
== 0 && pos
== 0
7164 && len
> UINTVAL (XEXP (inner
, 1)))
7166 /* We're extracting the least significant bits of an rtx
7167 (ashift X (const_int C)), where LEN > C. Extract the
7168 least significant (LEN - C) bits of X, giving an rtx
7169 whose mode is MODE, then shift it left C times. */
7170 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7171 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7172 unsignedp
, in_dest
, in_compare
);
7174 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7177 inner_mode
= GET_MODE (inner
);
7179 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7180 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7182 /* See if this can be done without an extraction. We never can if the
7183 width of the field is not the same as that of some integer mode. For
7184 registers, we can only avoid the extraction if the position is at the
7185 low-order bit and this is either not in the destination or we have the
7186 appropriate STRICT_LOW_PART operation available.
7188 For MEM, we can avoid an extract if the field starts on an appropriate
7189 boundary and we can change the mode of the memory reference. */
7191 if (tmode
!= BLKmode
7192 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7194 && (inner_mode
== tmode
7196 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7197 || reg_truncated_to_mode (tmode
, inner
))
7200 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7201 || (MEM_P (inner
) && pos_rtx
== 0
7203 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7204 : BITS_PER_UNIT
)) == 0
7205 /* We can't do this if we are widening INNER_MODE (it
7206 may not be aligned, for one thing). */
7207 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7208 && (inner_mode
== tmode
7209 || (! mode_dependent_address_p (XEXP (inner
, 0))
7210 && ! MEM_VOLATILE_P (inner
))))))
7212 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7213 field. If the original and current mode are the same, we need not
7214 adjust the offset. Otherwise, we do if bytes big endian.
7216 If INNER is not a MEM, get a piece consisting of just the field
7217 of interest (in this case POS % BITS_PER_WORD must be 0). */
7221 HOST_WIDE_INT offset
;
7223 /* POS counts from lsb, but make OFFSET count in memory order. */
7224 if (BYTES_BIG_ENDIAN
)
7225 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7227 offset
= pos
/ BITS_PER_UNIT
;
7229 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7231 else if (REG_P (inner
))
7233 if (tmode
!= inner_mode
)
7235 /* We can't call gen_lowpart in a DEST since we
7236 always want a SUBREG (see below) and it would sometimes
7237 return a new hard register. */
7240 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7242 if (WORDS_BIG_ENDIAN
7243 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7244 final_word
= ((GET_MODE_SIZE (inner_mode
)
7245 - GET_MODE_SIZE (tmode
))
7246 / UNITS_PER_WORD
) - final_word
;
7248 final_word
*= UNITS_PER_WORD
;
7249 if (BYTES_BIG_ENDIAN
&&
7250 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7251 final_word
+= (GET_MODE_SIZE (inner_mode
)
7252 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7254 /* Avoid creating invalid subregs, for example when
7255 simplifying (x>>32)&255. */
7256 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7259 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7262 new_rtx
= gen_lowpart (tmode
, inner
);
7268 new_rtx
= force_to_mode (inner
, tmode
,
7269 len
>= HOST_BITS_PER_WIDE_INT
7270 ? ~(unsigned HOST_WIDE_INT
) 0
7271 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7274 /* If this extraction is going into the destination of a SET,
7275 make a STRICT_LOW_PART unless we made a MEM. */
7278 return (MEM_P (new_rtx
) ? new_rtx
7279 : (GET_CODE (new_rtx
) != SUBREG
7280 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7281 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7286 if (CONST_INT_P (new_rtx
)
7287 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7288 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7289 mode
, new_rtx
, tmode
);
7291 /* If we know that no extraneous bits are set, and that the high
7292 bit is not set, convert the extraction to the cheaper of
7293 sign and zero extension, that are equivalent in these cases. */
7294 if (flag_expensive_optimizations
7295 && (HWI_COMPUTABLE_MODE_P (tmode
)
7296 && ((nonzero_bits (new_rtx
, tmode
)
7297 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7300 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7301 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7303 /* Prefer ZERO_EXTENSION, since it gives more information to
7305 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7306 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7311 /* Otherwise, sign- or zero-extend unless we already are in the
7314 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7318 /* Unless this is a COMPARE or we have a funny memory reference,
7319 don't do anything with zero-extending field extracts starting at
7320 the low-order bit since they are simple AND operations. */
7321 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7322 && ! in_compare
&& unsignedp
)
7325 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7326 if the position is not a constant and the length is not 1. In all
7327 other cases, we would only be going outside our object in cases when
7328 an original shift would have been undefined. */
7330 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7331 || (pos_rtx
!= 0 && len
!= 1)))
7334 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7335 and the mode for the result. */
7336 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7338 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7339 pos_mode
= mode_for_extraction (EP_insv
, 2);
7340 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7343 if (! in_dest
&& unsignedp
7344 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7346 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7347 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7348 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7351 if (! in_dest
&& ! unsignedp
7352 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7354 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7355 pos_mode
= mode_for_extraction (EP_extv
, 3);
7356 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7359 /* Never narrow an object, since that might not be safe. */
7361 if (mode
!= VOIDmode
7362 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7363 extraction_mode
= mode
;
7365 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7366 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7367 pos_mode
= GET_MODE (pos_rtx
);
7369 /* If this is not from memory, the desired mode is the preferred mode
7370 for an extraction pattern's first input operand, or word_mode if there
7373 wanted_inner_mode
= wanted_inner_reg_mode
;
7376 /* Be careful not to go beyond the extracted object and maintain the
7377 natural alignment of the memory. */
7378 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7379 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7380 > GET_MODE_BITSIZE (wanted_inner_mode
))
7382 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7383 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7386 /* If we have to change the mode of memory and cannot, the desired mode
7387 is EXTRACTION_MODE. */
7388 if (inner_mode
!= wanted_inner_mode
7389 && (mode_dependent_address_p (XEXP (inner
, 0))
7390 || MEM_VOLATILE_P (inner
)
7392 wanted_inner_mode
= extraction_mode
;
7397 if (BITS_BIG_ENDIAN
)
7399 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7400 BITS_BIG_ENDIAN style. If position is constant, compute new
7401 position. Otherwise, build subtraction.
7402 Note that POS is relative to the mode of the original argument.
7403 If it's a MEM we need to recompute POS relative to that.
7404 However, if we're extracting from (or inserting into) a register,
7405 we want to recompute POS relative to wanted_inner_mode. */
7406 int width
= (MEM_P (inner
)
7407 ? GET_MODE_BITSIZE (is_mode
)
7408 : GET_MODE_BITSIZE (wanted_inner_mode
));
7411 pos
= width
- len
- pos
;
7414 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7415 /* POS may be less than 0 now, but we check for that below.
7416 Note that it can only be less than 0 if !MEM_P (inner). */
7419 /* If INNER has a wider mode, and this is a constant extraction, try to
7420 make it smaller and adjust the byte to point to the byte containing
7422 if (wanted_inner_mode
!= VOIDmode
7423 && inner_mode
!= wanted_inner_mode
7425 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7427 && ! mode_dependent_address_p (XEXP (inner
, 0))
7428 && ! MEM_VOLATILE_P (inner
))
7432 /* The computations below will be correct if the machine is big
7433 endian in both bits and bytes or little endian in bits and bytes.
7434 If it is mixed, we must adjust. */
7436 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7437 adjust OFFSET to compensate. */
7438 if (BYTES_BIG_ENDIAN
7439 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7440 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7442 /* We can now move to the desired byte. */
7443 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7444 * GET_MODE_SIZE (wanted_inner_mode
);
7445 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7447 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7448 && is_mode
!= wanted_inner_mode
)
7449 offset
= (GET_MODE_SIZE (is_mode
)
7450 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7452 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7455 /* If INNER is not memory, get it into the proper mode. If we are changing
7456 its mode, POS must be a constant and smaller than the size of the new
7458 else if (!MEM_P (inner
))
7460 /* On the LHS, don't create paradoxical subregs implicitely truncating
7461 the register unless TRULY_NOOP_TRUNCATION. */
7463 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7467 if (GET_MODE (inner
) != wanted_inner_mode
7469 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7475 inner
= force_to_mode (inner
, wanted_inner_mode
,
7477 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7478 ? ~(unsigned HOST_WIDE_INT
) 0
7479 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7484 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7485 have to zero extend. Otherwise, we can just use a SUBREG. */
7487 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7489 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7491 /* If we know that no extraneous bits are set, and that the high
7492 bit is not set, convert extraction to cheaper one - either
7493 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7495 if (flag_expensive_optimizations
7496 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7497 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7498 & ~(((unsigned HOST_WIDE_INT
)
7499 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7503 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7505 /* Prefer ZERO_EXTENSION, since it gives more information to
7507 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7508 < set_src_cost (temp
, optimize_this_for_speed_p
))
7513 else if (pos_rtx
!= 0
7514 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7515 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7517 /* Make POS_RTX unless we already have it and it is correct. If we don't
7518 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7520 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7521 pos_rtx
= orig_pos_rtx
;
7523 else if (pos_rtx
== 0)
7524 pos_rtx
= GEN_INT (pos
);
7526 /* Make the required operation. See if we can use existing rtx. */
7527 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7528 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7530 new_rtx
= gen_lowpart (mode
, new_rtx
);
7535 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7536 with any other operations in X. Return X without that shift if so. */
7539 extract_left_shift (rtx x
, int count
)
7541 enum rtx_code code
= GET_CODE (x
);
7542 enum machine_mode mode
= GET_MODE (x
);
7548 /* This is the shift itself. If it is wide enough, we will return
7549 either the value being shifted if the shift count is equal to
7550 COUNT or a shift for the difference. */
7551 if (CONST_INT_P (XEXP (x
, 1))
7552 && INTVAL (XEXP (x
, 1)) >= count
)
7553 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7554 INTVAL (XEXP (x
, 1)) - count
);
7558 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7559 return simplify_gen_unary (code
, mode
, tem
, mode
);
7563 case PLUS
: case IOR
: case XOR
: case AND
:
7564 /* If we can safely shift this constant and we find the inner shift,
7565 make a new operation. */
7566 if (CONST_INT_P (XEXP (x
, 1))
7567 && (UINTVAL (XEXP (x
, 1))
7568 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7569 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7570 return simplify_gen_binary (code
, mode
, tem
,
7571 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7582 /* Look at the expression rooted at X. Look for expressions
7583 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7584 Form these expressions.
7586 Return the new rtx, usually just X.
7588 Also, for machines like the VAX that don't have logical shift insns,
7589 try to convert logical to arithmetic shift operations in cases where
7590 they are equivalent. This undoes the canonicalizations to logical
7591 shifts done elsewhere.
7593 We try, as much as possible, to re-use rtl expressions to save memory.
7595 IN_CODE says what kind of expression we are processing. Normally, it is
7596 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7597 being kludges), it is MEM. When processing the arguments of a comparison
7598 or a COMPARE against zero, it is COMPARE. */
7601 make_compound_operation (rtx x
, enum rtx_code in_code
)
7603 enum rtx_code code
= GET_CODE (x
);
7604 enum machine_mode mode
= GET_MODE (x
);
7605 int mode_width
= GET_MODE_PRECISION (mode
);
7607 enum rtx_code next_code
;
7613 /* Select the code to be used in recursive calls. Once we are inside an
7614 address, we stay there. If we have a comparison, set to COMPARE,
7615 but once inside, go back to our default of SET. */
7617 next_code
= (code
== MEM
? MEM
7618 : ((code
== PLUS
|| code
== MINUS
)
7619 && SCALAR_INT_MODE_P (mode
)) ? MEM
7620 : ((code
== COMPARE
|| COMPARISON_P (x
))
7621 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7622 : in_code
== COMPARE
? SET
: in_code
);
7624 /* Process depending on the code of this operation. If NEW is set
7625 nonzero, it will be returned. */
7630 /* Convert shifts by constants into multiplications if inside
7632 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7633 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7634 && INTVAL (XEXP (x
, 1)) >= 0
7635 && SCALAR_INT_MODE_P (mode
))
7637 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7638 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7640 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7641 if (GET_CODE (new_rtx
) == NEG
)
7643 new_rtx
= XEXP (new_rtx
, 0);
7646 multval
= trunc_int_for_mode (multval
, mode
);
7647 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7654 lhs
= make_compound_operation (lhs
, next_code
);
7655 rhs
= make_compound_operation (rhs
, next_code
);
7656 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7657 && SCALAR_INT_MODE_P (mode
))
7659 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7661 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7663 else if (GET_CODE (lhs
) == MULT
7664 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7666 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7667 simplify_gen_unary (NEG
, mode
,
7670 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7674 SUBST (XEXP (x
, 0), lhs
);
7675 SUBST (XEXP (x
, 1), rhs
);
7678 x
= gen_lowpart (mode
, new_rtx
);
7684 lhs
= make_compound_operation (lhs
, next_code
);
7685 rhs
= make_compound_operation (rhs
, next_code
);
7686 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7687 && SCALAR_INT_MODE_P (mode
))
7689 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7691 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7693 else if (GET_CODE (rhs
) == MULT
7694 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7696 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7697 simplify_gen_unary (NEG
, mode
,
7700 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7704 SUBST (XEXP (x
, 0), lhs
);
7705 SUBST (XEXP (x
, 1), rhs
);
7708 return gen_lowpart (mode
, new_rtx
);
7711 /* If the second operand is not a constant, we can't do anything
7713 if (!CONST_INT_P (XEXP (x
, 1)))
7716 /* If the constant is a power of two minus one and the first operand
7717 is a logical right shift, make an extraction. */
7718 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7719 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7721 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7722 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7723 0, in_code
== COMPARE
);
7726 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7727 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7728 && subreg_lowpart_p (XEXP (x
, 0))
7729 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7730 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7732 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7734 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7735 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7736 0, in_code
== COMPARE
);
7738 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7739 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7740 || GET_CODE (XEXP (x
, 0)) == IOR
)
7741 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7742 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7743 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7745 /* Apply the distributive law, and then try to make extractions. */
7746 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7747 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7749 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7751 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7754 /* If we are have (and (rotate X C) M) and C is larger than the number
7755 of bits in M, this is an extraction. */
7757 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7758 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7759 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7760 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7762 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7763 new_rtx
= make_extraction (mode
, new_rtx
,
7764 (GET_MODE_PRECISION (mode
)
7765 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7766 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7769 /* On machines without logical shifts, if the operand of the AND is
7770 a logical shift and our mask turns off all the propagated sign
7771 bits, we can replace the logical shift with an arithmetic shift. */
7772 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7773 && !have_insn_for (LSHIFTRT
, mode
)
7774 && have_insn_for (ASHIFTRT
, mode
)
7775 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7776 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7777 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7778 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7780 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7782 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7783 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7785 gen_rtx_ASHIFTRT (mode
,
7786 make_compound_operation
7787 (XEXP (XEXP (x
, 0), 0), next_code
),
7788 XEXP (XEXP (x
, 0), 1)));
7791 /* If the constant is one less than a power of two, this might be
7792 representable by an extraction even if no shift is present.
7793 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7794 we are in a COMPARE. */
7795 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7796 new_rtx
= make_extraction (mode
,
7797 make_compound_operation (XEXP (x
, 0),
7799 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7801 /* If we are in a comparison and this is an AND with a power of two,
7802 convert this into the appropriate bit extract. */
7803 else if (in_code
== COMPARE
7804 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7805 new_rtx
= make_extraction (mode
,
7806 make_compound_operation (XEXP (x
, 0),
7808 i
, NULL_RTX
, 1, 1, 0, 1);
7813 /* If the sign bit is known to be zero, replace this with an
7814 arithmetic shift. */
7815 if (have_insn_for (ASHIFTRT
, mode
)
7816 && ! have_insn_for (LSHIFTRT
, mode
)
7817 && mode_width
<= HOST_BITS_PER_WIDE_INT
7818 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7820 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7821 make_compound_operation (XEXP (x
, 0),
7827 /* ... fall through ... */
7833 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7834 this is a SIGN_EXTRACT. */
7835 if (CONST_INT_P (rhs
)
7836 && GET_CODE (lhs
) == ASHIFT
7837 && CONST_INT_P (XEXP (lhs
, 1))
7838 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7839 && INTVAL (XEXP (lhs
, 1)) >= 0
7840 && INTVAL (rhs
) < mode_width
)
7842 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7843 new_rtx
= make_extraction (mode
, new_rtx
,
7844 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7845 NULL_RTX
, mode_width
- INTVAL (rhs
),
7846 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7850 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7851 If so, try to merge the shifts into a SIGN_EXTEND. We could
7852 also do this for some cases of SIGN_EXTRACT, but it doesn't
7853 seem worth the effort; the case checked for occurs on Alpha. */
7856 && ! (GET_CODE (lhs
) == SUBREG
7857 && (OBJECT_P (SUBREG_REG (lhs
))))
7858 && CONST_INT_P (rhs
)
7859 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7860 && INTVAL (rhs
) < mode_width
7861 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7862 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7863 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7864 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7869 /* Call ourselves recursively on the inner expression. If we are
7870 narrowing the object and it has a different RTL code from
7871 what it originally did, do this SUBREG as a force_to_mode. */
7873 rtx inner
= SUBREG_REG (x
), simplified
;
7875 tem
= make_compound_operation (inner
, in_code
);
7878 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7882 if (GET_CODE (tem
) != GET_CODE (inner
)
7883 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7884 && subreg_lowpart_p (x
))
7887 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7889 /* If we have something other than a SUBREG, we might have
7890 done an expansion, so rerun ourselves. */
7891 if (GET_CODE (newer
) != SUBREG
)
7892 newer
= make_compound_operation (newer
, in_code
);
7894 /* force_to_mode can expand compounds. If it just re-expanded the
7895 compound, use gen_lowpart to convert to the desired mode. */
7896 if (rtx_equal_p (newer
, x
)
7897 /* Likewise if it re-expanded the compound only partially.
7898 This happens for SUBREG of ZERO_EXTRACT if they extract
7899 the same number of bits. */
7900 || (GET_CODE (newer
) == SUBREG
7901 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7902 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7903 && GET_CODE (inner
) == AND
7904 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7905 return gen_lowpart (GET_MODE (x
), tem
);
7921 x
= gen_lowpart (mode
, new_rtx
);
7922 code
= GET_CODE (x
);
7925 /* Now recursively process each operand of this operation. We need to
7926 handle ZERO_EXTEND specially so that we don't lose track of the
7928 if (GET_CODE (x
) == ZERO_EXTEND
)
7930 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7931 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7932 new_rtx
, GET_MODE (XEXP (x
, 0)));
7935 SUBST (XEXP (x
, 0), new_rtx
);
7939 fmt
= GET_RTX_FORMAT (code
);
7940 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7943 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7944 SUBST (XEXP (x
, i
), new_rtx
);
7946 else if (fmt
[i
] == 'E')
7947 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7949 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7950 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7954 /* If this is a commutative operation, the changes to the operands
7955 may have made it noncanonical. */
7956 if (COMMUTATIVE_ARITH_P (x
)
7957 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7960 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7961 SUBST (XEXP (x
, 1), tem
);
7967 /* Given M see if it is a value that would select a field of bits
7968 within an item, but not the entire word. Return -1 if not.
7969 Otherwise, return the starting position of the field, where 0 is the
7972 *PLEN is set to the length of the field. */
7975 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7977 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7978 int pos
= m
? ctz_hwi (m
) : -1;
7982 /* Now shift off the low-order zero bits and see if we have a
7983 power of two minus 1. */
7984 len
= exact_log2 ((m
>> pos
) + 1);
7993 /* If X refers to a register that equals REG in value, replace these
7994 references with REG. */
7996 canon_reg_for_combine (rtx x
, rtx reg
)
8003 enum rtx_code code
= GET_CODE (x
);
8004 switch (GET_RTX_CLASS (code
))
8007 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8008 if (op0
!= XEXP (x
, 0))
8009 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8014 case RTX_COMM_ARITH
:
8015 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8016 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8017 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8018 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8022 case RTX_COMM_COMPARE
:
8023 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8024 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8025 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8026 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8027 GET_MODE (op0
), op0
, op1
);
8031 case RTX_BITFIELD_OPS
:
8032 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8033 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8034 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8035 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8036 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8037 GET_MODE (op0
), op0
, op1
, op2
);
8042 if (rtx_equal_p (get_last_value (reg
), x
)
8043 || rtx_equal_p (reg
, get_last_value (x
)))
8052 fmt
= GET_RTX_FORMAT (code
);
8054 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8057 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8058 if (op
!= XEXP (x
, i
))
8068 else if (fmt
[i
] == 'E')
8071 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8073 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8074 if (op
!= XVECEXP (x
, i
, j
))
8081 XVECEXP (x
, i
, j
) = op
;
8092 /* Return X converted to MODE. If the value is already truncated to
8093 MODE we can just return a subreg even though in the general case we
8094 would need an explicit truncation. */
8097 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
8099 if (!CONST_INT_P (x
)
8100 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8101 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8102 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8104 /* Bit-cast X into an integer mode. */
8105 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8106 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8107 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8111 return gen_lowpart (mode
, x
);
8114 /* See if X can be simplified knowing that we will only refer to it in
8115 MODE and will only refer to those bits that are nonzero in MASK.
8116 If other bits are being computed or if masking operations are done
8117 that select a superset of the bits in MASK, they can sometimes be
8120 Return a possibly simplified expression, but always convert X to
8121 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8123 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8124 are all off in X. This is used when X will be complemented, by either
8125 NOT, NEG, or XOR. */
8128 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8131 enum rtx_code code
= GET_CODE (x
);
8132 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8133 enum machine_mode op_mode
;
8134 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8137 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8138 code below will do the wrong thing since the mode of such an
8139 expression is VOIDmode.
8141 Also do nothing if X is a CLOBBER; this can happen if X was
8142 the return value from a call to gen_lowpart. */
8143 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8146 /* We want to perform the operation is its present mode unless we know
8147 that the operation is valid in MODE, in which case we do the operation
8149 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8150 && have_insn_for (code
, mode
))
8151 ? mode
: GET_MODE (x
));
8153 /* It is not valid to do a right-shift in a narrower mode
8154 than the one it came in with. */
8155 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8156 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8157 op_mode
= GET_MODE (x
);
8159 /* Truncate MASK to fit OP_MODE. */
8161 mask
&= GET_MODE_MASK (op_mode
);
8163 /* When we have an arithmetic operation, or a shift whose count we
8164 do not know, we need to assume that all bits up to the highest-order
8165 bit in MASK will be needed. This is how we form such a mask. */
8166 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8167 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8169 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8172 /* Determine what bits of X are guaranteed to be (non)zero. */
8173 nonzero
= nonzero_bits (x
, mode
);
8175 /* If none of the bits in X are needed, return a zero. */
8176 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8179 /* If X is a CONST_INT, return a new one. Do this here since the
8180 test below will fail. */
8181 if (CONST_INT_P (x
))
8183 if (SCALAR_INT_MODE_P (mode
))
8184 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8187 x
= GEN_INT (INTVAL (x
) & mask
);
8188 return gen_lowpart_common (mode
, x
);
8192 /* If X is narrower than MODE and we want all the bits in X's mode, just
8193 get X in the proper mode. */
8194 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8195 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8196 return gen_lowpart (mode
, x
);
8198 /* We can ignore the effect of a SUBREG if it narrows the mode or
8199 if the constant masks to zero all the bits the mode doesn't have. */
8200 if (GET_CODE (x
) == SUBREG
8201 && subreg_lowpart_p (x
)
8202 && ((GET_MODE_SIZE (GET_MODE (x
))
8203 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8205 & GET_MODE_MASK (GET_MODE (x
))
8206 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8207 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8209 /* The arithmetic simplifications here only work for scalar integer modes. */
8210 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8211 return gen_lowpart_or_truncate (mode
, x
);
8216 /* If X is a (clobber (const_int)), return it since we know we are
8217 generating something that won't match. */
8224 x
= expand_compound_operation (x
);
8225 if (GET_CODE (x
) != code
)
8226 return force_to_mode (x
, mode
, mask
, next_select
);
8230 /* Similarly for a truncate. */
8231 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8234 /* If this is an AND with a constant, convert it into an AND
8235 whose constant is the AND of that constant with MASK. If it
8236 remains an AND of MASK, delete it since it is redundant. */
8238 if (CONST_INT_P (XEXP (x
, 1)))
8240 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8241 mask
& INTVAL (XEXP (x
, 1)));
8243 /* If X is still an AND, see if it is an AND with a mask that
8244 is just some low-order bits. If so, and it is MASK, we don't
8247 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8248 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8252 /* If it remains an AND, try making another AND with the bits
8253 in the mode mask that aren't in MASK turned on. If the
8254 constant in the AND is wide enough, this might make a
8255 cheaper constant. */
8257 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8258 && GET_MODE_MASK (GET_MODE (x
)) != mask
8259 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8261 unsigned HOST_WIDE_INT cval
8262 = UINTVAL (XEXP (x
, 1))
8263 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8264 int width
= GET_MODE_PRECISION (GET_MODE (x
));
8267 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8268 number, sign extend it. */
8269 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8270 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8271 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8273 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8274 XEXP (x
, 0), GEN_INT (cval
));
8275 if (set_src_cost (y
, optimize_this_for_speed_p
)
8276 < set_src_cost (x
, optimize_this_for_speed_p
))
8286 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8287 low-order bits (as in an alignment operation) and FOO is already
8288 aligned to that boundary, mask C1 to that boundary as well.
8289 This may eliminate that PLUS and, later, the AND. */
8292 unsigned int width
= GET_MODE_PRECISION (mode
);
8293 unsigned HOST_WIDE_INT smask
= mask
;
8295 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8296 number, sign extend it. */
8298 if (width
< HOST_BITS_PER_WIDE_INT
8299 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8300 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8302 if (CONST_INT_P (XEXP (x
, 1))
8303 && exact_log2 (- smask
) >= 0
8304 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8305 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8306 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8307 (INTVAL (XEXP (x
, 1)) & smask
)),
8308 mode
, smask
, next_select
);
8311 /* ... fall through ... */
8314 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8315 most significant bit in MASK since carries from those bits will
8316 affect the bits we are interested in. */
8321 /* If X is (minus C Y) where C's least set bit is larger than any bit
8322 in the mask, then we may replace with (neg Y). */
8323 if (CONST_INT_P (XEXP (x
, 0))
8324 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8325 & -INTVAL (XEXP (x
, 0))))
8328 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8330 return force_to_mode (x
, mode
, mask
, next_select
);
8333 /* Similarly, if C contains every bit in the fuller_mask, then we may
8334 replace with (not Y). */
8335 if (CONST_INT_P (XEXP (x
, 0))
8336 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8338 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8339 XEXP (x
, 1), GET_MODE (x
));
8340 return force_to_mode (x
, mode
, mask
, next_select
);
8348 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8349 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8350 operation which may be a bitfield extraction. Ensure that the
8351 constant we form is not wider than the mode of X. */
8353 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8354 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8355 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8356 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8357 && CONST_INT_P (XEXP (x
, 1))
8358 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8359 + floor_log2 (INTVAL (XEXP (x
, 1))))
8360 < GET_MODE_PRECISION (GET_MODE (x
)))
8361 && (UINTVAL (XEXP (x
, 1))
8362 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8364 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8365 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8366 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8367 XEXP (XEXP (x
, 0), 0), temp
);
8368 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8369 XEXP (XEXP (x
, 0), 1));
8370 return force_to_mode (x
, mode
, mask
, next_select
);
8374 /* For most binary operations, just propagate into the operation and
8375 change the mode if we have an operation of that mode. */
8377 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8378 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8380 /* If we ended up truncating both operands, truncate the result of the
8381 operation instead. */
8382 if (GET_CODE (op0
) == TRUNCATE
8383 && GET_CODE (op1
) == TRUNCATE
)
8385 op0
= XEXP (op0
, 0);
8386 op1
= XEXP (op1
, 0);
8389 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8390 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8392 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8393 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8397 /* For left shifts, do the same, but just for the first operand.
8398 However, we cannot do anything with shifts where we cannot
8399 guarantee that the counts are smaller than the size of the mode
8400 because such a count will have a different meaning in a
8403 if (! (CONST_INT_P (XEXP (x
, 1))
8404 && INTVAL (XEXP (x
, 1)) >= 0
8405 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8406 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8407 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8408 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8411 /* If the shift count is a constant and we can do arithmetic in
8412 the mode of the shift, refine which bits we need. Otherwise, use the
8413 conservative form of the mask. */
8414 if (CONST_INT_P (XEXP (x
, 1))
8415 && INTVAL (XEXP (x
, 1)) >= 0
8416 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8417 && HWI_COMPUTABLE_MODE_P (op_mode
))
8418 mask
>>= INTVAL (XEXP (x
, 1));
8422 op0
= gen_lowpart_or_truncate (op_mode
,
8423 force_to_mode (XEXP (x
, 0), op_mode
,
8424 mask
, next_select
));
8426 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8427 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8431 /* Here we can only do something if the shift count is a constant,
8432 this shift constant is valid for the host, and we can do arithmetic
8435 if (CONST_INT_P (XEXP (x
, 1))
8436 && INTVAL (XEXP (x
, 1)) >= 0
8437 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8438 && HWI_COMPUTABLE_MODE_P (op_mode
))
8440 rtx inner
= XEXP (x
, 0);
8441 unsigned HOST_WIDE_INT inner_mask
;
8443 /* Select the mask of the bits we need for the shift operand. */
8444 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8446 /* We can only change the mode of the shift if we can do arithmetic
8447 in the mode of the shift and INNER_MASK is no wider than the
8448 width of X's mode. */
8449 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8450 op_mode
= GET_MODE (x
);
8452 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8454 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8455 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8458 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8459 shift and AND produces only copies of the sign bit (C2 is one less
8460 than a power of two), we can do this with just a shift. */
8462 if (GET_CODE (x
) == LSHIFTRT
8463 && CONST_INT_P (XEXP (x
, 1))
8464 /* The shift puts one of the sign bit copies in the least significant
8466 && ((INTVAL (XEXP (x
, 1))
8467 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8468 >= GET_MODE_PRECISION (GET_MODE (x
)))
8469 && exact_log2 (mask
+ 1) >= 0
8470 /* Number of bits left after the shift must be more than the mask
8472 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8473 <= GET_MODE_PRECISION (GET_MODE (x
)))
8474 /* Must be more sign bit copies than the mask needs. */
8475 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8476 >= exact_log2 (mask
+ 1)))
8477 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8478 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8479 - exact_log2 (mask
+ 1)));
8484 /* If we are just looking for the sign bit, we don't need this shift at
8485 all, even if it has a variable count. */
8486 if (val_signbit_p (GET_MODE (x
), mask
))
8487 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8489 /* If this is a shift by a constant, get a mask that contains those bits
8490 that are not copies of the sign bit. We then have two cases: If
8491 MASK only includes those bits, this can be a logical shift, which may
8492 allow simplifications. If MASK is a single-bit field not within
8493 those bits, we are requesting a copy of the sign bit and hence can
8494 shift the sign bit to the appropriate location. */
8496 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8497 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8501 /* If the considered data is wider than HOST_WIDE_INT, we can't
8502 represent a mask for all its bits in a single scalar.
8503 But we only care about the lower bits, so calculate these. */
8505 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8507 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8509 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8510 is the number of bits a full-width mask would have set.
8511 We need only shift if these are fewer than nonzero can
8512 hold. If not, we must keep all bits set in nonzero. */
8514 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8515 < HOST_BITS_PER_WIDE_INT
)
8516 nonzero
>>= INTVAL (XEXP (x
, 1))
8517 + HOST_BITS_PER_WIDE_INT
8518 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8522 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8523 nonzero
>>= INTVAL (XEXP (x
, 1));
8526 if ((mask
& ~nonzero
) == 0)
8528 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8529 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8530 if (GET_CODE (x
) != ASHIFTRT
)
8531 return force_to_mode (x
, mode
, mask
, next_select
);
8534 else if ((i
= exact_log2 (mask
)) >= 0)
8536 x
= simplify_shift_const
8537 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8538 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8540 if (GET_CODE (x
) != ASHIFTRT
)
8541 return force_to_mode (x
, mode
, mask
, next_select
);
8545 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8546 even if the shift count isn't a constant. */
8548 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8549 XEXP (x
, 0), XEXP (x
, 1));
8553 /* If this is a zero- or sign-extension operation that just affects bits
8554 we don't care about, remove it. Be sure the call above returned
8555 something that is still a shift. */
8557 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8558 && CONST_INT_P (XEXP (x
, 1))
8559 && INTVAL (XEXP (x
, 1)) >= 0
8560 && (INTVAL (XEXP (x
, 1))
8561 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8562 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8563 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8564 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8571 /* If the shift count is constant and we can do computations
8572 in the mode of X, compute where the bits we care about are.
8573 Otherwise, we can't do anything. Don't change the mode of
8574 the shift or propagate MODE into the shift, though. */
8575 if (CONST_INT_P (XEXP (x
, 1))
8576 && INTVAL (XEXP (x
, 1)) >= 0)
8578 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8579 GET_MODE (x
), GEN_INT (mask
),
8581 if (temp
&& CONST_INT_P (temp
))
8583 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8584 INTVAL (temp
), next_select
));
8589 /* If we just want the low-order bit, the NEG isn't needed since it
8590 won't change the low-order bit. */
8592 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8594 /* We need any bits less significant than the most significant bit in
8595 MASK since carries from those bits will affect the bits we are
8601 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8602 same as the XOR case above. Ensure that the constant we form is not
8603 wider than the mode of X. */
8605 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8606 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8607 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8608 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8609 < GET_MODE_PRECISION (GET_MODE (x
)))
8610 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8612 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8614 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8615 XEXP (XEXP (x
, 0), 0), temp
);
8616 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8617 temp
, XEXP (XEXP (x
, 0), 1));
8619 return force_to_mode (x
, mode
, mask
, next_select
);
8622 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8623 use the full mask inside the NOT. */
8627 op0
= gen_lowpart_or_truncate (op_mode
,
8628 force_to_mode (XEXP (x
, 0), mode
, mask
,
8630 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8631 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8635 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8636 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8637 which is equal to STORE_FLAG_VALUE. */
8638 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8639 && XEXP (x
, 1) == const0_rtx
8640 && GET_MODE (XEXP (x
, 0)) == mode
8641 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8642 && (nonzero_bits (XEXP (x
, 0), mode
)
8643 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8644 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8649 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8650 written in a narrower mode. We play it safe and do not do so. */
8653 gen_lowpart_or_truncate (GET_MODE (x
),
8654 force_to_mode (XEXP (x
, 1), mode
,
8655 mask
, next_select
)));
8657 gen_lowpart_or_truncate (GET_MODE (x
),
8658 force_to_mode (XEXP (x
, 2), mode
,
8659 mask
, next_select
)));
8666 /* Ensure we return a value of the proper mode. */
8667 return gen_lowpart_or_truncate (mode
, x
);
8670 /* Return nonzero if X is an expression that has one of two values depending on
8671 whether some other value is zero or nonzero. In that case, we return the
8672 value that is being tested, *PTRUE is set to the value if the rtx being
8673 returned has a nonzero value, and *PFALSE is set to the other alternative.
8675 If we return zero, we set *PTRUE and *PFALSE to X. */
8678 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8680 enum machine_mode mode
= GET_MODE (x
);
8681 enum rtx_code code
= GET_CODE (x
);
8682 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8683 unsigned HOST_WIDE_INT nz
;
8685 /* If we are comparing a value against zero, we are done. */
8686 if ((code
== NE
|| code
== EQ
)
8687 && XEXP (x
, 1) == const0_rtx
)
8689 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8690 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8694 /* If this is a unary operation whose operand has one of two values, apply
8695 our opcode to compute those values. */
8696 else if (UNARY_P (x
)
8697 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8699 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8700 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8701 GET_MODE (XEXP (x
, 0)));
8705 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8706 make can't possibly match and would suppress other optimizations. */
8707 else if (code
== COMPARE
)
8710 /* If this is a binary operation, see if either side has only one of two
8711 values. If either one does or if both do and they are conditional on
8712 the same value, compute the new true and false values. */
8713 else if (BINARY_P (x
))
8715 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8716 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8718 if ((cond0
!= 0 || cond1
!= 0)
8719 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8721 /* If if_then_else_cond returned zero, then true/false are the
8722 same rtl. We must copy one of them to prevent invalid rtl
8725 true0
= copy_rtx (true0
);
8726 else if (cond1
== 0)
8727 true1
= copy_rtx (true1
);
8729 if (COMPARISON_P (x
))
8731 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8733 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8738 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8739 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8742 return cond0
? cond0
: cond1
;
8745 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8746 operands is zero when the other is nonzero, and vice-versa,
8747 and STORE_FLAG_VALUE is 1 or -1. */
8749 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8750 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8752 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8754 rtx op0
= XEXP (XEXP (x
, 0), 1);
8755 rtx op1
= XEXP (XEXP (x
, 1), 1);
8757 cond0
= XEXP (XEXP (x
, 0), 0);
8758 cond1
= XEXP (XEXP (x
, 1), 0);
8760 if (COMPARISON_P (cond0
)
8761 && COMPARISON_P (cond1
)
8762 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8763 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8764 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8765 || ((swap_condition (GET_CODE (cond0
))
8766 == reversed_comparison_code (cond1
, NULL
))
8767 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8768 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8769 && ! side_effects_p (x
))
8771 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8772 *pfalse
= simplify_gen_binary (MULT
, mode
,
8774 ? simplify_gen_unary (NEG
, mode
,
8782 /* Similarly for MULT, AND and UMIN, except that for these the result
8784 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8785 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8786 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8788 cond0
= XEXP (XEXP (x
, 0), 0);
8789 cond1
= XEXP (XEXP (x
, 1), 0);
8791 if (COMPARISON_P (cond0
)
8792 && COMPARISON_P (cond1
)
8793 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8794 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8795 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8796 || ((swap_condition (GET_CODE (cond0
))
8797 == reversed_comparison_code (cond1
, NULL
))
8798 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8799 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8800 && ! side_effects_p (x
))
8802 *ptrue
= *pfalse
= const0_rtx
;
8808 else if (code
== IF_THEN_ELSE
)
8810 /* If we have IF_THEN_ELSE already, extract the condition and
8811 canonicalize it if it is NE or EQ. */
8812 cond0
= XEXP (x
, 0);
8813 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8814 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8815 return XEXP (cond0
, 0);
8816 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8818 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8819 return XEXP (cond0
, 0);
8825 /* If X is a SUBREG, we can narrow both the true and false values
8826 if the inner expression, if there is a condition. */
8827 else if (code
== SUBREG
8828 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8831 true0
= simplify_gen_subreg (mode
, true0
,
8832 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8833 false0
= simplify_gen_subreg (mode
, false0
,
8834 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8835 if (true0
&& false0
)
8843 /* If X is a constant, this isn't special and will cause confusions
8844 if we treat it as such. Likewise if it is equivalent to a constant. */
8845 else if (CONSTANT_P (x
)
8846 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8849 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8850 will be least confusing to the rest of the compiler. */
8851 else if (mode
== BImode
)
8853 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8857 /* If X is known to be either 0 or -1, those are the true and
8858 false values when testing X. */
8859 else if (x
== constm1_rtx
|| x
== const0_rtx
8860 || (mode
!= VOIDmode
8861 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8863 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8867 /* Likewise for 0 or a single bit. */
8868 else if (HWI_COMPUTABLE_MODE_P (mode
)
8869 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8871 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8875 /* Otherwise fail; show no condition with true and false values the same. */
8876 *ptrue
= *pfalse
= x
;
8880 /* Return the value of expression X given the fact that condition COND
8881 is known to be true when applied to REG as its first operand and VAL
8882 as its second. X is known to not be shared and so can be modified in
8885 We only handle the simplest cases, and specifically those cases that
8886 arise with IF_THEN_ELSE expressions. */
8889 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8891 enum rtx_code code
= GET_CODE (x
);
8896 if (side_effects_p (x
))
8899 /* If either operand of the condition is a floating point value,
8900 then we have to avoid collapsing an EQ comparison. */
8902 && rtx_equal_p (x
, reg
)
8903 && ! FLOAT_MODE_P (GET_MODE (x
))
8904 && ! FLOAT_MODE_P (GET_MODE (val
)))
8907 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8910 /* If X is (abs REG) and we know something about REG's relationship
8911 with zero, we may be able to simplify this. */
8913 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8916 case GE
: case GT
: case EQ
:
8919 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8921 GET_MODE (XEXP (x
, 0)));
8926 /* The only other cases we handle are MIN, MAX, and comparisons if the
8927 operands are the same as REG and VAL. */
8929 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8931 if (rtx_equal_p (XEXP (x
, 0), val
))
8932 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8934 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8936 if (COMPARISON_P (x
))
8938 if (comparison_dominates_p (cond
, code
))
8939 return const_true_rtx
;
8941 code
= reversed_comparison_code (x
, NULL
);
8943 && comparison_dominates_p (cond
, code
))
8948 else if (code
== SMAX
|| code
== SMIN
8949 || code
== UMIN
|| code
== UMAX
)
8951 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8953 /* Do not reverse the condition when it is NE or EQ.
8954 This is because we cannot conclude anything about
8955 the value of 'SMAX (x, y)' when x is not equal to y,
8956 but we can when x equals y. */
8957 if ((code
== SMAX
|| code
== UMAX
)
8958 && ! (cond
== EQ
|| cond
== NE
))
8959 cond
= reverse_condition (cond
);
8964 return unsignedp
? x
: XEXP (x
, 1);
8966 return unsignedp
? x
: XEXP (x
, 0);
8968 return unsignedp
? XEXP (x
, 1) : x
;
8970 return unsignedp
? XEXP (x
, 0) : x
;
8977 else if (code
== SUBREG
)
8979 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8980 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8982 if (SUBREG_REG (x
) != r
)
8984 /* We must simplify subreg here, before we lose track of the
8985 original inner_mode. */
8986 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8987 inner_mode
, SUBREG_BYTE (x
));
8991 SUBST (SUBREG_REG (x
), r
);
8996 /* We don't have to handle SIGN_EXTEND here, because even in the
8997 case of replacing something with a modeless CONST_INT, a
8998 CONST_INT is already (supposed to be) a valid sign extension for
8999 its narrower mode, which implies it's already properly
9000 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9001 story is different. */
9002 else if (code
== ZERO_EXTEND
)
9004 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9005 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9007 if (XEXP (x
, 0) != r
)
9009 /* We must simplify the zero_extend here, before we lose
9010 track of the original inner_mode. */
9011 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9016 SUBST (XEXP (x
, 0), r
);
9022 fmt
= GET_RTX_FORMAT (code
);
9023 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9026 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9027 else if (fmt
[i
] == 'E')
9028 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9029 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9036 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9037 assignment as a field assignment. */
9040 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
9042 if (x
== y
|| rtx_equal_p (x
, y
))
9045 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9048 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9049 Note that all SUBREGs of MEM are paradoxical; otherwise they
9050 would have been rewritten. */
9051 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9052 && MEM_P (SUBREG_REG (y
))
9053 && rtx_equal_p (SUBREG_REG (y
),
9054 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9057 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9058 && MEM_P (SUBREG_REG (x
))
9059 && rtx_equal_p (SUBREG_REG (x
),
9060 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9063 /* We used to see if get_last_value of X and Y were the same but that's
9064 not correct. In one direction, we'll cause the assignment to have
9065 the wrong destination and in the case, we'll import a register into this
9066 insn that might have already have been dead. So fail if none of the
9067 above cases are true. */
9071 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9072 Return that assignment if so.
9074 We only handle the most common cases. */
9077 make_field_assignment (rtx x
)
9079 rtx dest
= SET_DEST (x
);
9080 rtx src
= SET_SRC (x
);
9085 unsigned HOST_WIDE_INT len
;
9087 enum machine_mode mode
;
9089 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9090 a clear of a one-bit field. We will have changed it to
9091 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9094 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9095 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9096 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9097 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9099 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9102 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9106 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9107 && subreg_lowpart_p (XEXP (src
, 0))
9108 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9109 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9110 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9111 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9112 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9113 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9115 assign
= make_extraction (VOIDmode
, dest
, 0,
9116 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9119 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9123 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9125 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9126 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9127 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9129 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9132 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9136 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9137 SRC is an AND with all bits of that field set, then we can discard
9139 if (GET_CODE (dest
) == ZERO_EXTRACT
9140 && CONST_INT_P (XEXP (dest
, 1))
9141 && GET_CODE (src
) == AND
9142 && CONST_INT_P (XEXP (src
, 1)))
9144 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9145 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9146 unsigned HOST_WIDE_INT ze_mask
;
9148 if (width
>= HOST_BITS_PER_WIDE_INT
)
9151 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9153 /* Complete overlap. We can remove the source AND. */
9154 if ((and_mask
& ze_mask
) == ze_mask
)
9155 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9157 /* Partial overlap. We can reduce the source AND. */
9158 if ((and_mask
& ze_mask
) != and_mask
)
9160 mode
= GET_MODE (src
);
9161 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9162 gen_int_mode (and_mask
& ze_mask
, mode
));
9163 return gen_rtx_SET (VOIDmode
, dest
, src
);
9167 /* The other case we handle is assignments into a constant-position
9168 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9169 a mask that has all one bits except for a group of zero bits and
9170 OTHER is known to have zeros where C1 has ones, this is such an
9171 assignment. Compute the position and length from C1. Shift OTHER
9172 to the appropriate position, force it to the required mode, and
9173 make the extraction. Check for the AND in both operands. */
9175 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9178 rhs
= expand_compound_operation (XEXP (src
, 0));
9179 lhs
= expand_compound_operation (XEXP (src
, 1));
9181 if (GET_CODE (rhs
) == AND
9182 && CONST_INT_P (XEXP (rhs
, 1))
9183 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9184 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9185 else if (GET_CODE (lhs
) == AND
9186 && CONST_INT_P (XEXP (lhs
, 1))
9187 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9188 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9192 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9193 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9194 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9195 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9198 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9202 /* The mode to use for the source is the mode of the assignment, or of
9203 what is inside a possible STRICT_LOW_PART. */
9204 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9205 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9207 /* Shift OTHER right POS places and make it the source, restricting it
9208 to the proper length and mode. */
9210 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9214 src
= force_to_mode (src
, mode
,
9215 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9216 ? ~(unsigned HOST_WIDE_INT
) 0
9217 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9220 /* If SRC is masked by an AND that does not make a difference in
9221 the value being stored, strip it. */
9222 if (GET_CODE (assign
) == ZERO_EXTRACT
9223 && CONST_INT_P (XEXP (assign
, 1))
9224 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9225 && GET_CODE (src
) == AND
9226 && CONST_INT_P (XEXP (src
, 1))
9227 && UINTVAL (XEXP (src
, 1))
9228 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9229 src
= XEXP (src
, 0);
9231 return gen_rtx_SET (VOIDmode
, assign
, src
);
9234 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9238 apply_distributive_law (rtx x
)
9240 enum rtx_code code
= GET_CODE (x
);
9241 enum rtx_code inner_code
;
9242 rtx lhs
, rhs
, other
;
9245 /* Distributivity is not true for floating point as it can change the
9246 value. So we don't do it unless -funsafe-math-optimizations. */
9247 if (FLOAT_MODE_P (GET_MODE (x
))
9248 && ! flag_unsafe_math_optimizations
)
9251 /* The outer operation can only be one of the following: */
9252 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9253 && code
!= PLUS
&& code
!= MINUS
)
9259 /* If either operand is a primitive we can't do anything, so get out
9261 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9264 lhs
= expand_compound_operation (lhs
);
9265 rhs
= expand_compound_operation (rhs
);
9266 inner_code
= GET_CODE (lhs
);
9267 if (inner_code
!= GET_CODE (rhs
))
9270 /* See if the inner and outer operations distribute. */
9277 /* These all distribute except over PLUS. */
9278 if (code
== PLUS
|| code
== MINUS
)
9283 if (code
!= PLUS
&& code
!= MINUS
)
9288 /* This is also a multiply, so it distributes over everything. */
9291 /* This used to handle SUBREG, but this turned out to be counter-
9292 productive, since (subreg (op ...)) usually is not handled by
9293 insn patterns, and this "optimization" therefore transformed
9294 recognizable patterns into unrecognizable ones. Therefore the
9295 SUBREG case was removed from here.
9297 It is possible that distributing SUBREG over arithmetic operations
9298 leads to an intermediate result than can then be optimized further,
9299 e.g. by moving the outer SUBREG to the other side of a SET as done
9300 in simplify_set. This seems to have been the original intent of
9301 handling SUBREGs here.
9303 However, with current GCC this does not appear to actually happen,
9304 at least on major platforms. If some case is found where removing
9305 the SUBREG case here prevents follow-on optimizations, distributing
9306 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9312 /* Set LHS and RHS to the inner operands (A and B in the example
9313 above) and set OTHER to the common operand (C in the example).
9314 There is only one way to do this unless the inner operation is
9316 if (COMMUTATIVE_ARITH_P (lhs
)
9317 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9318 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9319 else if (COMMUTATIVE_ARITH_P (lhs
)
9320 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9321 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9322 else if (COMMUTATIVE_ARITH_P (lhs
)
9323 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9324 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9325 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9326 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9330 /* Form the new inner operation, seeing if it simplifies first. */
9331 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9333 /* There is one exception to the general way of distributing:
9334 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9335 if (code
== XOR
&& inner_code
== IOR
)
9338 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9341 /* We may be able to continuing distributing the result, so call
9342 ourselves recursively on the inner operation before forming the
9343 outer operation, which we return. */
9344 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9345 apply_distributive_law (tem
), other
);
9348 /* See if X is of the form (* (+ A B) C), and if so convert to
9349 (+ (* A C) (* B C)) and try to simplify.
9351 Most of the time, this results in no change. However, if some of
9352 the operands are the same or inverses of each other, simplifications
9355 For example, (and (ior A B) (not B)) can occur as the result of
9356 expanding a bit field assignment. When we apply the distributive
9357 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9358 which then simplifies to (and (A (not B))).
9360 Note that no checks happen on the validity of applying the inverse
9361 distributive law. This is pointless since we can do it in the
9362 few places where this routine is called.
9364 N is the index of the term that is decomposed (the arithmetic operation,
9365 i.e. (+ A B) in the first example above). !N is the index of the term that
9366 is distributed, i.e. of C in the first example above. */
9368 distribute_and_simplify_rtx (rtx x
, int n
)
9370 enum machine_mode mode
;
9371 enum rtx_code outer_code
, inner_code
;
9372 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9374 /* Distributivity is not true for floating point as it can change the
9375 value. So we don't do it unless -funsafe-math-optimizations. */
9376 if (FLOAT_MODE_P (GET_MODE (x
))
9377 && ! flag_unsafe_math_optimizations
)
9380 decomposed
= XEXP (x
, n
);
9381 if (!ARITHMETIC_P (decomposed
))
9384 mode
= GET_MODE (x
);
9385 outer_code
= GET_CODE (x
);
9386 distributed
= XEXP (x
, !n
);
9388 inner_code
= GET_CODE (decomposed
);
9389 inner_op0
= XEXP (decomposed
, 0);
9390 inner_op1
= XEXP (decomposed
, 1);
9392 /* Special case (and (xor B C) (not A)), which is equivalent to
9393 (xor (ior A B) (ior A C)) */
9394 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9396 distributed
= XEXP (distributed
, 0);
9402 /* Distribute the second term. */
9403 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9404 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9408 /* Distribute the first term. */
9409 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9410 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9413 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9415 if (GET_CODE (tmp
) != outer_code
9416 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9417 < set_src_cost (x
, optimize_this_for_speed_p
)))
9423 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9424 in MODE. Return an equivalent form, if different from (and VAROP
9425 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9428 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9429 unsigned HOST_WIDE_INT constop
)
9431 unsigned HOST_WIDE_INT nonzero
;
9432 unsigned HOST_WIDE_INT orig_constop
;
9437 orig_constop
= constop
;
9438 if (GET_CODE (varop
) == CLOBBER
)
9441 /* Simplify VAROP knowing that we will be only looking at some of the
9444 Note by passing in CONSTOP, we guarantee that the bits not set in
9445 CONSTOP are not significant and will never be examined. We must
9446 ensure that is the case by explicitly masking out those bits
9447 before returning. */
9448 varop
= force_to_mode (varop
, mode
, constop
, 0);
9450 /* If VAROP is a CLOBBER, we will fail so return it. */
9451 if (GET_CODE (varop
) == CLOBBER
)
9454 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9455 to VAROP and return the new constant. */
9456 if (CONST_INT_P (varop
))
9457 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9459 /* See what bits may be nonzero in VAROP. Unlike the general case of
9460 a call to nonzero_bits, here we don't care about bits outside
9463 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9465 /* Turn off all bits in the constant that are known to already be zero.
9466 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9467 which is tested below. */
9471 /* If we don't have any bits left, return zero. */
9475 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9476 a power of two, we can replace this with an ASHIFT. */
9477 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9478 && (i
= exact_log2 (constop
)) >= 0)
9479 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9481 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9482 or XOR, then try to apply the distributive law. This may eliminate
9483 operations if either branch can be simplified because of the AND.
9484 It may also make some cases more complex, but those cases probably
9485 won't match a pattern either with or without this. */
9487 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9491 apply_distributive_law
9492 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9493 simplify_and_const_int (NULL_RTX
,
9497 simplify_and_const_int (NULL_RTX
,
9502 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9503 the AND and see if one of the operands simplifies to zero. If so, we
9504 may eliminate it. */
9506 if (GET_CODE (varop
) == PLUS
9507 && exact_log2 (constop
+ 1) >= 0)
9511 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9512 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9513 if (o0
== const0_rtx
)
9515 if (o1
== const0_rtx
)
9519 /* Make a SUBREG if necessary. If we can't make it, fail. */
9520 varop
= gen_lowpart (mode
, varop
);
9521 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9524 /* If we are only masking insignificant bits, return VAROP. */
9525 if (constop
== nonzero
)
9528 if (varop
== orig_varop
&& constop
== orig_constop
)
9531 /* Otherwise, return an AND. */
9532 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9536 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9539 Return an equivalent form, if different from X. Otherwise, return X. If
9540 X is zero, we are to always construct the equivalent form. */
9543 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9544 unsigned HOST_WIDE_INT constop
)
9546 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9551 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9552 gen_int_mode (constop
, mode
));
9553 if (GET_MODE (x
) != mode
)
9554 x
= gen_lowpart (mode
, x
);
9558 /* Given a REG, X, compute which bits in X can be nonzero.
9559 We don't care about bits outside of those defined in MODE.
9561 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9562 a shift, AND, or zero_extract, we can do better. */
9565 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9566 const_rtx known_x ATTRIBUTE_UNUSED
,
9567 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9568 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9569 unsigned HOST_WIDE_INT
*nonzero
)
9574 /* If X is a register whose nonzero bits value is current, use it.
9575 Otherwise, if X is a register whose value we can find, use that
9576 value. Otherwise, use the previously-computed global nonzero bits
9577 for this register. */
9579 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9580 if (rsp
->last_set_value
!= 0
9581 && (rsp
->last_set_mode
== mode
9582 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9583 && GET_MODE_CLASS (mode
) == MODE_INT
))
9584 && ((rsp
->last_set_label
>= label_tick_ebb_start
9585 && rsp
->last_set_label
< label_tick
)
9586 || (rsp
->last_set_label
== label_tick
9587 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9588 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9589 && REG_N_SETS (REGNO (x
)) == 1
9591 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9593 *nonzero
&= rsp
->last_set_nonzero_bits
;
9597 tem
= get_last_value (x
);
9601 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9602 /* If X is narrower than MODE and TEM is a non-negative
9603 constant that would appear negative in the mode of X,
9604 sign-extend it for use in reg_nonzero_bits because some
9605 machines (maybe most) will actually do the sign-extension
9606 and this is the conservative approach.
9608 ??? For 2.5, try to tighten up the MD files in this regard
9609 instead of this kludge. */
9611 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9612 && CONST_INT_P (tem
)
9614 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9615 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9619 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9621 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9623 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9624 /* We don't know anything about the upper bits. */
9625 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9632 /* Return the number of bits at the high-order end of X that are known to
9633 be equal to the sign bit. X will be used in mode MODE; if MODE is
9634 VOIDmode, X will be used in its own mode. The returned value will always
9635 be between 1 and the number of bits in MODE. */
9638 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9639 const_rtx known_x ATTRIBUTE_UNUSED
,
9640 enum machine_mode known_mode
9642 unsigned int known_ret ATTRIBUTE_UNUSED
,
9643 unsigned int *result
)
9648 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9649 if (rsp
->last_set_value
!= 0
9650 && rsp
->last_set_mode
== mode
9651 && ((rsp
->last_set_label
>= label_tick_ebb_start
9652 && rsp
->last_set_label
< label_tick
)
9653 || (rsp
->last_set_label
== label_tick
9654 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9655 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9656 && REG_N_SETS (REGNO (x
)) == 1
9658 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9660 *result
= rsp
->last_set_sign_bit_copies
;
9664 tem
= get_last_value (x
);
9668 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9669 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9670 *result
= rsp
->sign_bit_copies
;
9675 /* Return the number of "extended" bits there are in X, when interpreted
9676 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9677 unsigned quantities, this is the number of high-order zero bits.
9678 For signed quantities, this is the number of copies of the sign bit
9679 minus 1. In both case, this function returns the number of "spare"
9680 bits. For example, if two quantities for which this function returns
9681 at least 1 are added, the addition is known not to overflow.
9683 This function will always return 0 unless called during combine, which
9684 implies that it must be called from a define_split. */
9687 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9689 if (nonzero_sign_valid
== 0)
9693 ? (HWI_COMPUTABLE_MODE_P (mode
)
9694 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9695 - floor_log2 (nonzero_bits (x
, mode
)))
9697 : num_sign_bit_copies (x
, mode
) - 1);
9700 /* This function is called from `simplify_shift_const' to merge two
9701 outer operations. Specifically, we have already found that we need
9702 to perform operation *POP0 with constant *PCONST0 at the outermost
9703 position. We would now like to also perform OP1 with constant CONST1
9704 (with *POP0 being done last).
9706 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9707 the resulting operation. *PCOMP_P is set to 1 if we would need to
9708 complement the innermost operand, otherwise it is unchanged.
9710 MODE is the mode in which the operation will be done. No bits outside
9711 the width of this mode matter. It is assumed that the width of this mode
9712 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9714 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9715 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9716 result is simply *PCONST0.
9718 If the resulting operation cannot be expressed as one operation, we
9719 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9722 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9724 enum rtx_code op0
= *pop0
;
9725 HOST_WIDE_INT const0
= *pconst0
;
9727 const0
&= GET_MODE_MASK (mode
);
9728 const1
&= GET_MODE_MASK (mode
);
9730 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9734 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9737 if (op1
== UNKNOWN
|| op0
== SET
)
9740 else if (op0
== UNKNOWN
)
9741 op0
= op1
, const0
= const1
;
9743 else if (op0
== op1
)
9767 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9768 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9771 /* If the two constants aren't the same, we can't do anything. The
9772 remaining six cases can all be done. */
9773 else if (const0
!= const1
)
9781 /* (a & b) | b == b */
9783 else /* op1 == XOR */
9784 /* (a ^ b) | b == a | b */
9790 /* (a & b) ^ b == (~a) & b */
9791 op0
= AND
, *pcomp_p
= 1;
9792 else /* op1 == IOR */
9793 /* (a | b) ^ b == a & ~b */
9794 op0
= AND
, const0
= ~const0
;
9799 /* (a | b) & b == b */
9801 else /* op1 == XOR */
9802 /* (a ^ b) & b) == (~a) & b */
9809 /* Check for NO-OP cases. */
9810 const0
&= GET_MODE_MASK (mode
);
9812 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9814 else if (const0
== 0 && op0
== AND
)
9816 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9822 /* ??? Slightly redundant with the above mask, but not entirely.
9823 Moving this above means we'd have to sign-extend the mode mask
9824 for the final test. */
9825 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9826 *pconst0
= trunc_int_for_mode (const0
, mode
);
9831 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9832 the shift in. The original shift operation CODE is performed on OP in
9833 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9834 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9835 result of the shift is subject to operation OUTER_CODE with operand
9838 static enum machine_mode
9839 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9840 enum machine_mode orig_mode
, enum machine_mode mode
,
9841 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9843 if (orig_mode
== mode
)
9845 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9847 /* In general we can't perform in wider mode for right shift and rotate. */
9851 /* We can still widen if the bits brought in from the left are identical
9852 to the sign bit of ORIG_MODE. */
9853 if (num_sign_bit_copies (op
, mode
)
9854 > (unsigned) (GET_MODE_PRECISION (mode
)
9855 - GET_MODE_PRECISION (orig_mode
)))
9860 /* Similarly here but with zero bits. */
9861 if (HWI_COMPUTABLE_MODE_P (mode
)
9862 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9865 /* We can also widen if the bits brought in will be masked off. This
9866 operation is performed in ORIG_MODE. */
9867 if (outer_code
== AND
)
9869 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9872 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9888 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9889 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9890 if we cannot simplify it. Otherwise, return a simplified value.
9892 The shift is normally computed in the widest mode we find in VAROP, as
9893 long as it isn't a different number of words than RESULT_MODE. Exceptions
9894 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9897 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9898 rtx varop
, int orig_count
)
9900 enum rtx_code orig_code
= code
;
9901 rtx orig_varop
= varop
;
9903 enum machine_mode mode
= result_mode
;
9904 enum machine_mode shift_mode
, tmode
;
9905 unsigned int mode_words
9906 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9907 /* We form (outer_op (code varop count) (outer_const)). */
9908 enum rtx_code outer_op
= UNKNOWN
;
9909 HOST_WIDE_INT outer_const
= 0;
9910 int complement_p
= 0;
9913 /* Make sure and truncate the "natural" shift on the way in. We don't
9914 want to do this inside the loop as it makes it more difficult to
9916 if (SHIFT_COUNT_TRUNCATED
)
9917 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9919 /* If we were given an invalid count, don't do anything except exactly
9920 what was requested. */
9922 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9927 /* Unless one of the branches of the `if' in this loop does a `continue',
9928 we will `break' the loop after the `if'. */
9932 /* If we have an operand of (clobber (const_int 0)), fail. */
9933 if (GET_CODE (varop
) == CLOBBER
)
9936 /* Convert ROTATERT to ROTATE. */
9937 if (code
== ROTATERT
)
9939 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9941 if (VECTOR_MODE_P (result_mode
))
9942 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9944 count
= bitsize
- count
;
9947 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9948 mode
, outer_op
, outer_const
);
9950 /* Handle cases where the count is greater than the size of the mode
9951 minus 1. For ASHIFT, use the size minus one as the count (this can
9952 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9953 take the count modulo the size. For other shifts, the result is
9956 Since these shifts are being produced by the compiler by combining
9957 multiple operations, each of which are defined, we know what the
9958 result is supposed to be. */
9960 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9962 if (code
== ASHIFTRT
)
9963 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9964 else if (code
== ROTATE
|| code
== ROTATERT
)
9965 count
%= GET_MODE_PRECISION (shift_mode
);
9968 /* We can't simply return zero because there may be an
9976 /* If we discovered we had to complement VAROP, leave. Making a NOT
9977 here would cause an infinite loop. */
9981 /* An arithmetic right shift of a quantity known to be -1 or 0
9983 if (code
== ASHIFTRT
9984 && (num_sign_bit_copies (varop
, shift_mode
)
9985 == GET_MODE_PRECISION (shift_mode
)))
9991 /* If we are doing an arithmetic right shift and discarding all but
9992 the sign bit copies, this is equivalent to doing a shift by the
9993 bitsize minus one. Convert it into that shift because it will often
9994 allow other simplifications. */
9996 if (code
== ASHIFTRT
9997 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9998 >= GET_MODE_PRECISION (shift_mode
)))
9999 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10001 /* We simplify the tests below and elsewhere by converting
10002 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10003 `make_compound_operation' will convert it to an ASHIFTRT for
10004 those machines (such as VAX) that don't have an LSHIFTRT. */
10005 if (code
== ASHIFTRT
10006 && val_signbit_known_clear_p (shift_mode
,
10007 nonzero_bits (varop
, shift_mode
)))
10010 if (((code
== LSHIFTRT
10011 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10012 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10014 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10015 && !((nonzero_bits (varop
, shift_mode
) << count
)
10016 & GET_MODE_MASK (shift_mode
))))
10017 && !side_effects_p (varop
))
10018 varop
= const0_rtx
;
10020 switch (GET_CODE (varop
))
10026 new_rtx
= expand_compound_operation (varop
);
10027 if (new_rtx
!= varop
)
10035 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10036 minus the width of a smaller mode, we can do this with a
10037 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10038 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10039 && ! mode_dependent_address_p (XEXP (varop
, 0))
10040 && ! MEM_VOLATILE_P (varop
)
10041 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10042 MODE_INT
, 1)) != BLKmode
)
10044 new_rtx
= adjust_address_nv (varop
, tmode
,
10045 BYTES_BIG_ENDIAN
? 0
10046 : count
/ BITS_PER_UNIT
);
10048 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10049 : ZERO_EXTEND
, mode
, new_rtx
);
10056 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10057 the same number of words as what we've seen so far. Then store
10058 the widest mode in MODE. */
10059 if (subreg_lowpart_p (varop
)
10060 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10061 > GET_MODE_SIZE (GET_MODE (varop
)))
10062 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10063 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10065 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10066 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10068 varop
= SUBREG_REG (varop
);
10069 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10070 mode
= GET_MODE (varop
);
10076 /* Some machines use MULT instead of ASHIFT because MULT
10077 is cheaper. But it is still better on those machines to
10078 merge two shifts into one. */
10079 if (CONST_INT_P (XEXP (varop
, 1))
10080 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10083 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10085 GEN_INT (exact_log2 (
10086 UINTVAL (XEXP (varop
, 1)))));
10092 /* Similar, for when divides are cheaper. */
10093 if (CONST_INT_P (XEXP (varop
, 1))
10094 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10097 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10099 GEN_INT (exact_log2 (
10100 UINTVAL (XEXP (varop
, 1)))));
10106 /* If we are extracting just the sign bit of an arithmetic
10107 right shift, that shift is not needed. However, the sign
10108 bit of a wider mode may be different from what would be
10109 interpreted as the sign bit in a narrower mode, so, if
10110 the result is narrower, don't discard the shift. */
10111 if (code
== LSHIFTRT
10112 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10113 && (GET_MODE_BITSIZE (result_mode
)
10114 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10116 varop
= XEXP (varop
, 0);
10120 /* ... fall through ... */
10125 /* Here we have two nested shifts. The result is usually the
10126 AND of a new shift with a mask. We compute the result below. */
10127 if (CONST_INT_P (XEXP (varop
, 1))
10128 && INTVAL (XEXP (varop
, 1)) >= 0
10129 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10130 && HWI_COMPUTABLE_MODE_P (result_mode
)
10131 && HWI_COMPUTABLE_MODE_P (mode
)
10132 && !VECTOR_MODE_P (result_mode
))
10134 enum rtx_code first_code
= GET_CODE (varop
);
10135 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10136 unsigned HOST_WIDE_INT mask
;
10139 /* We have one common special case. We can't do any merging if
10140 the inner code is an ASHIFTRT of a smaller mode. However, if
10141 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10142 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10143 we can convert it to
10144 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10145 This simplifies certain SIGN_EXTEND operations. */
10146 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10147 && count
== (GET_MODE_PRECISION (result_mode
)
10148 - GET_MODE_PRECISION (GET_MODE (varop
))))
10150 /* C3 has the low-order C1 bits zero. */
10152 mask
= GET_MODE_MASK (mode
)
10153 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10155 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10156 XEXP (varop
, 0), mask
);
10157 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10159 count
= first_count
;
10164 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10165 than C1 high-order bits equal to the sign bit, we can convert
10166 this to either an ASHIFT or an ASHIFTRT depending on the
10169 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10171 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10172 && GET_MODE (varop
) == shift_mode
10173 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10176 varop
= XEXP (varop
, 0);
10177 count
-= first_count
;
10187 /* There are some cases we can't do. If CODE is ASHIFTRT,
10188 we can only do this if FIRST_CODE is also ASHIFTRT.
10190 We can't do the case when CODE is ROTATE and FIRST_CODE is
10193 If the mode of this shift is not the mode of the outer shift,
10194 we can't do this if either shift is a right shift or ROTATE.
10196 Finally, we can't do any of these if the mode is too wide
10197 unless the codes are the same.
10199 Handle the case where the shift codes are the same
10202 if (code
== first_code
)
10204 if (GET_MODE (varop
) != result_mode
10205 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10206 || code
== ROTATE
))
10209 count
+= first_count
;
10210 varop
= XEXP (varop
, 0);
10214 if (code
== ASHIFTRT
10215 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10216 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10217 || (GET_MODE (varop
) != result_mode
10218 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10219 || first_code
== ROTATE
10220 || code
== ROTATE
)))
10223 /* To compute the mask to apply after the shift, shift the
10224 nonzero bits of the inner shift the same way the
10225 outer shift will. */
10227 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10230 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10233 /* Give up if we can't compute an outer operation to use. */
10235 || !CONST_INT_P (mask_rtx
)
10236 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10238 result_mode
, &complement_p
))
10241 /* If the shifts are in the same direction, we add the
10242 counts. Otherwise, we subtract them. */
10243 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10244 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10245 count
+= first_count
;
10247 count
-= first_count
;
10249 /* If COUNT is positive, the new shift is usually CODE,
10250 except for the two exceptions below, in which case it is
10251 FIRST_CODE. If the count is negative, FIRST_CODE should
10254 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10255 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10257 else if (count
< 0)
10258 code
= first_code
, count
= -count
;
10260 varop
= XEXP (varop
, 0);
10264 /* If we have (A << B << C) for any shift, we can convert this to
10265 (A << C << B). This wins if A is a constant. Only try this if
10266 B is not a constant. */
10268 else if (GET_CODE (varop
) == code
10269 && CONST_INT_P (XEXP (varop
, 0))
10270 && !CONST_INT_P (XEXP (varop
, 1)))
10272 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10275 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10282 if (VECTOR_MODE_P (mode
))
10285 /* Make this fit the case below. */
10286 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10292 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10293 with C the size of VAROP - 1 and the shift is logical if
10294 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10295 we have an (le X 0) operation. If we have an arithmetic shift
10296 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10297 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10299 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10300 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10301 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10302 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10303 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10304 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10307 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10310 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10311 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10316 /* If we have (shift (logical)), move the logical to the outside
10317 to allow it to possibly combine with another logical and the
10318 shift to combine with another shift. This also canonicalizes to
10319 what a ZERO_EXTRACT looks like. Also, some machines have
10320 (and (shift)) insns. */
10322 if (CONST_INT_P (XEXP (varop
, 1))
10323 /* We can't do this if we have (ashiftrt (xor)) and the
10324 constant has its sign bit set in shift_mode. */
10325 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10326 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10328 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10330 GEN_INT (count
))) != 0
10331 && CONST_INT_P (new_rtx
)
10332 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10333 INTVAL (new_rtx
), result_mode
, &complement_p
))
10335 varop
= XEXP (varop
, 0);
10339 /* If we can't do that, try to simplify the shift in each arm of the
10340 logical expression, make a new logical expression, and apply
10341 the inverse distributive law. This also can't be done
10342 for some (ashiftrt (xor)). */
10343 if (CONST_INT_P (XEXP (varop
, 1))
10344 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10345 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10348 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10349 XEXP (varop
, 0), count
);
10350 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10351 XEXP (varop
, 1), count
);
10353 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10355 varop
= apply_distributive_law (varop
);
10363 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10364 says that the sign bit can be tested, FOO has mode MODE, C is
10365 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10366 that may be nonzero. */
10367 if (code
== LSHIFTRT
10368 && XEXP (varop
, 1) == const0_rtx
10369 && GET_MODE (XEXP (varop
, 0)) == result_mode
10370 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10371 && HWI_COMPUTABLE_MODE_P (result_mode
)
10372 && STORE_FLAG_VALUE
== -1
10373 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10374 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10377 varop
= XEXP (varop
, 0);
10384 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10385 than the number of bits in the mode is equivalent to A. */
10386 if (code
== LSHIFTRT
10387 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10388 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10390 varop
= XEXP (varop
, 0);
10395 /* NEG commutes with ASHIFT since it is multiplication. Move the
10396 NEG outside to allow shifts to combine. */
10398 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10401 varop
= XEXP (varop
, 0);
10407 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10408 is one less than the number of bits in the mode is
10409 equivalent to (xor A 1). */
10410 if (code
== LSHIFTRT
10411 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10412 && XEXP (varop
, 1) == constm1_rtx
10413 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10414 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10418 varop
= XEXP (varop
, 0);
10422 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10423 that might be nonzero in BAR are those being shifted out and those
10424 bits are known zero in FOO, we can replace the PLUS with FOO.
10425 Similarly in the other operand order. This code occurs when
10426 we are computing the size of a variable-size array. */
10428 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10429 && count
< HOST_BITS_PER_WIDE_INT
10430 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10431 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10432 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10434 varop
= XEXP (varop
, 0);
10437 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10438 && count
< HOST_BITS_PER_WIDE_INT
10439 && HWI_COMPUTABLE_MODE_P (result_mode
)
10440 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10442 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10443 & nonzero_bits (XEXP (varop
, 1),
10446 varop
= XEXP (varop
, 1);
10450 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10452 && CONST_INT_P (XEXP (varop
, 1))
10453 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10455 GEN_INT (count
))) != 0
10456 && CONST_INT_P (new_rtx
)
10457 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10458 INTVAL (new_rtx
), result_mode
, &complement_p
))
10460 varop
= XEXP (varop
, 0);
10464 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10465 signbit', and attempt to change the PLUS to an XOR and move it to
10466 the outer operation as is done above in the AND/IOR/XOR case
10467 leg for shift(logical). See details in logical handling above
10468 for reasoning in doing so. */
10469 if (code
== LSHIFTRT
10470 && CONST_INT_P (XEXP (varop
, 1))
10471 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10472 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10474 GEN_INT (count
))) != 0
10475 && CONST_INT_P (new_rtx
)
10476 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10477 INTVAL (new_rtx
), result_mode
, &complement_p
))
10479 varop
= XEXP (varop
, 0);
10486 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10487 with C the size of VAROP - 1 and the shift is logical if
10488 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10489 we have a (gt X 0) operation. If the shift is arithmetic with
10490 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10491 we have a (neg (gt X 0)) operation. */
10493 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10494 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10495 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10496 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10497 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10498 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10499 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10502 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10505 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10506 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10513 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10514 if the truncate does not affect the value. */
10515 if (code
== LSHIFTRT
10516 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10517 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10518 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10519 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10520 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10522 rtx varop_inner
= XEXP (varop
, 0);
10525 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10526 XEXP (varop_inner
, 0),
10528 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10529 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10542 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10543 outer_op
, outer_const
);
10545 /* We have now finished analyzing the shift. The result should be
10546 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10547 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10548 to the result of the shift. OUTER_CONST is the relevant constant,
10549 but we must turn off all bits turned off in the shift. */
10551 if (outer_op
== UNKNOWN
10552 && orig_code
== code
&& orig_count
== count
10553 && varop
== orig_varop
10554 && shift_mode
== GET_MODE (varop
))
10557 /* Make a SUBREG if necessary. If we can't make it, fail. */
10558 varop
= gen_lowpart (shift_mode
, varop
);
10559 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10562 /* If we have an outer operation and we just made a shift, it is
10563 possible that we could have simplified the shift were it not
10564 for the outer operation. So try to do the simplification
10567 if (outer_op
!= UNKNOWN
)
10568 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10573 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10575 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10576 turn off all the bits that the shift would have turned off. */
10577 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10578 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10579 GET_MODE_MASK (result_mode
) >> orig_count
);
10581 /* Do the remainder of the processing in RESULT_MODE. */
10582 x
= gen_lowpart_or_truncate (result_mode
, x
);
10584 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10587 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10589 if (outer_op
!= UNKNOWN
)
10591 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10592 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10593 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10595 if (outer_op
== AND
)
10596 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10597 else if (outer_op
== SET
)
10599 /* This means that we have determined that the result is
10600 equivalent to a constant. This should be rare. */
10601 if (!side_effects_p (x
))
10602 x
= GEN_INT (outer_const
);
10604 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10605 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10607 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10608 GEN_INT (outer_const
));
10614 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10615 The result of the shift is RESULT_MODE. If we cannot simplify it,
10616 return X or, if it is NULL, synthesize the expression with
10617 simplify_gen_binary. Otherwise, return a simplified value.
10619 The shift is normally computed in the widest mode we find in VAROP, as
10620 long as it isn't a different number of words than RESULT_MODE. Exceptions
10621 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10624 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10625 rtx varop
, int count
)
10627 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10632 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10633 if (GET_MODE (x
) != result_mode
)
10634 x
= gen_lowpart (result_mode
, x
);
10639 /* Like recog, but we receive the address of a pointer to a new pattern.
10640 We try to match the rtx that the pointer points to.
10641 If that fails, we may try to modify or replace the pattern,
10642 storing the replacement into the same pointer object.
10644 Modifications include deletion or addition of CLOBBERs.
10646 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10647 the CLOBBERs are placed.
10649 The value is the final insn code from the pattern ultimately matched,
10653 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10655 rtx pat
= *pnewpat
;
10656 int insn_code_number
;
10657 int num_clobbers_to_add
= 0;
10660 rtx old_notes
, old_pat
;
10662 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10663 we use to indicate that something didn't match. If we find such a
10664 thing, force rejection. */
10665 if (GET_CODE (pat
) == PARALLEL
)
10666 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10667 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10668 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10671 old_pat
= PATTERN (insn
);
10672 old_notes
= REG_NOTES (insn
);
10673 PATTERN (insn
) = pat
;
10674 REG_NOTES (insn
) = 0;
10676 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10677 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10679 if (insn_code_number
< 0)
10680 fputs ("Failed to match this instruction:\n", dump_file
);
10682 fputs ("Successfully matched this instruction:\n", dump_file
);
10683 print_rtl_single (dump_file
, pat
);
10686 /* If it isn't, there is the possibility that we previously had an insn
10687 that clobbered some register as a side effect, but the combined
10688 insn doesn't need to do that. So try once more without the clobbers
10689 unless this represents an ASM insn. */
10691 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10692 && GET_CODE (pat
) == PARALLEL
)
10696 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10697 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10700 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10704 SUBST_INT (XVECLEN (pat
, 0), pos
);
10707 pat
= XVECEXP (pat
, 0, 0);
10709 PATTERN (insn
) = pat
;
10710 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10711 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10713 if (insn_code_number
< 0)
10714 fputs ("Failed to match this instruction:\n", dump_file
);
10716 fputs ("Successfully matched this instruction:\n", dump_file
);
10717 print_rtl_single (dump_file
, pat
);
10720 PATTERN (insn
) = old_pat
;
10721 REG_NOTES (insn
) = old_notes
;
10723 /* Recognize all noop sets, these will be killed by followup pass. */
10724 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10725 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10727 /* If we had any clobbers to add, make a new pattern than contains
10728 them. Then check to make sure that all of them are dead. */
10729 if (num_clobbers_to_add
)
10731 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10732 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10733 ? (XVECLEN (pat
, 0)
10734 + num_clobbers_to_add
)
10735 : num_clobbers_to_add
+ 1));
10737 if (GET_CODE (pat
) == PARALLEL
)
10738 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10739 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10741 XVECEXP (newpat
, 0, 0) = pat
;
10743 add_clobbers (newpat
, insn_code_number
);
10745 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10746 i
< XVECLEN (newpat
, 0); i
++)
10748 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10749 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10751 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10753 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10754 notes
= alloc_reg_note (REG_UNUSED
,
10755 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10764 return insn_code_number
;
10767 /* Like gen_lowpart_general but for use by combine. In combine it
10768 is not possible to create any new pseudoregs. However, it is
10769 safe to create invalid memory addresses, because combine will
10770 try to recognize them and all they will do is make the combine
10773 If for some reason this cannot do its job, an rtx
10774 (clobber (const_int 0)) is returned.
10775 An insn containing that will not be recognized. */
10778 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10780 enum machine_mode imode
= GET_MODE (x
);
10781 unsigned int osize
= GET_MODE_SIZE (omode
);
10782 unsigned int isize
= GET_MODE_SIZE (imode
);
10785 if (omode
== imode
)
10788 /* Return identity if this is a CONST or symbolic reference. */
10790 && (GET_CODE (x
) == CONST
10791 || GET_CODE (x
) == SYMBOL_REF
10792 || GET_CODE (x
) == LABEL_REF
))
10795 /* We can only support MODE being wider than a word if X is a
10796 constant integer or has a mode the same size. */
10797 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10798 && ! ((imode
== VOIDmode
10799 && (CONST_INT_P (x
)
10800 || GET_CODE (x
) == CONST_DOUBLE
))
10801 || isize
== osize
))
10804 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10805 won't know what to do. So we will strip off the SUBREG here and
10806 process normally. */
10807 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10809 x
= SUBREG_REG (x
);
10811 /* For use in case we fall down into the address adjustments
10812 further below, we need to adjust the known mode and size of
10813 x; imode and isize, since we just adjusted x. */
10814 imode
= GET_MODE (x
);
10816 if (imode
== omode
)
10819 isize
= GET_MODE_SIZE (imode
);
10822 result
= gen_lowpart_common (omode
, x
);
10831 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10833 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10836 /* If we want to refer to something bigger than the original memref,
10837 generate a paradoxical subreg instead. That will force a reload
10838 of the original memref X. */
10840 return gen_rtx_SUBREG (omode
, x
, 0);
10842 if (WORDS_BIG_ENDIAN
)
10843 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10845 /* Adjust the address so that the address-after-the-data is
10847 if (BYTES_BIG_ENDIAN
)
10848 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10850 return adjust_address_nv (x
, omode
, offset
);
10853 /* If X is a comparison operator, rewrite it in a new mode. This
10854 probably won't match, but may allow further simplifications. */
10855 else if (COMPARISON_P (x
))
10856 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10858 /* If we couldn't simplify X any other way, just enclose it in a
10859 SUBREG. Normally, this SUBREG won't match, but some patterns may
10860 include an explicit SUBREG or we may simplify it further in combine. */
10866 offset
= subreg_lowpart_offset (omode
, imode
);
10867 if (imode
== VOIDmode
)
10869 imode
= int_mode_for_mode (omode
);
10870 x
= gen_lowpart_common (imode
, x
);
10874 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10880 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10883 /* Try to simplify a comparison between OP0 and a constant OP1,
10884 where CODE is the comparison code that will be tested, into a
10885 (CODE OP0 const0_rtx) form.
10887 The result is a possibly different comparison code to use.
10888 *POP1 may be updated. */
10890 static enum rtx_code
10891 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10893 enum machine_mode mode
= GET_MODE (op0
);
10894 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10895 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10897 /* Get the constant we are comparing against and turn off all bits
10898 not on in our mode. */
10899 if (mode
!= VOIDmode
)
10900 const_op
= trunc_int_for_mode (const_op
, mode
);
10902 /* If we are comparing against a constant power of two and the value
10903 being compared can only have that single bit nonzero (e.g., it was
10904 `and'ed with that bit), we can replace this with a comparison
10907 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10908 || code
== LT
|| code
== LTU
)
10909 && mode_width
<= HOST_BITS_PER_WIDE_INT
10910 && exact_log2 (const_op
) >= 0
10911 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10913 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10917 /* Similarly, if we are comparing a value known to be either -1 or
10918 0 with -1, change it to the opposite comparison against zero. */
10920 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10921 || code
== GEU
|| code
== LTU
)
10922 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10924 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10928 /* Do some canonicalizations based on the comparison code. We prefer
10929 comparisons against zero and then prefer equality comparisons.
10930 If we can reduce the size of a constant, we will do that too. */
10934 /* < C is equivalent to <= (C - 1) */
10939 /* ... fall through to LE case below. */
10945 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10952 /* If we are doing a <= 0 comparison on a value known to have
10953 a zero sign bit, we can replace this with == 0. */
10954 else if (const_op
== 0
10955 && mode_width
<= HOST_BITS_PER_WIDE_INT
10956 && (nonzero_bits (op0
, mode
)
10957 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10963 /* >= C is equivalent to > (C - 1). */
10968 /* ... fall through to GT below. */
10974 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10981 /* If we are doing a > 0 comparison on a value known to have
10982 a zero sign bit, we can replace this with != 0. */
10983 else if (const_op
== 0
10984 && mode_width
<= HOST_BITS_PER_WIDE_INT
10985 && (nonzero_bits (op0
, mode
)
10986 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10992 /* < C is equivalent to <= (C - 1). */
10997 /* ... fall through ... */
10999 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11000 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11001 && (unsigned HOST_WIDE_INT
) const_op
11002 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11012 /* unsigned <= 0 is equivalent to == 0 */
11015 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11016 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11017 && (unsigned HOST_WIDE_INT
) const_op
11018 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11026 /* >= C is equivalent to > (C - 1). */
11031 /* ... fall through ... */
11034 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11035 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11036 && (unsigned HOST_WIDE_INT
) const_op
11037 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11047 /* unsigned > 0 is equivalent to != 0 */
11050 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11051 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
11052 && (unsigned HOST_WIDE_INT
) const_op
11053 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11064 *pop1
= GEN_INT (const_op
);
11068 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11069 comparison code that will be tested.
11071 The result is a possibly different comparison code to use. *POP0 and
11072 *POP1 may be updated.
11074 It is possible that we might detect that a comparison is either always
11075 true or always false. However, we do not perform general constant
11076 folding in combine, so this knowledge isn't useful. Such tautologies
11077 should have been detected earlier. Hence we ignore all such cases. */
11079 static enum rtx_code
11080 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11086 enum machine_mode mode
, tmode
;
11088 /* Try a few ways of applying the same transformation to both operands. */
11091 #ifndef WORD_REGISTER_OPERATIONS
11092 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11093 so check specially. */
11094 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11095 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11096 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11097 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11098 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11099 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11100 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11101 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11102 && CONST_INT_P (XEXP (op0
, 1))
11103 && XEXP (op0
, 1) == XEXP (op1
, 1)
11104 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11105 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11106 && (INTVAL (XEXP (op0
, 1))
11107 == (GET_MODE_PRECISION (GET_MODE (op0
))
11108 - (GET_MODE_PRECISION
11109 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11111 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11112 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11116 /* If both operands are the same constant shift, see if we can ignore the
11117 shift. We can if the shift is a rotate or if the bits shifted out of
11118 this shift are known to be zero for both inputs and if the type of
11119 comparison is compatible with the shift. */
11120 if (GET_CODE (op0
) == GET_CODE (op1
)
11121 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0
))
11122 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11123 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11124 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11125 || (GET_CODE (op0
) == ASHIFTRT
11126 && (code
!= GTU
&& code
!= LTU
11127 && code
!= GEU
&& code
!= LEU
)))
11128 && CONST_INT_P (XEXP (op0
, 1))
11129 && INTVAL (XEXP (op0
, 1)) >= 0
11130 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11131 && XEXP (op0
, 1) == XEXP (op1
, 1))
11133 enum machine_mode mode
= GET_MODE (op0
);
11134 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11135 int shift_count
= INTVAL (XEXP (op0
, 1));
11137 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11138 mask
&= (mask
>> shift_count
) << shift_count
;
11139 else if (GET_CODE (op0
) == ASHIFT
)
11140 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11142 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11143 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11144 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11149 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11150 SUBREGs are of the same mode, and, in both cases, the AND would
11151 be redundant if the comparison was done in the narrower mode,
11152 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11153 and the operand's possibly nonzero bits are 0xffffff01; in that case
11154 if we only care about QImode, we don't need the AND). This case
11155 occurs if the output mode of an scc insn is not SImode and
11156 STORE_FLAG_VALUE == 1 (e.g., the 386).
11158 Similarly, check for a case where the AND's are ZERO_EXTEND
11159 operations from some narrower mode even though a SUBREG is not
11162 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11163 && CONST_INT_P (XEXP (op0
, 1))
11164 && CONST_INT_P (XEXP (op1
, 1)))
11166 rtx inner_op0
= XEXP (op0
, 0);
11167 rtx inner_op1
= XEXP (op1
, 0);
11168 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11169 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11172 if (paradoxical_subreg_p (inner_op0
)
11173 && GET_CODE (inner_op1
) == SUBREG
11174 && (GET_MODE (SUBREG_REG (inner_op0
))
11175 == GET_MODE (SUBREG_REG (inner_op1
)))
11176 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11177 <= HOST_BITS_PER_WIDE_INT
)
11178 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11179 GET_MODE (SUBREG_REG (inner_op0
)))))
11180 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11181 GET_MODE (SUBREG_REG (inner_op1
))))))
11183 op0
= SUBREG_REG (inner_op0
);
11184 op1
= SUBREG_REG (inner_op1
);
11186 /* The resulting comparison is always unsigned since we masked
11187 off the original sign bit. */
11188 code
= unsigned_condition (code
);
11194 for (tmode
= GET_CLASS_NARROWEST_MODE
11195 (GET_MODE_CLASS (GET_MODE (op0
)));
11196 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11197 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11199 op0
= gen_lowpart (tmode
, inner_op0
);
11200 op1
= gen_lowpart (tmode
, inner_op1
);
11201 code
= unsigned_condition (code
);
11210 /* If both operands are NOT, we can strip off the outer operation
11211 and adjust the comparison code for swapped operands; similarly for
11212 NEG, except that this must be an equality comparison. */
11213 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11214 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11215 && (code
== EQ
|| code
== NE
)))
11216 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11222 /* If the first operand is a constant, swap the operands and adjust the
11223 comparison code appropriately, but don't do this if the second operand
11224 is already a constant integer. */
11225 if (swap_commutative_operands_p (op0
, op1
))
11227 tem
= op0
, op0
= op1
, op1
= tem
;
11228 code
= swap_condition (code
);
11231 /* We now enter a loop during which we will try to simplify the comparison.
11232 For the most part, we only are concerned with comparisons with zero,
11233 but some things may really be comparisons with zero but not start
11234 out looking that way. */
11236 while (CONST_INT_P (op1
))
11238 enum machine_mode mode
= GET_MODE (op0
);
11239 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11240 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11241 int equality_comparison_p
;
11242 int sign_bit_comparison_p
;
11243 int unsigned_comparison_p
;
11244 HOST_WIDE_INT const_op
;
11246 /* We only want to handle integral modes. This catches VOIDmode,
11247 CCmode, and the floating-point modes. An exception is that we
11248 can handle VOIDmode if OP0 is a COMPARE or a comparison
11251 if (GET_MODE_CLASS (mode
) != MODE_INT
11252 && ! (mode
== VOIDmode
11253 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11256 /* Try to simplify the compare to constant, possibly changing the
11257 comparison op, and/or changing op1 to zero. */
11258 code
= simplify_compare_const (code
, op0
, &op1
);
11259 const_op
= INTVAL (op1
);
11261 /* Compute some predicates to simplify code below. */
11263 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11264 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11265 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11268 /* If this is a sign bit comparison and we can do arithmetic in
11269 MODE, say that we will only be needing the sign bit of OP0. */
11270 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11271 op0
= force_to_mode (op0
, mode
,
11272 (unsigned HOST_WIDE_INT
) 1
11273 << (GET_MODE_PRECISION (mode
) - 1),
11276 /* Now try cases based on the opcode of OP0. If none of the cases
11277 does a "continue", we exit this loop immediately after the
11280 switch (GET_CODE (op0
))
11283 /* If we are extracting a single bit from a variable position in
11284 a constant that has only a single bit set and are comparing it
11285 with zero, we can convert this into an equality comparison
11286 between the position and the location of the single bit. */
11287 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11288 have already reduced the shift count modulo the word size. */
11289 if (!SHIFT_COUNT_TRUNCATED
11290 && CONST_INT_P (XEXP (op0
, 0))
11291 && XEXP (op0
, 1) == const1_rtx
11292 && equality_comparison_p
&& const_op
== 0
11293 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11295 if (BITS_BIG_ENDIAN
)
11297 enum machine_mode new_mode
11298 = mode_for_extraction (EP_extzv
, 1);
11299 if (new_mode
== MAX_MACHINE_MODE
)
11300 i
= BITS_PER_WORD
- 1 - i
;
11304 i
= (GET_MODE_PRECISION (mode
) - 1 - i
);
11308 op0
= XEXP (op0
, 2);
11312 /* Result is nonzero iff shift count is equal to I. */
11313 code
= reverse_condition (code
);
11317 /* ... fall through ... */
11320 tem
= expand_compound_operation (op0
);
11329 /* If testing for equality, we can take the NOT of the constant. */
11330 if (equality_comparison_p
11331 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11333 op0
= XEXP (op0
, 0);
11338 /* If just looking at the sign bit, reverse the sense of the
11340 if (sign_bit_comparison_p
)
11342 op0
= XEXP (op0
, 0);
11343 code
= (code
== GE
? LT
: GE
);
11349 /* If testing for equality, we can take the NEG of the constant. */
11350 if (equality_comparison_p
11351 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11353 op0
= XEXP (op0
, 0);
11358 /* The remaining cases only apply to comparisons with zero. */
11362 /* When X is ABS or is known positive,
11363 (neg X) is < 0 if and only if X != 0. */
11365 if (sign_bit_comparison_p
11366 && (GET_CODE (XEXP (op0
, 0)) == ABS
11367 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11368 && (nonzero_bits (XEXP (op0
, 0), mode
)
11369 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11372 op0
= XEXP (op0
, 0);
11373 code
= (code
== LT
? NE
: EQ
);
11377 /* If we have NEG of something whose two high-order bits are the
11378 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11379 if (num_sign_bit_copies (op0
, mode
) >= 2)
11381 op0
= XEXP (op0
, 0);
11382 code
= swap_condition (code
);
11388 /* If we are testing equality and our count is a constant, we
11389 can perform the inverse operation on our RHS. */
11390 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11391 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11392 op1
, XEXP (op0
, 1))) != 0)
11394 op0
= XEXP (op0
, 0);
11399 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11400 a particular bit. Convert it to an AND of a constant of that
11401 bit. This will be converted into a ZERO_EXTRACT. */
11402 if (const_op
== 0 && sign_bit_comparison_p
11403 && CONST_INT_P (XEXP (op0
, 1))
11404 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11406 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11407 ((unsigned HOST_WIDE_INT
) 1
11409 - INTVAL (XEXP (op0
, 1)))));
11410 code
= (code
== LT
? NE
: EQ
);
11414 /* Fall through. */
11417 /* ABS is ignorable inside an equality comparison with zero. */
11418 if (const_op
== 0 && equality_comparison_p
)
11420 op0
= XEXP (op0
, 0);
11426 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11427 (compare FOO CONST) if CONST fits in FOO's mode and we
11428 are either testing inequality or have an unsigned
11429 comparison with ZERO_EXTEND or a signed comparison with
11430 SIGN_EXTEND. But don't do it if we don't have a compare
11431 insn of the given mode, since we'd have to revert it
11432 later on, and then we wouldn't know whether to sign- or
11434 mode
= GET_MODE (XEXP (op0
, 0));
11435 if (GET_MODE_CLASS (mode
) == MODE_INT
11436 && ! unsigned_comparison_p
11437 && HWI_COMPUTABLE_MODE_P (mode
)
11438 && trunc_int_for_mode (const_op
, mode
) == const_op
11439 && have_insn_for (COMPARE
, mode
))
11441 op0
= XEXP (op0
, 0);
11447 /* Check for the case where we are comparing A - C1 with C2, that is
11449 (subreg:MODE (plus (A) (-C1))) op (C2)
11451 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11452 comparison in the wider mode. One of the following two conditions
11453 must be true in order for this to be valid:
11455 1. The mode extension results in the same bit pattern being added
11456 on both sides and the comparison is equality or unsigned. As
11457 C2 has been truncated to fit in MODE, the pattern can only be
11460 2. The mode extension results in the sign bit being copied on
11463 The difficulty here is that we have predicates for A but not for
11464 (A - C1) so we need to check that C1 is within proper bounds so
11465 as to perturbate A as little as possible. */
11467 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11468 && subreg_lowpart_p (op0
)
11469 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11470 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11471 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11473 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11474 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11475 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11478 && (unsigned HOST_WIDE_INT
) c1
11479 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11480 && (equality_comparison_p
|| unsigned_comparison_p
)
11481 /* (A - C1) zero-extends if it is positive and sign-extends
11482 if it is negative, C2 both zero- and sign-extends. */
11483 && ((0 == (nonzero_bits (a
, inner_mode
)
11484 & ~GET_MODE_MASK (mode
))
11486 /* (A - C1) sign-extends if it is positive and 1-extends
11487 if it is negative, C2 both sign- and 1-extends. */
11488 || (num_sign_bit_copies (a
, inner_mode
)
11489 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11492 || ((unsigned HOST_WIDE_INT
) c1
11493 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11494 /* (A - C1) always sign-extends, like C2. */
11495 && num_sign_bit_copies (a
, inner_mode
)
11496 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11497 - (mode_width
- 1))))
11499 op0
= SUBREG_REG (op0
);
11504 /* If the inner mode is narrower and we are extracting the low part,
11505 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11506 if (subreg_lowpart_p (op0
)
11507 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11508 /* Fall through */ ;
11512 /* ... fall through ... */
11515 mode
= GET_MODE (XEXP (op0
, 0));
11516 if (GET_MODE_CLASS (mode
) == MODE_INT
11517 && (unsigned_comparison_p
|| equality_comparison_p
)
11518 && HWI_COMPUTABLE_MODE_P (mode
)
11519 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11521 && have_insn_for (COMPARE
, mode
))
11523 op0
= XEXP (op0
, 0);
11529 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11530 this for equality comparisons due to pathological cases involving
11532 if (equality_comparison_p
11533 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11534 op1
, XEXP (op0
, 1))))
11536 op0
= XEXP (op0
, 0);
11541 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11542 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11543 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11545 op0
= XEXP (XEXP (op0
, 0), 0);
11546 code
= (code
== LT
? EQ
: NE
);
11552 /* We used to optimize signed comparisons against zero, but that
11553 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11554 arrive here as equality comparisons, or (GEU, LTU) are
11555 optimized away. No need to special-case them. */
11557 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11558 (eq B (minus A C)), whichever simplifies. We can only do
11559 this for equality comparisons due to pathological cases involving
11561 if (equality_comparison_p
11562 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11563 XEXP (op0
, 1), op1
)))
11565 op0
= XEXP (op0
, 0);
11570 if (equality_comparison_p
11571 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11572 XEXP (op0
, 0), op1
)))
11574 op0
= XEXP (op0
, 1);
11579 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11580 of bits in X minus 1, is one iff X > 0. */
11581 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11582 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11583 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11584 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11586 op0
= XEXP (op0
, 1);
11587 code
= (code
== GE
? LE
: GT
);
11593 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11594 if C is zero or B is a constant. */
11595 if (equality_comparison_p
11596 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11597 XEXP (op0
, 1), op1
)))
11599 op0
= XEXP (op0
, 0);
11606 case UNEQ
: case LTGT
:
11607 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11608 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11609 case UNORDERED
: case ORDERED
:
11610 /* We can't do anything if OP0 is a condition code value, rather
11611 than an actual data value. */
11613 || CC0_P (XEXP (op0
, 0))
11614 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11617 /* Get the two operands being compared. */
11618 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11619 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11621 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11623 /* Check for the cases where we simply want the result of the
11624 earlier test or the opposite of that result. */
11625 if (code
== NE
|| code
== EQ
11626 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11627 && (code
== LT
|| code
== GE
)))
11629 enum rtx_code new_code
;
11630 if (code
== LT
|| code
== NE
)
11631 new_code
= GET_CODE (op0
);
11633 new_code
= reversed_comparison_code (op0
, NULL
);
11635 if (new_code
!= UNKNOWN
)
11646 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11648 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11649 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11650 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11652 op0
= XEXP (op0
, 1);
11653 code
= (code
== GE
? GT
: LE
);
11659 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11660 will be converted to a ZERO_EXTRACT later. */
11661 if (const_op
== 0 && equality_comparison_p
11662 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11663 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11665 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11666 XEXP (XEXP (op0
, 0), 1));
11667 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11671 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11672 zero and X is a comparison and C1 and C2 describe only bits set
11673 in STORE_FLAG_VALUE, we can compare with X. */
11674 if (const_op
== 0 && equality_comparison_p
11675 && mode_width
<= HOST_BITS_PER_WIDE_INT
11676 && CONST_INT_P (XEXP (op0
, 1))
11677 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11678 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11679 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11680 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11682 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11683 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11684 if ((~STORE_FLAG_VALUE
& mask
) == 0
11685 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11686 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11687 && COMPARISON_P (tem
))))
11689 op0
= XEXP (XEXP (op0
, 0), 0);
11694 /* If we are doing an equality comparison of an AND of a bit equal
11695 to the sign bit, replace this with a LT or GE comparison of
11696 the underlying value. */
11697 if (equality_comparison_p
11699 && CONST_INT_P (XEXP (op0
, 1))
11700 && mode_width
<= HOST_BITS_PER_WIDE_INT
11701 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11702 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11704 op0
= XEXP (op0
, 0);
11705 code
= (code
== EQ
? GE
: LT
);
11709 /* If this AND operation is really a ZERO_EXTEND from a narrower
11710 mode, the constant fits within that mode, and this is either an
11711 equality or unsigned comparison, try to do this comparison in
11716 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11717 -> (ne:DI (reg:SI 4) (const_int 0))
11719 unless TRULY_NOOP_TRUNCATION allows it or the register is
11720 known to hold a value of the required mode the
11721 transformation is invalid. */
11722 if ((equality_comparison_p
|| unsigned_comparison_p
)
11723 && CONST_INT_P (XEXP (op0
, 1))
11724 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11725 & GET_MODE_MASK (mode
))
11727 && const_op
>> i
== 0
11728 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11729 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11730 || (REG_P (XEXP (op0
, 0))
11731 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11733 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11737 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11738 fits in both M1 and M2 and the SUBREG is either paradoxical
11739 or represents the low part, permute the SUBREG and the AND
11741 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11743 unsigned HOST_WIDE_INT c1
;
11744 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11745 /* Require an integral mode, to avoid creating something like
11747 if (SCALAR_INT_MODE_P (tmode
)
11748 /* It is unsafe to commute the AND into the SUBREG if the
11749 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11750 not defined. As originally written the upper bits
11751 have a defined value due to the AND operation.
11752 However, if we commute the AND inside the SUBREG then
11753 they no longer have defined values and the meaning of
11754 the code has been changed. */
11756 #ifdef WORD_REGISTER_OPERATIONS
11757 || (mode_width
> GET_MODE_PRECISION (tmode
)
11758 && mode_width
<= BITS_PER_WORD
)
11760 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11761 && subreg_lowpart_p (XEXP (op0
, 0))))
11762 && CONST_INT_P (XEXP (op0
, 1))
11763 && mode_width
<= HOST_BITS_PER_WIDE_INT
11764 && HWI_COMPUTABLE_MODE_P (tmode
)
11765 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11766 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11768 && c1
!= GET_MODE_MASK (tmode
))
11770 op0
= simplify_gen_binary (AND
, tmode
,
11771 SUBREG_REG (XEXP (op0
, 0)),
11772 gen_int_mode (c1
, tmode
));
11773 op0
= gen_lowpart (mode
, op0
);
11778 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11779 if (const_op
== 0 && equality_comparison_p
11780 && XEXP (op0
, 1) == const1_rtx
11781 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11783 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11784 XEXP (XEXP (op0
, 0), 0), 1);
11785 code
= (code
== NE
? EQ
: NE
);
11789 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11790 (eq (and (lshiftrt X) 1) 0).
11791 Also handle the case where (not X) is expressed using xor. */
11792 if (const_op
== 0 && equality_comparison_p
11793 && XEXP (op0
, 1) == const1_rtx
11794 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11796 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11797 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11799 if (GET_CODE (shift_op
) == NOT
11800 || (GET_CODE (shift_op
) == XOR
11801 && CONST_INT_P (XEXP (shift_op
, 1))
11802 && CONST_INT_P (shift_count
)
11803 && HWI_COMPUTABLE_MODE_P (mode
)
11804 && (UINTVAL (XEXP (shift_op
, 1))
11805 == (unsigned HOST_WIDE_INT
) 1
11806 << INTVAL (shift_count
))))
11809 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11810 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11811 code
= (code
== NE
? EQ
: NE
);
11818 /* If we have (compare (ashift FOO N) (const_int C)) and
11819 the high order N bits of FOO (N+1 if an inequality comparison)
11820 are known to be zero, we can do this by comparing FOO with C
11821 shifted right N bits so long as the low-order N bits of C are
11823 if (CONST_INT_P (XEXP (op0
, 1))
11824 && INTVAL (XEXP (op0
, 1)) >= 0
11825 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11826 < HOST_BITS_PER_WIDE_INT
)
11827 && (((unsigned HOST_WIDE_INT
) const_op
11828 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11830 && mode_width
<= HOST_BITS_PER_WIDE_INT
11831 && (nonzero_bits (XEXP (op0
, 0), mode
)
11832 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11833 + ! equality_comparison_p
))) == 0)
11835 /* We must perform a logical shift, not an arithmetic one,
11836 as we want the top N bits of C to be zero. */
11837 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11839 temp
>>= INTVAL (XEXP (op0
, 1));
11840 op1
= gen_int_mode (temp
, mode
);
11841 op0
= XEXP (op0
, 0);
11845 /* If we are doing a sign bit comparison, it means we are testing
11846 a particular bit. Convert it to the appropriate AND. */
11847 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11848 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11850 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11851 ((unsigned HOST_WIDE_INT
) 1
11853 - INTVAL (XEXP (op0
, 1)))));
11854 code
= (code
== LT
? NE
: EQ
);
11858 /* If this an equality comparison with zero and we are shifting
11859 the low bit to the sign bit, we can convert this to an AND of the
11861 if (const_op
== 0 && equality_comparison_p
11862 && CONST_INT_P (XEXP (op0
, 1))
11863 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11865 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11871 /* If this is an equality comparison with zero, we can do this
11872 as a logical shift, which might be much simpler. */
11873 if (equality_comparison_p
&& const_op
== 0
11874 && CONST_INT_P (XEXP (op0
, 1)))
11876 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11878 INTVAL (XEXP (op0
, 1)));
11882 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11883 do the comparison in a narrower mode. */
11884 if (! unsigned_comparison_p
11885 && CONST_INT_P (XEXP (op0
, 1))
11886 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11887 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11888 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11889 MODE_INT
, 1)) != BLKmode
11890 && (((unsigned HOST_WIDE_INT
) const_op
11891 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11892 <= GET_MODE_MASK (tmode
)))
11894 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11898 /* Likewise if OP0 is a PLUS of a sign extension with a
11899 constant, which is usually represented with the PLUS
11900 between the shifts. */
11901 if (! unsigned_comparison_p
11902 && CONST_INT_P (XEXP (op0
, 1))
11903 && GET_CODE (XEXP (op0
, 0)) == PLUS
11904 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11905 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11906 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11907 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11908 MODE_INT
, 1)) != BLKmode
11909 && (((unsigned HOST_WIDE_INT
) const_op
11910 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11911 <= GET_MODE_MASK (tmode
)))
11913 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11914 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11915 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11916 add_const
, XEXP (op0
, 1));
11918 op0
= simplify_gen_binary (PLUS
, tmode
,
11919 gen_lowpart (tmode
, inner
),
11924 /* ... fall through ... */
11926 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11927 the low order N bits of FOO are known to be zero, we can do this
11928 by comparing FOO with C shifted left N bits so long as no
11929 overflow occurs. Even if the low order N bits of FOO aren't known
11930 to be zero, if the comparison is >= or < we can use the same
11931 optimization and for > or <= by setting all the low
11932 order N bits in the comparison constant. */
11933 if (CONST_INT_P (XEXP (op0
, 1))
11934 && INTVAL (XEXP (op0
, 1)) > 0
11935 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11936 && mode_width
<= HOST_BITS_PER_WIDE_INT
11937 && (((unsigned HOST_WIDE_INT
) const_op
11938 + (GET_CODE (op0
) != LSHIFTRT
11939 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11942 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11944 unsigned HOST_WIDE_INT low_bits
11945 = (nonzero_bits (XEXP (op0
, 0), mode
)
11946 & (((unsigned HOST_WIDE_INT
) 1
11947 << INTVAL (XEXP (op0
, 1))) - 1));
11948 if (low_bits
== 0 || !equality_comparison_p
)
11950 /* If the shift was logical, then we must make the condition
11952 if (GET_CODE (op0
) == LSHIFTRT
)
11953 code
= unsigned_condition (code
);
11955 const_op
<<= INTVAL (XEXP (op0
, 1));
11957 && (code
== GT
|| code
== GTU
11958 || code
== LE
|| code
== LEU
))
11960 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11961 op1
= GEN_INT (const_op
);
11962 op0
= XEXP (op0
, 0);
11967 /* If we are using this shift to extract just the sign bit, we
11968 can replace this with an LT or GE comparison. */
11970 && (equality_comparison_p
|| sign_bit_comparison_p
)
11971 && CONST_INT_P (XEXP (op0
, 1))
11972 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11974 op0
= XEXP (op0
, 0);
11975 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11987 /* Now make any compound operations involved in this comparison. Then,
11988 check for an outmost SUBREG on OP0 that is not doing anything or is
11989 paradoxical. The latter transformation must only be performed when
11990 it is known that the "extra" bits will be the same in op0 and op1 or
11991 that they don't matter. There are three cases to consider:
11993 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11994 care bits and we can assume they have any convenient value. So
11995 making the transformation is safe.
11997 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11998 In this case the upper bits of op0 are undefined. We should not make
11999 the simplification in that case as we do not know the contents of
12002 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12003 UNKNOWN. In that case we know those bits are zeros or ones. We must
12004 also be sure that they are the same as the upper bits of op1.
12006 We can never remove a SUBREG for a non-equality comparison because
12007 the sign bit is in a different place in the underlying object. */
12009 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12010 op1
= make_compound_operation (op1
, SET
);
12012 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12013 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12014 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12015 && (code
== NE
|| code
== EQ
))
12017 if (paradoxical_subreg_p (op0
))
12019 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12021 if (REG_P (SUBREG_REG (op0
)))
12023 op0
= SUBREG_REG (op0
);
12024 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12027 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12028 <= HOST_BITS_PER_WIDE_INT
)
12029 && (nonzero_bits (SUBREG_REG (op0
),
12030 GET_MODE (SUBREG_REG (op0
)))
12031 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12033 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12035 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12036 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12037 op0
= SUBREG_REG (op0
), op1
= tem
;
12041 /* We now do the opposite procedure: Some machines don't have compare
12042 insns in all modes. If OP0's mode is an integer mode smaller than a
12043 word and we can't do a compare in that mode, see if there is a larger
12044 mode for which we can do the compare. There are a number of cases in
12045 which we can use the wider mode. */
12047 mode
= GET_MODE (op0
);
12048 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12049 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12050 && ! have_insn_for (COMPARE
, mode
))
12051 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12052 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12053 tmode
= GET_MODE_WIDER_MODE (tmode
))
12054 if (have_insn_for (COMPARE
, tmode
))
12058 /* If this is a test for negative, we can make an explicit
12059 test of the sign bit. Test this first so we can use
12060 a paradoxical subreg to extend OP0. */
12062 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12063 && HWI_COMPUTABLE_MODE_P (mode
))
12065 op0
= simplify_gen_binary (AND
, tmode
,
12066 gen_lowpart (tmode
, op0
),
12067 GEN_INT ((unsigned HOST_WIDE_INT
) 1
12068 << (GET_MODE_BITSIZE (mode
)
12070 code
= (code
== LT
) ? NE
: EQ
;
12074 /* If the only nonzero bits in OP0 and OP1 are those in the
12075 narrower mode and this is an equality or unsigned comparison,
12076 we can use the wider mode. Similarly for sign-extended
12077 values, in which case it is true for all comparisons. */
12078 zero_extended
= ((code
== EQ
|| code
== NE
12079 || code
== GEU
|| code
== GTU
12080 || code
== LEU
|| code
== LTU
)
12081 && (nonzero_bits (op0
, tmode
)
12082 & ~GET_MODE_MASK (mode
)) == 0
12083 && ((CONST_INT_P (op1
)
12084 || (nonzero_bits (op1
, tmode
)
12085 & ~GET_MODE_MASK (mode
)) == 0)));
12088 || ((num_sign_bit_copies (op0
, tmode
)
12089 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12090 - GET_MODE_PRECISION (mode
)))
12091 && (num_sign_bit_copies (op1
, tmode
)
12092 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12093 - GET_MODE_PRECISION (mode
)))))
12095 /* If OP0 is an AND and we don't have an AND in MODE either,
12096 make a new AND in the proper mode. */
12097 if (GET_CODE (op0
) == AND
12098 && !have_insn_for (AND
, mode
))
12099 op0
= simplify_gen_binary (AND
, tmode
,
12100 gen_lowpart (tmode
,
12102 gen_lowpart (tmode
,
12108 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12109 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12113 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12114 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12121 #ifdef CANONICALIZE_COMPARISON
12122 /* If this machine only supports a subset of valid comparisons, see if we
12123 can convert an unsupported one into a supported one. */
12124 CANONICALIZE_COMPARISON (code
, op0
, op1
);
12133 /* Utility function for record_value_for_reg. Count number of
12138 enum rtx_code code
= GET_CODE (x
);
12142 if (GET_RTX_CLASS (code
) == '2'
12143 || GET_RTX_CLASS (code
) == 'c')
12145 rtx x0
= XEXP (x
, 0);
12146 rtx x1
= XEXP (x
, 1);
12149 return 1 + 2 * count_rtxs (x0
);
12151 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
12152 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
12153 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12154 return 2 + 2 * count_rtxs (x0
)
12155 + count_rtxs (x
== XEXP (x1
, 0)
12156 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12158 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
12159 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
12160 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12161 return 2 + 2 * count_rtxs (x1
)
12162 + count_rtxs (x
== XEXP (x0
, 0)
12163 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12166 fmt
= GET_RTX_FORMAT (code
);
12167 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12169 ret
+= count_rtxs (XEXP (x
, i
));
12170 else if (fmt
[i
] == 'E')
12171 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12172 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12177 /* Utility function for following routine. Called when X is part of a value
12178 being stored into last_set_value. Sets last_set_table_tick
12179 for each register mentioned. Similar to mention_regs in cse.c */
12182 update_table_tick (rtx x
)
12184 enum rtx_code code
= GET_CODE (x
);
12185 const char *fmt
= GET_RTX_FORMAT (code
);
12190 unsigned int regno
= REGNO (x
);
12191 unsigned int endregno
= END_REGNO (x
);
12194 for (r
= regno
; r
< endregno
; r
++)
12196 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12197 rsp
->last_set_table_tick
= label_tick
;
12203 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12206 /* Check for identical subexpressions. If x contains
12207 identical subexpression we only have to traverse one of
12209 if (i
== 0 && ARITHMETIC_P (x
))
12211 /* Note that at this point x1 has already been
12213 rtx x0
= XEXP (x
, 0);
12214 rtx x1
= XEXP (x
, 1);
12216 /* If x0 and x1 are identical then there is no need to
12221 /* If x0 is identical to a subexpression of x1 then while
12222 processing x1, x0 has already been processed. Thus we
12223 are done with x. */
12224 if (ARITHMETIC_P (x1
)
12225 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12228 /* If x1 is identical to a subexpression of x0 then we
12229 still have to process the rest of x0. */
12230 if (ARITHMETIC_P (x0
)
12231 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12233 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12238 update_table_tick (XEXP (x
, i
));
12240 else if (fmt
[i
] == 'E')
12241 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12242 update_table_tick (XVECEXP (x
, i
, j
));
12245 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12246 are saying that the register is clobbered and we no longer know its
12247 value. If INSN is zero, don't update reg_stat[].last_set; this is
12248 only permitted with VALUE also zero and is used to invalidate the
12252 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12254 unsigned int regno
= REGNO (reg
);
12255 unsigned int endregno
= END_REGNO (reg
);
12257 reg_stat_type
*rsp
;
12259 /* If VALUE contains REG and we have a previous value for REG, substitute
12260 the previous value. */
12261 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12265 /* Set things up so get_last_value is allowed to see anything set up to
12267 subst_low_luid
= DF_INSN_LUID (insn
);
12268 tem
= get_last_value (reg
);
12270 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12271 it isn't going to be useful and will take a lot of time to process,
12272 so just use the CLOBBER. */
12276 if (ARITHMETIC_P (tem
)
12277 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12278 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12279 tem
= XEXP (tem
, 0);
12280 else if (count_occurrences (value
, reg
, 1) >= 2)
12282 /* If there are two or more occurrences of REG in VALUE,
12283 prevent the value from growing too much. */
12284 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12285 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12288 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12292 /* For each register modified, show we don't know its value, that
12293 we don't know about its bitwise content, that its value has been
12294 updated, and that we don't know the location of the death of the
12296 for (i
= regno
; i
< endregno
; i
++)
12298 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12301 rsp
->last_set
= insn
;
12303 rsp
->last_set_value
= 0;
12304 rsp
->last_set_mode
= VOIDmode
;
12305 rsp
->last_set_nonzero_bits
= 0;
12306 rsp
->last_set_sign_bit_copies
= 0;
12307 rsp
->last_death
= 0;
12308 rsp
->truncated_to_mode
= VOIDmode
;
12311 /* Mark registers that are being referenced in this value. */
12313 update_table_tick (value
);
12315 /* Now update the status of each register being set.
12316 If someone is using this register in this block, set this register
12317 to invalid since we will get confused between the two lives in this
12318 basic block. This makes using this register always invalid. In cse, we
12319 scan the table to invalidate all entries using this register, but this
12320 is too much work for us. */
12322 for (i
= regno
; i
< endregno
; i
++)
12324 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12325 rsp
->last_set_label
= label_tick
;
12327 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12328 rsp
->last_set_invalid
= 1;
12330 rsp
->last_set_invalid
= 0;
12333 /* The value being assigned might refer to X (like in "x++;"). In that
12334 case, we must replace it with (clobber (const_int 0)) to prevent
12336 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12337 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12339 value
= copy_rtx (value
);
12340 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12344 /* For the main register being modified, update the value, the mode, the
12345 nonzero bits, and the number of sign bit copies. */
12347 rsp
->last_set_value
= value
;
12351 enum machine_mode mode
= GET_MODE (reg
);
12352 subst_low_luid
= DF_INSN_LUID (insn
);
12353 rsp
->last_set_mode
= mode
;
12354 if (GET_MODE_CLASS (mode
) == MODE_INT
12355 && HWI_COMPUTABLE_MODE_P (mode
))
12356 mode
= nonzero_bits_mode
;
12357 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12358 rsp
->last_set_sign_bit_copies
12359 = num_sign_bit_copies (value
, GET_MODE (reg
));
12363 /* Called via note_stores from record_dead_and_set_regs to handle one
12364 SET or CLOBBER in an insn. DATA is the instruction in which the
12365 set is occurring. */
12368 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12370 rtx record_dead_insn
= (rtx
) data
;
12372 if (GET_CODE (dest
) == SUBREG
)
12373 dest
= SUBREG_REG (dest
);
12375 if (!record_dead_insn
)
12378 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12384 /* If we are setting the whole register, we know its value. Otherwise
12385 show that we don't know the value. We can handle SUBREG in
12387 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12388 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12389 else if (GET_CODE (setter
) == SET
12390 && GET_CODE (SET_DEST (setter
)) == SUBREG
12391 && SUBREG_REG (SET_DEST (setter
)) == dest
12392 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12393 && subreg_lowpart_p (SET_DEST (setter
)))
12394 record_value_for_reg (dest
, record_dead_insn
,
12395 gen_lowpart (GET_MODE (dest
),
12396 SET_SRC (setter
)));
12398 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12400 else if (MEM_P (dest
)
12401 /* Ignore pushes, they clobber nothing. */
12402 && ! push_operand (dest
, GET_MODE (dest
)))
12403 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12406 /* Update the records of when each REG was most recently set or killed
12407 for the things done by INSN. This is the last thing done in processing
12408 INSN in the combiner loop.
12410 We update reg_stat[], in particular fields last_set, last_set_value,
12411 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12412 last_death, and also the similar information mem_last_set (which insn
12413 most recently modified memory) and last_call_luid (which insn was the
12414 most recent subroutine call). */
12417 record_dead_and_set_regs (rtx insn
)
12422 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12424 if (REG_NOTE_KIND (link
) == REG_DEAD
12425 && REG_P (XEXP (link
, 0)))
12427 unsigned int regno
= REGNO (XEXP (link
, 0));
12428 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12430 for (i
= regno
; i
< endregno
; i
++)
12432 reg_stat_type
*rsp
;
12434 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12435 rsp
->last_death
= insn
;
12438 else if (REG_NOTE_KIND (link
) == REG_INC
)
12439 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12444 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12445 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12447 reg_stat_type
*rsp
;
12449 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12450 rsp
->last_set_invalid
= 1;
12451 rsp
->last_set
= insn
;
12452 rsp
->last_set_value
= 0;
12453 rsp
->last_set_mode
= VOIDmode
;
12454 rsp
->last_set_nonzero_bits
= 0;
12455 rsp
->last_set_sign_bit_copies
= 0;
12456 rsp
->last_death
= 0;
12457 rsp
->truncated_to_mode
= VOIDmode
;
12460 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12462 /* We can't combine into a call pattern. Remember, though, that
12463 the return value register is set at this LUID. We could
12464 still replace a register with the return value from the
12465 wrong subroutine call! */
12466 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12469 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12472 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12473 register present in the SUBREG, so for each such SUBREG go back and
12474 adjust nonzero and sign bit information of the registers that are
12475 known to have some zero/sign bits set.
12477 This is needed because when combine blows the SUBREGs away, the
12478 information on zero/sign bits is lost and further combines can be
12479 missed because of that. */
12482 record_promoted_value (rtx insn
, rtx subreg
)
12484 struct insn_link
*links
;
12486 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12487 enum machine_mode mode
= GET_MODE (subreg
);
12489 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12492 for (links
= LOG_LINKS (insn
); links
;)
12494 reg_stat_type
*rsp
;
12496 insn
= links
->insn
;
12497 set
= single_set (insn
);
12499 if (! set
|| !REG_P (SET_DEST (set
))
12500 || REGNO (SET_DEST (set
)) != regno
12501 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12503 links
= links
->next
;
12507 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12508 if (rsp
->last_set
== insn
)
12510 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12511 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12514 if (REG_P (SET_SRC (set
)))
12516 regno
= REGNO (SET_SRC (set
));
12517 links
= LOG_LINKS (insn
);
12524 /* Check if X, a register, is known to contain a value already
12525 truncated to MODE. In this case we can use a subreg to refer to
12526 the truncated value even though in the generic case we would need
12527 an explicit truncation. */
12530 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12532 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12533 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12536 || rsp
->truncation_label
< label_tick_ebb_start
)
12538 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12540 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12545 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12546 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12547 might be able to turn a truncate into a subreg using this information.
12548 Return -1 if traversing *P is complete or 0 otherwise. */
12551 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12554 enum machine_mode truncated_mode
;
12555 reg_stat_type
*rsp
;
12557 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12559 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12560 truncated_mode
= GET_MODE (x
);
12562 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12565 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12568 x
= SUBREG_REG (x
);
12570 /* ??? For hard-regs we now record everything. We might be able to
12571 optimize this using last_set_mode. */
12572 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12573 truncated_mode
= GET_MODE (x
);
12577 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12578 if (rsp
->truncated_to_mode
== 0
12579 || rsp
->truncation_label
< label_tick_ebb_start
12580 || (GET_MODE_SIZE (truncated_mode
)
12581 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12583 rsp
->truncated_to_mode
= truncated_mode
;
12584 rsp
->truncation_label
= label_tick
;
12590 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12591 the modes they are used in. This can help truning TRUNCATEs into
12595 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12597 for_each_rtx (x
, record_truncated_value
, NULL
);
12600 /* Scan X for promoted SUBREGs. For each one found,
12601 note what it implies to the registers used in it. */
12604 check_promoted_subreg (rtx insn
, rtx x
)
12606 if (GET_CODE (x
) == SUBREG
12607 && SUBREG_PROMOTED_VAR_P (x
)
12608 && REG_P (SUBREG_REG (x
)))
12609 record_promoted_value (insn
, x
);
12612 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12615 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12619 check_promoted_subreg (insn
, XEXP (x
, i
));
12623 if (XVEC (x
, i
) != 0)
12624 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12625 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12631 /* Verify that all the registers and memory references mentioned in *LOC are
12632 still valid. *LOC was part of a value set in INSN when label_tick was
12633 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12634 the invalid references with (clobber (const_int 0)) and return 1. This
12635 replacement is useful because we often can get useful information about
12636 the form of a value (e.g., if it was produced by a shift that always
12637 produces -1 or 0) even though we don't know exactly what registers it
12638 was produced from. */
12641 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12644 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12645 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12650 unsigned int regno
= REGNO (x
);
12651 unsigned int endregno
= END_REGNO (x
);
12654 for (j
= regno
; j
< endregno
; j
++)
12656 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12657 if (rsp
->last_set_invalid
12658 /* If this is a pseudo-register that was only set once and not
12659 live at the beginning of the function, it is always valid. */
12660 || (! (regno
>= FIRST_PSEUDO_REGISTER
12661 && REG_N_SETS (regno
) == 1
12662 && (!REGNO_REG_SET_P
12663 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12664 && rsp
->last_set_label
> tick
))
12667 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12674 /* If this is a memory reference, make sure that there were no stores after
12675 it that might have clobbered the value. We don't have alias info, so we
12676 assume any store invalidates it. Moreover, we only have local UIDs, so
12677 we also assume that there were stores in the intervening basic blocks. */
12678 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12679 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12682 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12686 for (i
= 0; i
< len
; i
++)
12690 /* Check for identical subexpressions. If x contains
12691 identical subexpression we only have to traverse one of
12693 if (i
== 1 && ARITHMETIC_P (x
))
12695 /* Note that at this point x0 has already been checked
12696 and found valid. */
12697 rtx x0
= XEXP (x
, 0);
12698 rtx x1
= XEXP (x
, 1);
12700 /* If x0 and x1 are identical then x is also valid. */
12704 /* If x1 is identical to a subexpression of x0 then
12705 while checking x0, x1 has already been checked. Thus
12706 it is valid and so as x. */
12707 if (ARITHMETIC_P (x0
)
12708 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12711 /* If x0 is identical to a subexpression of x1 then x is
12712 valid iff the rest of x1 is valid. */
12713 if (ARITHMETIC_P (x1
)
12714 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12716 get_last_value_validate (&XEXP (x1
,
12717 x0
== XEXP (x1
, 0) ? 1 : 0),
12718 insn
, tick
, replace
);
12721 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12725 else if (fmt
[i
] == 'E')
12726 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12727 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12728 insn
, tick
, replace
) == 0)
12732 /* If we haven't found a reason for it to be invalid, it is valid. */
12736 /* Get the last value assigned to X, if known. Some registers
12737 in the value may be replaced with (clobber (const_int 0)) if their value
12738 is known longer known reliably. */
12741 get_last_value (const_rtx x
)
12743 unsigned int regno
;
12745 reg_stat_type
*rsp
;
12747 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12748 then convert it to the desired mode. If this is a paradoxical SUBREG,
12749 we cannot predict what values the "extra" bits might have. */
12750 if (GET_CODE (x
) == SUBREG
12751 && subreg_lowpart_p (x
)
12752 && !paradoxical_subreg_p (x
)
12753 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12754 return gen_lowpart (GET_MODE (x
), value
);
12760 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12761 value
= rsp
->last_set_value
;
12763 /* If we don't have a value, or if it isn't for this basic block and
12764 it's either a hard register, set more than once, or it's a live
12765 at the beginning of the function, return 0.
12767 Because if it's not live at the beginning of the function then the reg
12768 is always set before being used (is never used without being set).
12769 And, if it's set only once, and it's always set before use, then all
12770 uses must have the same last value, even if it's not from this basic
12774 || (rsp
->last_set_label
< label_tick_ebb_start
12775 && (regno
< FIRST_PSEUDO_REGISTER
12776 || REG_N_SETS (regno
) != 1
12778 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12781 /* If the value was set in a later insn than the ones we are processing,
12782 we can't use it even if the register was only set once. */
12783 if (rsp
->last_set_label
== label_tick
12784 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12787 /* If the value has all its registers valid, return it. */
12788 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12791 /* Otherwise, make a copy and replace any invalid register with
12792 (clobber (const_int 0)). If that fails for some reason, return 0. */
12794 value
= copy_rtx (value
);
12795 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12801 /* Return nonzero if expression X refers to a REG or to memory
12802 that is set in an instruction more recent than FROM_LUID. */
12805 use_crosses_set_p (const_rtx x
, int from_luid
)
12809 enum rtx_code code
= GET_CODE (x
);
12813 unsigned int regno
= REGNO (x
);
12814 unsigned endreg
= END_REGNO (x
);
12816 #ifdef PUSH_ROUNDING
12817 /* Don't allow uses of the stack pointer to be moved,
12818 because we don't know whether the move crosses a push insn. */
12819 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12822 for (; regno
< endreg
; regno
++)
12824 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12826 && rsp
->last_set_label
== label_tick
12827 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12833 if (code
== MEM
&& mem_last_set
> from_luid
)
12836 fmt
= GET_RTX_FORMAT (code
);
12838 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12843 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12844 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12847 else if (fmt
[i
] == 'e'
12848 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12854 /* Define three variables used for communication between the following
12857 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12858 static int reg_dead_flag
;
12860 /* Function called via note_stores from reg_dead_at_p.
12862 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12863 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12866 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12868 unsigned int regno
, endregno
;
12873 regno
= REGNO (dest
);
12874 endregno
= END_REGNO (dest
);
12875 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12876 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12879 /* Return nonzero if REG is known to be dead at INSN.
12881 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12882 referencing REG, it is dead. If we hit a SET referencing REG, it is
12883 live. Otherwise, see if it is live or dead at the start of the basic
12884 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12885 must be assumed to be always live. */
12888 reg_dead_at_p (rtx reg
, rtx insn
)
12893 /* Set variables for reg_dead_at_p_1. */
12894 reg_dead_regno
= REGNO (reg
);
12895 reg_dead_endregno
= END_REGNO (reg
);
12899 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12900 we allow the machine description to decide whether use-and-clobber
12901 patterns are OK. */
12902 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12904 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12905 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12909 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12910 beginning of basic block. */
12911 block
= BLOCK_FOR_INSN (insn
);
12916 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12918 return reg_dead_flag
== 1 ? 1 : 0;
12920 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12924 if (insn
== BB_HEAD (block
))
12927 insn
= PREV_INSN (insn
);
12930 /* Look at live-in sets for the basic block that we were in. */
12931 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12932 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12938 /* Note hard registers in X that are used. */
12941 mark_used_regs_combine (rtx x
)
12943 RTX_CODE code
= GET_CODE (x
);
12944 unsigned int regno
;
12957 case ADDR_DIFF_VEC
:
12960 /* CC0 must die in the insn after it is set, so we don't need to take
12961 special note of it here. */
12967 /* If we are clobbering a MEM, mark any hard registers inside the
12968 address as used. */
12969 if (MEM_P (XEXP (x
, 0)))
12970 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12975 /* A hard reg in a wide mode may really be multiple registers.
12976 If so, mark all of them just like the first. */
12977 if (regno
< FIRST_PSEUDO_REGISTER
)
12979 /* None of this applies to the stack, frame or arg pointers. */
12980 if (regno
== STACK_POINTER_REGNUM
12981 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12982 || regno
== HARD_FRAME_POINTER_REGNUM
12984 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12985 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12987 || regno
== FRAME_POINTER_REGNUM
)
12990 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12996 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12998 rtx testreg
= SET_DEST (x
);
13000 while (GET_CODE (testreg
) == SUBREG
13001 || GET_CODE (testreg
) == ZERO_EXTRACT
13002 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13003 testreg
= XEXP (testreg
, 0);
13005 if (MEM_P (testreg
))
13006 mark_used_regs_combine (XEXP (testreg
, 0));
13008 mark_used_regs_combine (SET_SRC (x
));
13016 /* Recursively scan the operands of this expression. */
13019 const char *fmt
= GET_RTX_FORMAT (code
);
13021 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13024 mark_used_regs_combine (XEXP (x
, i
));
13025 else if (fmt
[i
] == 'E')
13029 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13030 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13036 /* Remove register number REGNO from the dead registers list of INSN.
13038 Return the note used to record the death, if there was one. */
13041 remove_death (unsigned int regno
, rtx insn
)
13043 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13046 remove_note (insn
, note
);
13051 /* For each register (hardware or pseudo) used within expression X, if its
13052 death is in an instruction with luid between FROM_LUID (inclusive) and
13053 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13054 list headed by PNOTES.
13056 That said, don't move registers killed by maybe_kill_insn.
13058 This is done when X is being merged by combination into TO_INSN. These
13059 notes will then be distributed as needed. */
13062 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
13067 enum rtx_code code
= GET_CODE (x
);
13071 unsigned int regno
= REGNO (x
);
13072 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
13074 /* Don't move the register if it gets killed in between from and to. */
13075 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13076 && ! reg_referenced_p (x
, maybe_kill_insn
))
13080 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13081 && DF_INSN_LUID (where_dead
) >= from_luid
13082 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13084 rtx note
= remove_death (regno
, where_dead
);
13086 /* It is possible for the call above to return 0. This can occur
13087 when last_death points to I2 or I1 that we combined with.
13088 In that case make a new note.
13090 We must also check for the case where X is a hard register
13091 and NOTE is a death note for a range of hard registers
13092 including X. In that case, we must put REG_DEAD notes for
13093 the remaining registers in place of NOTE. */
13095 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13096 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13097 > GET_MODE_SIZE (GET_MODE (x
))))
13099 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13100 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13101 unsigned int ourend
= END_HARD_REGNO (x
);
13104 for (i
= deadregno
; i
< deadend
; i
++)
13105 if (i
< regno
|| i
>= ourend
)
13106 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13109 /* If we didn't find any note, or if we found a REG_DEAD note that
13110 covers only part of the given reg, and we have a multi-reg hard
13111 register, then to be safe we must check for REG_DEAD notes
13112 for each register other than the first. They could have
13113 their own REG_DEAD notes lying around. */
13114 else if ((note
== 0
13116 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13117 < GET_MODE_SIZE (GET_MODE (x
)))))
13118 && regno
< FIRST_PSEUDO_REGISTER
13119 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13121 unsigned int ourend
= END_HARD_REGNO (x
);
13122 unsigned int i
, offset
;
13126 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13130 for (i
= regno
+ offset
; i
< ourend
; i
++)
13131 move_deaths (regno_reg_rtx
[i
],
13132 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13135 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13137 XEXP (note
, 1) = *pnotes
;
13141 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13147 else if (GET_CODE (x
) == SET
)
13149 rtx dest
= SET_DEST (x
);
13151 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13153 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13154 that accesses one word of a multi-word item, some
13155 piece of everything register in the expression is used by
13156 this insn, so remove any old death. */
13157 /* ??? So why do we test for equality of the sizes? */
13159 if (GET_CODE (dest
) == ZERO_EXTRACT
13160 || GET_CODE (dest
) == STRICT_LOW_PART
13161 || (GET_CODE (dest
) == SUBREG
13162 && (((GET_MODE_SIZE (GET_MODE (dest
))
13163 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13164 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13165 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13167 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13171 /* If this is some other SUBREG, we know it replaces the entire
13172 value, so use that as the destination. */
13173 if (GET_CODE (dest
) == SUBREG
)
13174 dest
= SUBREG_REG (dest
);
13176 /* If this is a MEM, adjust deaths of anything used in the address.
13177 For a REG (the only other possibility), the entire value is
13178 being replaced so the old value is not used in this insn. */
13181 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13186 else if (GET_CODE (x
) == CLOBBER
)
13189 len
= GET_RTX_LENGTH (code
);
13190 fmt
= GET_RTX_FORMAT (code
);
13192 for (i
= 0; i
< len
; i
++)
13197 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13198 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13201 else if (fmt
[i
] == 'e')
13202 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13206 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13207 pattern of an insn. X must be a REG. */
13210 reg_bitfield_target_p (rtx x
, rtx body
)
13214 if (GET_CODE (body
) == SET
)
13216 rtx dest
= SET_DEST (body
);
13218 unsigned int regno
, tregno
, endregno
, endtregno
;
13220 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13221 target
= XEXP (dest
, 0);
13222 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13223 target
= SUBREG_REG (XEXP (dest
, 0));
13227 if (GET_CODE (target
) == SUBREG
)
13228 target
= SUBREG_REG (target
);
13230 if (!REG_P (target
))
13233 tregno
= REGNO (target
), regno
= REGNO (x
);
13234 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13235 return target
== x
;
13237 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13238 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13240 return endregno
> tregno
&& regno
< endtregno
;
13243 else if (GET_CODE (body
) == PARALLEL
)
13244 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13245 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13251 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13252 as appropriate. I3 and I2 are the insns resulting from the combination
13253 insns including FROM (I2 may be zero).
13255 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13256 not need REG_DEAD notes because they are being substituted for. This
13257 saves searching in the most common cases.
13259 Each note in the list is either ignored or placed on some insns, depending
13260 on the type of note. */
13263 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13264 rtx elim_i1
, rtx elim_i0
)
13266 rtx note
, next_note
;
13269 for (note
= notes
; note
; note
= next_note
)
13271 rtx place
= 0, place2
= 0;
13273 next_note
= XEXP (note
, 1);
13274 switch (REG_NOTE_KIND (note
))
13278 /* Doesn't matter much where we put this, as long as it's somewhere.
13279 It is preferable to keep these notes on branches, which is most
13280 likely to be i3. */
13284 case REG_NON_LOCAL_GOTO
:
13289 gcc_assert (i2
&& JUMP_P (i2
));
13294 case REG_EH_REGION
:
13295 /* These notes must remain with the call or trapping instruction. */
13298 else if (i2
&& CALL_P (i2
))
13302 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13303 if (may_trap_p (i3
))
13305 else if (i2
&& may_trap_p (i2
))
13307 /* ??? Otherwise assume we've combined things such that we
13308 can now prove that the instructions can't trap. Drop the
13309 note in this case. */
13313 case REG_ARGS_SIZE
:
13314 /* ??? How to distribute between i3-i1. Assume i3 contains the
13315 entire adjustment. Assert i3 contains at least some adjust. */
13316 if (!noop_move_p (i3
))
13318 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13319 /* fixup_args_size_notes looks at REG_NORETURN note,
13320 so ensure the note is placed there first. */
13324 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13325 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13329 XEXP (n
, 1) = REG_NOTES (i3
);
13330 REG_NOTES (i3
) = n
;
13334 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13335 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13336 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13337 gcc_assert (old_size
!= args_size
13339 && !ACCUMULATE_OUTGOING_ARGS
13340 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13347 /* These notes must remain with the call. It should not be
13348 possible for both I2 and I3 to be a call. */
13353 gcc_assert (i2
&& CALL_P (i2
));
13359 /* Any clobbers for i3 may still exist, and so we must process
13360 REG_UNUSED notes from that insn.
13362 Any clobbers from i2 or i1 can only exist if they were added by
13363 recog_for_combine. In that case, recog_for_combine created the
13364 necessary REG_UNUSED notes. Trying to keep any original
13365 REG_UNUSED notes from these insns can cause incorrect output
13366 if it is for the same register as the original i3 dest.
13367 In that case, we will notice that the register is set in i3,
13368 and then add a REG_UNUSED note for the destination of i3, which
13369 is wrong. However, it is possible to have REG_UNUSED notes from
13370 i2 or i1 for register which were both used and clobbered, so
13371 we keep notes from i2 or i1 if they will turn into REG_DEAD
13374 /* If this register is set or clobbered in I3, put the note there
13375 unless there is one already. */
13376 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13378 if (from_insn
!= i3
)
13381 if (! (REG_P (XEXP (note
, 0))
13382 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13383 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13386 /* Otherwise, if this register is used by I3, then this register
13387 now dies here, so we must put a REG_DEAD note here unless there
13389 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13390 && ! (REG_P (XEXP (note
, 0))
13391 ? find_regno_note (i3
, REG_DEAD
,
13392 REGNO (XEXP (note
, 0)))
13393 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13395 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13403 /* These notes say something about results of an insn. We can
13404 only support them if they used to be on I3 in which case they
13405 remain on I3. Otherwise they are ignored.
13407 If the note refers to an expression that is not a constant, we
13408 must also ignore the note since we cannot tell whether the
13409 equivalence is still true. It might be possible to do
13410 slightly better than this (we only have a problem if I2DEST
13411 or I1DEST is present in the expression), but it doesn't
13412 seem worth the trouble. */
13414 if (from_insn
== i3
13415 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13420 /* These notes say something about how a register is used. They must
13421 be present on any use of the register in I2 or I3. */
13422 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13425 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13434 case REG_LABEL_TARGET
:
13435 case REG_LABEL_OPERAND
:
13436 /* This can show up in several ways -- either directly in the
13437 pattern, or hidden off in the constant pool with (or without?)
13438 a REG_EQUAL note. */
13439 /* ??? Ignore the without-reg_equal-note problem for now. */
13440 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13441 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13442 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13443 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13447 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13448 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13449 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13450 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13458 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13459 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13461 if (place
&& JUMP_P (place
)
13462 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13463 && (JUMP_LABEL (place
) == NULL
13464 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13466 rtx label
= JUMP_LABEL (place
);
13469 JUMP_LABEL (place
) = XEXP (note
, 0);
13470 else if (LABEL_P (label
))
13471 LABEL_NUSES (label
)--;
13474 if (place2
&& JUMP_P (place2
)
13475 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13476 && (JUMP_LABEL (place2
) == NULL
13477 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13479 rtx label
= JUMP_LABEL (place2
);
13482 JUMP_LABEL (place2
) = XEXP (note
, 0);
13483 else if (LABEL_P (label
))
13484 LABEL_NUSES (label
)--;
13490 /* This note says something about the value of a register prior
13491 to the execution of an insn. It is too much trouble to see
13492 if the note is still correct in all situations. It is better
13493 to simply delete it. */
13497 /* If we replaced the right hand side of FROM_INSN with a
13498 REG_EQUAL note, the original use of the dying register
13499 will not have been combined into I3 and I2. In such cases,
13500 FROM_INSN is guaranteed to be the first of the combined
13501 instructions, so we simply need to search back before
13502 FROM_INSN for the previous use or set of this register,
13503 then alter the notes there appropriately.
13505 If the register is used as an input in I3, it dies there.
13506 Similarly for I2, if it is nonzero and adjacent to I3.
13508 If the register is not used as an input in either I3 or I2
13509 and it is not one of the registers we were supposed to eliminate,
13510 there are two possibilities. We might have a non-adjacent I2
13511 or we might have somehow eliminated an additional register
13512 from a computation. For example, we might have had A & B where
13513 we discover that B will always be zero. In this case we will
13514 eliminate the reference to A.
13516 In both cases, we must search to see if we can find a previous
13517 use of A and put the death note there. */
13520 && from_insn
== i2mod
13521 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13526 && CALL_P (from_insn
)
13527 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13529 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13531 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13532 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13534 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13536 && reg_overlap_mentioned_p (XEXP (note
, 0),
13538 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13539 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13546 basic_block bb
= this_basic_block
;
13548 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13550 if (!NONDEBUG_INSN_P (tem
))
13552 if (tem
== BB_HEAD (bb
))
13557 /* If the register is being set at TEM, see if that is all
13558 TEM is doing. If so, delete TEM. Otherwise, make this
13559 into a REG_UNUSED note instead. Don't delete sets to
13560 global register vars. */
13561 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13562 || !global_regs
[REGNO (XEXP (note
, 0))])
13563 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13565 rtx set
= single_set (tem
);
13566 rtx inner_dest
= 0;
13568 rtx cc0_setter
= NULL_RTX
;
13572 for (inner_dest
= SET_DEST (set
);
13573 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13574 || GET_CODE (inner_dest
) == SUBREG
13575 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13576 inner_dest
= XEXP (inner_dest
, 0))
13579 /* Verify that it was the set, and not a clobber that
13580 modified the register.
13582 CC0 targets must be careful to maintain setter/user
13583 pairs. If we cannot delete the setter due to side
13584 effects, mark the user with an UNUSED note instead
13587 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13588 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13590 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13591 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13592 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13596 /* Move the notes and links of TEM elsewhere.
13597 This might delete other dead insns recursively.
13598 First set the pattern to something that won't use
13600 rtx old_notes
= REG_NOTES (tem
);
13602 PATTERN (tem
) = pc_rtx
;
13603 REG_NOTES (tem
) = NULL
;
13605 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13606 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13607 distribute_links (LOG_LINKS (tem
));
13609 SET_INSN_DELETED (tem
);
13614 /* Delete the setter too. */
13617 PATTERN (cc0_setter
) = pc_rtx
;
13618 old_notes
= REG_NOTES (cc0_setter
);
13619 REG_NOTES (cc0_setter
) = NULL
;
13621 distribute_notes (old_notes
, cc0_setter
,
13622 cc0_setter
, NULL_RTX
,
13623 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13624 distribute_links (LOG_LINKS (cc0_setter
));
13626 SET_INSN_DELETED (cc0_setter
);
13627 if (cc0_setter
== i2
)
13634 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13636 /* If there isn't already a REG_UNUSED note, put one
13637 here. Do not place a REG_DEAD note, even if
13638 the register is also used here; that would not
13639 match the algorithm used in lifetime analysis
13640 and can cause the consistency check in the
13641 scheduler to fail. */
13642 if (! find_regno_note (tem
, REG_UNUSED
,
13643 REGNO (XEXP (note
, 0))))
13648 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13650 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13654 /* If we are doing a 3->2 combination, and we have a
13655 register which formerly died in i3 and was not used
13656 by i2, which now no longer dies in i3 and is used in
13657 i2 but does not die in i2, and place is between i2
13658 and i3, then we may need to move a link from place to
13660 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13662 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13663 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13665 struct insn_link
*links
= LOG_LINKS (place
);
13666 LOG_LINKS (place
) = NULL
;
13667 distribute_links (links
);
13672 if (tem
== BB_HEAD (bb
))
13678 /* If the register is set or already dead at PLACE, we needn't do
13679 anything with this note if it is still a REG_DEAD note.
13680 We check here if it is set at all, not if is it totally replaced,
13681 which is what `dead_or_set_p' checks, so also check for it being
13684 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13686 unsigned int regno
= REGNO (XEXP (note
, 0));
13687 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13689 if (dead_or_set_p (place
, XEXP (note
, 0))
13690 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13692 /* Unless the register previously died in PLACE, clear
13693 last_death. [I no longer understand why this is
13695 if (rsp
->last_death
!= place
)
13696 rsp
->last_death
= 0;
13700 rsp
->last_death
= place
;
13702 /* If this is a death note for a hard reg that is occupying
13703 multiple registers, ensure that we are still using all
13704 parts of the object. If we find a piece of the object
13705 that is unused, we must arrange for an appropriate REG_DEAD
13706 note to be added for it. However, we can't just emit a USE
13707 and tag the note to it, since the register might actually
13708 be dead; so we recourse, and the recursive call then finds
13709 the previous insn that used this register. */
13711 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13712 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13714 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13718 for (i
= regno
; i
< endregno
; i
++)
13719 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13720 && ! find_regno_fusage (place
, USE
, i
))
13721 || dead_or_set_regno_p (place
, i
))
13726 /* Put only REG_DEAD notes for pieces that are
13727 not already dead or set. */
13729 for (i
= regno
; i
< endregno
;
13730 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13732 rtx piece
= regno_reg_rtx
[i
];
13733 basic_block bb
= this_basic_block
;
13735 if (! dead_or_set_p (place
, piece
)
13736 && ! reg_bitfield_target_p (piece
,
13739 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13742 distribute_notes (new_note
, place
, place
,
13743 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13746 else if (! refers_to_regno_p (i
, i
+ 1,
13747 PATTERN (place
), 0)
13748 && ! find_regno_fusage (place
, USE
, i
))
13749 for (tem
= PREV_INSN (place
); ;
13750 tem
= PREV_INSN (tem
))
13752 if (!NONDEBUG_INSN_P (tem
))
13754 if (tem
== BB_HEAD (bb
))
13758 if (dead_or_set_p (tem
, piece
)
13759 || reg_bitfield_target_p (piece
,
13762 add_reg_note (tem
, REG_UNUSED
, piece
);
13776 /* Any other notes should not be present at this point in the
13778 gcc_unreachable ();
13783 XEXP (note
, 1) = REG_NOTES (place
);
13784 REG_NOTES (place
) = note
;
13788 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13792 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13793 I3, I2, and I1 to new locations. This is also called to add a link
13794 pointing at I3 when I3's destination is changed. */
13797 distribute_links (struct insn_link
*links
)
13799 struct insn_link
*link
, *next_link
;
13801 for (link
= links
; link
; link
= next_link
)
13807 next_link
= link
->next
;
13809 /* If the insn that this link points to is a NOTE or isn't a single
13810 set, ignore it. In the latter case, it isn't clear what we
13811 can do other than ignore the link, since we can't tell which
13812 register it was for. Such links wouldn't be used by combine
13815 It is not possible for the destination of the target of the link to
13816 have been changed by combine. The only potential of this is if we
13817 replace I3, I2, and I1 by I3 and I2. But in that case the
13818 destination of I2 also remains unchanged. */
13820 if (NOTE_P (link
->insn
)
13821 || (set
= single_set (link
->insn
)) == 0)
13824 reg
= SET_DEST (set
);
13825 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13826 || GET_CODE (reg
) == STRICT_LOW_PART
)
13827 reg
= XEXP (reg
, 0);
13829 /* A LOG_LINK is defined as being placed on the first insn that uses
13830 a register and points to the insn that sets the register. Start
13831 searching at the next insn after the target of the link and stop
13832 when we reach a set of the register or the end of the basic block.
13834 Note that this correctly handles the link that used to point from
13835 I3 to I2. Also note that not much searching is typically done here
13836 since most links don't point very far away. */
13838 for (insn
= NEXT_INSN (link
->insn
);
13839 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13840 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13841 insn
= NEXT_INSN (insn
))
13842 if (DEBUG_INSN_P (insn
))
13844 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13846 if (reg_referenced_p (reg
, PATTERN (insn
)))
13850 else if (CALL_P (insn
)
13851 && find_reg_fusage (insn
, USE
, reg
))
13856 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13859 /* If we found a place to put the link, place it there unless there
13860 is already a link to the same insn as LINK at that point. */
13864 struct insn_link
*link2
;
13866 FOR_EACH_LOG_LINK (link2
, place
)
13867 if (link2
->insn
== link
->insn
)
13872 link
->next
= LOG_LINKS (place
);
13873 LOG_LINKS (place
) = link
;
13875 /* Set added_links_insn to the earliest insn we added a
13877 if (added_links_insn
== 0
13878 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13879 added_links_insn
= place
;
13885 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13886 Check whether the expression pointer to by LOC is a register or
13887 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13888 Otherwise return zero. */
13891 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13896 && (REG_P (x
) || MEM_P (x
))
13897 && ! reg_mentioned_p (x
, (rtx
) expr
))
13902 /* Check for any register or memory mentioned in EQUIV that is not
13903 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13904 of EXPR where some registers may have been replaced by constants. */
13907 unmentioned_reg_p (rtx equiv
, rtx expr
)
13909 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13912 DEBUG_FUNCTION
void
13913 dump_combine_stats (FILE *file
)
13917 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13918 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13922 dump_combine_total_stats (FILE *file
)
13926 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13927 total_attempts
, total_merges
, total_extras
, total_successes
);
13931 gate_handle_combine (void)
13933 return (optimize
> 0);
13936 /* Try combining insns through substitution. */
13937 static unsigned int
13938 rest_of_handle_combine (void)
13940 int rebuild_jump_labels_after_combine
;
13942 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13943 df_note_add_problem ();
13946 regstat_init_n_sets_and_refs ();
13948 rebuild_jump_labels_after_combine
13949 = combine_instructions (get_insns (), max_reg_num ());
13951 /* Combining insns may have turned an indirect jump into a
13952 direct jump. Rebuild the JUMP_LABEL fields of jumping
13954 if (rebuild_jump_labels_after_combine
)
13956 timevar_push (TV_JUMP
);
13957 rebuild_jump_labels (get_insns ());
13959 timevar_pop (TV_JUMP
);
13962 regstat_free_n_sets_and_refs ();
13966 struct rtl_opt_pass pass_combine
=
13970 "combine", /* name */
13971 gate_handle_combine
, /* gate */
13972 rest_of_handle_combine
, /* execute */
13975 0, /* static_pass_number */
13976 TV_COMBINE
, /* tv_id */
13977 PROP_cfglayout
, /* properties_required */
13978 0, /* properties_provided */
13979 0, /* properties_destroyed */
13980 0, /* todo_flags_start */
13981 TODO_df_finish
| TODO_verify_rtl_sharing
|
13982 TODO_ggc_collect
, /* todo_flags_finish */