1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "basic-block.h"
70 #include "hard-reg-set.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* In all the following vectors indexed by quantity number. */
83 /* Element Q is the hard reg number chosen for quantity Q,
84 or -1 if none was found. */
86 static short *qty_phys_reg
;
88 /* We maintain two hard register sets that indicate suggested hard registers
89 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
90 that are tied to the quantity by a simple copy. The second contains all
91 hard registers that are tied to the quantity via an arithmetic operation.
93 The former register set is given priority for allocation. This tends to
94 eliminate copy insns. */
96 /* Element Q is a set of hard registers that are suggested for quantity Q by
99 static HARD_REG_SET
*qty_phys_copy_sugg
;
101 /* Element Q is a set of hard registers that are suggested for quantity Q by
104 static HARD_REG_SET
*qty_phys_sugg
;
106 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
108 static short *qty_phys_num_copy_sugg
;
110 /* Element Q is the number of suggested registers in qty_phys_sugg. */
112 static short *qty_phys_num_sugg
;
114 /* Element Q is the number of refs to quantity Q. */
116 static int *qty_n_refs
;
118 /* Element Q is a reg class contained in (smaller than) the
119 preferred classes of all the pseudo regs that are tied in quantity Q.
120 This is the preferred class for allocating that quantity. */
122 static enum reg_class
*qty_min_class
;
124 /* Insn number (counting from head of basic block)
125 where quantity Q was born. -1 if birth has not been recorded. */
127 static int *qty_birth
;
129 /* Insn number (counting from head of basic block)
130 where quantity Q died. Due to the way tying is done,
131 and the fact that we consider in this pass only regs that die but once,
132 a quantity can die only once. Each quantity's life span
133 is a set of consecutive insns. -1 if death has not been recorded. */
135 static int *qty_death
;
137 /* Number of words needed to hold the data in quantity Q.
138 This depends on its machine mode. It is used for these purposes:
139 1. It is used in computing the relative importances of qtys,
140 which determines the order in which we look for regs for them.
141 2. It is used in rules that prevent tying several registers of
142 different sizes in a way that is geometrically impossible
143 (see combine_regs). */
145 static int *qty_size
;
147 /* This holds the mode of the registers that are tied to qty Q,
148 or VOIDmode if registers with differing modes are tied together. */
150 static enum machine_mode
*qty_mode
;
152 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
154 static int *qty_n_calls_crossed
;
156 /* Register class within which we allocate qty Q if we can't get
157 its preferred class. */
159 static enum reg_class
*qty_alternate_class
;
161 /* Element Q is nonzero if this quantity has been used in a SUBREG
162 that changes its size. */
164 static char *qty_changes_size
;
166 /* Element Q is the register number of one pseudo register whose
167 reg_qty value is Q. This register should be the head of the chain
168 maintained in reg_next_in_qty. */
170 static int *qty_first_reg
;
172 /* If (REG N) has been assigned a quantity number, is a register number
173 of another register assigned the same quantity number, or -1 for the
174 end of the chain. qty_first_reg point to the head of this chain. */
176 static int *reg_next_in_qty
;
178 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
180 of -1 if this register cannot be allocated by local-alloc,
181 or -2 if not known yet.
183 Note that if we see a use or death of pseudo register N with
184 reg_qty[N] == -2, register N must be local to the current block. If
185 it were used in more than one block, we would have reg_qty[N] == -1.
186 This relies on the fact that if reg_basic_block[N] is >= 0, register N
187 will not appear in any other block. We save a considerable number of
188 tests by exploiting this.
190 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
195 /* The offset (in words) of register N within its quantity.
196 This can be nonzero if register N is SImode, and has been tied
197 to a subreg of a DImode register. */
199 static char *reg_offset
;
201 /* Vector of substitutions of register numbers,
202 used to map pseudo regs into hardware regs.
203 This is set up as a result of register allocation.
204 Element N is the hard reg assigned to pseudo reg N,
205 or is -1 if no hard reg was assigned.
206 If N is a hard reg number, element N is N. */
210 /* Set of hard registers live at the current point in the scan
211 of the instructions in a basic block. */
213 static HARD_REG_SET regs_live
;
215 /* Each set of hard registers indicates registers live at a particular
216 point in the basic block. For N even, regs_live_at[N] says which
217 hard registers are needed *after* insn N/2 (i.e., they may not
218 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
220 If an object is to conflict with the inputs of insn J but not the
221 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
222 if it is to conflict with the outputs of insn J but not the inputs of
223 insn J + 1, it is said to die at index J*2 + 1. */
225 static HARD_REG_SET
*regs_live_at
;
227 /* Communicate local vars `insn_number' and `insn'
228 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
229 static int this_insn_number
;
230 static rtx this_insn
;
232 /* Used to communicate changes made by update_equiv_regs to
233 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
234 found or created, so that we can keep track of what memory accesses might
235 be created later, e.g. by reload. */
237 static rtx
*reg_equiv_replacement
;
239 /* Used for communication between update_equiv_regs and no_equiv. */
240 static rtx
*reg_equiv_init_insns
;
242 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
243 static int recorded_label_ref
;
245 static void alloc_qty
PROTO((int, enum machine_mode
, int, int));
246 static void validate_equiv_mem_from_store
PROTO((rtx
, rtx
, void *));
247 static int validate_equiv_mem
PROTO((rtx
, rtx
, rtx
));
248 static int contains_replace_regs
PROTO((rtx
, char *));
249 static int memref_referenced_p
PROTO((rtx
, rtx
));
250 static int memref_used_between_p
PROTO((rtx
, rtx
, rtx
));
251 static void update_equiv_regs
PROTO((void));
252 static void no_equiv
PROTO((rtx
, rtx
, void *));
253 static void block_alloc
PROTO((int));
254 static int qty_sugg_compare
PROTO((int, int));
255 static int qty_sugg_compare_1
PROTO((const PTR
, const PTR
));
256 static int qty_compare
PROTO((int, int));
257 static int qty_compare_1
PROTO((const PTR
, const PTR
));
258 static int combine_regs
PROTO((rtx
, rtx
, int, int, rtx
, int));
259 static int reg_meets_class_p
PROTO((int, enum reg_class
));
260 static void update_qty_class
PROTO((int, int));
261 static void reg_is_set
PROTO((rtx
, rtx
, void *));
262 static void reg_is_born
PROTO((rtx
, int));
263 static void wipe_dead_reg
PROTO((rtx
, int));
264 static int find_free_reg
PROTO((enum reg_class
, enum machine_mode
,
265 int, int, int, int, int));
266 static void mark_life
PROTO((int, enum machine_mode
, int));
267 static void post_mark_life
PROTO((int, enum machine_mode
, int, int, int));
268 static int no_conflict_p
PROTO((rtx
, rtx
, rtx
));
269 static int requires_inout
PROTO((const char *));
271 /* Allocate a new quantity (new within current basic block)
272 for register number REGNO which is born at index BIRTH
273 within the block. MODE and SIZE are info on reg REGNO. */
276 alloc_qty (regno
, mode
, size
, birth
)
278 enum machine_mode mode
;
281 register int qty
= next_qty
++;
283 reg_qty
[regno
] = qty
;
284 reg_offset
[regno
] = 0;
285 reg_next_in_qty
[regno
] = -1;
287 qty_first_reg
[qty
] = regno
;
288 qty_size
[qty
] = size
;
289 qty_mode
[qty
] = mode
;
290 qty_birth
[qty
] = birth
;
291 qty_n_calls_crossed
[qty
] = REG_N_CALLS_CROSSED (regno
);
292 qty_min_class
[qty
] = reg_preferred_class (regno
);
293 qty_alternate_class
[qty
] = reg_alternate_class (regno
);
294 qty_n_refs
[qty
] = REG_N_REFS (regno
);
295 qty_changes_size
[qty
] = REG_CHANGES_SIZE (regno
);
298 /* Main entry point of this file. */
306 /* We need to keep track of whether or not we recorded a LABEL_REF so
307 that we know if the jump optimizer needs to be rerun. */
308 recorded_label_ref
= 0;
310 /* Leaf functions and non-leaf functions have different needs.
311 If defined, let the machine say what kind of ordering we
313 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
314 ORDER_REGS_FOR_LOCAL_ALLOC
;
317 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
319 update_equiv_regs ();
321 /* This sets the maximum number of quantities we can have. Quantity
322 numbers start at zero and we can have one for each pseudo. */
323 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
325 /* Allocate vectors of temporary data.
326 See the declarations of these variables, above,
327 for what they mean. */
329 qty_phys_reg
= (short *) xmalloc (max_qty
* sizeof (short));
331 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
332 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
333 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
334 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
335 qty_birth
= (int *) xmalloc (max_qty
* sizeof (int));
336 qty_death
= (int *) xmalloc (max_qty
* sizeof (int));
337 qty_first_reg
= (int *) xmalloc (max_qty
* sizeof (int));
338 qty_size
= (int *) xmalloc (max_qty
* sizeof (int));
340 = (enum machine_mode
*) xmalloc (max_qty
* sizeof (enum machine_mode
));
341 qty_n_calls_crossed
= (int *) xmalloc (max_qty
* sizeof (int));
343 = (enum reg_class
*) xmalloc (max_qty
* sizeof (enum reg_class
));
345 = (enum reg_class
*) xmalloc (max_qty
* sizeof (enum reg_class
));
346 qty_n_refs
= (int *) xmalloc (max_qty
* sizeof (int));
347 qty_changes_size
= (char *) xmalloc (max_qty
* sizeof (char));
349 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
350 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
351 reg_next_in_qty
= (int *) xmalloc(max_regno
* sizeof (int));
353 /* Allocate the reg_renumber array */
354 allocate_reg_info (max_regno
, FALSE
, TRUE
);
356 /* Determine which pseudo-registers can be allocated by local-alloc.
357 In general, these are the registers used only in a single block and
358 which only die once. However, if a register's preferred class has only
359 a few entries, don't allocate this register here unless it is preferred
360 or nothing since retry_global_alloc won't be able to move it to
361 GENERAL_REGS if a reload register of this class is needed.
363 We need not be concerned with which block actually uses the register
364 since we will never see it outside that block. */
366 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
368 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1
369 && (reg_alternate_class (i
) == NO_REGS
370 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i
))))
376 /* Force loop below to initialize entire quantity array. */
379 /* Allocate each block's local registers, block by block. */
381 for (b
= 0; b
< n_basic_blocks
; b
++)
383 /* NEXT_QTY indicates which elements of the `qty_...'
384 vectors might need to be initialized because they were used
385 for the previous block; it is set to the entire array before
386 block 0. Initialize those, with explicit loop if there are few,
387 else with bzero and bcopy. Do not initialize vectors that are
388 explicit set by `alloc_qty'. */
392 for (i
= 0; i
< next_qty
; i
++)
394 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
395 qty_phys_num_copy_sugg
[i
] = 0;
396 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
397 qty_phys_num_sugg
[i
] = 0;
402 #define CLEAR(vector) \
403 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
405 CLEAR (qty_phys_copy_sugg
);
406 CLEAR (qty_phys_num_copy_sugg
);
407 CLEAR (qty_phys_sugg
);
408 CLEAR (qty_phys_num_sugg
);
417 free (qty_phys_copy_sugg
);
418 free (qty_phys_num_copy_sugg
);
419 free (qty_phys_sugg
);
420 free (qty_phys_num_sugg
);
423 free (qty_first_reg
);
426 free (qty_n_calls_crossed
);
427 free (qty_min_class
);
428 free (qty_alternate_class
);
430 free (qty_changes_size
);
434 free (reg_next_in_qty
);
436 return recorded_label_ref
;
439 /* Depth of loops we are in while in update_equiv_regs. */
440 static int loop_depth
;
442 /* Used for communication between the following two functions: contains
443 a MEM that we wish to ensure remains unchanged. */
444 static rtx equiv_mem
;
446 /* Set nonzero if EQUIV_MEM is modified. */
447 static int equiv_mem_modified
;
449 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
450 Called via note_stores. */
453 validate_equiv_mem_from_store (dest
, set
, data
)
455 rtx set ATTRIBUTE_UNUSED
;
456 void *data ATTRIBUTE_UNUSED
;
458 if ((GET_CODE (dest
) == REG
459 && reg_overlap_mentioned_p (dest
, equiv_mem
))
460 || (GET_CODE (dest
) == MEM
461 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
462 equiv_mem_modified
= 1;
465 /* Verify that no store between START and the death of REG invalidates
466 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
467 by storing into an overlapping memory location, or with a non-const
470 Return 1 if MEMREF remains valid. */
473 validate_equiv_mem (start
, reg
, memref
)
482 equiv_mem_modified
= 0;
484 /* If the memory reference has side effects or is volatile, it isn't a
485 valid equivalence. */
486 if (side_effects_p (memref
))
489 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
491 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
494 if (find_reg_note (insn
, REG_DEAD
, reg
))
497 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
498 && ! CONST_CALL_P (insn
))
501 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
503 /* If a register mentioned in MEMREF is modified via an
504 auto-increment, we lose the equivalence. Do the same if one
505 dies; although we could extend the life, it doesn't seem worth
508 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
509 if ((REG_NOTE_KIND (note
) == REG_INC
510 || REG_NOTE_KIND (note
) == REG_DEAD
)
511 && GET_CODE (XEXP (note
, 0)) == REG
512 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
519 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
522 contains_replace_regs (x
, reg_equiv_replace
)
524 char *reg_equiv_replace
;
528 enum rtx_code code
= GET_CODE (x
);
544 return reg_equiv_replace
[REGNO (x
)];
550 fmt
= GET_RTX_FORMAT (code
);
551 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
555 if (contains_replace_regs (XEXP (x
, i
), reg_equiv_replace
))
559 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
560 if (contains_replace_regs (XVECEXP (x
, i
, j
), reg_equiv_replace
))
568 /* TRUE if X references a memory location that would be affected by a store
572 memref_referenced_p (memref
, x
)
578 enum rtx_code code
= GET_CODE (x
);
594 return (reg_equiv_replacement
[REGNO (x
)]
595 && memref_referenced_p (memref
,
596 reg_equiv_replacement
[REGNO (x
)]));
599 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
604 /* If we are setting a MEM, it doesn't count (its address does), but any
605 other SET_DEST that has a MEM in it is referencing the MEM. */
606 if (GET_CODE (SET_DEST (x
)) == MEM
)
608 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
611 else if (memref_referenced_p (memref
, SET_DEST (x
)))
614 return memref_referenced_p (memref
, SET_SRC (x
));
620 fmt
= GET_RTX_FORMAT (code
);
621 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
625 if (memref_referenced_p (memref
, XEXP (x
, i
)))
629 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
630 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
638 /* TRUE if some insn in the range (START, END] references a memory location
639 that would be affected by a store to MEMREF. */
642 memref_used_between_p (memref
, start
, end
)
649 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
650 insn
= NEXT_INSN (insn
))
651 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
652 && memref_referenced_p (memref
, PATTERN (insn
)))
658 /* Return nonzero if the rtx X is invariant over the current function. */
660 function_invariant_p (x
)
665 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
667 if (GET_CODE (x
) == PLUS
668 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
669 && CONSTANT_P (XEXP (x
, 1)))
674 /* Find registers that are equivalent to a single value throughout the
675 compilation (either because they can be referenced in memory or are set once
676 from a single constant). Lower their priority for a register.
678 If such a register is only referenced once, try substituting its value
679 into the using insn. If it succeeds, we can eliminate the register
685 /* Set when an attempt should be made to replace a register with the
686 associated reg_equiv_replacement entry at the end of this function. */
687 char *reg_equiv_replace
;
691 reg_equiv_replace
= (char *) xcalloc (max_regno
, sizeof *reg_equiv_replace
);
692 reg_equiv_init_insns
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
693 reg_equiv_replacement
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
695 init_alias_analysis ();
699 /* Scan the insns and find which registers have equivalences. Do this
700 in a separate scan of the insns because (due to -fcse-follow-jumps)
701 a register can be set below its use. */
702 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
709 if (GET_CODE (insn
) == NOTE
)
711 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
713 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
717 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
720 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
721 if (REG_NOTE_KIND (note
) == REG_INC
)
722 no_equiv (XEXP (note
, 0), note
, NULL
);
724 set
= single_set (insn
);
726 /* If this insn contains more (or less) than a single SET,
727 only mark all destinations as having no known equivalence. */
730 note_stores (PATTERN (insn
), no_equiv
, NULL
);
733 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
737 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
739 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
741 note_stores (part
, no_equiv
, NULL
);
745 dest
= SET_DEST (set
);
748 /* If this sets a MEM to the contents of a REG that is only used
749 in a single basic block, see if the register is always equivalent
750 to that memory location and if moving the store from INSN to the
751 insn that set REG is safe. If so, put a REG_EQUIV note on the
754 Don't add a REG_EQUIV note if the insn already has one. The existing
755 REG_EQUIV is likely more useful than the one we are adding.
757 If one of the regs in the address is marked as reg_equiv_replace,
758 then we can't add this REG_EQUIV note. The reg_equiv_replace
759 optimization may move the set of this register immediately before
760 insn, which puts it after reg_equiv_init_insns[regno], and hence
761 the mention in the REG_EQUIV note would be to an uninitialized
763 /* ????? This test isn't good enough; we might see a MEM with a use of
764 a pseudo register before we see its setting insn that will cause
765 reg_equiv_replace for that pseudo to be set.
766 Equivalences to MEMs should be made in another pass, after the
767 reg_equiv_replace information has been gathered. */
769 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
770 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
771 && REG_BASIC_BLOCK (regno
) >= 0
772 && REG_N_SETS (regno
) == 1
773 && reg_equiv_init_insns
[regno
] != 0
774 && reg_equiv_init_insns
[regno
] != const0_rtx
775 && ! find_reg_note (XEXP (reg_equiv_init_insns
[regno
], 0),
777 && ! contains_replace_regs (XEXP (dest
, 0), reg_equiv_replace
))
779 rtx init_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
780 if (validate_equiv_mem (init_insn
, src
, dest
)
781 && ! memref_used_between_p (dest
, init_insn
, insn
))
782 REG_NOTES (init_insn
)
783 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
786 /* We only handle the case of a pseudo register being set
787 once, or always to the same value. */
788 /* ??? The mn10200 port breaks if we add equivalences for
789 values that need an ADDRESS_REGS register and set them equivalent
790 to a MEM of a pseudo. The actual problem is in the over-conservative
791 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
792 calculate_needs, but we traditionally work around this problem
793 here by rejecting equivalences when the destination is in a register
794 that's likely spilled. This is fragile, of course, since the
795 preferred class of a pseudo depends on all instructions that set
798 if (GET_CODE (dest
) != REG
799 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
800 || reg_equiv_init_insns
[regno
] == const0_rtx
801 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
802 && GET_CODE (src
) == MEM
))
804 /* This might be seting a SUBREG of a pseudo, a pseudo that is
805 also set somewhere else to a constant. */
806 note_stores (set
, no_equiv
, NULL
);
809 /* Don't handle the equivalence if the source is in a register
810 class that's likely to be spilled. */
811 if (GET_CODE (src
) == REG
812 && REGNO (src
) >= FIRST_PSEUDO_REGISTER
813 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src
))))
815 no_equiv (dest
, set
, NULL
);
819 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
821 if (REG_N_SETS (regno
) != 1
823 || ! function_invariant_p (XEXP (note
, 0))
824 || (reg_equiv_replacement
[regno
]
825 && ! rtx_equal_p (XEXP (note
, 0),
826 reg_equiv_replacement
[regno
]))))
828 no_equiv (dest
, set
, NULL
);
831 /* Record this insn as initializing this register. */
832 reg_equiv_init_insns
[regno
]
833 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init_insns
[regno
]);
835 /* If this register is known to be equal to a constant, record that
836 it is always equivalent to the constant. */
837 if (note
&& function_invariant_p (XEXP (note
, 0)))
838 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
840 /* If this insn introduces a "constant" register, decrease the priority
841 of that register. Record this insn if the register is only used once
842 more and the equivalence value is the same as our source.
844 The latter condition is checked for two reasons: First, it is an
845 indication that it may be more efficient to actually emit the insn
846 as written (if no registers are available, reload will substitute
847 the equivalence). Secondly, it avoids problems with any registers
848 dying in this insn whose death notes would be missed.
850 If we don't have a REG_EQUIV note, see if this insn is loading
851 a register used only in one basic block from a MEM. If so, and the
852 MEM remains unchanged for the life of the register, add a REG_EQUIV
855 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
857 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
858 && GET_CODE (SET_SRC (set
)) == MEM
859 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
860 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
865 int regno
= REGNO (dest
);
867 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
868 We might end up substituting the LABEL_REF for uses of the
869 pseudo here or later. That kind of transformation may turn an
870 indirect jump into a direct jump, in which case we must rerun the
871 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
872 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
873 || (GET_CODE (XEXP (note
, 0)) == CONST
874 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
875 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
877 recorded_label_ref
= 1;
880 reg_equiv_replacement
[regno
] = XEXP (note
, 0);
882 /* Don't mess with things live during setjmp. */
883 if (REG_LIVE_LENGTH (regno
) >= 0)
885 /* Note that the statement below does not affect the priority
887 REG_LIVE_LENGTH (regno
) *= 2;
890 /* If the register is referenced exactly twice, meaning it is
891 set once and used once, indicate that the reference may be
892 replaced by the equivalence we computed above. If the
893 register is only used in one basic block, this can't succeed
894 or combine would have done it.
896 It would be nice to use "loop_depth * 2" in the compare
897 below. Unfortunately, LOOP_DEPTH need not be constant within
898 a basic block so this would be too complicated.
900 This case normally occurs when a parameter is read from
901 memory and then used exactly once, not in a loop. */
903 if (REG_N_REFS (regno
) == 2
904 && REG_BASIC_BLOCK (regno
) < 0
905 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
906 reg_equiv_replace
[regno
] = 1;
911 /* Now scan all regs killed in an insn to see if any of them are
912 registers only used that once. If so, see if we can replace the
913 reference with the equivalent from. If we can, delete the
914 initializing reference and this register will go away. If we
915 can't replace the reference, and the instruction is not in a
916 loop, then move the register initialization just before the use,
917 so that they are in the same basic block. */
920 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
924 /* Keep track of which basic block we are in. */
925 if (block
+ 1 < n_basic_blocks
926 && BLOCK_HEAD (block
+ 1) == insn
)
929 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
931 if (GET_CODE (insn
) == NOTE
)
933 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
935 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
946 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
948 if (REG_NOTE_KIND (link
) == REG_DEAD
949 /* Make sure this insn still refers to the register. */
950 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
952 int regno
= REGNO (XEXP (link
, 0));
955 if (! reg_equiv_replace
[regno
])
958 /* reg_equiv_replace[REGNO] gets set only when
959 REG_N_REFS[REGNO] is 2, i.e. the register is set
960 once and used once. (If it were only set, but not used,
961 flow would have deleted the setting insns.) Hence
962 there can only be one insn in reg_equiv_init_insns. */
963 equiv_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
965 if (validate_replace_rtx (regno_reg_rtx
[regno
],
966 reg_equiv_replacement
[regno
], insn
))
968 remove_death (regno
, insn
);
969 REG_N_REFS (regno
) = 0;
970 PUT_CODE (equiv_insn
, NOTE
);
971 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
972 NOTE_SOURCE_FILE (equiv_insn
) = 0;
974 /* If we aren't in a loop, and there are no calls in
975 INSN or in the initialization of the register, then
976 move the initialization of the register to just
977 before INSN. Update the flow information. */
979 && GET_CODE (equiv_insn
) == INSN
980 && GET_CODE (insn
) == INSN
981 && REG_BASIC_BLOCK (regno
) < 0)
985 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
986 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
987 REG_NOTES (equiv_insn
) = 0;
989 PUT_CODE (equiv_insn
, NOTE
);
990 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
991 NOTE_SOURCE_FILE (equiv_insn
) = 0;
994 REG_BASIC_BLOCK (regno
) = 0;
996 REG_BASIC_BLOCK (regno
) = block
;
997 REG_N_CALLS_CROSSED (regno
) = 0;
998 REG_LIVE_LENGTH (regno
) = 2;
1000 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
1001 BLOCK_HEAD (block
) = PREV_INSN (insn
);
1003 for (l
= 0; l
< n_basic_blocks
; l
++)
1004 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
1012 end_alias_analysis ();
1013 free (reg_equiv_replace
);
1014 free (reg_equiv_init_insns
);
1015 free (reg_equiv_replacement
);
1018 /* Mark REG as having no known equivalence.
1019 Some instructions might have been proceessed before and furnished
1020 with REG_EQUIV notes for this register; these notes will have to be
1022 STORE is the piece of RTL that does the non-constant / conflicting
1023 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1024 but needs to be there because this function is called from note_stores. */
1026 no_equiv (reg
, store
, data
)
1027 rtx reg
, store ATTRIBUTE_UNUSED
;
1028 void *data ATTRIBUTE_UNUSED
;
1033 if (GET_CODE (reg
) != REG
)
1035 regno
= REGNO (reg
);
1036 list
= reg_equiv_init_insns
[regno
];
1037 if (list
== const0_rtx
)
1039 for (; list
; list
= XEXP (list
, 1))
1041 rtx insn
= XEXP (list
, 0);
1042 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1044 reg_equiv_init_insns
[regno
] = const0_rtx
;
1045 reg_equiv_replacement
[regno
] = NULL_RTX
;
1048 /* Allocate hard regs to the pseudo regs used only within block number B.
1049 Only the pseudos that die but once can be handled. */
1058 int insn_number
= 0;
1060 int max_uid
= get_max_uid ();
1062 int no_conflict_combined_regno
= -1;
1064 /* Count the instructions in the basic block. */
1066 insn
= BLOCK_END (b
);
1069 if (GET_CODE (insn
) != NOTE
)
1070 if (++insn_count
> max_uid
)
1072 if (insn
== BLOCK_HEAD (b
))
1074 insn
= PREV_INSN (insn
);
1077 /* +2 to leave room for a post_mark_life at the last insn and for
1078 the birth of a CLOBBER in the first insn. */
1079 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1080 sizeof (HARD_REG_SET
));
1082 /* Initialize table of hardware registers currently live. */
1084 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1086 /* This loop scans the instructions of the basic block
1087 and assigns quantities to registers.
1088 It computes which registers to tie. */
1090 insn
= BLOCK_HEAD (b
);
1093 if (GET_CODE (insn
) != NOTE
)
1096 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1098 register rtx link
, set
;
1099 register int win
= 0;
1100 register rtx r0
, r1
;
1101 int combined_regno
= -1;
1104 this_insn_number
= insn_number
;
1107 extract_insn (insn
);
1108 which_alternative
= -1;
1110 /* Is this insn suitable for tying two registers?
1111 If so, try doing that.
1112 Suitable insns are those with at least two operands and where
1113 operand 0 is an output that is a register that is not
1116 We can tie operand 0 with some operand that dies in this insn.
1117 First look for operands that are required to be in the same
1118 register as operand 0. If we find such, only try tying that
1119 operand or one that can be put into that operand if the
1120 operation is commutative. If we don't find an operand
1121 that is required to be in the same register as operand 0,
1122 we can tie with any operand.
1124 Subregs in place of regs are also ok.
1126 If tying is done, WIN is set nonzero. */
1128 if (recog_data
.n_operands
> 1
1129 && recog_data
.constraints
[0][0] == '='
1130 && recog_data
.constraints
[0][1] != '&')
1132 /* If non-negative, is an operand that must match operand 0. */
1133 int must_match_0
= -1;
1134 /* Counts number of alternatives that require a match with
1136 int n_matching_alts
= 0;
1138 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1140 const char *p
= recog_data
.constraints
[i
];
1141 int this_match
= (requires_inout (p
));
1143 n_matching_alts
+= this_match
;
1144 if (this_match
== recog_data
.n_alternatives
)
1148 r0
= recog_data
.operand
[0];
1149 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1151 /* Skip this operand if we found an operand that
1152 must match operand 0 and this operand isn't it
1153 and can't be made to be it by commutativity. */
1155 if (must_match_0
>= 0 && i
!= must_match_0
1156 && ! (i
== must_match_0
+ 1
1157 && recog_data
.constraints
[i
-1][0] == '%')
1158 && ! (i
== must_match_0
- 1
1159 && recog_data
.constraints
[i
][0] == '%'))
1162 /* Likewise if each alternative has some operand that
1163 must match operand zero. In that case, skip any
1164 operand that doesn't list operand 0 since we know that
1165 the operand always conflicts with operand 0. We
1166 ignore commutatity in this case to keep things simple. */
1167 if (n_matching_alts
== recog_data
.n_alternatives
1168 && 0 == requires_inout (recog_data
.constraints
[i
]))
1171 r1
= recog_data
.operand
[i
];
1173 /* If the operand is an address, find a register in it.
1174 There may be more than one register, but we only try one
1176 if (recog_data
.constraints
[i
][0] == 'p')
1177 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1180 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1182 /* We have two priorities for hard register preferences.
1183 If we have a move insn or an insn whose first input
1184 can only be in the same register as the output, give
1185 priority to an equivalence found from that insn. */
1187 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1189 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1190 win
= combine_regs (r1
, r0
, may_save_copy
,
1191 insn_number
, insn
, 0);
1198 /* Recognize an insn sequence with an ultimate result
1199 which can safely overlap one of the inputs.
1200 The sequence begins with a CLOBBER of its result,
1201 and ends with an insn that copies the result to itself
1202 and has a REG_EQUAL note for an equivalent formula.
1203 That note indicates what the inputs are.
1204 The result and the input can overlap if each insn in
1205 the sequence either doesn't mention the input
1206 or has a REG_NO_CONFLICT note to inhibit the conflict.
1208 We do the combining test at the CLOBBER so that the
1209 destination register won't have had a quantity number
1210 assigned, since that would prevent combining. */
1212 if (GET_CODE (PATTERN (insn
)) == CLOBBER
1213 && (r0
= XEXP (PATTERN (insn
), 0),
1214 GET_CODE (r0
) == REG
)
1215 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1216 && XEXP (link
, 0) != 0
1217 && GET_CODE (XEXP (link
, 0)) == INSN
1218 && (set
= single_set (XEXP (link
, 0))) != 0
1219 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1220 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1223 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1224 /* Check that we have such a sequence. */
1225 && no_conflict_p (insn
, r0
, r1
))
1226 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1227 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1228 && (r1
= XEXP (XEXP (note
, 0), 0),
1229 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1230 && no_conflict_p (insn
, r0
, r1
))
1231 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1233 /* Here we care if the operation to be computed is
1235 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1236 || GET_CODE (XEXP (note
, 0)) == NE
1237 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1238 && (r1
= XEXP (XEXP (note
, 0), 1),
1239 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1240 && no_conflict_p (insn
, r0
, r1
))
1241 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1243 /* If we did combine something, show the register number
1244 in question so that we know to ignore its death. */
1246 no_conflict_combined_regno
= REGNO (r1
);
1249 /* If registers were just tied, set COMBINED_REGNO
1250 to the number of the register used in this insn
1251 that was tied to the register set in this insn.
1252 This register's qty should not be "killed". */
1256 while (GET_CODE (r1
) == SUBREG
)
1257 r1
= SUBREG_REG (r1
);
1258 combined_regno
= REGNO (r1
);
1261 /* Mark the death of everything that dies in this instruction,
1262 except for anything that was just combined. */
1264 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1265 if (REG_NOTE_KIND (link
) == REG_DEAD
1266 && GET_CODE (XEXP (link
, 0)) == REG
1267 && combined_regno
!= REGNO (XEXP (link
, 0))
1268 && (no_conflict_combined_regno
!= REGNO (XEXP (link
, 0))
1269 || ! find_reg_note (insn
, REG_NO_CONFLICT
, XEXP (link
, 0))))
1270 wipe_dead_reg (XEXP (link
, 0), 0);
1272 /* Allocate qty numbers for all registers local to this block
1273 that are born (set) in this instruction.
1274 A pseudo that already has a qty is not changed. */
1276 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1278 /* If anything is set in this insn and then unused, mark it as dying
1279 after this insn, so it will conflict with our outputs. This
1280 can't match with something that combined, and it doesn't matter
1281 if it did. Do this after the calls to reg_is_set since these
1282 die after, not during, the current insn. */
1284 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1285 if (REG_NOTE_KIND (link
) == REG_UNUSED
1286 && GET_CODE (XEXP (link
, 0)) == REG
)
1287 wipe_dead_reg (XEXP (link
, 0), 1);
1289 /* If this is an insn that has a REG_RETVAL note pointing at a
1290 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1291 block, so clear any register number that combined within it. */
1292 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1293 && GET_CODE (XEXP (note
, 0)) == INSN
1294 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1295 no_conflict_combined_regno
= -1;
1298 /* Set the registers live after INSN_NUMBER. Note that we never
1299 record the registers live before the block's first insn, since no
1300 pseudos we care about are live before that insn. */
1302 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1303 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1305 if (insn
== BLOCK_END (b
))
1308 insn
= NEXT_INSN (insn
);
1311 /* Now every register that is local to this basic block
1312 should have been given a quantity, or else -1 meaning ignore it.
1313 Every quantity should have a known birth and death.
1315 Order the qtys so we assign them registers in order of the
1316 number of suggested registers they need so we allocate those with
1317 the most restrictive needs first. */
1319 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1320 for (i
= 0; i
< next_qty
; i
++)
1323 #define EXCHANGE(I1, I2) \
1324 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1329 /* Make qty_order[2] be the one to allocate last. */
1330 if (qty_sugg_compare (0, 1) > 0)
1332 if (qty_sugg_compare (1, 2) > 0)
1335 /* ... Fall through ... */
1337 /* Put the best one to allocate in qty_order[0]. */
1338 if (qty_sugg_compare (0, 1) > 0)
1341 /* ... Fall through ... */
1345 /* Nothing to do here. */
1349 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1352 /* Try to put each quantity in a suggested physical register, if it has one.
1353 This may cause registers to be allocated that otherwise wouldn't be, but
1354 this seems acceptable in local allocation (unlike global allocation). */
1355 for (i
= 0; i
< next_qty
; i
++)
1358 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1359 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
], qty_mode
[q
], q
,
1360 0, 1, qty_birth
[q
], qty_death
[q
]);
1362 qty_phys_reg
[q
] = -1;
1365 /* Order the qtys so we assign them registers in order of
1366 decreasing length of life. Normally call qsort, but if we
1367 have only a very small number of quantities, sort them ourselves. */
1369 for (i
= 0; i
< next_qty
; i
++)
1372 #define EXCHANGE(I1, I2) \
1373 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1378 /* Make qty_order[2] be the one to allocate last. */
1379 if (qty_compare (0, 1) > 0)
1381 if (qty_compare (1, 2) > 0)
1384 /* ... Fall through ... */
1386 /* Put the best one to allocate in qty_order[0]. */
1387 if (qty_compare (0, 1) > 0)
1390 /* ... Fall through ... */
1394 /* Nothing to do here. */
1398 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1401 /* Now for each qty that is not a hardware register,
1402 look for a hardware register to put it in.
1403 First try the register class that is cheapest for this qty,
1404 if there is more than one class. */
1406 for (i
= 0; i
< next_qty
; i
++)
1409 if (qty_phys_reg
[q
] < 0)
1411 #ifdef INSN_SCHEDULING
1412 /* These values represent the adjusted lifetime of a qty so
1413 that it conflicts with qtys which appear near the start/end
1414 of this qty's lifetime.
1416 The purpose behind extending the lifetime of this qty is to
1417 discourage the register allocator from creating false
1420 The adjustment value is choosen to indicate that this qty
1421 conflicts with all the qtys in the instructions immediately
1422 before and after the lifetime of this qty.
1424 Experiments have shown that higher values tend to hurt
1425 overall code performance.
1427 If allocation using the extended lifetime fails we will try
1428 again with the qty's unadjusted lifetime. */
1429 int fake_birth
= MAX (0, qty_birth
[q
] - 2 + qty_birth
[q
] % 2);
1430 int fake_death
= MIN (insn_number
* 2 + 1,
1431 qty_death
[q
] + 2 - qty_death
[q
] % 2);
1434 if (N_REG_CLASSES
> 1)
1436 #ifdef INSN_SCHEDULING
1437 /* We try to avoid using hard registers allocated to qtys which
1438 are born immediately after this qty or die immediately before
1441 This optimization is only appropriate when we will run
1442 a scheduling pass after reload and we are not optimizing
1444 if (flag_schedule_insns_after_reload
1446 && !SMALL_REGISTER_CLASSES
)
1449 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1450 qty_mode
[q
], q
, 0, 0,
1451 fake_birth
, fake_death
);
1452 if (qty_phys_reg
[q
] >= 0)
1456 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1457 qty_mode
[q
], q
, 0, 0,
1458 qty_birth
[q
], qty_death
[q
]);
1459 if (qty_phys_reg
[q
] >= 0)
1463 #ifdef INSN_SCHEDULING
1464 /* Similarly, avoid false dependencies. */
1465 if (flag_schedule_insns_after_reload
1467 && !SMALL_REGISTER_CLASSES
1468 && qty_alternate_class
[q
] != NO_REGS
)
1469 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1470 qty_mode
[q
], q
, 0, 0,
1471 fake_birth
, fake_death
);
1473 if (qty_alternate_class
[q
] != NO_REGS
)
1474 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1475 qty_mode
[q
], q
, 0, 0,
1476 qty_birth
[q
], qty_death
[q
]);
1480 /* Now propagate the register assignments
1481 to the pseudo regs belonging to the qtys. */
1483 for (q
= 0; q
< next_qty
; q
++)
1484 if (qty_phys_reg
[q
] >= 0)
1486 for (i
= qty_first_reg
[q
]; i
>= 0; i
= reg_next_in_qty
[i
])
1487 reg_renumber
[i
] = qty_phys_reg
[q
] + reg_offset
[i
];
1491 free (regs_live_at
);
1495 /* Compare two quantities' priority for getting real registers.
1496 We give shorter-lived quantities higher priority.
1497 Quantities with more references are also preferred, as are quantities that
1498 require multiple registers. This is the identical prioritization as
1499 done by global-alloc.
1501 We used to give preference to registers with *longer* lives, but using
1502 the same algorithm in both local- and global-alloc can speed up execution
1503 of some programs by as much as a factor of three! */
1505 /* Note that the quotient will never be bigger than
1506 the value of floor_log2 times the maximum number of
1507 times a register can occur in one insn (surely less than 100).
1508 Multiplying this by 10000 can't overflow.
1509 QTY_CMP_PRI is also used by qty_sugg_compare. */
1511 #define QTY_CMP_PRI(q) \
1512 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1513 / (qty_death[q] - qty_birth[q])) * 10000))
1516 qty_compare (q1
, q2
)
1519 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1523 qty_compare_1 (q1p
, q2p
)
1527 register int q1
= *(const int *)q1p
, q2
= *(const int *)q2p
;
1528 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1533 /* If qtys are equally good, sort by qty number,
1534 so that the results of qsort leave nothing to chance. */
1538 /* Compare two quantities' priority for getting real registers. This version
1539 is called for quantities that have suggested hard registers. First priority
1540 goes to quantities that have copy preferences, then to those that have
1541 normal preferences. Within those groups, quantities with the lower
1542 number of preferences have the highest priority. Of those, we use the same
1543 algorithm as above. */
1545 #define QTY_CMP_SUGG(q) \
1546 (qty_phys_num_copy_sugg[q] \
1547 ? qty_phys_num_copy_sugg[q] \
1548 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1551 qty_sugg_compare (q1
, q2
)
1554 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1559 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1563 qty_sugg_compare_1 (q1p
, q2p
)
1567 register int q1
= *(const int *)q1p
, q2
= *(const int *)q2p
;
1568 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1573 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1577 /* If qtys are equally good, sort by qty number,
1578 so that the results of qsort leave nothing to chance. */
1585 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1586 Returns 1 if have done so, or 0 if cannot.
1588 Combining registers means marking them as having the same quantity
1589 and adjusting the offsets within the quantity if either of
1592 We don't actually combine a hard reg with a pseudo; instead
1593 we just record the hard reg as the suggestion for the pseudo's quantity.
1594 If we really combined them, we could lose if the pseudo lives
1595 across an insn that clobbers the hard reg (eg, movstr).
1597 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1598 there is no REG_DEAD note on INSN. This occurs during the processing
1599 of REG_NO_CONFLICT blocks.
1601 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1602 SETREG or if the input and output must share a register.
1603 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1605 There are elaborate checks for the validity of combining. */
1609 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1610 rtx usedreg
, setreg
;
1616 register int ureg
, sreg
;
1617 register int offset
= 0;
1621 /* Determine the numbers and sizes of registers being used. If a subreg
1622 is present that does not change the entire register, don't consider
1623 this a copy insn. */
1625 while (GET_CODE (usedreg
) == SUBREG
)
1627 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1629 offset
+= SUBREG_WORD (usedreg
);
1630 usedreg
= SUBREG_REG (usedreg
);
1632 if (GET_CODE (usedreg
) != REG
)
1634 ureg
= REGNO (usedreg
);
1635 usize
= REG_SIZE (usedreg
);
1637 while (GET_CODE (setreg
) == SUBREG
)
1639 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1641 offset
-= SUBREG_WORD (setreg
);
1642 setreg
= SUBREG_REG (setreg
);
1644 if (GET_CODE (setreg
) != REG
)
1646 sreg
= REGNO (setreg
);
1647 ssize
= REG_SIZE (setreg
);
1649 /* If UREG is a pseudo-register that hasn't already been assigned a
1650 quantity number, it means that it is not local to this block or dies
1651 more than once. In either event, we can't do anything with it. */
1652 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1653 /* Do not combine registers unless one fits within the other. */
1654 || (offset
> 0 && usize
+ offset
> ssize
)
1655 || (offset
< 0 && usize
+ offset
< ssize
)
1656 /* Do not combine with a smaller already-assigned object
1657 if that smaller object is already combined with something bigger. */
1658 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1659 && usize
< qty_size
[reg_qty
[ureg
]])
1660 /* Can't combine if SREG is not a register we can allocate. */
1661 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1662 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1663 These have already been taken care of. This probably wouldn't
1664 combine anyway, but don't take any chances. */
1665 || (ureg
>= FIRST_PSEUDO_REGISTER
1666 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1667 /* Don't tie something to itself. In most cases it would make no
1668 difference, but it would screw up if the reg being tied to itself
1669 also dies in this insn. */
1671 /* Don't try to connect two different hardware registers. */
1672 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1673 /* Don't use a hard reg that might be spilled. */
1674 || (ureg
< FIRST_PSEUDO_REGISTER
1675 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg
)))
1676 || (sreg
< FIRST_PSEUDO_REGISTER
1677 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg
)))
1678 /* Don't connect two different machine modes if they have different
1679 implications as to which registers may be used. */
1680 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1683 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1684 qty_phys_sugg for the pseudo instead of tying them.
1686 Return "failure" so that the lifespan of UREG is terminated here;
1687 that way the two lifespans will be disjoint and nothing will prevent
1688 the pseudo reg from being given this hard reg. */
1690 if (ureg
< FIRST_PSEUDO_REGISTER
)
1692 /* Allocate a quantity number so we have a place to put our
1694 if (reg_qty
[sreg
] == -2)
1695 reg_is_born (setreg
, 2 * insn_number
);
1697 if (reg_qty
[sreg
] >= 0)
1700 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1702 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1703 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1705 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1707 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1708 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1714 /* Similarly for SREG a hard register and UREG a pseudo register. */
1716 if (sreg
< FIRST_PSEUDO_REGISTER
)
1719 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1721 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1722 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1724 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1726 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1727 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1732 /* At this point we know that SREG and UREG are both pseudos.
1733 Do nothing if SREG already has a quantity or is a register that we
1735 if (reg_qty
[sreg
] >= -1
1736 /* If we are not going to let any regs live across calls,
1737 don't tie a call-crossing reg to a non-call-crossing reg. */
1738 || (current_function_has_nonlocal_label
1739 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1740 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1743 /* We don't already know about SREG, so tie it to UREG
1744 if this is the last use of UREG, provided the classes they want
1747 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1748 && reg_meets_class_p (sreg
, qty_min_class
[reg_qty
[ureg
]]))
1750 /* Add SREG to UREG's quantity. */
1751 sqty
= reg_qty
[ureg
];
1752 reg_qty
[sreg
] = sqty
;
1753 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1754 reg_next_in_qty
[sreg
] = qty_first_reg
[sqty
];
1755 qty_first_reg
[sqty
] = sreg
;
1757 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1758 update_qty_class (sqty
, sreg
);
1760 /* Update info about quantity SQTY. */
1761 qty_n_calls_crossed
[sqty
] += REG_N_CALLS_CROSSED (sreg
);
1762 qty_n_refs
[sqty
] += REG_N_REFS (sreg
);
1767 for (i
= qty_first_reg
[sqty
]; i
>= 0; i
= reg_next_in_qty
[i
])
1768 reg_offset
[i
] -= offset
;
1770 qty_size
[sqty
] = ssize
;
1771 qty_mode
[sqty
] = GET_MODE (setreg
);
1780 /* Return 1 if the preferred class of REG allows it to be tied
1781 to a quantity or register whose class is CLASS.
1782 True if REG's reg class either contains or is contained in CLASS. */
1785 reg_meets_class_p (reg
, class)
1787 enum reg_class
class;
1789 register enum reg_class rclass
= reg_preferred_class (reg
);
1790 return (reg_class_subset_p (rclass
, class)
1791 || reg_class_subset_p (class, rclass
));
1794 /* Update the class of QTY assuming that REG is being tied to it. */
1797 update_qty_class (qty
, reg
)
1801 enum reg_class rclass
= reg_preferred_class (reg
);
1802 if (reg_class_subset_p (rclass
, qty_min_class
[qty
]))
1803 qty_min_class
[qty
] = rclass
;
1805 rclass
= reg_alternate_class (reg
);
1806 if (reg_class_subset_p (rclass
, qty_alternate_class
[qty
]))
1807 qty_alternate_class
[qty
] = rclass
;
1809 if (REG_CHANGES_SIZE (reg
))
1810 qty_changes_size
[qty
] = 1;
1813 /* Handle something which alters the value of an rtx REG.
1815 REG is whatever is set or clobbered. SETTER is the rtx that
1816 is modifying the register.
1818 If it is not really a register, we do nothing.
1819 The file-global variables `this_insn' and `this_insn_number'
1820 carry info from `block_alloc'. */
1823 reg_is_set (reg
, setter
, data
)
1826 void *data ATTRIBUTE_UNUSED
;
1828 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1829 a hard register. These may actually not exist any more. */
1831 if (GET_CODE (reg
) != SUBREG
1832 && GET_CODE (reg
) != REG
)
1835 /* Mark this register as being born. If it is used in a CLOBBER, mark
1836 it as being born halfway between the previous insn and this insn so that
1837 it conflicts with our inputs but not the outputs of the previous insn. */
1839 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1842 /* Handle beginning of the life of register REG.
1843 BIRTH is the index at which this is happening. */
1846 reg_is_born (reg
, birth
)
1852 if (GET_CODE (reg
) == SUBREG
)
1853 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1855 regno
= REGNO (reg
);
1857 if (regno
< FIRST_PSEUDO_REGISTER
)
1859 mark_life (regno
, GET_MODE (reg
), 1);
1861 /* If the register was to have been born earlier that the present
1862 insn, mark it as live where it is actually born. */
1863 if (birth
< 2 * this_insn_number
)
1864 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1868 if (reg_qty
[regno
] == -2)
1869 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1871 /* If this register has a quantity number, show that it isn't dead. */
1872 if (reg_qty
[regno
] >= 0)
1873 qty_death
[reg_qty
[regno
]] = -1;
1877 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1878 REG is an output that is dying (i.e., it is never used), otherwise it
1879 is an input (the normal case).
1880 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1883 wipe_dead_reg (reg
, output_p
)
1887 register int regno
= REGNO (reg
);
1889 /* If this insn has multiple results,
1890 and the dead reg is used in one of the results,
1891 extend its life to after this insn,
1892 so it won't get allocated together with any other result of this insn.
1894 It is unsafe to use !single_set here since it will ignore an unused
1895 output. Just because an output is unused does not mean the compiler
1896 can assume the side effect will not occur. Consider if REG appears
1897 in the address of an output and we reload the output. If we allocate
1898 REG to the same hard register as an unused output we could set the hard
1899 register before the output reload insn. */
1900 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1901 && multiple_sets (this_insn
))
1904 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1906 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1907 if (GET_CODE (set
) == SET
1908 && GET_CODE (SET_DEST (set
)) != REG
1909 && !rtx_equal_p (reg
, SET_DEST (set
))
1910 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1915 /* If this register is used in an auto-increment address, then extend its
1916 life to after this insn, so that it won't get allocated together with
1917 the result of this insn. */
1918 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
1921 if (regno
< FIRST_PSEUDO_REGISTER
)
1923 mark_life (regno
, GET_MODE (reg
), 0);
1925 /* If a hard register is dying as an output, mark it as in use at
1926 the beginning of this insn (the above statement would cause this
1929 post_mark_life (regno
, GET_MODE (reg
), 1,
1930 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1933 else if (reg_qty
[regno
] >= 0)
1934 qty_death
[reg_qty
[regno
]] = 2 * this_insn_number
+ output_p
;
1937 /* Find a block of SIZE words of hard regs in reg_class CLASS
1938 that can hold something of machine-mode MODE
1939 (but actually we test only the first of the block for holding MODE)
1940 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1941 and return the number of the first of them.
1942 Return -1 if such a block cannot be found.
1943 If QTY crosses calls, insist on a register preserved by calls,
1944 unless ACCEPT_CALL_CLOBBERED is nonzero.
1946 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1947 register is available. If not, return -1. */
1950 find_free_reg (class, mode
, qty
, accept_call_clobbered
, just_try_suggested
,
1951 born_index
, dead_index
)
1952 enum reg_class
class;
1953 enum machine_mode mode
;
1955 int accept_call_clobbered
;
1956 int just_try_suggested
;
1957 int born_index
, dead_index
;
1959 register int i
, ins
;
1961 register /* Declare it register if it's a scalar. */
1963 HARD_REG_SET used
, first_used
;
1964 #ifdef ELIMINABLE_REGS
1965 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1968 /* Validate our parameters. */
1969 if (born_index
< 0 || born_index
> dead_index
)
1972 /* Don't let a pseudo live in a reg across a function call
1973 if we might get a nonlocal goto. */
1974 if (current_function_has_nonlocal_label
1975 && qty_n_calls_crossed
[qty
] > 0)
1978 if (accept_call_clobbered
)
1979 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1980 else if (qty_n_calls_crossed
[qty
] == 0)
1981 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1983 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1985 if (accept_call_clobbered
)
1986 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
1988 for (ins
= born_index
; ins
< dead_index
; ins
++)
1989 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1991 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1993 /* Don't use the frame pointer reg in local-alloc even if
1994 we may omit the frame pointer, because if we do that and then we
1995 need a frame pointer, reload won't know how to move the pseudo
1996 to another hard reg. It can move only regs made by global-alloc.
1998 This is true of any register that can be eliminated. */
1999 #ifdef ELIMINABLE_REGS
2000 for (i
= 0; i
< (int)(sizeof eliminables
/ sizeof eliminables
[0]); i
++)
2001 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2002 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2003 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2004 that it might be eliminated into. */
2005 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2008 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2011 #ifdef CLASS_CANNOT_CHANGE_SIZE
2012 if (qty_changes_size
[qty
])
2013 IOR_HARD_REG_SET (used
,
2014 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
]);
2017 /* Normally, the registers that can be used for the first register in
2018 a multi-register quantity are the same as those that can be used for
2019 subsequent registers. However, if just trying suggested registers,
2020 restrict our consideration to them. If there are copy-suggested
2021 register, try them. Otherwise, try the arithmetic-suggested
2023 COPY_HARD_REG_SET (first_used
, used
);
2025 if (just_try_suggested
)
2027 if (qty_phys_num_copy_sugg
[qty
] != 0)
2028 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qty
]);
2030 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qty
]);
2033 /* If all registers are excluded, we can't do anything. */
2034 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2036 /* If at least one would be suitable, test each hard reg. */
2038 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2040 #ifdef REG_ALLOC_ORDER
2041 int regno
= reg_alloc_order
[i
];
2045 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2046 && HARD_REGNO_MODE_OK (regno
, mode
)
2047 && (qty_n_calls_crossed
[qty
] == 0
2048 || accept_call_clobbered
2049 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2052 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2053 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2056 /* Mark that this register is in use between its birth and death
2058 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2061 #ifndef REG_ALLOC_ORDER
2062 i
+= j
; /* Skip starting points we know will lose */
2069 /* If we are just trying suggested register, we have just tried copy-
2070 suggested registers, and there are arithmetic-suggested registers,
2073 /* If it would be profitable to allocate a call-clobbered register
2074 and save and restore it around calls, do that. */
2075 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qty
] != 0
2076 && qty_phys_num_sugg
[qty
] != 0)
2078 /* Don't try the copy-suggested regs again. */
2079 qty_phys_num_copy_sugg
[qty
] = 0;
2080 return find_free_reg (class, mode
, qty
, accept_call_clobbered
, 1,
2081 born_index
, dead_index
);
2084 /* We need not check to see if the current function has nonlocal
2085 labels because we don't put any pseudos that are live over calls in
2086 registers in that case. */
2088 if (! accept_call_clobbered
2089 && flag_caller_saves
2090 && ! just_try_suggested
2091 && qty_n_calls_crossed
[qty
] != 0
2092 && CALLER_SAVE_PROFITABLE (qty_n_refs
[qty
], qty_n_calls_crossed
[qty
]))
2094 i
= find_free_reg (class, mode
, qty
, 1, 0, born_index
, dead_index
);
2096 caller_save_needed
= 1;
2102 /* Mark that REGNO with machine-mode MODE is live starting from the current
2103 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2107 mark_life (regno
, mode
, life
)
2109 enum machine_mode mode
;
2112 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2115 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2118 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2121 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2122 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2123 to insn number DEATH (exclusive). */
2126 post_mark_life (regno
, mode
, life
, birth
, death
)
2128 enum machine_mode mode
;
2129 int life
, birth
, death
;
2131 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2133 register /* Declare it register if it's a scalar. */
2135 HARD_REG_SET this_reg
;
2137 CLEAR_HARD_REG_SET (this_reg
);
2139 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2142 while (birth
< death
)
2144 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2148 while (birth
< death
)
2150 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2155 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2156 is the register being clobbered, and R1 is a register being used in
2157 the equivalent expression.
2159 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2160 in which it is used, return 1.
2162 Otherwise, return 0. */
2165 no_conflict_p (insn
, r0
, r1
)
2169 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2172 /* If R1 is a hard register, return 0 since we handle this case
2173 when we scan the insns that actually use it. */
2176 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2177 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2178 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2181 last
= XEXP (note
, 0);
2183 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2184 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
2186 if (find_reg_note (p
, REG_DEAD
, r1
))
2189 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2190 some earlier optimization pass has inserted instructions into
2191 the sequence, and it is not safe to perform this optimization.
2192 Note that emit_no_conflict_block always ensures that this is
2193 true when these sequences are created. */
2194 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2201 /* Return the number of alternatives for which the constraint string P
2202 indicates that the operand must be equal to operand 0 and that no register
2211 int reg_allowed
= 0;
2212 int num_matching_alts
= 0;
2217 case '=': case '+': case '?':
2218 case '#': case '&': case '!':
2220 case '1': case '2': case '3': case '4': case '5':
2221 case '6': case '7': case '8': case '9':
2222 case 'm': case '<': case '>': case 'V': case 'o':
2223 case 'E': case 'F': case 'G': case 'H':
2224 case 's': case 'i': case 'n':
2225 case 'I': case 'J': case 'K': case 'L':
2226 case 'M': case 'N': case 'O': case 'P':
2227 #ifdef EXTRA_CONSTRAINT
2228 case 'Q': case 'R': case 'S': case 'T': case 'U':
2231 /* These don't say anything we care about. */
2235 if (found_zero
&& ! reg_allowed
)
2236 num_matching_alts
++;
2238 found_zero
= reg_allowed
= 0;
2252 if (found_zero
&& ! reg_allowed
)
2253 num_matching_alts
++;
2255 return num_matching_alts
;
2259 dump_local_alloc (file
)
2263 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2264 if (reg_renumber
[i
] != -1)
2265 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);