1 /* IRA hard register and memory cost calculation for allocnos.
2 Copyright (C) 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
41 /* The file contains code is similar to one in regclass but the code
42 works on the allocno basis. */
44 #ifdef FORBIDDEN_INC_DEC_CLASSES
45 /* Indexed by n, is TRUE if allocno with number N is used in an
46 auto-inc or auto-dec context. */
47 static bool *in_inc_dec
;
50 /* The `costs' struct records the cost of using hard registers of each
51 class considered for the calculation and of using memory for each
56 /* Costs for register classes start here. We process only some
57 register classes (cover classes on the 1st cost calculation
58 iteration and important classes on the 2nd iteration). */
62 /* Initialized once. It is a maximal possible size of the allocated
64 static int max_struct_costs_size
;
66 /* Allocated and initialized once, and used to initialize cost values
68 static struct costs
*init_cost
;
70 /* Allocated once, and used for temporary purposes. */
71 static struct costs
*temp_costs
;
73 /* Allocated once, and used for the cost calculation. */
74 static struct costs
*op_costs
[MAX_RECOG_OPERANDS
];
75 static struct costs
*this_op_costs
[MAX_RECOG_OPERANDS
];
77 /* Original and accumulated costs of each class for each allocno. */
78 static struct costs
*allocno_costs
, *total_costs
;
80 /* Classes used for cost calculation. They may be different on
81 different iterations of the cost calculations or in different
82 optimization modes. */
83 static enum reg_class
*cost_classes
;
85 /* The size of the previous array. */
86 static int cost_classes_num
;
88 /* Map: cost class -> order number (they start with 0) of the cost
89 class. The order number is negative for non-cost classes. */
90 static int cost_class_nums
[N_REG_CLASSES
];
92 /* It is the current size of struct costs. */
93 static int struct_costs_size
;
95 /* Return pointer to structure containing costs of allocno with given
97 #define COSTS_OF_ALLOCNO(arr, num) \
98 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
100 /* Record register class preferences of each allocno. Null value
101 means no preferences. It happens on the 1st iteration of the cost
103 static enum reg_class
*allocno_pref
;
105 /* Allocated buffers for allocno_pref. */
106 static enum reg_class
*allocno_pref_buffer
;
108 /* Execution frequency of the current insn. */
109 static int frequency
;
113 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
114 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
115 be a pseudo register. */
117 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class rclass
, bool to_p
,
118 secondary_reload_info
*prev_sri
)
120 secondary_reload_info sri
;
121 enum reg_class secondary_class
= NO_REGS
;
123 /* If X is a SCRATCH, there is actually nothing to move since we are
124 assuming optimal allocation. */
125 if (GET_CODE (x
) == SCRATCH
)
128 /* Get the class we will actually use for a reload. */
129 rclass
= PREFERRED_RELOAD_CLASS (x
, rclass
);
131 /* If we need a secondary reload for an intermediate, the cost is
132 that to load the input into the intermediate register, then to
134 sri
.prev_sri
= prev_sri
;
136 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
138 if (ira_register_move_cost
[mode
] == NULL
)
139 ira_init_register_move_cost (mode
);
141 if (secondary_class
!= NO_REGS
)
142 return (move_cost
[mode
][secondary_class
][rclass
] + sri
.extra_cost
143 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
145 /* For memory, use the memory move cost, for (hard) registers, use
146 the cost to move between the register classes, and use 2 for
147 everything else (constants). */
148 if (MEM_P (x
) || rclass
== NO_REGS
)
149 return sri
.extra_cost
+ ira_memory_move_cost
[mode
][rclass
][to_p
!= 0];
152 (sri
.extra_cost
+ move_cost
[mode
][REGNO_REG_CLASS (REGNO (x
))][rclass
]);
154 /* If this is a constant, we may eventually want to call rtx_cost
156 return sri
.extra_cost
+ COSTS_N_INSNS (1);
161 /* Record the cost of using memory or hard registers of various
162 classes for the operands in INSN.
164 N_ALTS is the number of alternatives.
165 N_OPS is the number of operands.
166 OPS is an array of the operands.
167 MODES are the modes of the operands, in case any are VOIDmode.
168 CONSTRAINTS are the constraints to use for the operands. This array
169 is modified by this procedure.
171 This procedure works alternative by alternative. For each
172 alternative we assume that we will be able to allocate all allocnos
173 to their ideal register class and calculate the cost of using that
174 alternative. Then we compute, for each operand that is a
175 pseudo-register, the cost of having the allocno allocated to each
176 register class and using it in that alternative. To this cost is
177 added the cost of the alternative.
179 The cost of each class for this insn is its lowest cost among all
182 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
183 enum machine_mode
*modes
, const char **constraints
,
184 rtx insn
, struct costs
**op_costs
,
185 enum reg_class
*allocno_pref
)
190 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
192 for (i
= 0; i
< n_ops
; i
++)
193 insn_allows_mem
[i
] = 0;
195 /* Process each alternative, each time minimizing an operand's cost
196 with the cost for each operand in that alternative. */
197 for (alt
= 0; alt
< n_alts
; alt
++)
199 enum reg_class classes
[MAX_RECOG_OPERANDS
];
200 int allows_mem
[MAX_RECOG_OPERANDS
];
203 int alt_cost
= 0, op_cost_add
;
205 for (i
= 0; i
< n_ops
; i
++)
208 const char *p
= constraints
[i
];
210 enum machine_mode mode
= modes
[i
];
214 /* Initially show we know nothing about the register class. */
215 classes
[i
] = NO_REGS
;
218 /* If this operand has no constraints at all, we can
219 conclude nothing about it since anything is valid. */
222 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
223 memset (this_op_costs
[i
], 0, struct_costs_size
);
227 /* If this alternative is only relevant when this operand
228 matches a previous operand, we do different things
229 depending on whether this operand is a allocno-reg or not.
230 We must process any modifiers for the operand before we
231 can make this test. */
232 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
235 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
237 /* Copy class and whether memory is allowed from the
238 matching alternative. Then perform any needed cost
239 computations and/or adjustments. */
241 classes
[i
] = classes
[j
];
242 allows_mem
[i
] = allows_mem
[j
];
244 insn_allows_mem
[i
] = 1;
246 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
248 /* If this matches the other operand, we have no
249 added cost and we win. */
250 if (rtx_equal_p (ops
[j
], op
))
252 /* If we can put the other operand into a register,
253 add to the cost of this alternative the cost to
254 copy this operand to the register used for the
256 else if (classes
[j
] != NO_REGS
)
258 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
262 else if (! REG_P (ops
[j
])
263 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
265 /* This op is an allocno but the one it matches is
268 /* If we can't put the other operand into a
269 register, this alternative can't be used. */
271 if (classes
[j
] == NO_REGS
)
273 /* Otherwise, add to the cost of this alternative
274 the cost to copy the other operand to the hard
275 register used for this operand. */
277 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
281 /* The costs of this operand are not the same as the
282 other operand since move costs are not symmetric.
283 Moreover, if we cannot tie them, this alternative
284 needs to do a copy, which is one insn. */
285 struct costs
*pp
= this_op_costs
[i
];
287 if (ira_register_move_cost
[mode
] == NULL
)
288 ira_init_register_move_cost (mode
);
290 for (k
= 0; k
< cost_classes_num
; k
++)
292 rclass
= cost_classes
[k
];
294 = ((recog_data
.operand_type
[i
] != OP_OUT
295 ? ira_may_move_in_cost
[mode
][rclass
]
296 [classes
[i
]] * frequency
: 0)
297 + (recog_data
.operand_type
[i
] != OP_IN
298 ? ira_may_move_out_cost
[mode
][classes
[i
]]
299 [rclass
] * frequency
: 0));
302 /* If the alternative actually allows memory, make
303 things a bit cheaper since we won't need an extra
306 = ((recog_data
.operand_type
[i
] != OP_IN
307 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
308 + (recog_data
.operand_type
[i
] != OP_OUT
309 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
310 - allows_mem
[i
]) * frequency
;
312 /* If we have assigned a class to this allocno in our
313 first pass, add a cost to this alternative
314 corresponding to what we would add if this allocno
315 were not in the appropriate class. We could use
316 cover class here but it is less accurate
320 enum reg_class pref_class
321 = allocno_pref
[ALLOCNO_NUM
322 (ira_curr_regno_allocno_map
325 if (pref_class
== NO_REGS
)
327 += ((recog_data
.operand_type
[i
] != OP_IN
328 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
330 + (recog_data
.operand_type
[i
] != OP_OUT
331 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
333 else if (ira_reg_class_intersect
334 [pref_class
][classes
[i
]] == NO_REGS
)
335 alt_cost
+= (ira_register_move_cost
336 [mode
][pref_class
][classes
[i
]]);
338 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
339 && ! find_reg_note (insn
, REG_DEAD
, op
))
342 /* This is in place of ordinary cost computation for
343 this operand, so skip to the end of the
344 alternative (should be just one character). */
345 while (*p
&& *p
++ != ',')
353 /* Scan all the constraint letters. See if the operand
354 matches any of the constraints. Collect the valid
355 register classes and see if this operand accepts
364 /* Ignore the next letter for this pass. */
370 case '!': case '#': case '&':
371 case '0': case '1': case '2': case '3': case '4':
372 case '5': case '6': case '7': case '8': case '9':
377 win
= address_operand (op
, GET_MODE (op
));
378 /* We know this operand is an address, so we want it
379 to be allocated to a register that can be the
380 base of an address, i.e. BASE_REG_CLASS. */
382 = ira_reg_class_union
[classes
[i
]]
383 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
386 case 'm': case 'o': case 'V':
387 /* It doesn't seem worth distinguishing between
388 offsettable and non-offsettable addresses
390 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
397 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
398 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
404 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
405 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
411 if (GET_CODE (op
) == CONST_DOUBLE
412 || (GET_CODE (op
) == CONST_VECTOR
413 && (GET_MODE_CLASS (GET_MODE (op
))
414 == MODE_VECTOR_FLOAT
)))
420 if (GET_CODE (op
) == CONST_DOUBLE
421 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
426 if (GET_CODE (op
) == CONST_INT
427 || (GET_CODE (op
) == CONST_DOUBLE
428 && GET_MODE (op
) == VOIDmode
))
433 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
438 if (GET_CODE (op
) == CONST_INT
439 || (GET_CODE (op
) == CONST_DOUBLE
440 && GET_MODE (op
) == VOIDmode
))
452 if (GET_CODE (op
) == CONST_INT
453 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
464 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
466 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
468 classes
[i
] = ira_reg_class_union
[classes
[i
]][GENERAL_REGS
];
472 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
473 classes
[i
] = ira_reg_class_union
[classes
[i
]]
474 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
475 #ifdef EXTRA_CONSTRAINT_STR
476 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
479 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
481 /* Every MEM can be reloaded to fit. */
482 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
486 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
488 /* Every address can be reloaded to fit. */
490 if (address_operand (op
, GET_MODE (op
)))
492 /* We know this operand is an address, so we
493 want it to be allocated to a hard register
494 that can be the base of an address,
495 i.e. BASE_REG_CLASS. */
497 = ira_reg_class_union
[classes
[i
]]
498 [base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
503 p
+= CONSTRAINT_LEN (c
, p
);
510 /* How we account for this operand now depends on whether it
511 is a pseudo register or not. If it is, we first check if
512 any register classes are valid. If not, we ignore this
513 alternative, since we want to assume that all allocnos get
514 allocated for register preferencing. If some register
515 class is valid, compute the costs of moving the allocno
517 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
519 if (classes
[i
] == NO_REGS
)
521 /* We must always fail if the operand is a REG, but
522 we did not find a suitable class.
524 Otherwise we may perform an uninitialized read
525 from this_op_costs after the `continue' statement
531 struct costs
*pp
= this_op_costs
[i
];
533 if (ira_register_move_cost
[mode
] == NULL
)
534 ira_init_register_move_cost (mode
);
536 for (k
= 0; k
< cost_classes_num
; k
++)
538 rclass
= cost_classes
[k
];
540 = ((recog_data
.operand_type
[i
] != OP_OUT
541 ? ira_may_move_in_cost
[mode
][rclass
]
542 [classes
[i
]] * frequency
: 0)
543 + (recog_data
.operand_type
[i
] != OP_IN
544 ? ira_may_move_out_cost
[mode
][classes
[i
]]
545 [rclass
] * frequency
: 0));
548 /* If the alternative actually allows memory, make
549 things a bit cheaper since we won't need an extra
552 = ((recog_data
.operand_type
[i
] != OP_IN
553 ? ira_memory_move_cost
[mode
][classes
[i
]][0] : 0)
554 + (recog_data
.operand_type
[i
] != OP_OUT
555 ? ira_memory_move_cost
[mode
][classes
[i
]][1] : 0)
556 - allows_mem
[i
]) * frequency
;
557 /* If we have assigned a class to this allocno in our
558 first pass, add a cost to this alternative
559 corresponding to what we would add if this allocno
560 were not in the appropriate class. We could use
561 cover class here but it is less accurate
565 enum reg_class pref_class
566 = allocno_pref
[ALLOCNO_NUM
567 (ira_curr_regno_allocno_map
570 if (pref_class
== NO_REGS
)
572 += ((recog_data
.operand_type
[i
] != OP_IN
573 ? ira_memory_move_cost
[mode
][classes
[i
]][0]
575 + (recog_data
.operand_type
[i
] != OP_OUT
576 ? ira_memory_move_cost
[mode
][classes
[i
]][1]
578 else if (ira_reg_class_intersect
[pref_class
][classes
[i
]]
580 alt_cost
+= (ira_register_move_cost
581 [mode
][pref_class
][classes
[i
]]);
586 /* Otherwise, if this alternative wins, either because we
587 have already determined that or if we have a hard
588 register of the proper class, there is no cost for this
590 else if (win
|| (REG_P (op
)
591 && reg_fits_class_p (op
, classes
[i
],
595 /* If registers are valid, the cost of this alternative
596 includes copying the object to and/or from a
598 else if (classes
[i
] != NO_REGS
)
600 if (recog_data
.operand_type
[i
] != OP_OUT
)
601 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
603 if (recog_data
.operand_type
[i
] != OP_IN
)
604 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
606 /* The only other way this alternative can be used is if
607 this is a constant that could be placed into memory. */
608 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
609 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
617 op_cost_add
= alt_cost
* frequency
;
618 /* Finally, update the costs with the information we've
619 calculated about this alternative. */
620 for (i
= 0; i
< n_ops
; i
++)
621 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
623 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
624 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
626 pp
->mem_cost
= MIN (pp
->mem_cost
,
627 (qq
->mem_cost
+ op_cost_add
) * scale
);
629 for (k
= 0; k
< cost_classes_num
; k
++)
631 = MIN (pp
->cost
[k
], (qq
->cost
[k
] + op_cost_add
) * scale
);
635 for (i
= 0; i
< n_ops
; i
++)
640 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
642 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
643 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
644 ALLOCNO_BAD_SPILL_P (a
) = true;
647 /* If this insn is a single set copying operand 1 to operand 0 and
648 one operand is an allocno with the other a hard reg or an allocno
649 that prefers a hard register that is in its own register class
650 then we may want to adjust the cost of that register class to -1.
652 Avoid the adjustment if the source does not die to avoid
653 stressing of register allocator by preferrencing two colliding
654 registers into single class.
656 Also avoid the adjustment if a copy between hard registers of the
657 class is expensive (ten times the cost of a default copy is
658 considered arbitrarily expensive). This avoids losing when the
659 preferred class is very expensive as the source of a copy
661 if ((set
= single_set (insn
)) != 0
662 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
663 && REG_P (ops
[0]) && REG_P (ops
[1])
664 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
665 for (i
= 0; i
<= 1; i
++)
666 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
668 unsigned int regno
= REGNO (ops
[!i
]);
669 enum machine_mode mode
= GET_MODE (ops
[!i
]);
673 if (regno
< FIRST_PSEUDO_REGISTER
)
674 for (k
= 0; k
< cost_classes_num
; k
++)
676 rclass
= cost_classes
[k
];
677 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
678 && (reg_class_size
[rclass
]
679 == (unsigned) CLASS_MAX_NREGS (rclass
, mode
)))
681 if (reg_class_size
[rclass
] == 1)
682 op_costs
[i
]->cost
[k
] = -frequency
;
686 nr
< (unsigned) hard_regno_nregs
[regno
][mode
];
688 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
692 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
693 op_costs
[i
]->cost
[k
] = -frequency
;
702 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
704 ok_for_index_p_nonstrict (rtx reg
)
706 unsigned regno
= REGNO (reg
);
708 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
711 /* A version of regno_ok_for_base_p for use here, when all
712 pseudo-registers should count as OK. Arguments as for
713 regno_ok_for_base_p. */
715 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
716 enum rtx_code outer_code
, enum rtx_code index_code
)
718 unsigned regno
= REGNO (reg
);
720 if (regno
>= FIRST_PSEUDO_REGISTER
)
722 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
725 /* Record the pseudo registers we must reload into hard registers in a
726 subexpression of a memory address, X.
728 If CONTEXT is 0, we are looking at the base part of an address,
729 otherwise we are looking at the index part.
731 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
732 give the context that the rtx appears in. These three arguments
733 are passed down to base_reg_class.
735 SCALE is twice the amount to multiply the cost by (it is twice so
736 we can represent half-cost adjustments). */
738 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
739 enum rtx_code outer_code
, enum rtx_code index_code
,
742 enum rtx_code code
= GET_CODE (x
);
743 enum reg_class rclass
;
746 rclass
= INDEX_REG_CLASS
;
748 rclass
= base_reg_class (mode
, outer_code
, index_code
);
761 /* When we have an address that is a sum, we must determine
762 whether registers are "base" or "index" regs. If there is a
763 sum of two registers, we must choose one to be the "base".
764 Luckily, we can use the REG_POINTER to make a good choice
765 most of the time. We only need to do this on machines that
766 can have two registers in an address and where the base and
767 index register classes are different.
769 ??? This code used to set REGNO_POINTER_FLAG in some cases,
770 but that seems bogus since it should only be set when we are
771 sure the register is being used as a pointer. */
773 rtx arg0
= XEXP (x
, 0);
774 rtx arg1
= XEXP (x
, 1);
775 enum rtx_code code0
= GET_CODE (arg0
);
776 enum rtx_code code1
= GET_CODE (arg1
);
778 /* Look inside subregs. */
780 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
782 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
784 /* If this machine only allows one register per address, it
785 must be in the first operand. */
786 if (MAX_REGS_PER_ADDRESS
== 1)
787 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
789 /* If index and base registers are the same on this machine,
790 just record registers in any non-constant operands. We
791 assume here, as well as in the tests below, that all
792 addresses are in canonical form. */
793 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
795 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
796 if (! CONSTANT_P (arg1
))
797 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
800 /* If the second operand is a constant integer, it doesn't
801 change what class the first operand must be. */
802 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
803 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
804 /* If the second operand is a symbolic constant, the first
805 operand must be an index register. */
806 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
807 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
808 /* If both operands are registers but one is already a hard
809 register of index or reg-base class, give the other the
810 class that the hard register is not. */
811 else if (code0
== REG
&& code1
== REG
812 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
813 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
814 || ok_for_index_p_nonstrict (arg0
)))
815 record_address_regs (mode
, arg1
,
816 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
819 else if (code0
== REG
&& code1
== REG
820 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
821 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
822 || ok_for_index_p_nonstrict (arg1
)))
823 record_address_regs (mode
, arg0
,
824 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
827 /* If one operand is known to be a pointer, it must be the
828 base with the other operand the index. Likewise if the
829 other operand is a MULT. */
830 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
832 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
833 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
835 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
837 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
838 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
840 /* Otherwise, count equal chances that each might be a base or
841 index register. This case should be rare. */
844 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
845 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
846 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
847 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
852 /* Double the importance of an allocno that is incremented or
853 decremented, since it would take two extra insns if it ends
854 up in the wrong place. */
857 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
858 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
859 if (REG_P (XEXP (XEXP (x
, 1), 1)))
860 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
868 /* Double the importance of an allocno that is incremented or
869 decremented, since it would take two extra insns if it ends
870 up in the wrong place. If the operand is a pseudo-register,
871 show it is being used in an INC_DEC context. */
872 #ifdef FORBIDDEN_INC_DEC_CLASSES
873 if (REG_P (XEXP (x
, 0))
874 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
875 in_inc_dec
[ALLOCNO_NUM (ira_curr_regno_allocno_map
876 [REGNO (XEXP (x
, 0))])] = true;
878 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
886 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
889 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[REGNO (x
)]) = true;
890 pp
= COSTS_OF_ALLOCNO (allocno_costs
,
891 ALLOCNO_NUM (ira_curr_regno_allocno_map
893 pp
->mem_cost
+= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
894 if (ira_register_move_cost
[Pmode
] == NULL
)
895 ira_init_register_move_cost (Pmode
);
896 for (k
= 0; k
< cost_classes_num
; k
++)
900 += (ira_may_move_in_cost
[Pmode
][i
][rclass
] * scale
) / 2;
907 const char *fmt
= GET_RTX_FORMAT (code
);
909 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
911 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
919 /* Calculate the costs of insn operands. */
921 record_operand_costs (rtx insn
, struct costs
**op_costs
,
922 enum reg_class
*allocno_pref
)
924 const char *constraints
[MAX_RECOG_OPERANDS
];
925 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
928 for (i
= 0; i
< recog_data
.n_operands
; i
++)
930 constraints
[i
] = recog_data
.constraints
[i
];
931 modes
[i
] = recog_data
.operand_mode
[i
];
934 /* If we get here, we are set up to record the costs of all the
935 operands for this insn. Start by initializing the costs. Then
936 handle any address registers. Finally record the desired classes
937 for any allocnos, doing it twice if some pair of operands are
939 for (i
= 0; i
< recog_data
.n_operands
; i
++)
941 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
943 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
944 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
946 if (MEM_P (recog_data
.operand
[i
]))
947 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
948 XEXP (recog_data
.operand
[i
], 0),
949 0, MEM
, SCRATCH
, frequency
* 2);
950 else if (constraints
[i
][0] == 'p'
951 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
953 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
954 SCRATCH
, frequency
* 2);
957 /* Check for commutative in a separate loop so everything will have
958 been initialized. We must do this even if one operand is a
959 constant--see addsi3 in m68k.md. */
960 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
961 if (constraints
[i
][0] == '%')
963 const char *xconstraints
[MAX_RECOG_OPERANDS
];
966 /* Handle commutative operands by swapping the constraints.
967 We assume the modes are the same. */
968 for (j
= 0; j
< recog_data
.n_operands
; j
++)
969 xconstraints
[j
] = constraints
[j
];
971 xconstraints
[i
] = constraints
[i
+1];
972 xconstraints
[i
+1] = constraints
[i
];
973 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
974 recog_data
.operand
, modes
,
975 xconstraints
, insn
, op_costs
, allocno_pref
);
977 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
978 recog_data
.operand
, modes
,
979 constraints
, insn
, op_costs
, allocno_pref
);
984 /* Process one insn INSN. Scan it and record each time it would save
985 code to put a certain allocnos in a certain class. Return the last
986 insn processed, so that the scan can be continued from there. */
988 scan_one_insn (rtx insn
)
990 enum rtx_code pat_code
;
997 pat_code
= GET_CODE (PATTERN (insn
));
998 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
999 || pat_code
== ADDR_VEC
|| pat_code
== ADDR_DIFF_VEC
)
1002 set
= single_set (insn
);
1003 extract_insn (insn
);
1005 /* If this insn loads a parameter from its stack slot, then it
1006 represents a savings, rather than a cost, if the parameter is
1007 stored in memory. Record this fact. */
1008 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1009 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1010 && MEM_P (XEXP (note
, 0)))
1012 enum reg_class cl
= GENERAL_REGS
;
1013 rtx reg
= SET_DEST (set
);
1014 int num
= ALLOCNO_NUM (ira_curr_regno_allocno_map
[REGNO (reg
)]);
1017 cl
= allocno_pref
[num
];
1018 COSTS_OF_ALLOCNO (allocno_costs
, num
)->mem_cost
1019 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1020 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
1021 0, MEM
, SCRATCH
, frequency
* 2);
1024 record_operand_costs (insn
, op_costs
, allocno_pref
);
1026 /* Now add the cost for each operand to the total costs for its
1028 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1029 if (REG_P (recog_data
.operand
[i
])
1030 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1032 int regno
= REGNO (recog_data
.operand
[i
]);
1034 = COSTS_OF_ALLOCNO (allocno_costs
,
1035 ALLOCNO_NUM (ira_curr_regno_allocno_map
[regno
]));
1036 struct costs
*q
= op_costs
[i
];
1038 p
->mem_cost
+= q
->mem_cost
;
1039 for (k
= 0; k
< cost_classes_num
; k
++)
1040 p
->cost
[k
] += q
->cost
[k
];
1048 /* Print allocnos costs to file F. */
1050 print_costs (FILE *f
)
1054 ira_allocno_iterator ai
;
1057 FOR_EACH_ALLOCNO (a
, ai
)
1061 int regno
= ALLOCNO_REGNO (a
);
1063 i
= ALLOCNO_NUM (a
);
1064 fprintf (f
, " a%d(r%d,", i
, regno
);
1065 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1066 fprintf (f
, "b%d", bb
->index
);
1068 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1069 fprintf (f
, ") costs:");
1070 for (k
= 0; k
< cost_classes_num
; k
++)
1072 rclass
= cost_classes
[k
];
1073 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1074 #ifdef FORBIDDEN_INC_DEC_CLASSES
1075 && (! in_inc_dec
[i
] || ! forbidden_inc_dec_class
[rclass
])
1077 #ifdef CANNOT_CHANGE_MODE_CLASS
1078 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
,
1079 PSEUDO_REGNO_MODE (regno
))
1083 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1084 COSTS_OF_ALLOCNO (allocno_costs
, i
)->cost
[k
]);
1085 if (flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1086 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1087 fprintf (f
, ",%d", COSTS_OF_ALLOCNO (total_costs
, i
)->cost
[k
]);
1090 fprintf (f
, " MEM:%i\n", COSTS_OF_ALLOCNO (allocno_costs
, i
)->mem_cost
);
1094 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1097 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1102 bb
= loop_tree_node
->bb
;
1105 frequency
= REG_FREQ_FROM_BB (bb
);
1108 FOR_BB_INSNS (bb
, insn
)
1109 insn
= scan_one_insn (insn
);
1112 /* Find costs of register classes and memory for allocnos and their
1115 find_allocno_class_costs (void)
1122 #ifdef FORBIDDEN_INC_DEC_CLASSES
1123 in_inc_dec
= ira_allocate (sizeof (bool) * ira_allocnos_num
);
1124 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1125 allocno_pref
= NULL
;
1126 /* Normally we scan the insns once and determine the best class to
1127 use for each allocno. However, if -fexpensive-optimizations are
1128 on, we do so twice, the second time using the tentative best
1129 classes to guide the selection. */
1130 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1132 if (internal_flag_ira_verbose
> 0 && ira_dump_file
)
1133 fprintf (ira_dump_file
, "\nPass %i for finding allocno costs\n\n",
1135 /* We could use only cover classes. Unfortunately it does not
1136 work well for some targets where some subclass of cover class
1137 is costly and wrong cover class is chosen. */
1138 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1139 cost_class_nums
[i
] = -1;
1140 for (cost_classes_num
= 0;
1141 cost_classes_num
< ira_important_classes_num
;
1144 cost_classes
[cost_classes_num
]
1145 = ira_important_classes
[cost_classes_num
];
1146 cost_class_nums
[cost_classes
[cost_classes_num
]]
1150 = sizeof (struct costs
) + sizeof (int) * (cost_classes_num
- 1);
1151 /* Zero out our accumulation of the cost of each class for each
1153 memset (allocno_costs
, 0, ira_allocnos_num
* struct_costs_size
);
1154 #ifdef FORBIDDEN_INC_DEC_CLASSES
1155 memset (in_inc_dec
, 0, ira_allocnos_num
* sizeof (bool));
1158 /* Scan the instructions and record each time it would save code
1159 to put a certain allocno in a certain class. */
1160 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1161 process_bb_node_for_costs
, NULL
);
1163 memcpy (total_costs
, allocno_costs
,
1164 max_struct_costs_size
* ira_allocnos_num
);
1166 allocno_pref
= allocno_pref_buffer
;
1168 /* Now for each allocno look at how desirable each class is and
1169 find which class is preferred. */
1170 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1172 ira_allocno_t a
, parent_a
;
1173 int rclass
, a_num
, parent_a_num
;
1174 ira_loop_tree_node_t parent
;
1176 enum reg_class best
, alt_class
, common_class
;
1177 #ifdef FORBIDDEN_INC_DEC_CLASSES
1178 int inc_dec_p
= false;
1181 if (ira_regno_allocno_map
[i
] == NULL
)
1183 memset (temp_costs
, 0, struct_costs_size
);
1184 /* Find cost of all allocnos with the same regno. */
1185 for (a
= ira_regno_allocno_map
[i
];
1187 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1189 a_num
= ALLOCNO_NUM (a
);
1190 if ((flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1191 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
)
1192 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1193 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1194 /* There are no caps yet. */
1195 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE (a
)->border_allocnos
,
1198 /* Propagate costs to upper levels in the region
1200 parent_a_num
= ALLOCNO_NUM (parent_a
);
1201 for (k
= 0; k
< cost_classes_num
; k
++)
1202 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->cost
[k
]
1203 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1204 COSTS_OF_ALLOCNO (total_costs
, parent_a_num
)->mem_cost
1205 += COSTS_OF_ALLOCNO (total_costs
, a_num
)->mem_cost
;
1207 for (k
= 0; k
< cost_classes_num
; k
++)
1209 += COSTS_OF_ALLOCNO (allocno_costs
, a_num
)->cost
[k
];
1210 temp_costs
->mem_cost
1211 += COSTS_OF_ALLOCNO (allocno_costs
, a_num
)->mem_cost
;
1212 #ifdef FORBIDDEN_INC_DEC_CLASSES
1213 if (in_inc_dec
[a_num
])
1217 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1219 alt_class
= NO_REGS
;
1220 /* Find best common class for all allocnos with the same
1222 for (k
= 0; k
< cost_classes_num
; k
++)
1224 rclass
= cost_classes
[k
];
1225 /* Ignore classes that are too small for this operand or
1226 invalid for an operand that was auto-incremented. */
1227 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1228 #ifdef FORBIDDEN_INC_DEC_CLASSES
1229 || (inc_dec_p
&& forbidden_inc_dec_class
[rclass
])
1231 #ifdef CANNOT_CHANGE_MODE_CLASS
1232 || invalid_mode_change_p (i
, (enum reg_class
) rclass
,
1233 PSEUDO_REGNO_MODE (i
))
1237 if (temp_costs
->cost
[k
] < best_cost
)
1239 best_cost
= temp_costs
->cost
[k
];
1240 best
= (enum reg_class
) rclass
;
1242 else if (temp_costs
->cost
[k
] == best_cost
)
1243 best
= ira_reg_class_union
[best
][rclass
];
1244 if (pass
== flag_expensive_optimizations
1245 && temp_costs
->cost
[k
] < temp_costs
->mem_cost
1246 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1247 > reg_class_size
[alt_class
]))
1248 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1250 if (pass
== flag_expensive_optimizations
)
1252 if (best_cost
> temp_costs
->mem_cost
)
1253 best
= alt_class
= NO_REGS
;
1254 else if (best
== alt_class
)
1255 alt_class
= NO_REGS
;
1256 setup_reg_classes (i
, best
, alt_class
);
1257 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1258 fprintf (ira_dump_file
,
1259 " r%d: preferred %s, alternative %s\n",
1260 i
, reg_class_names
[best
], reg_class_names
[alt_class
]);
1262 if (best_cost
> temp_costs
->mem_cost
)
1263 common_class
= NO_REGS
;
1265 /* Make the common class a cover class. Remember all
1266 allocnos with the same regno should have the same cover
1268 common_class
= ira_class_translate
[best
];
1269 for (a
= ira_regno_allocno_map
[i
];
1271 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1273 a_num
= ALLOCNO_NUM (a
);
1274 if (common_class
== NO_REGS
)
1278 /* Finding best class which is subset of the common
1280 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1282 for (k
= 0; k
< cost_classes_num
; k
++)
1284 rclass
= cost_classes
[k
];
1285 if (! ira_class_subset_p
[rclass
][common_class
])
1287 /* Ignore classes that are too small for this
1288 operand or invalid for an operand that was
1289 auto-incremented. */
1290 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1291 #ifdef FORBIDDEN_INC_DEC_CLASSES
1292 || (inc_dec_p
&& forbidden_inc_dec_class
[rclass
])
1294 #ifdef CANNOT_CHANGE_MODE_CLASS
1295 || invalid_mode_change_p (i
, (enum reg_class
) rclass
,
1296 PSEUDO_REGNO_MODE (i
))
1300 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1304 = COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
];
1305 best
= (enum reg_class
) rclass
;
1307 else if (COSTS_OF_ALLOCNO (total_costs
, a_num
)->cost
[k
]
1309 best
= ira_reg_class_union
[best
][rclass
];
1312 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
1313 && (pass
== 0 || allocno_pref
[a_num
] != best
))
1315 fprintf (ira_dump_file
, " a%d (r%d,", a_num
, i
);
1316 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1317 fprintf (ira_dump_file
, "b%d", bb
->index
);
1319 fprintf (ira_dump_file
, "l%d",
1320 ALLOCNO_LOOP_TREE_NODE (a
)->loop
->num
);
1321 fprintf (ira_dump_file
, ") best %s, cover %s\n",
1322 reg_class_names
[best
],
1323 reg_class_names
[ira_class_translate
[best
]]);
1325 allocno_pref
[a_num
] = best
;
1329 if (internal_flag_ira_verbose
> 4 && ira_dump_file
)
1331 print_costs (ira_dump_file
);
1332 fprintf (ira_dump_file
,"\n");
1335 #ifdef FORBIDDEN_INC_DEC_CLASSES
1336 ira_free (in_inc_dec
);
1342 /* Process moves involving hard regs to modify allocno hard register
1343 costs. We can do this only after determining allocno cover class.
1344 If a hard register forms a register class, than moves with the hard
1345 register are already taken into account in class costs for the
1348 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1350 int i
, freq
, cost
, src_regno
, dst_regno
, hard_regno
;
1353 enum reg_class rclass
, hard_reg_class
;
1354 enum machine_mode mode
;
1356 rtx insn
, set
, src
, dst
;
1358 bb
= loop_tree_node
->bb
;
1361 freq
= REG_FREQ_FROM_BB (bb
);
1364 FOR_BB_INSNS (bb
, insn
)
1366 if (! INSN_P (insn
))
1368 set
= single_set (insn
);
1369 if (set
== NULL_RTX
)
1371 dst
= SET_DEST (set
);
1372 src
= SET_SRC (set
);
1373 if (! REG_P (dst
) || ! REG_P (src
))
1375 dst_regno
= REGNO (dst
);
1376 src_regno
= REGNO (src
);
1377 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1378 && src_regno
< FIRST_PSEUDO_REGISTER
)
1380 hard_regno
= src_regno
;
1382 a
= ira_curr_regno_allocno_map
[dst_regno
];
1384 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1385 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1387 hard_regno
= dst_regno
;
1389 a
= ira_curr_regno_allocno_map
[src_regno
];
1393 rclass
= ALLOCNO_COVER_CLASS (a
);
1394 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
1396 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
1399 mode
= ALLOCNO_MODE (a
);
1400 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1401 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
1402 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
1403 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
1404 ALLOCNO_COVER_CLASS_COST (a
));
1405 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1407 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1408 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1409 ALLOCNO_COVER_CLASS_COST (a
) = MIN (ALLOCNO_COVER_CLASS_COST (a
),
1410 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1414 /* After we find hard register and memory costs for allocnos, define
1415 its cover class and modify hard register cost because insns moving
1416 allocno to/from hard registers. */
1418 setup_allocno_cover_class_and_costs (void)
1420 int i
, j
, n
, regno
, num
;
1422 enum reg_class cover_class
, rclass
;
1423 enum machine_mode mode
;
1425 ira_allocno_iterator ai
;
1427 FOR_EACH_ALLOCNO (a
, ai
)
1429 i
= ALLOCNO_NUM (a
);
1430 mode
= ALLOCNO_MODE (a
);
1431 cover_class
= ira_class_translate
[allocno_pref
[i
]];
1432 ira_assert (allocno_pref
[i
] == NO_REGS
|| cover_class
!= NO_REGS
);
1433 ALLOCNO_MEMORY_COST (a
) = COSTS_OF_ALLOCNO (allocno_costs
, i
)->mem_cost
;
1434 ira_set_allocno_cover_class (a
, cover_class
);
1435 if (cover_class
== NO_REGS
)
1437 ALLOCNO_AVAILABLE_REGS_NUM (a
) = ira_available_class_regs
[cover_class
];
1438 num
= cost_class_nums
[allocno_pref
[i
]];
1439 ira_assert (num
>= 0);
1440 ALLOCNO_COVER_CLASS_COST (a
)
1441 = COSTS_OF_ALLOCNO (allocno_costs
, i
)->cost
[num
];
1442 if (optimize
&& ALLOCNO_COVER_CLASS (a
) != allocno_pref
[i
])
1444 n
= ira_class_hard_regs_num
[cover_class
];
1445 ALLOCNO_HARD_REG_COSTS (a
)
1446 = reg_costs
= ira_allocate_cost_vector (cover_class
);
1447 for (j
= n
- 1; j
>= 0; j
--)
1449 regno
= ira_class_hard_regs
[cover_class
][j
];
1450 rclass
= REGNO_REG_CLASS (regno
);
1451 num
= cost_class_nums
[rclass
];
1454 /* The hard register class is not a cover class or a
1455 class not fully inside in a cover class -- use
1456 the allocno cover class. */
1457 ira_assert (ira_hard_regno_cover_class
[regno
] == cover_class
);
1458 num
= cost_class_nums
[cover_class
];
1460 reg_costs
[j
] = COSTS_OF_ALLOCNO (allocno_costs
, i
)->cost
[num
];
1465 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1466 process_bb_node_for_hard_reg_moves
, NULL
);
1471 /* Function called once during compiler work. */
1473 ira_init_costs_once (void)
1478 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1481 this_op_costs
[i
] = NULL
;
1484 cost_classes
= NULL
;
1487 /* Free allocated temporary cost vectors. */
1489 free_ira_costs (void)
1493 if (init_cost
!= NULL
)
1496 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1498 if (op_costs
[i
] != NULL
)
1500 if (this_op_costs
[i
] != NULL
)
1501 free (this_op_costs
[i
]);
1502 op_costs
[i
] = this_op_costs
[i
] = NULL
;
1504 if (temp_costs
!= NULL
)
1507 if (cost_classes
!= NULL
)
1508 free (cost_classes
);
1509 cost_classes
= NULL
;
1512 /* This is called each time register related information is
1515 ira_init_costs (void)
1520 max_struct_costs_size
1521 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
1522 /* Don't use ira_allocate because vectors live through several IRA calls. */
1523 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
1524 init_cost
->mem_cost
= 1000000;
1525 for (i
= 0; i
< ira_important_classes_num
; i
++)
1526 init_cost
->cost
[i
] = 1000000;
1527 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
1529 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
1530 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
1532 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
1533 cost_classes
= (enum reg_class
*) xmalloc (sizeof (enum reg_class
)
1534 * ira_important_classes_num
);
1537 /* Function called once at the end of compiler work. */
1539 ira_finish_costs_once (void)
1546 /* Entry function which defines cover class, memory and hard register
1547 costs for each allocno. */
1552 ira_allocno_iterator ai
;
1554 allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
1555 * ira_allocnos_num
);
1556 total_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
1557 * ira_allocnos_num
);
1559 = (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
1560 * ira_allocnos_num
);
1561 find_allocno_class_costs ();
1562 setup_allocno_cover_class_and_costs ();
1563 /* Because we could process operands only as subregs, check mode of
1564 the registers themselves too. */
1565 FOR_EACH_ALLOCNO (a
, ai
)
1566 if (ira_register_move_cost
[ALLOCNO_MODE (a
)] == NULL
1567 && have_regs_of_mode
[ALLOCNO_MODE (a
)])
1568 ira_init_register_move_cost (ALLOCNO_MODE (a
));
1569 ira_free (allocno_pref_buffer
);
1570 ira_free (total_costs
);
1571 ira_free (allocno_costs
);
1576 /* Change hard register costs for allocnos which lives through
1577 function calls. This is called only when we found all intersected
1578 calls during building allocno live ranges. */
1580 ira_tune_allocno_costs_and_cover_classes (void)
1583 int cost
, min_cost
, *reg_costs
;
1584 enum reg_class cover_class
, rclass
;
1585 enum machine_mode mode
;
1587 ira_allocno_iterator ai
;
1589 FOR_EACH_ALLOCNO (a
, ai
)
1591 cover_class
= ALLOCNO_COVER_CLASS (a
);
1592 if (cover_class
== NO_REGS
)
1594 mode
= ALLOCNO_MODE (a
);
1595 n
= ira_class_hard_regs_num
[cover_class
];
1597 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0)
1599 ira_allocate_and_set_costs
1600 (&ALLOCNO_HARD_REG_COSTS (a
), cover_class
,
1601 ALLOCNO_COVER_CLASS_COST (a
));
1602 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
1603 for (j
= n
- 1; j
>= 0; j
--)
1605 regno
= ira_class_hard_regs
[cover_class
][j
];
1606 rclass
= REGNO_REG_CLASS (regno
);
1608 if (! ira_hard_reg_not_in_set_p (regno
, mode
, call_used_reg_set
)
1609 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1610 cost
+= (ALLOCNO_CALL_FREQ (a
)
1611 * (ira_memory_move_cost
[mode
][rclass
][0]
1612 + ira_memory_move_cost
[mode
][rclass
][1]));
1613 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
1614 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
1615 + ira_memory_move_cost
[mode
][rclass
][1])
1617 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
1619 reg_costs
[j
] += cost
;
1620 if (min_cost
> reg_costs
[j
])
1621 min_cost
= reg_costs
[j
];
1624 if (min_cost
!= INT_MAX
)
1625 ALLOCNO_COVER_CLASS_COST (a
) = min_cost
;