1 ;; Machine description of the Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005,
3 ; 2007 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; UNSPEC_VOLATILE usage
26 (UNSPECV_FLUSH_ICACHE 1)])
30 [(UNSPEC_LOAD_SDA_BASE 2)
32 (UNSPEC_PIC_LOAD_ADDR 4)
37 ;; Insn type. Used to default other attribute values.
39 "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
40 (const_string "misc"))
43 (define_attr "length" ""
44 (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
47 (eq_attr "type" "int4,load4,store4,shift4,div4")
50 (eq_attr "type" "multi")
53 (eq_attr "type" "uncond_branch,branch,call")
58 ;; The length here is the length of a single asm. Unfortunately it might be
59 ;; 2 or 4 so we must allow for 4. That's ok though.
60 (define_asm_attributes
61 [(set_attr "length" "4")
62 (set_attr "type" "multi")])
64 ;; Whether an instruction is short (16-bit) or long (32-bit).
65 (define_attr "insn_size" "short,long"
66 (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
67 (const_string "short")
68 (const_string "long")))
70 ;; The target CPU we're compiling for.
71 (define_attr "cpu" "m32r,m32r2,m32rx"
72 (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))
73 (const_string "m32rx")
74 (ne (symbol_ref "TARGET_M32R2") (const_int 0))
75 (const_string "m32r2")]
76 (const_string "m32r")))
78 ;; Defines the pipeline where an instruction can be executed on.
79 ;; For the M32R, a short instruction can execute one of the two pipes.
80 ;; For the M32Rx, the restrictions are modelled in the second
81 ;; condition of this attribute definition.
82 (define_attr "m32r_pipeline" "either,s,o,long"
83 (cond [(and (eq_attr "cpu" "m32r")
84 (eq_attr "insn_size" "short"))
85 (const_string "either")
86 (eq_attr "insn_size" "!short")
87 (const_string "long")]
88 (cond [(eq_attr "type" "int2")
89 (const_string "either")
90 (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
92 (eq_attr "type" "mul2")
94 (const_string "long"))))
96 ;; ::::::::::::::::::::
98 ;; :: Pipeline description
100 ;; ::::::::::::::::::::
102 ;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the
103 ;; "M32R-FPU Software Manual", Revision 1.01, plus additional information
104 ;; obtained by our best friend and mine, Google.
106 ;; The pipeline is modelled as a fetch unit, and a core with a memory unit,
107 ;; two execution units, where "fetch" models IF and D, "memory" for MEM1
108 ;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA. Writeback and
109 ;; bypasses are not modelled.
110 (define_automaton "m32r")
112 ;; We pretend there are two short (16 bits) instruction fetchers. The
113 ;; "s" short fetcher cannot be reserved until the "o" short fetcher is
114 ;; reserved. Some instructions reserve both the left and right fetchers.
115 ;; These fetch units are a hack to get GCC to better pack the instructions
116 ;; for the M32Rx processor, which has two execution pipes.
118 ;; In reality there is only one decoder, which can decode either two 16-bit
119 ;; instructions, or a single 32-bit instruction.
121 ;; Note, "fetch" models both the IF and the D pipeline stages.
123 ;; The m32rx core has two execution pipes. We name them o_E and s_E.
124 ;; In addition, there's a memory unit.
126 (define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")
128 ;; Prevent the s pipe from being reserved before the o pipe.
129 (absence_set "s_IF" "o_IF")
130 (absence_set "s_E" "o_E")
132 ;; On the M32Rx, long instructions execute on both pipes, so reserve
133 ;; both fetch slots and both pipes.
134 (define_reservation "long_IF" "o_IF+s_IF")
135 (define_reservation "long_E" "o_E+s_E")
137 ;; ::::::::::::::::::::
139 ;; Simple instructions do 4 stages: IF D E WB. WB is not modelled.
140 ;; Hence, ready latency is 1.
141 (define_insn_reservation "short_left" 1
142 (and (eq_attr "m32r_pipeline" "o")
143 (and (eq_attr "insn_size" "short")
144 (eq_attr "type" "!load2")))
147 (define_insn_reservation "short_right" 1
148 (and (eq_attr "m32r_pipeline" "s")
149 (and (eq_attr "insn_size" "short")
150 (eq_attr "type" "!load2")))
153 (define_insn_reservation "short_either" 1
154 (and (eq_attr "m32r_pipeline" "either")
155 (and (eq_attr "insn_size" "short")
156 (eq_attr "type" "!load2")))
159 (define_insn_reservation "long_m32r" 1
160 (and (eq_attr "cpu" "m32r")
161 (and (eq_attr "insn_size" "long")
162 (eq_attr "type" "!load4,load8")))
165 (define_insn_reservation "long_m32rx" 2
166 (and (eq_attr "m32r_pipeline" "long")
167 (and (eq_attr "insn_size" "long")
168 (eq_attr "type" "!load4,load8")))
171 ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
172 ;; MEM1 may require more than one cycle depending on locality. We
173 ;; optimistically assume all memory is nearby, i.e. MEM1 takes only
174 ;; one cycle. Hence, ready latency is 3.
176 ;; The M32Rx can do short load/store only on the left pipe.
177 (define_insn_reservation "short_load_left" 3
178 (and (eq_attr "m32r_pipeline" "o")
179 (and (eq_attr "insn_size" "short")
180 (eq_attr "type" "load2")))
183 (define_insn_reservation "short_load" 3
184 (and (eq_attr "m32r_pipeline" "either")
185 (and (eq_attr "insn_size" "short")
186 (eq_attr "type" "load2")))
187 "s_IF|o_IF,s_E|o_E,memory*2")
189 (define_insn_reservation "long_load" 3
190 (and (eq_attr "cpu" "m32r")
191 (and (eq_attr "insn_size" "long")
192 (eq_attr "type" "load4,load8")))
193 "long_IF,long_E,memory*2")
195 (define_insn_reservation "long_load_m32rx" 3
196 (and (eq_attr "m32r_pipeline" "long")
197 (eq_attr "type" "load4,load8"))
198 "long_IF,long_E,memory*2")
201 (include "predicates.md")
202 (include "constraints.md")
204 ;; Expand prologue as RTL
205 (define_expand "prologue"
210 m32r_expand_prologue ();
214 ;; Expand epilogue as RTL
215 (define_expand "epilogue"
220 m32r_expand_epilogue ();
221 emit_jump_insn (gen_return_normal ());
225 ;; Move instructions.
227 ;; For QI and HI moves, the register must contain the full properly
228 ;; sign-extended value. nonzero_bits assumes this [otherwise
229 ;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
230 ;; says it's a kludge and the .md files should be fixed instead].
232 (define_expand "movqi"
233 [(set (match_operand:QI 0 "general_operand" "")
234 (match_operand:QI 1 "general_operand" ""))]
238 /* Fixup PIC cases. */
241 if (symbolic_operand (operands[1], QImode))
243 if (reload_in_progress || reload_completed)
244 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
246 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
250 /* Everything except mem = const or mem = mem can be done easily.
251 Objects in the small data area are handled too. */
253 if (GET_CODE (operands[0]) == MEM)
254 operands[1] = force_reg (QImode, operands[1]);
257 (define_insn "*movqi_insn"
258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
259 (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
260 "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
269 [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
270 (set_attr "length" "2,2,4,2,4,2,4")])
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "general_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
278 /* Fixup PIC cases. */
281 if (symbolic_operand (operands[1], HImode))
283 if (reload_in_progress || reload_completed)
284 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
286 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
290 /* Everything except mem = const or mem = mem can be done easily. */
292 if (GET_CODE (operands[0]) == MEM)
293 operands[1] = force_reg (HImode, operands[1]);
296 (define_insn "*movhi_insn"
297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
298 (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
299 "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
309 [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
310 (set_attr "length" "2,2,4,4,2,4,2,4")])
312 (define_expand "movsi_push"
313 [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
314 (match_operand:SI 1 "register_operand" ""))]
318 (define_expand "movsi_pop"
319 [(set (match_operand:SI 0 "register_operand" "")
320 (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
324 (define_expand "movsi"
325 [(set (match_operand:SI 0 "general_operand" "")
326 (match_operand:SI 1 "general_operand" ""))]
330 /* Fixup PIC cases. */
333 if (symbolic_operand (operands[1], SImode))
335 if (reload_in_progress || reload_completed)
336 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
338 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
342 /* Everything except mem = const or mem = mem can be done easily. */
344 if (GET_CODE (operands[0]) == MEM)
345 operands[1] = force_reg (SImode, operands[1]);
347 /* Small Data Area reference? */
348 if (small_data_operand (operands[1], SImode))
350 emit_insn (gen_movsi_sda (operands[0], operands[1]));
354 /* If medium or large code model, symbols have to be loaded with
356 if (addr32_operand (operands[1], SImode))
358 emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
363 ;; ??? Do we need a const_double constraint here for large unsigned values?
364 (define_insn "*movsi_insn"
365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
370 if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
372 switch (GET_CODE (operands[1]))
384 if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
385 && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
391 if (satisfies_constraint_J (operands[1]))
392 return \"ldi %0,%#%1\\t; %X1\";
394 if (satisfies_constraint_M (operands[1]))
395 return \"ld24 %0,%#%1\\t; %X1\";
397 if (satisfies_constraint_L (operands[1]))
398 return \"seth %0,%#%T1\\t; %X1\";
406 return \"ld24 %0,%#%1\";
412 else if (GET_CODE (operands[0]) == MEM
413 && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
415 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
416 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
424 [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
425 (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
427 ; Try to use a four byte / two byte pair for constants not loadable with
431 [(set (match_operand:SI 0 "register_operand" "")
432 (match_operand:SI 1 "two_insn_const_operand" ""))]
434 [(set (match_dup 0) (match_dup 2))
435 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
438 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
439 unsigned HOST_WIDE_INT tmp;
442 /* In all cases we will emit two instructions. However we try to
443 use 2 byte instructions wherever possible. We can assume the
444 constant isn't loadable with any of ldi, ld24, or seth. */
446 /* See if we can load a 24-bit unsigned value and invert it. */
447 if (UINT24_P (~ val))
449 emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
450 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
454 /* See if we can load a 24-bit unsigned value and shift it into place.
455 0x01fffffe is just beyond ld24's range. */
456 for (shift = 1, tmp = 0x01fffffe;
460 if ((val & ~tmp) == 0)
462 emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
463 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
468 /* Can't use any two byte insn, fall back to seth/or3. Use ~0xffff instead
469 of 0xffff0000, since the later fails on a 64-bit host. */
470 operands[2] = GEN_INT ((val) & ~0xffff);
471 operands[3] = GEN_INT ((val) & 0xffff);
475 [(set (match_operand:SI 0 "register_operand" "")
476 (match_operand:SI 1 "seth_add3_operand" ""))]
479 (high:SI (match_dup 1)))
481 (lo_sum:SI (match_dup 0)
485 ;; Small data area support.
486 ;; The address of _SDA_BASE_ is loaded into a register and all objects in
487 ;; the small data area are indexed off that. This is done for each reference
488 ;; but cse will clean things up for us. We let the compiler choose the
489 ;; register to use so we needn't allocate (and maybe even fix) a special
490 ;; register to use. Since the load and store insns have a 16-bit offset the
491 ;; total size of the data area can be 64K. However, if the data area lives
492 ;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
493 ;; would then yield 3 instructions to reference an object [though there would
494 ;; be no net loss if two or more objects were referenced]. The 3 insns can be
495 ;; reduced back to 2 if the size of the small data area were reduced to 32K
496 ;; [then seth + ld/st would work for any object in the area]. Doing this
497 ;; would require special handling of _SDA_BASE_ (its value would be
498 ;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
499 ;; [I think]. What to do about this is deferred until later and for now we
500 ;; require .sdata to be in the first 16M.
502 (define_expand "movsi_sda"
504 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
505 (set (match_operand:SI 0 "register_operand" "")
506 (lo_sum:SI (match_dup 2)
507 (match_operand:SI 1 "small_data_operand" "")))]
511 if (reload_in_progress || reload_completed)
512 operands[2] = operands[0];
514 operands[2] = gen_reg_rtx (SImode);
517 (define_insn "*load_sda_base_32"
518 [(set (match_operand:SI 0 "register_operand" "=r")
519 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
521 "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
522 [(set_attr "type" "multi")
523 (set_attr "length" "8")])
525 (define_insn "*load_sda_base"
526 [(set (match_operand:SI 0 "register_operand" "=r")
527 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
529 "ld24 %0,#_SDA_BASE_"
530 [(set_attr "type" "int4")
531 (set_attr "length" "4")])
533 ;; 32-bit address support.
535 (define_expand "movsi_addr32"
537 ; addr32_operand isn't used because it's too restrictive,
538 ; seth_add3_operand is more general and thus safer.
539 (high:SI (match_operand:SI 1 "seth_add3_operand" "")))
540 (set (match_operand:SI 0 "register_operand" "")
541 (lo_sum:SI (match_dup 2) (match_dup 1)))]
545 if (reload_in_progress || reload_completed)
546 operands[2] = operands[0];
548 operands[2] = gen_reg_rtx (SImode);
551 (define_insn "set_hi_si"
552 [(set (match_operand:SI 0 "register_operand" "=r")
553 (high:SI (match_operand 1 "symbolic_operand" "")))]
555 "seth %0,%#shigh(%1)"
556 [(set_attr "type" "int4")
557 (set_attr "length" "4")])
559 (define_insn "lo_sum_si"
560 [(set (match_operand:SI 0 "register_operand" "=r")
561 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
562 (match_operand:SI 2 "immediate_operand" "in")))]
565 [(set_attr "type" "int4")
566 (set_attr "length" "4")])
568 (define_expand "movdi"
569 [(set (match_operand:DI 0 "general_operand" "")
570 (match_operand:DI 1 "general_operand" ""))]
574 /* Fixup PIC cases. */
577 if (symbolic_operand (operands[1], DImode))
579 if (reload_in_progress || reload_completed)
580 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
582 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
586 /* Everything except mem = const or mem = mem can be done easily. */
588 if (GET_CODE (operands[0]) == MEM)
589 operands[1] = force_reg (DImode, operands[1]);
592 (define_insn "*movdi_insn"
593 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
594 (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
595 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
597 [(set_attr "type" "multi,multi,multi,load8,store8")
598 (set_attr "length" "4,4,16,6,6")])
601 [(set (match_operand:DI 0 "move_dest_operand" "")
602 (match_operand:DI 1 "move_double_src_operand" ""))]
605 "operands[2] = gen_split_move_double (operands);")
607 ;; Floating point move insns.
609 (define_expand "movsf"
610 [(set (match_operand:SF 0 "general_operand" "")
611 (match_operand:SF 1 "general_operand" ""))]
615 /* Fixup PIC cases. */
618 if (symbolic_operand (operands[1], SFmode))
620 if (reload_in_progress || reload_completed)
621 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
623 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
627 /* Everything except mem = const or mem = mem can be done easily. */
629 if (GET_CODE (operands[0]) == MEM)
630 operands[1] = force_reg (SFmode, operands[1]);
633 (define_insn "*movsf_insn"
634 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
635 (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
636 "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
646 ;; ??? Length of alternative 1 is either 2, 4 or 8.
647 [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
648 (set_attr "length" "2,8,2,2,4,2,2,4")])
651 [(set (match_operand:SF 0 "register_operand" "")
652 (match_operand:SF 1 "const_double_operand" ""))]
654 [(set (match_dup 2) (match_dup 3))]
657 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
658 operands[3] = operand_subword (operands[1], 0, 0, SFmode);
661 (define_expand "movdf"
662 [(set (match_operand:DF 0 "general_operand" "")
663 (match_operand:DF 1 "general_operand" ""))]
667 /* Fixup PIC cases. */
670 if (symbolic_operand (operands[1], DFmode))
672 if (reload_in_progress || reload_completed)
673 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
675 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
679 /* Everything except mem = const or mem = mem can be done easily. */
681 if (GET_CODE (operands[0]) == MEM)
682 operands[1] = force_reg (DFmode, operands[1]);
685 (define_insn "*movdf_insn"
686 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
687 (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
688 "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
690 [(set_attr "type" "multi,multi,load8,store8")
691 (set_attr "length" "4,16,6,6")])
694 [(set (match_operand:DF 0 "move_dest_operand" "")
695 (match_operand:DF 1 "move_double_src_operand" ""))]
698 "operands[2] = gen_split_move_double (operands);")
700 ;; Zero extension instructions.
702 (define_insn "zero_extendqihi2"
703 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
704 (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
710 [(set_attr "type" "int4,load2,load4")
711 (set_attr "length" "4,2,4")])
713 (define_insn "zero_extendqisi2"
714 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
715 (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
721 [(set_attr "type" "int4,load2,load4")
722 (set_attr "length" "4,2,4")])
724 (define_insn "zero_extendhisi2"
725 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
726 (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
732 [(set_attr "type" "int4,load2,load4")
733 (set_attr "length" "4,2,4")])
735 ;; Signed conversions from a smaller integer to a larger integer
736 (define_insn "extendqihi2"
737 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
738 (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
744 [(set_attr "type" "multi,load2,load4")
745 (set_attr "length" "2,2,4")])
748 [(set (match_operand:HI 0 "register_operand" "")
749 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
755 rtx op0 = gen_lowpart (SImode, operands[0]);
756 rtx shift = GEN_INT (24);
758 operands[2] = gen_ashlsi3 (op0, op0, shift);
759 operands[3] = gen_ashrsi3 (op0, op0, shift);
762 (define_insn "extendqisi2"
763 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
764 (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
770 [(set_attr "type" "multi,load2,load4")
771 (set_attr "length" "4,2,4")])
774 [(set (match_operand:SI 0 "register_operand" "")
775 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
781 rtx shift = GEN_INT (24);
783 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
784 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
787 (define_insn "extendhisi2"
788 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
789 (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
795 [(set_attr "type" "multi,load2,load4")
796 (set_attr "length" "4,2,4")])
799 [(set (match_operand:SI 0 "register_operand" "")
800 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
806 rtx shift = GEN_INT (16);
808 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
809 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
812 ;; Arithmetic instructions.
814 ; ??? Adding an alternative to split add3 of small constants into two
815 ; insns yields better instruction packing but slower code. Adds of small
816 ; values is done a lot.
818 (define_insn "addsi3"
819 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
820 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
821 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
827 [(set_attr "type" "int2,int2,int4")
828 (set_attr "length" "2,2,4")])
831 ; [(set (match_operand:SI 0 "register_operand" "")
832 ; (plus:SI (match_operand:SI 1 "register_operand" "")
833 ; (match_operand:SI 2 "int8_operand" "")))]
835 ; && REGNO (operands[0]) != REGNO (operands[1])
836 ; && satisfies_constraint_I (operands[2])
837 ; && INTVAL (operands[2]) != 0"
838 ; [(set (match_dup 0) (match_dup 1))
839 ; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
842 (define_insn "adddi3"
843 [(set (match_operand:DI 0 "register_operand" "=r")
844 (plus:DI (match_operand:DI 1 "register_operand" "%0")
845 (match_operand:DI 2 "register_operand" "r")))
846 (clobber (reg:CC 17))]
849 [(set_attr "type" "multi")
850 (set_attr "length" "6")])
852 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
854 [(set (match_operand:DI 0 "register_operand" "")
855 (plus:DI (match_operand:DI 1 "register_operand" "")
856 (match_operand:DI 2 "register_operand" "")))
857 (clobber (reg:CC 17))]
859 [(parallel [(set (reg:CC 17)
861 (use (match_dup 4))])
862 (parallel [(set (match_dup 4)
863 (plus:SI (match_dup 4)
864 (plus:SI (match_dup 5)
865 (ne:SI (reg:CC 17) (const_int 0)))))
867 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
868 (parallel [(set (match_dup 6)
869 (plus:SI (match_dup 6)
870 (plus:SI (match_dup 7)
871 (ne:SI (reg:CC 17) (const_int 0)))))
873 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
876 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
877 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
878 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
879 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
882 (define_insn "*clear_c"
885 (use (match_operand:SI 0 "register_operand" "r"))]
888 [(set_attr "type" "int2")
889 (set_attr "length" "2")])
891 (define_insn "*add_carry"
892 [(set (match_operand:SI 0 "register_operand" "=r")
893 (plus:SI (match_operand:SI 1 "register_operand" "%0")
894 (plus:SI (match_operand:SI 2 "register_operand" "r")
895 (ne:SI (reg:CC 17) (const_int 0)))))
897 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
900 [(set_attr "type" "int2")
901 (set_attr "length" "2")])
903 (define_insn "subsi3"
904 [(set (match_operand:SI 0 "register_operand" "=r")
905 (minus:SI (match_operand:SI 1 "register_operand" "0")
906 (match_operand:SI 2 "register_operand" "r")))]
909 [(set_attr "type" "int2")
910 (set_attr "length" "2")])
912 (define_insn "subdi3"
913 [(set (match_operand:DI 0 "register_operand" "=r")
914 (minus:DI (match_operand:DI 1 "register_operand" "0")
915 (match_operand:DI 2 "register_operand" "r")))
916 (clobber (reg:CC 17))]
919 [(set_attr "type" "multi")
920 (set_attr "length" "6")])
922 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
924 [(set (match_operand:DI 0 "register_operand" "")
925 (minus:DI (match_operand:DI 1 "register_operand" "")
926 (match_operand:DI 2 "register_operand" "")))
927 (clobber (reg:CC 17))]
929 [(parallel [(set (reg:CC 17)
931 (use (match_dup 4))])
932 (parallel [(set (match_dup 4)
933 (minus:SI (match_dup 4)
934 (minus:SI (match_dup 5)
935 (ne:SI (reg:CC 17) (const_int 0)))))
937 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
938 (parallel [(set (match_dup 6)
939 (minus:SI (match_dup 6)
940 (minus:SI (match_dup 7)
941 (ne:SI (reg:CC 17) (const_int 0)))))
943 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
946 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
947 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
948 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
949 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
952 (define_insn "*sub_carry"
953 [(set (match_operand:SI 0 "register_operand" "=r")
954 (minus:SI (match_operand:SI 1 "register_operand" "%0")
955 (minus:SI (match_operand:SI 2 "register_operand" "r")
956 (ne:SI (reg:CC 17) (const_int 0)))))
958 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
961 [(set_attr "type" "int2")
962 (set_attr "length" "2")])
964 ; Multiply/Divide instructions.
966 (define_insn "mulhisi3"
967 [(set (match_operand:SI 0 "register_operand" "=r")
968 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
969 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
971 "mullo %1,%2\;mvfacmi %0"
972 [(set_attr "type" "multi")
973 (set_attr "length" "4")])
975 (define_insn "mulsi3"
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (mult:SI (match_operand:SI 1 "register_operand" "%0")
978 (match_operand:SI 2 "register_operand" "r")))]
981 [(set_attr "type" "mul2")
982 (set_attr "length" "2")])
984 (define_insn "divsi3"
985 [(set (match_operand:SI 0 "register_operand" "=r")
986 (div:SI (match_operand:SI 1 "register_operand" "0")
987 (match_operand:SI 2 "register_operand" "r")))]
990 [(set_attr "type" "div4")
991 (set_attr "length" "4")])
993 (define_insn "udivsi3"
994 [(set (match_operand:SI 0 "register_operand" "=r")
995 (udiv:SI (match_operand:SI 1 "register_operand" "0")
996 (match_operand:SI 2 "register_operand" "r")))]
999 [(set_attr "type" "div4")
1000 (set_attr "length" "4")])
1002 (define_insn "modsi3"
1003 [(set (match_operand:SI 0 "register_operand" "=r")
1004 (mod:SI (match_operand:SI 1 "register_operand" "0")
1005 (match_operand:SI 2 "register_operand" "r")))]
1008 [(set_attr "type" "div4")
1009 (set_attr "length" "4")])
1011 (define_insn "umodsi3"
1012 [(set (match_operand:SI 0 "register_operand" "=r")
1013 (umod:SI (match_operand:SI 1 "register_operand" "0")
1014 (match_operand:SI 2 "register_operand" "r")))]
1017 [(set_attr "type" "div4")
1018 (set_attr "length" "4")])
1020 ;; Boolean instructions.
1022 ;; We don't define the DImode versions as expand_binop does a good enough job.
1023 ;; And if it doesn't it should be fixed.
1025 (define_insn "andsi3"
1026 [(set (match_operand:SI 0 "register_operand" "=r,r")
1027 (and:SI (match_operand:SI 1 "register_operand" "%0,r")
1028 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1032 /* If we are worried about space, see if we can break this up into two
1033 short instructions, which might eliminate a NOP being inserted. */
1035 && m32r_not_same_reg (operands[0], operands[1])
1036 && satisfies_constraint_I (operands[2]))
1039 else if (GET_CODE (operands[2]) == CONST_INT)
1040 return \"and3 %0,%1,%#%X2\";
1042 return \"and %0,%2\";
1044 [(set_attr "type" "int2,int4")
1045 (set_attr "length" "2,4")])
1048 [(set (match_operand:SI 0 "register_operand" "")
1049 (and:SI (match_operand:SI 1 "register_operand" "")
1050 (match_operand:SI 2 "int8_operand" "")))]
1051 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1052 [(set (match_dup 0) (match_dup 2))
1053 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
1056 (define_insn "iorsi3"
1057 [(set (match_operand:SI 0 "register_operand" "=r,r")
1058 (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
1059 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1063 /* If we are worried about space, see if we can break this up into two
1064 short instructions, which might eliminate a NOP being inserted. */
1066 && m32r_not_same_reg (operands[0], operands[1])
1067 && satisfies_constraint_I (operands[2]))
1070 else if (GET_CODE (operands[2]) == CONST_INT)
1071 return \"or3 %0,%1,%#%X2\";
1073 return \"or %0,%2\";
1075 [(set_attr "type" "int2,int4")
1076 (set_attr "length" "2,4")])
1079 [(set (match_operand:SI 0 "register_operand" "")
1080 (ior:SI (match_operand:SI 1 "register_operand" "")
1081 (match_operand:SI 2 "int8_operand" "")))]
1082 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1083 [(set (match_dup 0) (match_dup 2))
1084 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
1087 (define_insn "xorsi3"
1088 [(set (match_operand:SI 0 "register_operand" "=r,r")
1089 (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
1090 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1094 /* If we are worried about space, see if we can break this up into two
1095 short instructions, which might eliminate a NOP being inserted. */
1097 && m32r_not_same_reg (operands[0], operands[1])
1098 && satisfies_constraint_I (operands[2]))
1101 else if (GET_CODE (operands[2]) == CONST_INT)
1102 return \"xor3 %0,%1,%#%X2\";
1104 return \"xor %0,%2\";
1106 [(set_attr "type" "int2,int4")
1107 (set_attr "length" "2,4")])
1110 [(set (match_operand:SI 0 "register_operand" "")
1111 (xor:SI (match_operand:SI 1 "register_operand" "")
1112 (match_operand:SI 2 "int8_operand" "")))]
1113 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1114 [(set (match_dup 0) (match_dup 2))
1115 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
1118 (define_insn "negsi2"
1119 [(set (match_operand:SI 0 "register_operand" "=r")
1120 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1123 [(set_attr "type" "int2")
1124 (set_attr "length" "2")])
1126 (define_insn "one_cmplsi2"
1127 [(set (match_operand:SI 0 "register_operand" "=r")
1128 (not:SI (match_operand:SI 1 "register_operand" "r")))]
1131 [(set_attr "type" "int2")
1132 (set_attr "length" "2")])
1134 ;; Shift instructions.
1136 (define_insn "ashlsi3"
1137 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1138 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1139 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1145 [(set_attr "type" "shift2,shift2,shift4")
1146 (set_attr "length" "2,2,4")])
1148 (define_insn "ashrsi3"
1149 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1150 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1151 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1157 [(set_attr "type" "shift2,shift2,shift4")
1158 (set_attr "length" "2,2,4")])
1160 (define_insn "lshrsi3"
1161 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1162 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1163 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1169 [(set_attr "type" "shift2,shift2,shift4")
1170 (set_attr "length" "2,2,4")])
1172 ;; Compare instructions.
1173 ;; This controls RTL generation and register allocation.
1175 ;; We generate RTL for comparisons and branches by having the cmpxx
1176 ;; patterns store away the operands. Then the bcc patterns
1177 ;; emit RTL for both the compare and the branch.
1179 ;; On the m32r it is more efficient to use the bxxz instructions and
1180 ;; thus merge the compare and branch into one instruction, so they are
1183 (define_expand "cmpsi"
1185 (compare:CC (match_operand:SI 0 "register_operand" "")
1186 (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
1190 m32r_compare_op0 = operands[0];
1191 m32r_compare_op1 = operands[1];
1195 (define_insn "cmp_eqsi_zero_insn"
1197 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1198 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
1199 "TARGET_M32RX || TARGET_M32R2"
1203 [(set_attr "type" "int4")
1204 (set_attr "length" "4")])
1206 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
1207 ;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
1208 ;; is quite inefficient. However, it is rarely used.
1210 (define_insn "cmp_eqsi_insn"
1212 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1213 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
1214 (clobber (match_scratch:SI 2 "=&r,&r"))]
1218 if (which_alternative == 0)
1220 return \"mv %2,%0\;sub %2,%1\;cmpui %2,#1\";
1224 if (INTVAL (operands [1]) == 0)
1225 return \"cmpui %0, #1\";
1226 else if (REGNO (operands [2]) == REGNO (operands [0]))
1227 return \"addi %0,%#%N1\;cmpui %2,#1\";
1229 return \"add3 %2,%0,%#%N1\;cmpui %2,#1\";
1232 [(set_attr "type" "multi,multi")
1233 (set_attr "length" "8,8")])
1235 (define_insn "cmp_ltsi_insn"
1237 (lt:CC (match_operand:SI 0 "register_operand" "r,r")
1238 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1243 [(set_attr "type" "int2,int4")
1244 (set_attr "length" "2,4")])
1246 (define_insn "cmp_ltusi_insn"
1248 (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
1249 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1254 [(set_attr "type" "int2,int4")
1255 (set_attr "length" "2,4")])
1257 ;; These control RTL generation for conditional jump insns.
1259 (define_expand "beq"
1261 (if_then_else (match_dup 1)
1262 (label_ref (match_operand 0 "" ""))
1267 operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
1270 (define_expand "bne"
1272 (if_then_else (match_dup 1)
1273 (label_ref (match_operand 0 "" ""))
1278 operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
1281 (define_expand "bgt"
1283 (if_then_else (match_dup 1)
1284 (label_ref (match_operand 0 "" ""))
1289 operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
1292 (define_expand "ble"
1294 (if_then_else (match_dup 1)
1295 (label_ref (match_operand 0 "" ""))
1300 operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
1303 (define_expand "bge"
1305 (if_then_else (match_dup 1)
1306 (label_ref (match_operand 0 "" ""))
1311 operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
1314 (define_expand "blt"
1316 (if_then_else (match_dup 1)
1317 (label_ref (match_operand 0 "" ""))
1322 operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
1325 (define_expand "bgtu"
1327 (if_then_else (match_dup 1)
1328 (label_ref (match_operand 0 "" ""))
1333 operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1336 (define_expand "bleu"
1338 (if_then_else (match_dup 1)
1339 (label_ref (match_operand 0 "" ""))
1344 operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1347 (define_expand "bgeu"
1349 (if_then_else (match_dup 1)
1350 (label_ref (match_operand 0 "" ""))
1355 operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1358 (define_expand "bltu"
1360 (if_then_else (match_dup 1)
1361 (label_ref (match_operand 0 "" ""))
1366 operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1369 ;; Now match both normal and inverted jump.
1371 (define_insn "*branch_insn"
1373 (if_then_else (match_operator 1 "eqne_comparison_operator"
1374 [(reg 17) (const_int 0)])
1375 (label_ref (match_operand 0 "" ""))
1380 static char instruction[40];
1381 sprintf (instruction, \"%s%s %%l0\",
1382 (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
1383 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1386 [(set_attr "type" "branch")
1388 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1389 ; lengths and insn alignments that are complex to track.
1390 ; It's not important that we be hyper-precise here. It may be more
1391 ; important blah blah blah when the chip supports parallel execution
1392 ; blah blah blah but until then blah blah blah this is simple and
1394 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1400 (define_insn "*rev_branch_insn"
1402 (if_then_else (match_operator 1 "eqne_comparison_operator"
1403 [(reg 17) (const_int 0)])
1405 (label_ref (match_operand 0 "" ""))))]
1406 ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
1410 static char instruction[40];
1411 sprintf (instruction, \"%s%s %%l0\",
1412 (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
1413 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1416 [(set_attr "type" "branch")
1418 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1419 ; lengths and insn alignments that are complex to track.
1420 ; It's not important that we be hyper-precise here. It may be more
1421 ; important blah blah blah when the chip supports parallel execution
1422 ; blah blah blah but until then blah blah blah this is simple and
1424 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1430 ; reg/reg compare and branch insns
1432 (define_insn "*reg_branch_insn"
1434 (if_then_else (match_operator 1 "eqne_comparison_operator"
1435 [(match_operand:SI 2 "register_operand" "r")
1436 (match_operand:SI 3 "register_operand" "r")])
1437 (label_ref (match_operand 0 "" ""))
1442 /* Is branch target reachable with beq/bne? */
1443 if (get_attr_length (insn) == 4)
1445 if (GET_CODE (operands[1]) == EQ)
1446 return \"beq %2,%3,%l0\";
1448 return \"bne %2,%3,%l0\";
1452 if (GET_CODE (operands[1]) == EQ)
1453 return \"bne %2,%3,1f\;bra %l0\;1:\";
1455 return \"beq %2,%3,1f\;bra %l0\;1:\";
1458 [(set_attr "type" "branch")
1459 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1460 ; which is complex to track and inaccurate length specs.
1461 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1467 (define_insn "*rev_reg_branch_insn"
1469 (if_then_else (match_operator 1 "eqne_comparison_operator"
1470 [(match_operand:SI 2 "register_operand" "r")
1471 (match_operand:SI 3 "register_operand" "r")])
1473 (label_ref (match_operand 0 "" ""))))]
1477 /* Is branch target reachable with beq/bne? */
1478 if (get_attr_length (insn) == 4)
1480 if (GET_CODE (operands[1]) == NE)
1481 return \"beq %2,%3,%l0\";
1483 return \"bne %2,%3,%l0\";
1487 if (GET_CODE (operands[1]) == NE)
1488 return \"bne %2,%3,1f\;bra %l0\;1:\";
1490 return \"beq %2,%3,1f\;bra %l0\;1:\";
1493 [(set_attr "type" "branch")
1494 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1495 ; which is complex to track and inaccurate length specs.
1496 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1502 ; reg/zero compare and branch insns
1504 (define_insn "*zero_branch_insn"
1506 (if_then_else (match_operator 1 "signed_comparison_operator"
1507 [(match_operand:SI 2 "register_operand" "r")
1509 (label_ref (match_operand 0 "" ""))
1514 const char *br,*invbr;
1517 switch (GET_CODE (operands[1]))
1519 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1520 case NE : br = \"ne\"; invbr = \"eq\"; break;
1521 case LE : br = \"le\"; invbr = \"gt\"; break;
1522 case GT : br = \"gt\"; invbr = \"le\"; break;
1523 case LT : br = \"lt\"; invbr = \"ge\"; break;
1524 case GE : br = \"ge\"; invbr = \"lt\"; break;
1526 default: gcc_unreachable ();
1529 /* Is branch target reachable with bxxz? */
1530 if (get_attr_length (insn) == 4)
1532 sprintf (asmtext, \"b%sz %%2,%%l0\", br);
1533 output_asm_insn (asmtext, operands);
1537 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
1538 output_asm_insn (asmtext, operands);
1542 [(set_attr "type" "branch")
1543 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1544 ; which is complex to track and inaccurate length specs.
1545 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1551 (define_insn "*rev_zero_branch_insn"
1553 (if_then_else (match_operator 1 "eqne_comparison_operator"
1554 [(match_operand:SI 2 "register_operand" "r")
1557 (label_ref (match_operand 0 "" ""))))]
1561 const char *br,*invbr;
1564 switch (GET_CODE (operands[1]))
1566 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1567 case NE : br = \"ne\"; invbr = \"eq\"; break;
1568 case LE : br = \"le\"; invbr = \"gt\"; break;
1569 case GT : br = \"gt\"; invbr = \"le\"; break;
1570 case LT : br = \"lt\"; invbr = \"ge\"; break;
1571 case GE : br = \"ge\"; invbr = \"lt\"; break;
1573 default: gcc_unreachable ();
1576 /* Is branch target reachable with bxxz? */
1577 if (get_attr_length (insn) == 4)
1579 sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
1580 output_asm_insn (asmtext, operands);
1584 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
1585 output_asm_insn (asmtext, operands);
1589 [(set_attr "type" "branch")
1590 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1591 ; which is complex to track and inaccurate length specs.
1592 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1598 ;; S<cc> operations to set a register to 1/0 based on a comparison
1600 (define_expand "seq"
1601 [(match_operand:SI 0 "register_operand" "")]
1605 rtx op0 = operands[0];
1606 rtx op1 = m32r_compare_op0;
1607 rtx op2 = m32r_compare_op1;
1608 enum machine_mode mode = GET_MODE (op0);
1613 if (! register_operand (op1, mode))
1614 op1 = force_reg (mode, op1);
1616 if (TARGET_M32RX || TARGET_M32R2)
1618 if (! reg_or_zero_operand (op2, mode))
1619 op2 = force_reg (mode, op2);
1621 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
1624 if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
1626 emit_insn (gen_seq_zero_insn (op0, op1));
1630 if (! reg_or_eq_int16_operand (op2, mode))
1631 op2 = force_reg (mode, op2);
1633 emit_insn (gen_seq_insn (op0, op1, op2));
1637 (define_insn "seq_insn_m32rx"
1638 [(set (match_operand:SI 0 "register_operand" "=r")
1639 (eq:SI (match_operand:SI 1 "register_operand" "%r")
1640 (match_operand:SI 2 "reg_or_zero_operand" "rP")))
1641 (clobber (reg:CC 17))]
1642 "TARGET_M32RX || TARGET_M32R2"
1644 [(set_attr "type" "multi")
1645 (set_attr "length" "6")])
1648 [(set (match_operand:SI 0 "register_operand" "")
1649 (eq:SI (match_operand:SI 1 "register_operand" "")
1650 (match_operand:SI 2 "reg_or_zero_operand" "")))
1651 (clobber (reg:CC 17))]
1652 "TARGET_M32RX || TARGET_M32R2"
1654 (eq:CC (match_dup 1)
1657 (ne:SI (reg:CC 17) (const_int 0)))]
1660 (define_insn "seq_zero_insn"
1661 [(set (match_operand:SI 0 "register_operand" "=r")
1662 (eq:SI (match_operand:SI 1 "register_operand" "r")
1664 (clobber (reg:CC 17))]
1667 [(set_attr "type" "multi")
1668 (set_attr "length" "6")])
1671 [(set (match_operand:SI 0 "register_operand" "")
1672 (eq:SI (match_operand:SI 1 "register_operand" "")
1674 (clobber (reg:CC 17))]
1679 rtx op0 = operands[0];
1680 rtx op1 = operands[1];
1683 emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
1684 emit_insn (gen_movcc_insn (op0));
1685 operands[3] = get_insns ();
1689 (define_insn "seq_insn"
1690 [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
1691 (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
1692 (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
1693 (clobber (reg:CC 17))
1694 (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
1697 [(set_attr "type" "multi")
1698 (set_attr "length" "8,8,10,10")])
1701 [(set (match_operand:SI 0 "register_operand" "")
1702 (eq:SI (match_operand:SI 1 "register_operand" "")
1703 (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
1704 (clobber (reg:CC 17))
1705 (clobber (match_scratch:SI 3 ""))]
1706 "TARGET_M32R && reload_completed"
1710 rtx op0 = operands[0];
1711 rtx op1 = operands[1];
1712 rtx op2 = operands[2];
1713 rtx op3 = operands[3];
1714 HOST_WIDE_INT value;
1716 if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
1717 && REGNO (op2) == REGNO (op3))
1724 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
1725 && REGNO (op1) != REGNO (op3))
1727 emit_move_insn (op3, op1);
1731 if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0)
1732 emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
1734 emit_insn (gen_xorsi3 (op3, op1, op2));
1736 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
1737 emit_insn (gen_movcc_insn (op0));
1738 operands[4] = get_insns ();
1742 (define_expand "sne"
1743 [(match_operand:SI 0 "register_operand" "")]
1747 rtx op0 = operands[0];
1748 rtx op1 = m32r_compare_op0;
1749 rtx op2 = m32r_compare_op1;
1750 enum machine_mode mode = GET_MODE (op0);
1755 if (GET_CODE (op2) != CONST_INT
1756 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
1760 if (reload_completed || reload_in_progress)
1763 reg = gen_reg_rtx (SImode);
1764 emit_insn (gen_xorsi3 (reg, op1, op2));
1767 if (! register_operand (op1, mode))
1768 op1 = force_reg (mode, op1);
1770 emit_insn (gen_sne_zero_insn (op0, op1));
1777 (define_insn "sne_zero_insn"
1778 [(set (match_operand:SI 0 "register_operand" "=r")
1779 (ne:SI (match_operand:SI 1 "register_operand" "r")
1781 (clobber (reg:CC 17))
1782 (clobber (match_scratch:SI 2 "=&r"))]
1785 [(set_attr "type" "multi")
1786 (set_attr "length" "6")])
1789 [(set (match_operand:SI 0 "register_operand" "")
1790 (ne:SI (match_operand:SI 1 "register_operand" "")
1792 (clobber (reg:CC 17))
1793 (clobber (match_scratch:SI 2 ""))]
1798 (ltu:CC (match_dup 2)
1801 (ne:SI (reg:CC 17) (const_int 0)))]
1804 (define_expand "slt"
1805 [(match_operand:SI 0 "register_operand" "")]
1809 rtx op0 = operands[0];
1810 rtx op1 = m32r_compare_op0;
1811 rtx op2 = m32r_compare_op1;
1812 enum machine_mode mode = GET_MODE (op0);
1817 if (! register_operand (op1, mode))
1818 op1 = force_reg (mode, op1);
1820 if (! reg_or_int16_operand (op2, mode))
1821 op2 = force_reg (mode, op2);
1823 emit_insn (gen_slt_insn (op0, op1, op2));
1827 (define_insn "slt_insn"
1828 [(set (match_operand:SI 0 "register_operand" "=r,r")
1829 (lt:SI (match_operand:SI 1 "register_operand" "r,r")
1830 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1831 (clobber (reg:CC 17))]
1834 [(set_attr "type" "multi")
1835 (set_attr "length" "4,6")])
1838 [(set (match_operand:SI 0 "register_operand" "")
1839 (lt:SI (match_operand:SI 1 "register_operand" "")
1840 (match_operand:SI 2 "reg_or_int16_operand" "")))
1841 (clobber (reg:CC 17))]
1844 (lt:CC (match_dup 1)
1847 (ne:SI (reg:CC 17) (const_int 0)))]
1850 (define_expand "sle"
1851 [(match_operand:SI 0 "register_operand" "")]
1855 rtx op0 = operands[0];
1856 rtx op1 = m32r_compare_op0;
1857 rtx op2 = m32r_compare_op1;
1858 enum machine_mode mode = GET_MODE (op0);
1863 if (! register_operand (op1, mode))
1864 op1 = force_reg (mode, op1);
1866 if (GET_CODE (op2) == CONST_INT)
1868 HOST_WIDE_INT value = INTVAL (op2);
1869 if (value >= 2147483647)
1871 emit_move_insn (op0, const1_rtx);
1875 op2 = GEN_INT (value+1);
1876 if (value < -32768 || value >= 32767)
1877 op2 = force_reg (mode, op2);
1879 emit_insn (gen_slt_insn (op0, op1, op2));
1883 if (! register_operand (op2, mode))
1884 op2 = force_reg (mode, op2);
1886 emit_insn (gen_sle_insn (op0, op1, op2));
1890 (define_insn "sle_insn"
1891 [(set (match_operand:SI 0 "register_operand" "=r")
1892 (le:SI (match_operand:SI 1 "register_operand" "r")
1893 (match_operand:SI 2 "register_operand" "r")))
1894 (clobber (reg:CC 17))]
1897 [(set_attr "type" "multi")
1898 (set_attr "length" "8")])
1901 [(set (match_operand:SI 0 "register_operand" "")
1902 (le:SI (match_operand:SI 1 "register_operand" "")
1903 (match_operand:SI 2 "register_operand" "")))
1904 (clobber (reg:CC 17))]
1907 (lt:CC (match_dup 2)
1910 (ne:SI (reg:CC 17) (const_int 0)))
1912 (xor:SI (match_dup 0)
1916 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1917 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1919 [(set (match_operand:SI 0 "register_operand" "")
1920 (le:SI (match_operand:SI 1 "register_operand" "")
1921 (match_operand:SI 2 "register_operand" "")))
1922 (clobber (reg:CC 17))]
1925 (lt:CC (match_dup 2)
1928 (ne:SI (reg:CC 17) (const_int 0)))
1930 (plus:SI (match_dup 0)
1933 (neg:SI (match_dup 0)))]
1936 (define_expand "sgt"
1937 [(match_operand:SI 0 "register_operand" "")]
1941 rtx op0 = operands[0];
1942 rtx op1 = m32r_compare_op0;
1943 rtx op2 = m32r_compare_op1;
1944 enum machine_mode mode = GET_MODE (op0);
1949 if (! register_operand (op1, mode))
1950 op1 = force_reg (mode, op1);
1952 if (! register_operand (op2, mode))
1953 op2 = force_reg (mode, op2);
1955 emit_insn (gen_slt_insn (op0, op2, op1));
1959 (define_expand "sge"
1960 [(match_operand:SI 0 "register_operand" "")]
1964 rtx op0 = operands[0];
1965 rtx op1 = m32r_compare_op0;
1966 rtx op2 = m32r_compare_op1;
1967 enum machine_mode mode = GET_MODE (op0);
1972 if (! register_operand (op1, mode))
1973 op1 = force_reg (mode, op1);
1975 if (! reg_or_int16_operand (op2, mode))
1976 op2 = force_reg (mode, op2);
1978 emit_insn (gen_sge_insn (op0, op1, op2));
1982 (define_insn "sge_insn"
1983 [(set (match_operand:SI 0 "register_operand" "=r,r")
1984 (ge:SI (match_operand:SI 1 "register_operand" "r,r")
1985 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1986 (clobber (reg:CC 17))]
1989 [(set_attr "type" "multi")
1990 (set_attr "length" "8,10")])
1993 [(set (match_operand:SI 0 "register_operand" "")
1994 (ge:SI (match_operand:SI 1 "register_operand" "")
1995 (match_operand:SI 2 "reg_or_int16_operand" "")))
1996 (clobber (reg:CC 17))]
1999 (lt:CC (match_dup 1)
2002 (ne:SI (reg:CC 17) (const_int 0)))
2004 (xor:SI (match_dup 0)
2008 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2009 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2011 [(set (match_operand:SI 0 "register_operand" "")
2012 (ge:SI (match_operand:SI 1 "register_operand" "")
2013 (match_operand:SI 2 "reg_or_int16_operand" "")))
2014 (clobber (reg:CC 17))]
2017 (lt:CC (match_dup 1)
2020 (ne:SI (reg:CC 17) (const_int 0)))
2022 (plus:SI (match_dup 0)
2025 (neg:SI (match_dup 0)))]
2028 (define_expand "sltu"
2029 [(match_operand:SI 0 "register_operand" "")]
2033 rtx op0 = operands[0];
2034 rtx op1 = m32r_compare_op0;
2035 rtx op2 = m32r_compare_op1;
2036 enum machine_mode mode = GET_MODE (op0);
2041 if (! register_operand (op1, mode))
2042 op1 = force_reg (mode, op1);
2044 if (! reg_or_int16_operand (op2, mode))
2045 op2 = force_reg (mode, op2);
2047 emit_insn (gen_sltu_insn (op0, op1, op2));
2051 (define_insn "sltu_insn"
2052 [(set (match_operand:SI 0 "register_operand" "=r,r")
2053 (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
2054 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2055 (clobber (reg:CC 17))]
2058 [(set_attr "type" "multi")
2059 (set_attr "length" "6,8")])
2062 [(set (match_operand:SI 0 "register_operand" "")
2063 (ltu:SI (match_operand:SI 1 "register_operand" "")
2064 (match_operand:SI 2 "reg_or_int16_operand" "")))
2065 (clobber (reg:CC 17))]
2068 (ltu:CC (match_dup 1)
2071 (ne:SI (reg:CC 17) (const_int 0)))]
2074 (define_expand "sleu"
2075 [(match_operand:SI 0 "register_operand" "")]
2079 rtx op0 = operands[0];
2080 rtx op1 = m32r_compare_op0;
2081 rtx op2 = m32r_compare_op1;
2082 enum machine_mode mode = GET_MODE (op0);
2087 if (GET_CODE (op2) == CONST_INT)
2089 HOST_WIDE_INT value = INTVAL (op2);
2090 if (value >= 2147483647)
2092 emit_move_insn (op0, const1_rtx);
2096 op2 = GEN_INT (value+1);
2097 if (value < 0 || value >= 32767)
2098 op2 = force_reg (mode, op2);
2100 emit_insn (gen_sltu_insn (op0, op1, op2));
2104 if (! register_operand (op2, mode))
2105 op2 = force_reg (mode, op2);
2107 emit_insn (gen_sleu_insn (op0, op1, op2));
2111 (define_insn "sleu_insn"
2112 [(set (match_operand:SI 0 "register_operand" "=r")
2113 (leu:SI (match_operand:SI 1 "register_operand" "r")
2114 (match_operand:SI 2 "register_operand" "r")))
2115 (clobber (reg:CC 17))]
2118 [(set_attr "type" "multi")
2119 (set_attr "length" "8")])
2122 [(set (match_operand:SI 0 "register_operand" "")
2123 (leu:SI (match_operand:SI 1 "register_operand" "")
2124 (match_operand:SI 2 "register_operand" "")))
2125 (clobber (reg:CC 17))]
2128 (ltu:CC (match_dup 2)
2131 (ne:SI (reg:CC 17) (const_int 0)))
2133 (xor:SI (match_dup 0)
2137 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2138 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2140 [(set (match_operand:SI 0 "register_operand" "")
2141 (leu:SI (match_operand:SI 1 "register_operand" "")
2142 (match_operand:SI 2 "register_operand" "")))
2143 (clobber (reg:CC 17))]
2146 (ltu:CC (match_dup 2)
2149 (ne:SI (reg:CC 17) (const_int 0)))
2151 (plus:SI (match_dup 0)
2154 (neg:SI (match_dup 0)))]
2157 (define_expand "sgtu"
2158 [(match_operand:SI 0 "register_operand" "")]
2162 rtx op0 = operands[0];
2163 rtx op1 = m32r_compare_op0;
2164 rtx op2 = m32r_compare_op1;
2165 enum machine_mode mode = GET_MODE (op0);
2170 if (! register_operand (op1, mode))
2171 op1 = force_reg (mode, op1);
2173 if (! register_operand (op2, mode))
2174 op2 = force_reg (mode, op2);
2176 emit_insn (gen_sltu_insn (op0, op2, op1));
2180 (define_expand "sgeu"
2181 [(match_operand:SI 0 "register_operand" "")]
2185 rtx op0 = operands[0];
2186 rtx op1 = m32r_compare_op0;
2187 rtx op2 = m32r_compare_op1;
2188 enum machine_mode mode = GET_MODE (op0);
2193 if (! register_operand (op1, mode))
2194 op1 = force_reg (mode, op1);
2196 if (! reg_or_int16_operand (op2, mode))
2197 op2 = force_reg (mode, op2);
2199 emit_insn (gen_sgeu_insn (op0, op1, op2));
2203 (define_insn "sgeu_insn"
2204 [(set (match_operand:SI 0 "register_operand" "=r,r")
2205 (geu:SI (match_operand:SI 1 "register_operand" "r,r")
2206 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2207 (clobber (reg:CC 17))]
2210 [(set_attr "type" "multi")
2211 (set_attr "length" "8,10")])
2214 [(set (match_operand:SI 0 "register_operand" "")
2215 (geu:SI (match_operand:SI 1 "register_operand" "")
2216 (match_operand:SI 2 "reg_or_int16_operand" "")))
2217 (clobber (reg:CC 17))]
2220 (ltu:CC (match_dup 1)
2223 (ne:SI (reg:CC 17) (const_int 0)))
2225 (xor:SI (match_dup 0)
2229 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2230 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2232 [(set (match_operand:SI 0 "register_operand" "")
2233 (geu:SI (match_operand:SI 1 "register_operand" "")
2234 (match_operand:SI 2 "reg_or_int16_operand" "")))
2235 (clobber (reg:CC 17))]
2238 (ltu:CC (match_dup 1)
2241 (ne:SI (reg:CC 17) (const_int 0)))
2243 (plus:SI (match_dup 0)
2246 (neg:SI (match_dup 0)))]
2249 (define_insn "movcc_insn"
2250 [(set (match_operand:SI 0 "register_operand" "=r")
2251 (ne:SI (reg:CC 17) (const_int 0)))]
2254 [(set_attr "type" "misc")
2255 (set_attr "length" "2")])
2258 ;; Unconditional and other jump instructions.
2261 [(set (pc) (label_ref (match_operand 0 "" "")))]
2264 [(set_attr "type" "uncond_branch")
2265 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
2271 (define_insn "indirect_jump"
2272 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
2275 [(set_attr "type" "uncond_branch")
2276 (set_attr "length" "2")])
2278 (define_insn "return_lr"
2279 [(parallel [(return) (use (reg:SI 14))])]
2282 [(set_attr "type" "uncond_branch")
2283 (set_attr "length" "2")])
2285 (define_insn "return_rte"
2289 [(set_attr "type" "uncond_branch")
2290 (set_attr "length" "2")])
2292 (define_expand "return"
2297 emit_jump_insn (gen_return_lr ());
2301 (define_expand "return_normal"
2306 enum m32r_function_type fn_type;
2308 fn_type = m32r_compute_function_type (current_function_decl);
2309 if (M32R_INTERRUPT_P (fn_type))
2311 emit_jump_insn (gen_return_rte ());
2315 emit_jump_insn (gen_return_lr ());
2319 (define_expand "tablejump"
2320 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
2321 (use (label_ref (match_operand 1 "" "")))])]
2325 /* In pic mode, our address differences are against the base of the
2326 table. Add that base value back in; CSE ought to be able to combine
2327 the two address loads. */
2332 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
2334 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
2335 operands[0] = memory_address (Pmode, tmp);
2339 (define_insn "*tablejump_insn"
2340 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
2341 (use (label_ref (match_operand 1 "" "")))]
2344 [(set_attr "type" "uncond_branch")
2345 (set_attr "length" "2")])
2347 (define_expand "call"
2348 ;; operands[1] is stack_size_rtx
2349 ;; operands[2] is next_arg_register
2350 [(parallel [(call (match_operand:SI 0 "call_operand" "")
2351 (match_operand 1 "" ""))
2352 (clobber (reg:SI 14))])]
2357 crtl->uses_pic_offset_table = 1;
2360 (define_insn "*call_via_reg"
2361 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
2362 (match_operand 1 "" ""))
2363 (clobber (reg:SI 14))]
2366 [(set_attr "type" "call")
2367 (set_attr "length" "2")])
2369 (define_insn "*call_via_label"
2370 [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
2371 (match_operand 1 "" ""))
2372 (clobber (reg:SI 14))]
2376 int call26_p = call26_operand (operands[0], FUNCTION_MODE);
2380 /* We may not be able to reach with a `bl' insn so punt and leave it to
2382 We do this here, rather than doing a force_reg in the define_expand
2383 so these insns won't be separated, say by scheduling, thus simplifying
2385 return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
2390 [(set_attr "type" "call")
2391 (set (attr "length")
2392 (if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
2394 (const_int 12) ; 10 + 2 for nop filler
2395 ; The return address must be on a 4 byte boundary so
2396 ; there's no point in using a value of 2 here. A 2 byte
2397 ; insn may go in the left slot but we currently can't
2398 ; use such knowledge.
2401 (define_expand "call_value"
2402 ;; operand 2 is stack_size_rtx
2403 ;; operand 3 is next_arg_register
2404 [(parallel [(set (match_operand 0 "register_operand" "=r")
2405 (call (match_operand:SI 1 "call_operand" "")
2406 (match_operand 2 "" "")))
2407 (clobber (reg:SI 14))])]
2412 crtl->uses_pic_offset_table = 1;
2415 (define_insn "*call_value_via_reg"
2416 [(set (match_operand 0 "register_operand" "=r")
2417 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
2418 (match_operand 2 "" "")))
2419 (clobber (reg:SI 14))]
2422 [(set_attr "type" "call")
2423 (set_attr "length" "2")])
2425 (define_insn "*call_value_via_label"
2426 [(set (match_operand 0 "register_operand" "=r")
2427 (call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
2428 (match_operand 2 "" "")))
2429 (clobber (reg:SI 14))]
2433 int call26_p = call26_operand (operands[1], FUNCTION_MODE);
2436 crtl->uses_pic_offset_table = 1;
2440 /* We may not be able to reach with a `bl' insn so punt and leave it to
2442 We do this here, rather than doing a force_reg in the define_expand
2443 so these insns won't be separated, say by scheduling, thus simplifying
2445 return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
2450 [(set_attr "type" "call")
2451 (set (attr "length")
2452 (if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
2454 (const_int 12) ; 10 + 2 for nop filler
2455 ; The return address must be on a 4 byte boundary so
2456 ; there's no point in using a value of 2 here. A 2 byte
2457 ; insn may go in the left slot but we currently can't
2458 ; use such knowledge.
2465 [(set_attr "type" "int2")
2466 (set_attr "length" "2")])
2468 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2469 ;; all of memory. This blocks insns from being moved across this point.
2471 (define_insn "blockage"
2472 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
2476 ;; Special pattern to flush the icache.
2478 (define_insn "flush_icache"
2479 [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
2480 UNSPECV_FLUSH_ICACHE)
2481 (match_operand 1 "" "")
2482 (clobber (reg:SI 17))]
2484 "* return \"trap %#%1 ; flush-icache\";"
2485 [(set_attr "type" "int4")
2486 (set_attr "length" "4")])
2488 ;; Speed up fabs and provide correct sign handling for -0
2490 (define_insn "absdf2"
2491 [(set (match_operand:DF 0 "register_operand" "=r")
2492 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
2495 [(set_attr "type" "multi")
2496 (set_attr "length" "4")])
2499 [(set (match_operand:DF 0 "register_operand" "")
2500 (abs:DF (match_operand:DF 1 "register_operand" "")))]
2503 (ashift:SI (match_dup 2)
2506 (lshiftrt:SI (match_dup 2)
2508 "operands[2] = gen_highpart (SImode, operands[0]);")
2510 (define_insn "abssf2"
2511 [(set (match_operand:SF 0 "register_operand" "=r")
2512 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2515 [(set_attr "type" "multi")
2516 (set_attr "length" "4")])
2519 [(set (match_operand:SF 0 "register_operand" "")
2520 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2523 (ashift:SI (match_dup 2)
2526 (lshiftrt:SI (match_dup 2)
2528 "operands[2] = gen_highpart (SImode, operands[0]);")
2530 ;; Conditional move instructions
2531 ;; Based on those done for the d10v
2533 (define_expand "movsicc"
2535 (set (match_operand:SI 0 "register_operand" "r")
2536 (if_then_else:SI (match_operand 1 "" "")
2537 (match_operand:SI 2 "conditional_move_operand" "O")
2538 (match_operand:SI 3 "conditional_move_operand" "O")
2545 if (! zero_and_one (operands [2], operands [3]))
2548 /* Generate the comparison that will set the carry flag. */
2549 operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0,
2550 m32r_compare_op1, TRUE);
2552 /* See other movsicc pattern below for reason why. */
2553 emit_insn (gen_blockage ());
2556 ;; Generate the conditional instructions based on how the carry flag is examined.
2557 (define_insn "*movsicc_internal"
2558 [(set (match_operand:SI 0 "register_operand" "=r")
2559 (if_then_else:SI (match_operand 1 "carry_compare_operand" "")
2560 (match_operand:SI 2 "conditional_move_operand" "O")
2561 (match_operand:SI 3 "conditional_move_operand" "O")
2564 "zero_and_one (operands [2], operands[3])"
2565 "* return emit_cond_move (operands, insn);"
2566 [(set_attr "type" "multi")
2567 (set_attr "length" "8")
2572 ;; Block moves, see m32r.c for more details.
2573 ;; Argument 0 is the destination
2574 ;; Argument 1 is the source
2575 ;; Argument 2 is the length
2576 ;; Argument 3 is the alignment
2578 (define_expand "movmemsi"
2579 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
2580 (match_operand:BLK 1 "general_operand" ""))
2581 (use (match_operand:SI 2 "immediate_operand" ""))
2582 (use (match_operand:SI 3 "immediate_operand" ""))])]
2586 if (operands[0]) /* Avoid unused code messages. */
2588 if (m32r_expand_block_move (operands))
2595 ;; Insn generated by block moves
2597 (define_insn "movmemsi_internal"
2598 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
2599 (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
2600 (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
2601 (set (match_operand:SI 3 "register_operand" "=0")
2602 (plus:SI (minus (match_dup 2) (const_int 4))
2604 (set (match_operand:SI 4 "register_operand" "=1")
2605 (plus:SI (match_dup 1)
2607 (clobber (match_scratch:SI 5 "=&r")) ;; temp1
2608 (clobber (match_scratch:SI 6 "=&r"))] ;; temp2
2610 "* m32r_output_block_move (insn, operands); return \"\"; "
2611 [(set_attr "type" "store8")
2612 (set_attr "length" "72")]) ;; Maximum
2616 /* When generating pic, we need to load the symbol offset into a register.
2617 So that the optimizer does not confuse this with a normal symbol load
2618 we use an unspec. The offset will be loaded from a constant pool entry,
2619 since that is the only type of relocation we can use. */
2621 (define_insn "pic_load_addr"
2622 [(set (match_operand:SI 0 "register_operand" "=r")
2623 (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
2626 [(set_attr "type" "int4")])
2628 (define_insn "gotoff_load_addr"
2629 [(set (match_operand:SI 0 "register_operand" "=r")
2630 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
2632 "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
2633 [(set_attr "type" "int4")
2634 (set_attr "length" "8")])
2636 ;; Load program counter insns.
2638 (define_insn "get_pc"
2639 [(clobber (reg:SI 14))
2640 (set (match_operand 0 "register_operand" "=r,r")
2641 (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
2642 (use (match_operand:SI 2 "immediate_operand" "W,i"))]
2645 bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr
2646 bl.s .+4\;ld24 %0,%#%1\;add %0,lr"
2647 [(set_attr "length" "12,8")])
2649 (define_expand "builtin_setjmp_receiver"
2650 [(label_ref (match_operand 0 "" ""))]
2654 m32r_load_pic_register ();