include/xtensa-dynconfig.h

   1 /* Xtensa configuration settings.
   2    Copyright (C) 2022-2023 Free Software Foundation, Inc.
   3
   4    This program is free software; you can redistribute it and/or modify
   5    it under the terms of the GNU General Public License as published by
   6    the Free Software Foundation; either version 2, or (at your option)
   7    any later version.
   8
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12    General Public License for more details.
  13
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software
  16    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  17
  18 #ifndef XTENSA_DYNCONFIG_H
  19 #define XTENSA_DYNCONFIG_H
  20
  21 #ifdef __cplusplus
  22 extern "C" {
  23 #endif
  24
  25 /*
  26  * Config versioning.
  27  *
  28  * When new config entries need to be passed through dynconfig
  29  * create new xtensa_config_v<N> structure and put them there.
  30  * Declare new function xtensa_get_config_v<N> (void).
  31  * Define corresponding X*HAL_* macros by accessing xtensa_get_config_v<N> ().
  32  * Define macro XTENSA_CONFIG_V<N>_ENTRY_LIST by listing
  33  * XTENSA_CONFIG_ENTRY for every entry in the new structure.
  34  * Add constant definition for the new xtensa_config_v<N> to the
  35  * XTENSA_CONFIG_INSTANCE_LIST.
  36  * Add XTENSA_CONFIG_V<N>_ENTRY_LIST to the XTENSA_CONFIG_ENTRY_LIST.
  37  *
  38  * On the user side (gcc/binutils/...) add definition for the function
  39  * xtensa_get_config_v<N> (void).
  40  */
  41
  42 struct xtensa_config_v1
  43 {
  44   int xchal_have_be;
  45   int xchal_have_density;
  46   int xchal_have_const16;
  47   int xchal_have_abs;
  48   int xchal_have_addx;
  49   int xchal_have_l32r;
  50   int xshal_use_absolute_literals;
  51   int xshal_have_text_section_literals;
  52   int xchal_have_mac16;
  53   int xchal_have_mul16;
  54   int xchal_have_mul32;
  55   int xchal_have_mul32_high;
  56   int xchal_have_div32;
  57   int xchal_have_nsa;
  58   int xchal_have_minmax;
  59   int xchal_have_sext;
  60   int xchal_have_loops;
  61   int xchal_have_threadptr;
  62   int xchal_have_release_sync;
  63   int xchal_have_s32c1i;
  64   int xchal_have_booleans;
  65   int xchal_have_fp;
  66   int xchal_have_fp_div;
  67   int xchal_have_fp_recip;
  68   int xchal_have_fp_sqrt;
  69   int xchal_have_fp_rsqrt;
  70   int xchal_have_fp_postinc;
  71   int xchal_have_dfp;
  72   int xchal_have_dfp_div;
  73   int xchal_have_dfp_recip;
  74   int xchal_have_dfp_sqrt;
  75   int xchal_have_dfp_rsqrt;
  76   int xchal_have_windowed;
  77   int xchal_num_aregs;
  78   int xchal_have_wide_branches;
  79   int xchal_have_predicted_branches;
  80   int xchal_icache_size;
  81   int xchal_dcache_size;
  82   int xchal_icache_linesize;
  83   int xchal_dcache_linesize;
  84   int xchal_icache_linewidth;
  85   int xchal_dcache_linewidth;
  86   int xchal_dcache_is_writeback;
  87   int xchal_have_mmu;
  88   int xchal_mmu_min_pte_page_size;
  89   int xchal_have_debug;
  90   int xchal_num_ibreak;
  91   int xchal_num_dbreak;
  92   int xchal_debuglevel;
  93   int xchal_max_instruction_size;
  94   int xchal_inst_fetch_width;
  95   int xshal_abi;
  96   int xthal_abi_windowed;
  97   int xthal_abi_call0;
  98 };
  99
 100 struct xtensa_config_v2
 101 {
 102   int xchal_m_stage;
 103   int xtensa_march_latest;
 104   int xtensa_march_earliest;
 105 };
 106
 107 struct xtensa_config_v3
 108 {
 109   int xchal_have_clamps;
 110   int xchal_have_depbits;
 111   int xchal_have_exclusive;
 112   int xchal_have_xea3;
 113 };
 114
 115 struct xtensa_config_v4
 116 {
 117   int xchal_data_width;
 118   int xchal_unaligned_load_exception;
 119   int xchal_unaligned_store_exception;
 120   int xchal_unaligned_load_hw;
 121   int xchal_unaligned_store_hw;
 122 };
 123
 124 extern const void *xtensa_load_config (const char *name,
 125                                        const void *no_plugin_def,
 126                                        const void *no_name_def);
 127 extern const struct xtensa_config_v1 *xtensa_get_config_v1 (void);
 128 extern const struct xtensa_config_v2 *xtensa_get_config_v2 (void);
 129 extern const struct xtensa_config_v3 *xtensa_get_config_v3 (void);
 130 extern const struct xtensa_config_v4 *xtensa_get_config_v4 (void);
 131
 132 #ifdef XTENSA_CONFIG_DEFINITION
 133
 134 #ifndef XCHAL_HAVE_MUL32_HIGH
 135 #define XCHAL_HAVE_MUL32_HIGH 0
 136 #endif
 137
 138 #ifndef XCHAL_HAVE_RELEASE_SYNC
 139 #define XCHAL_HAVE_RELEASE_SYNC 0
 140 #endif
 141
 142 #ifndef XCHAL_HAVE_S32C1I
 143 #define XCHAL_HAVE_S32C1I 0
 144 #endif
 145
 146 #ifndef XCHAL_HAVE_THREADPTR
 147 #define XCHAL_HAVE_THREADPTR 0
 148 #endif
 149
 150 #ifndef XCHAL_HAVE_FP_POSTINC
 151 #define XCHAL_HAVE_FP_POSTINC 0
 152 #endif
 153
 154 #ifndef XCHAL_HAVE_DFP
 155 #define XCHAL_HAVE_DFP 0
 156 #endif
 157
 158 #ifndef XCHAL_HAVE_DFP_DIV
 159 #define XCHAL_HAVE_DFP_DIV 0
 160 #endif
 161
 162 #ifndef XCHAL_HAVE_DFP_RECIP
 163 #define XCHAL_HAVE_DFP_RECIP 0
 164 #endif
 165
 166 #ifndef XCHAL_HAVE_DFP_SQRT
 167 #define XCHAL_HAVE_DFP_SQRT 0
 168 #endif
 169
 170 #ifndef XCHAL_HAVE_DFP_RSQRT
 171 #define XCHAL_HAVE_DFP_RSQRT 0
 172 #endif
 173
 174 #ifndef XSHAL_HAVE_TEXT_SECTION_LITERALS
 175 #define XSHAL_HAVE_TEXT_SECTION_LITERALS 0
 176 #endif
 177
 178 #ifndef XCHAL_MMU_MIN_PTE_PAGE_SIZE
 179 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 1
 180 #endif
 181
 182 #ifndef XTHAL_ABI_WINDOWED
 183 #define XTHAL_ABI_WINDOWED 0
 184 #endif
 185
 186 #ifndef XTHAL_ABI_CALL0
 187 #define XTHAL_ABI_CALL0 1
 188 #endif
 189
 190 #ifndef XCHAL_M_STAGE
 191 #define XCHAL_M_STAGE 0
 192 #endif
 193
 194 #ifndef XTENSA_MARCH_LATEST
 195 #define XTENSA_MARCH_LATEST 0
 196 #endif
 197
 198 #ifndef XTENSA_MARCH_EARLIEST
 199 #define XTENSA_MARCH_EARLIEST 0
 200 #endif
 201
 202 #ifndef XCHAL_HAVE_CLAMPS
 203 #define XCHAL_HAVE_CLAMPS 0
 204 #endif
 205
 206 #ifndef XCHAL_HAVE_DEPBITS
 207 #define XCHAL_HAVE_DEPBITS 0
 208 #endif
 209
 210 #ifndef XCHAL_HAVE_EXCLUSIVE
 211 #define XCHAL_HAVE_EXCLUSIVE 0
 212 #endif
 213
 214 #ifndef XCHAL_HAVE_XEA3
 215 #define XCHAL_HAVE_XEA3 0
 216 #endif
 217
 218 #ifndef XCHAL_DATA_WIDTH
 219 #define XCHAL_DATA_WIDTH 16
 220 #endif
 221
 222 #ifndef XCHAL_UNALIGNED_LOAD_EXCEPTION
 223 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1
 224 #endif
 225
 226 #ifndef XCHAL_UNALIGNED_STORE_EXCEPTION
 227 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1
 228 #endif
 229
 230 #ifndef XCHAL_UNALIGNED_LOAD_HW
 231 #define XCHAL_UNALIGNED_LOAD_HW 0
 232 #endif
 233
 234 #ifndef XCHAL_UNALIGNED_STORE_HW
 235 #define XCHAL_UNALIGNED_STORE_HW 0
 236 #endif
 237
 238 #define XTENSA_CONFIG_ENTRY(a) a
 239
 240 #define XTENSA_CONFIG_V1_ENTRY_LIST \
 241     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_BE), \
 242     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DENSITY), \
 243     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_CONST16), \
 244     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_ABS), \
 245     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_ADDX), \
 246     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_L32R), \
 247     XTENSA_CONFIG_ENTRY(XSHAL_USE_ABSOLUTE_LITERALS), \
 248     XTENSA_CONFIG_ENTRY(XSHAL_HAVE_TEXT_SECTION_LITERALS), \
 249     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MAC16), \
 250     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL16), \
 251     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL32), \
 252     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL32_HIGH), \
 253     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DIV32), \
 254     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_NSA), \
 255     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MINMAX), \
 256     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_SEXT), \
 257     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_LOOPS), \
 258     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_THREADPTR), \
 259     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_RELEASE_SYNC), \
 260     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_S32C1I), \
 261     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_BOOLEANS), \
 262     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP), \
 263     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_DIV), \
 264     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_RECIP), \
 265     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_SQRT), \
 266     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_RSQRT), \
 267     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_POSTINC), \
 268     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP), \
 269     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_DIV), \
 270     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_RECIP), \
 271     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_SQRT), \
 272     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_RSQRT), \
 273     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_WINDOWED), \
 274     XTENSA_CONFIG_ENTRY(XCHAL_NUM_AREGS), \
 275     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_WIDE_BRANCHES), \
 276     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_PREDICTED_BRANCHES), \
 277     XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_SIZE), \
 278     XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_SIZE), \
 279     XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_LINESIZE), \
 280     XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_LINESIZE), \
 281     XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_LINEWIDTH), \
 282     XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_LINEWIDTH), \
 283     XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_IS_WRITEBACK), \
 284     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MMU), \
 285     XTENSA_CONFIG_ENTRY(XCHAL_MMU_MIN_PTE_PAGE_SIZE), \
 286     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DEBUG), \
 287     XTENSA_CONFIG_ENTRY(XCHAL_NUM_IBREAK), \
 288     XTENSA_CONFIG_ENTRY(XCHAL_NUM_DBREAK), \
 289     XTENSA_CONFIG_ENTRY(XCHAL_DEBUGLEVEL), \
 290     XTENSA_CONFIG_ENTRY(XCHAL_MAX_INSTRUCTION_SIZE), \
 291     XTENSA_CONFIG_ENTRY(XCHAL_INST_FETCH_WIDTH), \
 292     XTENSA_CONFIG_ENTRY(XSHAL_ABI), \
 293     XTENSA_CONFIG_ENTRY(XTHAL_ABI_WINDOWED), \
 294     XTENSA_CONFIG_ENTRY(XTHAL_ABI_CALL0)
 295
 296 #define XTENSA_CONFIG_V2_ENTRY_LIST \
 297     XTENSA_CONFIG_ENTRY(XCHAL_M_STAGE), \
 298     XTENSA_CONFIG_ENTRY(XTENSA_MARCH_LATEST), \
 299     XTENSA_CONFIG_ENTRY(XTENSA_MARCH_EARLIEST)
 300
 301 #define XTENSA_CONFIG_V3_ENTRY_LIST \
 302     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_CLAMPS), \
 303     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DEPBITS), \
 304     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_EXCLUSIVE), \
 305     XTENSA_CONFIG_ENTRY(XCHAL_HAVE_XEA3)
 306
 307 #define XTENSA_CONFIG_V4_ENTRY_LIST \
 308     XTENSA_CONFIG_ENTRY(XCHAL_DATA_WIDTH), \
 309     XTENSA_CONFIG_ENTRY(XCHAL_UNALIGNED_LOAD_EXCEPTION), \
 310     XTENSA_CONFIG_ENTRY(XCHAL_UNALIGNED_STORE_EXCEPTION), \
 311     XTENSA_CONFIG_ENTRY(XCHAL_UNALIGNED_LOAD_HW), \
 312     XTENSA_CONFIG_ENTRY(XCHAL_UNALIGNED_STORE_HW)
 313
 314 #define XTENSA_CONFIG_INSTANCE_LIST \
 315 const struct xtensa_config_v1 xtensa_config_v1 = { \
 316     XTENSA_CONFIG_V1_ENTRY_LIST, \
 317 }; \
 318 const struct xtensa_config_v2 xtensa_config_v2 = { \
 319     XTENSA_CONFIG_V2_ENTRY_LIST, \
 320 }; \
 321 const struct xtensa_config_v3 xtensa_config_v3 = { \
 322     XTENSA_CONFIG_V3_ENTRY_LIST, \
 323 }; \
 324 const struct xtensa_config_v4 xtensa_config_v4 = { \
 325     XTENSA_CONFIG_V4_ENTRY_LIST, \
 326 }
 327
 328 #define XTENSA_CONFIG_ENTRY_LIST \
 329     XTENSA_CONFIG_V1_ENTRY_LIST, \
 330     XTENSA_CONFIG_V2_ENTRY_LIST, \
 331     XTENSA_CONFIG_V3_ENTRY_LIST, \
 332     XTENSA_CONFIG_V4_ENTRY_LIST
 333
 334 #else /* XTENSA_CONFIG_DEFINITION */
 335
 336 #undef XCHAL_HAVE_BE
 337 #define XCHAL_HAVE_BE                   (xtensa_get_config_v1 ()->xchal_have_be)
 338
 339 #undef XCHAL_HAVE_DENSITY
 340 #define XCHAL_HAVE_DENSITY              (xtensa_get_config_v1 ()->xchal_have_density)
 341
 342 #undef XCHAL_HAVE_CONST16
 343 #define XCHAL_HAVE_CONST16              (xtensa_get_config_v1 ()->xchal_have_const16)
 344
 345 #undef XCHAL_HAVE_ABS
 346 #define XCHAL_HAVE_ABS                  (xtensa_get_config_v1 ()->xchal_have_abs)
 347
 348 #undef XCHAL_HAVE_ADDX
 349 #define XCHAL_HAVE_ADDX                 (xtensa_get_config_v1 ()->xchal_have_addx)
 350
 351 #undef XCHAL_HAVE_L32R
 352 #define XCHAL_HAVE_L32R                 (xtensa_get_config_v1 ()->xchal_have_l32r)
 353
 354 #undef XSHAL_USE_ABSOLUTE_LITERALS
 355 #define XSHAL_USE_ABSOLUTE_LITERALS     (xtensa_get_config_v1 ()->xshal_use_absolute_literals)
 356
 357 #undef XSHAL_HAVE_TEXT_SECTION_LITERALS
 358 #define XSHAL_HAVE_TEXT_SECTION_LITERALS (xtensa_get_config_v1 ()->xshal_have_text_section_literals)
 359
 360 #undef XCHAL_HAVE_MAC16
 361 #define XCHAL_HAVE_MAC16                (xtensa_get_config_v1 ()->xchal_have_mac16)
 362
 363 #undef XCHAL_HAVE_MUL16
 364 #define XCHAL_HAVE_MUL16                (xtensa_get_config_v1 ()->xchal_have_mul16)
 365
 366 #undef XCHAL_HAVE_MUL32
 367 #define XCHAL_HAVE_MUL32                (xtensa_get_config_v1 ()->xchal_have_mul32)
 368
 369 #undef XCHAL_HAVE_MUL32_HIGH
 370 #define XCHAL_HAVE_MUL32_HIGH           (xtensa_get_config_v1 ()->xchal_have_mul32_high)
 371
 372 #undef XCHAL_HAVE_DIV32
 373 #define XCHAL_HAVE_DIV32                (xtensa_get_config_v1 ()->xchal_have_div32)
 374
 375 #undef XCHAL_HAVE_NSA
 376 #define XCHAL_HAVE_NSA                  (xtensa_get_config_v1 ()->xchal_have_nsa)
 377
 378 #undef XCHAL_HAVE_MINMAX
 379 #define XCHAL_HAVE_MINMAX               (xtensa_get_config_v1 ()->xchal_have_minmax)
 380
 381 #undef XCHAL_HAVE_SEXT
 382 #define XCHAL_HAVE_SEXT                 (xtensa_get_config_v1 ()->xchal_have_sext)
 383
 384 #undef XCHAL_HAVE_LOOPS
 385 #define XCHAL_HAVE_LOOPS                (xtensa_get_config_v1 ()->xchal_have_loops)
 386
 387 #undef XCHAL_HAVE_THREADPTR
 388 #define XCHAL_HAVE_THREADPTR            (xtensa_get_config_v1 ()->xchal_have_threadptr)
 389
 390 #undef XCHAL_HAVE_RELEASE_SYNC
 391 #define XCHAL_HAVE_RELEASE_SYNC         (xtensa_get_config_v1 ()->xchal_have_release_sync)
 392
 393 #undef XCHAL_HAVE_S32C1I
 394 #define XCHAL_HAVE_S32C1I               (xtensa_get_config_v1 ()->xchal_have_s32c1i)
 395
 396 #undef XCHAL_HAVE_BOOLEANS
 397 #define XCHAL_HAVE_BOOLEANS             (xtensa_get_config_v1 ()->xchal_have_booleans)
 398
 399 #undef XCHAL_HAVE_FP
 400 #define XCHAL_HAVE_FP                   (xtensa_get_config_v1 ()->xchal_have_fp)
 401
 402 #undef XCHAL_HAVE_FP_DIV
 403 #define XCHAL_HAVE_FP_DIV               (xtensa_get_config_v1 ()->xchal_have_fp_div)
 404
 405 #undef XCHAL_HAVE_FP_RECIP
 406 #define XCHAL_HAVE_FP_RECIP             (xtensa_get_config_v1 ()->xchal_have_fp_recip)
 407
 408 #undef XCHAL_HAVE_FP_SQRT
 409 #define XCHAL_HAVE_FP_SQRT              (xtensa_get_config_v1 ()->xchal_have_fp_sqrt)
 410
 411 #undef XCHAL_HAVE_FP_RSQRT
 412 #define XCHAL_HAVE_FP_RSQRT             (xtensa_get_config_v1 ()->xchal_have_fp_rsqrt)
 413
 414 #undef XCHAL_HAVE_FP_POSTINC
 415 #define XCHAL_HAVE_FP_POSTINC           (xtensa_get_config_v1 ()->xchal_have_fp_postinc)
 416
 417 #undef XCHAL_HAVE_DFP
 418 #define XCHAL_HAVE_DFP                  (xtensa_get_config_v1 ()->xchal_have_dfp)
 419
 420 #undef XCHAL_HAVE_DFP_DIV
 421 #define XCHAL_HAVE_DFP_DIV              (xtensa_get_config_v1 ()->xchal_have_dfp_div)
 422
 423 #undef XCHAL_HAVE_DFP_RECIP
 424 #define XCHAL_HAVE_DFP_RECIP            (xtensa_get_config_v1 ()->xchal_have_dfp_recip)
 425
 426 #undef XCHAL_HAVE_DFP_SQRT
 427 #define XCHAL_HAVE_DFP_SQRT             (xtensa_get_config_v1 ()->xchal_have_dfp_sqrt)
 428
 429 #undef XCHAL_HAVE_DFP_RSQRT
 430 #define XCHAL_HAVE_DFP_RSQRT            (xtensa_get_config_v1 ()->xchal_have_dfp_rsqrt)
 431
 432 #undef XCHAL_HAVE_WINDOWED
 433 #define XCHAL_HAVE_WINDOWED             (xtensa_get_config_v1 ()->xchal_have_windowed)
 434
 435 #undef XCHAL_NUM_AREGS
 436 #define XCHAL_NUM_AREGS                 (xtensa_get_config_v1 ()->xchal_num_aregs)
 437
 438 #undef XCHAL_HAVE_WIDE_BRANCHES
 439 #define XCHAL_HAVE_WIDE_BRANCHES        (xtensa_get_config_v1 ()->xchal_have_wide_branches)
 440
 441 #undef XCHAL_HAVE_PREDICTED_BRANCHES
 442 #define XCHAL_HAVE_PREDICTED_BRANCHES   (xtensa_get_config_v1 ()->xchal_have_predicted_branches)
 443
 444
 445 #undef XCHAL_ICACHE_SIZE
 446 #define XCHAL_ICACHE_SIZE               (xtensa_get_config_v1 ()->xchal_icache_size)
 447
 448 #undef XCHAL_DCACHE_SIZE
 449 #define XCHAL_DCACHE_SIZE               (xtensa_get_config_v1 ()->xchal_dcache_size)
 450
 451 #undef XCHAL_ICACHE_LINESIZE
 452 #define XCHAL_ICACHE_LINESIZE           (xtensa_get_config_v1 ()->xchal_icache_linesize)
 453
 454 #undef XCHAL_DCACHE_LINESIZE
 455 #define XCHAL_DCACHE_LINESIZE           (xtensa_get_config_v1 ()->xchal_dcache_linesize)
 456
 457 #undef XCHAL_ICACHE_LINEWIDTH
 458 #define XCHAL_ICACHE_LINEWIDTH          (xtensa_get_config_v1 ()->xchal_icache_linewidth)
 459
 460 #undef XCHAL_DCACHE_LINEWIDTH
 461 #define XCHAL_DCACHE_LINEWIDTH          (xtensa_get_config_v1 ()->xchal_dcache_linewidth)
 462
 463 #undef XCHAL_DCACHE_IS_WRITEBACK
 464 #define XCHAL_DCACHE_IS_WRITEBACK       (xtensa_get_config_v1 ()->xchal_dcache_is_writeback)
 465
 466
 467 #undef XCHAL_HAVE_MMU
 468 #define XCHAL_HAVE_MMU                  (xtensa_get_config_v1 ()->xchal_have_mmu)
 469
 470 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
 471 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE     (xtensa_get_config_v1 ()->xchal_mmu_min_pte_page_size)
 472
 473
 474 #undef XCHAL_HAVE_DEBUG
 475 #define XCHAL_HAVE_DEBUG                (xtensa_get_config_v1 ()->xchal_have_debug)
 476
 477 #undef XCHAL_NUM_IBREAK
 478 #define XCHAL_NUM_IBREAK                (xtensa_get_config_v1 ()->xchal_num_ibreak)
 479
 480 #undef XCHAL_NUM_DBREAK
 481 #define XCHAL_NUM_DBREAK                (xtensa_get_config_v1 ()->xchal_num_dbreak)
 482
 483 #undef XCHAL_DEBUGLEVEL
 484 #define XCHAL_DEBUGLEVEL                (xtensa_get_config_v1 ()->xchal_debuglevel)
 485
 486
 487 #undef XCHAL_MAX_INSTRUCTION_SIZE
 488 #define XCHAL_MAX_INSTRUCTION_SIZE      (xtensa_get_config_v1 ()->xchal_max_instruction_size)
 489
 490 #undef XCHAL_INST_FETCH_WIDTH
 491 #define XCHAL_INST_FETCH_WIDTH          (xtensa_get_config_v1 ()->xchal_inst_fetch_width)
 492
 493
 494 #undef XSHAL_ABI
 495 #undef XTHAL_ABI_WINDOWED
 496 #undef XTHAL_ABI_CALL0
 497 #define XSHAL_ABI                       (xtensa_get_config_v1 ()->xshal_abi)
 498 #define XTHAL_ABI_WINDOWED              (xtensa_get_config_v1 ()->xthal_abi_windowed)
 499 #define XTHAL_ABI_CALL0                 (xtensa_get_config_v1 ()->xthal_abi_call0)
 500
 501
 502 #undef XCHAL_M_STAGE
 503 #define XCHAL_M_STAGE                   (xtensa_get_config_v2 ()->xchal_m_stage)
 504
 505 #undef XTENSA_MARCH_LATEST
 506 #define XTENSA_MARCH_LATEST             (xtensa_get_config_v2 ()->xtensa_march_latest)
 507
 508 #undef XTENSA_MARCH_EARLIEST
 509 #define XTENSA_MARCH_EARLIEST           (xtensa_get_config_v2 ()->xtensa_march_earliest)
 510
 511
 512 #undef XCHAL_HAVE_CLAMPS
 513 #define XCHAL_HAVE_CLAMPS               (xtensa_get_config_v3 ()->xchal_have_clamps)
 514
 515 #undef XCHAL_HAVE_DEPBITS
 516 #define XCHAL_HAVE_DEPBITS              (xtensa_get_config_v3 ()->xchal_have_depbits)
 517
 518 #undef XCHAL_HAVE_EXCLUSIVE
 519 #define XCHAL_HAVE_EXCLUSIVE            (xtensa_get_config_v3 ()->xchal_have_exclusive)
 520
 521 #undef XCHAL_HAVE_XEA3
 522 #define XCHAL_HAVE_XEA3                 (xtensa_get_config_v3 ()->xchal_have_xea3)
 523
 524
 525 #undef XCHAL_DATA_WIDTH
 526 #define XCHAL_DATA_WIDTH                (xtensa_get_config_v4 ()->xchal_data_width)
 527
 528 #undef XCHAL_UNALIGNED_LOAD_EXCEPTION
 529 #define XCHAL_UNALIGNED_LOAD_EXCEPTION  (xtensa_get_config_v4 ()->xchal_unaligned_load_exception)
 530
 531 #undef XCHAL_UNALIGNED_STORE_EXCEPTION
 532 #define XCHAL_UNALIGNED_STORE_EXCEPTION (xtensa_get_config_v4 ()->xchal_unaligned_store_exception)
 533
 534 #undef XCHAL_UNALIGNED_LOAD_HW
 535 #define XCHAL_UNALIGNED_LOAD_HW         (xtensa_get_config_v4 ()->xchal_unaligned_load_hw)
 536
 537 #undef XCHAL_UNALIGNED_STORE_HW
 538 #define XCHAL_UNALIGNED_STORE_HW        (xtensa_get_config_v4 ()->xchal_unaligned_store_hw)
 539
 540 #endif /* XTENSA_CONFIG_DEFINITION */
 541
 542 #ifdef __cplusplus
 543 }
 544 #endif
 545 #endif /* !XTENSA_DYNCONFIG_H */