1 ;; Pipeline description for Motorola PowerPC 8540 processor.
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 ;; MA 02111-1307, USA.
21 (define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
22 (define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
24 ;; We don't simulate general issue queue (GIC). If we have SU insn
25 ;; and then SU1 insn, they can not be issued on the same cycle
26 ;; (although SU1 insn and then SU insn can be issued) because the SU
27 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
28 ;; multipass insn scheduling will find the situation and issue the SU1
29 ;; insn and then the SU insn.
30 (define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
32 ;; We could describe completion buffers slots in combination with the
33 ;; retirement units and the order of completion but the result
34 ;; automaton would behave in the same way because we can not describe
35 ;; real latency time with taking in order completion into account.
36 ;; Actually we could define the real latency time by querying reserved
37 ;; automaton units but the current scheduler uses latency time before
38 ;; issuing insns and making any reservations.
40 ;; So our description is aimed to achieve a insn schedule in which the
41 ;; insns would not wait in the completion buffer.
42 (define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
45 (define_cpu_unit "ppc8540_bu" "ppc8540_most")
48 (define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
50 ;; We could describe here MU subunits for float multiply, float add
51 ;; etc. But the result automaton would behave the same way as the
52 ;; described one pipeline below because MU can start only one insn
53 ;; per cycle. Actually we could simplify the automaton more not
54 ;; describing stages 1-3, the result automata would be the same.
55 (define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
56 (define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
58 ;; The following unit is used to describe non-pipelined division.
59 (define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
61 ;; Here we simplified LSU unit description not describing the stages.
62 (define_cpu_unit "ppc8540_lsu" "ppc8540_most")
64 ;; The following units are used to make automata deterministic
65 (define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
66 (define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
67 (define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
68 (define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
70 ;; The following sets to make automata deterministic when option ndfa is used.
71 (presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
72 (presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
73 (presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
74 (presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
76 ;; Some useful abbreviations.
77 (define_reservation "ppc8540_decode"
78 "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
79 (define_reservation "ppc8540_issue"
80 "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
81 (define_reservation "ppc8540_retire"
82 "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
83 (define_reservation "ppc8540_su_stage0"
84 "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
87 (define_insn_reservation "ppc8540_su" 1
88 (and (eq_attr "type" "integer,insert_word,cmp,compare,delayed_compare,fast_compare")
89 (eq_attr "cpu" "ppc8540"))
90 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
92 ;; Branch. Actually this latency time is not used by the scheduler.
93 (define_insn_reservation "ppc8540_branch" 1
94 (and (eq_attr "type" "jmpreg,branch")
95 (eq_attr "cpu" "ppc8540"))
96 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
99 (define_insn_reservation "ppc8540_multiply" 4
100 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
101 (eq_attr "cpu" "ppc8540"))
102 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
103 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
105 ;; Divide. We use the average latency time here. We omit reserving a
106 ;; retire unit because of the result automata will be huge. We ignore
107 ;; reservation of miu_stage3 here because we use the average latency
109 (define_insn_reservation "ppc8540_divide" 14
110 (and (eq_attr "type" "idiv")
111 (eq_attr "cpu" "ppc8540"))
112 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
116 (define_insn_reservation "ppc8540_cr_logical" 1
117 (and (eq_attr "type" "cr_logical,delayed_cr")
118 (eq_attr "cpu" "ppc8540"))
119 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
122 (define_insn_reservation "ppc8540_mfcr" 1
123 (and (eq_attr "type" "mfcr")
124 (eq_attr "cpu" "ppc8540"))
125 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
128 (define_insn_reservation "ppc8540_mtcrf" 1
129 (and (eq_attr "type" "mtcr")
130 (eq_attr "cpu" "ppc8540"))
131 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
134 (define_insn_reservation "ppc8540_mtjmpr" 1
135 (and (eq_attr "type" "mtjmpr,mfjmpr")
136 (eq_attr "cpu" "ppc8540"))
137 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
140 (define_insn_reservation "ppc8540_load" 3
141 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
142 (eq_attr "cpu" "ppc8540"))
143 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
146 (define_insn_reservation "ppc8540_store" 3
147 (and (eq_attr "type" "store,store_ux,store_u")
148 (eq_attr "cpu" "ppc8540"))
149 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
152 (define_insn_reservation "ppc8540_simple_float" 1
153 (and (eq_attr "type" "fpsimple")
154 (eq_attr "cpu" "ppc8540"))
155 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
158 (define_insn_reservation "ppc8540_float" 4
159 (and (eq_attr "type" "fp")
160 (eq_attr "cpu" "ppc8540"))
161 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
162 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
164 ;; float divides. We omit reserving a retire unit and miu_stage3
165 ;; because of the result automata will be huge.
166 (define_insn_reservation "ppc8540_float_vector_divide" 29
167 (and (eq_attr "type" "vecfdiv")
168 (eq_attr "cpu" "ppc8540"))
169 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
173 (define_insn_reservation "ppc8540_brinc" 1
174 (and (eq_attr "type" "brinc")
175 (eq_attr "cpu" "ppc8540"))
176 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
179 (define_insn_reservation "ppc8540_simple_vector" 1
180 (and (eq_attr "type" "vecsimple")
181 (eq_attr "cpu" "ppc8540"))
182 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
184 ;; Simple vector compare
185 (define_insn_reservation "ppc8540_simple_vector_compare" 1
186 (and (eq_attr "type" "veccmpsimple")
187 (eq_attr "cpu" "ppc8540"))
188 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
191 (define_insn_reservation "ppc8540_vector_compare" 1
192 (and (eq_attr "type" "veccmp")
193 (eq_attr "cpu" "ppc8540"))
194 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
196 ;; evsplatfi evsplati
197 (define_insn_reservation "ppc8540_vector_perm" 1
198 (and (eq_attr "type" "vecperm")
199 (eq_attr "cpu" "ppc8540"))
200 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
203 (define_insn_reservation "ppc8540_float_vector" 4
204 (and (eq_attr "type" "vecfloat")
205 (eq_attr "cpu" "ppc8540"))
206 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
207 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
209 ;; Vector divides: Use the average. We omit reserving a retire unit
210 ;; because of the result automata will be huge. We ignore reservation
211 ;; of miu_stage3 here because we use the average latency time.
212 (define_insn_reservation "ppc8540_vector_divide" 14
213 (and (eq_attr "type" "vecdiv")
214 (eq_attr "cpu" "ppc8540"))
215 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
219 (define_insn_reservation "ppc8540_complex_vector" 4
220 (and (eq_attr "type" "veccomplex")
221 (eq_attr "cpu" "ppc8540"))
222 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
223 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
226 (define_insn_reservation "ppc8540_vector_load" 3
227 (and (eq_attr "type" "vecload")
228 (eq_attr "cpu" "ppc8540"))
229 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
232 (define_insn_reservation "ppc8540_vector_store" 3
233 (and (eq_attr "type" "vecstore")
234 (eq_attr "cpu" "ppc8540"))
235 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")