1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
96 #include "dominance.h"
99 #include "cfgcleanup.h"
100 #include "basic-block.h"
101 #include "insn-config.h"
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
104 #include "insn-attr.h"
106 #include "diagnostic-core.h"
108 #include "insn-codes.h"
110 #include "rtlhooks-def.h"
112 #include "tree-pass.h"
114 #include "valtrack.h"
115 #include "hash-map.h"
117 #include "plugin-api.h"
121 #include "statistics.h"
123 #include "rtl-iter.h"
125 /* Number of attempts to combine instructions in this function. */
127 static int combine_attempts
;
129 /* Number of attempts that got as far as substitution in this function. */
131 static int combine_merges
;
133 /* Number of instructions combined with added SETs in this function. */
135 static int combine_extras
;
137 /* Number of instructions combined in this function. */
139 static int combine_successes
;
141 /* Totals over entire compilation. */
143 static int total_attempts
, total_merges
, total_extras
, total_successes
;
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
152 static rtx_insn
*i2mod
;
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
156 static rtx i2mod_old_rhs
;
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
160 static rtx i2mod_new_rhs
;
162 typedef struct reg_stat_struct
{
163 /* Record last point of death of (hard or pseudo) register n. */
164 rtx_insn
*last_death
;
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
219 int last_set_table_tick
;
221 /* Record the value of label_tick when the value for register n is placed in
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
231 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
232 char last_set_sign_bit_copies
;
233 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
239 char last_set_invalid
;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
251 If an entry is zero, it means that we don't know anything special. */
253 unsigned char sign_bit_copies
;
255 unsigned HOST_WIDE_INT nonzero_bits
;
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
261 int truncation_label
;
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
268 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
272 static vec
<reg_stat_type
> reg_stat
;
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
277 static int mem_last_set
;
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
282 static int last_call_luid
;
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
290 static rtx_insn
*subst_insn
;
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
299 static int subst_low_luid
;
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
304 static HARD_REG_SET newpat_used_regs
;
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
310 static rtx_insn
*added_links_insn
;
312 /* Basic block in which we are performing combines. */
313 static basic_block this_basic_block
;
314 static bool optimize_this_for_speed_p
;
317 /* Length of the currently allocated uid_insn_cost array. */
319 static int max_uid_known
;
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
324 static int *uid_insn_cost
;
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
332 struct insn_link
*next
;
335 static struct insn_link
**uid_log_links
;
337 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
338 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
340 #define FOR_EACH_LOG_LINK(L, INSN) \
341 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
343 /* Links for LOG_LINKS are allocated from this obstack. */
345 static struct obstack insn_link_obstack
;
347 /* Allocate a link. */
349 static inline struct insn_link
*
350 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
353 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
354 sizeof (struct insn_link
));
361 /* Incremented for each basic block. */
363 static int label_tick
;
365 /* Reset to label_tick for each extended basic block in scanning order. */
367 static int label_tick_ebb_start
;
369 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
370 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
372 static machine_mode nonzero_bits_mode
;
374 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
375 be safely used. It is zero while computing them and after combine has
376 completed. This former test prevents propagating values based on
377 previously set values, which can be incorrect if a variable is modified
380 static int nonzero_sign_valid
;
383 /* Record one modification to rtl structure
384 to be undone by storing old_contents into *where. */
386 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
392 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
393 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
396 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
397 num_undo says how many are currently recorded.
399 other_insn is nonzero if we have modified some other insn in the process
400 of working on subst_insn. It must be verified too. */
406 rtx_insn
*other_insn
;
409 static struct undobuf undobuf
;
411 /* Number of times the pseudo being substituted for
412 was found and replaced. */
414 static int n_occurrences
;
416 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
418 unsigned HOST_WIDE_INT
,
419 unsigned HOST_WIDE_INT
*);
420 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
422 unsigned int, unsigned int *);
423 static void do_SUBST (rtx
*, rtx
);
424 static void do_SUBST_INT (int *, int);
425 static void init_reg_last (void);
426 static void setup_incoming_promotions (rtx_insn
*);
427 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
428 static int cant_combine_insn_p (rtx_insn
*);
429 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
430 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
431 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
432 static int contains_muldiv (rtx
);
433 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
435 static void undo_all (void);
436 static void undo_commit (void);
437 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
438 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
439 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
440 static rtx
simplify_if_then_else (rtx
);
441 static rtx
simplify_set (rtx
);
442 static rtx
simplify_logical (rtx
);
443 static rtx
expand_compound_operation (rtx
);
444 static const_rtx
expand_field_assignment (const_rtx
);
445 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
446 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
447 static rtx
extract_left_shift (rtx
, int);
448 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
449 unsigned HOST_WIDE_INT
*);
450 static rtx
canon_reg_for_combine (rtx
, rtx
);
451 static rtx
force_to_mode (rtx
, machine_mode
,
452 unsigned HOST_WIDE_INT
, int);
453 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
454 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
455 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
456 static rtx
make_field_assignment (rtx
);
457 static rtx
apply_distributive_law (rtx
);
458 static rtx
distribute_and_simplify_rtx (rtx
, int);
459 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
460 unsigned HOST_WIDE_INT
);
461 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
462 unsigned HOST_WIDE_INT
);
463 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
464 HOST_WIDE_INT
, machine_mode
, int *);
465 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
466 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
468 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
469 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
470 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
472 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
473 static void update_table_tick (rtx
);
474 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
475 static void check_promoted_subreg (rtx_insn
*, rtx
);
476 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
477 static void record_dead_and_set_regs (rtx_insn
*);
478 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
479 static rtx
get_last_value (const_rtx
);
480 static int use_crosses_set_p (const_rtx
, int);
481 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
482 static int reg_dead_at_p (rtx
, rtx_insn
*);
483 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
484 static int reg_bitfield_target_p (rtx
, rtx
);
485 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
486 static void distribute_links (struct insn_link
*);
487 static void mark_used_regs_combine (rtx
);
488 static void record_promoted_value (rtx_insn
*, rtx
);
489 static bool unmentioned_reg_p (rtx
, rtx
);
490 static void record_truncated_values (rtx
*, void *);
491 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
492 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
495 /* It is not safe to use ordinary gen_lowpart in combine.
496 See comments in gen_lowpart_for_combine. */
497 #undef RTL_HOOKS_GEN_LOWPART
498 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
500 /* Our implementation of gen_lowpart never emits a new pseudo. */
501 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
502 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
504 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
505 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
507 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
508 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
510 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
511 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
513 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
516 /* Convenience wrapper for the canonicalize_comparison target hook.
517 Target hooks cannot use enum rtx_code. */
519 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
520 bool op0_preserve_value
)
522 int code_int
= (int)*code
;
523 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
524 *code
= (enum rtx_code
)code_int
;
527 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
528 PATTERN can not be split. Otherwise, it returns an insn sequence.
529 This is a wrapper around split_insns which ensures that the
530 reg_stat vector is made larger if the splitter creates a new
534 combine_split_insns (rtx pattern
, rtx insn
)
539 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
540 nregs
= max_reg_num ();
541 if (nregs
> reg_stat
.length ())
542 reg_stat
.safe_grow_cleared (nregs
);
546 /* This is used by find_single_use to locate an rtx in LOC that
547 contains exactly one use of DEST, which is typically either a REG
548 or CC0. It returns a pointer to the innermost rtx expression
549 containing DEST. Appearances of DEST that are being used to
550 totally replace it are not counted. */
553 find_single_use_1 (rtx dest
, rtx
*loc
)
556 enum rtx_code code
= GET_CODE (x
);
572 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
573 of a REG that occupies all of the REG, the insn uses DEST if
574 it is mentioned in the destination or the source. Otherwise, we
575 need just check the source. */
576 if (GET_CODE (SET_DEST (x
)) != CC0
577 && GET_CODE (SET_DEST (x
)) != PC
578 && !REG_P (SET_DEST (x
))
579 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
580 && REG_P (SUBREG_REG (SET_DEST (x
)))
581 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
582 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
583 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
584 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
587 return find_single_use_1 (dest
, &SET_SRC (x
));
591 return find_single_use_1 (dest
, &XEXP (x
, 0));
597 /* If it wasn't one of the common cases above, check each expression and
598 vector of this code. Look for a unique usage of DEST. */
600 fmt
= GET_RTX_FORMAT (code
);
601 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
605 if (dest
== XEXP (x
, i
)
606 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
607 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
610 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
613 result
= this_result
;
614 else if (this_result
)
615 /* Duplicate usage. */
618 else if (fmt
[i
] == 'E')
622 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
624 if (XVECEXP (x
, i
, j
) == dest
626 && REG_P (XVECEXP (x
, i
, j
))
627 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
630 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
633 result
= this_result
;
634 else if (this_result
)
644 /* See if DEST, produced in INSN, is used only a single time in the
645 sequel. If so, return a pointer to the innermost rtx expression in which
648 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
650 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
651 care about REG_DEAD notes or LOG_LINKS.
653 Otherwise, we find the single use by finding an insn that has a
654 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
655 only referenced once in that insn, we know that it must be the first
656 and last insn referencing DEST. */
659 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
664 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
684 bb
= BLOCK_FOR_INSN (insn
);
685 for (next
= NEXT_INSN (insn
);
686 next
&& BLOCK_FOR_INSN (next
) == bb
;
687 next
= NEXT_INSN (next
))
688 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
690 FOR_EACH_LOG_LINK (link
, next
)
691 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
696 result
= find_single_use_1 (dest
, &PATTERN (next
));
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
713 do_SUBST (rtx
*into
, rtx newval
)
718 if (oldval
== newval
)
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
726 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
727 && CONST_INT_P (newval
))
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
731 gcc_assert (INTVAL (newval
)
732 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
740 gcc_assert (!(GET_CODE (oldval
) == SUBREG
741 && CONST_INT_P (SUBREG_REG (oldval
))));
742 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
743 && CONST_INT_P (XEXP (oldval
, 0))));
747 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
749 buf
= XNEW (struct undo
);
751 buf
->kind
= UNDO_RTX
;
753 buf
->old_contents
.r
= oldval
;
756 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
766 do_SUBST_INT (int *into
, int newval
)
771 if (oldval
== newval
)
775 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
777 buf
= XNEW (struct undo
);
779 buf
->kind
= UNDO_INT
;
781 buf
->old_contents
.i
= oldval
;
784 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
795 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
798 machine_mode oldval
= GET_MODE (*into
);
800 if (oldval
== newval
)
804 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
806 buf
= XNEW (struct undo
);
808 buf
->kind
= UNDO_MODE
;
810 buf
->old_contents
.m
= oldval
;
811 adjust_reg_mode (*into
, newval
);
813 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
822 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
825 struct insn_link
* oldval
= *into
;
827 if (oldval
== newval
)
831 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
833 buf
= XNEW (struct undo
);
835 buf
->kind
= UNDO_LINKS
;
837 buf
->old_contents
.l
= oldval
;
840 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
855 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
856 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
858 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
859 int new_i2_cost
, new_i3_cost
;
860 int old_cost
, new_cost
;
862 /* Lookup the original insn_rtx_costs. */
863 i2_cost
= INSN_COST (i2
);
864 i3_cost
= INSN_COST (i3
);
868 i1_cost
= INSN_COST (i1
);
871 i0_cost
= INSN_COST (i0
);
872 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
873 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
877 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
878 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
884 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
885 i1_cost
= i0_cost
= 0;
888 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
890 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
894 /* Calculate the replacement insn_rtx_costs. */
895 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
898 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
899 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
900 ? new_i2_cost
+ new_i3_cost
: 0;
904 new_cost
= new_i3_cost
;
908 if (undobuf
.other_insn
)
910 int old_other_cost
, new_other_cost
;
912 old_other_cost
= INSN_COST (undobuf
.other_insn
);
913 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
914 if (old_other_cost
> 0 && new_other_cost
> 0)
916 old_cost
+= old_other_cost
;
917 new_cost
+= new_other_cost
;
923 /* Disallow this combination if both new_cost and old_cost are greater than
924 zero, and new_cost is greater than old cost. */
925 int reject
= old_cost
> 0 && new_cost
> old_cost
;
929 fprintf (dump_file
, "%s combination of insns ",
930 reject
? "rejecting" : "allowing");
932 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
933 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
934 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
935 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
937 fprintf (dump_file
, "original costs ");
939 fprintf (dump_file
, "%d + ", i0_cost
);
940 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
941 fprintf (dump_file
, "%d + ", i1_cost
);
942 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
945 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
946 new_i2_cost
, new_i3_cost
, new_cost
);
948 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
954 /* Update the uid_insn_cost array with the replacement costs. */
955 INSN_COST (i2
) = new_i2_cost
;
956 INSN_COST (i3
) = new_i3_cost
;
968 /* Delete any insns that copy a register to itself. */
971 delete_noop_moves (void)
973 rtx_insn
*insn
, *next
;
976 FOR_EACH_BB_FN (bb
, cfun
)
978 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
980 next
= NEXT_INSN (insn
);
981 if (INSN_P (insn
) && noop_move_p (insn
))
984 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
986 delete_insn_and_edges (insn
);
993 /* Return false if we do not want to (or cannot) combine DEF. */
995 can_combine_def_p (df_ref def
)
997 /* Do not consider if it is pre/post modification in MEM. */
998 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1001 unsigned int regno
= DF_REF_REGNO (def
);
1003 /* Do not combine frame pointer adjustments. */
1004 if ((regno
== FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1007 || (regno
== HARD_FRAME_POINTER_REGNUM
1008 && (!reload_completed
|| frame_pointer_needed
))
1010 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1011 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1019 /* Return false if we do not want to (or cannot) combine USE. */
1021 can_combine_use_p (df_ref use
)
1023 /* Do not consider the usage of the stack pointer by function call. */
1024 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1030 /* Fill in log links field for all insns. */
1033 create_log_links (void)
1036 rtx_insn
**next_use
;
1040 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1042 /* Pass through each block from the end, recording the uses of each
1043 register and establishing log links when def is encountered.
1044 Note that we do not clear next_use array in order to save time,
1045 so we have to test whether the use is in the same basic block as def.
1047 There are a few cases below when we do not consider the definition or
1048 usage -- these are taken from original flow.c did. Don't ask me why it is
1049 done this way; I don't know and if it works, I don't want to know. */
1051 FOR_EACH_BB_FN (bb
, cfun
)
1053 FOR_BB_INSNS_REVERSE (bb
, insn
)
1055 if (!NONDEBUG_INSN_P (insn
))
1058 /* Log links are created only once. */
1059 gcc_assert (!LOG_LINKS (insn
));
1061 FOR_EACH_INSN_DEF (def
, insn
)
1063 unsigned int regno
= DF_REF_REGNO (def
);
1066 if (!next_use
[regno
])
1069 if (!can_combine_def_p (def
))
1072 use_insn
= next_use
[regno
];
1073 next_use
[regno
] = NULL
;
1075 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1080 We don't build a LOG_LINK for hard registers contained
1081 in ASM_OPERANDs. If these registers get replaced,
1082 we might wind up changing the semantics of the insn,
1083 even if reload can make what appear to be valid
1084 assignments later. */
1085 if (regno
< FIRST_PSEUDO_REGISTER
1086 && asm_noperands (PATTERN (use_insn
)) >= 0)
1089 /* Don't add duplicate links between instructions. */
1090 struct insn_link
*links
;
1091 FOR_EACH_LOG_LINK (links
, use_insn
)
1092 if (insn
== links
->insn
&& regno
== links
->regno
)
1096 LOG_LINKS (use_insn
)
1097 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1100 FOR_EACH_INSN_USE (use
, insn
)
1101 if (can_combine_use_p (use
))
1102 next_use
[DF_REF_REGNO (use
)] = insn
;
1109 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1110 true if we found a LOG_LINK that proves that A feeds B. This only works
1111 if there are no instructions between A and B which could have a link
1112 depending on A, since in that case we would not record a link for B.
1113 We also check the implicit dependency created by a cc0 setter/user
1117 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1119 struct insn_link
*links
;
1120 FOR_EACH_LOG_LINK (links
, b
)
1121 if (links
->insn
== a
)
1130 /* Main entry point for combiner. F is the first insn of the function.
1131 NREGS is the first unused pseudo-reg number.
1133 Return nonzero if the combiner has turned an indirect jump
1134 instruction into a direct jump. */
1136 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1138 rtx_insn
*insn
, *next
;
1142 struct insn_link
*links
, *nextlinks
;
1144 basic_block last_bb
;
1146 int new_direct_jump_p
= 0;
1148 for (first
= f
; first
&& !INSN_P (first
); )
1149 first
= NEXT_INSN (first
);
1153 combine_attempts
= 0;
1156 combine_successes
= 0;
1158 rtl_hooks
= combine_rtl_hooks
;
1160 reg_stat
.safe_grow_cleared (nregs
);
1162 init_recog_no_volatile ();
1164 /* Allocate array for insn info. */
1165 max_uid_known
= get_max_uid ();
1166 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1167 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1168 gcc_obstack_init (&insn_link_obstack
);
1170 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1172 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1173 problems when, for example, we have j <<= 1 in a loop. */
1175 nonzero_sign_valid
= 0;
1176 label_tick
= label_tick_ebb_start
= 1;
1178 /* Scan all SETs and see if we can deduce anything about what
1179 bits are known to be zero for some registers and how many copies
1180 of the sign bit are known to exist for those registers.
1182 Also set any known values so that we can use it while searching
1183 for what bits are known to be set. */
1185 setup_incoming_promotions (first
);
1186 /* Allow the entry block and the first block to fall into the same EBB.
1187 Conceptually the incoming promotions are assigned to the entry block. */
1188 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1190 create_log_links ();
1191 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1193 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1198 if (!single_pred_p (this_basic_block
)
1199 || single_pred (this_basic_block
) != last_bb
)
1200 label_tick_ebb_start
= label_tick
;
1201 last_bb
= this_basic_block
;
1203 FOR_BB_INSNS (this_basic_block
, insn
)
1204 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1210 subst_low_luid
= DF_INSN_LUID (insn
);
1213 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1215 record_dead_and_set_regs (insn
);
1218 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1219 if (REG_NOTE_KIND (links
) == REG_INC
)
1220 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1224 /* Record the current insn_rtx_cost of this instruction. */
1225 if (NONJUMP_INSN_P (insn
))
1226 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1227 optimize_this_for_speed_p
);
1229 fprintf (dump_file
, "insn_cost %d: %d\n",
1230 INSN_UID (insn
), INSN_COST (insn
));
1234 nonzero_sign_valid
= 1;
1236 /* Now scan all the insns in forward order. */
1237 label_tick
= label_tick_ebb_start
= 1;
1239 setup_incoming_promotions (first
);
1240 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1241 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1243 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1245 rtx_insn
*last_combined_insn
= NULL
;
1246 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1251 if (!single_pred_p (this_basic_block
)
1252 || single_pred (this_basic_block
) != last_bb
)
1253 label_tick_ebb_start
= label_tick
;
1254 last_bb
= this_basic_block
;
1256 rtl_profile_for_bb (this_basic_block
);
1257 for (insn
= BB_HEAD (this_basic_block
);
1258 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1259 insn
= next
? next
: NEXT_INSN (insn
))
1262 if (!NONDEBUG_INSN_P (insn
))
1265 while (last_combined_insn
1266 && last_combined_insn
->deleted ())
1267 last_combined_insn
= PREV_INSN (last_combined_insn
);
1268 if (last_combined_insn
== NULL_RTX
1269 || BARRIER_P (last_combined_insn
)
1270 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1271 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1272 last_combined_insn
= insn
;
1274 /* See if we know about function return values before this
1275 insn based upon SUBREG flags. */
1276 check_promoted_subreg (insn
, PATTERN (insn
));
1278 /* See if we can find hardregs and subreg of pseudos in
1279 narrower modes. This could help turning TRUNCATEs
1281 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1283 /* Try this insn with each insn it links back to. */
1285 FOR_EACH_LOG_LINK (links
, insn
)
1286 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1287 NULL
, &new_direct_jump_p
,
1288 last_combined_insn
)) != 0)
1290 statistics_counter_event (cfun
, "two-insn combine", 1);
1294 /* Try each sequence of three linked insns ending with this one. */
1296 if (max_combine
>= 3)
1297 FOR_EACH_LOG_LINK (links
, insn
)
1299 rtx_insn
*link
= links
->insn
;
1301 /* If the linked insn has been replaced by a note, then there
1302 is no point in pursuing this chain any further. */
1306 FOR_EACH_LOG_LINK (nextlinks
, link
)
1307 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1308 NULL
, &new_direct_jump_p
,
1309 last_combined_insn
)) != 0)
1311 statistics_counter_event (cfun
, "three-insn combine", 1);
1317 /* Try to combine a jump insn that uses CC0
1318 with a preceding insn that sets CC0, and maybe with its
1319 logical predecessor as well.
1320 This is how we make decrement-and-branch insns.
1321 We need this special code because data flow connections
1322 via CC0 do not get entered in LOG_LINKS. */
1325 && (prev
= prev_nonnote_insn (insn
)) != 0
1326 && NONJUMP_INSN_P (prev
)
1327 && sets_cc0_p (PATTERN (prev
)))
1329 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1331 last_combined_insn
)) != 0)
1334 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1335 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1336 NULL
, &new_direct_jump_p
,
1337 last_combined_insn
)) != 0)
1341 /* Do the same for an insn that explicitly references CC0. */
1342 if (NONJUMP_INSN_P (insn
)
1343 && (prev
= prev_nonnote_insn (insn
)) != 0
1344 && NONJUMP_INSN_P (prev
)
1345 && sets_cc0_p (PATTERN (prev
))
1346 && GET_CODE (PATTERN (insn
)) == SET
1347 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1349 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1351 last_combined_insn
)) != 0)
1354 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1355 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1356 NULL
, &new_direct_jump_p
,
1357 last_combined_insn
)) != 0)
1361 /* Finally, see if any of the insns that this insn links to
1362 explicitly references CC0. If so, try this insn, that insn,
1363 and its predecessor if it sets CC0. */
1364 FOR_EACH_LOG_LINK (links
, insn
)
1365 if (NONJUMP_INSN_P (links
->insn
)
1366 && GET_CODE (PATTERN (links
->insn
)) == SET
1367 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1368 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1369 && NONJUMP_INSN_P (prev
)
1370 && sets_cc0_p (PATTERN (prev
))
1371 && (next
= try_combine (insn
, links
->insn
,
1372 prev
, NULL
, &new_direct_jump_p
,
1373 last_combined_insn
)) != 0)
1377 /* Try combining an insn with two different insns whose results it
1379 if (max_combine
>= 3)
1380 FOR_EACH_LOG_LINK (links
, insn
)
1381 for (nextlinks
= links
->next
; nextlinks
;
1382 nextlinks
= nextlinks
->next
)
1383 if ((next
= try_combine (insn
, links
->insn
,
1384 nextlinks
->insn
, NULL
,
1386 last_combined_insn
)) != 0)
1389 statistics_counter_event (cfun
, "three-insn combine", 1);
1393 /* Try four-instruction combinations. */
1394 if (max_combine
>= 4)
1395 FOR_EACH_LOG_LINK (links
, insn
)
1397 struct insn_link
*next1
;
1398 rtx_insn
*link
= links
->insn
;
1400 /* If the linked insn has been replaced by a note, then there
1401 is no point in pursuing this chain any further. */
1405 FOR_EACH_LOG_LINK (next1
, link
)
1407 rtx_insn
*link1
= next1
->insn
;
1410 /* I0 -> I1 -> I2 -> I3. */
1411 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1420 /* I0, I1 -> I2, I2 -> I3. */
1421 for (nextlinks
= next1
->next
; nextlinks
;
1422 nextlinks
= nextlinks
->next
)
1423 if ((next
= try_combine (insn
, link
, link1
,
1426 last_combined_insn
)) != 0)
1428 statistics_counter_event (cfun
, "four-insn combine", 1);
1433 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1435 rtx_insn
*link1
= next1
->insn
;
1438 /* I0 -> I2; I1, I2 -> I3. */
1439 FOR_EACH_LOG_LINK (nextlinks
, link
)
1440 if ((next
= try_combine (insn
, link
, link1
,
1443 last_combined_insn
)) != 0)
1445 statistics_counter_event (cfun
, "four-insn combine", 1);
1448 /* I0 -> I1; I1, I2 -> I3. */
1449 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1450 if ((next
= try_combine (insn
, link
, link1
,
1453 last_combined_insn
)) != 0)
1455 statistics_counter_event (cfun
, "four-insn combine", 1);
1461 /* Try this insn with each REG_EQUAL note it links back to. */
1462 FOR_EACH_LOG_LINK (links
, insn
)
1465 rtx_insn
*temp
= links
->insn
;
1466 if ((set
= single_set (temp
)) != 0
1467 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1468 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1469 /* Avoid using a register that may already been marked
1470 dead by an earlier instruction. */
1471 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1472 && (GET_MODE (note
) == VOIDmode
1473 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1474 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1476 /* Temporarily replace the set's source with the
1477 contents of the REG_EQUAL note. The insn will
1478 be deleted or recognized by try_combine. */
1479 rtx orig
= SET_SRC (set
);
1480 SET_SRC (set
) = note
;
1482 i2mod_old_rhs
= copy_rtx (orig
);
1483 i2mod_new_rhs
= copy_rtx (note
);
1484 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1486 last_combined_insn
);
1490 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1493 SET_SRC (set
) = orig
;
1498 record_dead_and_set_regs (insn
);
1505 default_rtl_profile ();
1507 new_direct_jump_p
|= purge_all_dead_edges ();
1508 delete_noop_moves ();
1511 obstack_free (&insn_link_obstack
, NULL
);
1512 free (uid_log_links
);
1513 free (uid_insn_cost
);
1514 reg_stat
.release ();
1517 struct undo
*undo
, *next
;
1518 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1526 total_attempts
+= combine_attempts
;
1527 total_merges
+= combine_merges
;
1528 total_extras
+= combine_extras
;
1529 total_successes
+= combine_successes
;
1531 nonzero_sign_valid
= 0;
1532 rtl_hooks
= general_rtl_hooks
;
1534 /* Make recognizer allow volatile MEMs again. */
1537 return new_direct_jump_p
;
1540 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1543 init_reg_last (void)
1548 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1549 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1552 /* Set up any promoted values for incoming argument registers. */
1555 setup_incoming_promotions (rtx_insn
*first
)
1558 bool strictly_local
= false;
1560 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1561 arg
= DECL_CHAIN (arg
))
1563 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1565 machine_mode mode1
, mode2
, mode3
, mode4
;
1567 /* Only continue if the incoming argument is in a register. */
1571 /* Determine, if possible, whether all call sites of the current
1572 function lie within the current compilation unit. (This does
1573 take into account the exporting of a function via taking its
1574 address, and so forth.) */
1575 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1577 /* The mode and signedness of the argument before any promotions happen
1578 (equal to the mode of the pseudo holding it at that stage). */
1579 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1580 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1582 /* The mode and signedness of the argument after any source language and
1583 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1584 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1585 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1587 /* The mode and signedness of the argument as it is actually passed,
1588 see assign_parm_setup_reg in function.c. */
1589 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1590 TREE_TYPE (cfun
->decl
), 0);
1592 /* The mode of the register in which the argument is being passed. */
1593 mode4
= GET_MODE (reg
);
1595 /* Eliminate sign extensions in the callee when:
1596 (a) A mode promotion has occurred; */
1599 /* (b) The mode of the register is the same as the mode of
1600 the argument as it is passed; */
1603 /* (c) There's no language level extension; */
1606 /* (c.1) All callers are from the current compilation unit. If that's
1607 the case we don't have to rely on an ABI, we only have to know
1608 what we're generating right now, and we know that we will do the
1609 mode1 to mode2 promotion with the given sign. */
1610 else if (!strictly_local
)
1612 /* (c.2) The combination of the two promotions is useful. This is
1613 true when the signs match, or if the first promotion is unsigned.
1614 In the later case, (sign_extend (zero_extend x)) is the same as
1615 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1621 /* Record that the value was promoted from mode1 to mode3,
1622 so that any sign extension at the head of the current
1623 function may be eliminated. */
1624 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1625 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1626 record_value_for_reg (reg
, first
, x
);
1630 /* Called via note_stores. If X is a pseudo that is narrower than
1631 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1633 If we are setting only a portion of X and we can't figure out what
1634 portion, assume all bits will be used since we don't know what will
1637 Similarly, set how many bits of X are known to be copies of the sign bit
1638 at all locations in the function. This is the smallest number implied
1642 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1644 rtx_insn
*insn
= (rtx_insn
*) data
;
1648 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1649 /* If this register is undefined at the start of the file, we can't
1650 say what its contents were. */
1651 && ! REGNO_REG_SET_P
1652 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1653 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1655 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1657 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1659 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1660 rsp
->sign_bit_copies
= 1;
1664 /* If this register is being initialized using itself, and the
1665 register is uninitialized in this basic block, and there are
1666 no LOG_LINKS which set the register, then part of the
1667 register is uninitialized. In that case we can't assume
1668 anything about the number of nonzero bits.
1670 ??? We could do better if we checked this in
1671 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1672 could avoid making assumptions about the insn which initially
1673 sets the register, while still using the information in other
1674 insns. We would have to be careful to check every insn
1675 involved in the combination. */
1678 && reg_referenced_p (x
, PATTERN (insn
))
1679 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1682 struct insn_link
*link
;
1684 FOR_EACH_LOG_LINK (link
, insn
)
1685 if (dead_or_set_p (link
->insn
, x
))
1689 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1690 rsp
->sign_bit_copies
= 1;
1695 /* If this is a complex assignment, see if we can convert it into a
1696 simple assignment. */
1697 set
= expand_field_assignment (set
);
1699 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1700 set what we know about X. */
1702 if (SET_DEST (set
) == x
1703 || (paradoxical_subreg_p (SET_DEST (set
))
1704 && SUBREG_REG (SET_DEST (set
)) == x
))
1706 rtx src
= SET_SRC (set
);
1708 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1709 /* If X is narrower than a word and SRC is a non-negative
1710 constant that would appear negative in the mode of X,
1711 sign-extend it for use in reg_stat[].nonzero_bits because some
1712 machines (maybe most) will actually do the sign-extension
1713 and this is the conservative approach.
1715 ??? For 2.5, try to tighten up the MD files in this regard
1716 instead of this kludge. */
1718 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1719 && CONST_INT_P (src
)
1721 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1722 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1725 /* Don't call nonzero_bits if it cannot change anything. */
1726 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1727 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1728 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1729 if (rsp
->sign_bit_copies
== 0
1730 || rsp
->sign_bit_copies
> num
)
1731 rsp
->sign_bit_copies
= num
;
1735 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1736 rsp
->sign_bit_copies
= 1;
1741 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1742 optionally insns that were previously combined into I3 or that will be
1743 combined into the merger of INSN and I3. The order is PRED, PRED2,
1744 INSN, SUCC, SUCC2, I3.
1746 Return 0 if the combination is not allowed for any reason.
1748 If the combination is allowed, *PDEST will be set to the single
1749 destination of INSN and *PSRC to the single source, and this function
1753 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1754 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1755 rtx
*pdest
, rtx
*psrc
)
1764 bool all_adjacent
= true;
1765 int (*is_volatile_p
) (const_rtx
);
1771 if (next_active_insn (succ2
) != i3
)
1772 all_adjacent
= false;
1773 if (next_active_insn (succ
) != succ2
)
1774 all_adjacent
= false;
1776 else if (next_active_insn (succ
) != i3
)
1777 all_adjacent
= false;
1778 if (next_active_insn (insn
) != succ
)
1779 all_adjacent
= false;
1781 else if (next_active_insn (insn
) != i3
)
1782 all_adjacent
= false;
1784 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1785 or a PARALLEL consisting of such a SET and CLOBBERs.
1787 If INSN has CLOBBER parallel parts, ignore them for our processing.
1788 By definition, these happen during the execution of the insn. When it
1789 is merged with another insn, all bets are off. If they are, in fact,
1790 needed and aren't also supplied in I3, they may be added by
1791 recog_for_combine. Otherwise, it won't match.
1793 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1796 Get the source and destination of INSN. If more than one, can't
1799 if (GET_CODE (PATTERN (insn
)) == SET
)
1800 set
= PATTERN (insn
);
1801 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1802 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1804 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1806 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1808 switch (GET_CODE (elt
))
1810 /* This is important to combine floating point insns
1811 for the SH4 port. */
1813 /* Combining an isolated USE doesn't make sense.
1814 We depend here on combinable_i3pat to reject them. */
1815 /* The code below this loop only verifies that the inputs of
1816 the SET in INSN do not change. We call reg_set_between_p
1817 to verify that the REG in the USE does not change between
1819 If the USE in INSN was for a pseudo register, the matching
1820 insn pattern will likely match any register; combining this
1821 with any other USE would only be safe if we knew that the
1822 used registers have identical values, or if there was
1823 something to tell them apart, e.g. different modes. For
1824 now, we forgo such complicated tests and simply disallow
1825 combining of USES of pseudo registers with any other USE. */
1826 if (REG_P (XEXP (elt
, 0))
1827 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1829 rtx i3pat
= PATTERN (i3
);
1830 int i
= XVECLEN (i3pat
, 0) - 1;
1831 unsigned int regno
= REGNO (XEXP (elt
, 0));
1835 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1837 if (GET_CODE (i3elt
) == USE
1838 && REG_P (XEXP (i3elt
, 0))
1839 && (REGNO (XEXP (i3elt
, 0)) == regno
1840 ? reg_set_between_p (XEXP (elt
, 0),
1841 PREV_INSN (insn
), i3
)
1842 : regno
>= FIRST_PSEUDO_REGISTER
))
1849 /* We can ignore CLOBBERs. */
1854 /* Ignore SETs whose result isn't used but not those that
1855 have side-effects. */
1856 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1857 && insn_nothrow_p (insn
)
1858 && !side_effects_p (elt
))
1861 /* If we have already found a SET, this is a second one and
1862 so we cannot combine with this insn. */
1870 /* Anything else means we can't combine. */
1876 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1877 so don't do anything with it. */
1878 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1887 /* The simplification in expand_field_assignment may call back to
1888 get_last_value, so set safe guard here. */
1889 subst_low_luid
= DF_INSN_LUID (insn
);
1891 set
= expand_field_assignment (set
);
1892 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1894 /* Don't eliminate a store in the stack pointer. */
1895 if (dest
== stack_pointer_rtx
1896 /* Don't combine with an insn that sets a register to itself if it has
1897 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1898 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1899 /* Can't merge an ASM_OPERANDS. */
1900 || GET_CODE (src
) == ASM_OPERANDS
1901 /* Can't merge a function call. */
1902 || GET_CODE (src
) == CALL
1903 /* Don't eliminate a function call argument. */
1905 && (find_reg_fusage (i3
, USE
, dest
)
1907 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1908 && global_regs
[REGNO (dest
)])))
1909 /* Don't substitute into an incremented register. */
1910 || FIND_REG_INC_NOTE (i3
, dest
)
1911 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1912 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1913 /* Don't substitute into a non-local goto, this confuses CFG. */
1914 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1915 /* Make sure that DEST is not used after SUCC but before I3. */
1918 && (reg_used_between_p (dest
, succ2
, i3
)
1919 || reg_used_between_p (dest
, succ
, succ2
)))
1920 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1921 /* Make sure that the value that is to be substituted for the register
1922 does not use any registers whose values alter in between. However,
1923 If the insns are adjacent, a use can't cross a set even though we
1924 think it might (this can happen for a sequence of insns each setting
1925 the same destination; last_set of that register might point to
1926 a NOTE). If INSN has a REG_EQUIV note, the register is always
1927 equivalent to the memory so the substitution is valid even if there
1928 are intervening stores. Also, don't move a volatile asm or
1929 UNSPEC_VOLATILE across any other insns. */
1932 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1933 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1934 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1935 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1936 /* Don't combine across a CALL_INSN, because that would possibly
1937 change whether the life span of some REGs crosses calls or not,
1938 and it is a pain to update that information.
1939 Exception: if source is a constant, moving it later can't hurt.
1940 Accept that as a special case. */
1941 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1944 /* DEST must either be a REG or CC0. */
1947 /* If register alignment is being enforced for multi-word items in all
1948 cases except for parameters, it is possible to have a register copy
1949 insn referencing a hard register that is not allowed to contain the
1950 mode being copied and which would not be valid as an operand of most
1951 insns. Eliminate this problem by not combining with such an insn.
1953 Also, on some machines we don't want to extend the life of a hard
1957 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1958 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1959 /* Don't extend the life of a hard register unless it is
1960 user variable (if we have few registers) or it can't
1961 fit into the desired register (meaning something special
1963 Also avoid substituting a return register into I3, because
1964 reload can't handle a conflict with constraints of other
1966 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1967 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1970 else if (GET_CODE (dest
) != CC0
)
1974 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1975 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1976 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1978 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1980 /* If the clobber represents an earlyclobber operand, we must not
1981 substitute an expression containing the clobbered register.
1982 As we do not analyze the constraint strings here, we have to
1983 make the conservative assumption. However, if the register is
1984 a fixed hard reg, the clobber cannot represent any operand;
1985 we leave it up to the machine description to either accept or
1986 reject use-and-clobber patterns. */
1988 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1989 || !fixed_regs
[REGNO (reg
)])
1990 if (reg_overlap_mentioned_p (reg
, src
))
1994 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1995 or not), reject, unless nothing volatile comes between it and I3 */
1997 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1999 /* Make sure neither succ nor succ2 contains a volatile reference. */
2000 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2002 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2004 /* We'll check insns between INSN and I3 below. */
2007 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2008 to be an explicit register variable, and was chosen for a reason. */
2010 if (GET_CODE (src
) == ASM_OPERANDS
2011 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2014 /* If INSN contains volatile references (specifically volatile MEMs),
2015 we cannot combine across any other volatile references.
2016 Even if INSN doesn't contain volatile references, any intervening
2017 volatile insn might affect machine state. */
2019 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2023 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2024 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2027 /* If INSN contains an autoincrement or autodecrement, make sure that
2028 register is not used between there and I3, and not already used in
2029 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2030 Also insist that I3 not be a jump; if it were one
2031 and the incremented register were spilled, we would lose. */
2034 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2035 if (REG_NOTE_KIND (link
) == REG_INC
2037 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2038 || (pred
!= NULL_RTX
2039 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2040 || (pred2
!= NULL_RTX
2041 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2042 || (succ
!= NULL_RTX
2043 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2044 || (succ2
!= NULL_RTX
2045 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2046 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2051 /* Don't combine an insn that follows a CC0-setting insn.
2052 An insn that uses CC0 must not be separated from the one that sets it.
2053 We do, however, allow I2 to follow a CC0-setting insn if that insn
2054 is passed as I1; in that case it will be deleted also.
2055 We also allow combining in this case if all the insns are adjacent
2056 because that would leave the two CC0 insns adjacent as well.
2057 It would be more logical to test whether CC0 occurs inside I1 or I2,
2058 but that would be much slower, and this ought to be equivalent. */
2060 p
= prev_nonnote_insn (insn
);
2061 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2066 /* If we get here, we have passed all the tests and the combination is
2075 /* LOC is the location within I3 that contains its pattern or the component
2076 of a PARALLEL of the pattern. We validate that it is valid for combining.
2078 One problem is if I3 modifies its output, as opposed to replacing it
2079 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2080 doing so would produce an insn that is not equivalent to the original insns.
2084 (set (reg:DI 101) (reg:DI 100))
2085 (set (subreg:SI (reg:DI 101) 0) <foo>)
2087 This is NOT equivalent to:
2089 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2090 (set (reg:DI 101) (reg:DI 100))])
2092 Not only does this modify 100 (in which case it might still be valid
2093 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2095 We can also run into a problem if I2 sets a register that I1
2096 uses and I1 gets directly substituted into I3 (not via I2). In that
2097 case, we would be getting the wrong value of I2DEST into I3, so we
2098 must reject the combination. This case occurs when I2 and I1 both
2099 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2100 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2101 of a SET must prevent combination from occurring. The same situation
2102 can occur for I0, in which case I0_NOT_IN_SRC is set.
2104 Before doing the above check, we first try to expand a field assignment
2105 into a set of logical operations.
2107 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2108 we place a register that is both set and used within I3. If more than one
2109 such register is detected, we fail.
2111 Return 1 if the combination is valid, zero otherwise. */
2114 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2115 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2119 if (GET_CODE (x
) == SET
)
2122 rtx dest
= SET_DEST (set
);
2123 rtx src
= SET_SRC (set
);
2124 rtx inner_dest
= dest
;
2127 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2128 || GET_CODE (inner_dest
) == SUBREG
2129 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2130 inner_dest
= XEXP (inner_dest
, 0);
2132 /* Check for the case where I3 modifies its output, as discussed
2133 above. We don't want to prevent pseudos from being combined
2134 into the address of a MEM, so only prevent the combination if
2135 i1 or i2 set the same MEM. */
2136 if ((inner_dest
!= dest
&&
2137 (!MEM_P (inner_dest
)
2138 || rtx_equal_p (i2dest
, inner_dest
)
2139 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2140 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2141 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2142 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2143 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2145 /* This is the same test done in can_combine_p except we can't test
2146 all_adjacent; we don't have to, since this instruction will stay
2147 in place, thus we are not considering increasing the lifetime of
2150 Also, if this insn sets a function argument, combining it with
2151 something that might need a spill could clobber a previous
2152 function argument; the all_adjacent test in can_combine_p also
2153 checks this; here, we do a more specific test for this case. */
2155 || (REG_P (inner_dest
)
2156 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2157 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2158 GET_MODE (inner_dest
))))
2159 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2160 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2163 /* If DEST is used in I3, it is being killed in this insn, so
2164 record that for later. We have to consider paradoxical
2165 subregs here, since they kill the whole register, but we
2166 ignore partial subregs, STRICT_LOW_PART, etc.
2167 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2168 STACK_POINTER_REGNUM, since these are always considered to be
2169 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2171 if (GET_CODE (subdest
) == SUBREG
2172 && (GET_MODE_SIZE (GET_MODE (subdest
))
2173 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2174 subdest
= SUBREG_REG (subdest
);
2177 && reg_referenced_p (subdest
, PATTERN (i3
))
2178 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2179 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2180 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2182 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2183 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2184 || ! fixed_regs
[REGNO (subdest
)])
2186 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2188 if (*pi3dest_killed
)
2191 *pi3dest_killed
= subdest
;
2195 else if (GET_CODE (x
) == PARALLEL
)
2199 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2200 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2201 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2208 /* Return 1 if X is an arithmetic expression that contains a multiplication
2209 and division. We don't count multiplications by powers of two here. */
2212 contains_muldiv (rtx x
)
2214 switch (GET_CODE (x
))
2216 case MOD
: case DIV
: case UMOD
: case UDIV
:
2220 return ! (CONST_INT_P (XEXP (x
, 1))
2221 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2224 return contains_muldiv (XEXP (x
, 0))
2225 || contains_muldiv (XEXP (x
, 1));
2228 return contains_muldiv (XEXP (x
, 0));
2234 /* Determine whether INSN can be used in a combination. Return nonzero if
2235 not. This is used in try_combine to detect early some cases where we
2236 can't perform combinations. */
2239 cant_combine_insn_p (rtx_insn
*insn
)
2244 /* If this isn't really an insn, we can't do anything.
2245 This can occur when flow deletes an insn that it has merged into an
2246 auto-increment address. */
2247 if (! INSN_P (insn
))
2250 /* Never combine loads and stores involving hard regs that are likely
2251 to be spilled. The register allocator can usually handle such
2252 reg-reg moves by tying. If we allow the combiner to make
2253 substitutions of likely-spilled regs, reload might die.
2254 As an exception, we allow combinations involving fixed regs; these are
2255 not available to the register allocator so there's no risk involved. */
2257 set
= single_set (insn
);
2260 src
= SET_SRC (set
);
2261 dest
= SET_DEST (set
);
2262 if (GET_CODE (src
) == SUBREG
)
2263 src
= SUBREG_REG (src
);
2264 if (GET_CODE (dest
) == SUBREG
)
2265 dest
= SUBREG_REG (dest
);
2266 if (REG_P (src
) && REG_P (dest
)
2267 && ((HARD_REGISTER_P (src
)
2268 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2269 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2270 || (HARD_REGISTER_P (dest
)
2271 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2272 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2278 struct likely_spilled_retval_info
2280 unsigned regno
, nregs
;
2284 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2285 hard registers that are known to be written to / clobbered in full. */
2287 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2289 struct likely_spilled_retval_info
*const info
=
2290 (struct likely_spilled_retval_info
*) data
;
2291 unsigned regno
, nregs
;
2294 if (!REG_P (XEXP (set
, 0)))
2297 if (regno
>= info
->regno
+ info
->nregs
)
2299 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2300 if (regno
+ nregs
<= info
->regno
)
2302 new_mask
= (2U << (nregs
- 1)) - 1;
2303 if (regno
< info
->regno
)
2304 new_mask
>>= info
->regno
- regno
;
2306 new_mask
<<= regno
- info
->regno
;
2307 info
->mask
&= ~new_mask
;
2310 /* Return nonzero iff part of the return value is live during INSN, and
2311 it is likely spilled. This can happen when more than one insn is needed
2312 to copy the return value, e.g. when we consider to combine into the
2313 second copy insn for a complex value. */
2316 likely_spilled_retval_p (rtx_insn
*insn
)
2318 rtx_insn
*use
= BB_END (this_basic_block
);
2321 unsigned regno
, nregs
;
2322 /* We assume here that no machine mode needs more than
2323 32 hard registers when the value overlaps with a register
2324 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2326 struct likely_spilled_retval_info info
;
2328 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2330 reg
= XEXP (PATTERN (use
), 0);
2331 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2333 regno
= REGNO (reg
);
2334 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2337 mask
= (2U << (nregs
- 1)) - 1;
2339 /* Disregard parts of the return value that are set later. */
2343 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2345 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2348 /* Check if any of the (probably) live return value registers is
2353 if ((mask
& 1 << nregs
)
2354 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2360 /* Adjust INSN after we made a change to its destination.
2362 Changing the destination can invalidate notes that say something about
2363 the results of the insn and a LOG_LINK pointing to the insn. */
2366 adjust_for_new_dest (rtx_insn
*insn
)
2368 /* For notes, be conservative and simply remove them. */
2369 remove_reg_equal_equiv_notes (insn
);
2371 /* The new insn will have a destination that was previously the destination
2372 of an insn just above it. Call distribute_links to make a LOG_LINK from
2373 the next use of that destination. */
2375 rtx set
= single_set (insn
);
2378 rtx reg
= SET_DEST (set
);
2380 while (GET_CODE (reg
) == ZERO_EXTRACT
2381 || GET_CODE (reg
) == STRICT_LOW_PART
2382 || GET_CODE (reg
) == SUBREG
)
2383 reg
= XEXP (reg
, 0);
2384 gcc_assert (REG_P (reg
));
2386 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2388 df_insn_rescan (insn
);
2391 /* Return TRUE if combine can reuse reg X in mode MODE.
2392 ADDED_SETS is nonzero if the original set is still required. */
2394 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2402 /* Allow hard registers if the new mode is legal, and occupies no more
2403 registers than the old mode. */
2404 if (regno
< FIRST_PSEUDO_REGISTER
)
2405 return (HARD_REGNO_MODE_OK (regno
, mode
)
2406 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2407 >= hard_regno_nregs
[regno
][mode
]));
2409 /* Or a pseudo that is only used once. */
2410 return (REG_N_SETS (regno
) == 1 && !added_sets
2411 && !REG_USERVAR_P (x
));
2415 /* Check whether X, the destination of a set, refers to part of
2416 the register specified by REG. */
2419 reg_subword_p (rtx x
, rtx reg
)
2421 /* Check that reg is an integer mode register. */
2422 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2425 if (GET_CODE (x
) == STRICT_LOW_PART
2426 || GET_CODE (x
) == ZERO_EXTRACT
)
2429 return GET_CODE (x
) == SUBREG
2430 && SUBREG_REG (x
) == reg
2431 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2434 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2435 Note that the INSN should be deleted *after* removing dead edges, so
2436 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2437 but not for a (set (pc) (label_ref FOO)). */
2440 update_cfg_for_uncondjump (rtx_insn
*insn
)
2442 basic_block bb
= BLOCK_FOR_INSN (insn
);
2443 gcc_assert (BB_END (bb
) == insn
);
2445 purge_dead_edges (bb
);
2448 if (EDGE_COUNT (bb
->succs
) == 1)
2452 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2454 /* Remove barriers from the footer if there are any. */
2455 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2456 if (BARRIER_P (insn
))
2458 if (PREV_INSN (insn
))
2459 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2461 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2462 if (NEXT_INSN (insn
))
2463 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2465 else if (LABEL_P (insn
))
2471 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2472 by an arbitrary number of CLOBBERs. */
2474 is_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2476 rtx pat
= PATTERN (insn
);
2478 if (GET_CODE (pat
) != PARALLEL
)
2481 int len
= XVECLEN (pat
, 0);
2486 for (i
= 0; i
< n
; i
++)
2487 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2488 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2490 for ( ; i
< len
; i
++)
2491 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2497 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2498 CLOBBERs), can be split into individual SETs in that order, without
2499 changing semantics. */
2501 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2503 if (!insn_nothrow_p (insn
))
2506 rtx pat
= PATTERN (insn
);
2509 for (i
= 0; i
< n
; i
++)
2511 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2514 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2516 for (j
= i
+ 1; j
< n
; j
++)
2517 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2525 /* Try to combine the insns I0, I1 and I2 into I3.
2526 Here I0, I1 and I2 appear earlier than I3.
2527 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2530 If we are combining more than two insns and the resulting insn is not
2531 recognized, try splitting it into two insns. If that happens, I2 and I3
2532 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2533 Otherwise, I0, I1 and I2 are pseudo-deleted.
2535 Return 0 if the combination does not work. Then nothing is changed.
2536 If we did the combination, return the insn at which combine should
2539 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2540 new direct jump instruction.
2542 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2543 been I3 passed to an earlier try_combine within the same basic
2547 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2548 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2550 /* New patterns for I3 and I2, respectively. */
2551 rtx newpat
, newi2pat
= 0;
2552 rtvec newpat_vec_with_clobbers
= 0;
2553 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2554 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2556 int added_sets_0
, added_sets_1
, added_sets_2
;
2557 /* Total number of SETs to put into I3. */
2559 /* Nonzero if I2's or I1's body now appears in I3. */
2560 int i2_is_used
= 0, i1_is_used
= 0;
2561 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2562 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2563 /* Contains I3 if the destination of I3 is used in its source, which means
2564 that the old life of I3 is being killed. If that usage is placed into
2565 I2 and not in I3, a REG_DEAD note must be made. */
2566 rtx i3dest_killed
= 0;
2567 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2568 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2569 /* Copy of SET_SRC of I1 and I0, if needed. */
2570 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2571 /* Set if I2DEST was reused as a scratch register. */
2572 bool i2scratch
= false;
2573 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2574 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2575 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2576 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2577 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2578 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2579 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2580 /* Notes that must be added to REG_NOTES in I3 and I2. */
2581 rtx new_i3_notes
, new_i2_notes
;
2582 /* Notes that we substituted I3 into I2 instead of the normal case. */
2583 int i3_subst_into_i2
= 0;
2584 /* Notes that I1, I2 or I3 is a MULT operation. */
2587 int changed_i3_dest
= 0;
2590 rtx_insn
*temp_insn
;
2592 struct insn_link
*link
;
2594 rtx new_other_notes
;
2597 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2599 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2602 /* Only try four-insn combinations when there's high likelihood of
2603 success. Look for simple insns, such as loads of constants or
2604 binary operations involving a constant. */
2611 if (!flag_expensive_optimizations
)
2614 for (i
= 0; i
< 4; i
++)
2616 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2617 rtx set
= single_set (insn
);
2621 src
= SET_SRC (set
);
2622 if (CONSTANT_P (src
))
2627 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2629 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2630 || GET_CODE (src
) == LSHIFTRT
)
2633 if (ngood
< 2 && nshift
< 2)
2637 /* Exit early if one of the insns involved can't be used for
2640 || (i1
&& CALL_P (i1
))
2641 || (i0
&& CALL_P (i0
))
2642 || cant_combine_insn_p (i3
)
2643 || cant_combine_insn_p (i2
)
2644 || (i1
&& cant_combine_insn_p (i1
))
2645 || (i0
&& cant_combine_insn_p (i0
))
2646 || likely_spilled_retval_p (i3
))
2650 undobuf
.other_insn
= 0;
2652 /* Reset the hard register usage information. */
2653 CLEAR_HARD_REG_SET (newpat_used_regs
);
2655 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2658 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2659 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2661 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2662 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2664 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2665 INSN_UID (i2
), INSN_UID (i3
));
2668 /* If multiple insns feed into one of I2 or I3, they can be in any
2669 order. To simplify the code below, reorder them in sequence. */
2670 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2671 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2672 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2673 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2674 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2675 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2677 added_links_insn
= 0;
2679 /* First check for one important special case that the code below will
2680 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2681 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2682 we may be able to replace that destination with the destination of I3.
2683 This occurs in the common code where we compute both a quotient and
2684 remainder into a structure, in which case we want to do the computation
2685 directly into the structure to avoid register-register copies.
2687 Note that this case handles both multiple sets in I2 and also cases
2688 where I2 has a number of CLOBBERs inside the PARALLEL.
2690 We make very conservative checks below and only try to handle the
2691 most common cases of this. For example, we only handle the case
2692 where I2 and I3 are adjacent to avoid making difficult register
2695 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2696 && REG_P (SET_SRC (PATTERN (i3
)))
2697 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2698 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2699 && GET_CODE (PATTERN (i2
)) == PARALLEL
2700 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2701 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2702 below would need to check what is inside (and reg_overlap_mentioned_p
2703 doesn't support those codes anyway). Don't allow those destinations;
2704 the resulting insn isn't likely to be recognized anyway. */
2705 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2706 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2707 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2708 SET_DEST (PATTERN (i3
)))
2709 && next_active_insn (i2
) == i3
)
2711 rtx p2
= PATTERN (i2
);
2713 /* Make sure that the destination of I3,
2714 which we are going to substitute into one output of I2,
2715 is not used within another output of I2. We must avoid making this:
2716 (parallel [(set (mem (reg 69)) ...)
2717 (set (reg 69) ...)])
2718 which is not well-defined as to order of actions.
2719 (Besides, reload can't handle output reloads for this.)
2721 The problem can also happen if the dest of I3 is a memory ref,
2722 if another dest in I2 is an indirect memory ref. */
2723 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2724 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2725 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2726 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2727 SET_DEST (XVECEXP (p2
, 0, i
))))
2730 /* Make sure this PARALLEL is not an asm. We do not allow combining
2731 that usually (see can_combine_p), so do not here either. */
2732 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2733 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2734 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2737 if (i
== XVECLEN (p2
, 0))
2738 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2739 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2740 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2745 subst_low_luid
= DF_INSN_LUID (i2
);
2747 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2748 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2749 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2750 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2752 /* Replace the dest in I2 with our dest and make the resulting
2753 insn the new pattern for I3. Then skip to where we validate
2754 the pattern. Everything was set up above. */
2755 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2757 i3_subst_into_i2
= 1;
2758 goto validate_replacement
;
2762 /* If I2 is setting a pseudo to a constant and I3 is setting some
2763 sub-part of it to another constant, merge them by making a new
2766 && (temp_expr
= single_set (i2
)) != 0
2767 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2768 && GET_CODE (PATTERN (i3
)) == SET
2769 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2770 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2772 rtx dest
= SET_DEST (PATTERN (i3
));
2776 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2778 if (CONST_INT_P (XEXP (dest
, 1))
2779 && CONST_INT_P (XEXP (dest
, 2)))
2781 width
= INTVAL (XEXP (dest
, 1));
2782 offset
= INTVAL (XEXP (dest
, 2));
2783 dest
= XEXP (dest
, 0);
2784 if (BITS_BIG_ENDIAN
)
2785 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2790 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2791 dest
= XEXP (dest
, 0);
2792 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2798 /* If this is the low part, we're done. */
2799 if (subreg_lowpart_p (dest
))
2801 /* Handle the case where inner is twice the size of outer. */
2802 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2803 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2804 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2805 /* Otherwise give up for now. */
2812 rtx inner
= SET_SRC (PATTERN (i3
));
2813 rtx outer
= SET_SRC (temp_expr
);
2816 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2817 std::make_pair (inner
, GET_MODE (dest
)),
2822 subst_low_luid
= DF_INSN_LUID (i2
);
2823 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2824 i2dest
= SET_DEST (temp_expr
);
2825 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2827 /* Replace the source in I2 with the new constant and make the
2828 resulting insn the new pattern for I3. Then skip to where we
2829 validate the pattern. Everything was set up above. */
2830 SUBST (SET_SRC (temp_expr
),
2831 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2833 newpat
= PATTERN (i2
);
2835 /* The dest of I3 has been replaced with the dest of I2. */
2836 changed_i3_dest
= 1;
2837 goto validate_replacement
;
2842 /* If we have no I1 and I2 looks like:
2843 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2845 make up a dummy I1 that is
2848 (set (reg:CC X) (compare:CC Y (const_int 0)))
2850 (We can ignore any trailing CLOBBERs.)
2852 This undoes a previous combination and allows us to match a branch-and-
2856 && is_parallel_of_n_reg_sets (i2
, 2)
2857 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2859 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2860 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2861 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2862 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2863 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2864 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2866 /* We make I1 with the same INSN_UID as I2. This gives it
2867 the same DF_INSN_LUID for value tracking. Our fake I1 will
2868 never appear in the insn stream so giving it the same INSN_UID
2869 as I2 will not cause a problem. */
2871 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2872 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2874 INSN_UID (i1
) = INSN_UID (i2
);
2876 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2877 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2878 SET_DEST (PATTERN (i1
)));
2879 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2880 SUBST_LINK (LOG_LINKS (i2
),
2881 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2884 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2885 make those two SETs separate I1 and I2 insns, and make an I0 that is
2888 && is_parallel_of_n_reg_sets (i2
, 2)
2889 && can_split_parallel_of_n_reg_sets (i2
, 2)
2890 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2891 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2893 /* If there is no I1, there is no I0 either. */
2896 /* We make I1 with the same INSN_UID as I2. This gives it
2897 the same DF_INSN_LUID for value tracking. Our fake I1 will
2898 never appear in the insn stream so giving it the same INSN_UID
2899 as I2 will not cause a problem. */
2901 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2902 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2904 INSN_UID (i1
) = INSN_UID (i2
);
2906 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2910 /* Verify that I2 and I1 are valid for combining. */
2911 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2912 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2914 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2921 /* Record whether I2DEST is used in I2SRC and similarly for the other
2922 cases. Knowing this will help in register status updating below. */
2923 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2924 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2925 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2926 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2927 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2928 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2929 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2930 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2931 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2933 /* For the earlier insns, determine which of the subsequent ones they
2935 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2936 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2937 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2938 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2939 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2941 /* Ensure that I3's pattern can be the destination of combines. */
2942 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2943 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2944 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2945 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2952 /* See if any of the insns is a MULT operation. Unless one is, we will
2953 reject a combination that is, since it must be slower. Be conservative
2955 if (GET_CODE (i2src
) == MULT
2956 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2957 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2958 || (GET_CODE (PATTERN (i3
)) == SET
2959 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2962 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2963 We used to do this EXCEPT in one case: I3 has a post-inc in an
2964 output operand. However, that exception can give rise to insns like
2966 which is a famous insn on the PDP-11 where the value of r3 used as the
2967 source was model-dependent. Avoid this sort of thing. */
2970 if (!(GET_CODE (PATTERN (i3
)) == SET
2971 && REG_P (SET_SRC (PATTERN (i3
)))
2972 && MEM_P (SET_DEST (PATTERN (i3
)))
2973 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2974 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2975 /* It's not the exception. */
2980 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2981 if (REG_NOTE_KIND (link
) == REG_INC
2982 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2984 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2992 /* See if the SETs in I1 or I2 need to be kept around in the merged
2993 instruction: whenever the value set there is still needed past I3.
2994 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2996 For the SET in I1, we have two cases: if I1 and I2 independently feed
2997 into I3, the set in I1 needs to be kept around unless I1DEST dies
2998 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2999 in I1 needs to be kept around unless I1DEST dies or is set in either
3000 I2 or I3. The same considerations apply to I0. */
3002 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3005 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3006 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3011 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3012 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3013 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3014 && dead_or_set_p (i2
, i0dest
)));
3018 /* We are about to copy insns for the case where they need to be kept
3019 around. Check that they can be copied in the merged instruction. */
3021 if (targetm
.cannot_copy_insn_p
3022 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3023 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3024 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3030 /* If the set in I2 needs to be kept around, we must make a copy of
3031 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3032 PATTERN (I2), we are only substituting for the original I1DEST, not into
3033 an already-substituted copy. This also prevents making self-referential
3034 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3039 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3040 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
3042 i2pat
= copy_rtx (PATTERN (i2
));
3047 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3048 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
3050 i1pat
= copy_rtx (PATTERN (i1
));
3055 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3056 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
3058 i0pat
= copy_rtx (PATTERN (i0
));
3063 /* Substitute in the latest insn for the regs set by the earlier ones. */
3065 maxreg
= max_reg_num ();
3070 /* Many machines that don't use CC0 have insns that can both perform an
3071 arithmetic operation and set the condition code. These operations will
3072 be represented as a PARALLEL with the first element of the vector
3073 being a COMPARE of an arithmetic operation with the constant zero.
3074 The second element of the vector will set some pseudo to the result
3075 of the same arithmetic operation. If we simplify the COMPARE, we won't
3076 match such a pattern and so will generate an extra insn. Here we test
3077 for this case, where both the comparison and the operation result are
3078 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3079 I2SRC. Later we will make the PARALLEL that contains I2. */
3081 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3082 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3083 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3084 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3087 rtx
*cc_use_loc
= NULL
;
3088 rtx_insn
*cc_use_insn
= NULL
;
3089 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3090 machine_mode compare_mode
, orig_compare_mode
;
3091 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3093 newpat
= PATTERN (i3
);
3094 newpat_dest
= SET_DEST (newpat
);
3095 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3097 if (undobuf
.other_insn
== 0
3098 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3101 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3102 compare_code
= simplify_compare_const (compare_code
,
3103 GET_MODE (i2dest
), op0
, &op1
);
3104 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3107 /* Do the rest only if op1 is const0_rtx, which may be the
3108 result of simplification. */
3109 if (op1
== const0_rtx
)
3111 /* If a single use of the CC is found, prepare to modify it
3112 when SELECT_CC_MODE returns a new CC-class mode, or when
3113 the above simplify_compare_const() returned a new comparison
3114 operator. undobuf.other_insn is assigned the CC use insn
3115 when modifying it. */
3118 #ifdef SELECT_CC_MODE
3119 machine_mode new_mode
3120 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3121 if (new_mode
!= orig_compare_mode
3122 && can_change_dest_mode (SET_DEST (newpat
),
3123 added_sets_2
, new_mode
))
3125 unsigned int regno
= REGNO (newpat_dest
);
3126 compare_mode
= new_mode
;
3127 if (regno
< FIRST_PSEUDO_REGISTER
)
3128 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3131 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3132 newpat_dest
= regno_reg_rtx
[regno
];
3136 /* Cases for modifying the CC-using comparison. */
3137 if (compare_code
!= orig_compare_code
3138 /* ??? Do we need to verify the zero rtx? */
3139 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3141 /* Replace cc_use_loc with entire new RTX. */
3143 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3144 newpat_dest
, const0_rtx
));
3145 undobuf
.other_insn
= cc_use_insn
;
3147 else if (compare_mode
!= orig_compare_mode
)
3149 /* Just replace the CC reg with a new mode. */
3150 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3151 undobuf
.other_insn
= cc_use_insn
;
3155 /* Now we modify the current newpat:
3156 First, SET_DEST(newpat) is updated if the CC mode has been
3157 altered. For targets without SELECT_CC_MODE, this should be
3159 if (compare_mode
!= orig_compare_mode
)
3160 SUBST (SET_DEST (newpat
), newpat_dest
);
3161 /* This is always done to propagate i2src into newpat. */
3162 SUBST (SET_SRC (newpat
),
3163 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3164 /* Create new version of i2pat if needed; the below PARALLEL
3165 creation needs this to work correctly. */
3166 if (! rtx_equal_p (i2src
, op0
))
3167 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3173 if (i2_is_used
== 0)
3175 /* It is possible that the source of I2 or I1 may be performing
3176 an unneeded operation, such as a ZERO_EXTEND of something
3177 that is known to have the high part zero. Handle that case
3178 by letting subst look at the inner insns.
3180 Another way to do this would be to have a function that tries
3181 to simplify a single insn instead of merging two or more
3182 insns. We don't do this because of the potential of infinite
3183 loops and because of the potential extra memory required.
3184 However, doing it the way we are is a bit of a kludge and
3185 doesn't catch all cases.
3187 But only do this if -fexpensive-optimizations since it slows
3188 things down and doesn't usually win.
3190 This is not done in the COMPARE case above because the
3191 unmodified I2PAT is used in the PARALLEL and so a pattern
3192 with a modified I2SRC would not match. */
3194 if (flag_expensive_optimizations
)
3196 /* Pass pc_rtx so no substitutions are done, just
3200 subst_low_luid
= DF_INSN_LUID (i1
);
3201 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3204 subst_low_luid
= DF_INSN_LUID (i2
);
3205 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3208 n_occurrences
= 0; /* `subst' counts here */
3209 subst_low_luid
= DF_INSN_LUID (i2
);
3211 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3212 copy of I2SRC each time we substitute it, in order to avoid creating
3213 self-referential RTL when we will be substituting I1SRC for I1DEST
3214 later. Likewise if I0 feeds into I2, either directly or indirectly
3215 through I1, and I0DEST is in I0SRC. */
3216 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3217 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3218 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3219 && i0dest_in_i0src
));
3222 /* Record whether I2's body now appears within I3's body. */
3223 i2_is_used
= n_occurrences
;
3226 /* If we already got a failure, don't try to do more. Otherwise, try to
3227 substitute I1 if we have it. */
3229 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3231 /* Check that an autoincrement side-effect on I1 has not been lost.
3232 This happens if I1DEST is mentioned in I2 and dies there, and
3233 has disappeared from the new pattern. */
3234 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3236 && dead_or_set_p (i2
, i1dest
)
3237 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3238 /* Before we can do this substitution, we must redo the test done
3239 above (see detailed comments there) that ensures I1DEST isn't
3240 mentioned in any SETs in NEWPAT that are field assignments. */
3241 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3249 subst_low_luid
= DF_INSN_LUID (i1
);
3251 /* If the following substitution will modify I1SRC, make a copy of it
3252 for the case where it is substituted for I1DEST in I2PAT later. */
3253 if (added_sets_2
&& i1_feeds_i2_n
)
3254 i1src_copy
= copy_rtx (i1src
);
3256 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3257 copy of I1SRC each time we substitute it, in order to avoid creating
3258 self-referential RTL when we will be substituting I0SRC for I0DEST
3260 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3261 i0_feeds_i1_n
&& i0dest_in_i0src
);
3264 /* Record whether I1's body now appears within I3's body. */
3265 i1_is_used
= n_occurrences
;
3268 /* Likewise for I0 if we have it. */
3270 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3272 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3273 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3274 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3275 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3276 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3283 /* If the following substitution will modify I0SRC, make a copy of it
3284 for the case where it is substituted for I0DEST in I1PAT later. */
3285 if (added_sets_1
&& i0_feeds_i1_n
)
3286 i0src_copy
= copy_rtx (i0src
);
3287 /* And a copy for I0DEST in I2PAT substitution. */
3288 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3289 || (i0_feeds_i2_n
)))
3290 i0src_copy2
= copy_rtx (i0src
);
3293 subst_low_luid
= DF_INSN_LUID (i0
);
3294 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3298 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3299 to count all the ways that I2SRC and I1SRC can be used. */
3300 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3301 && i2_is_used
+ added_sets_2
> 1)
3302 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3303 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3305 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3306 && (n_occurrences
+ added_sets_0
3307 + (added_sets_1
&& i0_feeds_i1_n
)
3308 + (added_sets_2
&& i0_feeds_i2_n
)
3310 /* Fail if we tried to make a new register. */
3311 || max_reg_num () != maxreg
3312 /* Fail if we couldn't do something and have a CLOBBER. */
3313 || GET_CODE (newpat
) == CLOBBER
3314 /* Fail if this new pattern is a MULT and we didn't have one before
3315 at the outer level. */
3316 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3323 /* If the actions of the earlier insns must be kept
3324 in addition to substituting them into the latest one,
3325 we must make a new PARALLEL for the latest insn
3326 to hold additional the SETs. */
3328 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3330 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3333 if (GET_CODE (newpat
) == PARALLEL
)
3335 rtvec old
= XVEC (newpat
, 0);
3336 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3337 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3338 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3339 sizeof (old
->elem
[0]) * old
->num_elem
);
3344 total_sets
= 1 + extra_sets
;
3345 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3346 XVECEXP (newpat
, 0, 0) = old
;
3350 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3356 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3358 XVECEXP (newpat
, 0, --total_sets
) = t
;
3364 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3365 i0_feeds_i1_n
&& i0dest_in_i0src
);
3366 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3367 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3369 XVECEXP (newpat
, 0, --total_sets
) = t
;
3373 validate_replacement
:
3375 /* Note which hard regs this insn has as inputs. */
3376 mark_used_regs_combine (newpat
);
3378 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3379 consider splitting this pattern, we might need these clobbers. */
3380 if (i1
&& GET_CODE (newpat
) == PARALLEL
3381 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3383 int len
= XVECLEN (newpat
, 0);
3385 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3386 for (i
= 0; i
< len
; i
++)
3387 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3390 /* We have recognized nothing yet. */
3391 insn_code_number
= -1;
3393 /* See if this is a PARALLEL of two SETs where one SET's destination is
3394 a register that is unused and this isn't marked as an instruction that
3395 might trap in an EH region. In that case, we just need the other SET.
3396 We prefer this over the PARALLEL.
3398 This can occur when simplifying a divmod insn. We *must* test for this
3399 case here because the code below that splits two independent SETs doesn't
3400 handle this case correctly when it updates the register status.
3402 It's pointless doing this if we originally had two sets, one from
3403 i3, and one from i2. Combining then splitting the parallel results
3404 in the original i2 again plus an invalid insn (which we delete).
3405 The net effect is only to move instructions around, which makes
3406 debug info less accurate. */
3408 if (!(added_sets_2
&& i1
== 0)
3409 && GET_CODE (newpat
) == PARALLEL
3410 && XVECLEN (newpat
, 0) == 2
3411 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3412 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3413 && asm_noperands (newpat
) < 0)
3415 rtx set0
= XVECEXP (newpat
, 0, 0);
3416 rtx set1
= XVECEXP (newpat
, 0, 1);
3417 rtx oldpat
= newpat
;
3419 if (((REG_P (SET_DEST (set1
))
3420 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3421 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3422 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3423 && insn_nothrow_p (i3
)
3424 && !side_effects_p (SET_SRC (set1
)))
3427 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3430 else if (((REG_P (SET_DEST (set0
))
3431 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3432 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3433 && find_reg_note (i3
, REG_UNUSED
,
3434 SUBREG_REG (SET_DEST (set0
)))))
3435 && insn_nothrow_p (i3
)
3436 && !side_effects_p (SET_SRC (set0
)))
3439 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3441 if (insn_code_number
>= 0)
3442 changed_i3_dest
= 1;
3445 if (insn_code_number
< 0)
3449 /* Is the result of combination a valid instruction? */
3450 if (insn_code_number
< 0)
3451 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3453 /* If we were combining three insns and the result is a simple SET
3454 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3455 insns. There are two ways to do this. It can be split using a
3456 machine-specific method (like when you have an addition of a large
3457 constant) or by combine in the function find_split_point. */
3459 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3460 && asm_noperands (newpat
) < 0)
3462 rtx parallel
, *split
;
3463 rtx_insn
*m_split_insn
;
3465 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3466 use I2DEST as a scratch register will help. In the latter case,
3467 convert I2DEST to the mode of the source of NEWPAT if we can. */
3469 m_split_insn
= combine_split_insns (newpat
, i3
);
3471 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3472 inputs of NEWPAT. */
3474 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3475 possible to try that as a scratch reg. This would require adding
3476 more code to make it work though. */
3478 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3480 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3482 /* First try to split using the original register as a
3483 scratch register. */
3484 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3485 gen_rtvec (2, newpat
,
3486 gen_rtx_CLOBBER (VOIDmode
,
3488 m_split_insn
= combine_split_insns (parallel
, i3
);
3490 /* If that didn't work, try changing the mode of I2DEST if
3492 if (m_split_insn
== 0
3493 && new_mode
!= GET_MODE (i2dest
)
3494 && new_mode
!= VOIDmode
3495 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3497 machine_mode old_mode
= GET_MODE (i2dest
);
3500 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3501 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3504 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3505 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3508 parallel
= (gen_rtx_PARALLEL
3510 gen_rtvec (2, newpat
,
3511 gen_rtx_CLOBBER (VOIDmode
,
3513 m_split_insn
= combine_split_insns (parallel
, i3
);
3515 if (m_split_insn
== 0
3516 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3520 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3521 buf
= undobuf
.undos
;
3522 undobuf
.undos
= buf
->next
;
3523 buf
->next
= undobuf
.frees
;
3524 undobuf
.frees
= buf
;
3528 i2scratch
= m_split_insn
!= 0;
3531 /* If recog_for_combine has discarded clobbers, try to use them
3532 again for the split. */
3533 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3535 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3536 m_split_insn
= combine_split_insns (parallel
, i3
);
3539 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3541 rtx m_split_pat
= PATTERN (m_split_insn
);
3542 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3543 if (insn_code_number
>= 0)
3544 newpat
= m_split_pat
;
3546 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3547 && (next_nonnote_nondebug_insn (i2
) == i3
3548 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3551 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3552 newi2pat
= PATTERN (m_split_insn
);
3554 i3set
= single_set (NEXT_INSN (m_split_insn
));
3555 i2set
= single_set (m_split_insn
);
3557 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3559 /* If I2 or I3 has multiple SETs, we won't know how to track
3560 register status, so don't use these insns. If I2's destination
3561 is used between I2 and I3, we also can't use these insns. */
3563 if (i2_code_number
>= 0 && i2set
&& i3set
3564 && (next_nonnote_nondebug_insn (i2
) == i3
3565 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3566 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3568 if (insn_code_number
>= 0)
3571 /* It is possible that both insns now set the destination of I3.
3572 If so, we must show an extra use of it. */
3574 if (insn_code_number
>= 0)
3576 rtx new_i3_dest
= SET_DEST (i3set
);
3577 rtx new_i2_dest
= SET_DEST (i2set
);
3579 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3580 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3581 || GET_CODE (new_i3_dest
) == SUBREG
)
3582 new_i3_dest
= XEXP (new_i3_dest
, 0);
3584 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3585 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3586 || GET_CODE (new_i2_dest
) == SUBREG
)
3587 new_i2_dest
= XEXP (new_i2_dest
, 0);
3589 if (REG_P (new_i3_dest
)
3590 && REG_P (new_i2_dest
)
3591 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3592 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3596 /* If we can split it and use I2DEST, go ahead and see if that
3597 helps things be recognized. Verify that none of the registers
3598 are set between I2 and I3. */
3599 if (insn_code_number
< 0
3600 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3604 /* We need I2DEST in the proper mode. If it is a hard register
3605 or the only use of a pseudo, we can change its mode.
3606 Make sure we don't change a hard register to have a mode that
3607 isn't valid for it, or change the number of registers. */
3608 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3609 || GET_MODE (*split
) == VOIDmode
3610 || can_change_dest_mode (i2dest
, added_sets_2
,
3612 && (next_nonnote_nondebug_insn (i2
) == i3
3613 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3614 /* We can't overwrite I2DEST if its value is still used by
3616 && ! reg_referenced_p (i2dest
, newpat
))
3618 rtx newdest
= i2dest
;
3619 enum rtx_code split_code
= GET_CODE (*split
);
3620 machine_mode split_mode
= GET_MODE (*split
);
3621 bool subst_done
= false;
3622 newi2pat
= NULL_RTX
;
3626 /* *SPLIT may be part of I2SRC, so make sure we have the
3627 original expression around for later debug processing.
3628 We should not need I2SRC any more in other cases. */
3629 if (MAY_HAVE_DEBUG_INSNS
)
3630 i2src
= copy_rtx (i2src
);
3634 /* Get NEWDEST as a register in the proper mode. We have already
3635 validated that we can do this. */
3636 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3638 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3639 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3642 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3643 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3647 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3648 an ASHIFT. This can occur if it was inside a PLUS and hence
3649 appeared to be a memory address. This is a kludge. */
3650 if (split_code
== MULT
3651 && CONST_INT_P (XEXP (*split
, 1))
3652 && INTVAL (XEXP (*split
, 1)) > 0
3653 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3655 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3656 XEXP (*split
, 0), GEN_INT (i
)));
3657 /* Update split_code because we may not have a multiply
3659 split_code
= GET_CODE (*split
);
3662 #ifdef INSN_SCHEDULING
3663 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3664 be written as a ZERO_EXTEND. */
3665 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3667 #ifdef LOAD_EXTEND_OP
3668 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3669 what it really is. */
3670 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3672 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3673 SUBREG_REG (*split
)));
3676 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3677 SUBREG_REG (*split
)));
3681 /* Attempt to split binary operators using arithmetic identities. */
3682 if (BINARY_P (SET_SRC (newpat
))
3683 && split_mode
== GET_MODE (SET_SRC (newpat
))
3684 && ! side_effects_p (SET_SRC (newpat
)))
3686 rtx setsrc
= SET_SRC (newpat
);
3687 machine_mode mode
= GET_MODE (setsrc
);
3688 enum rtx_code code
= GET_CODE (setsrc
);
3689 rtx src_op0
= XEXP (setsrc
, 0);
3690 rtx src_op1
= XEXP (setsrc
, 1);
3692 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3693 if (rtx_equal_p (src_op0
, src_op1
))
3695 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3696 SUBST (XEXP (setsrc
, 0), newdest
);
3697 SUBST (XEXP (setsrc
, 1), newdest
);
3700 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3701 else if ((code
== PLUS
|| code
== MULT
)
3702 && GET_CODE (src_op0
) == code
3703 && GET_CODE (XEXP (src_op0
, 0)) == code
3704 && (INTEGRAL_MODE_P (mode
)
3705 || (FLOAT_MODE_P (mode
)
3706 && flag_unsafe_math_optimizations
)))
3708 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3709 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3710 rtx r
= XEXP (src_op0
, 1);
3713 /* Split both "((X op Y) op X) op Y" and
3714 "((X op Y) op Y) op X" as "T op T" where T is
3716 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3717 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3719 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3721 SUBST (XEXP (setsrc
, 0), newdest
);
3722 SUBST (XEXP (setsrc
, 1), newdest
);
3725 /* Split "((X op X) op Y) op Y)" as "T op T" where
3727 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3729 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3730 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3731 SUBST (XEXP (setsrc
, 0), newdest
);
3732 SUBST (XEXP (setsrc
, 1), newdest
);
3740 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3741 SUBST (*split
, newdest
);
3744 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3746 /* recog_for_combine might have added CLOBBERs to newi2pat.
3747 Make sure NEWPAT does not depend on the clobbered regs. */
3748 if (GET_CODE (newi2pat
) == PARALLEL
)
3749 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3750 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3752 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3753 if (reg_overlap_mentioned_p (reg
, newpat
))
3760 /* If the split point was a MULT and we didn't have one before,
3761 don't use one now. */
3762 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3763 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3767 /* Check for a case where we loaded from memory in a narrow mode and
3768 then sign extended it, but we need both registers. In that case,
3769 we have a PARALLEL with both loads from the same memory location.
3770 We can split this into a load from memory followed by a register-register
3771 copy. This saves at least one insn, more if register allocation can
3774 We cannot do this if the destination of the first assignment is a
3775 condition code register or cc0. We eliminate this case by making sure
3776 the SET_DEST and SET_SRC have the same mode.
3778 We cannot do this if the destination of the second assignment is
3779 a register that we have already assumed is zero-extended. Similarly
3780 for a SUBREG of such a register. */
3782 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3783 && GET_CODE (newpat
) == PARALLEL
3784 && XVECLEN (newpat
, 0) == 2
3785 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3786 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3787 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3788 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3789 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3790 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3791 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3792 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3794 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3795 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3796 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3798 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3799 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3800 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3801 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3802 != GET_MODE_MASK (word_mode
))))
3803 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3804 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3806 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3807 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3808 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3809 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3810 != GET_MODE_MASK (word_mode
)))))
3811 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3812 SET_SRC (XVECEXP (newpat
, 0, 1)))
3813 && ! find_reg_note (i3
, REG_UNUSED
,
3814 SET_DEST (XVECEXP (newpat
, 0, 0))))
3818 newi2pat
= XVECEXP (newpat
, 0, 0);
3819 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3820 newpat
= XVECEXP (newpat
, 0, 1);
3821 SUBST (SET_SRC (newpat
),
3822 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3823 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3825 if (i2_code_number
>= 0)
3826 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3828 if (insn_code_number
>= 0)
3832 /* Similarly, check for a case where we have a PARALLEL of two independent
3833 SETs but we started with three insns. In this case, we can do the sets
3834 as two separate insns. This case occurs when some SET allows two
3835 other insns to combine, but the destination of that SET is still live.
3837 Also do this if we started with two insns and (at least) one of the
3838 resulting sets is a noop; this noop will be deleted later. */
3840 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3841 && GET_CODE (newpat
) == PARALLEL
3842 && XVECLEN (newpat
, 0) == 2
3843 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3844 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3845 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3846 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3847 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3848 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3849 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3850 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3851 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3852 XVECEXP (newpat
, 0, 0))
3853 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3854 XVECEXP (newpat
, 0, 1))
3855 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3856 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3858 rtx set0
= XVECEXP (newpat
, 0, 0);
3859 rtx set1
= XVECEXP (newpat
, 0, 1);
3861 /* Normally, it doesn't matter which of the two is done first,
3862 but the one that references cc0 can't be the second, and
3863 one which uses any regs/memory set in between i2 and i3 can't
3864 be first. The PARALLEL might also have been pre-existing in i3,
3865 so we need to make sure that we won't wrongly hoist a SET to i2
3866 that would conflict with a death note present in there. */
3867 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3868 && !(REG_P (SET_DEST (set1
))
3869 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3870 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3871 && find_reg_note (i2
, REG_DEAD
,
3872 SUBREG_REG (SET_DEST (set1
))))
3874 && !reg_referenced_p (cc0_rtx
, set0
)
3876 /* If I3 is a jump, ensure that set0 is a jump so that
3877 we do not create invalid RTL. */
3878 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3884 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3885 && !(REG_P (SET_DEST (set0
))
3886 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3887 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3888 && find_reg_note (i2
, REG_DEAD
,
3889 SUBREG_REG (SET_DEST (set0
))))
3891 && !reg_referenced_p (cc0_rtx
, set1
)
3893 /* If I3 is a jump, ensure that set1 is a jump so that
3894 we do not create invalid RTL. */
3895 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3907 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3909 if (i2_code_number
>= 0)
3911 /* recog_for_combine might have added CLOBBERs to newi2pat.
3912 Make sure NEWPAT does not depend on the clobbered regs. */
3913 if (GET_CODE (newi2pat
) == PARALLEL
)
3915 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3916 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3918 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3919 if (reg_overlap_mentioned_p (reg
, newpat
))
3927 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3931 /* If it still isn't recognized, fail and change things back the way they
3933 if ((insn_code_number
< 0
3934 /* Is the result a reasonable ASM_OPERANDS? */
3935 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3941 /* If we had to change another insn, make sure it is valid also. */
3942 if (undobuf
.other_insn
)
3944 CLEAR_HARD_REG_SET (newpat_used_regs
);
3946 other_pat
= PATTERN (undobuf
.other_insn
);
3947 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3950 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3958 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3959 they are adjacent to each other or not. */
3961 rtx_insn
*p
= prev_nonnote_insn (i3
);
3962 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3963 && sets_cc0_p (newi2pat
))
3971 /* Only allow this combination if insn_rtx_costs reports that the
3972 replacement instructions are cheaper than the originals. */
3973 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3979 if (MAY_HAVE_DEBUG_INSNS
)
3983 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3984 if (undo
->kind
== UNDO_MODE
)
3986 rtx reg
= *undo
->where
.r
;
3987 machine_mode new_mode
= GET_MODE (reg
);
3988 machine_mode old_mode
= undo
->old_contents
.m
;
3990 /* Temporarily revert mode back. */
3991 adjust_reg_mode (reg
, old_mode
);
3993 if (reg
== i2dest
&& i2scratch
)
3995 /* If we used i2dest as a scratch register with a
3996 different mode, substitute it for the original
3997 i2src while its original mode is temporarily
3998 restored, and then clear i2scratch so that we don't
3999 do it again later. */
4000 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4003 /* Put back the new mode. */
4004 adjust_reg_mode (reg
, new_mode
);
4008 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4009 rtx_insn
*first
, *last
;
4014 last
= last_combined_insn
;
4019 last
= undobuf
.other_insn
;
4021 if (DF_INSN_LUID (last
)
4022 < DF_INSN_LUID (last_combined_insn
))
4023 last
= last_combined_insn
;
4026 /* We're dealing with a reg that changed mode but not
4027 meaning, so we want to turn it into a subreg for
4028 the new mode. However, because of REG sharing and
4029 because its mode had already changed, we have to do
4030 it in two steps. First, replace any debug uses of
4031 reg, with its original mode temporarily restored,
4032 with this copy we have created; then, replace the
4033 copy with the SUBREG of the original shared reg,
4034 once again changed to the new mode. */
4035 propagate_for_debug (first
, last
, reg
, tempreg
,
4037 adjust_reg_mode (reg
, new_mode
);
4038 propagate_for_debug (first
, last
, tempreg
,
4039 lowpart_subreg (old_mode
, reg
, new_mode
),
4045 /* If we will be able to accept this, we have made a
4046 change to the destination of I3. This requires us to
4047 do a few adjustments. */
4049 if (changed_i3_dest
)
4051 PATTERN (i3
) = newpat
;
4052 adjust_for_new_dest (i3
);
4055 /* We now know that we can do this combination. Merge the insns and
4056 update the status of registers and LOG_LINKS. */
4058 if (undobuf
.other_insn
)
4062 PATTERN (undobuf
.other_insn
) = other_pat
;
4064 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4065 ensure that they are still valid. Then add any non-duplicate
4066 notes added by recog_for_combine. */
4067 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4069 next
= XEXP (note
, 1);
4071 if ((REG_NOTE_KIND (note
) == REG_DEAD
4072 && !reg_referenced_p (XEXP (note
, 0),
4073 PATTERN (undobuf
.other_insn
)))
4074 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4075 && !reg_set_p (XEXP (note
, 0),
4076 PATTERN (undobuf
.other_insn
))))
4077 remove_note (undobuf
.other_insn
, note
);
4080 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4081 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4088 struct insn_link
*link
;
4091 /* I3 now uses what used to be its destination and which is now
4092 I2's destination. This requires us to do a few adjustments. */
4093 PATTERN (i3
) = newpat
;
4094 adjust_for_new_dest (i3
);
4096 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4099 However, some later insn might be using I2's dest and have
4100 a LOG_LINK pointing at I3. We must remove this link.
4101 The simplest way to remove the link is to point it at I1,
4102 which we know will be a NOTE. */
4104 /* newi2pat is usually a SET here; however, recog_for_combine might
4105 have added some clobbers. */
4106 if (GET_CODE (newi2pat
) == PARALLEL
)
4107 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4109 ni2dest
= SET_DEST (newi2pat
);
4111 for (insn
= NEXT_INSN (i3
);
4112 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4113 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4114 insn
= NEXT_INSN (insn
))
4116 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4118 FOR_EACH_LOG_LINK (link
, insn
)
4119 if (link
->insn
== i3
)
4128 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4129 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4132 /* Compute which registers we expect to eliminate. newi2pat may be setting
4133 either i3dest or i2dest, so we must check it. */
4134 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4135 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4138 /* For i1, we need to compute both local elimination and global
4139 elimination information with respect to newi2pat because i1dest
4140 may be the same as i3dest, in which case newi2pat may be setting
4141 i1dest. Global information is used when distributing REG_DEAD
4142 note for i2 and i3, in which case it does matter if newi2pat sets
4145 Local information is used when distributing REG_DEAD note for i1,
4146 in which case it doesn't matter if newi2pat sets i1dest or not.
4147 See PR62151, if we have four insns combination:
4149 i1: r1 <- i1src (using r0)
4151 i2: r0 <- i2src (using r1)
4152 i3: r3 <- i3src (using r0)
4154 From i1's point of view, r0 is eliminated, no matter if it is set
4155 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4156 should be discarded.
4158 Note local information only affects cases in forms like "I1->I2->I3",
4159 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4160 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4162 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4165 rtx elim_i1
= (local_elim_i1
== 0
4166 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4168 /* Same case as i1. */
4169 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4171 rtx elim_i0
= (local_elim_i0
== 0
4172 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4175 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4177 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4178 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4180 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4182 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4184 /* Ensure that we do not have something that should not be shared but
4185 occurs multiple times in the new insns. Check this by first
4186 resetting all the `used' flags and then copying anything is shared. */
4188 reset_used_flags (i3notes
);
4189 reset_used_flags (i2notes
);
4190 reset_used_flags (i1notes
);
4191 reset_used_flags (i0notes
);
4192 reset_used_flags (newpat
);
4193 reset_used_flags (newi2pat
);
4194 if (undobuf
.other_insn
)
4195 reset_used_flags (PATTERN (undobuf
.other_insn
));
4197 i3notes
= copy_rtx_if_shared (i3notes
);
4198 i2notes
= copy_rtx_if_shared (i2notes
);
4199 i1notes
= copy_rtx_if_shared (i1notes
);
4200 i0notes
= copy_rtx_if_shared (i0notes
);
4201 newpat
= copy_rtx_if_shared (newpat
);
4202 newi2pat
= copy_rtx_if_shared (newi2pat
);
4203 if (undobuf
.other_insn
)
4204 reset_used_flags (PATTERN (undobuf
.other_insn
));
4206 INSN_CODE (i3
) = insn_code_number
;
4207 PATTERN (i3
) = newpat
;
4209 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4211 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4213 reset_used_flags (call_usage
);
4214 call_usage
= copy_rtx (call_usage
);
4218 /* I2SRC must still be meaningful at this point. Some splitting
4219 operations can invalidate I2SRC, but those operations do not
4222 replace_rtx (call_usage
, i2dest
, i2src
);
4226 replace_rtx (call_usage
, i1dest
, i1src
);
4228 replace_rtx (call_usage
, i0dest
, i0src
);
4230 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4233 if (undobuf
.other_insn
)
4234 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4236 /* We had one special case above where I2 had more than one set and
4237 we replaced a destination of one of those sets with the destination
4238 of I3. In that case, we have to update LOG_LINKS of insns later
4239 in this basic block. Note that this (expensive) case is rare.
4241 Also, in this case, we must pretend that all REG_NOTEs for I2
4242 actually came from I3, so that REG_UNUSED notes from I2 will be
4243 properly handled. */
4245 if (i3_subst_into_i2
)
4247 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4248 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4249 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4250 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4251 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4252 && ! find_reg_note (i2
, REG_UNUSED
,
4253 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4254 for (temp_insn
= NEXT_INSN (i2
);
4256 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4257 || BB_HEAD (this_basic_block
) != temp_insn
);
4258 temp_insn
= NEXT_INSN (temp_insn
))
4259 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4260 FOR_EACH_LOG_LINK (link
, temp_insn
)
4261 if (link
->insn
== i2
)
4267 while (XEXP (link
, 1))
4268 link
= XEXP (link
, 1);
4269 XEXP (link
, 1) = i2notes
;
4276 LOG_LINKS (i3
) = NULL
;
4278 LOG_LINKS (i2
) = NULL
;
4283 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4284 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4286 INSN_CODE (i2
) = i2_code_number
;
4287 PATTERN (i2
) = newi2pat
;
4291 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4292 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4294 SET_INSN_DELETED (i2
);
4299 LOG_LINKS (i1
) = NULL
;
4301 if (MAY_HAVE_DEBUG_INSNS
)
4302 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4304 SET_INSN_DELETED (i1
);
4309 LOG_LINKS (i0
) = NULL
;
4311 if (MAY_HAVE_DEBUG_INSNS
)
4312 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4314 SET_INSN_DELETED (i0
);
4317 /* Get death notes for everything that is now used in either I3 or
4318 I2 and used to die in a previous insn. If we built two new
4319 patterns, move from I1 to I2 then I2 to I3 so that we get the
4320 proper movement on registers that I2 modifies. */
4323 from_luid
= DF_INSN_LUID (i0
);
4325 from_luid
= DF_INSN_LUID (i1
);
4327 from_luid
= DF_INSN_LUID (i2
);
4329 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4330 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4332 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4334 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4335 elim_i2
, elim_i1
, elim_i0
);
4337 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4338 elim_i2
, elim_i1
, elim_i0
);
4340 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4341 elim_i2
, local_elim_i1
, local_elim_i0
);
4343 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4344 elim_i2
, elim_i1
, local_elim_i0
);
4346 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4347 elim_i2
, elim_i1
, elim_i0
);
4349 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4350 know these are REG_UNUSED and want them to go to the desired insn,
4351 so we always pass it as i3. */
4353 if (newi2pat
&& new_i2_notes
)
4354 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4358 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4361 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4362 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4363 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4364 in that case, it might delete I2. Similarly for I2 and I1.
4365 Show an additional death due to the REG_DEAD note we make here. If
4366 we discard it in distribute_notes, we will decrement it again. */
4370 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4371 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4372 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4375 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4376 elim_i2
, elim_i1
, elim_i0
);
4379 if (i2dest_in_i2src
)
4381 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4382 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4383 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4384 NULL_RTX
, NULL_RTX
);
4386 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4387 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4390 if (i1dest_in_i1src
)
4392 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4393 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4394 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4395 NULL_RTX
, NULL_RTX
);
4397 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4398 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4401 if (i0dest_in_i0src
)
4403 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4404 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4405 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4406 NULL_RTX
, NULL_RTX
);
4408 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4409 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4412 distribute_links (i3links
);
4413 distribute_links (i2links
);
4414 distribute_links (i1links
);
4415 distribute_links (i0links
);
4419 struct insn_link
*link
;
4420 rtx_insn
*i2_insn
= 0;
4421 rtx i2_val
= 0, set
;
4423 /* The insn that used to set this register doesn't exist, and
4424 this life of the register may not exist either. See if one of
4425 I3's links points to an insn that sets I2DEST. If it does,
4426 that is now the last known value for I2DEST. If we don't update
4427 this and I2 set the register to a value that depended on its old
4428 contents, we will get confused. If this insn is used, thing
4429 will be set correctly in combine_instructions. */
4430 FOR_EACH_LOG_LINK (link
, i3
)
4431 if ((set
= single_set (link
->insn
)) != 0
4432 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4433 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4435 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4437 /* If the reg formerly set in I2 died only once and that was in I3,
4438 zero its use count so it won't make `reload' do any work. */
4440 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4441 && ! i2dest_in_i2src
)
4442 INC_REG_N_SETS (REGNO (i2dest
), -1);
4445 if (i1
&& REG_P (i1dest
))
4447 struct insn_link
*link
;
4448 rtx_insn
*i1_insn
= 0;
4449 rtx i1_val
= 0, set
;
4451 FOR_EACH_LOG_LINK (link
, i3
)
4452 if ((set
= single_set (link
->insn
)) != 0
4453 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4454 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4456 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4458 if (! added_sets_1
&& ! i1dest_in_i1src
)
4459 INC_REG_N_SETS (REGNO (i1dest
), -1);
4462 if (i0
&& REG_P (i0dest
))
4464 struct insn_link
*link
;
4465 rtx_insn
*i0_insn
= 0;
4466 rtx i0_val
= 0, set
;
4468 FOR_EACH_LOG_LINK (link
, i3
)
4469 if ((set
= single_set (link
->insn
)) != 0
4470 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4471 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4473 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4475 if (! added_sets_0
&& ! i0dest_in_i0src
)
4476 INC_REG_N_SETS (REGNO (i0dest
), -1);
4479 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4480 been made to this insn. The order is important, because newi2pat
4481 can affect nonzero_bits of newpat. */
4483 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4484 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4487 if (undobuf
.other_insn
!= NULL_RTX
)
4491 fprintf (dump_file
, "modifying other_insn ");
4492 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4494 df_insn_rescan (undobuf
.other_insn
);
4497 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4501 fprintf (dump_file
, "modifying insn i0 ");
4502 dump_insn_slim (dump_file
, i0
);
4504 df_insn_rescan (i0
);
4507 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4511 fprintf (dump_file
, "modifying insn i1 ");
4512 dump_insn_slim (dump_file
, i1
);
4514 df_insn_rescan (i1
);
4517 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4521 fprintf (dump_file
, "modifying insn i2 ");
4522 dump_insn_slim (dump_file
, i2
);
4524 df_insn_rescan (i2
);
4527 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4531 fprintf (dump_file
, "modifying insn i3 ");
4532 dump_insn_slim (dump_file
, i3
);
4534 df_insn_rescan (i3
);
4537 /* Set new_direct_jump_p if a new return or simple jump instruction
4538 has been created. Adjust the CFG accordingly. */
4539 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4541 *new_direct_jump_p
= 1;
4542 mark_jump_label (PATTERN (i3
), i3
, 0);
4543 update_cfg_for_uncondjump (i3
);
4546 if (undobuf
.other_insn
!= NULL_RTX
4547 && (returnjump_p (undobuf
.other_insn
)
4548 || any_uncondjump_p (undobuf
.other_insn
)))
4550 *new_direct_jump_p
= 1;
4551 update_cfg_for_uncondjump (undobuf
.other_insn
);
4554 /* A noop might also need cleaning up of CFG, if it comes from the
4555 simplification of a jump. */
4557 && GET_CODE (newpat
) == SET
4558 && SET_SRC (newpat
) == pc_rtx
4559 && SET_DEST (newpat
) == pc_rtx
)
4561 *new_direct_jump_p
= 1;
4562 update_cfg_for_uncondjump (i3
);
4565 if (undobuf
.other_insn
!= NULL_RTX
4566 && JUMP_P (undobuf
.other_insn
)
4567 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4568 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4569 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4571 *new_direct_jump_p
= 1;
4572 update_cfg_for_uncondjump (undobuf
.other_insn
);
4575 combine_successes
++;
4578 if (added_links_insn
4579 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4580 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4581 return added_links_insn
;
4583 return newi2pat
? i2
: i3
;
4586 /* Undo all the modifications recorded in undobuf. */
4591 struct undo
*undo
, *next
;
4593 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4599 *undo
->where
.r
= undo
->old_contents
.r
;
4602 *undo
->where
.i
= undo
->old_contents
.i
;
4605 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4608 *undo
->where
.l
= undo
->old_contents
.l
;
4614 undo
->next
= undobuf
.frees
;
4615 undobuf
.frees
= undo
;
4621 /* We've committed to accepting the changes we made. Move all
4622 of the undos to the free list. */
4627 struct undo
*undo
, *next
;
4629 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4632 undo
->next
= undobuf
.frees
;
4633 undobuf
.frees
= undo
;
4638 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4639 where we have an arithmetic expression and return that point. LOC will
4642 try_combine will call this function to see if an insn can be split into
4646 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4649 enum rtx_code code
= GET_CODE (x
);
4651 unsigned HOST_WIDE_INT len
= 0;
4652 HOST_WIDE_INT pos
= 0;
4654 rtx inner
= NULL_RTX
;
4656 /* First special-case some codes. */
4660 #ifdef INSN_SCHEDULING
4661 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4663 if (MEM_P (SUBREG_REG (x
)))
4666 return find_split_point (&SUBREG_REG (x
), insn
, false);
4670 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4671 using LO_SUM and HIGH. */
4672 if (GET_CODE (XEXP (x
, 0)) == CONST
4673 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4675 machine_mode address_mode
= get_address_mode (x
);
4678 gen_rtx_LO_SUM (address_mode
,
4679 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4681 return &XEXP (XEXP (x
, 0), 0);
4685 /* If we have a PLUS whose second operand is a constant and the
4686 address is not valid, perhaps will can split it up using
4687 the machine-specific way to split large constants. We use
4688 the first pseudo-reg (one of the virtual regs) as a placeholder;
4689 it will not remain in the result. */
4690 if (GET_CODE (XEXP (x
, 0)) == PLUS
4691 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4692 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4693 MEM_ADDR_SPACE (x
)))
4695 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4696 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4700 /* This should have produced two insns, each of which sets our
4701 placeholder. If the source of the second is a valid address,
4702 we can make put both sources together and make a split point
4706 && NEXT_INSN (seq
) != NULL_RTX
4707 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4708 && NONJUMP_INSN_P (seq
)
4709 && GET_CODE (PATTERN (seq
)) == SET
4710 && SET_DEST (PATTERN (seq
)) == reg
4711 && ! reg_mentioned_p (reg
,
4712 SET_SRC (PATTERN (seq
)))
4713 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4714 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4715 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4716 && memory_address_addr_space_p
4717 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4718 MEM_ADDR_SPACE (x
)))
4720 rtx src1
= SET_SRC (PATTERN (seq
));
4721 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4723 /* Replace the placeholder in SRC2 with SRC1. If we can
4724 find where in SRC2 it was placed, that can become our
4725 split point and we can replace this address with SRC2.
4726 Just try two obvious places. */
4728 src2
= replace_rtx (src2
, reg
, src1
);
4730 if (XEXP (src2
, 0) == src1
)
4731 split
= &XEXP (src2
, 0);
4732 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4733 && XEXP (XEXP (src2
, 0), 0) == src1
)
4734 split
= &XEXP (XEXP (src2
, 0), 0);
4738 SUBST (XEXP (x
, 0), src2
);
4743 /* If that didn't work, perhaps the first operand is complex and
4744 needs to be computed separately, so make a split point there.
4745 This will occur on machines that just support REG + CONST
4746 and have a constant moved through some previous computation. */
4748 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4749 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4750 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4751 return &XEXP (XEXP (x
, 0), 0);
4754 /* If we have a PLUS whose first operand is complex, try computing it
4755 separately by making a split there. */
4756 if (GET_CODE (XEXP (x
, 0)) == PLUS
4757 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4759 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4760 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4761 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4762 return &XEXP (XEXP (x
, 0), 0);
4767 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4768 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4769 we need to put the operand into a register. So split at that
4772 if (SET_DEST (x
) == cc0_rtx
4773 && GET_CODE (SET_SRC (x
)) != COMPARE
4774 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4775 && !OBJECT_P (SET_SRC (x
))
4776 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4777 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4778 return &SET_SRC (x
);
4781 /* See if we can split SET_SRC as it stands. */
4782 split
= find_split_point (&SET_SRC (x
), insn
, true);
4783 if (split
&& split
!= &SET_SRC (x
))
4786 /* See if we can split SET_DEST as it stands. */
4787 split
= find_split_point (&SET_DEST (x
), insn
, false);
4788 if (split
&& split
!= &SET_DEST (x
))
4791 /* See if this is a bitfield assignment with everything constant. If
4792 so, this is an IOR of an AND, so split it into that. */
4793 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4794 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4795 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4796 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4797 && CONST_INT_P (SET_SRC (x
))
4798 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4799 + INTVAL (XEXP (SET_DEST (x
), 2)))
4800 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4801 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4803 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4804 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4805 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4806 rtx dest
= XEXP (SET_DEST (x
), 0);
4807 machine_mode mode
= GET_MODE (dest
);
4808 unsigned HOST_WIDE_INT mask
4809 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4812 if (BITS_BIG_ENDIAN
)
4813 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4815 or_mask
= gen_int_mode (src
<< pos
, mode
);
4818 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4821 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4823 simplify_gen_binary (IOR
, mode
,
4824 simplify_gen_binary (AND
, mode
,
4829 SUBST (SET_DEST (x
), dest
);
4831 split
= find_split_point (&SET_SRC (x
), insn
, true);
4832 if (split
&& split
!= &SET_SRC (x
))
4836 /* Otherwise, see if this is an operation that we can split into two.
4837 If so, try to split that. */
4838 code
= GET_CODE (SET_SRC (x
));
4843 /* If we are AND'ing with a large constant that is only a single
4844 bit and the result is only being used in a context where we
4845 need to know if it is zero or nonzero, replace it with a bit
4846 extraction. This will avoid the large constant, which might
4847 have taken more than one insn to make. If the constant were
4848 not a valid argument to the AND but took only one insn to make,
4849 this is no worse, but if it took more than one insn, it will
4852 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4853 && REG_P (XEXP (SET_SRC (x
), 0))
4854 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4855 && REG_P (SET_DEST (x
))
4856 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4857 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4858 && XEXP (*split
, 0) == SET_DEST (x
)
4859 && XEXP (*split
, 1) == const0_rtx
)
4861 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4862 XEXP (SET_SRC (x
), 0),
4863 pos
, NULL_RTX
, 1, 1, 0, 0);
4864 if (extraction
!= 0)
4866 SUBST (SET_SRC (x
), extraction
);
4867 return find_split_point (loc
, insn
, false);
4873 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4874 is known to be on, this can be converted into a NEG of a shift. */
4875 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4876 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4877 && 1 <= (pos
= exact_log2
4878 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4879 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4881 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4885 gen_rtx_LSHIFTRT (mode
,
4886 XEXP (SET_SRC (x
), 0),
4889 split
= find_split_point (&SET_SRC (x
), insn
, true);
4890 if (split
&& split
!= &SET_SRC (x
))
4896 inner
= XEXP (SET_SRC (x
), 0);
4898 /* We can't optimize if either mode is a partial integer
4899 mode as we don't know how many bits are significant
4901 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4902 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4906 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4912 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4913 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4915 inner
= XEXP (SET_SRC (x
), 0);
4916 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4917 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4919 if (BITS_BIG_ENDIAN
)
4920 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4921 unsignedp
= (code
== ZERO_EXTRACT
);
4930 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4932 machine_mode mode
= GET_MODE (SET_SRC (x
));
4934 /* For unsigned, we have a choice of a shift followed by an
4935 AND or two shifts. Use two shifts for field sizes where the
4936 constant might be too large. We assume here that we can
4937 always at least get 8-bit constants in an AND insn, which is
4938 true for every current RISC. */
4940 if (unsignedp
&& len
<= 8)
4942 unsigned HOST_WIDE_INT mask
4943 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4947 (mode
, gen_lowpart (mode
, inner
),
4949 gen_int_mode (mask
, mode
)));
4951 split
= find_split_point (&SET_SRC (x
), insn
, true);
4952 if (split
&& split
!= &SET_SRC (x
))
4959 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4960 gen_rtx_ASHIFT (mode
,
4961 gen_lowpart (mode
, inner
),
4962 GEN_INT (GET_MODE_PRECISION (mode
)
4964 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4966 split
= find_split_point (&SET_SRC (x
), insn
, true);
4967 if (split
&& split
!= &SET_SRC (x
))
4972 /* See if this is a simple operation with a constant as the second
4973 operand. It might be that this constant is out of range and hence
4974 could be used as a split point. */
4975 if (BINARY_P (SET_SRC (x
))
4976 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4977 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4978 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4979 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4980 return &XEXP (SET_SRC (x
), 1);
4982 /* Finally, see if this is a simple operation with its first operand
4983 not in a register. The operation might require this operand in a
4984 register, so return it as a split point. We can always do this
4985 because if the first operand were another operation, we would have
4986 already found it as a split point. */
4987 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4988 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4989 return &XEXP (SET_SRC (x
), 0);
4995 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4996 it is better to write this as (not (ior A B)) so we can split it.
4997 Similarly for IOR. */
4998 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5001 gen_rtx_NOT (GET_MODE (x
),
5002 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5004 XEXP (XEXP (x
, 0), 0),
5005 XEXP (XEXP (x
, 1), 0))));
5006 return find_split_point (loc
, insn
, set_src
);
5009 /* Many RISC machines have a large set of logical insns. If the
5010 second operand is a NOT, put it first so we will try to split the
5011 other operand first. */
5012 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5014 rtx tem
= XEXP (x
, 0);
5015 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5016 SUBST (XEXP (x
, 1), tem
);
5022 /* Canonicalization can produce (minus A (mult B C)), where C is a
5023 constant. It may be better to try splitting (plus (mult B -C) A)
5024 instead if this isn't a multiply by a power of two. */
5025 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5026 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5027 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5029 machine_mode mode
= GET_MODE (x
);
5030 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5031 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5032 SUBST (*loc
, gen_rtx_PLUS (mode
,
5034 XEXP (XEXP (x
, 1), 0),
5035 gen_int_mode (other_int
,
5038 return find_split_point (loc
, insn
, set_src
);
5041 /* Split at a multiply-accumulate instruction. However if this is
5042 the SET_SRC, we likely do not have such an instruction and it's
5043 worthless to try this split. */
5044 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
5051 /* Otherwise, select our actions depending on our rtx class. */
5052 switch (GET_RTX_CLASS (code
))
5054 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5056 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5059 /* ... fall through ... */
5061 case RTX_COMM_ARITH
:
5063 case RTX_COMM_COMPARE
:
5064 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5067 /* ... fall through ... */
5069 /* Some machines have (and (shift ...) ...) insns. If X is not
5070 an AND, but XEXP (X, 0) is, use it as our split point. */
5071 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5072 return &XEXP (x
, 0);
5074 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5080 /* Otherwise, we don't have a split point. */
5085 /* Throughout X, replace FROM with TO, and return the result.
5086 The result is TO if X is FROM;
5087 otherwise the result is X, but its contents may have been modified.
5088 If they were modified, a record was made in undobuf so that
5089 undo_all will (among other things) return X to its original state.
5091 If the number of changes necessary is too much to record to undo,
5092 the excess changes are not made, so the result is invalid.
5093 The changes already made can still be undone.
5094 undobuf.num_undo is incremented for such changes, so by testing that
5095 the caller can tell whether the result is valid.
5097 `n_occurrences' is incremented each time FROM is replaced.
5099 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5101 IN_COND is nonzero if we are at the top level of a condition.
5103 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5104 by copying if `n_occurrences' is nonzero. */
5107 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5109 enum rtx_code code
= GET_CODE (x
);
5110 machine_mode op0_mode
= VOIDmode
;
5115 /* Two expressions are equal if they are identical copies of a shared
5116 RTX or if they are both registers with the same register number
5119 #define COMBINE_RTX_EQUAL_P(X,Y) \
5121 || (REG_P (X) && REG_P (Y) \
5122 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5124 /* Do not substitute into clobbers of regs -- this will never result in
5126 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5129 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5132 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5135 /* If X and FROM are the same register but different modes, they
5136 will not have been seen as equal above. However, the log links code
5137 will make a LOG_LINKS entry for that case. If we do nothing, we
5138 will try to rerecognize our original insn and, when it succeeds,
5139 we will delete the feeding insn, which is incorrect.
5141 So force this insn not to match in this (rare) case. */
5142 if (! in_dest
&& code
== REG
&& REG_P (from
)
5143 && reg_overlap_mentioned_p (x
, from
))
5144 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5146 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5147 of which may contain things that can be combined. */
5148 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5151 /* It is possible to have a subexpression appear twice in the insn.
5152 Suppose that FROM is a register that appears within TO.
5153 Then, after that subexpression has been scanned once by `subst',
5154 the second time it is scanned, TO may be found. If we were
5155 to scan TO here, we would find FROM within it and create a
5156 self-referent rtl structure which is completely wrong. */
5157 if (COMBINE_RTX_EQUAL_P (x
, to
))
5160 /* Parallel asm_operands need special attention because all of the
5161 inputs are shared across the arms. Furthermore, unsharing the
5162 rtl results in recognition failures. Failure to handle this case
5163 specially can result in circular rtl.
5165 Solve this by doing a normal pass across the first entry of the
5166 parallel, and only processing the SET_DESTs of the subsequent
5169 if (code
== PARALLEL
5170 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5171 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5173 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5175 /* If this substitution failed, this whole thing fails. */
5176 if (GET_CODE (new_rtx
) == CLOBBER
5177 && XEXP (new_rtx
, 0) == const0_rtx
)
5180 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5182 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5184 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5187 && GET_CODE (dest
) != CC0
5188 && GET_CODE (dest
) != PC
)
5190 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5192 /* If this substitution failed, this whole thing fails. */
5193 if (GET_CODE (new_rtx
) == CLOBBER
5194 && XEXP (new_rtx
, 0) == const0_rtx
)
5197 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5203 len
= GET_RTX_LENGTH (code
);
5204 fmt
= GET_RTX_FORMAT (code
);
5206 /* We don't need to process a SET_DEST that is a register, CC0,
5207 or PC, so set up to skip this common case. All other cases
5208 where we want to suppress replacing something inside a
5209 SET_SRC are handled via the IN_DEST operand. */
5211 && (REG_P (SET_DEST (x
))
5212 || GET_CODE (SET_DEST (x
)) == CC0
5213 || GET_CODE (SET_DEST (x
)) == PC
))
5216 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5219 op0_mode
= GET_MODE (XEXP (x
, 0));
5221 for (i
= 0; i
< len
; i
++)
5226 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5228 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5230 new_rtx
= (unique_copy
&& n_occurrences
5231 ? copy_rtx (to
) : to
);
5236 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5239 /* If this substitution failed, this whole thing
5241 if (GET_CODE (new_rtx
) == CLOBBER
5242 && XEXP (new_rtx
, 0) == const0_rtx
)
5246 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5249 else if (fmt
[i
] == 'e')
5251 /* If this is a register being set, ignore it. */
5252 new_rtx
= XEXP (x
, i
);
5255 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5257 || code
== STRICT_LOW_PART
))
5260 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5262 /* In general, don't install a subreg involving two
5263 modes not tieable. It can worsen register
5264 allocation, and can even make invalid reload
5265 insns, since the reg inside may need to be copied
5266 from in the outside mode, and that may be invalid
5267 if it is an fp reg copied in integer mode.
5269 We allow two exceptions to this: It is valid if
5270 it is inside another SUBREG and the mode of that
5271 SUBREG and the mode of the inside of TO is
5272 tieable and it is valid if X is a SET that copies
5275 if (GET_CODE (to
) == SUBREG
5276 && ! MODES_TIEABLE_P (GET_MODE (to
),
5277 GET_MODE (SUBREG_REG (to
)))
5278 && ! (code
== SUBREG
5279 && MODES_TIEABLE_P (GET_MODE (x
),
5280 GET_MODE (SUBREG_REG (to
))))
5282 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5285 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5289 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5290 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5293 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5295 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5299 /* If we are in a SET_DEST, suppress most cases unless we
5300 have gone inside a MEM, in which case we want to
5301 simplify the address. We assume here that things that
5302 are actually part of the destination have their inner
5303 parts in the first expression. This is true for SUBREG,
5304 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5305 things aside from REG and MEM that should appear in a
5307 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5309 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5310 || code
== ZERO_EXTRACT
))
5313 code
== IF_THEN_ELSE
&& i
== 0,
5316 /* If we found that we will have to reject this combination,
5317 indicate that by returning the CLOBBER ourselves, rather than
5318 an expression containing it. This will speed things up as
5319 well as prevent accidents where two CLOBBERs are considered
5320 to be equal, thus producing an incorrect simplification. */
5322 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5325 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5327 machine_mode mode
= GET_MODE (x
);
5329 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5330 GET_MODE (SUBREG_REG (x
)),
5333 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5335 else if (CONST_SCALAR_INT_P (new_rtx
)
5336 && GET_CODE (x
) == ZERO_EXTEND
)
5338 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5339 new_rtx
, GET_MODE (XEXP (x
, 0)));
5343 SUBST (XEXP (x
, i
), new_rtx
);
5348 /* Check if we are loading something from the constant pool via float
5349 extension; in this case we would undo compress_float_constant
5350 optimization and degenerate constant load to an immediate value. */
5351 if (GET_CODE (x
) == FLOAT_EXTEND
5352 && MEM_P (XEXP (x
, 0))
5353 && MEM_READONLY_P (XEXP (x
, 0)))
5355 rtx tmp
= avoid_constant_pool_reference (x
);
5360 /* Try to simplify X. If the simplification changed the code, it is likely
5361 that further simplification will help, so loop, but limit the number
5362 of repetitions that will be performed. */
5364 for (i
= 0; i
< 4; i
++)
5366 /* If X is sufficiently simple, don't bother trying to do anything
5368 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5369 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5371 if (GET_CODE (x
) == code
)
5374 code
= GET_CODE (x
);
5376 /* We no longer know the original mode of operand 0 since we
5377 have changed the form of X) */
5378 op0_mode
= VOIDmode
;
5384 /* Simplify X, a piece of RTL. We just operate on the expression at the
5385 outer level; call `subst' to simplify recursively. Return the new
5388 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5389 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5393 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5396 enum rtx_code code
= GET_CODE (x
);
5397 machine_mode mode
= GET_MODE (x
);
5401 /* If this is a commutative operation, put a constant last and a complex
5402 expression first. We don't need to do this for comparisons here. */
5403 if (COMMUTATIVE_ARITH_P (x
)
5404 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5407 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5408 SUBST (XEXP (x
, 1), temp
);
5411 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5412 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5413 things. Check for cases where both arms are testing the same
5416 Don't do anything if all operands are very simple. */
5419 && ((!OBJECT_P (XEXP (x
, 0))
5420 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5421 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5422 || (!OBJECT_P (XEXP (x
, 1))
5423 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5424 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5426 && (!OBJECT_P (XEXP (x
, 0))
5427 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5428 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5430 rtx cond
, true_rtx
, false_rtx
;
5432 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5434 /* If everything is a comparison, what we have is highly unlikely
5435 to be simpler, so don't use it. */
5436 && ! (COMPARISON_P (x
)
5437 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5439 rtx cop1
= const0_rtx
;
5440 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5442 if (cond_code
== NE
&& COMPARISON_P (cond
))
5445 /* Simplify the alternative arms; this may collapse the true and
5446 false arms to store-flag values. Be careful to use copy_rtx
5447 here since true_rtx or false_rtx might share RTL with x as a
5448 result of the if_then_else_cond call above. */
5449 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5450 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5452 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5453 is unlikely to be simpler. */
5454 if (general_operand (true_rtx
, VOIDmode
)
5455 && general_operand (false_rtx
, VOIDmode
))
5457 enum rtx_code reversed
;
5459 /* Restarting if we generate a store-flag expression will cause
5460 us to loop. Just drop through in this case. */
5462 /* If the result values are STORE_FLAG_VALUE and zero, we can
5463 just make the comparison operation. */
5464 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5465 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5467 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5468 && ((reversed
= reversed_comparison_code_parts
5469 (cond_code
, cond
, cop1
, NULL
))
5471 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5474 /* Likewise, we can make the negate of a comparison operation
5475 if the result values are - STORE_FLAG_VALUE and zero. */
5476 else if (CONST_INT_P (true_rtx
)
5477 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5478 && false_rtx
== const0_rtx
)
5479 x
= simplify_gen_unary (NEG
, mode
,
5480 simplify_gen_relational (cond_code
,
5484 else if (CONST_INT_P (false_rtx
)
5485 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5486 && true_rtx
== const0_rtx
5487 && ((reversed
= reversed_comparison_code_parts
5488 (cond_code
, cond
, cop1
, NULL
))
5490 x
= simplify_gen_unary (NEG
, mode
,
5491 simplify_gen_relational (reversed
,
5496 return gen_rtx_IF_THEN_ELSE (mode
,
5497 simplify_gen_relational (cond_code
,
5502 true_rtx
, false_rtx
);
5504 code
= GET_CODE (x
);
5505 op0_mode
= VOIDmode
;
5510 /* Try to fold this expression in case we have constants that weren't
5513 switch (GET_RTX_CLASS (code
))
5516 if (op0_mode
== VOIDmode
)
5517 op0_mode
= GET_MODE (XEXP (x
, 0));
5518 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5521 case RTX_COMM_COMPARE
:
5523 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5524 if (cmp_mode
== VOIDmode
)
5526 cmp_mode
= GET_MODE (XEXP (x
, 1));
5527 if (cmp_mode
== VOIDmode
)
5528 cmp_mode
= op0_mode
;
5530 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5531 XEXP (x
, 0), XEXP (x
, 1));
5534 case RTX_COMM_ARITH
:
5536 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5538 case RTX_BITFIELD_OPS
:
5540 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5541 XEXP (x
, 1), XEXP (x
, 2));
5550 code
= GET_CODE (temp
);
5551 op0_mode
= VOIDmode
;
5552 mode
= GET_MODE (temp
);
5555 /* First see if we can apply the inverse distributive law. */
5556 if (code
== PLUS
|| code
== MINUS
5557 || code
== AND
|| code
== IOR
|| code
== XOR
)
5559 x
= apply_distributive_law (x
);
5560 code
= GET_CODE (x
);
5561 op0_mode
= VOIDmode
;
5564 /* If CODE is an associative operation not otherwise handled, see if we
5565 can associate some operands. This can win if they are constants or
5566 if they are logically related (i.e. (a & b) & a). */
5567 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5568 || code
== AND
|| code
== IOR
|| code
== XOR
5569 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5570 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5571 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5573 if (GET_CODE (XEXP (x
, 0)) == code
)
5575 rtx other
= XEXP (XEXP (x
, 0), 0);
5576 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5577 rtx inner_op1
= XEXP (x
, 1);
5580 /* Make sure we pass the constant operand if any as the second
5581 one if this is a commutative operation. */
5582 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5584 rtx tem
= inner_op0
;
5585 inner_op0
= inner_op1
;
5588 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5589 : code
== DIV
? MULT
5591 mode
, inner_op0
, inner_op1
);
5593 /* For commutative operations, try the other pair if that one
5595 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5597 other
= XEXP (XEXP (x
, 0), 1);
5598 inner
= simplify_binary_operation (code
, mode
,
5599 XEXP (XEXP (x
, 0), 0),
5604 return simplify_gen_binary (code
, mode
, other
, inner
);
5608 /* A little bit of algebraic simplification here. */
5612 /* Ensure that our address has any ASHIFTs converted to MULT in case
5613 address-recognizing predicates are called later. */
5614 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5615 SUBST (XEXP (x
, 0), temp
);
5619 if (op0_mode
== VOIDmode
)
5620 op0_mode
= GET_MODE (SUBREG_REG (x
));
5622 /* See if this can be moved to simplify_subreg. */
5623 if (CONSTANT_P (SUBREG_REG (x
))
5624 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5625 /* Don't call gen_lowpart if the inner mode
5626 is VOIDmode and we cannot simplify it, as SUBREG without
5627 inner mode is invalid. */
5628 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5629 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5630 return gen_lowpart (mode
, SUBREG_REG (x
));
5632 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5636 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5641 /* If op is known to have all lower bits zero, the result is zero. */
5643 && SCALAR_INT_MODE_P (mode
)
5644 && SCALAR_INT_MODE_P (op0_mode
)
5645 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5646 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5647 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5648 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5649 & GET_MODE_MASK (mode
)) == 0)
5650 return CONST0_RTX (mode
);
5653 /* Don't change the mode of the MEM if that would change the meaning
5655 if (MEM_P (SUBREG_REG (x
))
5656 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5657 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5658 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5659 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5661 /* Note that we cannot do any narrowing for non-constants since
5662 we might have been counting on using the fact that some bits were
5663 zero. We now do this in the SET. */
5668 temp
= expand_compound_operation (XEXP (x
, 0));
5670 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5671 replaced by (lshiftrt X C). This will convert
5672 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5674 if (GET_CODE (temp
) == ASHIFTRT
5675 && CONST_INT_P (XEXP (temp
, 1))
5676 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5677 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5678 INTVAL (XEXP (temp
, 1)));
5680 /* If X has only a single bit that might be nonzero, say, bit I, convert
5681 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5682 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5683 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5684 or a SUBREG of one since we'd be making the expression more
5685 complex if it was just a register. */
5688 && ! (GET_CODE (temp
) == SUBREG
5689 && REG_P (SUBREG_REG (temp
)))
5690 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5692 rtx temp1
= simplify_shift_const
5693 (NULL_RTX
, ASHIFTRT
, mode
,
5694 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5695 GET_MODE_PRECISION (mode
) - 1 - i
),
5696 GET_MODE_PRECISION (mode
) - 1 - i
);
5698 /* If all we did was surround TEMP with the two shifts, we
5699 haven't improved anything, so don't use it. Otherwise,
5700 we are better off with TEMP1. */
5701 if (GET_CODE (temp1
) != ASHIFTRT
5702 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5703 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5709 /* We can't handle truncation to a partial integer mode here
5710 because we don't know the real bitsize of the partial
5712 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5715 if (HWI_COMPUTABLE_MODE_P (mode
))
5717 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5718 GET_MODE_MASK (mode
), 0));
5720 /* We can truncate a constant value and return it. */
5721 if (CONST_INT_P (XEXP (x
, 0)))
5722 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5724 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5725 whose value is a comparison can be replaced with a subreg if
5726 STORE_FLAG_VALUE permits. */
5727 if (HWI_COMPUTABLE_MODE_P (mode
)
5728 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5729 && (temp
= get_last_value (XEXP (x
, 0)))
5730 && COMPARISON_P (temp
))
5731 return gen_lowpart (mode
, XEXP (x
, 0));
5735 /* (const (const X)) can become (const X). Do it this way rather than
5736 returning the inner CONST since CONST can be shared with a
5738 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5739 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5744 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5745 can add in an offset. find_split_point will split this address up
5746 again if it doesn't match. */
5747 if (GET_CODE (XEXP (x
, 0)) == HIGH
5748 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5754 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5755 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5756 bit-field and can be replaced by either a sign_extend or a
5757 sign_extract. The `and' may be a zero_extend and the two
5758 <c>, -<c> constants may be reversed. */
5759 if (GET_CODE (XEXP (x
, 0)) == XOR
5760 && CONST_INT_P (XEXP (x
, 1))
5761 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5762 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5763 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5764 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5765 && HWI_COMPUTABLE_MODE_P (mode
)
5766 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5767 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5768 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5769 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5770 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5771 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5772 == (unsigned int) i
+ 1))))
5773 return simplify_shift_const
5774 (NULL_RTX
, ASHIFTRT
, mode
,
5775 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5776 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5777 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5778 GET_MODE_PRECISION (mode
) - (i
+ 1));
5780 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5781 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5782 the bitsize of the mode - 1. This allows simplification of
5783 "a = (b & 8) == 0;" */
5784 if (XEXP (x
, 1) == constm1_rtx
5785 && !REG_P (XEXP (x
, 0))
5786 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5787 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5788 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5789 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5790 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5791 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5792 GET_MODE_PRECISION (mode
) - 1),
5793 GET_MODE_PRECISION (mode
) - 1);
5795 /* If we are adding two things that have no bits in common, convert
5796 the addition into an IOR. This will often be further simplified,
5797 for example in cases like ((a & 1) + (a & 2)), which can
5800 if (HWI_COMPUTABLE_MODE_P (mode
)
5801 && (nonzero_bits (XEXP (x
, 0), mode
)
5802 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5804 /* Try to simplify the expression further. */
5805 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5806 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5808 /* If we could, great. If not, do not go ahead with the IOR
5809 replacement, since PLUS appears in many special purpose
5810 address arithmetic instructions. */
5811 if (GET_CODE (temp
) != CLOBBER
5812 && (GET_CODE (temp
) != IOR
5813 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5814 || XEXP (temp
, 1) != XEXP (x
, 1))
5815 && (XEXP (temp
, 0) != XEXP (x
, 1)
5816 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5822 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5823 (and <foo> (const_int pow2-1)) */
5824 if (GET_CODE (XEXP (x
, 1)) == AND
5825 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5826 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5827 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5828 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5829 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5833 /* If we have (mult (plus A B) C), apply the distributive law and then
5834 the inverse distributive law to see if things simplify. This
5835 occurs mostly in addresses, often when unrolling loops. */
5837 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5839 rtx result
= distribute_and_simplify_rtx (x
, 0);
5844 /* Try simplify a*(b/c) as (a*b)/c. */
5845 if (FLOAT_MODE_P (mode
) && flag_associative_math
5846 && GET_CODE (XEXP (x
, 0)) == DIV
)
5848 rtx tem
= simplify_binary_operation (MULT
, mode
,
5849 XEXP (XEXP (x
, 0), 0),
5852 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5857 /* If this is a divide by a power of two, treat it as a shift if
5858 its first operand is a shift. */
5859 if (CONST_INT_P (XEXP (x
, 1))
5860 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5861 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5862 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5863 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5864 || GET_CODE (XEXP (x
, 0)) == ROTATE
5865 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5866 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5870 case GT
: case GTU
: case GE
: case GEU
:
5871 case LT
: case LTU
: case LE
: case LEU
:
5872 case UNEQ
: case LTGT
:
5873 case UNGT
: case UNGE
:
5874 case UNLT
: case UNLE
:
5875 case UNORDERED
: case ORDERED
:
5876 /* If the first operand is a condition code, we can't do anything
5878 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5879 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5880 && ! CC0_P (XEXP (x
, 0))))
5882 rtx op0
= XEXP (x
, 0);
5883 rtx op1
= XEXP (x
, 1);
5884 enum rtx_code new_code
;
5886 if (GET_CODE (op0
) == COMPARE
)
5887 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5889 /* Simplify our comparison, if possible. */
5890 new_code
= simplify_comparison (code
, &op0
, &op1
);
5892 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5893 if only the low-order bit is possibly nonzero in X (such as when
5894 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5895 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5896 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5899 Remove any ZERO_EXTRACT we made when thinking this was a
5900 comparison. It may now be simpler to use, e.g., an AND. If a
5901 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5902 the call to make_compound_operation in the SET case.
5904 Don't apply these optimizations if the caller would
5905 prefer a comparison rather than a value.
5906 E.g., for the condition in an IF_THEN_ELSE most targets need
5907 an explicit comparison. */
5912 else if (STORE_FLAG_VALUE
== 1
5913 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5914 && op1
== const0_rtx
5915 && mode
== GET_MODE (op0
)
5916 && nonzero_bits (op0
, mode
) == 1)
5917 return gen_lowpart (mode
,
5918 expand_compound_operation (op0
));
5920 else if (STORE_FLAG_VALUE
== 1
5921 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5922 && op1
== const0_rtx
5923 && mode
== GET_MODE (op0
)
5924 && (num_sign_bit_copies (op0
, mode
)
5925 == GET_MODE_PRECISION (mode
)))
5927 op0
= expand_compound_operation (op0
);
5928 return simplify_gen_unary (NEG
, mode
,
5929 gen_lowpart (mode
, op0
),
5933 else if (STORE_FLAG_VALUE
== 1
5934 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5935 && op1
== const0_rtx
5936 && mode
== GET_MODE (op0
)
5937 && nonzero_bits (op0
, mode
) == 1)
5939 op0
= expand_compound_operation (op0
);
5940 return simplify_gen_binary (XOR
, mode
,
5941 gen_lowpart (mode
, op0
),
5945 else if (STORE_FLAG_VALUE
== 1
5946 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5947 && op1
== const0_rtx
5948 && mode
== GET_MODE (op0
)
5949 && (num_sign_bit_copies (op0
, mode
)
5950 == GET_MODE_PRECISION (mode
)))
5952 op0
= expand_compound_operation (op0
);
5953 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5956 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5961 else if (STORE_FLAG_VALUE
== -1
5962 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5963 && op1
== const0_rtx
5964 && mode
== GET_MODE (op0
)
5965 && (num_sign_bit_copies (op0
, mode
)
5966 == GET_MODE_PRECISION (mode
)))
5967 return gen_lowpart (mode
,
5968 expand_compound_operation (op0
));
5970 else if (STORE_FLAG_VALUE
== -1
5971 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5972 && op1
== const0_rtx
5973 && mode
== GET_MODE (op0
)
5974 && nonzero_bits (op0
, mode
) == 1)
5976 op0
= expand_compound_operation (op0
);
5977 return simplify_gen_unary (NEG
, mode
,
5978 gen_lowpart (mode
, op0
),
5982 else if (STORE_FLAG_VALUE
== -1
5983 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5984 && op1
== const0_rtx
5985 && mode
== GET_MODE (op0
)
5986 && (num_sign_bit_copies (op0
, mode
)
5987 == GET_MODE_PRECISION (mode
)))
5989 op0
= expand_compound_operation (op0
);
5990 return simplify_gen_unary (NOT
, mode
,
5991 gen_lowpart (mode
, op0
),
5995 /* If X is 0/1, (eq X 0) is X-1. */
5996 else if (STORE_FLAG_VALUE
== -1
5997 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5998 && op1
== const0_rtx
5999 && mode
== GET_MODE (op0
)
6000 && nonzero_bits (op0
, mode
) == 1)
6002 op0
= expand_compound_operation (op0
);
6003 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6006 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6007 one bit that might be nonzero, we can convert (ne x 0) to
6008 (ashift x c) where C puts the bit in the sign bit. Remove any
6009 AND with STORE_FLAG_VALUE when we are done, since we are only
6010 going to test the sign bit. */
6011 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6012 && HWI_COMPUTABLE_MODE_P (mode
)
6013 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6014 && op1
== const0_rtx
6015 && mode
== GET_MODE (op0
)
6016 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6018 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6019 expand_compound_operation (op0
),
6020 GET_MODE_PRECISION (mode
) - 1 - i
);
6021 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6027 /* If the code changed, return a whole new comparison.
6028 We also need to avoid using SUBST in cases where
6029 simplify_comparison has widened a comparison with a CONST_INT,
6030 since in that case the wider CONST_INT may fail the sanity
6031 checks in do_SUBST. */
6032 if (new_code
!= code
6033 || (CONST_INT_P (op1
)
6034 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6035 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6036 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6038 /* Otherwise, keep this operation, but maybe change its operands.
6039 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6040 SUBST (XEXP (x
, 0), op0
);
6041 SUBST (XEXP (x
, 1), op1
);
6046 return simplify_if_then_else (x
);
6052 /* If we are processing SET_DEST, we are done. */
6056 return expand_compound_operation (x
);
6059 return simplify_set (x
);
6063 return simplify_logical (x
);
6070 /* If this is a shift by a constant amount, simplify it. */
6071 if (CONST_INT_P (XEXP (x
, 1)))
6072 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6073 INTVAL (XEXP (x
, 1)));
6075 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6077 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6078 ((unsigned HOST_WIDE_INT
) 1
6079 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6091 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6094 simplify_if_then_else (rtx x
)
6096 machine_mode mode
= GET_MODE (x
);
6097 rtx cond
= XEXP (x
, 0);
6098 rtx true_rtx
= XEXP (x
, 1);
6099 rtx false_rtx
= XEXP (x
, 2);
6100 enum rtx_code true_code
= GET_CODE (cond
);
6101 int comparison_p
= COMPARISON_P (cond
);
6104 enum rtx_code false_code
;
6107 /* Simplify storing of the truth value. */
6108 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6109 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6110 XEXP (cond
, 0), XEXP (cond
, 1));
6112 /* Also when the truth value has to be reversed. */
6114 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6115 && (reversed
= reversed_comparison (cond
, mode
)))
6118 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6119 in it is being compared against certain values. Get the true and false
6120 comparisons and see if that says anything about the value of each arm. */
6123 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6125 && REG_P (XEXP (cond
, 0)))
6128 rtx from
= XEXP (cond
, 0);
6129 rtx true_val
= XEXP (cond
, 1);
6130 rtx false_val
= true_val
;
6133 /* If FALSE_CODE is EQ, swap the codes and arms. */
6135 if (false_code
== EQ
)
6137 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6138 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6141 /* If we are comparing against zero and the expression being tested has
6142 only a single bit that might be nonzero, that is its value when it is
6143 not equal to zero. Similarly if it is known to be -1 or 0. */
6145 if (true_code
== EQ
&& true_val
== const0_rtx
6146 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6149 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6151 else if (true_code
== EQ
&& true_val
== const0_rtx
6152 && (num_sign_bit_copies (from
, GET_MODE (from
))
6153 == GET_MODE_PRECISION (GET_MODE (from
))))
6156 false_val
= constm1_rtx
;
6159 /* Now simplify an arm if we know the value of the register in the
6160 branch and it is used in the arm. Be careful due to the potential
6161 of locally-shared RTL. */
6163 if (reg_mentioned_p (from
, true_rtx
))
6164 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6166 pc_rtx
, pc_rtx
, 0, 0, 0);
6167 if (reg_mentioned_p (from
, false_rtx
))
6168 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6170 pc_rtx
, pc_rtx
, 0, 0, 0);
6172 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6173 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6175 true_rtx
= XEXP (x
, 1);
6176 false_rtx
= XEXP (x
, 2);
6177 true_code
= GET_CODE (cond
);
6180 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6181 reversed, do so to avoid needing two sets of patterns for
6182 subtract-and-branch insns. Similarly if we have a constant in the true
6183 arm, the false arm is the same as the first operand of the comparison, or
6184 the false arm is more complicated than the true arm. */
6187 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6188 && (true_rtx
== pc_rtx
6189 || (CONSTANT_P (true_rtx
)
6190 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6191 || true_rtx
== const0_rtx
6192 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6193 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6194 && !OBJECT_P (false_rtx
))
6195 || reg_mentioned_p (true_rtx
, false_rtx
)
6196 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6198 true_code
= reversed_comparison_code (cond
, NULL
);
6199 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6200 SUBST (XEXP (x
, 1), false_rtx
);
6201 SUBST (XEXP (x
, 2), true_rtx
);
6203 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6206 /* It is possible that the conditional has been simplified out. */
6207 true_code
= GET_CODE (cond
);
6208 comparison_p
= COMPARISON_P (cond
);
6211 /* If the two arms are identical, we don't need the comparison. */
6213 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6216 /* Convert a == b ? b : a to "a". */
6217 if (true_code
== EQ
&& ! side_effects_p (cond
)
6218 && !HONOR_NANS (mode
)
6219 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6220 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6222 else if (true_code
== NE
&& ! side_effects_p (cond
)
6223 && !HONOR_NANS (mode
)
6224 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6225 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6228 /* Look for cases where we have (abs x) or (neg (abs X)). */
6230 if (GET_MODE_CLASS (mode
) == MODE_INT
6232 && XEXP (cond
, 1) == const0_rtx
6233 && GET_CODE (false_rtx
) == NEG
6234 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6235 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6236 && ! side_effects_p (true_rtx
))
6241 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6245 simplify_gen_unary (NEG
, mode
,
6246 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6252 /* Look for MIN or MAX. */
6254 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6256 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6257 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6258 && ! side_effects_p (cond
))
6263 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6266 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6269 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6272 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6277 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6278 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6279 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6280 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6281 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6282 neither 1 or -1, but it isn't worth checking for. */
6284 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6286 && GET_MODE_CLASS (mode
) == MODE_INT
6287 && ! side_effects_p (x
))
6289 rtx t
= make_compound_operation (true_rtx
, SET
);
6290 rtx f
= make_compound_operation (false_rtx
, SET
);
6291 rtx cond_op0
= XEXP (cond
, 0);
6292 rtx cond_op1
= XEXP (cond
, 1);
6293 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6294 machine_mode m
= mode
;
6295 rtx z
= 0, c1
= NULL_RTX
;
6297 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6298 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6299 || GET_CODE (t
) == ASHIFT
6300 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6301 && rtx_equal_p (XEXP (t
, 0), f
))
6302 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6304 /* If an identity-zero op is commutative, check whether there
6305 would be a match if we swapped the operands. */
6306 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6307 || GET_CODE (t
) == XOR
)
6308 && rtx_equal_p (XEXP (t
, 1), f
))
6309 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6310 else if (GET_CODE (t
) == SIGN_EXTEND
6311 && (GET_CODE (XEXP (t
, 0)) == PLUS
6312 || GET_CODE (XEXP (t
, 0)) == MINUS
6313 || GET_CODE (XEXP (t
, 0)) == IOR
6314 || GET_CODE (XEXP (t
, 0)) == XOR
6315 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6316 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6317 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6318 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6319 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6320 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6321 && (num_sign_bit_copies (f
, GET_MODE (f
))
6323 (GET_MODE_PRECISION (mode
)
6324 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6326 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6327 extend_op
= SIGN_EXTEND
;
6328 m
= GET_MODE (XEXP (t
, 0));
6330 else if (GET_CODE (t
) == SIGN_EXTEND
6331 && (GET_CODE (XEXP (t
, 0)) == PLUS
6332 || GET_CODE (XEXP (t
, 0)) == IOR
6333 || GET_CODE (XEXP (t
, 0)) == XOR
)
6334 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6335 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6336 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6337 && (num_sign_bit_copies (f
, GET_MODE (f
))
6339 (GET_MODE_PRECISION (mode
)
6340 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6342 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6343 extend_op
= SIGN_EXTEND
;
6344 m
= GET_MODE (XEXP (t
, 0));
6346 else if (GET_CODE (t
) == ZERO_EXTEND
6347 && (GET_CODE (XEXP (t
, 0)) == PLUS
6348 || GET_CODE (XEXP (t
, 0)) == MINUS
6349 || GET_CODE (XEXP (t
, 0)) == IOR
6350 || GET_CODE (XEXP (t
, 0)) == XOR
6351 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6352 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6353 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6354 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6355 && HWI_COMPUTABLE_MODE_P (mode
)
6356 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6357 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6358 && ((nonzero_bits (f
, GET_MODE (f
))
6359 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6362 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6363 extend_op
= ZERO_EXTEND
;
6364 m
= GET_MODE (XEXP (t
, 0));
6366 else if (GET_CODE (t
) == ZERO_EXTEND
6367 && (GET_CODE (XEXP (t
, 0)) == PLUS
6368 || GET_CODE (XEXP (t
, 0)) == IOR
6369 || GET_CODE (XEXP (t
, 0)) == XOR
)
6370 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6371 && HWI_COMPUTABLE_MODE_P (mode
)
6372 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6373 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6374 && ((nonzero_bits (f
, GET_MODE (f
))
6375 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6378 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6379 extend_op
= ZERO_EXTEND
;
6380 m
= GET_MODE (XEXP (t
, 0));
6385 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6386 cond_op0
, cond_op1
),
6387 pc_rtx
, pc_rtx
, 0, 0, 0);
6388 temp
= simplify_gen_binary (MULT
, m
, temp
,
6389 simplify_gen_binary (MULT
, m
, c1
,
6391 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6392 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6394 if (extend_op
!= UNKNOWN
)
6395 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6401 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6402 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6403 negation of a single bit, we can convert this operation to a shift. We
6404 can actually do this more generally, but it doesn't seem worth it. */
6406 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6407 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6408 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6409 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6410 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6411 == GET_MODE_PRECISION (mode
))
6412 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6414 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6415 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6417 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6418 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6419 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6420 && GET_MODE (XEXP (cond
, 0)) == mode
6421 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6422 == nonzero_bits (XEXP (cond
, 0), mode
)
6423 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6424 return XEXP (cond
, 0);
6429 /* Simplify X, a SET expression. Return the new expression. */
6432 simplify_set (rtx x
)
6434 rtx src
= SET_SRC (x
);
6435 rtx dest
= SET_DEST (x
);
6437 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6438 rtx_insn
*other_insn
;
6441 /* (set (pc) (return)) gets written as (return). */
6442 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6445 /* Now that we know for sure which bits of SRC we are using, see if we can
6446 simplify the expression for the object knowing that we only need the
6449 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6451 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6452 SUBST (SET_SRC (x
), src
);
6455 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6456 the comparison result and try to simplify it unless we already have used
6457 undobuf.other_insn. */
6458 if ((GET_MODE_CLASS (mode
) == MODE_CC
6459 || GET_CODE (src
) == COMPARE
6461 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6462 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6463 && COMPARISON_P (*cc_use
)
6464 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6466 enum rtx_code old_code
= GET_CODE (*cc_use
);
6467 enum rtx_code new_code
;
6469 int other_changed
= 0;
6470 rtx inner_compare
= NULL_RTX
;
6471 machine_mode compare_mode
= GET_MODE (dest
);
6473 if (GET_CODE (src
) == COMPARE
)
6475 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6476 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6478 inner_compare
= op0
;
6479 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6483 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6485 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6488 new_code
= old_code
;
6489 else if (!CONSTANT_P (tmp
))
6491 new_code
= GET_CODE (tmp
);
6492 op0
= XEXP (tmp
, 0);
6493 op1
= XEXP (tmp
, 1);
6497 rtx pat
= PATTERN (other_insn
);
6498 undobuf
.other_insn
= other_insn
;
6499 SUBST (*cc_use
, tmp
);
6501 /* Attempt to simplify CC user. */
6502 if (GET_CODE (pat
) == SET
)
6504 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6505 if (new_rtx
!= NULL_RTX
)
6506 SUBST (SET_SRC (pat
), new_rtx
);
6509 /* Convert X into a no-op move. */
6510 SUBST (SET_DEST (x
), pc_rtx
);
6511 SUBST (SET_SRC (x
), pc_rtx
);
6515 /* Simplify our comparison, if possible. */
6516 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6518 #ifdef SELECT_CC_MODE
6519 /* If this machine has CC modes other than CCmode, check to see if we
6520 need to use a different CC mode here. */
6521 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6522 compare_mode
= GET_MODE (op0
);
6523 else if (inner_compare
6524 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6525 && new_code
== old_code
6526 && op0
== XEXP (inner_compare
, 0)
6527 && op1
== XEXP (inner_compare
, 1))
6528 compare_mode
= GET_MODE (inner_compare
);
6530 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6533 /* If the mode changed, we have to change SET_DEST, the mode in the
6534 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6535 a hard register, just build new versions with the proper mode. If it
6536 is a pseudo, we lose unless it is only time we set the pseudo, in
6537 which case we can safely change its mode. */
6538 if (compare_mode
!= GET_MODE (dest
))
6540 if (can_change_dest_mode (dest
, 0, compare_mode
))
6542 unsigned int regno
= REGNO (dest
);
6545 if (regno
< FIRST_PSEUDO_REGISTER
)
6546 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6549 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6550 new_dest
= regno_reg_rtx
[regno
];
6553 SUBST (SET_DEST (x
), new_dest
);
6554 SUBST (XEXP (*cc_use
, 0), new_dest
);
6561 #endif /* SELECT_CC_MODE */
6563 /* If the code changed, we have to build a new comparison in
6564 undobuf.other_insn. */
6565 if (new_code
!= old_code
)
6567 int other_changed_previously
= other_changed
;
6568 unsigned HOST_WIDE_INT mask
;
6569 rtx old_cc_use
= *cc_use
;
6571 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6575 /* If the only change we made was to change an EQ into an NE or
6576 vice versa, OP0 has only one bit that might be nonzero, and OP1
6577 is zero, check if changing the user of the condition code will
6578 produce a valid insn. If it won't, we can keep the original code
6579 in that insn by surrounding our operation with an XOR. */
6581 if (((old_code
== NE
&& new_code
== EQ
)
6582 || (old_code
== EQ
&& new_code
== NE
))
6583 && ! other_changed_previously
&& op1
== const0_rtx
6584 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6585 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6587 rtx pat
= PATTERN (other_insn
), note
= 0;
6589 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6590 && ! check_asm_operands (pat
)))
6592 *cc_use
= old_cc_use
;
6595 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6603 undobuf
.other_insn
= other_insn
;
6605 /* Otherwise, if we didn't previously have a COMPARE in the
6606 correct mode, we need one. */
6607 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6609 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6612 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6614 SUBST (SET_SRC (x
), op0
);
6617 /* Otherwise, update the COMPARE if needed. */
6618 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6620 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6626 /* Get SET_SRC in a form where we have placed back any
6627 compound expressions. Then do the checks below. */
6628 src
= make_compound_operation (src
, SET
);
6629 SUBST (SET_SRC (x
), src
);
6632 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6633 and X being a REG or (subreg (reg)), we may be able to convert this to
6634 (set (subreg:m2 x) (op)).
6636 We can always do this if M1 is narrower than M2 because that means that
6637 we only care about the low bits of the result.
6639 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6640 perform a narrower operation than requested since the high-order bits will
6641 be undefined. On machine where it is defined, this transformation is safe
6642 as long as M1 and M2 have the same number of words. */
6644 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6645 && !OBJECT_P (SUBREG_REG (src
))
6646 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6648 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6649 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6650 #ifndef WORD_REGISTER_OPERATIONS
6651 && (GET_MODE_SIZE (GET_MODE (src
))
6652 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6654 #ifdef CANNOT_CHANGE_MODE_CLASS
6655 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6656 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6657 GET_MODE (SUBREG_REG (src
)),
6661 || (GET_CODE (dest
) == SUBREG
6662 && REG_P (SUBREG_REG (dest
)))))
6664 SUBST (SET_DEST (x
),
6665 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6667 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6669 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6673 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6676 && GET_CODE (src
) == SUBREG
6677 && subreg_lowpart_p (src
)
6678 && (GET_MODE_PRECISION (GET_MODE (src
))
6679 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6681 rtx inner
= SUBREG_REG (src
);
6682 machine_mode inner_mode
= GET_MODE (inner
);
6684 /* Here we make sure that we don't have a sign bit on. */
6685 if (val_signbit_known_clear_p (GET_MODE (src
),
6686 nonzero_bits (inner
, inner_mode
)))
6688 SUBST (SET_SRC (x
), inner
);
6694 #ifdef LOAD_EXTEND_OP
6695 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6696 would require a paradoxical subreg. Replace the subreg with a
6697 zero_extend to avoid the reload that would otherwise be required. */
6699 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6700 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6701 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6702 && SUBREG_BYTE (src
) == 0
6703 && paradoxical_subreg_p (src
)
6704 && MEM_P (SUBREG_REG (src
)))
6707 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6708 GET_MODE (src
), SUBREG_REG (src
)));
6714 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6715 are comparing an item known to be 0 or -1 against 0, use a logical
6716 operation instead. Check for one of the arms being an IOR of the other
6717 arm with some value. We compute three terms to be IOR'ed together. In
6718 practice, at most two will be nonzero. Then we do the IOR's. */
6720 if (GET_CODE (dest
) != PC
6721 && GET_CODE (src
) == IF_THEN_ELSE
6722 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6723 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6724 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6725 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6726 #ifdef HAVE_conditional_move
6727 && ! can_conditionally_move_p (GET_MODE (src
))
6729 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6730 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6731 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6732 && ! side_effects_p (src
))
6734 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6735 ? XEXP (src
, 1) : XEXP (src
, 2));
6736 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6737 ? XEXP (src
, 2) : XEXP (src
, 1));
6738 rtx term1
= const0_rtx
, term2
, term3
;
6740 if (GET_CODE (true_rtx
) == IOR
6741 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6742 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6743 else if (GET_CODE (true_rtx
) == IOR
6744 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6745 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6746 else if (GET_CODE (false_rtx
) == IOR
6747 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6748 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6749 else if (GET_CODE (false_rtx
) == IOR
6750 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6751 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6753 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6754 XEXP (XEXP (src
, 0), 0), true_rtx
);
6755 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6756 simplify_gen_unary (NOT
, GET_MODE (src
),
6757 XEXP (XEXP (src
, 0), 0),
6762 simplify_gen_binary (IOR
, GET_MODE (src
),
6763 simplify_gen_binary (IOR
, GET_MODE (src
),
6770 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6771 whole thing fail. */
6772 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6774 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6777 /* Convert this into a field assignment operation, if possible. */
6778 return make_field_assignment (x
);
6781 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6785 simplify_logical (rtx x
)
6787 machine_mode mode
= GET_MODE (x
);
6788 rtx op0
= XEXP (x
, 0);
6789 rtx op1
= XEXP (x
, 1);
6791 switch (GET_CODE (x
))
6794 /* We can call simplify_and_const_int only if we don't lose
6795 any (sign) bits when converting INTVAL (op1) to
6796 "unsigned HOST_WIDE_INT". */
6797 if (CONST_INT_P (op1
)
6798 && (HWI_COMPUTABLE_MODE_P (mode
)
6799 || INTVAL (op1
) > 0))
6801 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6802 if (GET_CODE (x
) != AND
)
6809 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6810 apply the distributive law and then the inverse distributive
6811 law to see if things simplify. */
6812 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6814 rtx result
= distribute_and_simplify_rtx (x
, 0);
6818 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6820 rtx result
= distribute_and_simplify_rtx (x
, 1);
6827 /* If we have (ior (and A B) C), apply the distributive law and then
6828 the inverse distributive law to see if things simplify. */
6830 if (GET_CODE (op0
) == AND
)
6832 rtx result
= distribute_and_simplify_rtx (x
, 0);
6837 if (GET_CODE (op1
) == AND
)
6839 rtx result
= distribute_and_simplify_rtx (x
, 1);
6852 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6853 operations" because they can be replaced with two more basic operations.
6854 ZERO_EXTEND is also considered "compound" because it can be replaced with
6855 an AND operation, which is simpler, though only one operation.
6857 The function expand_compound_operation is called with an rtx expression
6858 and will convert it to the appropriate shifts and AND operations,
6859 simplifying at each stage.
6861 The function make_compound_operation is called to convert an expression
6862 consisting of shifts and ANDs into the equivalent compound expression.
6863 It is the inverse of this function, loosely speaking. */
6866 expand_compound_operation (rtx x
)
6868 unsigned HOST_WIDE_INT pos
= 0, len
;
6870 unsigned int modewidth
;
6873 switch (GET_CODE (x
))
6878 /* We can't necessarily use a const_int for a multiword mode;
6879 it depends on implicitly extending the value.
6880 Since we don't know the right way to extend it,
6881 we can't tell whether the implicit way is right.
6883 Even for a mode that is no wider than a const_int,
6884 we can't win, because we need to sign extend one of its bits through
6885 the rest of it, and we don't know which bit. */
6886 if (CONST_INT_P (XEXP (x
, 0)))
6889 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6890 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6891 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6892 reloaded. If not for that, MEM's would very rarely be safe.
6894 Reject MODEs bigger than a word, because we might not be able
6895 to reference a two-register group starting with an arbitrary register
6896 (and currently gen_lowpart might crash for a SUBREG). */
6898 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6901 /* Reject MODEs that aren't scalar integers because turning vector
6902 or complex modes into shifts causes problems. */
6904 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6907 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6908 /* If the inner object has VOIDmode (the only way this can happen
6909 is if it is an ASM_OPERANDS), we can't do anything since we don't
6910 know how much masking to do. */
6919 /* ... fall through ... */
6922 /* If the operand is a CLOBBER, just return it. */
6923 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6926 if (!CONST_INT_P (XEXP (x
, 1))
6927 || !CONST_INT_P (XEXP (x
, 2))
6928 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6931 /* Reject MODEs that aren't scalar integers because turning vector
6932 or complex modes into shifts causes problems. */
6934 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6937 len
= INTVAL (XEXP (x
, 1));
6938 pos
= INTVAL (XEXP (x
, 2));
6940 /* This should stay within the object being extracted, fail otherwise. */
6941 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6944 if (BITS_BIG_ENDIAN
)
6945 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6952 /* Convert sign extension to zero extension, if we know that the high
6953 bit is not set, as this is easier to optimize. It will be converted
6954 back to cheaper alternative in make_extraction. */
6955 if (GET_CODE (x
) == SIGN_EXTEND
6956 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6957 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6958 & ~(((unsigned HOST_WIDE_INT
)
6959 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6963 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6964 rtx temp2
= expand_compound_operation (temp
);
6966 /* Make sure this is a profitable operation. */
6967 if (set_src_cost (x
, optimize_this_for_speed_p
)
6968 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6970 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6971 > set_src_cost (temp
, optimize_this_for_speed_p
))
6977 /* We can optimize some special cases of ZERO_EXTEND. */
6978 if (GET_CODE (x
) == ZERO_EXTEND
)
6980 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6981 know that the last value didn't have any inappropriate bits
6983 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6984 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6985 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6986 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6987 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6988 return XEXP (XEXP (x
, 0), 0);
6990 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6991 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6992 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6993 && subreg_lowpart_p (XEXP (x
, 0))
6994 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6995 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6996 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6997 return SUBREG_REG (XEXP (x
, 0));
6999 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7000 is a comparison and STORE_FLAG_VALUE permits. This is like
7001 the first case, but it works even when GET_MODE (x) is larger
7002 than HOST_WIDE_INT. */
7003 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7004 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7005 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7006 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7007 <= HOST_BITS_PER_WIDE_INT
)
7008 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7009 return XEXP (XEXP (x
, 0), 0);
7011 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7012 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7013 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7014 && subreg_lowpart_p (XEXP (x
, 0))
7015 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7016 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7017 <= HOST_BITS_PER_WIDE_INT
)
7018 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7019 return SUBREG_REG (XEXP (x
, 0));
7023 /* If we reach here, we want to return a pair of shifts. The inner
7024 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7025 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7026 logical depending on the value of UNSIGNEDP.
7028 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7029 converted into an AND of a shift.
7031 We must check for the case where the left shift would have a negative
7032 count. This can happen in a case like (x >> 31) & 255 on machines
7033 that can't shift by a constant. On those machines, we would first
7034 combine the shift with the AND to produce a variable-position
7035 extraction. Then the constant of 31 would be substituted in
7036 to produce such a position. */
7038 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7039 if (modewidth
>= pos
+ len
)
7041 machine_mode mode
= GET_MODE (x
);
7042 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7043 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7045 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7046 tem
, modewidth
- pos
- len
);
7047 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7048 mode
, tem
, modewidth
- len
);
7050 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7051 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7052 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7055 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7057 /* Any other cases we can't handle. */
7060 /* If we couldn't do this for some reason, return the original
7062 if (GET_CODE (tem
) == CLOBBER
)
7068 /* X is a SET which contains an assignment of one object into
7069 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7070 or certain SUBREGS). If possible, convert it into a series of
7073 We half-heartedly support variable positions, but do not at all
7074 support variable lengths. */
7077 expand_field_assignment (const_rtx x
)
7080 rtx pos
; /* Always counts from low bit. */
7082 rtx mask
, cleared
, masked
;
7083 machine_mode compute_mode
;
7085 /* Loop until we find something we can't simplify. */
7088 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7089 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7091 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7092 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7093 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7095 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7096 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7098 inner
= XEXP (SET_DEST (x
), 0);
7099 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7100 pos
= XEXP (SET_DEST (x
), 2);
7102 /* A constant position should stay within the width of INNER. */
7103 if (CONST_INT_P (pos
)
7104 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7107 if (BITS_BIG_ENDIAN
)
7109 if (CONST_INT_P (pos
))
7110 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7112 else if (GET_CODE (pos
) == MINUS
7113 && CONST_INT_P (XEXP (pos
, 1))
7114 && (INTVAL (XEXP (pos
, 1))
7115 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7116 /* If position is ADJUST - X, new position is X. */
7117 pos
= XEXP (pos
, 0);
7120 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7121 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7122 gen_int_mode (prec
- len
,
7129 /* A SUBREG between two modes that occupy the same numbers of words
7130 can be done by moving the SUBREG to the source. */
7131 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7132 /* We need SUBREGs to compute nonzero_bits properly. */
7133 && nonzero_sign_valid
7134 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7135 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7136 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7137 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7139 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
7141 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7148 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7149 inner
= SUBREG_REG (inner
);
7151 compute_mode
= GET_MODE (inner
);
7153 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7154 if (! SCALAR_INT_MODE_P (compute_mode
))
7158 /* Don't do anything for vector or complex integral types. */
7159 if (! FLOAT_MODE_P (compute_mode
))
7162 /* Try to find an integral mode to pun with. */
7163 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7164 if (imode
== BLKmode
)
7167 compute_mode
= imode
;
7168 inner
= gen_lowpart (imode
, inner
);
7171 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7172 if (len
>= HOST_BITS_PER_WIDE_INT
)
7175 /* Now compute the equivalent expression. Make a copy of INNER
7176 for the SET_DEST in case it is a MEM into which we will substitute;
7177 we don't want shared RTL in that case. */
7178 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7180 cleared
= simplify_gen_binary (AND
, compute_mode
,
7181 simplify_gen_unary (NOT
, compute_mode
,
7182 simplify_gen_binary (ASHIFT
,
7187 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7188 simplify_gen_binary (
7190 gen_lowpart (compute_mode
, SET_SRC (x
)),
7194 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7195 simplify_gen_binary (IOR
, compute_mode
,
7202 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7203 it is an RTX that represents the (variable) starting position; otherwise,
7204 POS is the (constant) starting bit position. Both are counted from the LSB.
7206 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7208 IN_DEST is nonzero if this is a reference in the destination of a SET.
7209 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7210 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7213 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7214 ZERO_EXTRACT should be built even for bits starting at bit 0.
7216 MODE is the desired mode of the result (if IN_DEST == 0).
7218 The result is an RTX for the extraction or NULL_RTX if the target
7222 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7223 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7224 int in_dest
, int in_compare
)
7226 /* This mode describes the size of the storage area
7227 to fetch the overall value from. Within that, we
7228 ignore the POS lowest bits, etc. */
7229 machine_mode is_mode
= GET_MODE (inner
);
7230 machine_mode inner_mode
;
7231 machine_mode wanted_inner_mode
;
7232 machine_mode wanted_inner_reg_mode
= word_mode
;
7233 machine_mode pos_mode
= word_mode
;
7234 machine_mode extraction_mode
= word_mode
;
7235 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7237 rtx orig_pos_rtx
= pos_rtx
;
7238 HOST_WIDE_INT orig_pos
;
7240 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7241 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7243 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7245 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7246 consider just the QI as the memory to extract from.
7247 The subreg adds or removes high bits; its mode is
7248 irrelevant to the meaning of this extraction,
7249 since POS and LEN count from the lsb. */
7250 if (MEM_P (SUBREG_REG (inner
)))
7251 is_mode
= GET_MODE (SUBREG_REG (inner
));
7252 inner
= SUBREG_REG (inner
);
7254 else if (GET_CODE (inner
) == ASHIFT
7255 && CONST_INT_P (XEXP (inner
, 1))
7256 && pos_rtx
== 0 && pos
== 0
7257 && len
> UINTVAL (XEXP (inner
, 1)))
7259 /* We're extracting the least significant bits of an rtx
7260 (ashift X (const_int C)), where LEN > C. Extract the
7261 least significant (LEN - C) bits of X, giving an rtx
7262 whose mode is MODE, then shift it left C times. */
7263 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7264 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7265 unsignedp
, in_dest
, in_compare
);
7267 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7269 else if (GET_CODE (inner
) == TRUNCATE
)
7270 inner
= XEXP (inner
, 0);
7272 inner_mode
= GET_MODE (inner
);
7274 /* See if this can be done without an extraction. We never can if the
7275 width of the field is not the same as that of some integer mode. For
7276 registers, we can only avoid the extraction if the position is at the
7277 low-order bit and this is either not in the destination or we have the
7278 appropriate STRICT_LOW_PART operation available.
7280 For MEM, we can avoid an extract if the field starts on an appropriate
7281 boundary and we can change the mode of the memory reference. */
7283 if (tmode
!= BLKmode
7284 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7286 && (inner_mode
== tmode
7288 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7289 || reg_truncated_to_mode (tmode
, inner
))
7292 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7293 || (MEM_P (inner
) && pos_rtx
== 0
7295 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7296 : BITS_PER_UNIT
)) == 0
7297 /* We can't do this if we are widening INNER_MODE (it
7298 may not be aligned, for one thing). */
7299 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7300 && (inner_mode
== tmode
7301 || (! mode_dependent_address_p (XEXP (inner
, 0),
7302 MEM_ADDR_SPACE (inner
))
7303 && ! MEM_VOLATILE_P (inner
))))))
7305 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7306 field. If the original and current mode are the same, we need not
7307 adjust the offset. Otherwise, we do if bytes big endian.
7309 If INNER is not a MEM, get a piece consisting of just the field
7310 of interest (in this case POS % BITS_PER_WORD must be 0). */
7314 HOST_WIDE_INT offset
;
7316 /* POS counts from lsb, but make OFFSET count in memory order. */
7317 if (BYTES_BIG_ENDIAN
)
7318 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7320 offset
= pos
/ BITS_PER_UNIT
;
7322 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7324 else if (REG_P (inner
))
7326 if (tmode
!= inner_mode
)
7328 /* We can't call gen_lowpart in a DEST since we
7329 always want a SUBREG (see below) and it would sometimes
7330 return a new hard register. */
7333 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7335 if (WORDS_BIG_ENDIAN
7336 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7337 final_word
= ((GET_MODE_SIZE (inner_mode
)
7338 - GET_MODE_SIZE (tmode
))
7339 / UNITS_PER_WORD
) - final_word
;
7341 final_word
*= UNITS_PER_WORD
;
7342 if (BYTES_BIG_ENDIAN
&&
7343 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7344 final_word
+= (GET_MODE_SIZE (inner_mode
)
7345 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7347 /* Avoid creating invalid subregs, for example when
7348 simplifying (x>>32)&255. */
7349 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7352 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7355 new_rtx
= gen_lowpart (tmode
, inner
);
7361 new_rtx
= force_to_mode (inner
, tmode
,
7362 len
>= HOST_BITS_PER_WIDE_INT
7363 ? ~(unsigned HOST_WIDE_INT
) 0
7364 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7367 /* If this extraction is going into the destination of a SET,
7368 make a STRICT_LOW_PART unless we made a MEM. */
7371 return (MEM_P (new_rtx
) ? new_rtx
7372 : (GET_CODE (new_rtx
) != SUBREG
7373 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7374 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7379 if (CONST_SCALAR_INT_P (new_rtx
))
7380 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7381 mode
, new_rtx
, tmode
);
7383 /* If we know that no extraneous bits are set, and that the high
7384 bit is not set, convert the extraction to the cheaper of
7385 sign and zero extension, that are equivalent in these cases. */
7386 if (flag_expensive_optimizations
7387 && (HWI_COMPUTABLE_MODE_P (tmode
)
7388 && ((nonzero_bits (new_rtx
, tmode
)
7389 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7392 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7393 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7395 /* Prefer ZERO_EXTENSION, since it gives more information to
7397 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7398 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7403 /* Otherwise, sign- or zero-extend unless we already are in the
7406 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7410 /* Unless this is a COMPARE or we have a funny memory reference,
7411 don't do anything with zero-extending field extracts starting at
7412 the low-order bit since they are simple AND operations. */
7413 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7414 && ! in_compare
&& unsignedp
)
7417 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7418 if the position is not a constant and the length is not 1. In all
7419 other cases, we would only be going outside our object in cases when
7420 an original shift would have been undefined. */
7422 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7423 || (pos_rtx
!= 0 && len
!= 1)))
7426 enum extraction_pattern pattern
= (in_dest
? EP_insv
7427 : unsignedp
? EP_extzv
: EP_extv
);
7429 /* If INNER is not from memory, we want it to have the mode of a register
7430 extraction pattern's structure operand, or word_mode if there is no
7431 such pattern. The same applies to extraction_mode and pos_mode
7432 and their respective operands.
7434 For memory, assume that the desired extraction_mode and pos_mode
7435 are the same as for a register operation, since at present we don't
7436 have named patterns for aligned memory structures. */
7437 struct extraction_insn insn
;
7438 if (get_best_reg_extraction_insn (&insn
, pattern
,
7439 GET_MODE_BITSIZE (inner_mode
), mode
))
7441 wanted_inner_reg_mode
= insn
.struct_mode
;
7442 pos_mode
= insn
.pos_mode
;
7443 extraction_mode
= insn
.field_mode
;
7446 /* Never narrow an object, since that might not be safe. */
7448 if (mode
!= VOIDmode
7449 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7450 extraction_mode
= mode
;
7453 wanted_inner_mode
= wanted_inner_reg_mode
;
7456 /* Be careful not to go beyond the extracted object and maintain the
7457 natural alignment of the memory. */
7458 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7459 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7460 > GET_MODE_BITSIZE (wanted_inner_mode
))
7462 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7463 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7469 if (BITS_BIG_ENDIAN
)
7471 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7472 BITS_BIG_ENDIAN style. If position is constant, compute new
7473 position. Otherwise, build subtraction.
7474 Note that POS is relative to the mode of the original argument.
7475 If it's a MEM we need to recompute POS relative to that.
7476 However, if we're extracting from (or inserting into) a register,
7477 we want to recompute POS relative to wanted_inner_mode. */
7478 int width
= (MEM_P (inner
)
7479 ? GET_MODE_BITSIZE (is_mode
)
7480 : GET_MODE_BITSIZE (wanted_inner_mode
));
7483 pos
= width
- len
- pos
;
7486 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7487 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7489 /* POS may be less than 0 now, but we check for that below.
7490 Note that it can only be less than 0 if !MEM_P (inner). */
7493 /* If INNER has a wider mode, and this is a constant extraction, try to
7494 make it smaller and adjust the byte to point to the byte containing
7496 if (wanted_inner_mode
!= VOIDmode
7497 && inner_mode
!= wanted_inner_mode
7499 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7501 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7502 && ! MEM_VOLATILE_P (inner
))
7506 /* The computations below will be correct if the machine is big
7507 endian in both bits and bytes or little endian in bits and bytes.
7508 If it is mixed, we must adjust. */
7510 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7511 adjust OFFSET to compensate. */
7512 if (BYTES_BIG_ENDIAN
7513 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7514 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7516 /* We can now move to the desired byte. */
7517 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7518 * GET_MODE_SIZE (wanted_inner_mode
);
7519 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7521 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7522 && is_mode
!= wanted_inner_mode
)
7523 offset
= (GET_MODE_SIZE (is_mode
)
7524 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7526 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7529 /* If INNER is not memory, get it into the proper mode. If we are changing
7530 its mode, POS must be a constant and smaller than the size of the new
7532 else if (!MEM_P (inner
))
7534 /* On the LHS, don't create paradoxical subregs implicitely truncating
7535 the register unless TRULY_NOOP_TRUNCATION. */
7537 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7541 if (GET_MODE (inner
) != wanted_inner_mode
7543 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7549 inner
= force_to_mode (inner
, wanted_inner_mode
,
7551 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7552 ? ~(unsigned HOST_WIDE_INT
) 0
7553 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7558 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7559 have to zero extend. Otherwise, we can just use a SUBREG. */
7561 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7563 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7564 GET_MODE (pos_rtx
));
7566 /* If we know that no extraneous bits are set, and that the high
7567 bit is not set, convert extraction to cheaper one - either
7568 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7570 if (flag_expensive_optimizations
7571 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7572 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7573 & ~(((unsigned HOST_WIDE_INT
)
7574 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7578 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7579 GET_MODE (pos_rtx
));
7581 /* Prefer ZERO_EXTENSION, since it gives more information to
7583 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7584 < set_src_cost (temp
, optimize_this_for_speed_p
))
7590 /* Make POS_RTX unless we already have it and it is correct. If we don't
7591 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7593 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7594 pos_rtx
= orig_pos_rtx
;
7596 else if (pos_rtx
== 0)
7597 pos_rtx
= GEN_INT (pos
);
7599 /* Make the required operation. See if we can use existing rtx. */
7600 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7601 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7603 new_rtx
= gen_lowpart (mode
, new_rtx
);
7608 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7609 with any other operations in X. Return X without that shift if so. */
7612 extract_left_shift (rtx x
, int count
)
7614 enum rtx_code code
= GET_CODE (x
);
7615 machine_mode mode
= GET_MODE (x
);
7621 /* This is the shift itself. If it is wide enough, we will return
7622 either the value being shifted if the shift count is equal to
7623 COUNT or a shift for the difference. */
7624 if (CONST_INT_P (XEXP (x
, 1))
7625 && INTVAL (XEXP (x
, 1)) >= count
)
7626 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7627 INTVAL (XEXP (x
, 1)) - count
);
7631 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7632 return simplify_gen_unary (code
, mode
, tem
, mode
);
7636 case PLUS
: case IOR
: case XOR
: case AND
:
7637 /* If we can safely shift this constant and we find the inner shift,
7638 make a new operation. */
7639 if (CONST_INT_P (XEXP (x
, 1))
7640 && (UINTVAL (XEXP (x
, 1))
7641 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7642 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7644 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7645 return simplify_gen_binary (code
, mode
, tem
,
7646 gen_int_mode (val
, mode
));
7657 /* Look at the expression rooted at X. Look for expressions
7658 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7659 Form these expressions.
7661 Return the new rtx, usually just X.
7663 Also, for machines like the VAX that don't have logical shift insns,
7664 try to convert logical to arithmetic shift operations in cases where
7665 they are equivalent. This undoes the canonicalizations to logical
7666 shifts done elsewhere.
7668 We try, as much as possible, to re-use rtl expressions to save memory.
7670 IN_CODE says what kind of expression we are processing. Normally, it is
7671 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7672 being kludges), it is MEM. When processing the arguments of a comparison
7673 or a COMPARE against zero, it is COMPARE. */
7676 make_compound_operation (rtx x
, enum rtx_code in_code
)
7678 enum rtx_code code
= GET_CODE (x
);
7679 machine_mode mode
= GET_MODE (x
);
7680 int mode_width
= GET_MODE_PRECISION (mode
);
7682 enum rtx_code next_code
;
7688 /* Select the code to be used in recursive calls. Once we are inside an
7689 address, we stay there. If we have a comparison, set to COMPARE,
7690 but once inside, go back to our default of SET. */
7692 next_code
= (code
== MEM
? MEM
7693 : ((code
== PLUS
|| code
== MINUS
)
7694 && SCALAR_INT_MODE_P (mode
)) ? MEM
7695 : ((code
== COMPARE
|| COMPARISON_P (x
))
7696 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7697 : in_code
== COMPARE
? SET
: in_code
);
7699 /* Process depending on the code of this operation. If NEW is set
7700 nonzero, it will be returned. */
7705 /* Convert shifts by constants into multiplications if inside
7707 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7708 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7709 && INTVAL (XEXP (x
, 1)) >= 0
7710 && SCALAR_INT_MODE_P (mode
))
7712 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7713 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7715 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7716 if (GET_CODE (new_rtx
) == NEG
)
7718 new_rtx
= XEXP (new_rtx
, 0);
7721 multval
= trunc_int_for_mode (multval
, mode
);
7722 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7729 lhs
= make_compound_operation (lhs
, next_code
);
7730 rhs
= make_compound_operation (rhs
, next_code
);
7731 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7732 && SCALAR_INT_MODE_P (mode
))
7734 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7736 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7738 else if (GET_CODE (lhs
) == MULT
7739 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7741 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7742 simplify_gen_unary (NEG
, mode
,
7745 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7749 SUBST (XEXP (x
, 0), lhs
);
7750 SUBST (XEXP (x
, 1), rhs
);
7753 x
= gen_lowpart (mode
, new_rtx
);
7759 lhs
= make_compound_operation (lhs
, next_code
);
7760 rhs
= make_compound_operation (rhs
, next_code
);
7761 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7762 && SCALAR_INT_MODE_P (mode
))
7764 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7766 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7768 else if (GET_CODE (rhs
) == MULT
7769 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7771 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7772 simplify_gen_unary (NEG
, mode
,
7775 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7779 SUBST (XEXP (x
, 0), lhs
);
7780 SUBST (XEXP (x
, 1), rhs
);
7783 return gen_lowpart (mode
, new_rtx
);
7786 /* If the second operand is not a constant, we can't do anything
7788 if (!CONST_INT_P (XEXP (x
, 1)))
7791 /* If the constant is a power of two minus one and the first operand
7792 is a logical right shift, make an extraction. */
7793 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7794 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7796 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7797 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7798 0, in_code
== COMPARE
);
7801 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7802 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7803 && subreg_lowpart_p (XEXP (x
, 0))
7804 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7805 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7807 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7809 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7810 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7811 0, in_code
== COMPARE
);
7813 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7814 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7815 || GET_CODE (XEXP (x
, 0)) == IOR
)
7816 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7817 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7818 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7820 /* Apply the distributive law, and then try to make extractions. */
7821 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7822 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7824 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7826 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7829 /* If we are have (and (rotate X C) M) and C is larger than the number
7830 of bits in M, this is an extraction. */
7832 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7833 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7834 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7835 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7837 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7838 new_rtx
= make_extraction (mode
, new_rtx
,
7839 (GET_MODE_PRECISION (mode
)
7840 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7841 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7844 /* On machines without logical shifts, if the operand of the AND is
7845 a logical shift and our mask turns off all the propagated sign
7846 bits, we can replace the logical shift with an arithmetic shift. */
7847 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7848 && !have_insn_for (LSHIFTRT
, mode
)
7849 && have_insn_for (ASHIFTRT
, mode
)
7850 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7851 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7852 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7853 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7855 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7857 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7858 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7860 gen_rtx_ASHIFTRT (mode
,
7861 make_compound_operation
7862 (XEXP (XEXP (x
, 0), 0), next_code
),
7863 XEXP (XEXP (x
, 0), 1)));
7866 /* If the constant is one less than a power of two, this might be
7867 representable by an extraction even if no shift is present.
7868 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7869 we are in a COMPARE. */
7870 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7871 new_rtx
= make_extraction (mode
,
7872 make_compound_operation (XEXP (x
, 0),
7874 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7876 /* If we are in a comparison and this is an AND with a power of two,
7877 convert this into the appropriate bit extract. */
7878 else if (in_code
== COMPARE
7879 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7880 new_rtx
= make_extraction (mode
,
7881 make_compound_operation (XEXP (x
, 0),
7883 i
, NULL_RTX
, 1, 1, 0, 1);
7888 /* If the sign bit is known to be zero, replace this with an
7889 arithmetic shift. */
7890 if (have_insn_for (ASHIFTRT
, mode
)
7891 && ! have_insn_for (LSHIFTRT
, mode
)
7892 && mode_width
<= HOST_BITS_PER_WIDE_INT
7893 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7895 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7896 make_compound_operation (XEXP (x
, 0),
7902 /* ... fall through ... */
7908 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7909 this is a SIGN_EXTRACT. */
7910 if (CONST_INT_P (rhs
)
7911 && GET_CODE (lhs
) == ASHIFT
7912 && CONST_INT_P (XEXP (lhs
, 1))
7913 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7914 && INTVAL (XEXP (lhs
, 1)) >= 0
7915 && INTVAL (rhs
) < mode_width
)
7917 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7918 new_rtx
= make_extraction (mode
, new_rtx
,
7919 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7920 NULL_RTX
, mode_width
- INTVAL (rhs
),
7921 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7925 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7926 If so, try to merge the shifts into a SIGN_EXTEND. We could
7927 also do this for some cases of SIGN_EXTRACT, but it doesn't
7928 seem worth the effort; the case checked for occurs on Alpha. */
7931 && ! (GET_CODE (lhs
) == SUBREG
7932 && (OBJECT_P (SUBREG_REG (lhs
))))
7933 && CONST_INT_P (rhs
)
7934 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7935 && INTVAL (rhs
) < mode_width
7936 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7937 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7938 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7939 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7944 /* Call ourselves recursively on the inner expression. If we are
7945 narrowing the object and it has a different RTL code from
7946 what it originally did, do this SUBREG as a force_to_mode. */
7948 rtx inner
= SUBREG_REG (x
), simplified
;
7949 enum rtx_code subreg_code
= in_code
;
7951 /* If in_code is COMPARE, it isn't always safe to pass it through
7952 to the recursive make_compound_operation call. */
7953 if (subreg_code
== COMPARE
7954 && (!subreg_lowpart_p (x
)
7955 || GET_CODE (inner
) == SUBREG
7956 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7957 is (const_int 0), rather than
7958 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7959 || (GET_CODE (inner
) == AND
7960 && CONST_INT_P (XEXP (inner
, 1))
7961 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7962 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7963 >= GET_MODE_BITSIZE (mode
))))
7966 tem
= make_compound_operation (inner
, subreg_code
);
7969 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7973 if (GET_CODE (tem
) != GET_CODE (inner
)
7974 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7975 && subreg_lowpart_p (x
))
7978 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7980 /* If we have something other than a SUBREG, we might have
7981 done an expansion, so rerun ourselves. */
7982 if (GET_CODE (newer
) != SUBREG
)
7983 newer
= make_compound_operation (newer
, in_code
);
7985 /* force_to_mode can expand compounds. If it just re-expanded the
7986 compound, use gen_lowpart to convert to the desired mode. */
7987 if (rtx_equal_p (newer
, x
)
7988 /* Likewise if it re-expanded the compound only partially.
7989 This happens for SUBREG of ZERO_EXTRACT if they extract
7990 the same number of bits. */
7991 || (GET_CODE (newer
) == SUBREG
7992 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7993 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7994 && GET_CODE (inner
) == AND
7995 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7996 return gen_lowpart (GET_MODE (x
), tem
);
8012 x
= gen_lowpart (mode
, new_rtx
);
8013 code
= GET_CODE (x
);
8016 /* Now recursively process each operand of this operation. We need to
8017 handle ZERO_EXTEND specially so that we don't lose track of the
8019 if (GET_CODE (x
) == ZERO_EXTEND
)
8021 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8022 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8023 new_rtx
, GET_MODE (XEXP (x
, 0)));
8026 SUBST (XEXP (x
, 0), new_rtx
);
8030 fmt
= GET_RTX_FORMAT (code
);
8031 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8034 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8035 SUBST (XEXP (x
, i
), new_rtx
);
8037 else if (fmt
[i
] == 'E')
8038 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8040 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8041 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8045 /* If this is a commutative operation, the changes to the operands
8046 may have made it noncanonical. */
8047 if (COMMUTATIVE_ARITH_P (x
)
8048 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8051 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8052 SUBST (XEXP (x
, 1), tem
);
8058 /* Given M see if it is a value that would select a field of bits
8059 within an item, but not the entire word. Return -1 if not.
8060 Otherwise, return the starting position of the field, where 0 is the
8063 *PLEN is set to the length of the field. */
8066 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8068 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8069 int pos
= m
? ctz_hwi (m
) : -1;
8073 /* Now shift off the low-order zero bits and see if we have a
8074 power of two minus 1. */
8075 len
= exact_log2 ((m
>> pos
) + 1);
8084 /* If X refers to a register that equals REG in value, replace these
8085 references with REG. */
8087 canon_reg_for_combine (rtx x
, rtx reg
)
8094 enum rtx_code code
= GET_CODE (x
);
8095 switch (GET_RTX_CLASS (code
))
8098 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8099 if (op0
!= XEXP (x
, 0))
8100 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8105 case RTX_COMM_ARITH
:
8106 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8107 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8108 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8109 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8113 case RTX_COMM_COMPARE
:
8114 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8115 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8116 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8117 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8118 GET_MODE (op0
), op0
, op1
);
8122 case RTX_BITFIELD_OPS
:
8123 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8124 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8125 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8126 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8127 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8128 GET_MODE (op0
), op0
, op1
, op2
);
8133 if (rtx_equal_p (get_last_value (reg
), x
)
8134 || rtx_equal_p (reg
, get_last_value (x
)))
8143 fmt
= GET_RTX_FORMAT (code
);
8145 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8148 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8149 if (op
!= XEXP (x
, i
))
8159 else if (fmt
[i
] == 'E')
8162 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8164 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8165 if (op
!= XVECEXP (x
, i
, j
))
8172 XVECEXP (x
, i
, j
) = op
;
8183 /* Return X converted to MODE. If the value is already truncated to
8184 MODE we can just return a subreg even though in the general case we
8185 would need an explicit truncation. */
8188 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8190 if (!CONST_INT_P (x
)
8191 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8192 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8193 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8195 /* Bit-cast X into an integer mode. */
8196 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8197 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8198 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8202 return gen_lowpart (mode
, x
);
8205 /* See if X can be simplified knowing that we will only refer to it in
8206 MODE and will only refer to those bits that are nonzero in MASK.
8207 If other bits are being computed or if masking operations are done
8208 that select a superset of the bits in MASK, they can sometimes be
8211 Return a possibly simplified expression, but always convert X to
8212 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8214 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8215 are all off in X. This is used when X will be complemented, by either
8216 NOT, NEG, or XOR. */
8219 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8222 enum rtx_code code
= GET_CODE (x
);
8223 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8224 machine_mode op_mode
;
8225 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8228 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8229 code below will do the wrong thing since the mode of such an
8230 expression is VOIDmode.
8232 Also do nothing if X is a CLOBBER; this can happen if X was
8233 the return value from a call to gen_lowpart. */
8234 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8237 /* We want to perform the operation in its present mode unless we know
8238 that the operation is valid in MODE, in which case we do the operation
8240 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8241 && have_insn_for (code
, mode
))
8242 ? mode
: GET_MODE (x
));
8244 /* It is not valid to do a right-shift in a narrower mode
8245 than the one it came in with. */
8246 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8247 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8248 op_mode
= GET_MODE (x
);
8250 /* Truncate MASK to fit OP_MODE. */
8252 mask
&= GET_MODE_MASK (op_mode
);
8254 /* When we have an arithmetic operation, or a shift whose count we
8255 do not know, we need to assume that all bits up to the highest-order
8256 bit in MASK will be needed. This is how we form such a mask. */
8257 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8258 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8260 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8263 /* Determine what bits of X are guaranteed to be (non)zero. */
8264 nonzero
= nonzero_bits (x
, mode
);
8266 /* If none of the bits in X are needed, return a zero. */
8267 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8270 /* If X is a CONST_INT, return a new one. Do this here since the
8271 test below will fail. */
8272 if (CONST_INT_P (x
))
8274 if (SCALAR_INT_MODE_P (mode
))
8275 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8278 x
= GEN_INT (INTVAL (x
) & mask
);
8279 return gen_lowpart_common (mode
, x
);
8283 /* If X is narrower than MODE and we want all the bits in X's mode, just
8284 get X in the proper mode. */
8285 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8286 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8287 return gen_lowpart (mode
, x
);
8289 /* We can ignore the effect of a SUBREG if it narrows the mode or
8290 if the constant masks to zero all the bits the mode doesn't have. */
8291 if (GET_CODE (x
) == SUBREG
8292 && subreg_lowpart_p (x
)
8293 && ((GET_MODE_SIZE (GET_MODE (x
))
8294 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8296 & GET_MODE_MASK (GET_MODE (x
))
8297 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8298 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8300 /* The arithmetic simplifications here only work for scalar integer modes. */
8301 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8302 return gen_lowpart_or_truncate (mode
, x
);
8307 /* If X is a (clobber (const_int)), return it since we know we are
8308 generating something that won't match. */
8315 x
= expand_compound_operation (x
);
8316 if (GET_CODE (x
) != code
)
8317 return force_to_mode (x
, mode
, mask
, next_select
);
8321 /* Similarly for a truncate. */
8322 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8325 /* If this is an AND with a constant, convert it into an AND
8326 whose constant is the AND of that constant with MASK. If it
8327 remains an AND of MASK, delete it since it is redundant. */
8329 if (CONST_INT_P (XEXP (x
, 1)))
8331 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8332 mask
& INTVAL (XEXP (x
, 1)));
8334 /* If X is still an AND, see if it is an AND with a mask that
8335 is just some low-order bits. If so, and it is MASK, we don't
8338 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8339 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8343 /* If it remains an AND, try making another AND with the bits
8344 in the mode mask that aren't in MASK turned on. If the
8345 constant in the AND is wide enough, this might make a
8346 cheaper constant. */
8348 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8349 && GET_MODE_MASK (GET_MODE (x
)) != mask
8350 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8352 unsigned HOST_WIDE_INT cval
8353 = UINTVAL (XEXP (x
, 1))
8354 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8357 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8358 gen_int_mode (cval
, GET_MODE (x
)));
8359 if (set_src_cost (y
, optimize_this_for_speed_p
)
8360 < set_src_cost (x
, optimize_this_for_speed_p
))
8370 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8371 low-order bits (as in an alignment operation) and FOO is already
8372 aligned to that boundary, mask C1 to that boundary as well.
8373 This may eliminate that PLUS and, later, the AND. */
8376 unsigned int width
= GET_MODE_PRECISION (mode
);
8377 unsigned HOST_WIDE_INT smask
= mask
;
8379 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8380 number, sign extend it. */
8382 if (width
< HOST_BITS_PER_WIDE_INT
8383 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8384 smask
|= HOST_WIDE_INT_M1U
<< width
;
8386 if (CONST_INT_P (XEXP (x
, 1))
8387 && exact_log2 (- smask
) >= 0
8388 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8389 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8390 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8391 (INTVAL (XEXP (x
, 1)) & smask
)),
8392 mode
, smask
, next_select
);
8395 /* ... fall through ... */
8398 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8399 most significant bit in MASK since carries from those bits will
8400 affect the bits we are interested in. */
8405 /* If X is (minus C Y) where C's least set bit is larger than any bit
8406 in the mask, then we may replace with (neg Y). */
8407 if (CONST_INT_P (XEXP (x
, 0))
8408 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8410 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8412 return force_to_mode (x
, mode
, mask
, next_select
);
8415 /* Similarly, if C contains every bit in the fuller_mask, then we may
8416 replace with (not Y). */
8417 if (CONST_INT_P (XEXP (x
, 0))
8418 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8420 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8421 XEXP (x
, 1), GET_MODE (x
));
8422 return force_to_mode (x
, mode
, mask
, next_select
);
8430 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8431 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8432 operation which may be a bitfield extraction. Ensure that the
8433 constant we form is not wider than the mode of X. */
8435 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8436 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8437 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8438 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8439 && CONST_INT_P (XEXP (x
, 1))
8440 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8441 + floor_log2 (INTVAL (XEXP (x
, 1))))
8442 < GET_MODE_PRECISION (GET_MODE (x
)))
8443 && (UINTVAL (XEXP (x
, 1))
8444 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8446 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8447 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8449 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8450 XEXP (XEXP (x
, 0), 0), temp
);
8451 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8452 XEXP (XEXP (x
, 0), 1));
8453 return force_to_mode (x
, mode
, mask
, next_select
);
8457 /* For most binary operations, just propagate into the operation and
8458 change the mode if we have an operation of that mode. */
8460 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8461 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8463 /* If we ended up truncating both operands, truncate the result of the
8464 operation instead. */
8465 if (GET_CODE (op0
) == TRUNCATE
8466 && GET_CODE (op1
) == TRUNCATE
)
8468 op0
= XEXP (op0
, 0);
8469 op1
= XEXP (op1
, 0);
8472 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8473 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8475 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8476 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8480 /* For left shifts, do the same, but just for the first operand.
8481 However, we cannot do anything with shifts where we cannot
8482 guarantee that the counts are smaller than the size of the mode
8483 because such a count will have a different meaning in a
8486 if (! (CONST_INT_P (XEXP (x
, 1))
8487 && INTVAL (XEXP (x
, 1)) >= 0
8488 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8489 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8490 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8491 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8494 /* If the shift count is a constant and we can do arithmetic in
8495 the mode of the shift, refine which bits we need. Otherwise, use the
8496 conservative form of the mask. */
8497 if (CONST_INT_P (XEXP (x
, 1))
8498 && INTVAL (XEXP (x
, 1)) >= 0
8499 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8500 && HWI_COMPUTABLE_MODE_P (op_mode
))
8501 mask
>>= INTVAL (XEXP (x
, 1));
8505 op0
= gen_lowpart_or_truncate (op_mode
,
8506 force_to_mode (XEXP (x
, 0), op_mode
,
8507 mask
, next_select
));
8509 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8510 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8514 /* Here we can only do something if the shift count is a constant,
8515 this shift constant is valid for the host, and we can do arithmetic
8518 if (CONST_INT_P (XEXP (x
, 1))
8519 && INTVAL (XEXP (x
, 1)) >= 0
8520 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8521 && HWI_COMPUTABLE_MODE_P (op_mode
))
8523 rtx inner
= XEXP (x
, 0);
8524 unsigned HOST_WIDE_INT inner_mask
;
8526 /* Select the mask of the bits we need for the shift operand. */
8527 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8529 /* We can only change the mode of the shift if we can do arithmetic
8530 in the mode of the shift and INNER_MASK is no wider than the
8531 width of X's mode. */
8532 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8533 op_mode
= GET_MODE (x
);
8535 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8537 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8538 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8541 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8542 shift and AND produces only copies of the sign bit (C2 is one less
8543 than a power of two), we can do this with just a shift. */
8545 if (GET_CODE (x
) == LSHIFTRT
8546 && CONST_INT_P (XEXP (x
, 1))
8547 /* The shift puts one of the sign bit copies in the least significant
8549 && ((INTVAL (XEXP (x
, 1))
8550 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8551 >= GET_MODE_PRECISION (GET_MODE (x
)))
8552 && exact_log2 (mask
+ 1) >= 0
8553 /* Number of bits left after the shift must be more than the mask
8555 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8556 <= GET_MODE_PRECISION (GET_MODE (x
)))
8557 /* Must be more sign bit copies than the mask needs. */
8558 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8559 >= exact_log2 (mask
+ 1)))
8560 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8561 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8562 - exact_log2 (mask
+ 1)));
8567 /* If we are just looking for the sign bit, we don't need this shift at
8568 all, even if it has a variable count. */
8569 if (val_signbit_p (GET_MODE (x
), mask
))
8570 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8572 /* If this is a shift by a constant, get a mask that contains those bits
8573 that are not copies of the sign bit. We then have two cases: If
8574 MASK only includes those bits, this can be a logical shift, which may
8575 allow simplifications. If MASK is a single-bit field not within
8576 those bits, we are requesting a copy of the sign bit and hence can
8577 shift the sign bit to the appropriate location. */
8579 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8580 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8584 /* If the considered data is wider than HOST_WIDE_INT, we can't
8585 represent a mask for all its bits in a single scalar.
8586 But we only care about the lower bits, so calculate these. */
8588 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8590 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8592 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8593 is the number of bits a full-width mask would have set.
8594 We need only shift if these are fewer than nonzero can
8595 hold. If not, we must keep all bits set in nonzero. */
8597 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8598 < HOST_BITS_PER_WIDE_INT
)
8599 nonzero
>>= INTVAL (XEXP (x
, 1))
8600 + HOST_BITS_PER_WIDE_INT
8601 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8605 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8606 nonzero
>>= INTVAL (XEXP (x
, 1));
8609 if ((mask
& ~nonzero
) == 0)
8611 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8612 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8613 if (GET_CODE (x
) != ASHIFTRT
)
8614 return force_to_mode (x
, mode
, mask
, next_select
);
8617 else if ((i
= exact_log2 (mask
)) >= 0)
8619 x
= simplify_shift_const
8620 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8621 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8623 if (GET_CODE (x
) != ASHIFTRT
)
8624 return force_to_mode (x
, mode
, mask
, next_select
);
8628 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8629 even if the shift count isn't a constant. */
8631 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8632 XEXP (x
, 0), XEXP (x
, 1));
8636 /* If this is a zero- or sign-extension operation that just affects bits
8637 we don't care about, remove it. Be sure the call above returned
8638 something that is still a shift. */
8640 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8641 && CONST_INT_P (XEXP (x
, 1))
8642 && INTVAL (XEXP (x
, 1)) >= 0
8643 && (INTVAL (XEXP (x
, 1))
8644 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8645 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8646 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8647 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8654 /* If the shift count is constant and we can do computations
8655 in the mode of X, compute where the bits we care about are.
8656 Otherwise, we can't do anything. Don't change the mode of
8657 the shift or propagate MODE into the shift, though. */
8658 if (CONST_INT_P (XEXP (x
, 1))
8659 && INTVAL (XEXP (x
, 1)) >= 0)
8661 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8663 gen_int_mode (mask
, GET_MODE (x
)),
8665 if (temp
&& CONST_INT_P (temp
))
8666 x
= simplify_gen_binary (code
, GET_MODE (x
),
8667 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8668 INTVAL (temp
), next_select
),
8674 /* If we just want the low-order bit, the NEG isn't needed since it
8675 won't change the low-order bit. */
8677 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8679 /* We need any bits less significant than the most significant bit in
8680 MASK since carries from those bits will affect the bits we are
8686 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8687 same as the XOR case above. Ensure that the constant we form is not
8688 wider than the mode of X. */
8690 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8691 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8692 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8693 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8694 < GET_MODE_PRECISION (GET_MODE (x
)))
8695 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8697 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8699 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8700 XEXP (XEXP (x
, 0), 0), temp
);
8701 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8702 temp
, XEXP (XEXP (x
, 0), 1));
8704 return force_to_mode (x
, mode
, mask
, next_select
);
8707 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8708 use the full mask inside the NOT. */
8712 op0
= gen_lowpart_or_truncate (op_mode
,
8713 force_to_mode (XEXP (x
, 0), mode
, mask
,
8715 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8716 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8720 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8721 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8722 which is equal to STORE_FLAG_VALUE. */
8723 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8724 && XEXP (x
, 1) == const0_rtx
8725 && GET_MODE (XEXP (x
, 0)) == mode
8726 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8727 && (nonzero_bits (XEXP (x
, 0), mode
)
8728 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8729 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8734 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8735 written in a narrower mode. We play it safe and do not do so. */
8737 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8738 force_to_mode (XEXP (x
, 1), mode
,
8739 mask
, next_select
));
8740 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8741 force_to_mode (XEXP (x
, 2), mode
,
8742 mask
, next_select
));
8743 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8744 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8745 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8753 /* Ensure we return a value of the proper mode. */
8754 return gen_lowpart_or_truncate (mode
, x
);
8757 /* Return nonzero if X is an expression that has one of two values depending on
8758 whether some other value is zero or nonzero. In that case, we return the
8759 value that is being tested, *PTRUE is set to the value if the rtx being
8760 returned has a nonzero value, and *PFALSE is set to the other alternative.
8762 If we return zero, we set *PTRUE and *PFALSE to X. */
8765 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8767 machine_mode mode
= GET_MODE (x
);
8768 enum rtx_code code
= GET_CODE (x
);
8769 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8770 unsigned HOST_WIDE_INT nz
;
8772 /* If we are comparing a value against zero, we are done. */
8773 if ((code
== NE
|| code
== EQ
)
8774 && XEXP (x
, 1) == const0_rtx
)
8776 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8777 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8781 /* If this is a unary operation whose operand has one of two values, apply
8782 our opcode to compute those values. */
8783 else if (UNARY_P (x
)
8784 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8786 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8787 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8788 GET_MODE (XEXP (x
, 0)));
8792 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8793 make can't possibly match and would suppress other optimizations. */
8794 else if (code
== COMPARE
)
8797 /* If this is a binary operation, see if either side has only one of two
8798 values. If either one does or if both do and they are conditional on
8799 the same value, compute the new true and false values. */
8800 else if (BINARY_P (x
))
8802 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8803 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8805 if ((cond0
!= 0 || cond1
!= 0)
8806 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8808 /* If if_then_else_cond returned zero, then true/false are the
8809 same rtl. We must copy one of them to prevent invalid rtl
8812 true0
= copy_rtx (true0
);
8813 else if (cond1
== 0)
8814 true1
= copy_rtx (true1
);
8816 if (COMPARISON_P (x
))
8818 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8820 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8825 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8826 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8829 return cond0
? cond0
: cond1
;
8832 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8833 operands is zero when the other is nonzero, and vice-versa,
8834 and STORE_FLAG_VALUE is 1 or -1. */
8836 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8837 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8839 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8841 rtx op0
= XEXP (XEXP (x
, 0), 1);
8842 rtx op1
= XEXP (XEXP (x
, 1), 1);
8844 cond0
= XEXP (XEXP (x
, 0), 0);
8845 cond1
= XEXP (XEXP (x
, 1), 0);
8847 if (COMPARISON_P (cond0
)
8848 && COMPARISON_P (cond1
)
8849 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8850 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8851 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8852 || ((swap_condition (GET_CODE (cond0
))
8853 == reversed_comparison_code (cond1
, NULL
))
8854 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8855 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8856 && ! side_effects_p (x
))
8858 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8859 *pfalse
= simplify_gen_binary (MULT
, mode
,
8861 ? simplify_gen_unary (NEG
, mode
,
8869 /* Similarly for MULT, AND and UMIN, except that for these the result
8871 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8872 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8873 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8875 cond0
= XEXP (XEXP (x
, 0), 0);
8876 cond1
= XEXP (XEXP (x
, 1), 0);
8878 if (COMPARISON_P (cond0
)
8879 && COMPARISON_P (cond1
)
8880 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8881 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8882 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8883 || ((swap_condition (GET_CODE (cond0
))
8884 == reversed_comparison_code (cond1
, NULL
))
8885 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8886 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8887 && ! side_effects_p (x
))
8889 *ptrue
= *pfalse
= const0_rtx
;
8895 else if (code
== IF_THEN_ELSE
)
8897 /* If we have IF_THEN_ELSE already, extract the condition and
8898 canonicalize it if it is NE or EQ. */
8899 cond0
= XEXP (x
, 0);
8900 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8901 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8902 return XEXP (cond0
, 0);
8903 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8905 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8906 return XEXP (cond0
, 0);
8912 /* If X is a SUBREG, we can narrow both the true and false values
8913 if the inner expression, if there is a condition. */
8914 else if (code
== SUBREG
8915 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8918 true0
= simplify_gen_subreg (mode
, true0
,
8919 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8920 false0
= simplify_gen_subreg (mode
, false0
,
8921 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8922 if (true0
&& false0
)
8930 /* If X is a constant, this isn't special and will cause confusions
8931 if we treat it as such. Likewise if it is equivalent to a constant. */
8932 else if (CONSTANT_P (x
)
8933 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8936 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8937 will be least confusing to the rest of the compiler. */
8938 else if (mode
== BImode
)
8940 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8944 /* If X is known to be either 0 or -1, those are the true and
8945 false values when testing X. */
8946 else if (x
== constm1_rtx
|| x
== const0_rtx
8947 || (mode
!= VOIDmode
8948 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8950 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8954 /* Likewise for 0 or a single bit. */
8955 else if (HWI_COMPUTABLE_MODE_P (mode
)
8956 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8958 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8962 /* Otherwise fail; show no condition with true and false values the same. */
8963 *ptrue
= *pfalse
= x
;
8967 /* Return the value of expression X given the fact that condition COND
8968 is known to be true when applied to REG as its first operand and VAL
8969 as its second. X is known to not be shared and so can be modified in
8972 We only handle the simplest cases, and specifically those cases that
8973 arise with IF_THEN_ELSE expressions. */
8976 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8978 enum rtx_code code
= GET_CODE (x
);
8983 if (side_effects_p (x
))
8986 /* If either operand of the condition is a floating point value,
8987 then we have to avoid collapsing an EQ comparison. */
8989 && rtx_equal_p (x
, reg
)
8990 && ! FLOAT_MODE_P (GET_MODE (x
))
8991 && ! FLOAT_MODE_P (GET_MODE (val
)))
8994 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8997 /* If X is (abs REG) and we know something about REG's relationship
8998 with zero, we may be able to simplify this. */
9000 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9003 case GE
: case GT
: case EQ
:
9006 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9008 GET_MODE (XEXP (x
, 0)));
9013 /* The only other cases we handle are MIN, MAX, and comparisons if the
9014 operands are the same as REG and VAL. */
9016 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9018 if (rtx_equal_p (XEXP (x
, 0), val
))
9019 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
9021 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9023 if (COMPARISON_P (x
))
9025 if (comparison_dominates_p (cond
, code
))
9026 return const_true_rtx
;
9028 code
= reversed_comparison_code (x
, NULL
);
9030 && comparison_dominates_p (cond
, code
))
9035 else if (code
== SMAX
|| code
== SMIN
9036 || code
== UMIN
|| code
== UMAX
)
9038 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9040 /* Do not reverse the condition when it is NE or EQ.
9041 This is because we cannot conclude anything about
9042 the value of 'SMAX (x, y)' when x is not equal to y,
9043 but we can when x equals y. */
9044 if ((code
== SMAX
|| code
== UMAX
)
9045 && ! (cond
== EQ
|| cond
== NE
))
9046 cond
= reverse_condition (cond
);
9051 return unsignedp
? x
: XEXP (x
, 1);
9053 return unsignedp
? x
: XEXP (x
, 0);
9055 return unsignedp
? XEXP (x
, 1) : x
;
9057 return unsignedp
? XEXP (x
, 0) : x
;
9064 else if (code
== SUBREG
)
9066 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9067 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9069 if (SUBREG_REG (x
) != r
)
9071 /* We must simplify subreg here, before we lose track of the
9072 original inner_mode. */
9073 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9074 inner_mode
, SUBREG_BYTE (x
));
9078 SUBST (SUBREG_REG (x
), r
);
9083 /* We don't have to handle SIGN_EXTEND here, because even in the
9084 case of replacing something with a modeless CONST_INT, a
9085 CONST_INT is already (supposed to be) a valid sign extension for
9086 its narrower mode, which implies it's already properly
9087 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9088 story is different. */
9089 else if (code
== ZERO_EXTEND
)
9091 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9092 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9094 if (XEXP (x
, 0) != r
)
9096 /* We must simplify the zero_extend here, before we lose
9097 track of the original inner_mode. */
9098 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9103 SUBST (XEXP (x
, 0), r
);
9109 fmt
= GET_RTX_FORMAT (code
);
9110 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9113 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9114 else if (fmt
[i
] == 'E')
9115 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9116 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9123 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9124 assignment as a field assignment. */
9127 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
9129 if (x
== y
|| rtx_equal_p (x
, y
))
9132 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9135 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9136 Note that all SUBREGs of MEM are paradoxical; otherwise they
9137 would have been rewritten. */
9138 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9139 && MEM_P (SUBREG_REG (y
))
9140 && rtx_equal_p (SUBREG_REG (y
),
9141 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9144 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9145 && MEM_P (SUBREG_REG (x
))
9146 && rtx_equal_p (SUBREG_REG (x
),
9147 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9150 /* We used to see if get_last_value of X and Y were the same but that's
9151 not correct. In one direction, we'll cause the assignment to have
9152 the wrong destination and in the case, we'll import a register into this
9153 insn that might have already have been dead. So fail if none of the
9154 above cases are true. */
9158 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9159 Return that assignment if so.
9161 We only handle the most common cases. */
9164 make_field_assignment (rtx x
)
9166 rtx dest
= SET_DEST (x
);
9167 rtx src
= SET_SRC (x
);
9172 unsigned HOST_WIDE_INT len
;
9176 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9177 a clear of a one-bit field. We will have changed it to
9178 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9181 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9182 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9183 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9184 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9186 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9189 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9193 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9194 && subreg_lowpart_p (XEXP (src
, 0))
9195 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9196 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9197 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9198 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9199 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9200 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9202 assign
= make_extraction (VOIDmode
, dest
, 0,
9203 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9206 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9210 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9212 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9213 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9214 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9216 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9219 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9223 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9224 SRC is an AND with all bits of that field set, then we can discard
9226 if (GET_CODE (dest
) == ZERO_EXTRACT
9227 && CONST_INT_P (XEXP (dest
, 1))
9228 && GET_CODE (src
) == AND
9229 && CONST_INT_P (XEXP (src
, 1)))
9231 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9232 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9233 unsigned HOST_WIDE_INT ze_mask
;
9235 if (width
>= HOST_BITS_PER_WIDE_INT
)
9238 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9240 /* Complete overlap. We can remove the source AND. */
9241 if ((and_mask
& ze_mask
) == ze_mask
)
9242 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9244 /* Partial overlap. We can reduce the source AND. */
9245 if ((and_mask
& ze_mask
) != and_mask
)
9247 mode
= GET_MODE (src
);
9248 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9249 gen_int_mode (and_mask
& ze_mask
, mode
));
9250 return gen_rtx_SET (VOIDmode
, dest
, src
);
9254 /* The other case we handle is assignments into a constant-position
9255 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9256 a mask that has all one bits except for a group of zero bits and
9257 OTHER is known to have zeros where C1 has ones, this is such an
9258 assignment. Compute the position and length from C1. Shift OTHER
9259 to the appropriate position, force it to the required mode, and
9260 make the extraction. Check for the AND in both operands. */
9262 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9265 rhs
= expand_compound_operation (XEXP (src
, 0));
9266 lhs
= expand_compound_operation (XEXP (src
, 1));
9268 if (GET_CODE (rhs
) == AND
9269 && CONST_INT_P (XEXP (rhs
, 1))
9270 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9271 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9272 else if (GET_CODE (lhs
) == AND
9273 && CONST_INT_P (XEXP (lhs
, 1))
9274 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9275 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9279 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9280 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9281 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9282 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9285 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9289 /* The mode to use for the source is the mode of the assignment, or of
9290 what is inside a possible STRICT_LOW_PART. */
9291 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9292 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9294 /* Shift OTHER right POS places and make it the source, restricting it
9295 to the proper length and mode. */
9297 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9301 src
= force_to_mode (src
, mode
,
9302 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9303 ? ~(unsigned HOST_WIDE_INT
) 0
9304 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9307 /* If SRC is masked by an AND that does not make a difference in
9308 the value being stored, strip it. */
9309 if (GET_CODE (assign
) == ZERO_EXTRACT
9310 && CONST_INT_P (XEXP (assign
, 1))
9311 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9312 && GET_CODE (src
) == AND
9313 && CONST_INT_P (XEXP (src
, 1))
9314 && UINTVAL (XEXP (src
, 1))
9315 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9316 src
= XEXP (src
, 0);
9318 return gen_rtx_SET (VOIDmode
, assign
, src
);
9321 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9325 apply_distributive_law (rtx x
)
9327 enum rtx_code code
= GET_CODE (x
);
9328 enum rtx_code inner_code
;
9329 rtx lhs
, rhs
, other
;
9332 /* Distributivity is not true for floating point as it can change the
9333 value. So we don't do it unless -funsafe-math-optimizations. */
9334 if (FLOAT_MODE_P (GET_MODE (x
))
9335 && ! flag_unsafe_math_optimizations
)
9338 /* The outer operation can only be one of the following: */
9339 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9340 && code
!= PLUS
&& code
!= MINUS
)
9346 /* If either operand is a primitive we can't do anything, so get out
9348 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9351 lhs
= expand_compound_operation (lhs
);
9352 rhs
= expand_compound_operation (rhs
);
9353 inner_code
= GET_CODE (lhs
);
9354 if (inner_code
!= GET_CODE (rhs
))
9357 /* See if the inner and outer operations distribute. */
9364 /* These all distribute except over PLUS. */
9365 if (code
== PLUS
|| code
== MINUS
)
9370 if (code
!= PLUS
&& code
!= MINUS
)
9375 /* This is also a multiply, so it distributes over everything. */
9378 /* This used to handle SUBREG, but this turned out to be counter-
9379 productive, since (subreg (op ...)) usually is not handled by
9380 insn patterns, and this "optimization" therefore transformed
9381 recognizable patterns into unrecognizable ones. Therefore the
9382 SUBREG case was removed from here.
9384 It is possible that distributing SUBREG over arithmetic operations
9385 leads to an intermediate result than can then be optimized further,
9386 e.g. by moving the outer SUBREG to the other side of a SET as done
9387 in simplify_set. This seems to have been the original intent of
9388 handling SUBREGs here.
9390 However, with current GCC this does not appear to actually happen,
9391 at least on major platforms. If some case is found where removing
9392 the SUBREG case here prevents follow-on optimizations, distributing
9393 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9399 /* Set LHS and RHS to the inner operands (A and B in the example
9400 above) and set OTHER to the common operand (C in the example).
9401 There is only one way to do this unless the inner operation is
9403 if (COMMUTATIVE_ARITH_P (lhs
)
9404 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9405 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9406 else if (COMMUTATIVE_ARITH_P (lhs
)
9407 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9408 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9409 else if (COMMUTATIVE_ARITH_P (lhs
)
9410 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9411 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9412 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9413 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9417 /* Form the new inner operation, seeing if it simplifies first. */
9418 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9420 /* There is one exception to the general way of distributing:
9421 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9422 if (code
== XOR
&& inner_code
== IOR
)
9425 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9428 /* We may be able to continuing distributing the result, so call
9429 ourselves recursively on the inner operation before forming the
9430 outer operation, which we return. */
9431 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9432 apply_distributive_law (tem
), other
);
9435 /* See if X is of the form (* (+ A B) C), and if so convert to
9436 (+ (* A C) (* B C)) and try to simplify.
9438 Most of the time, this results in no change. However, if some of
9439 the operands are the same or inverses of each other, simplifications
9442 For example, (and (ior A B) (not B)) can occur as the result of
9443 expanding a bit field assignment. When we apply the distributive
9444 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9445 which then simplifies to (and (A (not B))).
9447 Note that no checks happen on the validity of applying the inverse
9448 distributive law. This is pointless since we can do it in the
9449 few places where this routine is called.
9451 N is the index of the term that is decomposed (the arithmetic operation,
9452 i.e. (+ A B) in the first example above). !N is the index of the term that
9453 is distributed, i.e. of C in the first example above. */
9455 distribute_and_simplify_rtx (rtx x
, int n
)
9458 enum rtx_code outer_code
, inner_code
;
9459 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9461 /* Distributivity is not true for floating point as it can change the
9462 value. So we don't do it unless -funsafe-math-optimizations. */
9463 if (FLOAT_MODE_P (GET_MODE (x
))
9464 && ! flag_unsafe_math_optimizations
)
9467 decomposed
= XEXP (x
, n
);
9468 if (!ARITHMETIC_P (decomposed
))
9471 mode
= GET_MODE (x
);
9472 outer_code
= GET_CODE (x
);
9473 distributed
= XEXP (x
, !n
);
9475 inner_code
= GET_CODE (decomposed
);
9476 inner_op0
= XEXP (decomposed
, 0);
9477 inner_op1
= XEXP (decomposed
, 1);
9479 /* Special case (and (xor B C) (not A)), which is equivalent to
9480 (xor (ior A B) (ior A C)) */
9481 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9483 distributed
= XEXP (distributed
, 0);
9489 /* Distribute the second term. */
9490 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9491 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9495 /* Distribute the first term. */
9496 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9497 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9500 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9502 if (GET_CODE (tmp
) != outer_code
9503 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9504 < set_src_cost (x
, optimize_this_for_speed_p
)))
9510 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9511 in MODE. Return an equivalent form, if different from (and VAROP
9512 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9515 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9516 unsigned HOST_WIDE_INT constop
)
9518 unsigned HOST_WIDE_INT nonzero
;
9519 unsigned HOST_WIDE_INT orig_constop
;
9524 orig_constop
= constop
;
9525 if (GET_CODE (varop
) == CLOBBER
)
9528 /* Simplify VAROP knowing that we will be only looking at some of the
9531 Note by passing in CONSTOP, we guarantee that the bits not set in
9532 CONSTOP are not significant and will never be examined. We must
9533 ensure that is the case by explicitly masking out those bits
9534 before returning. */
9535 varop
= force_to_mode (varop
, mode
, constop
, 0);
9537 /* If VAROP is a CLOBBER, we will fail so return it. */
9538 if (GET_CODE (varop
) == CLOBBER
)
9541 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9542 to VAROP and return the new constant. */
9543 if (CONST_INT_P (varop
))
9544 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9546 /* See what bits may be nonzero in VAROP. Unlike the general case of
9547 a call to nonzero_bits, here we don't care about bits outside
9550 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9552 /* Turn off all bits in the constant that are known to already be zero.
9553 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9554 which is tested below. */
9558 /* If we don't have any bits left, return zero. */
9562 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9563 a power of two, we can replace this with an ASHIFT. */
9564 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9565 && (i
= exact_log2 (constop
)) >= 0)
9566 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9568 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9569 or XOR, then try to apply the distributive law. This may eliminate
9570 operations if either branch can be simplified because of the AND.
9571 It may also make some cases more complex, but those cases probably
9572 won't match a pattern either with or without this. */
9574 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9578 apply_distributive_law
9579 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9580 simplify_and_const_int (NULL_RTX
,
9584 simplify_and_const_int (NULL_RTX
,
9589 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9590 the AND and see if one of the operands simplifies to zero. If so, we
9591 may eliminate it. */
9593 if (GET_CODE (varop
) == PLUS
9594 && exact_log2 (constop
+ 1) >= 0)
9598 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9599 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9600 if (o0
== const0_rtx
)
9602 if (o1
== const0_rtx
)
9606 /* Make a SUBREG if necessary. If we can't make it, fail. */
9607 varop
= gen_lowpart (mode
, varop
);
9608 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9611 /* If we are only masking insignificant bits, return VAROP. */
9612 if (constop
== nonzero
)
9615 if (varop
== orig_varop
&& constop
== orig_constop
)
9618 /* Otherwise, return an AND. */
9619 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9623 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9626 Return an equivalent form, if different from X. Otherwise, return X. If
9627 X is zero, we are to always construct the equivalent form. */
9630 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9631 unsigned HOST_WIDE_INT constop
)
9633 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9638 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9639 gen_int_mode (constop
, mode
));
9640 if (GET_MODE (x
) != mode
)
9641 x
= gen_lowpart (mode
, x
);
9645 /* Given a REG, X, compute which bits in X can be nonzero.
9646 We don't care about bits outside of those defined in MODE.
9648 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9649 a shift, AND, or zero_extract, we can do better. */
9652 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9653 const_rtx known_x ATTRIBUTE_UNUSED
,
9654 machine_mode known_mode ATTRIBUTE_UNUSED
,
9655 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9656 unsigned HOST_WIDE_INT
*nonzero
)
9661 /* If X is a register whose nonzero bits value is current, use it.
9662 Otherwise, if X is a register whose value we can find, use that
9663 value. Otherwise, use the previously-computed global nonzero bits
9664 for this register. */
9666 rsp
= ®_stat
[REGNO (x
)];
9667 if (rsp
->last_set_value
!= 0
9668 && (rsp
->last_set_mode
== mode
9669 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9670 && GET_MODE_CLASS (mode
) == MODE_INT
))
9671 && ((rsp
->last_set_label
>= label_tick_ebb_start
9672 && rsp
->last_set_label
< label_tick
)
9673 || (rsp
->last_set_label
== label_tick
9674 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9675 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9676 && REG_N_SETS (REGNO (x
)) == 1
9678 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9681 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9683 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9684 /* We don't know anything about the upper bits. */
9685 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9691 tem
= get_last_value (x
);
9695 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9696 /* If X is narrower than MODE and TEM is a non-negative
9697 constant that would appear negative in the mode of X,
9698 sign-extend it for use in reg_nonzero_bits because some
9699 machines (maybe most) will actually do the sign-extension
9700 and this is the conservative approach.
9702 ??? For 2.5, try to tighten up the MD files in this regard
9703 instead of this kludge. */
9705 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9706 && CONST_INT_P (tem
)
9708 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9709 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9713 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9715 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9717 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9718 /* We don't know anything about the upper bits. */
9719 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9727 /* Return the number of bits at the high-order end of X that are known to
9728 be equal to the sign bit. X will be used in mode MODE; if MODE is
9729 VOIDmode, X will be used in its own mode. The returned value will always
9730 be between 1 and the number of bits in MODE. */
9733 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9734 const_rtx known_x ATTRIBUTE_UNUSED
,
9735 machine_mode known_mode
9737 unsigned int known_ret ATTRIBUTE_UNUSED
,
9738 unsigned int *result
)
9743 rsp
= ®_stat
[REGNO (x
)];
9744 if (rsp
->last_set_value
!= 0
9745 && rsp
->last_set_mode
== mode
9746 && ((rsp
->last_set_label
>= label_tick_ebb_start
9747 && rsp
->last_set_label
< label_tick
)
9748 || (rsp
->last_set_label
== label_tick
9749 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9750 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9751 && REG_N_SETS (REGNO (x
)) == 1
9753 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9756 *result
= rsp
->last_set_sign_bit_copies
;
9760 tem
= get_last_value (x
);
9764 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9765 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9766 *result
= rsp
->sign_bit_copies
;
9771 /* Return the number of "extended" bits there are in X, when interpreted
9772 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9773 unsigned quantities, this is the number of high-order zero bits.
9774 For signed quantities, this is the number of copies of the sign bit
9775 minus 1. In both case, this function returns the number of "spare"
9776 bits. For example, if two quantities for which this function returns
9777 at least 1 are added, the addition is known not to overflow.
9779 This function will always return 0 unless called during combine, which
9780 implies that it must be called from a define_split. */
9783 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9785 if (nonzero_sign_valid
== 0)
9789 ? (HWI_COMPUTABLE_MODE_P (mode
)
9790 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9791 - floor_log2 (nonzero_bits (x
, mode
)))
9793 : num_sign_bit_copies (x
, mode
) - 1);
9796 /* This function is called from `simplify_shift_const' to merge two
9797 outer operations. Specifically, we have already found that we need
9798 to perform operation *POP0 with constant *PCONST0 at the outermost
9799 position. We would now like to also perform OP1 with constant CONST1
9800 (with *POP0 being done last).
9802 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9803 the resulting operation. *PCOMP_P is set to 1 if we would need to
9804 complement the innermost operand, otherwise it is unchanged.
9806 MODE is the mode in which the operation will be done. No bits outside
9807 the width of this mode matter. It is assumed that the width of this mode
9808 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9810 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9811 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9812 result is simply *PCONST0.
9814 If the resulting operation cannot be expressed as one operation, we
9815 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9818 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9820 enum rtx_code op0
= *pop0
;
9821 HOST_WIDE_INT const0
= *pconst0
;
9823 const0
&= GET_MODE_MASK (mode
);
9824 const1
&= GET_MODE_MASK (mode
);
9826 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9830 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9833 if (op1
== UNKNOWN
|| op0
== SET
)
9836 else if (op0
== UNKNOWN
)
9837 op0
= op1
, const0
= const1
;
9839 else if (op0
== op1
)
9863 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9864 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9867 /* If the two constants aren't the same, we can't do anything. The
9868 remaining six cases can all be done. */
9869 else if (const0
!= const1
)
9877 /* (a & b) | b == b */
9879 else /* op1 == XOR */
9880 /* (a ^ b) | b == a | b */
9886 /* (a & b) ^ b == (~a) & b */
9887 op0
= AND
, *pcomp_p
= 1;
9888 else /* op1 == IOR */
9889 /* (a | b) ^ b == a & ~b */
9890 op0
= AND
, const0
= ~const0
;
9895 /* (a | b) & b == b */
9897 else /* op1 == XOR */
9898 /* (a ^ b) & b) == (~a) & b */
9905 /* Check for NO-OP cases. */
9906 const0
&= GET_MODE_MASK (mode
);
9908 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9910 else if (const0
== 0 && op0
== AND
)
9912 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9918 /* ??? Slightly redundant with the above mask, but not entirely.
9919 Moving this above means we'd have to sign-extend the mode mask
9920 for the final test. */
9921 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9922 *pconst0
= trunc_int_for_mode (const0
, mode
);
9927 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9928 the shift in. The original shift operation CODE is performed on OP in
9929 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9930 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9931 result of the shift is subject to operation OUTER_CODE with operand
9935 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9936 machine_mode orig_mode
, machine_mode mode
,
9937 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9939 if (orig_mode
== mode
)
9941 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9943 /* In general we can't perform in wider mode for right shift and rotate. */
9947 /* We can still widen if the bits brought in from the left are identical
9948 to the sign bit of ORIG_MODE. */
9949 if (num_sign_bit_copies (op
, mode
)
9950 > (unsigned) (GET_MODE_PRECISION (mode
)
9951 - GET_MODE_PRECISION (orig_mode
)))
9956 /* Similarly here but with zero bits. */
9957 if (HWI_COMPUTABLE_MODE_P (mode
)
9958 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9961 /* We can also widen if the bits brought in will be masked off. This
9962 operation is performed in ORIG_MODE. */
9963 if (outer_code
== AND
)
9965 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9968 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9984 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9985 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9986 if we cannot simplify it. Otherwise, return a simplified value.
9988 The shift is normally computed in the widest mode we find in VAROP, as
9989 long as it isn't a different number of words than RESULT_MODE. Exceptions
9990 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9993 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
9994 rtx varop
, int orig_count
)
9996 enum rtx_code orig_code
= code
;
9997 rtx orig_varop
= varop
;
9999 machine_mode mode
= result_mode
;
10000 machine_mode shift_mode
, tmode
;
10001 unsigned int mode_words
10002 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10003 /* We form (outer_op (code varop count) (outer_const)). */
10004 enum rtx_code outer_op
= UNKNOWN
;
10005 HOST_WIDE_INT outer_const
= 0;
10006 int complement_p
= 0;
10009 /* Make sure and truncate the "natural" shift on the way in. We don't
10010 want to do this inside the loop as it makes it more difficult to
10012 if (SHIFT_COUNT_TRUNCATED
)
10013 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10015 /* If we were given an invalid count, don't do anything except exactly
10016 what was requested. */
10018 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10021 count
= orig_count
;
10023 /* Unless one of the branches of the `if' in this loop does a `continue',
10024 we will `break' the loop after the `if'. */
10028 /* If we have an operand of (clobber (const_int 0)), fail. */
10029 if (GET_CODE (varop
) == CLOBBER
)
10032 /* Convert ROTATERT to ROTATE. */
10033 if (code
== ROTATERT
)
10035 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10037 if (VECTOR_MODE_P (result_mode
))
10038 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10040 count
= bitsize
- count
;
10043 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10044 mode
, outer_op
, outer_const
);
10046 /* Handle cases where the count is greater than the size of the mode
10047 minus 1. For ASHIFT, use the size minus one as the count (this can
10048 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10049 take the count modulo the size. For other shifts, the result is
10052 Since these shifts are being produced by the compiler by combining
10053 multiple operations, each of which are defined, we know what the
10054 result is supposed to be. */
10056 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10058 if (code
== ASHIFTRT
)
10059 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10060 else if (code
== ROTATE
|| code
== ROTATERT
)
10061 count
%= GET_MODE_PRECISION (shift_mode
);
10064 /* We can't simply return zero because there may be an
10066 varop
= const0_rtx
;
10072 /* If we discovered we had to complement VAROP, leave. Making a NOT
10073 here would cause an infinite loop. */
10077 /* An arithmetic right shift of a quantity known to be -1 or 0
10079 if (code
== ASHIFTRT
10080 && (num_sign_bit_copies (varop
, shift_mode
)
10081 == GET_MODE_PRECISION (shift_mode
)))
10087 /* If we are doing an arithmetic right shift and discarding all but
10088 the sign bit copies, this is equivalent to doing a shift by the
10089 bitsize minus one. Convert it into that shift because it will often
10090 allow other simplifications. */
10092 if (code
== ASHIFTRT
10093 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10094 >= GET_MODE_PRECISION (shift_mode
)))
10095 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10097 /* We simplify the tests below and elsewhere by converting
10098 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10099 `make_compound_operation' will convert it to an ASHIFTRT for
10100 those machines (such as VAX) that don't have an LSHIFTRT. */
10101 if (code
== ASHIFTRT
10102 && val_signbit_known_clear_p (shift_mode
,
10103 nonzero_bits (varop
, shift_mode
)))
10106 if (((code
== LSHIFTRT
10107 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10108 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10110 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10111 && !((nonzero_bits (varop
, shift_mode
) << count
)
10112 & GET_MODE_MASK (shift_mode
))))
10113 && !side_effects_p (varop
))
10114 varop
= const0_rtx
;
10116 switch (GET_CODE (varop
))
10122 new_rtx
= expand_compound_operation (varop
);
10123 if (new_rtx
!= varop
)
10131 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10132 minus the width of a smaller mode, we can do this with a
10133 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10134 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10135 && ! mode_dependent_address_p (XEXP (varop
, 0),
10136 MEM_ADDR_SPACE (varop
))
10137 && ! MEM_VOLATILE_P (varop
)
10138 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10139 MODE_INT
, 1)) != BLKmode
)
10141 new_rtx
= adjust_address_nv (varop
, tmode
,
10142 BYTES_BIG_ENDIAN
? 0
10143 : count
/ BITS_PER_UNIT
);
10145 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10146 : ZERO_EXTEND
, mode
, new_rtx
);
10153 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10154 the same number of words as what we've seen so far. Then store
10155 the widest mode in MODE. */
10156 if (subreg_lowpart_p (varop
)
10157 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10158 > GET_MODE_SIZE (GET_MODE (varop
)))
10159 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10160 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10162 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10163 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10165 varop
= SUBREG_REG (varop
);
10166 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10167 mode
= GET_MODE (varop
);
10173 /* Some machines use MULT instead of ASHIFT because MULT
10174 is cheaper. But it is still better on those machines to
10175 merge two shifts into one. */
10176 if (CONST_INT_P (XEXP (varop
, 1))
10177 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10180 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10182 GEN_INT (exact_log2 (
10183 UINTVAL (XEXP (varop
, 1)))));
10189 /* Similar, for when divides are cheaper. */
10190 if (CONST_INT_P (XEXP (varop
, 1))
10191 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10194 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10196 GEN_INT (exact_log2 (
10197 UINTVAL (XEXP (varop
, 1)))));
10203 /* If we are extracting just the sign bit of an arithmetic
10204 right shift, that shift is not needed. However, the sign
10205 bit of a wider mode may be different from what would be
10206 interpreted as the sign bit in a narrower mode, so, if
10207 the result is narrower, don't discard the shift. */
10208 if (code
== LSHIFTRT
10209 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10210 && (GET_MODE_BITSIZE (result_mode
)
10211 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10213 varop
= XEXP (varop
, 0);
10217 /* ... fall through ... */
10222 /* Here we have two nested shifts. The result is usually the
10223 AND of a new shift with a mask. We compute the result below. */
10224 if (CONST_INT_P (XEXP (varop
, 1))
10225 && INTVAL (XEXP (varop
, 1)) >= 0
10226 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10227 && HWI_COMPUTABLE_MODE_P (result_mode
)
10228 && HWI_COMPUTABLE_MODE_P (mode
)
10229 && !VECTOR_MODE_P (result_mode
))
10231 enum rtx_code first_code
= GET_CODE (varop
);
10232 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10233 unsigned HOST_WIDE_INT mask
;
10236 /* We have one common special case. We can't do any merging if
10237 the inner code is an ASHIFTRT of a smaller mode. However, if
10238 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10239 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10240 we can convert it to
10241 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10242 This simplifies certain SIGN_EXTEND operations. */
10243 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10244 && count
== (GET_MODE_PRECISION (result_mode
)
10245 - GET_MODE_PRECISION (GET_MODE (varop
))))
10247 /* C3 has the low-order C1 bits zero. */
10249 mask
= GET_MODE_MASK (mode
)
10250 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10252 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10253 XEXP (varop
, 0), mask
);
10254 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10256 count
= first_count
;
10261 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10262 than C1 high-order bits equal to the sign bit, we can convert
10263 this to either an ASHIFT or an ASHIFTRT depending on the
10266 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10268 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10269 && GET_MODE (varop
) == shift_mode
10270 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10273 varop
= XEXP (varop
, 0);
10274 count
-= first_count
;
10284 /* There are some cases we can't do. If CODE is ASHIFTRT,
10285 we can only do this if FIRST_CODE is also ASHIFTRT.
10287 We can't do the case when CODE is ROTATE and FIRST_CODE is
10290 If the mode of this shift is not the mode of the outer shift,
10291 we can't do this if either shift is a right shift or ROTATE.
10293 Finally, we can't do any of these if the mode is too wide
10294 unless the codes are the same.
10296 Handle the case where the shift codes are the same
10299 if (code
== first_code
)
10301 if (GET_MODE (varop
) != result_mode
10302 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10303 || code
== ROTATE
))
10306 count
+= first_count
;
10307 varop
= XEXP (varop
, 0);
10311 if (code
== ASHIFTRT
10312 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10313 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10314 || (GET_MODE (varop
) != result_mode
10315 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10316 || first_code
== ROTATE
10317 || code
== ROTATE
)))
10320 /* To compute the mask to apply after the shift, shift the
10321 nonzero bits of the inner shift the same way the
10322 outer shift will. */
10324 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10328 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10331 /* Give up if we can't compute an outer operation to use. */
10333 || !CONST_INT_P (mask_rtx
)
10334 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10336 result_mode
, &complement_p
))
10339 /* If the shifts are in the same direction, we add the
10340 counts. Otherwise, we subtract them. */
10341 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10342 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10343 count
+= first_count
;
10345 count
-= first_count
;
10347 /* If COUNT is positive, the new shift is usually CODE,
10348 except for the two exceptions below, in which case it is
10349 FIRST_CODE. If the count is negative, FIRST_CODE should
10352 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10353 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10355 else if (count
< 0)
10356 code
= first_code
, count
= -count
;
10358 varop
= XEXP (varop
, 0);
10362 /* If we have (A << B << C) for any shift, we can convert this to
10363 (A << C << B). This wins if A is a constant. Only try this if
10364 B is not a constant. */
10366 else if (GET_CODE (varop
) == code
10367 && CONST_INT_P (XEXP (varop
, 0))
10368 && !CONST_INT_P (XEXP (varop
, 1)))
10370 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10373 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10380 if (VECTOR_MODE_P (mode
))
10383 /* Make this fit the case below. */
10384 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10390 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10391 with C the size of VAROP - 1 and the shift is logical if
10392 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10393 we have an (le X 0) operation. If we have an arithmetic shift
10394 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10395 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10397 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10398 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10399 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10400 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10401 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10402 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10405 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10408 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10409 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10414 /* If we have (shift (logical)), move the logical to the outside
10415 to allow it to possibly combine with another logical and the
10416 shift to combine with another shift. This also canonicalizes to
10417 what a ZERO_EXTRACT looks like. Also, some machines have
10418 (and (shift)) insns. */
10420 if (CONST_INT_P (XEXP (varop
, 1))
10421 /* We can't do this if we have (ashiftrt (xor)) and the
10422 constant has its sign bit set in shift_mode with shift_mode
10423 wider than result_mode. */
10424 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10425 && result_mode
!= shift_mode
10426 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10428 && (new_rtx
= simplify_const_binary_operation
10429 (code
, result_mode
,
10430 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10431 GEN_INT (count
))) != 0
10432 && CONST_INT_P (new_rtx
)
10433 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10434 INTVAL (new_rtx
), result_mode
, &complement_p
))
10436 varop
= XEXP (varop
, 0);
10440 /* If we can't do that, try to simplify the shift in each arm of the
10441 logical expression, make a new logical expression, and apply
10442 the inverse distributive law. This also can't be done for
10443 (ashiftrt (xor)) where we've widened the shift and the constant
10444 changes the sign bit. */
10445 if (CONST_INT_P (XEXP (varop
, 1))
10446 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10447 && result_mode
!= shift_mode
10448 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10451 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10452 XEXP (varop
, 0), count
);
10453 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10454 XEXP (varop
, 1), count
);
10456 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10458 varop
= apply_distributive_law (varop
);
10466 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10467 says that the sign bit can be tested, FOO has mode MODE, C is
10468 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10469 that may be nonzero. */
10470 if (code
== LSHIFTRT
10471 && XEXP (varop
, 1) == const0_rtx
10472 && GET_MODE (XEXP (varop
, 0)) == result_mode
10473 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10474 && HWI_COMPUTABLE_MODE_P (result_mode
)
10475 && STORE_FLAG_VALUE
== -1
10476 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10477 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10480 varop
= XEXP (varop
, 0);
10487 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10488 than the number of bits in the mode is equivalent to A. */
10489 if (code
== LSHIFTRT
10490 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10491 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10493 varop
= XEXP (varop
, 0);
10498 /* NEG commutes with ASHIFT since it is multiplication. Move the
10499 NEG outside to allow shifts to combine. */
10501 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10504 varop
= XEXP (varop
, 0);
10510 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10511 is one less than the number of bits in the mode is
10512 equivalent to (xor A 1). */
10513 if (code
== LSHIFTRT
10514 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10515 && XEXP (varop
, 1) == constm1_rtx
10516 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10517 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10521 varop
= XEXP (varop
, 0);
10525 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10526 that might be nonzero in BAR are those being shifted out and those
10527 bits are known zero in FOO, we can replace the PLUS with FOO.
10528 Similarly in the other operand order. This code occurs when
10529 we are computing the size of a variable-size array. */
10531 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10532 && count
< HOST_BITS_PER_WIDE_INT
10533 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10534 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10535 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10537 varop
= XEXP (varop
, 0);
10540 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10541 && count
< HOST_BITS_PER_WIDE_INT
10542 && HWI_COMPUTABLE_MODE_P (result_mode
)
10543 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10545 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10546 & nonzero_bits (XEXP (varop
, 1),
10549 varop
= XEXP (varop
, 1);
10553 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10555 && CONST_INT_P (XEXP (varop
, 1))
10556 && (new_rtx
= simplify_const_binary_operation
10557 (ASHIFT
, result_mode
,
10558 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10559 GEN_INT (count
))) != 0
10560 && CONST_INT_P (new_rtx
)
10561 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10562 INTVAL (new_rtx
), result_mode
, &complement_p
))
10564 varop
= XEXP (varop
, 0);
10568 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10569 signbit', and attempt to change the PLUS to an XOR and move it to
10570 the outer operation as is done above in the AND/IOR/XOR case
10571 leg for shift(logical). See details in logical handling above
10572 for reasoning in doing so. */
10573 if (code
== LSHIFTRT
10574 && CONST_INT_P (XEXP (varop
, 1))
10575 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10576 && (new_rtx
= simplify_const_binary_operation
10577 (code
, result_mode
,
10578 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10579 GEN_INT (count
))) != 0
10580 && CONST_INT_P (new_rtx
)
10581 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10582 INTVAL (new_rtx
), result_mode
, &complement_p
))
10584 varop
= XEXP (varop
, 0);
10591 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10592 with C the size of VAROP - 1 and the shift is logical if
10593 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10594 we have a (gt X 0) operation. If the shift is arithmetic with
10595 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10596 we have a (neg (gt X 0)) operation. */
10598 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10599 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10600 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10601 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10602 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10603 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10604 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10607 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10610 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10611 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10618 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10619 if the truncate does not affect the value. */
10620 if (code
== LSHIFTRT
10621 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10622 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10623 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10624 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10625 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10627 rtx varop_inner
= XEXP (varop
, 0);
10630 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10631 XEXP (varop_inner
, 0),
10633 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10634 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10647 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10648 outer_op
, outer_const
);
10650 /* We have now finished analyzing the shift. The result should be
10651 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10652 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10653 to the result of the shift. OUTER_CONST is the relevant constant,
10654 but we must turn off all bits turned off in the shift. */
10656 if (outer_op
== UNKNOWN
10657 && orig_code
== code
&& orig_count
== count
10658 && varop
== orig_varop
10659 && shift_mode
== GET_MODE (varop
))
10662 /* Make a SUBREG if necessary. If we can't make it, fail. */
10663 varop
= gen_lowpart (shift_mode
, varop
);
10664 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10667 /* If we have an outer operation and we just made a shift, it is
10668 possible that we could have simplified the shift were it not
10669 for the outer operation. So try to do the simplification
10672 if (outer_op
!= UNKNOWN
)
10673 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10678 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10680 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10681 turn off all the bits that the shift would have turned off. */
10682 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10683 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10684 GET_MODE_MASK (result_mode
) >> orig_count
);
10686 /* Do the remainder of the processing in RESULT_MODE. */
10687 x
= gen_lowpart_or_truncate (result_mode
, x
);
10689 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10692 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10694 if (outer_op
!= UNKNOWN
)
10696 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10697 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10698 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10700 if (outer_op
== AND
)
10701 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10702 else if (outer_op
== SET
)
10704 /* This means that we have determined that the result is
10705 equivalent to a constant. This should be rare. */
10706 if (!side_effects_p (x
))
10707 x
= GEN_INT (outer_const
);
10709 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10710 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10712 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10713 GEN_INT (outer_const
));
10719 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10720 The result of the shift is RESULT_MODE. If we cannot simplify it,
10721 return X or, if it is NULL, synthesize the expression with
10722 simplify_gen_binary. Otherwise, return a simplified value.
10724 The shift is normally computed in the widest mode we find in VAROP, as
10725 long as it isn't a different number of words than RESULT_MODE. Exceptions
10726 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10729 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10730 rtx varop
, int count
)
10732 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10737 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10738 if (GET_MODE (x
) != result_mode
)
10739 x
= gen_lowpart (result_mode
, x
);
10744 /* Like recog, but we receive the address of a pointer to a new pattern.
10745 We try to match the rtx that the pointer points to.
10746 If that fails, we may try to modify or replace the pattern,
10747 storing the replacement into the same pointer object.
10749 Modifications include deletion or addition of CLOBBERs.
10751 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10752 the CLOBBERs are placed.
10754 The value is the final insn code from the pattern ultimately matched,
10758 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10760 rtx pat
= *pnewpat
;
10761 rtx pat_without_clobbers
;
10762 int insn_code_number
;
10763 int num_clobbers_to_add
= 0;
10765 rtx notes
= NULL_RTX
;
10766 rtx old_notes
, old_pat
;
10769 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10770 we use to indicate that something didn't match. If we find such a
10771 thing, force rejection. */
10772 if (GET_CODE (pat
) == PARALLEL
)
10773 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10774 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10775 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10778 old_pat
= PATTERN (insn
);
10779 old_notes
= REG_NOTES (insn
);
10780 PATTERN (insn
) = pat
;
10781 REG_NOTES (insn
) = NULL_RTX
;
10783 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10784 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10786 if (insn_code_number
< 0)
10787 fputs ("Failed to match this instruction:\n", dump_file
);
10789 fputs ("Successfully matched this instruction:\n", dump_file
);
10790 print_rtl_single (dump_file
, pat
);
10793 /* If it isn't, there is the possibility that we previously had an insn
10794 that clobbered some register as a side effect, but the combined
10795 insn doesn't need to do that. So try once more without the clobbers
10796 unless this represents an ASM insn. */
10798 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10799 && GET_CODE (pat
) == PARALLEL
)
10803 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10804 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10807 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10811 SUBST_INT (XVECLEN (pat
, 0), pos
);
10814 pat
= XVECEXP (pat
, 0, 0);
10816 PATTERN (insn
) = pat
;
10817 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10818 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10820 if (insn_code_number
< 0)
10821 fputs ("Failed to match this instruction:\n", dump_file
);
10823 fputs ("Successfully matched this instruction:\n", dump_file
);
10824 print_rtl_single (dump_file
, pat
);
10828 pat_without_clobbers
= pat
;
10830 PATTERN (insn
) = old_pat
;
10831 REG_NOTES (insn
) = old_notes
;
10833 /* Recognize all noop sets, these will be killed by followup pass. */
10834 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10835 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10837 /* If we had any clobbers to add, make a new pattern than contains
10838 them. Then check to make sure that all of them are dead. */
10839 if (num_clobbers_to_add
)
10841 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10842 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10843 ? (XVECLEN (pat
, 0)
10844 + num_clobbers_to_add
)
10845 : num_clobbers_to_add
+ 1));
10847 if (GET_CODE (pat
) == PARALLEL
)
10848 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10849 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10851 XVECEXP (newpat
, 0, 0) = pat
;
10853 add_clobbers (newpat
, insn_code_number
);
10855 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10856 i
< XVECLEN (newpat
, 0); i
++)
10858 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10859 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10861 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10863 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10864 notes
= alloc_reg_note (REG_UNUSED
,
10865 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10871 if (insn_code_number
>= 0
10872 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10874 old_pat
= PATTERN (insn
);
10875 old_notes
= REG_NOTES (insn
);
10876 old_icode
= INSN_CODE (insn
);
10877 PATTERN (insn
) = pat
;
10878 REG_NOTES (insn
) = notes
;
10880 /* Allow targets to reject combined insn. */
10881 if (!targetm
.legitimate_combined_insn (insn
))
10883 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10884 fputs ("Instruction not appropriate for target.",
10887 /* Callers expect recog_for_combine to strip
10888 clobbers from the pattern on failure. */
10889 pat
= pat_without_clobbers
;
10892 insn_code_number
= -1;
10895 PATTERN (insn
) = old_pat
;
10896 REG_NOTES (insn
) = old_notes
;
10897 INSN_CODE (insn
) = old_icode
;
10903 return insn_code_number
;
10906 /* Like gen_lowpart_general but for use by combine. In combine it
10907 is not possible to create any new pseudoregs. However, it is
10908 safe to create invalid memory addresses, because combine will
10909 try to recognize them and all they will do is make the combine
10912 If for some reason this cannot do its job, an rtx
10913 (clobber (const_int 0)) is returned.
10914 An insn containing that will not be recognized. */
10917 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
10919 machine_mode imode
= GET_MODE (x
);
10920 unsigned int osize
= GET_MODE_SIZE (omode
);
10921 unsigned int isize
= GET_MODE_SIZE (imode
);
10924 if (omode
== imode
)
10927 /* We can only support MODE being wider than a word if X is a
10928 constant integer or has a mode the same size. */
10929 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10930 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10933 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10934 won't know what to do. So we will strip off the SUBREG here and
10935 process normally. */
10936 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10938 x
= SUBREG_REG (x
);
10940 /* For use in case we fall down into the address adjustments
10941 further below, we need to adjust the known mode and size of
10942 x; imode and isize, since we just adjusted x. */
10943 imode
= GET_MODE (x
);
10945 if (imode
== omode
)
10948 isize
= GET_MODE_SIZE (imode
);
10951 result
= gen_lowpart_common (omode
, x
);
10960 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10962 if (MEM_VOLATILE_P (x
)
10963 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10966 /* If we want to refer to something bigger than the original memref,
10967 generate a paradoxical subreg instead. That will force a reload
10968 of the original memref X. */
10970 return gen_rtx_SUBREG (omode
, x
, 0);
10972 if (WORDS_BIG_ENDIAN
)
10973 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10975 /* Adjust the address so that the address-after-the-data is
10977 if (BYTES_BIG_ENDIAN
)
10978 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10980 return adjust_address_nv (x
, omode
, offset
);
10983 /* If X is a comparison operator, rewrite it in a new mode. This
10984 probably won't match, but may allow further simplifications. */
10985 else if (COMPARISON_P (x
))
10986 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10988 /* If we couldn't simplify X any other way, just enclose it in a
10989 SUBREG. Normally, this SUBREG won't match, but some patterns may
10990 include an explicit SUBREG or we may simplify it further in combine. */
10996 offset
= subreg_lowpart_offset (omode
, imode
);
10997 if (imode
== VOIDmode
)
10999 imode
= int_mode_for_mode (omode
);
11000 x
= gen_lowpart_common (imode
, x
);
11004 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
11010 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11013 /* Try to simplify a comparison between OP0 and a constant OP1,
11014 where CODE is the comparison code that will be tested, into a
11015 (CODE OP0 const0_rtx) form.
11017 The result is a possibly different comparison code to use.
11018 *POP1 may be updated. */
11020 static enum rtx_code
11021 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11022 rtx op0
, rtx
*pop1
)
11024 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11025 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11027 /* Get the constant we are comparing against and turn off all bits
11028 not on in our mode. */
11029 if (mode
!= VOIDmode
)
11030 const_op
= trunc_int_for_mode (const_op
, mode
);
11032 /* If we are comparing against a constant power of two and the value
11033 being compared can only have that single bit nonzero (e.g., it was
11034 `and'ed with that bit), we can replace this with a comparison
11037 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11038 || code
== LT
|| code
== LTU
)
11039 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11040 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11041 && (nonzero_bits (op0
, mode
)
11042 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11044 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11048 /* Similarly, if we are comparing a value known to be either -1 or
11049 0 with -1, change it to the opposite comparison against zero. */
11051 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11052 || code
== GEU
|| code
== LTU
)
11053 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11055 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11059 /* Do some canonicalizations based on the comparison code. We prefer
11060 comparisons against zero and then prefer equality comparisons.
11061 If we can reduce the size of a constant, we will do that too. */
11065 /* < C is equivalent to <= (C - 1) */
11070 /* ... fall through to LE case below. */
11076 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11083 /* If we are doing a <= 0 comparison on a value known to have
11084 a zero sign bit, we can replace this with == 0. */
11085 else if (const_op
== 0
11086 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11087 && (nonzero_bits (op0
, mode
)
11088 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11094 /* >= C is equivalent to > (C - 1). */
11099 /* ... fall through to GT below. */
11105 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11112 /* If we are doing a > 0 comparison on a value known to have
11113 a zero sign bit, we can replace this with != 0. */
11114 else if (const_op
== 0
11115 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11116 && (nonzero_bits (op0
, mode
)
11117 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11123 /* < C is equivalent to <= (C - 1). */
11128 /* ... fall through ... */
11130 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11131 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11132 && (unsigned HOST_WIDE_INT
) const_op
11133 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11143 /* unsigned <= 0 is equivalent to == 0 */
11146 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11147 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11148 && (unsigned HOST_WIDE_INT
) const_op
11149 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11157 /* >= C is equivalent to > (C - 1). */
11162 /* ... fall through ... */
11165 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11166 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11167 && (unsigned HOST_WIDE_INT
) const_op
11168 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11178 /* unsigned > 0 is equivalent to != 0 */
11181 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11182 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11183 && (unsigned HOST_WIDE_INT
) const_op
11184 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11195 *pop1
= GEN_INT (const_op
);
11199 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11200 comparison code that will be tested.
11202 The result is a possibly different comparison code to use. *POP0 and
11203 *POP1 may be updated.
11205 It is possible that we might detect that a comparison is either always
11206 true or always false. However, we do not perform general constant
11207 folding in combine, so this knowledge isn't useful. Such tautologies
11208 should have been detected earlier. Hence we ignore all such cases. */
11210 static enum rtx_code
11211 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11217 machine_mode mode
, tmode
;
11219 /* Try a few ways of applying the same transformation to both operands. */
11222 #ifndef WORD_REGISTER_OPERATIONS
11223 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11224 so check specially. */
11225 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11226 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11227 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11228 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11229 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11230 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11231 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11232 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11233 && CONST_INT_P (XEXP (op0
, 1))
11234 && XEXP (op0
, 1) == XEXP (op1
, 1)
11235 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11236 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11237 && (INTVAL (XEXP (op0
, 1))
11238 == (GET_MODE_PRECISION (GET_MODE (op0
))
11239 - (GET_MODE_PRECISION
11240 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11242 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11243 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11247 /* If both operands are the same constant shift, see if we can ignore the
11248 shift. We can if the shift is a rotate or if the bits shifted out of
11249 this shift are known to be zero for both inputs and if the type of
11250 comparison is compatible with the shift. */
11251 if (GET_CODE (op0
) == GET_CODE (op1
)
11252 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11253 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11254 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11255 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11256 || (GET_CODE (op0
) == ASHIFTRT
11257 && (code
!= GTU
&& code
!= LTU
11258 && code
!= GEU
&& code
!= LEU
)))
11259 && CONST_INT_P (XEXP (op0
, 1))
11260 && INTVAL (XEXP (op0
, 1)) >= 0
11261 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11262 && XEXP (op0
, 1) == XEXP (op1
, 1))
11264 machine_mode mode
= GET_MODE (op0
);
11265 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11266 int shift_count
= INTVAL (XEXP (op0
, 1));
11268 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11269 mask
&= (mask
>> shift_count
) << shift_count
;
11270 else if (GET_CODE (op0
) == ASHIFT
)
11271 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11273 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11274 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11275 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11280 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11281 SUBREGs are of the same mode, and, in both cases, the AND would
11282 be redundant if the comparison was done in the narrower mode,
11283 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11284 and the operand's possibly nonzero bits are 0xffffff01; in that case
11285 if we only care about QImode, we don't need the AND). This case
11286 occurs if the output mode of an scc insn is not SImode and
11287 STORE_FLAG_VALUE == 1 (e.g., the 386).
11289 Similarly, check for a case where the AND's are ZERO_EXTEND
11290 operations from some narrower mode even though a SUBREG is not
11293 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11294 && CONST_INT_P (XEXP (op0
, 1))
11295 && CONST_INT_P (XEXP (op1
, 1)))
11297 rtx inner_op0
= XEXP (op0
, 0);
11298 rtx inner_op1
= XEXP (op1
, 0);
11299 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11300 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11303 if (paradoxical_subreg_p (inner_op0
)
11304 && GET_CODE (inner_op1
) == SUBREG
11305 && (GET_MODE (SUBREG_REG (inner_op0
))
11306 == GET_MODE (SUBREG_REG (inner_op1
)))
11307 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11308 <= HOST_BITS_PER_WIDE_INT
)
11309 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11310 GET_MODE (SUBREG_REG (inner_op0
)))))
11311 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11312 GET_MODE (SUBREG_REG (inner_op1
))))))
11314 op0
= SUBREG_REG (inner_op0
);
11315 op1
= SUBREG_REG (inner_op1
);
11317 /* The resulting comparison is always unsigned since we masked
11318 off the original sign bit. */
11319 code
= unsigned_condition (code
);
11325 for (tmode
= GET_CLASS_NARROWEST_MODE
11326 (GET_MODE_CLASS (GET_MODE (op0
)));
11327 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11328 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11330 op0
= gen_lowpart (tmode
, inner_op0
);
11331 op1
= gen_lowpart (tmode
, inner_op1
);
11332 code
= unsigned_condition (code
);
11341 /* If both operands are NOT, we can strip off the outer operation
11342 and adjust the comparison code for swapped operands; similarly for
11343 NEG, except that this must be an equality comparison. */
11344 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11345 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11346 && (code
== EQ
|| code
== NE
)))
11347 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11353 /* If the first operand is a constant, swap the operands and adjust the
11354 comparison code appropriately, but don't do this if the second operand
11355 is already a constant integer. */
11356 if (swap_commutative_operands_p (op0
, op1
))
11358 tem
= op0
, op0
= op1
, op1
= tem
;
11359 code
= swap_condition (code
);
11362 /* We now enter a loop during which we will try to simplify the comparison.
11363 For the most part, we only are concerned with comparisons with zero,
11364 but some things may really be comparisons with zero but not start
11365 out looking that way. */
11367 while (CONST_INT_P (op1
))
11369 machine_mode mode
= GET_MODE (op0
);
11370 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11371 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11372 int equality_comparison_p
;
11373 int sign_bit_comparison_p
;
11374 int unsigned_comparison_p
;
11375 HOST_WIDE_INT const_op
;
11377 /* We only want to handle integral modes. This catches VOIDmode,
11378 CCmode, and the floating-point modes. An exception is that we
11379 can handle VOIDmode if OP0 is a COMPARE or a comparison
11382 if (GET_MODE_CLASS (mode
) != MODE_INT
11383 && ! (mode
== VOIDmode
11384 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11387 /* Try to simplify the compare to constant, possibly changing the
11388 comparison op, and/or changing op1 to zero. */
11389 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11390 const_op
= INTVAL (op1
);
11392 /* Compute some predicates to simplify code below. */
11394 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11395 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11396 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11399 /* If this is a sign bit comparison and we can do arithmetic in
11400 MODE, say that we will only be needing the sign bit of OP0. */
11401 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11402 op0
= force_to_mode (op0
, mode
,
11403 (unsigned HOST_WIDE_INT
) 1
11404 << (GET_MODE_PRECISION (mode
) - 1),
11407 /* Now try cases based on the opcode of OP0. If none of the cases
11408 does a "continue", we exit this loop immediately after the
11411 switch (GET_CODE (op0
))
11414 /* If we are extracting a single bit from a variable position in
11415 a constant that has only a single bit set and are comparing it
11416 with zero, we can convert this into an equality comparison
11417 between the position and the location of the single bit. */
11418 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11419 have already reduced the shift count modulo the word size. */
11420 if (!SHIFT_COUNT_TRUNCATED
11421 && CONST_INT_P (XEXP (op0
, 0))
11422 && XEXP (op0
, 1) == const1_rtx
11423 && equality_comparison_p
&& const_op
== 0
11424 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11426 if (BITS_BIG_ENDIAN
)
11427 i
= BITS_PER_WORD
- 1 - i
;
11429 op0
= XEXP (op0
, 2);
11433 /* Result is nonzero iff shift count is equal to I. */
11434 code
= reverse_condition (code
);
11438 /* ... fall through ... */
11441 tem
= expand_compound_operation (op0
);
11450 /* If testing for equality, we can take the NOT of the constant. */
11451 if (equality_comparison_p
11452 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11454 op0
= XEXP (op0
, 0);
11459 /* If just looking at the sign bit, reverse the sense of the
11461 if (sign_bit_comparison_p
)
11463 op0
= XEXP (op0
, 0);
11464 code
= (code
== GE
? LT
: GE
);
11470 /* If testing for equality, we can take the NEG of the constant. */
11471 if (equality_comparison_p
11472 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11474 op0
= XEXP (op0
, 0);
11479 /* The remaining cases only apply to comparisons with zero. */
11483 /* When X is ABS or is known positive,
11484 (neg X) is < 0 if and only if X != 0. */
11486 if (sign_bit_comparison_p
11487 && (GET_CODE (XEXP (op0
, 0)) == ABS
11488 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11489 && (nonzero_bits (XEXP (op0
, 0), mode
)
11490 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11493 op0
= XEXP (op0
, 0);
11494 code
= (code
== LT
? NE
: EQ
);
11498 /* If we have NEG of something whose two high-order bits are the
11499 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11500 if (num_sign_bit_copies (op0
, mode
) >= 2)
11502 op0
= XEXP (op0
, 0);
11503 code
= swap_condition (code
);
11509 /* If we are testing equality and our count is a constant, we
11510 can perform the inverse operation on our RHS. */
11511 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11512 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11513 op1
, XEXP (op0
, 1))) != 0)
11515 op0
= XEXP (op0
, 0);
11520 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11521 a particular bit. Convert it to an AND of a constant of that
11522 bit. This will be converted into a ZERO_EXTRACT. */
11523 if (const_op
== 0 && sign_bit_comparison_p
11524 && CONST_INT_P (XEXP (op0
, 1))
11525 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11527 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11528 ((unsigned HOST_WIDE_INT
) 1
11530 - INTVAL (XEXP (op0
, 1)))));
11531 code
= (code
== LT
? NE
: EQ
);
11535 /* Fall through. */
11538 /* ABS is ignorable inside an equality comparison with zero. */
11539 if (const_op
== 0 && equality_comparison_p
)
11541 op0
= XEXP (op0
, 0);
11547 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11548 (compare FOO CONST) if CONST fits in FOO's mode and we
11549 are either testing inequality or have an unsigned
11550 comparison with ZERO_EXTEND or a signed comparison with
11551 SIGN_EXTEND. But don't do it if we don't have a compare
11552 insn of the given mode, since we'd have to revert it
11553 later on, and then we wouldn't know whether to sign- or
11555 mode
= GET_MODE (XEXP (op0
, 0));
11556 if (GET_MODE_CLASS (mode
) == MODE_INT
11557 && ! unsigned_comparison_p
11558 && HWI_COMPUTABLE_MODE_P (mode
)
11559 && trunc_int_for_mode (const_op
, mode
) == const_op
11560 && have_insn_for (COMPARE
, mode
))
11562 op0
= XEXP (op0
, 0);
11568 /* Check for the case where we are comparing A - C1 with C2, that is
11570 (subreg:MODE (plus (A) (-C1))) op (C2)
11572 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11573 comparison in the wider mode. One of the following two conditions
11574 must be true in order for this to be valid:
11576 1. The mode extension results in the same bit pattern being added
11577 on both sides and the comparison is equality or unsigned. As
11578 C2 has been truncated to fit in MODE, the pattern can only be
11581 2. The mode extension results in the sign bit being copied on
11584 The difficulty here is that we have predicates for A but not for
11585 (A - C1) so we need to check that C1 is within proper bounds so
11586 as to perturbate A as little as possible. */
11588 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11589 && subreg_lowpart_p (op0
)
11590 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11591 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11592 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11594 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11595 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11596 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11599 && (unsigned HOST_WIDE_INT
) c1
11600 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11601 && (equality_comparison_p
|| unsigned_comparison_p
)
11602 /* (A - C1) zero-extends if it is positive and sign-extends
11603 if it is negative, C2 both zero- and sign-extends. */
11604 && ((0 == (nonzero_bits (a
, inner_mode
)
11605 & ~GET_MODE_MASK (mode
))
11607 /* (A - C1) sign-extends if it is positive and 1-extends
11608 if it is negative, C2 both sign- and 1-extends. */
11609 || (num_sign_bit_copies (a
, inner_mode
)
11610 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11613 || ((unsigned HOST_WIDE_INT
) c1
11614 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11615 /* (A - C1) always sign-extends, like C2. */
11616 && num_sign_bit_copies (a
, inner_mode
)
11617 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11618 - (mode_width
- 1))))
11620 op0
= SUBREG_REG (op0
);
11625 /* If the inner mode is narrower and we are extracting the low part,
11626 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11627 if (subreg_lowpart_p (op0
)
11628 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11629 /* Fall through */ ;
11633 /* ... fall through ... */
11636 mode
= GET_MODE (XEXP (op0
, 0));
11637 if (GET_MODE_CLASS (mode
) == MODE_INT
11638 && (unsigned_comparison_p
|| equality_comparison_p
)
11639 && HWI_COMPUTABLE_MODE_P (mode
)
11640 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11642 && have_insn_for (COMPARE
, mode
))
11644 op0
= XEXP (op0
, 0);
11650 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11651 this for equality comparisons due to pathological cases involving
11653 if (equality_comparison_p
11654 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11655 op1
, XEXP (op0
, 1))))
11657 op0
= XEXP (op0
, 0);
11662 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11663 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11664 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11666 op0
= XEXP (XEXP (op0
, 0), 0);
11667 code
= (code
== LT
? EQ
: NE
);
11673 /* We used to optimize signed comparisons against zero, but that
11674 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11675 arrive here as equality comparisons, or (GEU, LTU) are
11676 optimized away. No need to special-case them. */
11678 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11679 (eq B (minus A C)), whichever simplifies. We can only do
11680 this for equality comparisons due to pathological cases involving
11682 if (equality_comparison_p
11683 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11684 XEXP (op0
, 1), op1
)))
11686 op0
= XEXP (op0
, 0);
11691 if (equality_comparison_p
11692 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11693 XEXP (op0
, 0), op1
)))
11695 op0
= XEXP (op0
, 1);
11700 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11701 of bits in X minus 1, is one iff X > 0. */
11702 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11703 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11704 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11705 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11707 op0
= XEXP (op0
, 1);
11708 code
= (code
== GE
? LE
: GT
);
11714 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11715 if C is zero or B is a constant. */
11716 if (equality_comparison_p
11717 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11718 XEXP (op0
, 1), op1
)))
11720 op0
= XEXP (op0
, 0);
11727 case UNEQ
: case LTGT
:
11728 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11729 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11730 case UNORDERED
: case ORDERED
:
11731 /* We can't do anything if OP0 is a condition code value, rather
11732 than an actual data value. */
11734 || CC0_P (XEXP (op0
, 0))
11735 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11738 /* Get the two operands being compared. */
11739 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11740 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11742 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11744 /* Check for the cases where we simply want the result of the
11745 earlier test or the opposite of that result. */
11746 if (code
== NE
|| code
== EQ
11747 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11748 && (code
== LT
|| code
== GE
)))
11750 enum rtx_code new_code
;
11751 if (code
== LT
|| code
== NE
)
11752 new_code
= GET_CODE (op0
);
11754 new_code
= reversed_comparison_code (op0
, NULL
);
11756 if (new_code
!= UNKNOWN
)
11767 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11769 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11770 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11771 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11773 op0
= XEXP (op0
, 1);
11774 code
= (code
== GE
? GT
: LE
);
11780 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11781 will be converted to a ZERO_EXTRACT later. */
11782 if (const_op
== 0 && equality_comparison_p
11783 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11784 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11786 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11787 XEXP (XEXP (op0
, 0), 1));
11788 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11792 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11793 zero and X is a comparison and C1 and C2 describe only bits set
11794 in STORE_FLAG_VALUE, we can compare with X. */
11795 if (const_op
== 0 && equality_comparison_p
11796 && mode_width
<= HOST_BITS_PER_WIDE_INT
11797 && CONST_INT_P (XEXP (op0
, 1))
11798 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11799 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11800 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11801 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11803 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11804 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11805 if ((~STORE_FLAG_VALUE
& mask
) == 0
11806 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11807 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11808 && COMPARISON_P (tem
))))
11810 op0
= XEXP (XEXP (op0
, 0), 0);
11815 /* If we are doing an equality comparison of an AND of a bit equal
11816 to the sign bit, replace this with a LT or GE comparison of
11817 the underlying value. */
11818 if (equality_comparison_p
11820 && CONST_INT_P (XEXP (op0
, 1))
11821 && mode_width
<= HOST_BITS_PER_WIDE_INT
11822 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11823 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11825 op0
= XEXP (op0
, 0);
11826 code
= (code
== EQ
? GE
: LT
);
11830 /* If this AND operation is really a ZERO_EXTEND from a narrower
11831 mode, the constant fits within that mode, and this is either an
11832 equality or unsigned comparison, try to do this comparison in
11837 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11838 -> (ne:DI (reg:SI 4) (const_int 0))
11840 unless TRULY_NOOP_TRUNCATION allows it or the register is
11841 known to hold a value of the required mode the
11842 transformation is invalid. */
11843 if ((equality_comparison_p
|| unsigned_comparison_p
)
11844 && CONST_INT_P (XEXP (op0
, 1))
11845 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11846 & GET_MODE_MASK (mode
))
11848 && const_op
>> i
== 0
11849 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11850 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11851 || (REG_P (XEXP (op0
, 0))
11852 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11854 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11858 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11859 fits in both M1 and M2 and the SUBREG is either paradoxical
11860 or represents the low part, permute the SUBREG and the AND
11862 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11864 unsigned HOST_WIDE_INT c1
;
11865 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11866 /* Require an integral mode, to avoid creating something like
11868 if (SCALAR_INT_MODE_P (tmode
)
11869 /* It is unsafe to commute the AND into the SUBREG if the
11870 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11871 not defined. As originally written the upper bits
11872 have a defined value due to the AND operation.
11873 However, if we commute the AND inside the SUBREG then
11874 they no longer have defined values and the meaning of
11875 the code has been changed. */
11877 #ifdef WORD_REGISTER_OPERATIONS
11878 || (mode_width
> GET_MODE_PRECISION (tmode
)
11879 && mode_width
<= BITS_PER_WORD
)
11881 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11882 && subreg_lowpart_p (XEXP (op0
, 0))))
11883 && CONST_INT_P (XEXP (op0
, 1))
11884 && mode_width
<= HOST_BITS_PER_WIDE_INT
11885 && HWI_COMPUTABLE_MODE_P (tmode
)
11886 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11887 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11889 && c1
!= GET_MODE_MASK (tmode
))
11891 op0
= simplify_gen_binary (AND
, tmode
,
11892 SUBREG_REG (XEXP (op0
, 0)),
11893 gen_int_mode (c1
, tmode
));
11894 op0
= gen_lowpart (mode
, op0
);
11899 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11900 if (const_op
== 0 && equality_comparison_p
11901 && XEXP (op0
, 1) == const1_rtx
11902 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11904 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11905 XEXP (XEXP (op0
, 0), 0), 1);
11906 code
= (code
== NE
? EQ
: NE
);
11910 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11911 (eq (and (lshiftrt X) 1) 0).
11912 Also handle the case where (not X) is expressed using xor. */
11913 if (const_op
== 0 && equality_comparison_p
11914 && XEXP (op0
, 1) == const1_rtx
11915 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11917 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11918 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11920 if (GET_CODE (shift_op
) == NOT
11921 || (GET_CODE (shift_op
) == XOR
11922 && CONST_INT_P (XEXP (shift_op
, 1))
11923 && CONST_INT_P (shift_count
)
11924 && HWI_COMPUTABLE_MODE_P (mode
)
11925 && (UINTVAL (XEXP (shift_op
, 1))
11926 == (unsigned HOST_WIDE_INT
) 1
11927 << INTVAL (shift_count
))))
11930 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11931 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11932 code
= (code
== NE
? EQ
: NE
);
11939 /* If we have (compare (ashift FOO N) (const_int C)) and
11940 the high order N bits of FOO (N+1 if an inequality comparison)
11941 are known to be zero, we can do this by comparing FOO with C
11942 shifted right N bits so long as the low-order N bits of C are
11944 if (CONST_INT_P (XEXP (op0
, 1))
11945 && INTVAL (XEXP (op0
, 1)) >= 0
11946 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11947 < HOST_BITS_PER_WIDE_INT
)
11948 && (((unsigned HOST_WIDE_INT
) const_op
11949 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11951 && mode_width
<= HOST_BITS_PER_WIDE_INT
11952 && (nonzero_bits (XEXP (op0
, 0), mode
)
11953 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11954 + ! equality_comparison_p
))) == 0)
11956 /* We must perform a logical shift, not an arithmetic one,
11957 as we want the top N bits of C to be zero. */
11958 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11960 temp
>>= INTVAL (XEXP (op0
, 1));
11961 op1
= gen_int_mode (temp
, mode
);
11962 op0
= XEXP (op0
, 0);
11966 /* If we are doing a sign bit comparison, it means we are testing
11967 a particular bit. Convert it to the appropriate AND. */
11968 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11969 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11971 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11972 ((unsigned HOST_WIDE_INT
) 1
11974 - INTVAL (XEXP (op0
, 1)))));
11975 code
= (code
== LT
? NE
: EQ
);
11979 /* If this an equality comparison with zero and we are shifting
11980 the low bit to the sign bit, we can convert this to an AND of the
11982 if (const_op
== 0 && equality_comparison_p
11983 && CONST_INT_P (XEXP (op0
, 1))
11984 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11986 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11992 /* If this is an equality comparison with zero, we can do this
11993 as a logical shift, which might be much simpler. */
11994 if (equality_comparison_p
&& const_op
== 0
11995 && CONST_INT_P (XEXP (op0
, 1)))
11997 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11999 INTVAL (XEXP (op0
, 1)));
12003 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12004 do the comparison in a narrower mode. */
12005 if (! unsigned_comparison_p
12006 && CONST_INT_P (XEXP (op0
, 1))
12007 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12008 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12009 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12010 MODE_INT
, 1)) != BLKmode
12011 && (((unsigned HOST_WIDE_INT
) const_op
12012 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12013 <= GET_MODE_MASK (tmode
)))
12015 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12019 /* Likewise if OP0 is a PLUS of a sign extension with a
12020 constant, which is usually represented with the PLUS
12021 between the shifts. */
12022 if (! unsigned_comparison_p
12023 && CONST_INT_P (XEXP (op0
, 1))
12024 && GET_CODE (XEXP (op0
, 0)) == PLUS
12025 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12026 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12027 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12028 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12029 MODE_INT
, 1)) != BLKmode
12030 && (((unsigned HOST_WIDE_INT
) const_op
12031 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12032 <= GET_MODE_MASK (tmode
)))
12034 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12035 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12036 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12037 add_const
, XEXP (op0
, 1));
12039 op0
= simplify_gen_binary (PLUS
, tmode
,
12040 gen_lowpart (tmode
, inner
),
12045 /* ... fall through ... */
12047 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12048 the low order N bits of FOO are known to be zero, we can do this
12049 by comparing FOO with C shifted left N bits so long as no
12050 overflow occurs. Even if the low order N bits of FOO aren't known
12051 to be zero, if the comparison is >= or < we can use the same
12052 optimization and for > or <= by setting all the low
12053 order N bits in the comparison constant. */
12054 if (CONST_INT_P (XEXP (op0
, 1))
12055 && INTVAL (XEXP (op0
, 1)) > 0
12056 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12057 && mode_width
<= HOST_BITS_PER_WIDE_INT
12058 && (((unsigned HOST_WIDE_INT
) const_op
12059 + (GET_CODE (op0
) != LSHIFTRT
12060 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12063 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12065 unsigned HOST_WIDE_INT low_bits
12066 = (nonzero_bits (XEXP (op0
, 0), mode
)
12067 & (((unsigned HOST_WIDE_INT
) 1
12068 << INTVAL (XEXP (op0
, 1))) - 1));
12069 if (low_bits
== 0 || !equality_comparison_p
)
12071 /* If the shift was logical, then we must make the condition
12073 if (GET_CODE (op0
) == LSHIFTRT
)
12074 code
= unsigned_condition (code
);
12076 const_op
<<= INTVAL (XEXP (op0
, 1));
12078 && (code
== GT
|| code
== GTU
12079 || code
== LE
|| code
== LEU
))
12081 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12082 op1
= GEN_INT (const_op
);
12083 op0
= XEXP (op0
, 0);
12088 /* If we are using this shift to extract just the sign bit, we
12089 can replace this with an LT or GE comparison. */
12091 && (equality_comparison_p
|| sign_bit_comparison_p
)
12092 && CONST_INT_P (XEXP (op0
, 1))
12093 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12095 op0
= XEXP (op0
, 0);
12096 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12108 /* Now make any compound operations involved in this comparison. Then,
12109 check for an outmost SUBREG on OP0 that is not doing anything or is
12110 paradoxical. The latter transformation must only be performed when
12111 it is known that the "extra" bits will be the same in op0 and op1 or
12112 that they don't matter. There are three cases to consider:
12114 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12115 care bits and we can assume they have any convenient value. So
12116 making the transformation is safe.
12118 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12119 In this case the upper bits of op0 are undefined. We should not make
12120 the simplification in that case as we do not know the contents of
12123 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12124 UNKNOWN. In that case we know those bits are zeros or ones. We must
12125 also be sure that they are the same as the upper bits of op1.
12127 We can never remove a SUBREG for a non-equality comparison because
12128 the sign bit is in a different place in the underlying object. */
12130 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12131 op1
= make_compound_operation (op1
, SET
);
12133 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12134 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12135 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12136 && (code
== NE
|| code
== EQ
))
12138 if (paradoxical_subreg_p (op0
))
12140 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12142 if (REG_P (SUBREG_REG (op0
)))
12144 op0
= SUBREG_REG (op0
);
12145 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12148 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12149 <= HOST_BITS_PER_WIDE_INT
)
12150 && (nonzero_bits (SUBREG_REG (op0
),
12151 GET_MODE (SUBREG_REG (op0
)))
12152 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12154 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12156 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12157 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12158 op0
= SUBREG_REG (op0
), op1
= tem
;
12162 /* We now do the opposite procedure: Some machines don't have compare
12163 insns in all modes. If OP0's mode is an integer mode smaller than a
12164 word and we can't do a compare in that mode, see if there is a larger
12165 mode for which we can do the compare. There are a number of cases in
12166 which we can use the wider mode. */
12168 mode
= GET_MODE (op0
);
12169 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12170 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12171 && ! have_insn_for (COMPARE
, mode
))
12172 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12173 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12174 tmode
= GET_MODE_WIDER_MODE (tmode
))
12175 if (have_insn_for (COMPARE
, tmode
))
12179 /* If this is a test for negative, we can make an explicit
12180 test of the sign bit. Test this first so we can use
12181 a paradoxical subreg to extend OP0. */
12183 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12184 && HWI_COMPUTABLE_MODE_P (mode
))
12186 unsigned HOST_WIDE_INT sign
12187 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12188 op0
= simplify_gen_binary (AND
, tmode
,
12189 gen_lowpart (tmode
, op0
),
12190 gen_int_mode (sign
, tmode
));
12191 code
= (code
== LT
) ? NE
: EQ
;
12195 /* If the only nonzero bits in OP0 and OP1 are those in the
12196 narrower mode and this is an equality or unsigned comparison,
12197 we can use the wider mode. Similarly for sign-extended
12198 values, in which case it is true for all comparisons. */
12199 zero_extended
= ((code
== EQ
|| code
== NE
12200 || code
== GEU
|| code
== GTU
12201 || code
== LEU
|| code
== LTU
)
12202 && (nonzero_bits (op0
, tmode
)
12203 & ~GET_MODE_MASK (mode
)) == 0
12204 && ((CONST_INT_P (op1
)
12205 || (nonzero_bits (op1
, tmode
)
12206 & ~GET_MODE_MASK (mode
)) == 0)));
12209 || ((num_sign_bit_copies (op0
, tmode
)
12210 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12211 - GET_MODE_PRECISION (mode
)))
12212 && (num_sign_bit_copies (op1
, tmode
)
12213 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12214 - GET_MODE_PRECISION (mode
)))))
12216 /* If OP0 is an AND and we don't have an AND in MODE either,
12217 make a new AND in the proper mode. */
12218 if (GET_CODE (op0
) == AND
12219 && !have_insn_for (AND
, mode
))
12220 op0
= simplify_gen_binary (AND
, tmode
,
12221 gen_lowpart (tmode
,
12223 gen_lowpart (tmode
,
12229 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12230 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12234 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12235 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12242 /* We may have changed the comparison operands. Re-canonicalize. */
12243 if (swap_commutative_operands_p (op0
, op1
))
12245 tem
= op0
, op0
= op1
, op1
= tem
;
12246 code
= swap_condition (code
);
12249 /* If this machine only supports a subset of valid comparisons, see if we
12250 can convert an unsupported one into a supported one. */
12251 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12259 /* Utility function for record_value_for_reg. Count number of
12264 enum rtx_code code
= GET_CODE (x
);
12268 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12269 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12271 rtx x0
= XEXP (x
, 0);
12272 rtx x1
= XEXP (x
, 1);
12275 return 1 + 2 * count_rtxs (x0
);
12277 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12278 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12279 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12280 return 2 + 2 * count_rtxs (x0
)
12281 + count_rtxs (x
== XEXP (x1
, 0)
12282 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12284 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12285 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12286 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12287 return 2 + 2 * count_rtxs (x1
)
12288 + count_rtxs (x
== XEXP (x0
, 0)
12289 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12292 fmt
= GET_RTX_FORMAT (code
);
12293 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12295 ret
+= count_rtxs (XEXP (x
, i
));
12296 else if (fmt
[i
] == 'E')
12297 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12298 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12303 /* Utility function for following routine. Called when X is part of a value
12304 being stored into last_set_value. Sets last_set_table_tick
12305 for each register mentioned. Similar to mention_regs in cse.c */
12308 update_table_tick (rtx x
)
12310 enum rtx_code code
= GET_CODE (x
);
12311 const char *fmt
= GET_RTX_FORMAT (code
);
12316 unsigned int regno
= REGNO (x
);
12317 unsigned int endregno
= END_REGNO (x
);
12320 for (r
= regno
; r
< endregno
; r
++)
12322 reg_stat_type
*rsp
= ®_stat
[r
];
12323 rsp
->last_set_table_tick
= label_tick
;
12329 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12332 /* Check for identical subexpressions. If x contains
12333 identical subexpression we only have to traverse one of
12335 if (i
== 0 && ARITHMETIC_P (x
))
12337 /* Note that at this point x1 has already been
12339 rtx x0
= XEXP (x
, 0);
12340 rtx x1
= XEXP (x
, 1);
12342 /* If x0 and x1 are identical then there is no need to
12347 /* If x0 is identical to a subexpression of x1 then while
12348 processing x1, x0 has already been processed. Thus we
12349 are done with x. */
12350 if (ARITHMETIC_P (x1
)
12351 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12354 /* If x1 is identical to a subexpression of x0 then we
12355 still have to process the rest of x0. */
12356 if (ARITHMETIC_P (x0
)
12357 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12359 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12364 update_table_tick (XEXP (x
, i
));
12366 else if (fmt
[i
] == 'E')
12367 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12368 update_table_tick (XVECEXP (x
, i
, j
));
12371 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12372 are saying that the register is clobbered and we no longer know its
12373 value. If INSN is zero, don't update reg_stat[].last_set; this is
12374 only permitted with VALUE also zero and is used to invalidate the
12378 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12380 unsigned int regno
= REGNO (reg
);
12381 unsigned int endregno
= END_REGNO (reg
);
12383 reg_stat_type
*rsp
;
12385 /* If VALUE contains REG and we have a previous value for REG, substitute
12386 the previous value. */
12387 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12391 /* Set things up so get_last_value is allowed to see anything set up to
12393 subst_low_luid
= DF_INSN_LUID (insn
);
12394 tem
= get_last_value (reg
);
12396 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12397 it isn't going to be useful and will take a lot of time to process,
12398 so just use the CLOBBER. */
12402 if (ARITHMETIC_P (tem
)
12403 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12404 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12405 tem
= XEXP (tem
, 0);
12406 else if (count_occurrences (value
, reg
, 1) >= 2)
12408 /* If there are two or more occurrences of REG in VALUE,
12409 prevent the value from growing too much. */
12410 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12411 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12414 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12418 /* For each register modified, show we don't know its value, that
12419 we don't know about its bitwise content, that its value has been
12420 updated, and that we don't know the location of the death of the
12422 for (i
= regno
; i
< endregno
; i
++)
12424 rsp
= ®_stat
[i
];
12427 rsp
->last_set
= insn
;
12429 rsp
->last_set_value
= 0;
12430 rsp
->last_set_mode
= VOIDmode
;
12431 rsp
->last_set_nonzero_bits
= 0;
12432 rsp
->last_set_sign_bit_copies
= 0;
12433 rsp
->last_death
= 0;
12434 rsp
->truncated_to_mode
= VOIDmode
;
12437 /* Mark registers that are being referenced in this value. */
12439 update_table_tick (value
);
12441 /* Now update the status of each register being set.
12442 If someone is using this register in this block, set this register
12443 to invalid since we will get confused between the two lives in this
12444 basic block. This makes using this register always invalid. In cse, we
12445 scan the table to invalidate all entries using this register, but this
12446 is too much work for us. */
12448 for (i
= regno
; i
< endregno
; i
++)
12450 rsp
= ®_stat
[i
];
12451 rsp
->last_set_label
= label_tick
;
12453 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12454 rsp
->last_set_invalid
= 1;
12456 rsp
->last_set_invalid
= 0;
12459 /* The value being assigned might refer to X (like in "x++;"). In that
12460 case, we must replace it with (clobber (const_int 0)) to prevent
12462 rsp
= ®_stat
[regno
];
12463 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12465 value
= copy_rtx (value
);
12466 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12470 /* For the main register being modified, update the value, the mode, the
12471 nonzero bits, and the number of sign bit copies. */
12473 rsp
->last_set_value
= value
;
12477 machine_mode mode
= GET_MODE (reg
);
12478 subst_low_luid
= DF_INSN_LUID (insn
);
12479 rsp
->last_set_mode
= mode
;
12480 if (GET_MODE_CLASS (mode
) == MODE_INT
12481 && HWI_COMPUTABLE_MODE_P (mode
))
12482 mode
= nonzero_bits_mode
;
12483 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12484 rsp
->last_set_sign_bit_copies
12485 = num_sign_bit_copies (value
, GET_MODE (reg
));
12489 /* Called via note_stores from record_dead_and_set_regs to handle one
12490 SET or CLOBBER in an insn. DATA is the instruction in which the
12491 set is occurring. */
12494 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12496 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12498 if (GET_CODE (dest
) == SUBREG
)
12499 dest
= SUBREG_REG (dest
);
12501 if (!record_dead_insn
)
12504 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12510 /* If we are setting the whole register, we know its value. Otherwise
12511 show that we don't know the value. We can handle SUBREG in
12513 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12514 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12515 else if (GET_CODE (setter
) == SET
12516 && GET_CODE (SET_DEST (setter
)) == SUBREG
12517 && SUBREG_REG (SET_DEST (setter
)) == dest
12518 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12519 && subreg_lowpart_p (SET_DEST (setter
)))
12520 record_value_for_reg (dest
, record_dead_insn
,
12521 gen_lowpart (GET_MODE (dest
),
12522 SET_SRC (setter
)));
12524 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12526 else if (MEM_P (dest
)
12527 /* Ignore pushes, they clobber nothing. */
12528 && ! push_operand (dest
, GET_MODE (dest
)))
12529 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12532 /* Update the records of when each REG was most recently set or killed
12533 for the things done by INSN. This is the last thing done in processing
12534 INSN in the combiner loop.
12536 We update reg_stat[], in particular fields last_set, last_set_value,
12537 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12538 last_death, and also the similar information mem_last_set (which insn
12539 most recently modified memory) and last_call_luid (which insn was the
12540 most recent subroutine call). */
12543 record_dead_and_set_regs (rtx_insn
*insn
)
12548 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12550 if (REG_NOTE_KIND (link
) == REG_DEAD
12551 && REG_P (XEXP (link
, 0)))
12553 unsigned int regno
= REGNO (XEXP (link
, 0));
12554 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12556 for (i
= regno
; i
< endregno
; i
++)
12558 reg_stat_type
*rsp
;
12560 rsp
= ®_stat
[i
];
12561 rsp
->last_death
= insn
;
12564 else if (REG_NOTE_KIND (link
) == REG_INC
)
12565 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12570 hard_reg_set_iterator hrsi
;
12571 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12573 reg_stat_type
*rsp
;
12575 rsp
= ®_stat
[i
];
12576 rsp
->last_set_invalid
= 1;
12577 rsp
->last_set
= insn
;
12578 rsp
->last_set_value
= 0;
12579 rsp
->last_set_mode
= VOIDmode
;
12580 rsp
->last_set_nonzero_bits
= 0;
12581 rsp
->last_set_sign_bit_copies
= 0;
12582 rsp
->last_death
= 0;
12583 rsp
->truncated_to_mode
= VOIDmode
;
12586 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12588 /* We can't combine into a call pattern. Remember, though, that
12589 the return value register is set at this LUID. We could
12590 still replace a register with the return value from the
12591 wrong subroutine call! */
12592 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12595 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12598 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12599 register present in the SUBREG, so for each such SUBREG go back and
12600 adjust nonzero and sign bit information of the registers that are
12601 known to have some zero/sign bits set.
12603 This is needed because when combine blows the SUBREGs away, the
12604 information on zero/sign bits is lost and further combines can be
12605 missed because of that. */
12608 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12610 struct insn_link
*links
;
12612 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12613 machine_mode mode
= GET_MODE (subreg
);
12615 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12618 for (links
= LOG_LINKS (insn
); links
;)
12620 reg_stat_type
*rsp
;
12622 insn
= links
->insn
;
12623 set
= single_set (insn
);
12625 if (! set
|| !REG_P (SET_DEST (set
))
12626 || REGNO (SET_DEST (set
)) != regno
12627 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12629 links
= links
->next
;
12633 rsp
= ®_stat
[regno
];
12634 if (rsp
->last_set
== insn
)
12636 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12637 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12640 if (REG_P (SET_SRC (set
)))
12642 regno
= REGNO (SET_SRC (set
));
12643 links
= LOG_LINKS (insn
);
12650 /* Check if X, a register, is known to contain a value already
12651 truncated to MODE. In this case we can use a subreg to refer to
12652 the truncated value even though in the generic case we would need
12653 an explicit truncation. */
12656 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12658 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12659 machine_mode truncated
= rsp
->truncated_to_mode
;
12662 || rsp
->truncation_label
< label_tick_ebb_start
)
12664 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12666 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12671 /* If X is a hard reg or a subreg record the mode that the register is
12672 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12673 to turn a truncate into a subreg using this information. Return true
12674 if traversing X is complete. */
12677 record_truncated_value (rtx x
)
12679 machine_mode truncated_mode
;
12680 reg_stat_type
*rsp
;
12682 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12684 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12685 truncated_mode
= GET_MODE (x
);
12687 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12690 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12693 x
= SUBREG_REG (x
);
12695 /* ??? For hard-regs we now record everything. We might be able to
12696 optimize this using last_set_mode. */
12697 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12698 truncated_mode
= GET_MODE (x
);
12702 rsp
= ®_stat
[REGNO (x
)];
12703 if (rsp
->truncated_to_mode
== 0
12704 || rsp
->truncation_label
< label_tick_ebb_start
12705 || (GET_MODE_SIZE (truncated_mode
)
12706 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12708 rsp
->truncated_to_mode
= truncated_mode
;
12709 rsp
->truncation_label
= label_tick
;
12715 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12716 the modes they are used in. This can help truning TRUNCATEs into
12720 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12722 subrtx_var_iterator::array_type array
;
12723 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12724 if (record_truncated_value (*iter
))
12725 iter
.skip_subrtxes ();
12728 /* Scan X for promoted SUBREGs. For each one found,
12729 note what it implies to the registers used in it. */
12732 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12734 if (GET_CODE (x
) == SUBREG
12735 && SUBREG_PROMOTED_VAR_P (x
)
12736 && REG_P (SUBREG_REG (x
)))
12737 record_promoted_value (insn
, x
);
12740 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12743 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12747 check_promoted_subreg (insn
, XEXP (x
, i
));
12751 if (XVEC (x
, i
) != 0)
12752 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12753 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12759 /* Verify that all the registers and memory references mentioned in *LOC are
12760 still valid. *LOC was part of a value set in INSN when label_tick was
12761 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12762 the invalid references with (clobber (const_int 0)) and return 1. This
12763 replacement is useful because we often can get useful information about
12764 the form of a value (e.g., if it was produced by a shift that always
12765 produces -1 or 0) even though we don't know exactly what registers it
12766 was produced from. */
12769 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12772 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12773 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12778 unsigned int regno
= REGNO (x
);
12779 unsigned int endregno
= END_REGNO (x
);
12782 for (j
= regno
; j
< endregno
; j
++)
12784 reg_stat_type
*rsp
= ®_stat
[j
];
12785 if (rsp
->last_set_invalid
12786 /* If this is a pseudo-register that was only set once and not
12787 live at the beginning of the function, it is always valid. */
12788 || (! (regno
>= FIRST_PSEUDO_REGISTER
12789 && REG_N_SETS (regno
) == 1
12790 && (!REGNO_REG_SET_P
12791 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12793 && rsp
->last_set_label
> tick
))
12796 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12803 /* If this is a memory reference, make sure that there were no stores after
12804 it that might have clobbered the value. We don't have alias info, so we
12805 assume any store invalidates it. Moreover, we only have local UIDs, so
12806 we also assume that there were stores in the intervening basic blocks. */
12807 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12808 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12811 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12815 for (i
= 0; i
< len
; i
++)
12819 /* Check for identical subexpressions. If x contains
12820 identical subexpression we only have to traverse one of
12822 if (i
== 1 && ARITHMETIC_P (x
))
12824 /* Note that at this point x0 has already been checked
12825 and found valid. */
12826 rtx x0
= XEXP (x
, 0);
12827 rtx x1
= XEXP (x
, 1);
12829 /* If x0 and x1 are identical then x is also valid. */
12833 /* If x1 is identical to a subexpression of x0 then
12834 while checking x0, x1 has already been checked. Thus
12835 it is valid and so as x. */
12836 if (ARITHMETIC_P (x0
)
12837 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12840 /* If x0 is identical to a subexpression of x1 then x is
12841 valid iff the rest of x1 is valid. */
12842 if (ARITHMETIC_P (x1
)
12843 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12845 get_last_value_validate (&XEXP (x1
,
12846 x0
== XEXP (x1
, 0) ? 1 : 0),
12847 insn
, tick
, replace
);
12850 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12854 else if (fmt
[i
] == 'E')
12855 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12856 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12857 insn
, tick
, replace
) == 0)
12861 /* If we haven't found a reason for it to be invalid, it is valid. */
12865 /* Get the last value assigned to X, if known. Some registers
12866 in the value may be replaced with (clobber (const_int 0)) if their value
12867 is known longer known reliably. */
12870 get_last_value (const_rtx x
)
12872 unsigned int regno
;
12874 reg_stat_type
*rsp
;
12876 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12877 then convert it to the desired mode. If this is a paradoxical SUBREG,
12878 we cannot predict what values the "extra" bits might have. */
12879 if (GET_CODE (x
) == SUBREG
12880 && subreg_lowpart_p (x
)
12881 && !paradoxical_subreg_p (x
)
12882 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12883 return gen_lowpart (GET_MODE (x
), value
);
12889 rsp
= ®_stat
[regno
];
12890 value
= rsp
->last_set_value
;
12892 /* If we don't have a value, or if it isn't for this basic block and
12893 it's either a hard register, set more than once, or it's a live
12894 at the beginning of the function, return 0.
12896 Because if it's not live at the beginning of the function then the reg
12897 is always set before being used (is never used without being set).
12898 And, if it's set only once, and it's always set before use, then all
12899 uses must have the same last value, even if it's not from this basic
12903 || (rsp
->last_set_label
< label_tick_ebb_start
12904 && (regno
< FIRST_PSEUDO_REGISTER
12905 || REG_N_SETS (regno
) != 1
12907 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12910 /* If the value was set in a later insn than the ones we are processing,
12911 we can't use it even if the register was only set once. */
12912 if (rsp
->last_set_label
== label_tick
12913 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12916 /* If the value has all its registers valid, return it. */
12917 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12920 /* Otherwise, make a copy and replace any invalid register with
12921 (clobber (const_int 0)). If that fails for some reason, return 0. */
12923 value
= copy_rtx (value
);
12924 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12930 /* Return nonzero if expression X refers to a REG or to memory
12931 that is set in an instruction more recent than FROM_LUID. */
12934 use_crosses_set_p (const_rtx x
, int from_luid
)
12938 enum rtx_code code
= GET_CODE (x
);
12942 unsigned int regno
= REGNO (x
);
12943 unsigned endreg
= END_REGNO (x
);
12945 #ifdef PUSH_ROUNDING
12946 /* Don't allow uses of the stack pointer to be moved,
12947 because we don't know whether the move crosses a push insn. */
12948 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12951 for (; regno
< endreg
; regno
++)
12953 reg_stat_type
*rsp
= ®_stat
[regno
];
12955 && rsp
->last_set_label
== label_tick
12956 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12962 if (code
== MEM
&& mem_last_set
> from_luid
)
12965 fmt
= GET_RTX_FORMAT (code
);
12967 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12972 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12973 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12976 else if (fmt
[i
] == 'e'
12977 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12983 /* Define three variables used for communication between the following
12986 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12987 static int reg_dead_flag
;
12989 /* Function called via note_stores from reg_dead_at_p.
12991 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12992 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12995 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12997 unsigned int regno
, endregno
;
13002 regno
= REGNO (dest
);
13003 endregno
= END_REGNO (dest
);
13004 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13005 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13008 /* Return nonzero if REG is known to be dead at INSN.
13010 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13011 referencing REG, it is dead. If we hit a SET referencing REG, it is
13012 live. Otherwise, see if it is live or dead at the start of the basic
13013 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13014 must be assumed to be always live. */
13017 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13022 /* Set variables for reg_dead_at_p_1. */
13023 reg_dead_regno
= REGNO (reg
);
13024 reg_dead_endregno
= END_REGNO (reg
);
13028 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13029 we allow the machine description to decide whether use-and-clobber
13030 patterns are OK. */
13031 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13033 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13034 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13038 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13039 beginning of basic block. */
13040 block
= BLOCK_FOR_INSN (insn
);
13045 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13048 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13050 return reg_dead_flag
== 1 ? 1 : 0;
13052 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13056 if (insn
== BB_HEAD (block
))
13059 insn
= PREV_INSN (insn
);
13062 /* Look at live-in sets for the basic block that we were in. */
13063 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13064 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13070 /* Note hard registers in X that are used. */
13073 mark_used_regs_combine (rtx x
)
13075 RTX_CODE code
= GET_CODE (x
);
13076 unsigned int regno
;
13087 case ADDR_DIFF_VEC
:
13090 /* CC0 must die in the insn after it is set, so we don't need to take
13091 special note of it here. */
13097 /* If we are clobbering a MEM, mark any hard registers inside the
13098 address as used. */
13099 if (MEM_P (XEXP (x
, 0)))
13100 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13105 /* A hard reg in a wide mode may really be multiple registers.
13106 If so, mark all of them just like the first. */
13107 if (regno
< FIRST_PSEUDO_REGISTER
)
13109 /* None of this applies to the stack, frame or arg pointers. */
13110 if (regno
== STACK_POINTER_REGNUM
13111 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13112 || regno
== HARD_FRAME_POINTER_REGNUM
13114 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13115 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13117 || regno
== FRAME_POINTER_REGNUM
)
13120 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13126 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13128 rtx testreg
= SET_DEST (x
);
13130 while (GET_CODE (testreg
) == SUBREG
13131 || GET_CODE (testreg
) == ZERO_EXTRACT
13132 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13133 testreg
= XEXP (testreg
, 0);
13135 if (MEM_P (testreg
))
13136 mark_used_regs_combine (XEXP (testreg
, 0));
13138 mark_used_regs_combine (SET_SRC (x
));
13146 /* Recursively scan the operands of this expression. */
13149 const char *fmt
= GET_RTX_FORMAT (code
);
13151 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13154 mark_used_regs_combine (XEXP (x
, i
));
13155 else if (fmt
[i
] == 'E')
13159 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13160 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13166 /* Remove register number REGNO from the dead registers list of INSN.
13168 Return the note used to record the death, if there was one. */
13171 remove_death (unsigned int regno
, rtx_insn
*insn
)
13173 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13176 remove_note (insn
, note
);
13181 /* For each register (hardware or pseudo) used within expression X, if its
13182 death is in an instruction with luid between FROM_LUID (inclusive) and
13183 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13184 list headed by PNOTES.
13186 That said, don't move registers killed by maybe_kill_insn.
13188 This is done when X is being merged by combination into TO_INSN. These
13189 notes will then be distributed as needed. */
13192 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13197 enum rtx_code code
= GET_CODE (x
);
13201 unsigned int regno
= REGNO (x
);
13202 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13204 /* Don't move the register if it gets killed in between from and to. */
13205 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13206 && ! reg_referenced_p (x
, maybe_kill_insn
))
13210 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13211 && DF_INSN_LUID (where_dead
) >= from_luid
13212 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13214 rtx note
= remove_death (regno
, where_dead
);
13216 /* It is possible for the call above to return 0. This can occur
13217 when last_death points to I2 or I1 that we combined with.
13218 In that case make a new note.
13220 We must also check for the case where X is a hard register
13221 and NOTE is a death note for a range of hard registers
13222 including X. In that case, we must put REG_DEAD notes for
13223 the remaining registers in place of NOTE. */
13225 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13226 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13227 > GET_MODE_SIZE (GET_MODE (x
))))
13229 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13230 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13231 unsigned int ourend
= END_HARD_REGNO (x
);
13234 for (i
= deadregno
; i
< deadend
; i
++)
13235 if (i
< regno
|| i
>= ourend
)
13236 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13239 /* If we didn't find any note, or if we found a REG_DEAD note that
13240 covers only part of the given reg, and we have a multi-reg hard
13241 register, then to be safe we must check for REG_DEAD notes
13242 for each register other than the first. They could have
13243 their own REG_DEAD notes lying around. */
13244 else if ((note
== 0
13246 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13247 < GET_MODE_SIZE (GET_MODE (x
)))))
13248 && regno
< FIRST_PSEUDO_REGISTER
13249 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13251 unsigned int ourend
= END_HARD_REGNO (x
);
13252 unsigned int i
, offset
;
13256 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13260 for (i
= regno
+ offset
; i
< ourend
; i
++)
13261 move_deaths (regno_reg_rtx
[i
],
13262 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13265 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13267 XEXP (note
, 1) = *pnotes
;
13271 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13277 else if (GET_CODE (x
) == SET
)
13279 rtx dest
= SET_DEST (x
);
13281 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13283 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13284 that accesses one word of a multi-word item, some
13285 piece of everything register in the expression is used by
13286 this insn, so remove any old death. */
13287 /* ??? So why do we test for equality of the sizes? */
13289 if (GET_CODE (dest
) == ZERO_EXTRACT
13290 || GET_CODE (dest
) == STRICT_LOW_PART
13291 || (GET_CODE (dest
) == SUBREG
13292 && (((GET_MODE_SIZE (GET_MODE (dest
))
13293 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13294 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13295 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13297 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13301 /* If this is some other SUBREG, we know it replaces the entire
13302 value, so use that as the destination. */
13303 if (GET_CODE (dest
) == SUBREG
)
13304 dest
= SUBREG_REG (dest
);
13306 /* If this is a MEM, adjust deaths of anything used in the address.
13307 For a REG (the only other possibility), the entire value is
13308 being replaced so the old value is not used in this insn. */
13311 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13316 else if (GET_CODE (x
) == CLOBBER
)
13319 len
= GET_RTX_LENGTH (code
);
13320 fmt
= GET_RTX_FORMAT (code
);
13322 for (i
= 0; i
< len
; i
++)
13327 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13328 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13331 else if (fmt
[i
] == 'e')
13332 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13336 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13337 pattern of an insn. X must be a REG. */
13340 reg_bitfield_target_p (rtx x
, rtx body
)
13344 if (GET_CODE (body
) == SET
)
13346 rtx dest
= SET_DEST (body
);
13348 unsigned int regno
, tregno
, endregno
, endtregno
;
13350 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13351 target
= XEXP (dest
, 0);
13352 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13353 target
= SUBREG_REG (XEXP (dest
, 0));
13357 if (GET_CODE (target
) == SUBREG
)
13358 target
= SUBREG_REG (target
);
13360 if (!REG_P (target
))
13363 tregno
= REGNO (target
), regno
= REGNO (x
);
13364 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13365 return target
== x
;
13367 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13368 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13370 return endregno
> tregno
&& regno
< endtregno
;
13373 else if (GET_CODE (body
) == PARALLEL
)
13374 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13375 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13381 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13382 as appropriate. I3 and I2 are the insns resulting from the combination
13383 insns including FROM (I2 may be zero).
13385 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13386 not need REG_DEAD notes because they are being substituted for. This
13387 saves searching in the most common cases.
13389 Each note in the list is either ignored or placed on some insns, depending
13390 on the type of note. */
13393 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13394 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13396 rtx note
, next_note
;
13398 rtx_insn
*tem_insn
;
13400 for (note
= notes
; note
; note
= next_note
)
13402 rtx_insn
*place
= 0, *place2
= 0;
13404 next_note
= XEXP (note
, 1);
13405 switch (REG_NOTE_KIND (note
))
13409 /* Doesn't matter much where we put this, as long as it's somewhere.
13410 It is preferable to keep these notes on branches, which is most
13411 likely to be i3. */
13415 case REG_NON_LOCAL_GOTO
:
13420 gcc_assert (i2
&& JUMP_P (i2
));
13425 case REG_EH_REGION
:
13426 /* These notes must remain with the call or trapping instruction. */
13429 else if (i2
&& CALL_P (i2
))
13433 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13434 if (may_trap_p (i3
))
13436 else if (i2
&& may_trap_p (i2
))
13438 /* ??? Otherwise assume we've combined things such that we
13439 can now prove that the instructions can't trap. Drop the
13440 note in this case. */
13444 case REG_ARGS_SIZE
:
13445 /* ??? How to distribute between i3-i1. Assume i3 contains the
13446 entire adjustment. Assert i3 contains at least some adjust. */
13447 if (!noop_move_p (i3
))
13449 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13450 /* fixup_args_size_notes looks at REG_NORETURN note,
13451 so ensure the note is placed there first. */
13455 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13456 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13460 XEXP (n
, 1) = REG_NOTES (i3
);
13461 REG_NOTES (i3
) = n
;
13465 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13466 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13467 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13468 gcc_assert (old_size
!= args_size
13470 && !ACCUMULATE_OUTGOING_ARGS
13471 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13478 case REG_CALL_DECL
:
13479 /* These notes must remain with the call. It should not be
13480 possible for both I2 and I3 to be a call. */
13485 gcc_assert (i2
&& CALL_P (i2
));
13491 /* Any clobbers for i3 may still exist, and so we must process
13492 REG_UNUSED notes from that insn.
13494 Any clobbers from i2 or i1 can only exist if they were added by
13495 recog_for_combine. In that case, recog_for_combine created the
13496 necessary REG_UNUSED notes. Trying to keep any original
13497 REG_UNUSED notes from these insns can cause incorrect output
13498 if it is for the same register as the original i3 dest.
13499 In that case, we will notice that the register is set in i3,
13500 and then add a REG_UNUSED note for the destination of i3, which
13501 is wrong. However, it is possible to have REG_UNUSED notes from
13502 i2 or i1 for register which were both used and clobbered, so
13503 we keep notes from i2 or i1 if they will turn into REG_DEAD
13506 /* If this register is set or clobbered in I3, put the note there
13507 unless there is one already. */
13508 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13510 if (from_insn
!= i3
)
13513 if (! (REG_P (XEXP (note
, 0))
13514 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13515 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13518 /* Otherwise, if this register is used by I3, then this register
13519 now dies here, so we must put a REG_DEAD note here unless there
13521 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13522 && ! (REG_P (XEXP (note
, 0))
13523 ? find_regno_note (i3
, REG_DEAD
,
13524 REGNO (XEXP (note
, 0)))
13525 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13527 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13535 /* These notes say something about results of an insn. We can
13536 only support them if they used to be on I3 in which case they
13537 remain on I3. Otherwise they are ignored.
13539 If the note refers to an expression that is not a constant, we
13540 must also ignore the note since we cannot tell whether the
13541 equivalence is still true. It might be possible to do
13542 slightly better than this (we only have a problem if I2DEST
13543 or I1DEST is present in the expression), but it doesn't
13544 seem worth the trouble. */
13546 if (from_insn
== i3
13547 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13552 /* These notes say something about how a register is used. They must
13553 be present on any use of the register in I2 or I3. */
13554 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13557 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13566 case REG_LABEL_TARGET
:
13567 case REG_LABEL_OPERAND
:
13568 /* This can show up in several ways -- either directly in the
13569 pattern, or hidden off in the constant pool with (or without?)
13570 a REG_EQUAL note. */
13571 /* ??? Ignore the without-reg_equal-note problem for now. */
13572 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13573 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13574 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13575 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13579 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13580 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13581 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13582 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13590 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13591 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13593 if (place
&& JUMP_P (place
)
13594 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13595 && (JUMP_LABEL (place
) == NULL
13596 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13598 rtx label
= JUMP_LABEL (place
);
13601 JUMP_LABEL (place
) = XEXP (note
, 0);
13602 else if (LABEL_P (label
))
13603 LABEL_NUSES (label
)--;
13606 if (place2
&& JUMP_P (place2
)
13607 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13608 && (JUMP_LABEL (place2
) == NULL
13609 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13611 rtx label
= JUMP_LABEL (place2
);
13614 JUMP_LABEL (place2
) = XEXP (note
, 0);
13615 else if (LABEL_P (label
))
13616 LABEL_NUSES (label
)--;
13622 /* This note says something about the value of a register prior
13623 to the execution of an insn. It is too much trouble to see
13624 if the note is still correct in all situations. It is better
13625 to simply delete it. */
13629 /* If we replaced the right hand side of FROM_INSN with a
13630 REG_EQUAL note, the original use of the dying register
13631 will not have been combined into I3 and I2. In such cases,
13632 FROM_INSN is guaranteed to be the first of the combined
13633 instructions, so we simply need to search back before
13634 FROM_INSN for the previous use or set of this register,
13635 then alter the notes there appropriately.
13637 If the register is used as an input in I3, it dies there.
13638 Similarly for I2, if it is nonzero and adjacent to I3.
13640 If the register is not used as an input in either I3 or I2
13641 and it is not one of the registers we were supposed to eliminate,
13642 there are two possibilities. We might have a non-adjacent I2
13643 or we might have somehow eliminated an additional register
13644 from a computation. For example, we might have had A & B where
13645 we discover that B will always be zero. In this case we will
13646 eliminate the reference to A.
13648 In both cases, we must search to see if we can find a previous
13649 use of A and put the death note there. */
13652 && from_insn
== i2mod
13653 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13654 tem_insn
= from_insn
;
13658 && CALL_P (from_insn
)
13659 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13661 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13663 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13664 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13666 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13668 && reg_overlap_mentioned_p (XEXP (note
, 0),
13670 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13671 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13678 basic_block bb
= this_basic_block
;
13680 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13682 if (!NONDEBUG_INSN_P (tem_insn
))
13684 if (tem_insn
== BB_HEAD (bb
))
13689 /* If the register is being set at TEM_INSN, see if that is all
13690 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13691 into a REG_UNUSED note instead. Don't delete sets to
13692 global register vars. */
13693 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13694 || !global_regs
[REGNO (XEXP (note
, 0))])
13695 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13697 rtx set
= single_set (tem_insn
);
13698 rtx inner_dest
= 0;
13700 rtx_insn
*cc0_setter
= NULL
;
13704 for (inner_dest
= SET_DEST (set
);
13705 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13706 || GET_CODE (inner_dest
) == SUBREG
13707 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13708 inner_dest
= XEXP (inner_dest
, 0))
13711 /* Verify that it was the set, and not a clobber that
13712 modified the register.
13714 CC0 targets must be careful to maintain setter/user
13715 pairs. If we cannot delete the setter due to side
13716 effects, mark the user with an UNUSED note instead
13719 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13720 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13722 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13723 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13724 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13728 /* Move the notes and links of TEM_INSN elsewhere.
13729 This might delete other dead insns recursively.
13730 First set the pattern to something that won't use
13732 rtx old_notes
= REG_NOTES (tem_insn
);
13734 PATTERN (tem_insn
) = pc_rtx
;
13735 REG_NOTES (tem_insn
) = NULL
;
13737 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13738 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13739 distribute_links (LOG_LINKS (tem_insn
));
13741 SET_INSN_DELETED (tem_insn
);
13742 if (tem_insn
== i2
)
13746 /* Delete the setter too. */
13749 PATTERN (cc0_setter
) = pc_rtx
;
13750 old_notes
= REG_NOTES (cc0_setter
);
13751 REG_NOTES (cc0_setter
) = NULL
;
13753 distribute_notes (old_notes
, cc0_setter
,
13755 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13756 distribute_links (LOG_LINKS (cc0_setter
));
13758 SET_INSN_DELETED (cc0_setter
);
13759 if (cc0_setter
== i2
)
13766 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13768 /* If there isn't already a REG_UNUSED note, put one
13769 here. Do not place a REG_DEAD note, even if
13770 the register is also used here; that would not
13771 match the algorithm used in lifetime analysis
13772 and can cause the consistency check in the
13773 scheduler to fail. */
13774 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13775 REGNO (XEXP (note
, 0))))
13780 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13781 || (CALL_P (tem_insn
)
13782 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13786 /* If we are doing a 3->2 combination, and we have a
13787 register which formerly died in i3 and was not used
13788 by i2, which now no longer dies in i3 and is used in
13789 i2 but does not die in i2, and place is between i2
13790 and i3, then we may need to move a link from place to
13792 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13794 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13795 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13797 struct insn_link
*links
= LOG_LINKS (place
);
13798 LOG_LINKS (place
) = NULL
;
13799 distribute_links (links
);
13804 if (tem_insn
== BB_HEAD (bb
))
13810 /* If the register is set or already dead at PLACE, we needn't do
13811 anything with this note if it is still a REG_DEAD note.
13812 We check here if it is set at all, not if is it totally replaced,
13813 which is what `dead_or_set_p' checks, so also check for it being
13816 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13818 unsigned int regno
= REGNO (XEXP (note
, 0));
13819 reg_stat_type
*rsp
= ®_stat
[regno
];
13821 if (dead_or_set_p (place
, XEXP (note
, 0))
13822 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13824 /* Unless the register previously died in PLACE, clear
13825 last_death. [I no longer understand why this is
13827 if (rsp
->last_death
!= place
)
13828 rsp
->last_death
= 0;
13832 rsp
->last_death
= place
;
13834 /* If this is a death note for a hard reg that is occupying
13835 multiple registers, ensure that we are still using all
13836 parts of the object. If we find a piece of the object
13837 that is unused, we must arrange for an appropriate REG_DEAD
13838 note to be added for it. However, we can't just emit a USE
13839 and tag the note to it, since the register might actually
13840 be dead; so we recourse, and the recursive call then finds
13841 the previous insn that used this register. */
13843 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13844 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13846 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13847 bool all_used
= true;
13850 for (i
= regno
; i
< endregno
; i
++)
13851 if ((! refers_to_regno_p (i
, PATTERN (place
))
13852 && ! find_regno_fusage (place
, USE
, i
))
13853 || dead_or_set_regno_p (place
, i
))
13861 /* Put only REG_DEAD notes for pieces that are
13862 not already dead or set. */
13864 for (i
= regno
; i
< endregno
;
13865 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13867 rtx piece
= regno_reg_rtx
[i
];
13868 basic_block bb
= this_basic_block
;
13870 if (! dead_or_set_p (place
, piece
)
13871 && ! reg_bitfield_target_p (piece
,
13874 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13877 distribute_notes (new_note
, place
, place
,
13878 NULL
, NULL_RTX
, NULL_RTX
,
13881 else if (! refers_to_regno_p (i
, PATTERN (place
))
13882 && ! find_regno_fusage (place
, USE
, i
))
13883 for (tem_insn
= PREV_INSN (place
); ;
13884 tem_insn
= PREV_INSN (tem_insn
))
13886 if (!NONDEBUG_INSN_P (tem_insn
))
13888 if (tem_insn
== BB_HEAD (bb
))
13892 if (dead_or_set_p (tem_insn
, piece
)
13893 || reg_bitfield_target_p (piece
,
13894 PATTERN (tem_insn
)))
13896 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
13909 /* Any other notes should not be present at this point in the
13911 gcc_unreachable ();
13916 XEXP (note
, 1) = REG_NOTES (place
);
13917 REG_NOTES (place
) = note
;
13921 add_shallow_copy_of_reg_note (place2
, note
);
13925 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13926 I3, I2, and I1 to new locations. This is also called to add a link
13927 pointing at I3 when I3's destination is changed. */
13930 distribute_links (struct insn_link
*links
)
13932 struct insn_link
*link
, *next_link
;
13934 for (link
= links
; link
; link
= next_link
)
13936 rtx_insn
*place
= 0;
13940 next_link
= link
->next
;
13942 /* If the insn that this link points to is a NOTE, ignore it. */
13943 if (NOTE_P (link
->insn
))
13947 rtx pat
= PATTERN (link
->insn
);
13948 if (GET_CODE (pat
) == SET
)
13950 else if (GET_CODE (pat
) == PARALLEL
)
13953 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
13955 set
= XVECEXP (pat
, 0, i
);
13956 if (GET_CODE (set
) != SET
)
13959 reg
= SET_DEST (set
);
13960 while (GET_CODE (reg
) == ZERO_EXTRACT
13961 || GET_CODE (reg
) == STRICT_LOW_PART
13962 || GET_CODE (reg
) == SUBREG
)
13963 reg
= XEXP (reg
, 0);
13968 if (REGNO (reg
) == link
->regno
)
13971 if (i
== XVECLEN (pat
, 0))
13977 reg
= SET_DEST (set
);
13979 while (GET_CODE (reg
) == ZERO_EXTRACT
13980 || GET_CODE (reg
) == STRICT_LOW_PART
13981 || GET_CODE (reg
) == SUBREG
)
13982 reg
= XEXP (reg
, 0);
13984 /* A LOG_LINK is defined as being placed on the first insn that uses
13985 a register and points to the insn that sets the register. Start
13986 searching at the next insn after the target of the link and stop
13987 when we reach a set of the register or the end of the basic block.
13989 Note that this correctly handles the link that used to point from
13990 I3 to I2. Also note that not much searching is typically done here
13991 since most links don't point very far away. */
13993 for (insn
= NEXT_INSN (link
->insn
);
13994 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13995 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13996 insn
= NEXT_INSN (insn
))
13997 if (DEBUG_INSN_P (insn
))
13999 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14001 if (reg_referenced_p (reg
, PATTERN (insn
)))
14005 else if (CALL_P (insn
)
14006 && find_reg_fusage (insn
, USE
, reg
))
14011 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14014 /* If we found a place to put the link, place it there unless there
14015 is already a link to the same insn as LINK at that point. */
14019 struct insn_link
*link2
;
14021 FOR_EACH_LOG_LINK (link2
, place
)
14022 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14027 link
->next
= LOG_LINKS (place
);
14028 LOG_LINKS (place
) = link
;
14030 /* Set added_links_insn to the earliest insn we added a
14032 if (added_links_insn
== 0
14033 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14034 added_links_insn
= place
;
14040 /* Check for any register or memory mentioned in EQUIV that is not
14041 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14042 of EXPR where some registers may have been replaced by constants. */
14045 unmentioned_reg_p (rtx equiv
, rtx expr
)
14047 subrtx_iterator::array_type array
;
14048 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14050 const_rtx x
= *iter
;
14051 if ((REG_P (x
) || MEM_P (x
))
14052 && !reg_mentioned_p (x
, expr
))
14058 DEBUG_FUNCTION
void
14059 dump_combine_stats (FILE *file
)
14063 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14064 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14068 dump_combine_total_stats (FILE *file
)
14072 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14073 total_attempts
, total_merges
, total_extras
, total_successes
);
14076 /* Try combining insns through substitution. */
14077 static unsigned int
14078 rest_of_handle_combine (void)
14080 int rebuild_jump_labels_after_combine
;
14082 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14083 df_note_add_problem ();
14086 regstat_init_n_sets_and_refs ();
14088 rebuild_jump_labels_after_combine
14089 = combine_instructions (get_insns (), max_reg_num ());
14091 /* Combining insns may have turned an indirect jump into a
14092 direct jump. Rebuild the JUMP_LABEL fields of jumping
14094 if (rebuild_jump_labels_after_combine
)
14096 timevar_push (TV_JUMP
);
14097 rebuild_jump_labels (get_insns ());
14099 timevar_pop (TV_JUMP
);
14102 regstat_free_n_sets_and_refs ();
14108 const pass_data pass_data_combine
=
14110 RTL_PASS
, /* type */
14111 "combine", /* name */
14112 OPTGROUP_NONE
, /* optinfo_flags */
14113 TV_COMBINE
, /* tv_id */
14114 PROP_cfglayout
, /* properties_required */
14115 0, /* properties_provided */
14116 0, /* properties_destroyed */
14117 0, /* todo_flags_start */
14118 TODO_df_finish
, /* todo_flags_finish */
14121 class pass_combine
: public rtl_opt_pass
14124 pass_combine (gcc::context
*ctxt
)
14125 : rtl_opt_pass (pass_data_combine
, ctxt
)
14128 /* opt_pass methods: */
14129 virtual bool gate (function
*) { return (optimize
> 0); }
14130 virtual unsigned int execute (function
*)
14132 return rest_of_handle_combine ();
14135 }; // class pass_combine
14137 } // anon namespace
14140 make_pass_combine (gcc::context
*ctxt
)
14142 return new pass_combine (ctxt
);