| blob | 5d4dc83f44816a5f2ff9e780ce402a634ad1fd83 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
85 /* This file should be included last. */
88 /* Defined for convenience. */
89 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
91 /* Classifies an address.
93 ADDRESS_REG_IMM
94 A simple base register plus immediate offset.
96 ADDRESS_REG_WB
97 A base register indexed by immediate offset with writeback.
99 ADDRESS_REG_REG
100 A base register indexed by (optionally scaled) register.
102 ADDRESS_REG_UXTW
103 A base register indexed by (optionally scaled) zero-extended register.
105 ADDRESS_REG_SXTW
106 A base register indexed by (optionally scaled) sign-extended register.
108 ADDRESS_LO_SUM
109 A LO_SUM rtx with a base register and "LO12" symbol relocation.
111 ADDRESS_SYMBOLIC:
112 A constant symbolic address, in pc-relative literal pool. */
115 ADDRESS_REG_IMM,
116 ADDRESS_REG_WB,
117 ADDRESS_REG_REG,
118 ADDRESS_REG_UXTW,
119 ADDRESS_REG_SXTW,
120 ADDRESS_LO_SUM,
121 ADDRESS_SYMBOLIC
122 };
126 rtx base;
127 rtx offset;
130 };
132 struct simd_immediate_info
133 {
134 rtx value;
139 };
141 /* The current code model. */
144 #ifdef HAVE_AS_TLS
145 #undef TARGET_HAVE_TLS
146 #define TARGET_HAVE_TLS 1
147 #endif
151 const_tree,
163 /* Major revision number of the ARM Architecture implemented by the target. */
166 /* The processor for which instructions should be scheduled. */
169 /* Mask to specify which instructions we are allowed to generate. */
172 /* Mask to specify which instruction scheduling options should be used. */
175 /* Support for command line parsing of boolean flags in the tuning
176 structures. */
177 struct aarch64_flag_desc
178 {
181 };
183 #define AARCH64_FUSION_PAIR(name, internal_name, y) \
184 { name, AARCH64_FUSE_##internal_name },
186 {
191 };
192 #undef AARCH64_FUION_PAIR
194 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name, y) \
195 { name, AARCH64_EXTRA_TUNE_##internal_name },
197 {
202 };
203 #undef AARCH64_EXTRA_TUNING_OPTION
205 /* Tuning parameters. */
208 {
209 {
214 },
220 };
223 {
224 {
229 },
235 };
238 {
239 {
244 },
250 };
253 {
255 /* Avoid the use of slow int<->fp moves for spilling by setting
256 their cost higher than memmov_cost. */
260 };
263 {
265 /* Avoid the use of slow int<->fp moves for spilling by setting
266 their cost higher than memmov_cost. */
270 };
273 {
275 /* Avoid the use of slow int<->fp moves for spilling by setting
276 their cost higher than memmov_cost. */
280 };
283 {
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost. */
298 };
300 /* Generic costs for vector insn classes. */
302 {
315 };
317 /* Generic costs for vector insn classes. */
319 {
332 };
334 /* Generic costs for vector insn classes. */
336 {
349 };
351 /* Generic costs for branch instructions. */
353 {
356 };
359 {
377 };
380 {
399 };
402 {
421 };
424 {
443 };
446 {
464 };
467 {
485 };
487 /* Support for fine-grained override of the tuning structures. */
488 struct aarch64_tuning_override_function
489 {
492 };
497 static const struct aarch64_tuning_override_function
498 aarch64_tuning_override_functions[] =
499 {
503 };
505 /* A processor implementing AArch64. */
506 struct processor
507 {
514 };
516 /* Processor cores implementing AArch64. */
518 {
519 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
520 {NAME, SCHED, #ARCH, ARCH, FLAGS, &COSTS##_tunings},
522 #undef AARCH64_CORE
525 };
527 /* Architectures implementing AArch64. */
529 {
530 #define AARCH64_ARCH(NAME, CORE, ARCH, FLAGS) \
531 {NAME, CORE, #ARCH, ARCH, FLAGS, NULL},
533 #undef AARCH64_ARCH
535 };
537 /* Target specification. These are populated as commandline arguments
538 are processed, or NULL if not specified. */
543 /* The current tuning set. */
546 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
548 /* An ISA extension in the co-processor and main instruction set space. */
549 struct aarch64_option_extension
550 {
554 };
556 /* ISA extensions in AArch64. */
558 {
559 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
560 {NAME, FLAGS_ON, FLAGS_OFF},
562 #undef AARCH64_OPT_EXTENSION
564 };
566 /* Used to track the size of an address when generating a pre/post
567 increment address. */
570 /* A table of valid AArch64 "bitmask immediate" values for
571 logical instructions. */
573 #define AARCH64_NUM_BITMASKS 5334
577 {
581 }
582 aarch64_cc;
584 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
586 /* The condition codes of the processor, and the inverse function. */
588 {
591 };
593 void
595 {
599 else
601 }
603 static unsigned int
605 {
609 }
611 static int
614 {
622 }
624 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
625 unsigned
627 {
635 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
636 equivalent DWARF register. */
638 }
640 /* Return TRUE if MODE is any of the large INT modes. */
641 static bool
643 {
645 }
647 /* Return TRUE if MODE is any of the vector modes. */
648 static bool
650 {
653 }
655 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
656 static bool
659 {
666 }
668 /* Implement HARD_REGNO_NREGS. */
670 int
672 {
674 {
680 }
682 }
684 /* Implement HARD_REGNO_MODE_OK. */
686 int
688 {
693 /* The purpose of comparing with ptr_mode is to support the
694 global register variable associated with the stack pointer
695 register via the syntax of asm ("wsp") in ILP32. */
705 {
707 return
709 else
711 }
714 }
716 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
717 machine_mode
719 machine_mode mode)
720 {
721 /* Handle modes that fit within single registers. */
723 {
726 else
728 }
729 /* Fall back to generic for multi-reg and very large modes. */
730 else
732 }
734 /* Return true if calls to DECL should be treated as
735 long-calls (ie called via a register). */
736 static bool
738 {
740 }
742 /* Return true if calls to symbol-ref SYM should be treated as
743 long-calls (ie called via a register). */
744 bool
746 {
748 }
750 /* Return true if the offsets to a zero/sign-extract operation
751 represent an expression that matches an extend operation. The
752 operands represent the paramters from
754 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
755 bool
757 rtx extract_imm)
758 {
775 }
777 /* Emit an insn that's a simple single-set. Both the operands must be
778 known to be valid. */
781 {
783 }
785 /* X and Y are two things to compare using CODE. Emit the compare insn and
786 return the rtx for register 0 in the proper mode. */
787 rtx
789 {
795 }
797 /* Build the SYMBOL_REF for __tls_get_addr. */
801 rtx
803 {
807 }
809 /* Return the TLS model to use for ADDR. */
811 static enum tls_model
813 {
818 {
822 }
827 }
829 /* We'll allow lo_sum's in addresses in our legitimate addresses
830 so that combine would take care of combining addresses where
831 necessary, but for generation purposes, we'll generate the address
832 as :
833 RTL Absolute
834 tmp = hi (symbol_ref); adrp x1, foo
835 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
836 nop
838 PIC TLS
839 adrp x1, :got:foo adrp tmp, :tlsgd:foo
840 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
841 bl __tls_get_addr
842 nop
844 Load TLS symbol, depending on TLS mechanism and TLS access model.
846 Global Dynamic - Traditional TLS:
847 adrp tmp, :tlsgd:imm
848 add dest, tmp, #:tlsgd_lo12:imm
849 bl __tls_get_addr
851 Global Dynamic - TLS Descriptors:
852 adrp dest, :tlsdesc:imm
853 ldr tmp, [dest, #:tlsdesc_lo12:imm]
854 add dest, dest, #:tlsdesc_lo12:imm
855 blr tmp
856 mrs tp, tpidr_el0
857 add dest, dest, tp
859 Initial Exec:
860 mrs tp, tpidr_el0
861 adrp tmp, :gottprel:imm
862 ldr dest, [tmp, #:gottprel_lo12:imm]
863 add dest, dest, tp
865 Local Exec:
866 mrs tp, tpidr_el0
867 add t0, tp, #:tprel_hi12:imm, lsl #12
868 add t0, t0, #:tprel_lo12_nc:imm
869 */
871 static void
874 {
876 {
878 {
879 /* In ILP32, the mode of dest can be either SImode or DImode. */
891 }
898 {
902 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
903 here before rtl expand. Tree IVOPT will generate rtl pattern to
904 decide rtx costs, in which case pic_offset_table_rtx is not
905 initialized. For that case no need to generate the first adrp
906 instruction as the the final cost for global variable access is
907 one instruction. */
909 {
910 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
911 using the page base as GOT base, the first page may be wasted,
912 in the worst scenario, there is only 28K space for GOT).
914 The generate instruction sequence for accessing global variable
915 is:
917 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
919 Only one instruction needed. But we must initialize
920 pic_offset_table_rtx properly. We generate initialize insn for
921 every global access, and allow CSE to remove all redundant.
923 The final instruction sequences will look like the following
924 for multiply global variables access.
926 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
928 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
929 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
930 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
931 ... */
939 }
942 {
945 else
947 }
948 else
949 {
952 }
955 }
958 {
959 /* In ILP32, the mode of dest can be either SImode or DImode,
960 while the got entry is always of SImode size. The mode of
961 dest depends on how dest is used: if dest is assigned to a
962 pointer (e.g. in the memory), it has SImode; it may have
963 DImode if dest is dereferenced to access the memeory.
964 This is why we have to handle three different ldr_got_small
965 patterns here (two patterns for ILP32). */
974 {
977 else
979 }
980 else
981 {
984 }
987 }
990 {
1002 }
1005 {
1008 rtx tp;
1012 /* In ILP32, the got entry is always of SImode size. Unlike
1013 small GOT, the dest is fixed at reg 0. */
1016 else
1026 }
1029 {
1030 /* In ILP32, the mode of dest can be either SImode or DImode,
1031 while the got entry is always of SImode size. The mode of
1032 dest depends on how dest is used: if dest is assigned to a
1033 pointer (e.g. in the memory), it has SImode; it may have
1034 DImode if dest is dereferenced to access the memeory.
1035 This is why we have to handle three different tlsie_small
1036 patterns here (two patterns for ILP32). */
1042 {
1045 else
1046 {
1049 }
1050 }
1051 else
1052 {
1055 }
1060 }
1063 {
1072 }
1080 }
1081 }
1083 /* Emit a move from SRC to DEST. Assume that the move expanders can
1084 handle all moves if !can_create_pseudo_p (). The distinction is
1085 important because, unlike emit_move_insn, the move expanders know
1086 how to force Pmode objects into the constant pool even when the
1087 constant pool address is not itself legitimate. */
1088 static rtx
1090 {
1094 }
1096 /* Split a 128-bit move operation into two 64-bit move operations,
1097 taking care to handle partial overlap of register to register
1098 copies. Special cases are needed when moving between GP regs and
1099 FP regs. SRC can be a register, constant or memory; DST a register
1100 or memory. If either operand is memory it must not have any side
1101 effects. */
1102 void
1104 {
1115 {
1119 /* Handle FP <-> GP regs. */
1121 {
1126 {
1129 }
1130 else
1131 {
1134 }
1136 }
1138 {
1143 {
1146 }
1147 else
1148 {
1151 }
1153 }
1154 }
1161 /* At most one pairing may overlap. */
1163 {
1166 }
1167 else
1168 {
1171 }
1172 }
1174 bool
1176 {
1179 }
1181 /* Split a complex SIMD combine. */
1183 void
1185 {
1192 {
1196 {
1217 }
1221 }
1222 }
1224 /* Split a complex SIMD move. */
1226 void
1228 {
1235 {
1241 {
1262 }
1266 }
1267 }
1269 static rtx
1271 {
1274 else
1275 {
1278 }
1279 }
1282 static rtx
1284 {
1286 {
1287 rtx high;
1288 /* Load the full offset into a register. This
1289 might be improvable in the future. */
1295 }
1297 }
1299 static int
1301 machine_mode mode)
1302 {
1308 rtx subtarget;
1313 {
1316 num_insns++;
1318 }
1321 {
1322 /* We know we can't do this in 1 insn, and we must be able to do it
1323 in two; so don't mess around looking for sequences that don't buy
1324 us anything. */
1326 {
1330 }
1333 }
1335 /* Remaining cases are all for DImode. */
1346 {
1348 one_match++;
1349 else
1350 {
1354 zero_match++;
1355 }
1356 }
1359 {
1360 /* Set one of the quarters and then insert back into result. */
1363 {
1368 }
1371 }
1378 {
1382 {
1384 {
1389 }
1392 }
1394 {
1396 {
1402 }
1405 }
1407 {
1409 {
1415 }
1418 }
1420 {
1422 {
1427 }
1430 }
1431 }
1433 /* See if we can do it by arithmetically combining two
1434 immediates. */
1436 {
1442 {
1444 {
1450 }
1453 }
1456 {
1458 {
1460 {
1465 }
1468 }
1469 }
1470 }
1472 /* See if we can do it by logically combining two immediates. */
1474 {
1476 {
1481 {
1483 {
1489 }
1492 }
1493 }
1495 {
1500 {
1502 {
1508 }
1511 }
1512 }
1513 }
1516 {
1517 /* Set either first three quarters or all but the third. */
1522 num_insns ++;
1524 /* Now insert other two quarters. */
1527 {
1529 {
1533 num_insns ++;
1534 }
1535 }
1537 }
1539 simple_sequence:
1543 {
1545 {
1547 {
1550 num_insns ++;
1552 }
1553 else
1554 {
1558 num_insns ++;
1559 }
1560 }
1561 }
1564 }
1567 void
1569 {
1574 /* Check on what type of symbol it is. */
1578 {
1582 /* If we have (const (plus symbol offset)), separate out the offset
1583 before we start classifying the symbol. */
1588 {
1592 {
1598 }
1613 {
1619 }
1620 /* FALLTHRU */
1630 }
1631 }
1634 {
1637 else
1638 {
1642 }
1645 }
1648 }
1650 static bool
1652 tree exp ATTRIBUTE_UNUSED)
1653 {
1654 /* Currently, always true. */
1656 }
1658 /* Implement TARGET_PASS_BY_REFERENCE. */
1660 static bool
1662 machine_mode mode,
1663 const_tree type,
1665 {
1666 HOST_WIDE_INT size;
1667 machine_mode dummymode;
1670 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1674 /* Aggregates are passed by reference based on their size. */
1676 {
1678 }
1680 /* Variable sized arguments are always returned by reference. */
1684 /* Can this be a candidate to be passed in fp/simd register(s)? */
1687 NULL))
1690 /* Arguments which are variable sized or larger than 2 registers are
1691 passed by reference unless they are a homogenous floating point
1692 aggregate. */
1694 }
1696 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1697 static bool
1699 {
1700 machine_mode dummy_mode;
1703 /* Never happens in little-endian mode. */
1707 /* Only composite types smaller than or equal to 16 bytes can
1708 be potentially returned in registers. */
1714 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1715 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1716 is always passed/returned in the least significant bits of fp/simd
1717 register(s). */
1723 }
1725 /* Implement TARGET_FUNCTION_VALUE.
1726 Define how to find the value returned by a function. */
1728 static rtx
1731 {
1732 machine_mode mode;
1735 machine_mode ag_mode;
1742 {
1746 {
1749 }
1750 }
1754 {
1756 {
1759 }
1760 else
1761 {
1763 rtx par;
1767 {
1772 }
1774 }
1775 }
1776 else
1778 }
1780 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1781 Return true if REGNO is the number of a hard register in which the values
1782 of called function may come back. */
1784 static bool
1786 {
1787 /* Maximum of 16 bytes can be returned in the general registers. Examples
1788 of 16-byte return values are: 128-bit integers and 16-byte small
1789 structures (excluding homogeneous floating-point aggregates). */
1793 /* Up to four fp/simd registers can return a function value, e.g. a
1794 homogeneous floating-point aggregate having four members. */
1799 }
1801 /* Implement TARGET_RETURN_IN_MEMORY.
1803 If the type T of the result of a function is such that
1804 void func (T arg)
1805 would require that arg be passed as a value in a register (or set of
1806 registers) according to the parameter passing rules, then the result
1807 is returned in the same registers as would be used for such an
1808 argument. */
1810 static bool
1812 {
1813 HOST_WIDE_INT size;
1814 machine_mode ag_mode;
1820 /* Simple scalar types always returned in registers. */
1824 type,
1827 NULL))
1830 /* Types larger than 2 registers returned in memory. */
1833 }
1835 static bool
1838 {
1841 type,
1843 nregs,
1844 NULL);
1845 }
1847 /* Given MODE and TYPE of a function argument, return the alignment in
1848 bits. The idea is to suppress any stronger alignment requested by
1849 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1850 This is a helper function for local use only. */
1852 static unsigned int
1854 {
1858 {
1860 {
1863 else
1865 }
1866 else
1868 }
1869 else
1873 }
1875 /* Layout a function argument according to the AAPCS64 rules. The rule
1876 numbers refer to the rule numbers in the AAPCS64. */
1878 static void
1880 const_tree type,
1882 {
1886 HOST_WIDE_INT size;
1888 /* We need to do this once per argument. */
1894 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1895 size
1897 UNITS_PER_WORD);
1901 mode,
1902 type,
1905 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1906 The following code thus handles passing by SIMD/FP registers first. */
1910 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1911 and homogenous short-vector aggregates (HVA). */
1913 {
1918 {
1921 {
1924 }
1925 else
1926 {
1927 rtx par;
1931 {
1934 tmp = gen_rtx_EXPR_LIST
1938 }
1940 }
1942 }
1943 else
1944 {
1945 /* C.3 NSRN is set to 8. */
1948 }
1949 }
1954 /* C6 - C9. though the sign and zero extension semantics are
1955 handled elsewhere. This is the case where the argument fits
1956 entirely general registers. */
1958 {
1963 /* C.8 if the argument has an alignment of 16 then the NGRN is
1964 rounded up to the next even number. */
1966 {
1969 }
1970 /* NREGS can be 0 when e.g. an empty structure is to be passed.
1971 A reg is still generated for it, but the caller should be smart
1972 enough not to use it. */
1974 {
1976 }
1977 else
1978 {
1979 rtx par;
1984 {
1989 }
1991 }
1995 }
1997 /* C.11 */
2000 /* The argument is passed on stack; record the needed number of words for
2001 this argument and align the total size if necessary. */
2002 on_stack:
2008 }
2010 /* Implement TARGET_FUNCTION_ARG. */
2012 static rtx
2015 {
2024 }
2026 void
2028 const_tree fntype ATTRIBUTE_UNUSED,
2029 rtx libname ATTRIBUTE_UNUSED,
2030 const_tree fndecl ATTRIBUTE_UNUSED,
2032 {
2046 {
2053 }
2055 }
2057 static void
2059 machine_mode mode,
2060 const_tree type,
2062 {
2065 {
2075 }
2076 }
2078 bool
2080 {
2083 }
2085 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2086 PARM_BOUNDARY bits of alignment, but will be given anything up
2087 to STACK_BOUNDARY bits if the type requires it. This makes sure
2088 that both before and after the layout of each argument, the Next
2089 Stacked Argument Address (NSAA) will have a minimum alignment of
2090 8 bytes. */
2092 static unsigned int
2094 {
2102 }
2104 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2106 Return true if an argument passed on the stack should be padded upwards,
2107 i.e. if the least-significant byte of the stack slot has useful data.
2109 Small aggregate types are placed in the lowest memory address.
2111 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2113 bool
2115 {
2116 /* On little-endian targets, the least significant byte of every stack
2117 argument is passed at the lowest byte address of the stack slot. */
2121 /* Otherwise, integral, floating-point and pointer types are padded downward:
2122 the least significant byte of a stack argument is passed at the highest
2123 byte address of the stack slot. */
2130 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2132 }
2134 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2136 It specifies padding for the last (may also be the only)
2137 element of a block move between registers and memory. If
2138 assuming the block is in the memory, padding upward means that
2139 the last element is padded after its highest significant byte,
2140 while in downward padding, the last element is padded at the
2141 its least significant byte side.
2143 Small aggregates and small complex types are always padded
2144 upwards.
2146 We don't need to worry about homogeneous floating-point or
2147 short-vector aggregates; their move is not affected by the
2148 padding direction determined here. Regardless of endianness,
2149 each element of such an aggregate is put in the least
2150 significant bits of a fp/simd register.
2152 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2153 register has useful data, and return the opposite if the most
2154 significant byte does. */
2156 bool
2159 {
2161 /* Small composite types are always padded upward. */
2163 {
2168 }
2170 /* Otherwise, use the default padding. */
2172 }
2174 static machine_mode
2176 {
2178 }
2180 static bool
2182 {
2183 /* In aarch64_override_options_after_change
2184 flag_omit_leaf_frame_pointer turns off the frame pointer by
2185 default. Turn it back on now if we've not got a leaf
2186 function. */
2192 }
2194 /* Mark the registers that need to be saved by the callee and calculate
2195 the size of the callee-saved registers area and frame record (both FP
2196 and LR may be omitted). */
2197 static void
2199 {
2206 #define SLOT_NOT_REQUIRED (-2)
2207 #define SLOT_REQUIRED (-1)
2212 /* First mark all the registers that really need to be saved... */
2219 /* ... that includes the eh data registers (if needed)... */
2225 /* ... and any callee saved register that dataflow says is live. */
2238 {
2239 /* FP and LR are placed in the linkage record. */
2246 }
2248 /* Now assign stack slots for them. */
2251 {
2258 }
2262 {
2270 }
2290 }
2292 static bool
2294 {
2296 }
2298 static unsigned
2300 {
2302 regno ++;
2304 }
2306 static void
2308 HOST_WIDE_INT adjustment)
2309 {
2320 }
2322 static rtx
2324 HOST_WIDE_INT adjustment)
2325 {
2327 {
2338 }
2339 }
2341 static void
2344 {
2354 }
2356 static rtx
2358 HOST_WIDE_INT adjustment)
2359 {
2361 {
2370 }
2371 }
2373 static rtx
2375 rtx reg2)
2376 {
2378 {
2387 }
2388 }
2390 static rtx
2392 rtx mem2)
2393 {
2395 {
2404 }
2405 }
2408 static void
2411 {
2421 {
2423 HOST_WIDE_INT offset;
2433 offset));
2441 {
2443 rtx mem2;
2447 offset));
2449 reg2));
2451 /* The first part of a frame-related parallel insn is
2452 always assumed to be relevant to the frame
2453 calculations; subsequent parts, are only
2454 frame-related if explicitly marked. */
2457 }
2458 else
2462 }
2463 }
2465 static void
2469 {
2475 HOST_WIDE_INT offset;
2480 {
2497 {
2499 rtx mem2;
2507 }
2508 else
2511 }
2512 }
2514 /* AArch64 stack frames generated by this compiler look like:
2516 +-------------------------------+
2517 | |
2518 | incoming stack arguments |
2519 | |
2520 +-------------------------------+
2521 | | <-- incoming stack pointer (aligned)
2522 | callee-allocated save area |
2523 | for register varargs |
2524 | |
2525 +-------------------------------+
2526 | local variables | <-- frame_pointer_rtx
2527 | |
2528 +-------------------------------+
2529 | padding0 | \
2530 +-------------------------------+ |
2531 | callee-saved registers | | frame.saved_regs_size
2532 +-------------------------------+ |
2533 | LR' | |
2534 +-------------------------------+ |
2535 | FP' | / <- hard_frame_pointer_rtx (aligned)
2536 +-------------------------------+
2537 | dynamic allocation |
2538 +-------------------------------+
2539 | padding |
2540 +-------------------------------+
2541 | outgoing stack arguments | <-- arg_pointer
2542 | |
2543 +-------------------------------+
2544 | | <-- stack_pointer_rtx (aligned)
2546 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2547 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2548 unchanged. */
2550 /* Generate the prologue instructions for entry into a function.
2551 Establish the stack frame by decreasing the stack pointer with a
2552 properly calculated size and, if necessary, create a frame record
2553 filled with the values of LR and previous frame pointer. The
2554 current FP is also set up if it is in use. */
2556 void
2558 {
2559 /* sub sp, sp, #<frame_size>
2560 stp {fp, lr}, [sp, #<frame_size> - 16]
2561 add fp, sp, #<frame_size> - hardfp_offset
2562 stp {cs_reg}, [fp, #-16] etc.
2564 sub sp, sp, <final_adjustment_if_any>
2565 */
2568 HOST_WIDE_INT hard_fp_offset;
2580 /* Store pairs and load pairs have a range only -512 to 504. */
2582 {
2583 /* When the frame has a large size, an initial decrease is done on
2584 the stack pointer to jump over the callee-allocated save area for
2585 register varargs, the local variable area and/or the callee-saved
2586 register area. This will allow the pre-index write-back
2587 store pair instructions to be used for setting up the stack frame
2588 efficiently. */
2597 {
2607 }
2609 {
2614 {
2618 }
2620 {
2624 }
2625 }
2626 }
2627 else
2631 {
2635 {
2639 {
2646 }
2647 else
2650 /* Set up frame pointer to point to the location of the
2651 previous frame pointer on the stack. */
2653 stack_pointer_rtx,
2657 }
2658 else
2659 {
2667 {
2671 }
2672 else
2673 {
2680 else
2682 }
2683 }
2686 skip_wb);
2688 skip_wb);
2689 }
2691 /* when offset >= 512,
2692 sub sp, sp, #<outgoing_args_size> */
2694 {
2696 {
2701 }
2702 }
2703 }
2705 /* Return TRUE if we can use a simple_return insn.
2707 This function checks whether the callee saved stack is empty, which
2708 means no restore actions are need. The pro_and_epilogue will use
2709 this to check whether shrink-wrapping opt is feasible. */
2711 bool
2713 {
2723 }
2725 /* Generate the epilogue instructions for returning from a function. */
2726 void
2728 {
2730 HOST_WIDE_INT fp_offset;
2731 HOST_WIDE_INT hard_fp_offset;
2733 /* We need to add memory barrier to prevent read from deallocated stack. */
2743 /* Store pairs and load pairs have a range only -512 to 504. */
2745 {
2753 {
2758 }
2759 }
2760 else
2763 /* If there were outgoing arguments or we've done dynamic stack
2764 allocation, then restore the stack pointer from the frame
2765 pointer. This is at most one insn and more efficient than using
2766 GCC's internal mechanism. */
2769 {
2774 hard_frame_pointer_rtx,
2777 }
2780 {
2803 {
2809 {
2814 }
2815 else
2816 {
2823 }
2824 }
2825 else
2826 {
2829 }
2831 /* Reset the CFA to be SP + FRAME_SIZE. */
2838 }
2841 {
2846 {
2850 }
2851 else
2852 {
2857 {
2862 }
2865 }
2867 /* Reset the CFA to be SP + 0. */
2870 }
2872 /* Stack adjustment for exception handler. */
2874 {
2875 /* We need to unwind the stack by the offset computed by
2876 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
2877 to be SP; letting the CFA move during this adjustment
2878 is just as correct as retaining the CFA from the body
2879 of the function. Therefore, do nothing special. */
2881 }
2886 }
2888 /* Return the place to copy the exception unwinding return address to.
2889 This will probably be a stack slot, but could (in theory be the
2890 return register). */
2891 rtx
2893 {
2894 HOST_WIDE_INT fp_offset;
2904 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
2905 result in a store to save LR introduced by builtin_eh_return () being
2906 incorrectly deleted because the alias is not detected.
2907 So in the calculation of the address to copy the exception unwinding
2908 return address to, we note 2 cases.
2909 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
2910 we return a SP-relative location since all the addresses are SP-relative
2911 in this case. This prevents the store from being optimized away.
2912 If the fp_offset is not 0, then the addresses will be FP-relative and
2913 therefore we return a FP-relative location. */
2916 {
2920 else
2923 }
2925 /* If FP is not needed, we calculate the location of LR, which would be
2926 at the top of the saved registers block. */
2930 stack_pointer_rtx,
2931 fp_offset
2934 }
2936 /* Possibly output code to build up a constant in a register. For
2937 the benefit of the costs infrastructure, returns the number of
2938 instructions which would be emitted. GENERATE inhibits or
2939 enables code generation. */
2941 static int
2943 {
2947 {
2951 }
2952 else
2953 {
2958 HOST_WIDE_INT valm;
2959 HOST_WIDE_INT tval;
2962 {
2972 }
2974 /* zcount contains the number of additional MOVK instructions
2975 required if the constant is built up with an initial MOVZ instruction,
2976 while ncount is the number of MOVK instructions required if starting
2977 with a MOVN instruction. Choose the sequence that yields the fewest
2978 number of instructions, preferring MOVZ instructions when they are both
2979 the same. */
2981 {
2986 insns++;
2987 }
2988 else
2989 {
2994 insns++;
2995 }
3000 {
3002 {
3007 insns++;
3008 }
3010 }
3011 }
3013 }
3015 static void
3017 {
3026 {
3029 }
3031 {
3033 {
3039 else
3042 }
3044 {
3048 }
3049 }
3050 }
3052 /* Output code to add DELTA to the first argument, and then jump
3053 to FUNCTION. Used for C++ multiple inheritance. */
3054 static void
3056 HOST_WIDE_INT delta,
3057 HOST_WIDE_INT vcall_offset,
3058 tree function)
3059 {
3060 /* The this pointer is always in x0. Note that this differs from
3061 Arm where the this pointer maybe bumped to r1 if r0 is required
3062 to return a pointer to an aggregate. On AArch64 a result value
3063 pointer will be in x8. */
3073 else
3074 {
3083 {
3087 else
3089 }
3093 else
3100 else
3101 {
3104 }
3108 else
3114 }
3116 /* Generate a tail call to the target function. */
3118 {
3121 }
3133 /* Stop pretending to be a post-reload pass. */
3135 }
3137 static bool
3139 {
3144 {
3148 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3149 TLS offsets, not real symbol references. */
3152 }
3154 }
3157 static int
3159 {
3168 }
3171 static void
3173 {
3179 {
3183 else
3186 {
3188 {
3189 /* set s consecutive bits to 1 (s < 64) */
3191 /* rotate right by r */
3194 /* replicate the constant depending on SIMD size */
3205 }
3208 }
3209 }
3210 }
3214 aarch64_bitmasks_cmp);
3215 }
3218 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3219 a left shift of 0 or 12 bits. */
3220 bool
3222 {
3225 );
3226 }
3229 /* Return true if val is an immediate that can be loaded into a
3230 register by a MOVZ instruction. */
3231 static bool
3233 {
3235 {
3239 }
3240 else
3241 {
3242 /* Ignore sign extension. */
3244 }
3247 }
3250 /* Return true if val is a valid bitmask immediate. */
3251 bool
3253 {
3255 {
3256 /* Replicate bit pattern. */
3259 }
3262 }
3265 /* Return true if val is an immediate that can be loaded into a
3266 register in a single instruction. */
3267 bool
3269 {
3273 }
3275 static bool
3277 {
3285 {
3289 else
3290 /* Avoid generating a 64-bit relocation in ILP32; leave
3291 to aarch64_expand_mov_immediate to handle it properly. */
3293 }
3296 }
3298 /* Return true if register REGNO is a valid index register.
3299 STRICT_P is true if REG_OK_STRICT is in effect. */
3301 bool
3303 {
3305 {
3313 }
3315 }
3317 /* Return true if register REGNO is a valid base register for mode MODE.
3318 STRICT_P is true if REG_OK_STRICT is in effect. */
3320 bool
3322 {
3324 {
3332 }
3334 /* The fake registers will be eliminated to either the stack or
3335 hard frame pointer, both of which are usually valid base registers.
3336 Reload deals with the cases where the eliminated form isn't valid. */
3341 }
3343 /* Return true if X is a valid base register for mode MODE.
3344 STRICT_P is true if REG_OK_STRICT is in effect. */
3346 static bool
3348 {
3353 }
3355 /* Return true if address offset is a valid index. If it is, fill in INFO
3356 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3358 static bool
3361 {
3363 rtx index;
3366 /* (reg:P) */
3369 {
3373 }
3374 /* (sign_extend:DI (reg:SI)) */
3379 {
3384 }
3385 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3392 {
3397 }
3398 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3405 {
3410 }
3411 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3418 {
3426 }
3427 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3428 (const_int 0xffffffff<<shift)) */
3435 {
3441 }
3442 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3449 {
3457 }
3458 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3459 (const_int 0xffffffff<<shift)) */
3466 {
3472 }
3473 /* (mult:P (reg:P) (const_int scale)) */
3478 {
3482 }
3483 /* (ashift:P (reg:P) (const_int shift)) */
3488 {
3492 }
3493 else
3504 {
3509 }
3512 }
3514 bool
3516 {
3520 }
3524 HOST_WIDE_INT offset)
3525 {
3527 }
3531 {
3535 }
3537 /* Return true if X is a valid address for machine mode MODE. If it is,
3538 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3539 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3541 static bool
3545 {
3549 /* On BE, we use load/store pair for all large int mode load/stores. */
3551 || (BYTES_BIG_ENDIAN
3555 !load_store_pair_p
3559 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3560 REG addressing. */
3566 {
3584 {
3590 }
3595 {
3602 /* TImode and TFmode values are allowed in both pairs of X
3603 registers and individual Q registers. The available
3604 address modes are:
3605 X,X: 7-bit signed scaled offset
3606 Q: 9-bit signed offset
3607 We conservatively require an offset representable in either mode.
3608 */
3613 /* A 7bit offset check because OImode will emit a ldp/stp
3614 instruction (only big endian will get here).
3615 For ldp/stp instructions, the offset is scaled for the size of a
3616 single element of the pair. */
3620 /* Three 9/12 bit offsets checks because CImode will emit three
3621 ldr/str instructions (only big endian will get here). */
3628 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3629 instructions (only big endian will get here). */
3638 else
3641 }
3644 {
3645 /* Look for base + (scaled/extended) index register. */
3648 {
3651 }
3654 {
3657 }
3658 }
3679 {
3680 HOST_WIDE_INT offset;
3684 /* TImode and TFmode values are allowed in both pairs of X
3685 registers and individual Q registers. The available
3686 address modes are:
3687 X,X: 7-bit signed scaled offset
3688 Q: 9-bit signed offset
3689 We conservatively require an offset representable in either mode.
3690 */
3698 else
3700 }
3706 /* load literal: pc-relative constant pool entry. Only supported
3707 for SI mode or larger. */
3711 {
3718 }
3727 {
3733 {
3734 /* The symbol and offset must be aligned to the access size. */
3741 {
3745 }
3751 else
3760 }
3761 }
3766 }
3767 }
3769 bool
3771 {
3772 rtx offset;
3776 }
3778 /* Classify the base of symbolic expression X, given that X appears in
3779 context CONTEXT. */
3781 enum aarch64_symbol_type
3784 {
3785 rtx offset;
3789 }
3792 /* Return TRUE if X is a legitimate address for accessing memory in
3793 mode MODE. */
3794 static bool
3796 {
3800 }
3802 /* Return TRUE if X is a legitimate address for accessing memory in
3803 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
3804 pair operation. */
3805 bool
3808 {
3812 }
3814 /* Return TRUE if rtx X is immediate constant 0.0 */
3815 bool
3817 {
3818 REAL_VALUE_TYPE r;
3827 }
3829 /* Return the fixed registers used for condition codes. */
3831 static bool
3833 {
3837 }
3839 /* Emit call insn with PAT and do aarch64-specific handling. */
3841 void
3843 {
3849 }
3851 machine_mode
3853 {
3854 /* All floating point compares return CCFP if it is an equality
3855 comparison, and CCFPE otherwise. */
3857 {
3859 {
3880 }
3881 }
3890 /* A compare with a shifted operand. Because of canonicalization,
3891 the comparison will have to be swapped when we emit the assembly
3892 code. */
3900 /* Similarly for a negated operand, but we can only do this for
3901 equalities. */
3908 /* A compare of a mode narrower than SI mode against zero can be done
3909 by extending the value in the comparison. */
3912 /* Only use sign-extension if we really need it. */
3916 /* For everything else, return CCmode. */
3918 }
3920 static int
3923 int
3925 {
3932 }
3934 static int
3936 {
3939 {
3943 {
3957 }
4012 {
4024 }
4031 {
4043 }
4048 {
4054 }
4059 {
4063 }
4069 }
4078 }
4080 bool
4082 HOST_WIDE_INT minval,
4083 HOST_WIDE_INT maxval)
4084 {
4085 HOST_WIDE_INT firstval;
4102 }
4104 bool
4106 {
4108 }
4110 static unsigned
4112 {
4116 {
4117 count++;
4119 }
4122 }
4124 /* N Z C V. */
4125 #define AARCH64_CC_V 1
4126 #define AARCH64_CC_C (1 << 1)
4127 #define AARCH64_CC_Z (1 << 2)
4128 #define AARCH64_CC_N (1 << 3)
4130 /* N Z C V flags for ccmp. The first code is for AND op and the other
4131 is for IOR op. Indexed by AARCH64_COND_CODE. */
4133 {
4150 };
4152 int
4154 {
4156 {
4189 }
4190 }
4193 void
4195 {
4197 {
4198 /* An integer or symbol address without a preceding # sign. */
4201 {
4213 {
4216 }
4217 /* Fall through. */
4221 }
4225 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4226 {
4231 {
4234 }
4237 {
4250 }
4251 }
4255 {
4258 /* Print N such that 2^N == X. */
4260 {
4263 }
4266 }
4270 /* Print the number of non-zero bits in X (a const_int). */
4272 {
4275 }
4281 /* Print the higher numbered register of a pair (TImode) of regs. */
4283 {
4286 }
4292 {
4294 /* Print a condition (eq, ne, etc). */
4296 /* CONST_TRUE_RTX means always -- that's the default. */
4301 {
4304 }
4309 }
4313 {
4315 /* Print the inverse of a condition (eq <-> ne, etc). */
4317 /* CONST_TRUE_RTX means never -- that's the default. */
4319 {
4322 }
4325 {
4328 }
4333 }
4341 /* Print a scalar FP/SIMD register name. */
4343 {
4344 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4346 }
4354 /* Print the first FP/SIMD register name in a list. */
4356 {
4357 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4359 }
4364 /* Print a scalar FP/SIMD register name + 1. */
4366 {
4367 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4369 }
4374 /* Print bottom 16 bits of integer constant in hex. */
4376 {
4379 }
4385 /* Print a general register name or the zero register (32-bit or
4386 64-bit). */
4389 {
4392 }
4395 {
4398 }
4401 {
4404 }
4406 /* Fall through */
4409 /* Print a normal operand, if it's a general register, then we
4410 assume DImode. */
4412 {
4415 }
4418 {
4439 {
4442 HOST_WIDE_INT_MIN,
4443 HOST_WIDE_INT_MAX));
4445 }
4447 {
4449 }
4450 else
4455 /* CONST_DOUBLE can represent a double-width integer.
4456 In this case, the mode of x is VOIDmode. */
4460 {
4463 }
4465 {
4466 #define buf_size 20
4468 REAL_VALUE_TYPE r;
4475 #undef buf_size
4476 }
4482 }
4490 {
4517 }
4523 {
4550 }
4557 {
4563 }
4568 {
4570 /* Print nzcv. */
4573 {
4576 }
4581 }
4585 {
4587 /* Print nzcv. */
4590 {
4593 }
4598 }
4604 }
4605 }
4607 void
4609 {
4615 {
4619 else
4628 else
4637 else
4646 else
4653 {
4680 }
4691 }
4694 }
4696 bool
4698 {
4705 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4706 referencing instruction, but they are constant offsets, not
4707 symbols. */
4713 {
4715 {
4721 }
4724 }
4727 }
4729 /* Implement REGNO_REG_CLASS. */
4731 enum reg_class
4733 {
4748 }
4750 static rtx
4752 {
4753 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4754 where mask is selected by alignment and size of the offset.
4755 We try to pick as large a range for the offset as possible to
4756 maximize the chance of a CSE. However, for aligned addresses
4757 we limit the range to 4k so that structures with different sized
4758 elements are likely to use the same base. */
4761 {
4763 HOST_WIDE_INT base_offset;
4765 /* Does it look like we'll need a load/store-pair operation? */
4770 /* For offsets aren't a multiple of the access size, the limit is
4771 -256...255. */
4774 else
4783 NULL_RTX);
4786 }
4789 }
4791 /* Try a machine-dependent way of reloading an illegitimate address
4792 operand. If we find one, push the reload and return the new rtx. */
4794 rtx
4796 machine_mode mode,
4799 {
4802 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
4807 {
4814 }
4816 /* We must recognize output that we have already generated ourselves. */
4822 {
4827 }
4829 /* We wish to handle large displacements off a base register by splitting
4830 the addend across an add and the mem insn. This can cut the number of
4831 extra insns needed from 3 to 1. It is only useful for load/store of a
4832 single register with 12 bit offset field. */
4840 {
4844 HOST_WIDE_INT offs;
4845 rtx cst;
4848 /* In ILP32, xmode can be either DImode or SImode. */
4851 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
4852 BLKmode alignment. */
4858 /* Align misaligned offset by adjusting high part to compensate. */
4860 {
4862 {
4863 /* Align down. */
4866 }
4867 else
4868 {
4869 /* Align up. */
4874 }
4875 }
4877 /* Check for overflow. */
4885 /* Reload high part into base reg, leaving the low part
4886 in the mem instruction.
4887 Note that replacing this gen_rtx_PLUS with plus_constant is
4888 wrong in this case because we rely on the
4889 (plus (plus reg c1) c2) structure being preserved so that
4890 XEXP (*p, 0) in push_reload below uses the correct term. */
4899 }
4902 }
4905 static reg_class_t
4907 reg_class_t rclass,
4908 machine_mode mode,
4910 {
4911 /* Without the TARGET_SIMD instructions we cannot move a Q register
4912 to a Q register directly. We need a scratch. */
4916 {
4922 }
4924 /* A TFmode or TImode memory access should be handled via an FP_REGS
4925 because AArch64 has richer addressing modes for LDR/STR instructions
4926 than LDP/STP instructions. */
4935 }
4937 static bool
4939 {
4940 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
4941 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4944 {
4956 }
4957 else
4958 {
4959 /* If we decided that we didn't need a leaf frame pointer but then used
4960 LR in the function, then we'll want a frame pointer after all, so
4961 prevent this elimination to ensure a frame pointer is used. */
4963 && flag_omit_leaf_frame_pointer
4966 }
4969 }
4971 HOST_WIDE_INT
4973 {
4977 {
4984 }
4987 {
4991 }
4994 }
4996 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
4997 previous frame. */
4999 rtx
5001 {
5005 }
5008 static void
5010 {
5012 {
5015 }
5016 else
5017 {
5020 }
5025 }
5027 static void
5029 {
5033 /* Don't need to copy the trailing D-words, we fill those in below. */
5045 /* XXX We should really define a "clear_cache" pattern and use
5046 gen_clear_cache(). */
5051 ptr_mode);
5052 }
5054 static unsigned char
5056 {
5058 {
5065 return
5077 }
5079 }
5081 static reg_class_t
5083 {
5088 {
5094 }
5096 /* If it's an integer immediate that MOVI can't handle, then
5097 FP_REGS is not an option, so we return NO_REGS instead. */
5102 /* Register eliminiation can result in a request for
5103 SP+constant->FP_REGS. We cannot support such operations which
5104 use SP as source and an FP_REG as destination, so reject out
5105 right now. */
5107 {
5110 /* Look through a possible SUBREG introduced by ILP32. */
5116 POINTER_REGS));
5118 }
5121 }
5123 void
5125 {
5127 }
5129 static void
5131 {
5134 else
5135 {
5143 }
5144 }
5146 static void
5148 {
5151 else
5152 {
5160 }
5161 }
5165 {
5171 {
5172 {
5175 },
5176 {
5179 },
5180 {
5183 },
5184 /* We assume that DImode is only generated when not optimizing and
5185 that we don't really need 64-bit address offsets. That would
5186 imply an object file with 8GB of code in a single function! */
5187 {
5190 }
5191 };
5199 /* Need to implement table size reduction, by chaning the code below. */
5209 }
5212 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5213 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5214 operator. */
5216 int
5218 {
5220 {
5223 {
5227 }
5228 }
5230 }
5232 static bool
5234 const_rtx x ATTRIBUTE_UNUSED)
5235 {
5236 /* We can't use blocks for constants when we're using a per-function
5237 constant pool. */
5239 }
5243 rtx x ATTRIBUTE_UNUSED,
5245 {
5246 /* Force all constant pool entries into the current function section. */
5248 }
5251 /* Costs. */
5253 /* Helper function for rtx cost calculation. Strip a shift expression
5254 from X. Returns the inner operand if successful, or the original
5255 expression on failure. */
5256 static rtx
5258 {
5261 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5262 we can convert both to ROR during final output. */
5277 }
5279 /* Helper function for rtx cost calculation. Strip an extend
5280 expression from X. Returns the inner operand if successful, or the
5281 original expression on failure. We deal with a number of possible
5282 canonicalization variations here. */
5283 static rtx
5285 {
5288 /* Zero and sign extraction of a widened value. */
5296 /* It can also be represented (for zero-extend) as an AND with an
5297 immediate. */
5306 /* Now handle extended register, as this may also have an optional
5307 left shift by 1..4. */
5321 }
5323 /* Return true iff CODE is a shift supported in combination
5324 with arithmetic instructions. */
5326 static bool
5328 {
5330 }
5332 /* Helper function for rtx cost calculation. Calculate the cost of
5333 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5334 Return the calculated cost of the expression, recursing manually in to
5335 operands where needed. */
5337 static int
5339 {
5355 /* Integer multiply/fma. */
5357 {
5358 /* The multiply will be canonicalized as a shift, cost it as such. */
5362 {
5366 {
5368 {
5370 /* ARITH + shift-by-register. */
5373 /* ARITH + extended register. We don't have a cost field
5374 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5376 else
5377 /* ARITH + shift-by-immediate. */
5379 }
5380 else
5381 /* LSL (immediate). */
5384 }
5385 /* Strip extends as we will have costed them in the case above. */
5392 }
5394 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5395 compound and let the below cases handle it. After all, MNEG is a
5396 special-case alias of MSUB. */
5398 {
5401 }
5403 /* Integer multiplies or FMAs have zero/sign extending variants. */
5408 {
5413 {
5415 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5417 else
5418 /* MUL/SMULL/UMULL. */
5420 }
5423 }
5425 /* This is either an integer multiply or a MADD. In both cases
5426 we want to recurse and cost the operands. */
5431 {
5433 /* MADD/MSUB. */
5435 else
5436 /* MUL. */
5438 }
5441 }
5442 else
5443 {
5445 {
5446 /* Floating-point FMA/FMUL can also support negations of the
5447 operands. */
5454 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5456 else
5457 /* FMUL/FNMUL. */
5459 }
5464 }
5465 }
5467 static int
5469 machine_mode mode,
5470 addr_space_t as ATTRIBUTE_UNUSED,
5472 {
5480 {
5482 {
5483 /* This is a CONST or SYMBOL ref which will be split
5484 in a different way depending on the code model in use.
5485 Cost it through the generic infrastructure. */
5487 /* Divide through by the cost of one instruction to
5488 bring it to the same units as the address costs. */
5490 /* The cost is then the cost of preparing the address,
5491 followed by an immediate (possibly 0) offset. */
5493 }
5494 else
5495 {
5496 /* This is most likely a jump table from a case
5497 statement. */
5499 }
5500 }
5503 {
5515 else
5531 }
5535 {
5536 /* For the sake of calculating the cost of the shifted register
5537 component, we can treat same sized modes in the same way. */
5539 {
5552 /* We can't tell, or this is a 128-bit vector. */
5556 }
5557 }
5560 }
5562 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5563 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5564 to be taken. */
5566 int
5568 {
5569 /* When optimizing for speed, use the cost of unpredictable branches. */
5575 else
5577 }
5579 /* Return true if the RTX X in mode MODE is a zero or sign extract
5580 usable in an ADD or SUB (extended register) instruction. */
5581 static bool
5583 {
5584 /* Catch add with a sign extract.
5585 This is add_<optab><mode>_multp2. */
5588 {
5599 op1))
5600 {
5602 }
5603 }
5606 }
5608 static bool
5610 {
5612 {
5624 }
5625 }
5627 /* Return true iff X is an rtx that will match an extr instruction
5628 i.e. as described in the *extr<mode>5_insn family of patterns.
5629 OP0 and OP1 will be set to the operands of the shifts involved
5630 on success and will be NULL_RTX otherwise. */
5632 static bool
5634 {
5649 {
5650 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5662 {
5666 }
5667 }
5670 }
5672 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5673 storing it in *COST. Result is true if the total cost of the operation
5674 has now been calculated. */
5675 static bool
5677 {
5678 rtx inner;
5679 rtx comparator;
5683 {
5687 }
5688 else
5689 {
5693 }
5696 {
5697 /* Conditional branch. */
5700 else
5701 {
5703 {
5705 {
5706 /* TBZ/TBNZ/CBZ/CBNZ. */
5708 /* TBZ/TBNZ. */
5711 else
5712 /* CBZ/CBNZ. */
5716 }
5717 }
5719 {
5720 /* TBZ/TBNZ. */
5723 }
5724 }
5725 }
5727 {
5728 /* It's a conditional operation based on the status flags,
5729 so it must be some flavor of CSEL. */
5731 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5740 }
5742 /* We don't know what this is, cost all operands. */
5744 }
5746 /* Calculate the cost of calculating X, storing it in *COST. Result
5747 is true if the total cost of the operation has now been calculated. */
5748 static bool
5751 {
5757 /* By default, assume that everything has equivalent cost to the
5758 cheapest instruction. Any additional costs are applied as a delta
5759 above this default. */
5763 {
5765 /* The cost depends entirely on the operands to SET. */
5771 {
5774 {
5788 }
5797 /* Fall through. */
5799 /* The cost is one per vector-register copied. */
5801 {
5805 }
5806 /* const0_rtx is in general free, but we will use an
5807 instruction to set a register to 0. */
5809 {
5810 /* The cost is 1 per register copied. */
5814 }
5815 else
5816 /* Cost is just the cost of the RHS of the set. */
5822 /* Bit-field insertion. Strip any redundant widening of
5823 the RHS to meet the width of the target. */
5834 {
5835 /* MOV immediate is assumed to always be cheap. */
5837 }
5838 else
5839 {
5840 /* BFM. */
5844 }
5849 /* We can't make sense of this, assume default cost. */
5852 }
5856 /* If an instruction can incorporate a constant within the
5857 instruction, the instruction's expression avoids calling
5858 rtx_cost() on the constant. If rtx_cost() is called on a
5859 constant, then it is usually because the constant must be
5860 moved into a register by one or more instructions.
5862 The exception is constant 0, which can be expressed
5863 as XZR/WZR and is therefore free. The exception to this is
5864 if we have (set (reg) (const0_rtx)) in which case we must cost
5865 the move. However, we can catch that when we cost the SET, so
5866 we don't need to consider that here. */
5869 else
5870 {
5871 /* To an approximation, building any other constant is
5872 proportionally expensive to the number of instructions
5873 required to build that constant. This is true whether we
5874 are compiling for SPEED or otherwise. */
5877 }
5882 {
5883 /* mov[df,sf]_aarch64. */
5885 /* FMOV (scalar immediate). */
5888 {
5889 /* This will be a load from memory. */
5892 else
5894 }
5895 else
5896 /* Otherwise this is +0.0. We get this using MOVI d0, #0
5897 or MOV v0.s[0], wzr - neither of which are modeled by the
5898 cost tables. Just use the default cost. */
5899 {
5900 }
5901 }
5907 {
5908 /* For loads we want the base cost of a load, plus an
5909 approximation for the additional cost of the addressing
5910 mode. */
5924 }
5932 {
5934 {
5935 /* FNEG. */
5937 }
5939 }
5942 {
5945 {
5946 /* CSETM. */
5949 }
5951 /* Cost this as SUB wzr, X. */
5955 }
5958 {
5959 /* Support (neg(fma...)) as a single instruction only if
5960 sign of zeros is unimportant. This matches the decision
5961 making in aarch64.md. */
5963 {
5964 /* FNMADD. */
5967 }
5969 /* FNEG. */
5972 }
5979 {
5982 else
5984 }
5994 {
5997 }
6000 {
6001 /* TODO: A write to the CC flags possibly costs extra, this
6002 needs encoding in the cost tables. */
6004 /* CC_ZESWPmode supports zero extend for free. */
6008 /* ANDS. */
6010 {
6013 }
6016 {
6017 /* ADDS (and CMN alias). */
6020 }
6023 {
6024 /* SUBS. */
6027 }
6030 {
6031 /* CMN. */
6038 }
6040 /* CMP.
6042 Compare can freely swap the order of operands, and
6043 canonicalization puts the more complex operation first.
6044 But the integer MINUS logic expects the shift/extend
6045 operation in op1. */
6048 {
6051 }
6053 }
6056 {
6057 /* FCMP. */
6062 {
6064 /* FCMP supports constant 0.0 for no extra cost. */
6066 }
6068 }
6071 {
6072 /* Vector compare. */
6077 {
6078 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6079 cost. */
6081 }
6083 }
6087 {
6091 cost_minus:
6094 /* Detect valid immediates. */
6100 {
6102 /* SUB(S) (immediate). */
6105 }
6107 /* Look for SUB (extended register). */
6109 {
6117 }
6121 /* Cost this as an FMA-alike operation. */
6125 {
6128 speed);
6130 }
6135 {
6137 {
6138 /* Vector SUB. */
6140 }
6142 {
6143 /* SUB(S). */
6145 }
6147 {
6148 /* FSUB. */
6150 }
6151 }
6153 }
6156 {
6157 rtx new_op0;
6162 cost_plus:
6165 {
6166 /* CSINC. */
6170 }
6175 {
6179 /* ADD (immediate). */
6182 }
6186 /* Look for ADD (extended register). */
6188 {
6196 }
6198 /* Strip any extend, leave shifts behind as we will
6199 cost them through mult_cost. */
6204 {
6206 speed);
6208 }
6213 {
6215 {
6216 /* Vector ADD. */
6218 }
6220 {
6221 /* ADD. */
6223 }
6225 {
6226 /* FADD. */
6228 }
6229 }
6231 }
6237 {
6240 else
6242 }
6247 {
6251 {
6254 else
6256 }
6258 }
6261 {
6268 }
6269 /* Fall through. */
6272 cost_logic:
6277 {
6281 }
6289 {
6290 /* This is a UBFM/SBFM. */
6295 }
6298 {
6299 /* We possibly get the immediate for free, this is not
6300 modelled. */
6303 {
6310 }
6311 else
6312 {
6315 /* Handle ORN, EON, or BIC. */
6321 /* If we had a shift on op0 then this is a logical-shift-
6322 by-register/immediate operation. Otherwise, this is just
6323 a logical operation. */
6325 {
6327 {
6328 /* Shift by immediate. */
6331 else
6333 }
6334 else
6336 }
6338 /* In both cases we want to cost both operands. */
6343 }
6344 }
6352 {
6353 /* Vector NOT. */
6356 }
6358 /* MVN-shifted-reg. */
6360 {
6367 }
6368 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6369 Handle the second form here taking care that 'a' in the above can
6370 be a shift. */
6372 {
6381 {
6384 else
6386 }
6389 }
6390 /* MVN. */
6399 /* If a value is written in SI mode, then zero extended to DI
6400 mode, the operation will in general be free as a write to
6401 a 'w' register implicitly zeroes the upper bits of an 'x'
6402 register. However, if this is
6404 (set (reg) (zero_extend (reg)))
6406 we must cost the explicit register move. */
6410 {
6414 /* MOV. */
6416 else
6417 /* Free, the cost is that of the SI mode operation. */
6421 }
6423 {
6424 /* All loads can zero extend to any size for free. */
6427 }
6430 {
6432 {
6433 /* UMOV. */
6435 }
6436 else
6437 {
6438 /* UXTB/UXTH. */
6440 }
6441 }
6446 {
6447 /* LDRSH. */
6449 {
6456 }
6458 }
6461 {
6464 else
6466 }
6474 {
6476 {
6478 {
6479 /* Vector shift (immediate). */
6481 }
6482 else
6483 {
6484 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6485 aliases. */
6487 }
6488 }
6490 /* We can incorporate zero/sign extend for free. */
6497 }
6498 else
6499 {
6501 {
6503 {
6504 /* Vector shift (register). */
6506 }
6507 else
6508 {
6509 /* LSLV. */
6511 }
6512 }
6514 }
6524 {
6525 /* ASR (immediate) and friends. */
6527 {
6530 else
6532 }
6536 }
6537 else
6538 {
6540 /* ASR (register) and friends. */
6542 {
6545 else
6547 }
6549 }
6555 {
6556 /* LDR. */
6559 }
6562 {
6563 /* ADRP, followed by ADD. */
6567 }
6570 {
6571 /* ADR. */
6574 }
6577 {
6578 /* One extra load instruction, after accessing the GOT. */
6582 }
6587 /* ADRP/ADD (immediate). */
6594 /* UBFX/SBFX. */
6596 {
6599 else
6601 }
6603 /* We can trust that the immediates used will be correct (there
6604 are no by-register forms), so we need only cost op0. */
6610 /* aarch64_rtx_mult_cost always handles recursion to its
6611 operands. */
6617 {
6629 }
6636 {
6640 /* There is no integer SQRT, so only DIV and UDIV can get
6641 here. */
6643 else
6645 }
6671 {
6674 else
6676 }
6678 /* FMSUB, FNMADD, and FNMSUB are free. */
6685 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
6686 and the by-element operand as operand 0. */
6690 /* Catch vector-by-element operations. The by-element operand can
6691 either be (vec_duplicate (vec_select (x))) or just
6692 (vec_select (x)), depending on whether we are multiplying by
6693 a vector or a scalar.
6695 Canonicalization is not very good in these cases, FMA4 will put the
6696 by-element operand as operand 0, FNMA4 will have it as operand 1. */
6707 /* If the remaining parameters are not registers,
6708 get the cost to put them into registers. */
6722 {
6724 {
6725 /*Vector truncate. */
6727 }
6728 else
6730 }
6735 {
6737 {
6738 /*Vector conversion. */
6740 }
6741 else
6743 }
6749 /* Strip the rounding part. They will all be implemented
6750 by the fcvt* family of instructions anyway. */
6752 {
6761 }
6764 {
6767 else
6769 }
6775 {
6776 /* ABS (vector). */
6779 }
6781 {
6784 /* FABD, which is analogous to FADD. */
6786 {
6793 }
6794 /* Simple FABS is analogous to FNEG. */
6797 }
6798 else
6799 {
6800 /* Integer ABS will either be split to
6801 two arithmetic instructions, or will be an ABS
6802 (scalar), which we don't model. */
6806 }
6812 {
6815 else
6816 {
6817 /* FMAXNM/FMINNM/FMAX/FMIN.
6818 TODO: This may not be accurate for all implementations, but
6819 we do not model this in the cost tables. */
6821 }
6822 }
6826 /* The floating point round to integer frint* instructions. */
6828 {
6833 }
6836 {
6841 }
6846 /* Decompose <su>muldi3_highpart. */
6848 mode == DImode
6849 /* (lshiftrt:TI */
6852 /* (mult:TI */
6854 /* (ANY_EXTEND:TI (reg:DI))
6855 (ANY_EXTEND:TI (reg:DI))) */
6862 /* (const_int 64) */
6865 {
6866 /* UMULH/SMULH. */
6874 }
6876 /* Fall through. */
6879 }
6886 }
6888 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
6889 calculated for X. This cost is stored in *COST. Returns true
6890 if the total cost of X was calculated. */
6891 static bool
6894 {
6898 {
6903 }
6906 }
6908 static int
6911 {
6917 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
6924 /* Moving between GPR and stack cost is the same as GP2GP. */
6929 /* To/From the stack register, we move via the gprs. */
6935 {
6936 /* 128-bit operations on general registers require 2 instructions. */
6944 /* When AdvSIMD instructions are disabled it is not possible to move
6945 a 128-bit value directly between Q registers. This is handled in
6946 secondary reload. A general register is used as a scratch to move
6947 the upper DI value and the lower DI value is moved directly,
6948 hence the cost is the sum of three moves. */
6953 }
6963 }
6965 static int
6967 reg_class_t rclass ATTRIBUTE_UNUSED,
6969 {
6971 }
6973 /* Return the number of instructions that can be issued per cycle. */
6974 static int
6976 {
6978 }
6980 static int
6982 {
6986 }
6988 /* Vectorizer cost model target hooks. */
6990 /* Implement targetm.vectorize.builtin_vectorization_cost. */
6991 static int
6993 tree vectype,
6995 {
6999 {
7046 }
7047 }
7049 /* Implement targetm.vectorize.add_stmt_cost. */
7050 static unsigned
7054 {
7059 {
7064 /* Statements in an inner loop relative to the loop being
7065 vectorized are weighted more heavily. The value here is
7066 a function (linear for now) of the loop nest level. */
7068 {
7074 }
7078 }
7081 }
7085 /* Parse the architecture extension string. */
7087 static void
7089 {
7090 /* The extension string is parsed left to right. */
7093 /* Flag to say whether we are adding or removing an extension. */
7097 {
7101 str++;
7106 else
7110 {
7114 }
7119 {
7123 }
7125 /* Scan over the extensions table trying to find an exact match. */
7127 {
7129 {
7130 /* Add or remove the extension. */
7133 else
7136 }
7137 }
7140 {
7141 /* Extension not found in list. */
7144 }
7147 };
7150 }
7152 /* Parse the ARCH string. */
7154 static void
7156 {
7168 else
7172 {
7175 }
7177 /* Loop through the list of supported ARCHs to find a match. */
7179 {
7181 {
7189 {
7190 /* ARCH string contains at least one extension. */
7192 }
7195 {
7198 }
7201 }
7202 }
7204 /* ARCH name not found in list. */
7207 }
7209 /* Parse the CPU string. */
7211 static void
7213 {
7225 else
7229 {
7232 }
7234 /* Loop through the list of supported CPUs to find a match. */
7236 {
7238 {
7243 {
7244 /* CPU string contains at least one extension. */
7246 }
7249 }
7250 }
7252 /* CPU name not found in list. */
7255 }
7257 /* Parse the TUNE string. */
7259 static void
7261 {
7266 /* Loop through the list of supported CPUs to find a match. */
7268 {
7270 {
7273 }
7274 }
7276 /* CPU name not found in list. */
7279 }
7281 /* Parse TOKEN, which has length LENGTH to see if it is an option
7282 described in FLAG. If it is, return the index bit for that fusion type.
7283 If not, error (printing OPTION_NAME) and return zero. */
7285 static unsigned int
7290 {
7292 {
7296 }
7300 }
7302 /* Parse OPTION which is a comma-separated list of flags to enable.
7303 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7304 default state we inherit from the CPU tuning structures. OPTION_NAME
7305 gives the top-level option we are parsing in the -moverride string,
7306 for use in error messages. */
7308 static unsigned int
7313 {
7320 {
7323 token_length,
7324 flags,
7325 option_name);
7326 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7327 in the token stream, reset the supported operations. So:
7329 adrp+add.cmp+branch.none.adrp+add
7331 would have the result of turning on only adrp+add fusion. */
7337 }
7339 /* We ended with a comma, print something. */
7341 {
7344 }
7346 /* We still have one more token to parse. */
7349 token_length,
7350 flags,
7351 option_name);
7357 }
7359 /* Support for overriding instruction fusion. */
7361 static void
7364 {
7366 aarch64_fusible_pairs,
7369 }
7371 /* Support for overriding other tuning flags. */
7373 static void
7376 {
7377 tune->extra_tuning_flags
7379 aarch64_tuning_flags,
7382 }
7384 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
7385 we understand. If it is, extract the option string and handoff to
7386 the appropriate function. */
7388 void
7392 {
7398 {
7401 }
7403 /* Get the length of the option name. */
7405 /* Skip the '=' to get to the option string. */
7406 option_part++;
7409 {
7411 {
7414 }
7415 }
7419 }
7421 /* Parse STRING looking for options in the format:
7422 string :: option:string
7423 option :: name=substring
7424 name :: {a-z}
7425 substring :: defined by option. */
7427 static void
7430 {
7441 {
7443 /* Make this substring look like a string. */
7447 }
7449 /* One last option to parse. */
7452 }
7454 /* Implement TARGET_OPTION_OVERRIDE. */
7456 static void
7458 {
7459 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
7460 If either of -march or -mtune is given, they override their
7461 respective component of -mcpu.
7463 So, first parse AARCH64_CPU_STRING, then the others, be careful
7464 with -march as, if -mcpu is not present on the command line, march
7465 must set a sensible default CPU. */
7467 {
7469 }
7472 {
7474 }
7477 {
7479 }
7481 #ifndef HAVE_AS_MABI_OPTION
7482 /* The compiler may have been configured with 2.23.* binutils, which does
7483 not have support for ILP32. */
7486 #endif
7492 /* This target defaults to strict volatile bitfields. */
7496 /* If the user did not specify a processor, choose the default
7497 one for them. This will be the CPU set during configuration using
7498 --with-cpu, otherwise it is "generic". */
7500 {
7503 }
7512 /* Make a copy of the tuning parameters attached to the core, which
7513 we may later overwrite. */
7522 {
7523 #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
7525 #else
7527 #endif
7528 }
7533 }
7535 /* Implement targetm.override_options_after_change. */
7537 static void
7539 {
7545 /* If not optimizing for size, set the default
7546 alignment to what the target wants */
7548 {
7555 }
7556 }
7560 {
7564 }
7566 void
7568 {
7570 }
7572 /* A checking mechanism for the implementation of the various code models. */
7573 static void
7575 {
7577 {
7579 {
7584 #ifdef HAVE_AS_SMALL_PIC_RELOCS
7586 ? AARCH64_CMODEL_SMALL_PIC
7588 #else
7590 #endif
7597 }
7598 }
7599 else
7601 }
7603 /* Return true if SYMBOL_REF X binds locally. */
7605 static bool
7607 {
7611 }
7613 /* Return true if SYMBOL_REF X is thread local */
7614 static bool
7616 {
7624 }
7626 /* Classify a TLS symbol into one of the TLS kinds. */
7627 enum aarch64_symbol_type
7629 {
7633 {
7650 }
7651 }
7653 /* Return the method that should be used to access SYMBOL_REF or
7654 LABEL_REF X in context CONTEXT. */
7656 enum aarch64_symbol_type
7659 {
7661 {
7663 {
7678 }
7679 }
7682 {
7690 {
7692 /* When we retreive symbol + offset address, we have to make sure
7693 the offset does not cause overflow of the final address. But
7694 we have no way of knowing the address of symbol at compile time
7695 so we can't accurately say if the distance between the PC and
7696 symbol + offset is outside the addressible range of +/-1M in the
7697 TINY code model. So we rely on images not being greater than
7698 1M and cap the offset at 1M and anything beyond 1M will have to
7699 be loaded using an alternative mechanism. */
7706 /* Same reasoning as the tiny code model, but the offset cap here is
7707 4G. */
7728 }
7729 }
7731 /* By default push everything into the constant pool. */
7733 }
7735 bool
7737 {
7739 }
7741 bool
7743 {
7751 }
7753 /* Return true if X holds either a quarter-precision or
7754 floating-point +0.0 constant. */
7755 static bool
7757 {
7764 /* We only handle moving 0.0 to a TFmode register. */
7769 }
7771 static bool
7773 {
7774 /* Do not allow vector struct mode constants. We could support
7775 0 and -1 easily, but they need support in aarch64-simd.md. */
7779 /* This could probably go away because
7780 we now decompose CONST_INTs according to expand_mov_immediate. */
7791 }
7793 rtx
7795 {
7801 /* Can return in any reg. */
7804 }
7806 /* On AAPCS systems, this is the "struct __va_list". */
7809 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
7810 Return the type to use as __builtin_va_list.
7812 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
7814 struct __va_list
7815 {
7816 void *__stack;
7817 void *__gr_top;
7818 void *__vr_top;
7819 int __gr_offs;
7820 int __vr_offs;
7821 }; */
7823 static tree
7825 {
7826 tree va_list_name;
7829 /* Create the type. */
7831 /* Give it the required name. */
7833 TYPE_DECL,
7835 va_list_type);
7840 /* Create the fields. */
7843 ptr_type_node);
7846 ptr_type_node);
7849 ptr_type_node);
7852 integer_type_node);
7855 integer_type_node);
7875 /* Compute its layout. */
7879 }
7881 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
7882 static void
7884 {
7888 tree t;
7894 gr_save_area_size
7896 vr_save_area_size
7900 {
7903 }
7912 NULL_TREE);
7914 NULL_TREE);
7916 NULL_TREE);
7918 NULL_TREE);
7920 NULL_TREE);
7922 /* Emit code to initialize STACK, which points to the next varargs stack
7923 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
7924 by named arguments. STACK is 8-byte aligned. */
7931 /* Emit code to initialize GRTOP, the top of the GR save area.
7932 virtual_incoming_args_rtx should have been 16 byte aligned. */
7937 /* Emit code to initialize VRTOP, the top of the VR save area.
7938 This address is gr_save_area_bytes below GRTOP, rounded
7939 down to the next 16-byte boundary. */
7949 /* Emit code to initialize GROFF, the offset from GRTOP of the
7950 next GPR argument. */
7955 /* Likewise emit code to initialize VROFF, the offset from FTOP
7956 of the next VR argument. */
7960 }
7962 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
7964 static tree
7967 {
7968 tree addr;
7974 machine_mode mode;
8001 type,
8005 {
8006 /* TYPE passed in fp/simd registers. */
8018 {
8021 }
8024 {
8026 }
8027 }
8028 else
8029 {
8030 /* TYPE passed in general registers. */
8043 {
8045 }
8046 }
8048 /* Get a local temporary for the field value. */
8051 /* Emit code to branch if off >= 0. */
8057 {
8058 /* Emit: offs = (offs + 15) & -16. */
8064 }
8065 else
8068 /* Update ap.__[g|v]r_offs */
8073 /* String up. */
8077 /* [cond2] if (ap.__[g|v]r_offs > 0) */
8082 /* String up: make sure the assignment happens before the use. */
8086 /* Prepare the trees handling the argument that is passed on the stack;
8087 the top level node will store in ON_STACK. */
8090 {
8091 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
8099 }
8100 else
8102 /* Advance ap.__stack */
8110 /* String up roundup and advance. */
8113 /* String up with arg */
8115 /* Big-endianness related address adjustment. */
8118 {
8122 }
8127 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
8137 {
8138 /* type ha; // treat as "struct {ftype field[n];}"
8139 ... [computing offs]
8140 for (i = 0; i <nregs; ++i, offs += 16)
8141 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
8142 return ha; */
8146 /* Declare a local variable. */
8150 /* Establish the base type. */
8152 {
8165 /* The half precision and quad precision are not fully supported yet. Enable
8166 the following code after the support is complete. Need to find the correct
8167 type node for __fp16 *. */
8168 #if 0
8173 #endif
8176 {
8180 }
8184 }
8186 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
8194 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
8196 {
8206 }
8210 }
8220 }
8222 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
8224 static void
8228 {
8230 CUMULATIVE_ARGS local_cum;
8233 /* The caller has advanced CUM up to, but not beyond, the last named
8234 argument. Advance a local copy of CUM past the last "real" named
8235 argument, to find out how many registers are left over. */
8239 /* Found out how many registers we need to save. */
8244 {
8247 }
8250 {
8252 {
8255 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
8263 }
8265 {
8266 /* We can't use move_block_from_reg, because it will use
8267 the wrong mode, storing D regs only. */
8271 /* Set OFF to the offset from virtual_incoming_args_rtx of
8272 the first vector register. The VR save area lies below
8273 the GR one, and is aligned to 16 bytes. */
8279 {
8287 }
8288 }
8289 }
8291 /* We don't save the size into *PRETEND_SIZE because we want to avoid
8292 any complication of having crtl->args.pretend_args_size changed. */
8297 }
8299 static void
8301 {
8304 {
8306 {
8309 }
8310 }
8311 }
8313 /* Walk down the type tree of TYPE counting consecutive base elements.
8314 If *MODEP is VOIDmode, then set it to the first valid floating point
8315 type. If a non-floating point type is found, or if a floating point
8316 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
8317 otherwise return the count in the sub-tree. */
8318 static int
8320 {
8321 machine_mode mode;
8322 HOST_WIDE_INT size;
8325 {
8353 /* Use V2SImode and V4SImode as representatives of all 64-bit
8354 and 128-bit vector types. */
8357 {
8366 }
8371 /* Vector modes are considered to be opaque: two vectors are
8372 equivalent for the purposes of being homogeneous aggregates
8373 if they are the same size. */
8380 {
8384 /* Can't handle incomplete types nor sizes that are not
8385 fixed. */
8392 || !index
8403 /* There must be no padding. */
8408 }
8411 {
8414 tree field;
8416 /* Can't handle incomplete types nor sizes that are not
8417 fixed. */
8423 {
8431 }
8433 /* There must be no padding. */
8438 }
8442 {
8443 /* These aren't very interesting except in a degenerate case. */
8446 tree field;
8448 /* Can't handle incomplete types nor sizes that are not
8449 fixed. */
8455 {
8463 }
8465 /* There must be no padding. */
8470 }
8474 }
8477 }
8479 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
8480 type as described in AAPCS64 \S 4.1.2.
8482 See the comment above aarch64_composite_type_p for the notes on MODE. */
8484 static bool
8486 machine_mode mode)
8487 {
8497 }
8499 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
8500 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
8501 array types. The C99 floating-point complex types are also considered
8502 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
8503 types, which are GCC extensions and out of the scope of AAPCS64, are
8504 treated as composite types here as well.
8506 Note that MODE itself is not sufficient in determining whether a type
8507 is such a composite type or not. This is because
8508 stor-layout.c:compute_record_mode may have already changed the MODE
8509 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
8510 structure with only one field may have its MODE set to the mode of the
8511 field. Also an integer mode whose size matches the size of the
8512 RECORD_TYPE type may be used to substitute the original mode
8513 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
8514 solely relied on. */
8516 static bool
8518 machine_mode mode)
8519 {
8532 }
8534 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
8535 shall be passed or returned in simd/fp register(s) (providing these
8536 parameter passing registers are available).
8538 Upon successful return, *COUNT returns the number of needed registers,
8539 *BASE_MODE returns the mode of the individual register and when IS_HAF
8540 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
8541 floating-point aggregate or a homogeneous short-vector aggregate. */
8543 static bool
8545 const_tree type,
8549 {
8557 {
8560 }
8562 {
8566 }
8568 {
8572 {
8575 }
8576 else
8578 }
8579 else
8584 }
8586 /* Implement TARGET_STRUCT_VALUE_RTX. */
8588 static rtx
8591 {
8593 }
8595 /* Implements target hook vector_mode_supported_p. */
8596 static bool
8598 {
8609 }
8611 /* Return appropriate SIMD container
8612 for MODE within a vector of WIDTH bits. */
8613 static machine_mode
8615 {
8618 {
8621 {
8636 }
8637 else
8639 {
8650 }
8651 }
8653 }
8655 /* Return 128-bit container as the preferred SIMD mode for MODE. */
8656 static machine_mode
8658 {
8660 }
8662 /* Return the bitmask of possible vector sizes for the vectorizer
8663 to iterate over. */
8664 static unsigned int
8666 {
8668 }
8670 /* Implement TARGET_MANGLE_TYPE. */
8674 {
8675 /* The AArch64 ABI documents say that "__va_list" has to be
8676 managled as if it is in the "std" namespace. */
8680 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
8681 builtin types. */
8685 /* Use the default mangling. */
8687 }
8690 /* Return true if the rtx_insn contains a MEM RTX somewhere
8691 in it. */
8693 static bool
8695 {
8702 }
8704 /* Find the first rtx_insn before insn that will generate an assembly
8705 instruction. */
8709 {
8713 do
8714 {
8716 }
8720 }
8722 static bool
8724 {
8726 /* A number of these may be AArch32 only. */
8731 };
8734 {
8737 }
8740 }
8742 /* Check if there is a register dependency between a load and the insn
8743 for which we hold recog_data. */
8745 static bool
8747 {
8748 rtx load_reg;
8758 {
8764 }
8766 }
8769 /* When working around the Cortex-A53 erratum 835769,
8770 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
8771 instruction and has a preceding memory instruction such that a NOP
8772 should be inserted between them. */
8774 bool
8776 {
8779 rtx body;
8792 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
8793 Restore recog state to INSN to avoid state corruption. */
8801 /* If the previous insn is a memory op and there is no dependency between
8802 it and the DImode madd, emit a NOP between them. If body is NULL then we
8803 have a complex memory operation, probably a load/store pair.
8804 Be conservative for now and emit a NOP. */
8811 }
8814 /* Implement FINAL_PRESCAN_INSN. */
8816 void
8818 {
8821 }
8824 /* Return the equivalent letter for size. */
8825 static char
8827 {
8829 {
8835 }
8836 }
8838 /* Return true iff x is a uniform vector of floating-point
8839 constants, and the constant can be represented in
8840 quarter-precision form. Note, as aarch64_float_const_representable
8841 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
8842 static bool
8844 {
8859 {
8867 }
8870 }
8872 /* Return true for valid and false for invalid. */
8873 bool
8876 {
8877 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
8878 matches = 1; \
8879 for (i = 0; i < idx; i += (STRIDE)) \
8880 if (!(TEST)) \
8881 matches = 0; \
8882 if (matches) \
8883 { \
8884 immtype = (CLASS); \
8885 elsize = (ELSIZE); \
8886 eshift = (SHIFT); \
8887 emvn = (NEG); \
8888 break; \
8889 }
8899 {
8905 {
8910 }
8913 }
8915 /* Splat vector constant out into a byte vector. */
8917 {
8918 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
8919 it must be laid out in the vector register in reverse order. */
8925 {
8928 }
8930 {
8933 }
8934 else
8938 {
8941 {
8944 }
8947 }
8948 }
8950 /* Sanity check. */
8953 do
8954 {
9003 }
9010 {
9020 /* Un-invert bytes of recognized vector, if necessary. */
9026 {
9027 /* FIXME: Broken on 32-bit H_W_I hosts. */
9036 }
9037 else
9038 {
9042 /* Construct 'abcdefgh' because the assembler cannot handle
9043 generic constants. */
9048 }
9049 }
9052 #undef CHECK
9053 }
9055 /* Check of immediate shift constants are within range. */
9056 bool
9058 {
9062 else
9064 }
9066 /* Return true if X is a uniform vector where all elements
9067 are either the floating-point constant 0.0 or the
9068 integer constant 0. */
9069 bool
9071 {
9073 }
9075 bool
9077 {
9082 {
9087 }
9090 }
9092 bool
9095 machine_mode mode)
9096 {
9109 }
9111 /* Return a const_int vector of VAL. */
9112 rtx
9114 {
9123 }
9125 /* Check OP is a legal scalar immediate for the MOVI instruction. */
9127 bool
9129 {
9130 machine_mode vmode;
9136 }
9138 /* Construct and return a PARALLEL RTX vector with elements numbering the
9139 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
9140 the vector - from the perspective of the architecture. This does not
9141 line up with GCC's perspective on lane numbers, so we end up with
9142 different masks depending on our target endian-ness. The diagram
9143 below may help. We must draw the distinction when building masks
9144 which select one half of the vector. An instruction selecting
9145 architectural low-lanes for a big-endian target, must be described using
9146 a mask selecting GCC high-lanes.
9148 Big-Endian Little-Endian
9150 GCC 0 1 2 3 3 2 1 0
9151 | x | x | x | x | | x | x | x | x |
9152 Architecture 3 2 1 0 3 2 1 0
9154 Low Mask: { 2, 3 } { 0, 1 }
9155 High Mask: { 0, 1 } { 2, 3 }
9156 */
9158 rtx
9160 {
9166 rtx t1;
9171 else
9179 }
9181 /* Check OP for validity as a PARALLEL RTX vector with elements
9182 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
9183 from the perspective of the architecture. See the diagram above
9184 aarch64_simd_vect_par_cnst_half for more details. */
9186 bool
9189 {
9202 {
9209 }
9211 }
9213 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
9214 HIGH (exclusive). */
9215 void
9217 const_tree exp)
9218 {
9219 HOST_WIDE_INT lane;
9224 {
9227 else
9229 }
9230 }
9232 /* Return TRUE if OP is a valid vector addressing mode. */
9233 bool
9235 {
9238 }
9240 /* Emit a register copy from operand to operand, taking care not to
9241 early-clobber source registers in the process.
9243 COUNT is the number of components into which the copy needs to be
9244 decomposed. */
9245 void
9248 {
9258 else
9262 }
9264 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
9265 one of VSTRUCT modes: OI, CI or XI. */
9266 int
9268 {
9269 machine_mode mode;
9274 {
9277 {
9286 }
9287 }
9289 }
9291 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
9292 one of VSTRUCT modes: OI, CI, EI, or XI. */
9293 int
9295 {
9297 }
9299 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
9300 alignment of a vector to 128 bits. */
9301 static HOST_WIDE_INT
9303 {
9306 }
9308 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
9309 static bool
9311 {
9315 /* We guarantee alignment for vectors up to 128-bits. */
9320 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
9322 }
9324 /* If VALS is a vector constant that can be loaded into a register
9325 using DUP, generate instructions to do so and return an RTX to
9326 assign to the register. Otherwise return NULL_RTX. */
9327 static rtx
9329 {
9334 rtx x;
9341 {
9345 }
9350 /* We can load this constant by using DUP and a constant in a
9351 single ARM register. This will be cheaper than a vector
9352 load. */
9355 }
9358 /* Generate code to load VALS, which is a PARALLEL containing only
9359 constants (for vec_init) or CONST_VECTOR, efficiently into a
9360 register. Returns an RTX to copy into the register, or NULL_RTX
9361 for a PARALLEL that can not be converted into a CONST_VECTOR. */
9362 static rtx
9364 {
9366 rtx const_dup;
9375 {
9376 /* A CONST_VECTOR must contain only CONST_INTs and
9377 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
9378 Only store valid constants in a CONST_VECTOR. */
9380 {
9383 n_const++;
9384 }
9387 }
9388 else
9393 /* Load using MOVI/MVNI. */
9396 /* Loaded using DUP. */
9399 /* Load from constant pool. We can not take advantage of single-cycle
9400 LD1 because we need a PC-relative addressing mode. */
9402 else
9403 /* A PARALLEL containing something not valid inside CONST_VECTOR.
9404 We can not construct an initializer. */
9406 }
9408 void
9410 {
9419 {
9423 else
9428 }
9431 {
9434 {
9437 }
9438 }
9440 /* Splat a single non-constant element if we can. */
9442 {
9446 }
9448 /* Half the fields (or less) are non-constant. Load constant then overwrite
9449 varying fields. Hope that this is more efficient than using the stack. */
9451 {
9454 /* Load constant part of vector. We really don't care what goes into the
9455 parts we will overwrite, but we're more likely to be able to load the
9456 constant efficiently if it has fewer, larger, repeating parts
9457 (see aarch64_simd_valid_immediate). */
9459 {
9465 {
9466 /* Look in the copied vector, as more elements are const. */
9469 {
9472 }
9473 }
9475 }
9478 /* Insert variables. */
9483 {
9489 }
9491 }
9493 /* Construct the vector in memory one field at a time
9494 and load the whole vector. */
9502 }
9504 static unsigned HOST_WIDE_INT
9506 {
9507 return
9510 }
9512 #ifndef TLS_SECTION_ASM_FLAG
9514 #endif
9516 void
9518 tree decl ATTRIBUTE_UNUSED)
9519 {
9522 /* If we have already declared this section, we can use an
9523 abbreviated form to switch back to it -- unless this section is
9524 part of a COMDAT groups, in which case GAS requires the full
9525 declaration every time. */
9528 {
9531 }
9554 {
9560 else
9563 #ifdef TYPE_OPERAND_FMT
9565 #else
9567 #endif
9574 {
9577 else
9580 }
9581 }
9584 }
9586 /* Select a format to encode pointers in exception handling data. */
9587 int
9589 {
9592 {
9598 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
9599 for everything. */
9603 /* No assumptions here. 8-byte relocs required. */
9606 }
9608 }
9610 /* Emit load exclusive. */
9612 static void
9615 {
9619 {
9626 }
9629 }
9631 /* Emit store exclusive. */
9633 static void
9636 {
9640 {
9647 }
9650 }
9652 /* Mark the previous jump instruction as unlikely. */
9654 static void
9656 {
9661 }
9663 /* Expand a compare and swap pattern. */
9665 void
9667 {
9683 /* Normally the succ memory model must be stronger than fail, but in the
9684 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
9685 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
9692 {
9695 /* For short modes, we're going to perform the comparison in SImode,
9696 so do the zero-extension now. */
9700 /* Fall through. */
9704 /* Force the value into a register if needed. */
9711 }
9714 {
9721 }
9731 }
9733 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
9734 sequence implementing an atomic operation. */
9736 static void
9738 {
9745 {
9747 }
9748 }
9750 /* Split a compare and swap pattern. */
9752 void
9754 {
9756 machine_mode mode;
9761 rtx model_rtx;
9775 {
9778 }
9781 /* The initial load can be relaxed for a __sync operation since a final
9782 barrier will be emitted to stop code hoisting. */
9786 else
9798 {
9803 }
9804 else
9805 {
9809 }
9813 /* Emit any final barrier needed for a __sync operation. */
9816 }
9818 /* Split an atomic operation. */
9820 void
9823 {
9829 rtx x;
9838 else
9842 /* The initial load can be relaxed for a __sync operation since a final
9843 barrier will be emitted to stop code hoisting. */
9847 else
9851 {
9865 {
9868 }
9869 /* Fall through. */
9875 }
9885 /* Emit any final barrier needed for a __sync operation. */
9888 }
9890 static void
9892 {
9900 }
9902 static void
9904 {
9906 {
9909 }
9911 {
9916 }
9918 }
9920 /* Target hook for c_mode_for_suffix. */
9921 static machine_mode
9923 {
9928 }
9930 /* We can only represent floating point constants which will fit in
9931 "quarter-precision" values. These values are characterised by
9932 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
9933 by:
9935 (-1)^s * (n/16) * 2^r
9937 Where:
9938 's' is the sign bit.
9939 'n' is an integer in the range 16 <= n <= 31.
9940 'r' is an integer in the range -3 <= r <= 4. */
9942 /* Return true iff X can be represented by a quarter-precision
9943 floating point immediate operand X. Note, we cannot represent 0.0. */
9944 bool
9946 {
9947 /* This represents our current view of how many bits
9948 make up the mantissa. */
9963 /* We cannot represent infinities, NaNs or +/-zero. We won't
9964 know if we have +zero until we analyse the mantissa, but we
9965 can reject the other invalid values. */
9970 /* Extract exponent. */
9974 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
9975 highest (sign) bit, with a fixed binary point at bit point_pos.
9976 m1 holds the low part of the mantissa, m2 the high part.
9977 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
9978 bits for the mantissa, this can fail (low bits will be lost). */
9982 /* If the low part of the mantissa has bits set we cannot represent
9983 the value. */
9986 /* We have rejected the lower HOST_WIDE_INT, so update our
9987 understanding of how many bits lie in the mantissa and
9988 look only at the high HOST_WIDE_INT. */
9992 /* We can only represent values with a mantissa of the form 1.xxxx. */
9997 /* Having filtered unrepresentable values, we may now remove all
9998 but the highest 5 bits. */
10001 /* We cannot represent the value 0.0, so reject it. This is handled
10002 elsewhere. */
10006 /* Then, as bit 4 is always set, we can mask it off, leaving
10007 the mantissa in the range [0, 15]. */
10011 /* GCC internally does not use IEEE754-like encoding (where normalized
10012 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
10013 Our mantissa values are shifted 4 places to the left relative to
10014 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
10015 by 5 places to correct for GCC's representation. */
10019 }
10023 machine_mode mode,
10025 {
10035 /* This will return true to show const_vector is legal for use as either
10036 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
10037 also update INFO to show how the immediate should be generated. */
10046 {
10050 else
10051 {
10052 #define buf_size 20
10053 REAL_VALUE_TYPE r;
10057 #undef buf_size
10061 else
10065 }
10066 }
10078 else
10082 }
10086 machine_mode mode)
10087 {
10088 machine_mode vmode;
10094 }
10096 /* Split operands into moves from op[1] + op[2] into op[0]. */
10098 void
10100 {
10111 {
10112 /* No-op move. Can't split to nothing; emit something. */
10115 }
10117 /* Preserve register attributes for variable tracking. */
10122 /* Special case of reversed high/low parts. */
10125 {
10129 }
10131 {
10132 /* Try to avoid unnecessary moves if part of the result
10133 is in the right place already. */
10138 }
10139 else
10140 {
10145 }
10146 }
10148 /* vec_perm support. */
10150 #define MAX_VECT_LEN 16
10152 struct expand_vec_perm_d
10153 {
10156 machine_mode vmode;
10160 };
10162 /* Generate a variable permutation. */
10164 static void
10166 {
10177 {
10179 {
10180 /* Expand the argument to a V16QI mode by duplicating it. */
10184 }
10185 else
10186 {
10188 }
10189 }
10190 else
10191 {
10192 rtx pair;
10195 {
10199 }
10200 else
10201 {
10205 }
10206 }
10207 }
10209 void
10211 {
10215 rtx mask;
10217 /* The TBL instruction does not use a modulo index, so we must take care
10218 of that ourselves. */
10223 /* For big-endian, we also need to reverse the index within the vector
10224 (but not which vector). */
10226 {
10227 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
10232 }
10234 }
10236 /* Recognize patterns suitable for the TRN instructions. */
10237 static bool
10239 {
10248 /* Note that these are little-endian tests.
10249 We correct for big-endian later. */
10254 else
10259 {
10264 }
10266 /* Success! */
10273 {
10276 }
10280 {
10282 {
10295 }
10296 }
10297 else
10298 {
10300 {
10313 }
10314 }
10318 }
10320 /* Recognize patterns suitable for the UZP instructions. */
10321 static bool
10323 {
10332 /* Note that these are little-endian tests.
10333 We correct for big-endian later. */
10338 else
10343 {
10347 }
10349 /* Success! */
10356 {
10359 }
10363 {
10365 {
10378 }
10379 }
10380 else
10381 {
10383 {
10396 }
10397 }
10401 }
10403 /* Recognize patterns suitable for the ZIP instructions. */
10404 static bool
10406 {
10415 /* Note that these are little-endian tests.
10416 We correct for big-endian later. */
10419 /* Do Nothing. */
10420 ;
10423 else
10428 {
10435 }
10437 /* Success! */
10444 {
10447 }
10451 {
10453 {
10466 }
10467 }
10468 else
10469 {
10471 {
10484 }
10485 }
10489 }
10491 /* Recognize patterns for the EXT insn. */
10493 static bool
10495 {
10498 rtx offset;
10502 /* Check if the extracted indices are increasing by one. */
10504 {
10507 {
10508 /* We'll pass the same vector in twice, so allow indices to wrap. */
10510 }
10513 }
10516 {
10529 }
10531 /* Success! */
10535 /* The case where (location == 0) is a no-op for both big- and little-endian,
10536 and is removed by the mid-end at optimization levels -O1 and higher. */
10539 {
10540 /* After setup, we want the high elements of the first vector (stored
10541 at the LSB end of the register), and the low elements of the second
10542 vector (stored at the MSB end of the register). So swap. */
10544 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
10546 }
10551 }
10553 /* Recognize patterns for the REV insns. */
10555 static bool
10557 {
10566 {
10569 {
10574 }
10578 {
10585 }
10589 {
10600 }
10604 }
10608 {
10609 /* This is guaranteed to be true as the value of diff
10610 is 7, 3, 1 and we should have enough elements in the
10611 queue to generate this. Getting a vector mask with a
10612 value of diff other than these values implies that
10613 something is wrong by the time we get here. */
10617 }
10619 /* Success! */
10625 }
10627 static bool
10629 {
10632 rtx in0;
10635 rtx lane;
10639 {
10642 }
10644 /* The generic preparation in aarch64_expand_vec_perm_const_1
10645 swaps the operand order and the permute indices if it finds
10646 d->perm[0] to be in the second operand. Thus, we can always
10647 use d->op0 and need not do any extra arithmetic to get the
10648 correct lane number. */
10653 {
10666 }
10670 }
10672 static bool
10674 {
10682 /* Generic code will try constant permutation twice. Once with the
10683 original mode and again with the elements lowered to QImode.
10684 So wait and don't do the selector expansion ourselves. */
10689 {
10692 /* If big-endian and two vectors we end up with a weird mixed-endian
10693 mode on NEON. Reverse the index within each word but not the word
10694 itself. */
10697 }
10703 }
10705 static bool
10707 {
10708 /* The pattern matching functions above are written to look for a small
10709 number to begin the sequence (0, 1, N/2). If we begin with an index
10710 from the second operand, we can swap the operands. */
10712 {
10720 }
10723 {
10737 }
10739 }
10741 /* Expand a vec_perm_const pattern. */
10743 bool
10745 {
10759 {
10764 }
10767 {
10776 /* The elements of PERM do not suggest that only the first operand
10777 is used, but both operands are identical. Allow easier matching
10778 of the permutation by folding the permutation into the single
10779 input vector. */
10780 /* Fall Through. */
10792 }
10795 }
10797 static bool
10800 {
10810 /* Calculate whether all elements are in one vector. */
10812 {
10816 }
10818 /* If all elements are from the second vector, reindex as if from the
10819 first vector. */
10824 /* Check whether the mask can be applied to a single vector. */
10837 }
10839 rtx
10841 {
10842 /* We have to reverse each vector because we dont have
10843 a permuted load that can reverse-load according to ABI rules. */
10844 rtx mask;
10858 }
10860 /* Implement MODES_TIEABLE_P. */
10862 bool
10864 {
10868 /* We specifically want to allow elements of "structure" modes to
10869 be tieable to the structure. This more general condition allows
10870 other rarer situations too. */
10877 }
10879 /* Return a new RTX holding the result of moving POINTER forward by
10880 AMOUNT bytes. */
10882 static rtx
10884 {
10889 }
10891 /* Return a new RTX holding the result of moving POINTER forward by the
10892 size of the mode it points to. */
10894 static rtx
10896 {
10900 }
10902 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
10903 MODE bytes. */
10905 static void
10907 machine_mode mode)
10908 {
10911 /* "Cast" the pointers to the correct mode. */
10914 /* Emit the memcpy. */
10917 /* Move the pointers forward. */
10920 }
10922 /* Expand movmem, as if from a __builtin_memcpy. Return true if
10923 we succeed, otherwise return false. */
10925 bool
10927 {
10931 rtx base;
10934 /* When optimizing for size, give a better estimate of the length of a
10935 memcpy call, but use the default otherwise. */
10938 /* We can't do anything smart if the amount to copy is not constant. */
10944 /* Try to keep the number of instructions low. For cases below 16 bytes we
10945 need to make at most two moves. For cases above 16 bytes it will be one
10946 move for each 16 byte chunk, then at most two additional moves. */
10956 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
10957 1-byte chunk. */
10959 {
10961 {
10964 }
10970 }
10972 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
10973 4-byte chunk, partially overlapping with the previously copied chunk. */
10975 {
10979 {
10985 }
10987 }
10989 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
10990 them, then (if applicable) an 8-byte chunk. */
10992 {
10994 {
10997 }
10998 else
10999 {
11002 }
11003 }
11005 /* Finish the final bytes of the copy. We can always do this in one
11006 instruction. We either copy the exact amount we need, or partially
11007 overlap with the previous chunk we copied and copy 8-bytes. */
11016 else
11017 {
11019 {
11023 }
11024 else
11025 {
11031 }
11032 }
11035 }
11037 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
11039 static unsigned HOST_WIDE_INT
11041 {
11043 }
11045 static bool
11050 {
11051 /* STORE_BY_PIECES can be used when copying a constant string, but
11052 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
11053 For now we always fail this and let the move_by_pieces code copy
11054 the string from read-only memory. */
11059 }
11061 static enum machine_mode
11063 {
11065 {
11098 }
11099 }
11101 static rtx
11104 {
11123 {
11139 }
11144 {
11147 }
11161 {
11164 }
11169 }
11171 static rtx
11174 {
11193 {
11211 }
11216 {
11219 }
11236 {
11239 }
11245 }
11247 #undef TARGET_GEN_CCMP_FIRST
11248 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
11250 #undef TARGET_GEN_CCMP_NEXT
11251 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
11253 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
11254 instruction fusion of some sort. */
11256 static bool
11258 {
11260 }
11263 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
11264 should be kept together during scheduling. */
11266 static bool
11268 {
11269 rtx set_dest;
11272 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
11280 {
11281 /* We are trying to match:
11282 prev (mov) == (set (reg r0) (const_int imm16))
11283 curr (movk) == (set (zero_extract (reg r0)
11284 (const_int 16)
11285 (const_int 16))
11286 (const_int imm16_1)) */
11298 {
11300 }
11301 }
11305 {
11307 /* We're trying to match:
11308 prev (adrp) == (set (reg r1)
11309 (high (symbol_ref ("SYM"))))
11310 curr (add) == (set (reg r0)
11311 (lo_sum (reg r1)
11312 (symbol_ref ("SYM"))))
11313 Note that r0 need not necessarily be the same as r1, especially
11314 during pre-regalloc scheduling. */
11318 {
11326 }
11327 }
11331 {
11333 /* We're trying to match:
11334 prev (movk) == (set (zero_extract (reg r0)
11335 (const_int 16)
11336 (const_int 32))
11337 (const_int imm16_1))
11338 curr (movk) == (set (zero_extract (reg r0)
11339 (const_int 16)
11340 (const_int 48))
11341 (const_int imm16_2)) */
11357 }
11360 {
11361 /* We're trying to match:
11362 prev (adrp) == (set (reg r0)
11363 (high (symbol_ref ("SYM"))))
11364 curr (ldr) == (set (reg r1)
11365 (mem (lo_sum (reg r0)
11366 (symbol_ref ("SYM")))))
11367 or
11368 curr (ldr) == (set (reg r1)
11369 (zero_extend (mem
11370 (lo_sum (reg r0)
11371 (symbol_ref ("SYM")))))) */
11374 {
11387 }
11388 }
11392 {
11395 /* FIXME: this misses some which is considered simple arthematic
11396 instructions for ThunderX. Simple shifts are missed here. */
11402 }
11405 }
11407 /* If MEM is in the form of [base+offset], extract the two parts
11408 of address and set to BASE and OFFSET, otherwise return false
11409 after clearing BASE and OFFSET. */
11411 bool
11413 {
11414 rtx addr;
11421 {
11425 }
11429 {
11433 }
11439 }
11441 /* Types for scheduling fusion. */
11442 enum sched_fusion_type
11443 {
11445 SCHED_FUSION_LD_SIGN_EXTEND,
11446 SCHED_FUSION_LD_ZERO_EXTEND,
11447 SCHED_FUSION_LD,
11448 SCHED_FUSION_ST,
11449 SCHED_FUSION_NUM
11450 };
11452 /* If INSN is a load or store of address in the form of [base+offset],
11453 extract the two parts and set to BASE and OFFSET. Return scheduling
11454 fusion type this INSN is. */
11456 static enum sched_fusion_type
11458 {
11475 {
11480 }
11482 {
11487 }
11492 {
11495 }
11496 else
11503 }
11505 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
11507 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
11508 and PRI are only calculated for these instructions. For other instruction,
11509 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
11510 type instruction fusion can be added by returning different priorities.
11512 It's important that irrelevant instructions get the largest FUSION_PRI. */
11514 static void
11517 {
11527 {
11531 }
11533 /* Set FUSION_PRI according to fusion type and base register. */
11536 /* Calculate PRI. */
11539 /* INSN with smaller offset goes first. */
11543 else
11548 }
11550 /* Given OPERANDS of consecutive load/store, check if we can merge
11551 them into ldp/stp. LOAD is true if they are load instructions.
11552 MODE is the mode of memory operands. */
11554 bool
11557 {
11563 {
11571 }
11572 else
11573 {
11578 }
11580 /* The mems cannot be volatile. */
11584 /* Check if the addresses are in the form of [base+offset]. */
11592 /* Check if the bases are same. */
11599 /* Check if the offsets are consecutive. */
11603 /* Check if the addresses are clobbered by load. */
11605 {
11609 /* In increasing order, the last load can clobber the address. */
11612 }
11616 else
11621 else
11624 /* Check if the registers are of same class. */
11629 }
11631 /* Given OPERANDS of consecutive load/store, check if we can merge
11632 them into ldp/stp by adjusting the offset. LOAD is true if they
11633 are load instructions. MODE is the mode of memory operands.
11635 Given below consecutive stores:
11637 str w1, [xb, 0x100]
11638 str w1, [xb, 0x104]
11639 str w1, [xb, 0x108]
11640 str w1, [xb, 0x10c]
11642 Though the offsets are out of the range supported by stp, we can
11643 still pair them after adjusting the offset, like:
11645 add scratch, xb, 0x100
11646 stp w1, w1, [scratch]
11647 stp w1, w1, [scratch, 0x8]
11649 The peephole patterns detecting this opportunity should guarantee
11650 the scratch register is avaliable. */
11652 bool
11655 {
11662 {
11675 }
11676 else
11677 {
11686 }
11687 /* Skip if memory operand is by itslef valid for ldp/stp. */
11691 /* The mems cannot be volatile. */
11696 /* Check if the addresses are in the form of [base+offset]. */
11710 /* Check if the bases are same. */
11721 /* Check if the offsets are consecutive. */
11730 /* Check if the addresses are clobbered by load. */
11732 {
11738 /* In increasing order, the last load can clobber the address. */
11741 }
11745 else
11750 else
11755 else
11760 else
11763 /* Check if the registers are of same class. */
11768 }
11770 /* Given OPERANDS of consecutive load/store, this function pairs them
11771 into ldp/stp after adjusting the offset. It depends on the fact
11772 that addresses of load/store instructions are in increasing order.
11773 MODE is the mode of memory operands. CODE is the rtl operator
11774 which should be applied to all memory operands, it's SIGN_EXTEND,
11775 ZERO_EXTEND or UNKNOWN. */
11777 bool
11780 {
11786 {
11791 }
11792 else
11793 {
11799 }
11804 /* Adjust offset thus it can fit in ldp/stp instruction. */
11812 /* Further adjust to make sure all offsets are OK. */
11814 {
11817 }
11819 /* Make sure the adjustment can be done with ADD/SUB instructions. */
11824 {
11827 }
11829 /* Create new memory references. */
11833 /* Check if the adjusted address is OK for ldp/stp. */
11852 {
11857 }
11859 {
11864 }
11867 {
11872 }
11873 else
11874 {
11879 }
11881 /* Emit adjusting instruction. */
11883 /* Emit ldp/stp instructions. */
11891 }
11893 /* Return 1 if pseudo register should be created and used to hold
11894 GOT address for PIC code. */
11896 bool
11898 {
11900 }
11902 #undef TARGET_ADDRESS_COST
11903 #define TARGET_ADDRESS_COST aarch64_address_cost
11905 /* This hook will determines whether unnamed bitfields affect the alignment
11906 of the containing structure. The hook returns true if the structure
11907 should inherit the alignment requirements of an unnamed bitfield's
11908 type. */
11909 #undef TARGET_ALIGN_ANON_BITFIELD
11910 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
11912 #undef TARGET_ASM_ALIGNED_DI_OP
11915 #undef TARGET_ASM_ALIGNED_HI_OP
11918 #undef TARGET_ASM_ALIGNED_SI_OP
11921 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11922 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
11923 hook_bool_const_tree_hwi_hwi_const_tree_true
11925 #undef TARGET_ASM_FILE_START
11926 #define TARGET_ASM_FILE_START aarch64_start_file
11928 #undef TARGET_ASM_OUTPUT_MI_THUNK
11929 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
11931 #undef TARGET_ASM_SELECT_RTX_SECTION
11932 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
11934 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11935 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
11937 #undef TARGET_BUILD_BUILTIN_VA_LIST
11938 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
11940 #undef TARGET_CALLEE_COPIES
11941 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
11943 #undef TARGET_CAN_ELIMINATE
11944 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
11946 #undef TARGET_CANNOT_FORCE_CONST_MEM
11947 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
11949 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11950 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
11952 /* Only the least significant bit is used for initialization guard
11953 variables. */
11954 #undef TARGET_CXX_GUARD_MASK_BIT
11955 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
11957 #undef TARGET_C_MODE_FOR_SUFFIX
11958 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
11960 #ifdef TARGET_BIG_ENDIAN_DEFAULT
11961 #undef TARGET_DEFAULT_TARGET_FLAGS
11962 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
11963 #endif
11965 #undef TARGET_CLASS_MAX_NREGS
11966 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
11968 #undef TARGET_BUILTIN_DECL
11969 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
11971 #undef TARGET_EXPAND_BUILTIN
11972 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
11974 #undef TARGET_EXPAND_BUILTIN_VA_START
11975 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
11977 #undef TARGET_FOLD_BUILTIN
11978 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
11980 #undef TARGET_FUNCTION_ARG
11981 #define TARGET_FUNCTION_ARG aarch64_function_arg
11983 #undef TARGET_FUNCTION_ARG_ADVANCE
11984 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
11986 #undef TARGET_FUNCTION_ARG_BOUNDARY
11987 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
11989 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11990 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
11992 #undef TARGET_FUNCTION_VALUE
11993 #define TARGET_FUNCTION_VALUE aarch64_function_value
11995 #undef TARGET_FUNCTION_VALUE_REGNO_P
11996 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
11998 #undef TARGET_FRAME_POINTER_REQUIRED
11999 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
12001 #undef TARGET_GIMPLE_FOLD_BUILTIN
12002 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
12004 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12005 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
12007 #undef TARGET_INIT_BUILTINS
12008 #define TARGET_INIT_BUILTINS aarch64_init_builtins
12010 #undef TARGET_LEGITIMATE_ADDRESS_P
12011 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
12013 #undef TARGET_LEGITIMATE_CONSTANT_P
12014 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
12016 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12017 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
12019 #undef TARGET_LRA_P
12020 #define TARGET_LRA_P hook_bool_void_true
12022 #undef TARGET_MANGLE_TYPE
12023 #define TARGET_MANGLE_TYPE aarch64_mangle_type
12025 #undef TARGET_MEMORY_MOVE_COST
12026 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
12028 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
12029 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
12031 #undef TARGET_MUST_PASS_IN_STACK
12032 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12034 /* This target hook should return true if accesses to volatile bitfields
12035 should use the narrowest mode possible. It should return false if these
12036 accesses should use the bitfield container type. */
12037 #undef TARGET_NARROW_VOLATILE_BITFIELD
12038 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
12040 #undef TARGET_OPTION_OVERRIDE
12041 #define TARGET_OPTION_OVERRIDE aarch64_override_options
12043 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
12044 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
12045 aarch64_override_options_after_change
12047 #undef TARGET_PASS_BY_REFERENCE
12048 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
12050 #undef TARGET_PREFERRED_RELOAD_CLASS
12051 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
12053 #undef TARGET_SCHED_REASSOCIATION_WIDTH
12054 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
12056 #undef TARGET_SECONDARY_RELOAD
12057 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
12059 #undef TARGET_SHIFT_TRUNCATION_MASK
12060 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
12062 #undef TARGET_SETUP_INCOMING_VARARGS
12063 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
12065 #undef TARGET_STRUCT_VALUE_RTX
12066 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
12068 #undef TARGET_REGISTER_MOVE_COST
12069 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
12071 #undef TARGET_RETURN_IN_MEMORY
12072 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
12074 #undef TARGET_RETURN_IN_MSB
12075 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
12077 #undef TARGET_RTX_COSTS
12078 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
12080 #undef TARGET_SCHED_ISSUE_RATE
12081 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
12083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12085 aarch64_sched_first_cycle_multipass_dfa_lookahead
12087 #undef TARGET_TRAMPOLINE_INIT
12088 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
12090 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12091 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
12093 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12094 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
12096 #undef TARGET_ARRAY_MODE_SUPPORTED_P
12097 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
12099 #undef TARGET_VECTORIZE_ADD_STMT_COST
12100 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
12102 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
12103 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
12104 aarch64_builtin_vectorization_cost
12106 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
12107 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
12109 #undef TARGET_VECTORIZE_BUILTINS
12110 #define TARGET_VECTORIZE_BUILTINS
12112 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
12113 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
12114 aarch64_builtin_vectorized_function
12116 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
12117 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
12118 aarch64_autovectorize_vector_sizes
12120 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
12121 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
12122 aarch64_atomic_assign_expand_fenv
12124 /* Section anchor support. */
12126 #undef TARGET_MIN_ANCHOR_OFFSET
12127 #define TARGET_MIN_ANCHOR_OFFSET -256
12129 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
12130 byte offset; we can do much more for larger data types, but have no way
12131 to determine the size of the access. We assume accesses are aligned. */
12132 #undef TARGET_MAX_ANCHOR_OFFSET
12133 #define TARGET_MAX_ANCHOR_OFFSET 4095
12135 #undef TARGET_VECTOR_ALIGNMENT
12136 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
12138 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
12139 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
12140 aarch64_simd_vector_alignment_reachable
12142 /* vec_perm support. */
12144 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
12145 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
12146 aarch64_vectorize_vec_perm_const_ok
12149 #undef TARGET_FIXED_CONDITION_CODE_REGS
12150 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
12152 #undef TARGET_FLAGS_REGNUM
12153 #define TARGET_FLAGS_REGNUM CC_REGNUM
12155 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
12156 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
12158 #undef TARGET_ASAN_SHADOW_OFFSET
12159 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
12161 #undef TARGET_LEGITIMIZE_ADDRESS
12162 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
12164 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12165 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12166 aarch64_use_by_pieces_infrastructure_p
12168 #undef TARGET_CAN_USE_DOLOOP_P
12169 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
12171 #undef TARGET_SCHED_MACRO_FUSION_P
12172 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
12174 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
12175 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
12177 #undef TARGET_SCHED_FUSION_PRIORITY
12178 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
12180 #undef TARGET_USE_PSEUDO_PIC_REG
12181 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg