1 ;; Machine description the Motorola MCore
2 ;; Copyright (C) 1993, 1999, 2000, 2004 Free Software Foundation, Inc.
3 ;; Contributed by Motorola.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; -------------------------------------------------------------------------
28 ;; -------------------------------------------------------------------------
32 (define_attr "type" "brcond,branch,jmp,load,store,move,alu,shift"
35 ;; If a branch destination is within -2048..2047 bytes away from the
36 ;; instruction it can be 2 bytes long. All other conditional branches
37 ;; are 10 bytes long, and all other unconditional branches are 8 bytes.
39 ;; the assembler handles the long-branch span case for us if we use
40 ;; the "jb*" mnemonics for jumps/branches. This pushes the span
41 ;; calculations and the literal table placement into the assembler,
42 ;; where their interactions can be managed in a single place.
44 ;; All MCORE instructions are two bytes long.
46 (define_attr "length" "" (const_int 2))
48 ;; Scheduling. We only model a simple load latency.
49 (define_insn_reservation "any_insn" 1
50 (eq_attr "type" "!load")
52 (define_insn_reservation "memory" 2
53 (eq_attr "type" "load")
56 ;; -------------------------------------------------------------------------
58 ;; -------------------------------------------------------------------------
62 (sign_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
64 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
67 [(set_attr "type" "shift")])
71 (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
73 (match_operand:SI 1 "mcore_literal_K_operand" "K")))]
76 [(set_attr "type" "shift")])
78 ;;; This is created by combine.
81 (ne:CC (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
83 (match_operand:SI 1 "mcore_literal_K_operand" "K"))
87 [(set_attr "type" "shift")])
90 ;; Created by combine from conditional patterns below (see sextb/btsti rx,31)
94 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
97 "GET_CODE(operands[0]) == SUBREG &&
98 GET_MODE(SUBREG_REG(operands[0])) == QImode"
100 [(set_attr "type" "shift")])
104 (ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
107 "GET_CODE(operands[0]) == SUBREG &&
108 GET_MODE(SUBREG_REG(operands[0])) == HImode"
110 [(set_attr "type" "shift")])
114 (if_then_else (ne (eq:CC (zero_extract:SI
115 (match_operand:SI 0 "mcore_arith_reg_operand" "")
117 (match_operand:SI 1 "mcore_literal_K_operand" ""))
120 (label_ref (match_operand 2 "" ""))
124 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
125 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
126 (label_ref (match_dup 2))
132 (if_then_else (eq (ne:CC (zero_extract:SI
133 (match_operand:SI 0 "mcore_arith_reg_operand" "")
135 (match_operand:SI 1 "mcore_literal_K_operand" ""))
138 (label_ref (match_operand 2 "" ""))
142 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))
143 (set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
144 (label_ref (match_dup 2))
148 ;; XXX - disabled by nickc because it fails on libiberty/fnmatch.c
150 ;; ; Experimental - relax immediates for and, andn, or, and tst to allow
151 ;; ; any immediate value (or an immediate at all -- or, andn, & tst).
152 ;; ; This is done to allow bit field masks to fold together in combine.
153 ;; ; The reload phase will force the immediate into a register at the
154 ;; ; very end. This helps in some cases, but hurts in others: we'd
155 ;; ; really like to cse these immediates. However, there is a phase
156 ;; ; ordering problem here. cse picks up individual masks and cse's
157 ;; ; those, but not folded masks (cse happens before combine). It's
158 ;; ; not clear what the best solution is because we really want cse
159 ;; ; before combine (leaving the bit field masks alone). To pick up
160 ;; ; relaxed immediates use -mrelax-immediates. It might take some
161 ;; ; experimenting to see which does better (i.e. regular imms vs.
162 ;; ; arbitrary imms) for a particular code. BRC
166 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
167 ;; (match_operand:SI 1 "mcore_arith_any_imm_operand" "rI"))
169 ;; "TARGET_RELAX_IMM"
174 ;; (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
175 ;; (match_operand:SI 1 "mcore_arith_M_operand" "r"))
177 ;; "!TARGET_RELAX_IMM"
182 (ne:CC (and:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
183 (match_operand:SI 1 "mcore_arith_M_operand" "r"))
192 (ne:CC (ne:SI (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
193 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
196 (clobber (match_operand:CC 2 "mcore_arith_reg_operand" "=r"))])]
198 [(set (reg:CC 17) (ne:SI (match_dup 0) (const_int 0)))
199 (set (reg:CC 17) (leu:CC (match_dup 0) (match_dup 1)))])
201 ;; -------------------------------------------------------------------------
202 ;; SImode signed integer comparisons
203 ;; -------------------------------------------------------------------------
205 (define_insn "decne_t"
206 [(set (reg:CC 17) (ne:CC (plus:SI (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
210 (plus:SI (match_dup 0)
215 ;; The combiner seems to prefer the following to the former.
218 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
221 (plus:SI (match_dup 0)
226 (define_insn "cmpnesi_t"
227 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
228 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
232 (define_insn "cmpneisi_t"
233 [(set (reg:CC 17) (ne:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
234 (match_operand:SI 1 "mcore_arith_K_operand" "K")))]
238 (define_insn "cmpgtsi_t"
239 [(set (reg:CC 17) (gt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
240 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
245 [(set (reg:CC 17) (gt:CC (plus:SI
246 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
249 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
253 (define_insn "cmpltsi_t"
254 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
255 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
260 (define_insn "cmpltisi_t"
261 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
262 (match_operand:SI 1 "mcore_arith_J_operand" "J")))]
268 [(set (reg:CC 17) (lt:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
274 [(set (reg:CC 17) (lt:CC (plus:SI
275 (match_operand:SI 0 "mcore_arith_reg_operand" "+r")
278 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
282 ;; -------------------------------------------------------------------------
283 ;; SImode unsigned integer comparisons
284 ;; -------------------------------------------------------------------------
286 (define_insn "cmpgeusi_t"
287 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
288 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
292 (define_insn "cmpgeusi_0"
293 [(set (reg:CC 17) (geu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
298 (define_insn "cmpleusi_t"
299 [(set (reg:CC 17) (leu:CC (match_operand:SI 0 "mcore_arith_reg_operand" "r")
300 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
304 ;; We save the compare operands in the cmpxx patterns and use them when
305 ;; we generate the branch.
307 ;; We accept constants here, in case we can modify them to ones which
308 ;; are more efficient to load. E.g. change 'x <= 62' to 'x < 63'.
310 (define_expand "cmpsi"
311 [(set (reg:CC 17) (compare:CC (match_operand:SI 0 "mcore_compare_operand" "")
312 (match_operand:SI 1 "nonmemory_operand" "")))]
315 { arch_compare_op0 = operands[0];
316 arch_compare_op1 = operands[1];
320 ;; -------------------------------------------------------------------------
321 ;; Logical operations
322 ;; -------------------------------------------------------------------------
324 ;; Logical AND clearing a single bit. andsi3 knows that we have this
325 ;; pattern and allows the constant literal pass through.
328 ;; RBE 2/97: don't need this pattern any longer...
329 ;; RBE: I don't think we need both "S" and exact_log2() clauses.
331 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
332 ;; (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
333 ;; (match_operand:SI 2 "const_int_operand" "S")))]
334 ;; "mcore_arith_S_operand (operands[2])"
338 (define_insn "andnsi3"
339 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
340 (and:SI (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))
341 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
345 (define_expand "andsi3"
346 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
347 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
348 (match_operand:SI 2 "nonmemory_operand" "")))]
352 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
353 && ! mcore_arith_S_operand (operands[2]))
355 int not_value = ~ INTVAL (operands[2]);
356 if ( CONST_OK_FOR_I (not_value)
357 || CONST_OK_FOR_M (not_value)
358 || CONST_OK_FOR_N (not_value))
360 operands[2] = copy_to_mode_reg (SImode, GEN_INT (not_value));
361 emit_insn (gen_andnsi3 (operands[0], operands[2], operands[1]));
366 if (! mcore_arith_K_S_operand (operands[2], SImode))
367 operands[2] = copy_to_mode_reg (SImode, operands[2]);
371 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
372 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
373 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,K,0,S")))]
377 switch (which_alternative)
379 case 0: return \"and %0,%2\";
380 case 1: return \"andi %0,%2\";
381 case 2: return \"and %0,%1\";
382 /* case -1: return \"bclri %0,%Q2\"; will not happen */
383 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
388 ;; This was the old "S" which was "!(2^n)" */
389 ;; case -1: return \"bclri %0,%Q2\"; will not happen */
392 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
393 (and:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r,0")
394 (match_operand:SI 2 "mcore_arith_K_S_operand" "r,K,0,S")))]
398 switch (which_alternative)
400 case 0: return \"and %0,%2\";
401 case 1: return \"andi %0,%2\";
402 case 2: return \"and %0,%1\";
403 case 3: return mcore_output_bclri (operands[0], INTVAL (operands[2]));
408 ;(define_insn "iorsi3"
409 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
410 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
411 ; (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
415 ; need an expand to resolve ambiguity betw. the two iors below.
416 (define_expand "iorsi3"
417 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
418 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
419 (match_operand:SI 2 "nonmemory_operand" "")))]
423 if (! mcore_arith_M_operand (operands[2], SImode))
424 operands[2] = copy_to_mode_reg (SImode, operands[2]);
428 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
429 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
430 (match_operand:SI 2 "mcore_arith_any_imm_operand" "r,M,T")))]
434 switch (which_alternative)
436 case 0: return \"or %0,%2\";
437 case 1: return \"bseti %0,%P2\";
438 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
444 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
445 (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
446 (match_operand:SI 2 "mcore_arith_M_operand" "r,M,T")))]
450 switch (which_alternative)
452 case 0: return \"or %0,%2\";
453 case 1: return \"bseti %0,%P2\";
454 case 2: return mcore_output_bseti (operands[0], INTVAL (operands[2]));
460 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
461 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
462 ; (match_operand:SI 2 "const_int_operand" "M")))]
463 ; "exact_log2 (INTVAL (operands[2])) >= 0"
467 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
468 ; (ior:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
469 ; (match_operand:SI 2 "const_int_operand" "i")))]
470 ; "mcore_num_ones (INTVAL (operands[2])) < 3"
471 ; "* return mcore_output_bseti (operands[0], INTVAL (operands[2]));")
473 (define_insn "xorsi3"
474 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
475 (xor:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
476 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
480 ; these patterns give better code then gcc invents if
481 ; left to its own devices
483 (define_insn "anddi3"
484 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
485 (and:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
486 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
488 "and %0,%2\;and %R0,%R2"
489 [(set_attr "length" "4")])
491 (define_insn "iordi3"
492 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
493 (ior:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
494 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
496 "or %0,%2\;or %R0,%R2"
497 [(set_attr "length" "4")])
499 (define_insn "xordi3"
500 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
501 (xor:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
502 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))]
504 "xor %0,%2\;xor %R0,%R2"
505 [(set_attr "length" "4")])
507 ;; -------------------------------------------------------------------------
508 ;; Shifts and rotates
509 ;; -------------------------------------------------------------------------
511 ;; Only allow these if the shift count is a convenient constant.
512 (define_expand "rotlsi3"
513 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
514 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
515 (match_operand:SI 2 "nonmemory_operand" "")))]
517 "if (! mcore_literal_K_operand (operands[2], SImode))
521 ;; We can only do constant rotates, which is what this pattern provides.
522 ;; The combiner will put it together for us when we do:
523 ;; (x << N) | (x >> (32 - N))
525 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
526 (rotate:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
527 (match_operand:SI 2 "mcore_literal_K_operand" "K")))]
530 [(set_attr "type" "shift")])
532 (define_insn "ashlsi3"
533 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
534 (ashift:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
535 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
540 [(set_attr "type" "shift")])
543 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
544 (ashift:SI (const_int 1)
545 (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
548 [(set_attr "type" "shift")])
550 (define_insn "ashrsi3"
551 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
552 (ashiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
553 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
558 [(set_attr "type" "shift")])
560 (define_insn "lshrsi3"
561 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
562 (lshiftrt:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0")
563 (match_operand:SI 2 "mcore_arith_K_operand_not_0" "r,K")))]
568 [(set_attr "type" "shift")])
570 ;(define_expand "ashldi3"
571 ; [(parallel[(set (match_operand:DI 0 "mcore_arith_reg_operand" "")
572 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "")
573 ; (match_operand:DI 2 "immediate_operand" "")))
575 ; (clobber (reg:CC 17))])]
580 ; if (GET_CODE (operands[2]) != CONST_INT
581 ; || INTVAL (operands[2]) != 1)
586 ; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
587 ; (ashift:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
589 ; (clobber (reg:CC 17))]
591 ; "lsli %R0,0\;rotli %0,0"
592 ; [(set_attr "length" "4") (set_attr "type" "shift")])
594 ;; -------------------------------------------------------------------------
595 ;; Index instructions
596 ;; -------------------------------------------------------------------------
597 ;; The second of each set of patterns is borrowed from the alpha.md file.
598 ;; These variants of the above insns can occur if the second operand
599 ;; is the frame pointer. This is a kludge, but there doesn't
600 ;; seem to be a way around it. Only recognize them while reloading.
602 ;; We must use reload_operand for some operands in case frame pointer
603 ;; elimination put a MEM with invalid address there. Otherwise,
604 ;; the result of the substitution will not match this pattern, and reload
605 ;; will not be able to correctly fix the result.
607 ;; indexing longlongs or doubles (8 bytes)
609 (define_insn "indexdi_t"
610 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
611 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
613 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
616 if (! mcore_is_same_reg (operands[1], operands[2]))
618 output_asm_insn (\"ixw\\t%0,%1\", operands);
619 output_asm_insn (\"ixw\\t%0,%1\", operands);
623 output_asm_insn (\"ixh\\t%0,%1\", operands);
624 output_asm_insn (\"ixh\\t%0,%1\", operands);
628 ;; if operands[1] == operands[2], the first option above is wrong! -- dac
629 ;; was this... -- dac
630 ;; ixw %0,%1\;ixw %0,%1"
632 [(set_attr "length" "4")])
635 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
636 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
638 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
639 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
642 ixw %0,%1\;ixw %0,%1\;addu %0,%3
643 ixw %0,%1\;ixw %0,%1\;addi %0,%3
644 ixw %0,%1\;ixw %0,%1\;subi %0,%M3"
645 [(set_attr "length" "6")])
647 ;; indexing longs (4 bytes)
649 (define_insn "indexsi_t"
650 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
651 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
653 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
658 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
659 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
661 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
662 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
665 ixw %0,%1\;addu %0,%3
666 ixw %0,%1\;addi %0,%3
667 ixw %0,%1\;subi %0,%M3"
668 [(set_attr "length" "4")])
670 ;; indexing shorts (2 bytes)
672 (define_insn "indexhi_t"
673 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
674 (plus:SI (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
676 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
681 [(set (match_operand:SI 0 "mcore_reload_operand" "=r,r,r")
682 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "mcore_reload_operand" "r,r,r")
684 (match_operand:SI 2 "mcore_arith_reg_operand" "0,0,0"))
685 (match_operand:SI 3 "mcore_addsub_operand" "r,J,L")))]
688 ixh %0,%1\;addu %0,%3
689 ixh %0,%1\;addi %0,%3
690 ixh %0,%1\;subi %0,%M3"
691 [(set_attr "length" "4")])
694 ;; Other sizes may be handy for indexing.
695 ;; the tradeoffs to consider when adding these are
696 ;; code size, execution time [vs. mul it is easy to win],
697 ;; and register pressure -- these patterns don't use an extra
698 ;; register to build the offset from the base
699 ;; and whether the compiler will not come up with some other idiom.
702 ;; -------------------------------------------------------------------------
703 ;; Addition, Subtraction instructions
704 ;; -------------------------------------------------------------------------
706 (define_expand "addsi3"
707 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
708 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
709 (match_operand:SI 2 "nonmemory_operand" "")))]
713 extern int flag_omit_frame_pointer;
715 /* If this is an add to the frame pointer, then accept it as is so
716 that we can later fold in the fp/sp offset from frame pointer
718 if (flag_omit_frame_pointer
719 && GET_CODE (operands[1]) == REG
720 && (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
721 || REGNO (operands[1]) == FRAME_POINTER_REGNUM))
723 emit_insn (gen_addsi3_fp (operands[0], operands[1], operands[2]));
727 /* Convert adds to subtracts if this makes loading the constant cheaper.
728 But only if we are allowed to generate new pseudos. */
729 if (! (reload_in_progress || reload_completed)
730 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < -32)
732 int neg_value = - INTVAL (operands[2]);
733 if ( CONST_OK_FOR_I (neg_value)
734 || CONST_OK_FOR_M (neg_value)
735 || CONST_OK_FOR_N (neg_value))
737 operands[2] = copy_to_mode_reg (SImode, GEN_INT (neg_value));
738 emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
743 if (! mcore_addsub_operand (operands[2], SImode))
744 operands[2] = copy_to_mode_reg (SImode, operands[2]);
747 ;; RBE: for some constants which are not in the range which allows
748 ;; us to do a single operation, we will try a paired addi/addi instead
749 ;; of a movi/addi. This relieves some register pressure at the expense
750 ;; of giving away some potential constant reuse.
752 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
753 ;; for later reference
755 ;; (define_insn "addsi3_i2"
756 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
757 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
758 ;; (match_operand:SI 2 "const_int_operand" "g")))]
759 ;; "GET_CODE(operands[2]) == CONST_INT
760 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
761 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
764 ;; int n = INTVAL(operands[2]);
767 ;; operands[2] = GEN_INT(n - 32);
768 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
773 ;; operands[2] = GEN_INT(n - 32);
774 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
777 ;; [(set_attr "length" "4")])
779 (define_insn "addsi3_i"
780 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
781 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
782 (match_operand:SI 2 "mcore_addsub_operand" "r,J,L")))]
789 ;; This exists so that address computations based on the frame pointer
790 ;; can be folded in when frame pointer elimination occurs. Ordinarily
791 ;; this would be bad because it allows insns which would require reloading,
792 ;; but without it, we get multiple adds where one would do.
794 (define_insn "addsi3_fp"
795 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
796 (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0,0,0")
797 (match_operand:SI 2 "immediate_operand" "r,J,L")))]
798 "flag_omit_frame_pointer
799 && (reload_in_progress || reload_completed || REGNO (operands[1]) == FRAME_POINTER_REGNUM)"
805 ;; RBE: for some constants which are not in the range which allows
806 ;; us to do a single operation, we will try a paired addi/addi instead
807 ;; of a movi/addi. This relieves some register pressure at the expense
808 ;; of giving away some potential constant reuse.
810 ;; RBE 6/17/97: this didn't buy us anything, but I keep the pattern
811 ;; for later reference
813 ;; (define_insn "subsi3_i2"
814 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
815 ;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
816 ;; (match_operand:SI 2 "const_int_operand" "g")))]
817 ;; "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
818 ;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
819 ;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
822 ;; int n = INTVAL(operands[2]);
825 ;; operands[2] = GEN_INT( n - 32);
826 ;; return \"subi\\t%0,32\;subi\\t%0,%2\";
831 ;; operands[2] = GEN_INT(n - 32);
832 ;; return \"addi\\t%0,32\;addi\\t%0,%2\";
835 ;; [(set_attr "length" "4")])
837 ;(define_insn "subsi3"
838 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
839 ; (minus:SI (match_operand:SI 1 "mcore_arith_K_operand" "0,0,r,K")
840 ; (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0,0")))]
848 (define_insn "subsi3"
849 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r")
850 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,0,r")
851 (match_operand:SI 2 "mcore_arith_J_operand" "r,J,0")))]
859 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
860 (minus:SI (match_operand:SI 1 "mcore_literal_K_operand" "K")
861 (match_operand:SI 2 "mcore_arith_reg_operand" "0")))]
865 (define_insn "adddi3"
866 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
867 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
868 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
869 (clobber (reg:CC 17))]
873 if (TARGET_LITTLE_END)
874 return \"cmplt %0,%0\;addc %0,%2\;addc %R0,%R2\";
875 return \"cmplt %R0,%R0\;addc %R0,%R2\;addc %0,%2\";
877 [(set_attr "length" "6")])
879 ;; special case for "longlong += 1"
881 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
882 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
884 (clobber (reg:CC 17))]
888 if (TARGET_LITTLE_END)
889 return \"addi %0,1\;cmpnei %0,0\;incf %R0\";
890 return \"addi %R0,1\;cmpnei %R0,0\;incf %0\";
892 [(set_attr "length" "6")])
894 ;; special case for "longlong -= 1"
896 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
897 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
899 (clobber (reg:CC 17))]
903 if (TARGET_LITTLE_END)
904 return \"cmpnei %0,0\;decf %R0\;subi %0,1\";
905 return \"cmpnei %R0,0\;decf %0\;subi %R0,1\";
907 [(set_attr "length" "6")])
909 ;; special case for "longlong += const_int"
910 ;; we have to use a register for the const_int because we don't
911 ;; have an unsigned compare immediate... only +/- 1 get to
912 ;; play the no-extra register game because they compare with 0.
913 ;; This winds up working out for any literal that is synthesized
914 ;; with a single instruction. The more complicated ones look
915 ;; like the get broken into subreg's to get initialized too soon
916 ;; for us to catch here. -- RBE 4/25/96
917 ;; only allow for-sure positive values.
920 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
921 (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
922 (match_operand:SI 2 "const_int_operand" "r")))
923 (clobber (reg:CC 17))]
924 "GET_CODE (operands[2]) == CONST_INT
925 && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
928 if (GET_MODE (operands[2]) != SImode)
930 if (TARGET_LITTLE_END)
931 return \"addu %0,%2\;cmphs %0,%2\;incf %R0\";
932 return \"addu %R0,%2\;cmphs %R0,%2\;incf %0\";
934 [(set_attr "length" "6")])
936 ;; optimize "long long" + "unsigned long"
937 ;; won't trigger because of how the extension is expanded upstream.
939 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
940 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
941 ;; (zero_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
942 ;; (clobber (reg:CC 17))]
944 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0"
945 ;; [(set_attr "length" "6")])
947 ;; optimize "long long" + "signed long"
948 ;; won't trigger because of how the extension is expanded upstream.
950 ;; [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
951 ;; (plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "%0")
952 ;; (sign_extend:DI (match_operand:SI 2 "mcore_arith_reg_operand" "r"))))
953 ;; (clobber (reg:CC 17))]
955 ;; "cmplt %R0,%R0\;addc %R0,%2\;inct %0\;btsti %2,31\;dect %0"
956 ;; [(set_attr "length" "6")])
958 (define_insn "subdi3"
959 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
960 (minus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
961 (match_operand:DI 2 "mcore_arith_reg_operand" "r")))
962 (clobber (reg:CC 17))]
966 if (TARGET_LITTLE_END)
967 return \"cmphs %0,%0\;subc %0,%2\;subc %R0,%R2\";
968 return \"cmphs %R0,%R0\;subc %R0,%R2\;subc %0,%2\";
970 [(set_attr "length" "6")])
972 ;; -------------------------------------------------------------------------
973 ;; Multiplication instructions
974 ;; -------------------------------------------------------------------------
976 (define_insn "mulsi3"
977 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
978 (mult:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
979 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
984 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
986 ;; Different constraints based on the architecture revision...
988 (define_expand "divsi3"
989 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
990 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
991 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
995 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
998 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
999 (div:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1000 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
1005 ;; 32/32 signed division -- added to the MCORE instruction set spring 1997
1007 ;; Different constraints based on the architecture revision...
1009 (define_expand "udivsi3"
1010 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1011 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
1012 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
1016 ;; MCORE Revision 1.50: restricts the divisor to be in r1. (6/97)
1018 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1019 (udiv:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1020 (match_operand:SI 2 "mcore_arith_reg_operand" "b")))]
1024 ;; -------------------------------------------------------------------------
1026 ;; -------------------------------------------------------------------------
1028 (define_insn "negsi2"
1029 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1030 (neg:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1034 return \"rsubi %0,0\";
1038 (define_insn "abssi2"
1039 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1040 (abs:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1044 (define_insn "negdi2"
1045 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=&r")
1046 (neg:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")))
1047 (clobber (reg:CC 17))]
1051 if (TARGET_LITTLE_END)
1052 return \"cmpnei %0,0\\n\\trsubi %0,0\\n\\tnot %R0\\n\\tincf %R0\";
1053 return \"cmpnei %R0,0\\n\\trsubi %R0,0\\n\\tnot %0\\n\\tincf %0\";
1055 [(set_attr "length" "8")])
1057 (define_insn "one_cmplsi2"
1058 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1059 (not:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1063 ;; -------------------------------------------------------------------------
1064 ;; Zero extension instructions
1065 ;; -------------------------------------------------------------------------
1067 (define_expand "zero_extendhisi2"
1068 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1069 (zero_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "")))]
1074 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r")
1075 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
1080 [(set_attr "type" "shift,load")])
1082 ;; ldh gives us a free zero-extension. The combiner picks up on this.
1084 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1085 (zero_extend:SI (mem:HI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1088 [(set_attr "type" "load")])
1091 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1092 (zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1093 (match_operand:SI 2 "const_int_operand" "")))))]
1094 "(INTVAL (operands[2]) >= 0) &&
1095 (INTVAL (operands[2]) < 32) &&
1096 ((INTVAL (operands[2])&1) == 0)"
1098 [(set_attr "type" "load")])
1100 (define_expand "zero_extendqisi2"
1101 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1102 (zero_extend:SI (match_operand:QI 1 "general_operand" "")))]
1106 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1108 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b,r")
1109 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,r,m")))]
1115 [(set_attr "type" "shift,shift,load")])
1117 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1119 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1120 (zero_extend:SI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1123 [(set_attr "type" "load")])
1126 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1127 (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1128 (match_operand:SI 2 "const_int_operand" "")))))]
1129 "(INTVAL (operands[2]) >= 0) &&
1130 (INTVAL (operands[2]) < 16)"
1132 [(set_attr "type" "load")])
1134 (define_expand "zero_extendqihi2"
1135 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "")
1136 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
1140 ;; RBE: XXX: we don't recognize that the xtrb3 kills the CC register.
1142 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r,b,r")
1143 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,r,m")))]
1149 [(set_attr "type" "shift,shift,load")])
1151 ;; ldb gives us a free zero-extension. The combiner picks up on this.
1152 ;; this doesn't catch references that are into a structure.
1153 ;; note that normally the compiler uses the above insn, unless it turns
1154 ;; out that we're dealing with a volatile...
1156 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1157 (zero_extend:HI (mem:QI (match_operand:SI 1 "mcore_arith_reg_operand" "r"))))]
1160 [(set_attr "type" "load")])
1163 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1164 (zero_extend:HI (mem:QI (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r")
1165 (match_operand:SI 2 "const_int_operand" "")))))]
1166 "(INTVAL (operands[2]) >= 0) &&
1167 (INTVAL (operands[2]) < 16)"
1169 [(set_attr "type" "load")])
1172 ;; -------------------------------------------------------------------------
1173 ;; Sign extension instructions
1174 ;; -------------------------------------------------------------------------
1176 (define_expand "extendsidi2"
1177 [(set (match_operand:DI 0 "mcore_arith_reg_operand" "=r")
1178 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
1184 if (TARGET_LITTLE_END)
1189 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], low),
1191 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], high),
1192 gen_rtx_ASHIFTRT (SImode,
1193 gen_rtx_SUBREG (SImode, operands[0], low),
1199 (define_insn "extendhisi2"
1200 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1201 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))]
1205 (define_insn "extendqisi2"
1206 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1207 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1211 (define_insn "extendqihi2"
1212 [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
1213 (sign_extend:HI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))]
1217 ;; -------------------------------------------------------------------------
1218 ;; Move instructions
1219 ;; -------------------------------------------------------------------------
1223 (define_expand "movsi"
1224 [(set (match_operand:SI 0 "general_operand" "")
1225 (match_operand:SI 1 "general_operand" ""))]
1229 if (GET_CODE (operands[0]) == MEM)
1230 operands[1] = force_reg (SImode, operands[1]);
1234 [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
1235 (match_operand:SI 1 "mcore_general_movsrc_operand" "r,P,i,c,R,m,r"))]
1236 "(register_operand (operands[0], SImode)
1237 || register_operand (operands[1], SImode))"
1238 "* return mcore_output_move (insn, operands, SImode);"
1239 [(set_attr "type" "move,move,move,move,load,load,store")])
1245 (define_expand "movhi"
1246 [(set (match_operand:HI 0 "general_operand" "")
1247 (match_operand:HI 1 "general_operand" ""))]
1251 if (GET_CODE (operands[0]) == MEM)
1252 operands[1] = force_reg (HImode, operands[1]);
1253 else if (CONSTANT_P (operands[1])
1254 && (GET_CODE (operands[1]) != CONST_INT
1255 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1256 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1257 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1258 && ! reload_completed && ! reload_in_progress)
1260 rtx reg = gen_reg_rtx (SImode);
1261 emit_insn (gen_movsi (reg, operands[1]));
1262 operands[1] = gen_lowpart (HImode, reg);
1267 [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1268 (match_operand:HI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1269 "(register_operand (operands[0], HImode)
1270 || register_operand (operands[1], HImode))"
1271 "* return mcore_output_move (insn, operands, HImode);"
1272 [(set_attr "type" "move,move,move,move,load,store")])
1278 (define_expand "movqi"
1279 [(set (match_operand:QI 0 "general_operand" "")
1280 (match_operand:QI 1 "general_operand" ""))]
1284 if (GET_CODE (operands[0]) == MEM)
1285 operands[1] = force_reg (QImode, operands[1]);
1286 else if (CONSTANT_P (operands[1])
1287 && (GET_CODE (operands[1]) != CONST_INT
1288 || (! CONST_OK_FOR_I (INTVAL (operands[1]))
1289 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1290 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
1291 && ! reload_completed && ! reload_in_progress)
1293 rtx reg = gen_reg_rtx (SImode);
1294 emit_insn (gen_movsi (reg, operands[1]));
1295 operands[1] = gen_lowpart (QImode, reg);
1300 [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
1301 (match_operand:QI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
1302 "(register_operand (operands[0], QImode)
1303 || register_operand (operands[1], QImode))"
1304 "* return mcore_output_move (insn, operands, QImode);"
1305 [(set_attr "type" "move,move,move,move,load,store")])
1310 (define_expand "movdi"
1311 [(set (match_operand:DI 0 "general_operand" "")
1312 (match_operand:DI 1 "general_operand" ""))]
1316 if (GET_CODE (operands[0]) == MEM)
1317 operands[1] = force_reg (DImode, operands[1]);
1318 else if (GET_CODE (operands[1]) == CONST_INT
1319 && ! CONST_OK_FOR_I (INTVAL (operands[1]))
1320 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
1321 && ! CONST_OK_FOR_N (INTVAL (operands[1])))
1324 for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
1325 emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
1326 simplify_gen_subreg (SImode, operands[1], DImode, i));
1331 (define_insn "movdi_i"
1332 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,a,r,m")
1333 (match_operand:DI 1 "mcore_general_movsrc_operand" "I,M,N,r,R,m,r"))]
1335 "* return mcore_output_movedouble (operands, DImode);"
1336 [(set_attr "length" "4") (set_attr "type" "move,move,move,move,load,load,store")])
1340 (define_expand "movsf"
1341 [(set (match_operand:SF 0 "general_operand" "")
1342 (match_operand:SF 1 "general_operand" ""))]
1346 if (GET_CODE (operands[0]) == MEM)
1347 operands[1] = force_reg (SFmode, operands[1]);
1350 (define_insn "movsf_i"
1351 [(set (match_operand:SF 0 "general_operand" "=r,r,m")
1352 (match_operand:SF 1 "general_operand" "r,m,r"))]
1358 [(set_attr "type" "move,load,store")])
1362 (define_expand "movdf"
1363 [(set (match_operand:DF 0 "general_operand" "")
1364 (match_operand:DF 1 "general_operand" ""))]
1368 if (GET_CODE (operands[0]) == MEM)
1369 operands[1] = force_reg (DFmode, operands[1]);
1372 (define_insn "movdf_k"
1373 [(set (match_operand:DF 0 "general_operand" "=r,r,m")
1374 (match_operand:DF 1 "general_operand" "r,m,r"))]
1376 "* return mcore_output_movedouble (operands, DFmode);"
1377 [(set_attr "length" "4") (set_attr "type" "move,load,store")])
1380 ;; Load/store multiple
1382 ;; ??? This is not currently used.
1384 [(set (match_operand:TI 0 "mcore_arith_reg_operand" "=r")
1385 (mem:TI (match_operand:SI 1 "mcore_arith_reg_operand" "r")))]
1389 ;; ??? This is not currently used.
1391 [(set (mem:TI (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1392 (match_operand:TI 1 "mcore_arith_reg_operand" "r"))]
1396 (define_expand "load_multiple"
1397 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1398 (match_operand:SI 1 "" ""))
1399 (use (match_operand:SI 2 "" ""))])]
1403 int regno, count, i;
1405 /* Support only loading a constant number of registers from memory and
1406 only if at least two registers. The last register must be r15. */
1407 if (GET_CODE (operands[2]) != CONST_INT
1408 || INTVAL (operands[2]) < 2
1409 || GET_CODE (operands[1]) != MEM
1410 || XEXP (operands[1], 0) != stack_pointer_rtx
1411 || GET_CODE (operands[0]) != REG
1412 || REGNO (operands[0]) + INTVAL (operands[2]) != 16)
1415 count = INTVAL (operands[2]);
1416 regno = REGNO (operands[0]);
1418 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1420 for (i = 0; i < count; i++)
1421 XVECEXP (operands[3], 0, i)
1422 = gen_rtx_SET (VOIDmode,
1423 gen_rtx_REG (SImode, regno + i),
1424 gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx,
1429 [(match_parallel 0 "mcore_load_multiple_operation"
1430 [(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
1431 (mem:SI (match_operand:SI 2 "register_operand" "r")))])]
1432 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1435 (define_expand "store_multiple"
1436 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1437 (match_operand:SI 1 "" ""))
1438 (use (match_operand:SI 2 "" ""))])]
1442 int regno, count, i;
1444 /* Support only storing a constant number of registers to memory and
1445 only if at least two registers. The last register must be r15. */
1446 if (GET_CODE (operands[2]) != CONST_INT
1447 || INTVAL (operands[2]) < 2
1448 || GET_CODE (operands[0]) != MEM
1449 || XEXP (operands[0], 0) != stack_pointer_rtx
1450 || GET_CODE (operands[1]) != REG
1451 || REGNO (operands[1]) + INTVAL (operands[2]) != 16)
1454 count = INTVAL (operands[2]);
1455 regno = REGNO (operands[1]);
1457 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1459 for (i = 0; i < count; i++)
1460 XVECEXP (operands[3], 0, i)
1461 = gen_rtx_SET (VOIDmode,
1462 gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx,
1464 gen_rtx_REG (SImode, regno + i));
1468 [(match_parallel 0 "mcore_store_multiple_operation"
1469 [(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
1470 (match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
1471 "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
1474 ;; ------------------------------------------------------------------------
1475 ;; Define the real conditional branch instructions.
1476 ;; ------------------------------------------------------------------------
1478 (define_insn "branch_true"
1479 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1480 (label_ref (match_operand 0 "" ""))
1484 [(set_attr "type" "brcond")])
1486 (define_insn "branch_false"
1487 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1488 (label_ref (match_operand 0 "" ""))
1492 [(set_attr "type" "brcond")])
1494 (define_insn "inverse_branch_true"
1495 [(set (pc) (if_then_else (ne (reg:CC 17) (const_int 0))
1497 (label_ref (match_operand 0 "" ""))))]
1500 [(set_attr "type" "brcond")])
1502 (define_insn "inverse_branch_false"
1503 [(set (pc) (if_then_else (eq (reg:CC 17) (const_int 0))
1505 (label_ref (match_operand 0 "" ""))))]
1508 [(set_attr "type" "brcond")])
1510 ;; Conditional branch insns
1512 ;; At top-level, condition test are eq/ne, because we
1513 ;; are comparing against the condition register (which
1514 ;; has the result of the true relational test
1516 ; There is no beq compare, so we reverse the branch arms.
1518 (define_expand "beq"
1519 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1521 (label_ref (match_operand 0 "" ""))))]
1525 operands[1] = mcore_gen_compare_reg (EQ);
1528 (define_expand "bne"
1529 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1530 (label_ref (match_operand 0 "" ""))
1535 operands[1] = mcore_gen_compare_reg (NE);
1538 ; check whether (GT A imm) can become (LE A imm) with the branch reversed.
1539 ; if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
1541 (define_expand "bgt"
1542 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1543 (label_ref (match_operand 0 "" ""))
1548 if (mcore_modify_comparison (LE))
1550 emit_jump_insn (gen_reverse_blt (operands[0]));
1553 operands[1] = mcore_gen_compare_reg (GT);
1556 ; There is no ble compare, so we reverse the branch arms.
1557 ; reversed the condition and branch arms for ble -- the check_dbra_loop()
1558 ; transformation assumes that ble uses a branch-true with the label as
1559 ; as the target. BRC
1561 ; check whether (LE A imm) can become (LT A imm + 1).
1563 (define_expand "ble"
1564 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
1565 (label_ref (match_operand 0 "" ""))
1570 if (mcore_modify_comparison (LE))
1572 emit_jump_insn (gen_blt (operands[0]));
1575 operands[1] = mcore_gen_compare_reg (LE);
1578 ; make generating a reversed blt simple
1579 (define_expand "reverse_blt"
1580 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1582 (label_ref (match_operand 0 "" ""))))]
1586 operands[1] = mcore_gen_compare_reg (LT);
1589 (define_expand "blt"
1590 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1591 (label_ref (match_operand 0 "" ""))
1596 operands[1] = mcore_gen_compare_reg (LT);
1599 ; There is no bge compare, so we reverse the branch arms.
1601 (define_expand "bge"
1602 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1604 (label_ref (match_operand 0 "" ""))))]
1608 operands[1] = mcore_gen_compare_reg (GE);
1611 ; There is no gtu compare, so we reverse the branch arms
1613 ;(define_expand "bgtu"
1614 ; [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1616 ; (label_ref (match_operand 0 "" ""))))]
1620 ; if (GET_CODE (arch_compare_op1) == CONST_INT
1621 ; && INTVAL (arch_compare_op1) == 0)
1622 ; operands[1] = mcore_gen_compare_reg (NE);
1624 ; { if (mcore_modify_comparison (GTU))
1626 ; emit_jump_insn (gen_bgeu (operands[0]));
1629 ; operands[1] = mcore_gen_compare_reg (LEU);
1633 (define_expand "bgtu"
1634 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1636 (label_ref (match_operand 0 "" ""))))]
1640 if (GET_CODE (arch_compare_op1) == CONST_INT
1641 && INTVAL (arch_compare_op1) == 0)
1643 /* The inverse of '> 0' for an unsigned test is
1644 '== 0' but we do not have such an instruction available.
1645 Instead we must reverse the branch (back to the normal
1646 ordering) and test '!= 0'. */
1648 operands[1] = mcore_gen_compare_reg (NE);
1650 emit_jump_insn (gen_rtx_SET (VOIDmode,
1652 gen_rtx_IF_THEN_ELSE (VOIDmode,
1653 gen_rtx_NE (VOIDmode,
1656 gen_rtx_LABEL_REF (VOIDmode,operands[0]),
1660 operands[1] = mcore_gen_compare_reg (GTU);
1664 (define_expand "bleu"
1665 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1666 (label_ref (match_operand 0 "" ""))
1671 operands[1] = mcore_gen_compare_reg (LEU);
1674 ; There is no bltu compare, so we reverse the branch arms
1675 (define_expand "bltu"
1676 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1678 (label_ref (match_operand 0 "" ""))))]
1682 operands[1] = mcore_gen_compare_reg (LTU);
1685 (define_expand "bgeu"
1686 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
1687 (label_ref (match_operand 0 "" ""))
1693 operands[1] = mcore_gen_compare_reg (GEU);
1696 ;; ------------------------------------------------------------------------
1697 ;; Jump and linkage insns
1698 ;; ------------------------------------------------------------------------
1700 (define_insn "jump_real"
1702 (label_ref (match_operand 0 "" "")))]
1705 [(set_attr "type" "branch")])
1707 (define_expand "jump"
1708 [(set (pc) (label_ref (match_operand 0 "" "")))]
1712 emit_jump_insn (gen_jump_real (operand0));
1717 (define_insn "indirect_jump"
1719 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))]
1722 [(set_attr "type" "jmp")])
1724 (define_expand "call"
1725 [(parallel[(call (match_operand:SI 0 "" "")
1726 (match_operand 1 "" ""))
1727 (clobber (reg:SI 15))])]
1731 if (GET_CODE (operands[0]) == MEM
1732 && ! register_operand (XEXP (operands[0], 0), SImode)
1733 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1734 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1735 force_reg (Pmode, XEXP (operands[0], 0)));
1738 (define_insn "call_internal"
1739 [(call (mem:SI (match_operand:SI 0 "mcore_call_address_operand" "riR"))
1740 (match_operand 1 "" ""))
1741 (clobber (reg:SI 15))]
1743 "* return mcore_output_call (operands, 0);")
1745 (define_expand "call_value"
1746 [(parallel[(set (match_operand 0 "register_operand" "")
1747 (call (match_operand:SI 1 "" "")
1748 (match_operand 2 "" "")))
1749 (clobber (reg:SI 15))])]
1753 if (GET_CODE (operands[0]) == MEM
1754 && ! register_operand (XEXP (operands[0], 0), SImode)
1755 && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
1756 operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
1757 force_reg (Pmode, XEXP (operands[1], 0)));
1760 (define_insn "call_value_internal"
1761 [(set (match_operand 0 "register_operand" "=r")
1762 (call (mem:SI (match_operand:SI 1 "mcore_call_address_operand" "riR"))
1763 (match_operand 2 "" "")))
1764 (clobber (reg:SI 15))]
1766 "* return mcore_output_call (operands, 1);")
1768 (define_insn "call_value_struct"
1769 [(parallel [(set (match_parallel 0 ""
1770 [(expr_list (match_operand 3 "register_operand" "") (match_operand 4 "immediate_operand" ""))
1771 (expr_list (match_operand 5 "register_operand" "") (match_operand 6 "immediate_operand" ""))])
1772 (call (match_operand:SI 1 "" "")
1773 (match_operand 2 "" "")))
1774 (clobber (reg:SI 15))])]
1776 "* return mcore_output_call (operands, 1);"
1780 ;; ------------------------------------------------------------------------
1782 ;; ------------------------------------------------------------------------
1789 (define_insn "tablejump"
1791 (match_operand:SI 0 "mcore_arith_reg_operand" "r"))
1792 (use (label_ref (match_operand 1 "" "")))]
1795 [(set_attr "type" "jmp")])
1797 (define_insn "*return"
1799 "reload_completed && ! mcore_naked_function_p ()"
1801 [(set_attr "type" "jmp")])
1803 (define_insn "*no_return"
1805 "reload_completed && mcore_naked_function_p ()"
1807 [(set_attr "length" "0")]
1810 (define_expand "prologue"
1813 "mcore_expand_prolog (); DONE;")
1815 (define_expand "epilogue"
1818 "mcore_expand_epilog ();")
1820 ;; ------------------------------------------------------------------------
1822 ;; ------------------------------------------------------------------------
1825 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1826 (ne:SI (reg:CC 17) (const_int 0)))]
1829 [(set_attr "type" "move")])
1832 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1833 (eq:SI (reg:CC 17) (const_int 0)))]
1836 [(set_attr "type" "move")])
1838 ; in 0.97 use (LE 0) with (LT 1) and complement c. BRC
1841 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1842 (ne:SI (gt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
1845 (clobber (reg:SI 17))])]
1848 (lt:CC (match_dup 1) (const_int 1)))
1849 (set (match_dup 0) (eq:SI (reg:CC 17) (const_int 0)))])
1852 (define_expand "seq"
1853 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1854 (eq:SI (match_dup 1) (const_int 0)))]
1858 operands[1] = mcore_gen_compare_reg (NE);
1861 (define_expand "sne"
1862 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1863 (ne:SI (match_dup 1) (const_int 0)))]
1867 operands[1] = mcore_gen_compare_reg (NE);
1870 (define_expand "slt"
1871 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1872 (ne:SI (match_dup 1) (const_int 0)))]
1876 operands[1] = mcore_gen_compare_reg (LT);
1879 ; make generating a LT with the comparison reversed easy. BRC
1880 (define_expand "reverse_slt"
1881 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1882 (eq:SI (match_dup 1) (const_int 0)))]
1886 operands[1] = mcore_gen_compare_reg (LT);
1889 (define_expand "sge"
1890 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1891 (eq:SI (match_dup 1) (const_int 0)))]
1895 operands[1] = mcore_gen_compare_reg (LT);
1898 ; check whether (GT A imm) can become (LE A imm) with the comparison
1899 ; reversed. if so, emit a (LT A imm + 1) in place of the (LE A imm). BRC
1901 (define_expand "sgt"
1902 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1903 (ne:SI (match_dup 1) (const_int 0)))]
1907 if (mcore_modify_comparison (LE))
1909 emit_insn (gen_reverse_slt (operands[0]));
1913 operands[1] = mcore_gen_compare_reg (GT);
1916 (define_expand "sle"
1917 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1918 (eq:SI (match_dup 1) (const_int 0)))]
1922 if (mcore_modify_comparison (LE))
1924 emit_insn (gen_slt (operands[0]));
1927 operands[1] = mcore_gen_compare_reg (GT);
1930 (define_expand "sltu"
1931 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1932 (eq:SI (match_dup 1) (const_int 0)))]
1936 operands[1] = mcore_gen_compare_reg (GEU);
1939 (define_expand "sgeu"
1940 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1941 (ne:SI (match_dup 1) (const_int 0)))]
1945 operands[1] = mcore_gen_compare_reg (GEU);
1948 (define_expand "sgtu"
1949 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1950 (eq:SI (match_dup 1) (const_int 0)))]
1954 operands[1] = mcore_gen_compare_reg (LEU);
1957 (define_expand "sleu"
1958 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
1959 (ne:SI (match_dup 1) (const_int 0)))]
1963 operands[1] = mcore_gen_compare_reg (LEU);
1966 (define_insn "incscc"
1967 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1968 (plus:SI (ne (reg:CC 17) (const_int 0))
1969 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1973 (define_insn "incscc_false"
1974 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1975 (plus:SI (eq (reg:CC 17) (const_int 0))
1976 (match_operand:SI 1 "mcore_arith_reg_operand" "0")))]
1980 (define_insn "decscc"
1981 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1982 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1983 (ne (reg:CC 17) (const_int 0))))]
1987 (define_insn "decscc_false"
1988 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
1989 (minus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0")
1990 (eq (reg:CC 17) (const_int 0))))]
1994 ;; ------------------------------------------------------------------------
1995 ;; Conditional move patterns.
1996 ;; ------------------------------------------------------------------------
1998 (define_expand "smaxsi3"
2000 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2001 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2002 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2003 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2004 (match_dup 1) (match_dup 2)))]
2009 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2010 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2011 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2014 (lt:SI (match_dup 1) (match_dup 2)))
2016 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2017 (match_dup 1) (match_dup 2)))]
2020 ; no tstgt in 0.97, so just use cmplti (btsti x,31) and reverse move
2023 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2024 (smax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2028 (lt:CC (match_dup 1) (const_int 0)))
2030 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2031 (match_dup 1) (const_int 0)))]
2034 (define_expand "sminsi3"
2036 (lt:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2037 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2038 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2039 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2040 (match_dup 1) (match_dup 2)))]
2045 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2046 (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2047 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2050 (lt:SI (match_dup 1) (match_dup 2)))
2052 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2053 (match_dup 1) (match_dup 2)))]
2057 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2058 ; (smin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2062 ; (gt:CC (match_dup 1) (const_int 0)))
2063 ; (set (match_dup 0)
2064 ; (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2065 ; (match_dup 1) (const_int 0)))]
2068 ; changed these unsigned patterns to use geu instead of ltu. it appears
2069 ; that the c-torture & ssrl test suites didn't catch these! only showed
2070 ; up in friedman's clib work. BRC 7/7/95
2072 (define_expand "umaxsi3"
2074 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2075 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2076 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2077 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2078 (match_dup 2) (match_dup 1)))]
2083 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2084 (umax:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2085 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2088 (geu:SI (match_dup 1) (match_dup 2)))
2090 (if_then_else:SI (eq (reg:CC 17) (const_int 0))
2091 (match_dup 2) (match_dup 1)))]
2094 (define_expand "uminsi3"
2096 (geu:CC (match_operand:SI 1 "mcore_arith_reg_operand" "")
2097 (match_operand:SI 2 "mcore_arith_reg_operand" "")))
2098 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2099 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2100 (match_dup 2) (match_dup 1)))]
2105 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2106 (umin:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2107 (match_operand:SI 2 "mcore_arith_reg_operand" "")))]
2110 (geu:SI (match_dup 1) (match_dup 2)))
2112 (if_then_else:SI (ne (reg:CC 17) (const_int 0))
2113 (match_dup 2) (match_dup 1)))]
2116 ;; ------------------------------------------------------------------------
2117 ;; conditional move patterns really start here
2118 ;; ------------------------------------------------------------------------
2120 ;; the "movtK" patterns are experimental. they are intended to account for
2121 ;; gcc's mucking on code such as:
2123 ;; free_ent = ((block_compress) ? 257 : 256 );
2125 ;; these patterns help to get a tstne/bgeni/inct (or equivalent) sequence
2126 ;; when both arms have constants that are +/- 1 of each other.
2128 ;; note in the following patterns that the "movtK" ones should be the first
2129 ;; one defined in each sequence. this is because the general pattern also
2130 ;; matches, so use ordering to determine priority (it's easier this way than
2131 ;; adding conditions to the general patterns). BRC
2133 ;; the U and Q constraints are necessary to ensure that reload does the
2134 ;; 'right thing'. U constrains the operand to 0 and Q to 1 for use in the
2135 ;; clrt & clrf and clrt/inct & clrf/incf patterns. BRC 6/26
2137 ;; ??? there appears to be some problems with these movtK patterns for ops
2138 ;; other than eq & ne. need to fix. 6/30 BRC
2140 ;; ------------------------------------------------------------------------
2142 ;; ------------------------------------------------------------------------
2144 ; experimental conditional move with two constants +/- 1 BRC
2146 (define_insn "movtK_1"
2147 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2149 (ne (reg:CC 17) (const_int 0))
2150 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2151 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2152 " GET_CODE (operands[1]) == CONST_INT
2153 && GET_CODE (operands[2]) == CONST_INT
2154 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
2155 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2156 "* return mcore_output_cmov (operands, 1, NULL);"
2157 [(set_attr "length" "4")])
2159 (define_insn "movt0"
2160 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2162 (ne (reg:CC 17) (const_int 0))
2163 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2164 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2172 ;; ------------------------------------------------------------------------
2174 ;; ------------------------------------------------------------------------
2176 ; experimental conditional move with two constants +/- 1 BRC
2177 (define_insn "movtK_2"
2178 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2180 (eq (reg:CC 17) (const_int 0))
2181 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2182 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2183 " GET_CODE (operands[1]) == CONST_INT
2184 && GET_CODE (operands[2]) == CONST_INT
2185 && ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
2186 || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2187 "* return mcore_output_cmov (operands, 0, NULL);"
2188 [(set_attr "length" "4")])
2190 (define_insn "movf0"
2191 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2193 (eq (reg:CC 17) (const_int 0))
2194 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2195 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2203 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
2204 ; because the instructions are not adjacent (peepholes are related by posn -
2205 ; not by dataflow). BRC
2208 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2209 (if_then_else:SI (eq (zero_extract:SI
2210 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2212 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2214 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2215 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2218 btsti %1,%2\;movf %0,%3
2219 btsti %1,%2\;movt %0,%4
2220 btsti %1,%2\;clrf %0
2221 btsti %1,%2\;clrt %0"
2222 [(set_attr "length" "4")])
2224 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2227 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2228 (if_then_else:SI (eq (lshiftrt:SI
2229 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2232 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2233 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2234 "GET_CODE (operands[1]) == SUBREG &&
2235 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2237 btsti %1,7\;movf %0,%2
2238 btsti %1,7\;movt %0,%3
2240 btsti %1,7\;clrt %0"
2241 [(set_attr "length" "4")])
2244 ;; ------------------------------------------------------------------------
2246 ;; ------------------------------------------------------------------------
2248 ;; Combine creates this from an andn instruction in a scc sequence.
2249 ;; We must recognize it to get conditional moves generated.
2251 ; experimental conditional move with two constants +/- 1 BRC
2252 (define_insn "movtK_3"
2253 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2255 (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2257 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2258 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2259 " GET_CODE (operands[2]) == CONST_INT
2260 && GET_CODE (operands[3]) == CONST_INT
2261 && ( (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
2262 || (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2265 rtx out_operands[4];
2266 out_operands[0] = operands[0];
2267 out_operands[1] = operands[2];
2268 out_operands[2] = operands[3];
2269 out_operands[3] = operands[1];
2271 return mcore_output_cmov (out_operands, 1, \"cmpnei %3,0\");
2274 [(set_attr "length" "6")])
2276 (define_insn "movt2"
2277 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2278 (if_then_else:SI (ne (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2280 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2281 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2284 cmpnei %1,0\;movt %0,%2
2285 cmpnei %1,0\;movf %0,%3
2286 cmpnei %1,0\;clrt %0
2287 cmpnei %1,0\;clrf %0"
2288 [(set_attr "length" "4")])
2290 ; turns lsli rx,imm/btsti rx,31 into btsti rx,imm. not done by a peephole
2291 ; because the instructions are not adjacent (peepholes are related by posn -
2292 ; not by dataflow). BRC
2295 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2296 (if_then_else:SI (ne (zero_extract:SI
2297 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2299 (match_operand:SI 2 "mcore_literal_K_operand" "K,K,K,K"))
2301 (match_operand:SI 3 "mcore_arith_imm_operand" "r,0,U,0")
2302 (match_operand:SI 4 "mcore_arith_imm_operand" "0,r,0,U")))]
2305 btsti %1,%2\;movt %0,%3
2306 btsti %1,%2\;movf %0,%4
2307 btsti %1,%2\;clrt %0
2308 btsti %1,%2\;clrf %0"
2309 [(set_attr "length" "4")])
2311 ; turns sextb rx/btsti rx,31 into btsti rx,7. must be QImode to be safe. BRC
2314 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2315 (if_then_else:SI (ne (lshiftrt:SI
2316 (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2319 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2320 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2321 "GET_CODE (operands[1]) == SUBREG &&
2322 GET_MODE (SUBREG_REG (operands[1])) == QImode"
2324 btsti %1,7\;movt %0,%2
2325 btsti %1,7\;movf %0,%3
2327 btsti %1,7\;clrf %0"
2328 [(set_attr "length" "4")])
2330 ;; ------------------------------------------------------------------------
2332 ;; ------------------------------------------------------------------------
2334 ; experimental conditional move with two constants +/- 1 BRC
2335 (define_insn "movtK_4"
2336 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2338 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2339 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2340 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2341 "GET_CODE (operands[1]) == CONST_INT &&
2342 GET_CODE (operands[2]) == CONST_INT &&
2343 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2344 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2345 "* return mcore_output_cmov(operands, 1, NULL);"
2346 [(set_attr "length" "4")])
2348 (define_insn "movt3"
2349 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2351 (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2352 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2353 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2361 ;; ------------------------------------------------------------------------
2363 ;; ------------------------------------------------------------------------
2365 ; experimental conditional move with two constants +/- 1 BRC
2366 (define_insn "movtK_5"
2367 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2369 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2370 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2371 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2372 "GET_CODE (operands[1]) == CONST_INT &&
2373 GET_CODE (operands[2]) == CONST_INT &&
2374 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2375 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2376 "* return mcore_output_cmov (operands, 0, NULL);"
2377 [(set_attr "length" "4")])
2379 (define_insn "movf1"
2380 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2382 (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2383 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2384 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2392 ;; ------------------------------------------------------------------------
2394 ;; ------------------------------------------------------------------------
2396 ;; Combine creates this from an andn instruction in a scc sequence.
2397 ;; We must recognize it to get conditional moves generated.
2399 ; experimental conditional move with two constants +/- 1 BRC
2401 (define_insn "movtK_6"
2402 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2404 (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2406 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2407 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2408 "GET_CODE (operands[1]) == CONST_INT &&
2409 GET_CODE (operands[2]) == CONST_INT &&
2410 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2411 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2414 rtx out_operands[4];
2415 out_operands[0] = operands[0];
2416 out_operands[1] = operands[2];
2417 out_operands[2] = operands[3];
2418 out_operands[3] = operands[1];
2420 return mcore_output_cmov (out_operands, 0, \"cmpnei %3,0\");
2422 [(set_attr "length" "6")])
2424 (define_insn "movf3"
2425 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2426 (if_then_else:SI (eq (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2428 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2429 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2432 cmpnei %1,0\;movf %0,%2
2433 cmpnei %1,0\;movt %0,%3
2434 cmpnei %1,0\;clrf %0
2435 cmpnei %1,0\;clrt %0"
2436 [(set_attr "length" "4")])
2438 ;; ------------------------------------------------------------------------
2440 ;; ------------------------------------------------------------------------
2442 ; experimental conditional move with two constants +/- 1 BRC
2443 (define_insn "movtK_7"
2444 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2446 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2447 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2448 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2449 "GET_CODE (operands[1]) == CONST_INT &&
2450 GET_CODE (operands[2]) == CONST_INT &&
2451 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2452 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2453 "* return mcore_output_cmov (operands, 0, NULL);"
2454 [(set_attr "length" "4")])
2456 (define_insn "movf4"
2457 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2459 (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
2460 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2461 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2469 ;; ------------------------------------------------------------------------
2471 ;; ------------------------------------------------------------------------
2473 ; experimental conditional move with two constants +/- 1 BRC
2474 (define_insn "movtK_8"
2475 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2477 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2478 (match_operand:SI 1 "mcore_arith_O_operand" "O")
2479 (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
2480 "GET_CODE (operands[1]) == CONST_INT &&
2481 GET_CODE (operands[2]) == CONST_INT &&
2482 ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
2483 (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
2484 "* return mcore_output_cmov (operands, 1, NULL);"
2485 [(set_attr "length" "4")])
2487 (define_insn "movt4"
2488 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2490 (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
2491 (match_operand:SI 1 "mcore_arith_imm_operand" "r,0,U,0")
2492 (match_operand:SI 2 "mcore_arith_imm_operand" "0,r,0,U")))]
2500 ;; Also need patterns to recognize lt/ge, since otherwise the compiler will
2501 ;; try to output not/asri/tstne/movf.
2503 ;; ------------------------------------------------------------------------
2505 ;; ------------------------------------------------------------------------
2507 ; experimental conditional move with two constants +/- 1 BRC
2508 (define_insn "movtK_9"
2509 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2511 (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2513 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2514 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2515 "GET_CODE (operands[2]) == CONST_INT &&
2516 GET_CODE (operands[3]) == CONST_INT &&
2517 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2518 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2521 rtx out_operands[4];
2522 out_operands[0] = operands[0];
2523 out_operands[1] = operands[2];
2524 out_operands[2] = operands[3];
2525 out_operands[3] = operands[1];
2527 return mcore_output_cmov (out_operands, 1, \"btsti %3,31\");
2529 [(set_attr "length" "6")])
2531 (define_insn "movt5"
2532 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2533 (if_then_else:SI (lt (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2535 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2536 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2539 btsti %1,31\;movt %0,%2
2540 btsti %1,31\;movf %0,%3
2541 btsti %1,31\;clrt %0
2542 btsti %1,31\;clrf %0"
2543 [(set_attr "length" "4")])
2546 ;; ------------------------------------------------------------------------
2548 ;; ------------------------------------------------------------------------
2550 ; experimental conditional move with two constants +/- 1 BRC
2551 (define_insn "movtK_10"
2552 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2554 (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r")
2556 (match_operand:SI 2 "mcore_arith_O_operand" "O")
2557 (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
2558 "GET_CODE (operands[2]) == CONST_INT &&
2559 GET_CODE (operands[3]) == CONST_INT &&
2560 ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
2561 (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
2564 rtx out_operands[4];
2565 out_operands[0] = operands[0];
2566 out_operands[1] = operands[2];
2567 out_operands[2] = operands[3];
2568 out_operands[3] = operands[1];
2570 return mcore_output_cmov (out_operands, 0, \"btsti %3,31\");
2572 [(set_attr "length" "6")])
2574 (define_insn "movf5"
2575 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,r,r,r")
2576 (if_then_else:SI (ge (match_operand:SI 1 "mcore_arith_reg_operand" "r,r,r,r")
2578 (match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
2579 (match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
2582 btsti %1,31\;movf %0,%2
2583 btsti %1,31\;movt %0,%3
2584 btsti %1,31\;clrf %0
2585 btsti %1,31\;clrt %0"
2586 [(set_attr "length" "4")])
2588 ;; ------------------------------------------------------------------------
2589 ;; Bitfield extract (xtrbN)
2590 ;; ------------------------------------------------------------------------
2592 ; sometimes we're better off using QI/HI mode and letting the machine indep.
2593 ; part expand insv and extv.
2595 ; e.g., sequences like:a [an insertion]
2598 ; movi r7,0x00ffffff
2600 ; stw r8,(r6) r8 dead
2605 ; stb r8,(r6) r8 dead
2607 ; it looks like always using SI mode is a win except in this type of code
2608 ; (when adjacent bit fields collapse on a byte or halfword boundary). when
2609 ; expanding with SI mode, non-adjacent bit field masks fold, but with QI/HI
2610 ; mode, they do not. one thought is to add some peepholes to cover cases
2611 ; like the above, but this is not a general solution.
2613 ; -mword-bitfields expands/inserts using SI mode. otherwise, do it with
2614 ; the smallest mode possible (using the machine indep. expansions). BRC
2616 ;(define_expand "extv"
2617 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2618 ; (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2619 ; (match_operand:SI 2 "const_int_operand" "")
2620 ; (match_operand:SI 3 "const_int_operand" "")))
2621 ; (clobber (reg:CC 17))]
2625 ; if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) % 8 != 0)
2627 ; if (TARGET_W_FIELD)
2629 ; rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2630 ; rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2632 ; emit_insn (gen_rtx_SET (SImode, operands[0], operands[1]));
2633 ; emit_insn (gen_rtx_SET (SImode, operands[0],
2634 ; gen_rtx_ASHIFT (SImode, operands[0], lshft)));
2635 ; emit_insn (gen_rtx_SET (SImode, operands[0],
2636 ; gen_rtx_ASHIFTRT (SImode, operands[0], rshft)));
2644 (define_expand "extv"
2645 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2646 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2647 (match_operand:SI 2 "const_int_operand" "")
2648 (match_operand:SI 3 "const_int_operand" "")))
2649 (clobber (reg:CC 17))]
2653 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2655 /* 8 bit field, aligned properly, use the xtrb[0123]+sext sequence. */
2656 /* not DONE, not FAIL, but let the RTL get generated.... */
2658 else if (TARGET_W_FIELD)
2660 /* Arbitrary placement; note that the tree->rtl generator will make
2661 something close to this if we return FAIL */
2662 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2663 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2664 rtx tmp1 = gen_reg_rtx (SImode);
2665 rtx tmp2 = gen_reg_rtx (SImode);
2667 emit_insn (gen_rtx_SET (SImode, tmp1, operands[1]));
2668 emit_insn (gen_rtx_SET (SImode, tmp2,
2669 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2670 emit_insn (gen_rtx_SET (SImode, operands[0],
2671 gen_rtx_ASHIFTRT (SImode, tmp2, rshft)));
2676 /* Let the caller choose an alternate sequence. */
2681 (define_expand "extzv"
2682 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2683 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "")
2684 (match_operand:SI 2 "const_int_operand" "")
2685 (match_operand:SI 3 "const_int_operand" "")))
2686 (clobber (reg:CC 17))]
2690 if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
2692 /* 8 bit field, aligned properly, use the xtrb[0123] sequence. */
2693 /* Let the template generate some RTL.... */
2695 else if (CONST_OK_FOR_K ((1 << INTVAL (operands[2])) - 1))
2697 /* A narrow bit-field (<=5 bits) means we can do a shift to put
2698 it in place and then use an andi to extract it.
2699 This is as good as a shiftleft/shiftright. */
2702 rtx mask = GEN_INT ((1 << INTVAL (operands[2])) - 1);
2704 if (INTVAL (operands[3]) == 0)
2706 shifted = operands[1];
2710 rtx rshft = GEN_INT (INTVAL (operands[3]));
2711 shifted = gen_reg_rtx (SImode);
2712 emit_insn (gen_rtx_SET (SImode, shifted,
2713 gen_rtx_LSHIFTRT (SImode, operands[1], rshft)));
2715 emit_insn (gen_rtx_SET (SImode, operands[0],
2716 gen_rtx_AND (SImode, shifted, mask)));
2719 else if (TARGET_W_FIELD)
2721 /* Arbitrary pattern; play shift/shift games to get it.
2722 * this is pretty much what the caller will do if we say FAIL */
2723 rtx lshft = GEN_INT (32 - (INTVAL (operands[2]) + INTVAL (operands[3])));
2724 rtx rshft = GEN_INT (32 - INTVAL (operands[2]));
2725 rtx tmp1 = gen_reg_rtx (SImode);
2726 rtx tmp2 = gen_reg_rtx (SImode);
2728 emit_insn (gen_rtx_SET (SImode, tmp1, operands[1]));
2729 emit_insn (gen_rtx_SET (SImode, tmp2,
2730 gen_rtx_ASHIFT (SImode, tmp1, lshft)));
2731 emit_insn (gen_rtx_SET (SImode, operands[0],
2732 gen_rtx_LSHIFTRT (SImode, tmp2, rshft)));
2737 /* Make the compiler figure out some alternative mechanism. */
2741 /* Emit the RTL pattern; something will match it later. */
2744 (define_expand "insv"
2745 [(set (zero_extract:SI (match_operand:SI 0 "mcore_arith_reg_operand" "")
2746 (match_operand:SI 1 "const_int_operand" "")
2747 (match_operand:SI 2 "const_int_operand" ""))
2748 (match_operand:SI 3 "general_operand" ""))
2749 (clobber (reg:CC 17))]
2753 if (mcore_expand_insv (operands))
2764 ;; the xtrb[0123] instructions handily get at 8-bit fields on nice boundaries.
2765 ;; but then, they do force you through r1.
2767 ;; the combiner will build such patterns for us, so we'll make them available
2770 ;; Note that we have both SIGNED and UNSIGNED versions of these...
2774 ;; These no longer worry about the clobbering of CC bit; not sure this is
2777 ;; the SIGNED versions of these
2780 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2781 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2785 xtrb0 %0,%1\;sextb %0"
2786 [(set_attr "type" "shift")])
2789 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2790 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2792 "xtrb1 %0,%1\;sextb %0"
2793 [(set_attr "type" "shift")])
2796 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2797 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2799 "xtrb2 %0,%1\;sextb %0"
2800 [(set_attr "type" "shift")])
2803 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2804 (sign_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0") (const_int 8) (const_int 0)))]
2807 [(set_attr "type" "shift")])
2809 ;; the UNSIGNED uses of xtrb[0123]
2812 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2813 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 24)))]
2818 [(set_attr "type" "shift")])
2821 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2822 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 16)))]
2825 [(set_attr "type" "shift")])
2828 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=b")
2829 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "r") (const_int 8) (const_int 8)))]
2832 [(set_attr "type" "shift")])
2834 ;; This can be peepholed if it follows a ldb ...
2836 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r,b")
2837 (zero_extract:SI (match_operand:SI 1 "mcore_arith_reg_operand" "0,r") (const_int 8) (const_int 0)))]
2841 xtrb3 %0,%1\;zextb %0"
2842 [(set_attr "type" "shift")])
2845 ;; ------------------------------------------------------------------------
2846 ;; Block move - adapted from m88k.md
2847 ;; ------------------------------------------------------------------------
2849 (define_expand "movstrsi"
2850 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
2851 (mem:BLK (match_operand:BLK 1 "" "")))
2852 (use (match_operand:SI 2 "general_operand" ""))
2853 (use (match_operand:SI 3 "immediate_operand" ""))])]
2857 rtx dest_mem = operands[0];
2858 rtx src_mem = operands[1];
2859 operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
2860 operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
2861 mcore_expand_block_move (dest_mem, src_mem, operands);
2865 ;; ;;; ??? These patterns are meant to be generated from expand_block_move,
2866 ;; ;;; but they currently are not.
2869 ;; [(set (match_operand:QI 0 "mcore_arith_reg_operand" "=r")
2870 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2873 ;; [(set_attr "type" "load")])
2876 ;; [(set (match_operand:HI 0 "mcore_arith_reg_operand" "=r")
2877 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2880 ;; [(set_attr "type" "load")])
2883 ;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2884 ;; (match_operand:BLK 1 "mcore_general_movsrc_operand" "m"))]
2887 ;; [(set_attr "type" "load")])
2890 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2891 ;; (match_operand:QI 1 "mcore_arith_reg_operand" "r"))]
2894 ;; [(set_attr "type" "store")])
2897 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2898 ;; (match_operand:HI 1 "mcore_arith_reg_operand" "r"))]
2901 ;; [(set_attr "type" "store")])
2904 ;; [(set (match_operand:BLK 0 "mcore_general_movdst_operand" "=m")
2905 ;; (match_operand:SI 1 "mcore_arith_reg_operand" "r"))]
2908 ;; [(set_attr "type" "store")])
2910 ;; ------------------------------------------------------------------------
2911 ;; Misc Optimizing quirks
2912 ;; ------------------------------------------------------------------------
2914 ;; pair to catch constructs like: (int *)((p+=4)-4) which happen
2915 ;; in stdarg/varargs traversal. This changes a 3 insn sequence to a 2
2916 ;; insn sequence. -- RBE 11/30/95
2919 (set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
2920 (match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
2921 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2922 "GET_CODE(operands[2]) == CONST_INT"
2924 [(set_attr "length" "4")])
2928 (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2929 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
2930 (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
2931 "GET_CODE(operands[2]) == CONST_INT &&
2932 operands[0] != operands[1]"
2933 [(set (match_dup 0) (match_dup 1))
2934 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
2939 ; note: in the following patterns, use mcore_is_dead() to ensure that the
2940 ; reg we may be trashing really is dead. reload doesn't always mark
2941 ; deaths, so mcore_is_dead() (see mcore.c) scans forward to find its death. BRC
2943 ;;; A peephole to convert the 3 instruction sequence generated by reload
2944 ;;; to load a FP-offset address into a 2 instruction sequence.
2945 ;;; ??? This probably never matches anymore.
2947 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2948 (match_operand:SI 1 "const_int_operand" "J"))
2949 (set (match_dup 0) (neg:SI (match_dup 0)))
2951 (plus:SI (match_dup 0)
2952 (match_operand:SI 2 "mcore_arith_reg_operand" "r")))]
2953 "CONST_OK_FOR_J (INTVAL (operands[1]))"
2954 "error\;mov %0,%2\;subi %0,%1")
2956 ;; Moves of inlinable constants are done late, so when a 'not' is generated
2957 ;; it is never combined with the following 'and' to generate an 'andn' b/c
2958 ;; the combiner never sees it. use a peephole to pick up this case (happens
2959 ;; mostly with bitfields) BRC
2962 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
2963 (match_operand:SI 1 "const_int_operand" "i"))
2964 (set (match_operand:SI 2 "mcore_arith_reg_operand" "r")
2965 (and:SI (match_dup 2) (match_dup 0)))]
2966 "mcore_const_trick_uses_not (INTVAL (operands[1])) &&
2967 operands[0] != operands[2] &&
2968 mcore_is_dead (insn, operands[0])"
2969 "* return mcore_output_andn (insn, operands);")
2971 ; when setting or clearing just two bits, it's cheapest to use two bseti's
2972 ; or bclri's. only happens when relaxing immediates. BRC
2975 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2976 (match_operand:SI 1 "const_int_operand" ""))
2977 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2978 (ior:SI (match_dup 2) (match_dup 0)))]
2979 "TARGET_HARDLIT && mcore_num_ones (INTVAL (operands[1])) == 2 &&
2980 mcore_is_dead (insn, operands[0])"
2981 "* return mcore_output_bseti (operands[2], INTVAL (operands[1]));")
2984 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2985 (match_operand:SI 1 "const_int_operand" ""))
2986 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
2987 (and:SI (match_dup 2) (match_dup 0)))]
2988 "TARGET_HARDLIT && mcore_num_zeros (INTVAL (operands[1])) == 2 &&
2989 mcore_is_dead (insn, operands[0])"
2990 "* return mcore_output_bclri (operands[2], INTVAL (operands[1]));")
2992 ; change an and with a mask that has a single cleared bit into a bclri. this
2993 ; handles QI and HI mode values using the knowledge that the most significant
2994 ; bits don't matter.
2997 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
2998 (match_operand:SI 1 "const_int_operand" ""))
2999 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3000 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
3002 "GET_CODE (operands[3]) == SUBREG &&
3003 GET_MODE (SUBREG_REG (operands[3])) == QImode &&
3004 mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
3005 mcore_is_dead (insn, operands[0])"
3007 if (! mcore_is_same_reg (operands[2], operands[3]))
3008 output_asm_insn (\"mov\\t%2,%3\", operands);
3009 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffffff00);")
3011 /* Do not fold these together -- mode is lost at final output phase. */
3014 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3015 (match_operand:SI 1 "const_int_operand" ""))
3016 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3017 (and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
3019 "GET_CODE (operands[3]) == SUBREG &&
3020 GET_MODE (SUBREG_REG (operands[3])) == HImode &&
3021 mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
3022 operands[2] == operands[3] &&
3023 mcore_is_dead (insn, operands[0])"
3025 if (! mcore_is_same_reg (operands[2], operands[3]))
3026 output_asm_insn (\"mov\\t%2,%3\", operands);
3027 return mcore_output_bclri (operands[2], INTVAL (operands[1]) | 0xffff0000);")
3029 ; This peephole helps when using -mwide-bitfields to widen fields so they
3030 ; collapse. This, however, has the effect that a narrower mode is not used
3033 ; e.g., sequences like:
3036 ; movi r7,0x00ffffff
3038 ; stw r8,(r6) r8 dead
3040 ; get peepholed to become:
3043 ; stb r8,(r6) r8 dead
3045 ; Do only easy addresses that have no offset. This peephole is also applied
3046 ; to halfwords. We need to check that the load is non-volatile before we get
3050 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3051 (match_operand:SI 1 "memory_operand" ""))
3052 (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3053 (match_operand:SI 3 "const_int_operand" ""))
3054 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
3055 (set (match_operand:SI 4 "memory_operand" "") (match_dup 0))]
3056 "mcore_is_dead (insn, operands[0]) &&
3057 ! MEM_VOLATILE_P (operands[1]) &&
3058 mcore_is_dead (insn, operands[2]) &&
3059 (mcore_byte_offset (INTVAL (operands[3])) > -1 ||
3060 mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
3061 ! MEM_VOLATILE_P (operands[4]) &&
3062 GET_CODE (XEXP (operands[4], 0)) == REG"
3066 enum machine_mode mode;
3067 rtx base_reg = XEXP (operands[4], 0);
3069 if ((ofs = mcore_byte_offset (INTVAL (operands[3]))) > -1)
3071 else if ((ofs = mcore_halfword_offset (INTVAL (operands[3]))) > -1)
3077 operands[4] = gen_rtx_MEM (mode,
3078 gen_rtx_PLUS (SImode, base_reg, GEN_INT(ofs)));
3080 operands[4] = gen_rtx_MEM (mode, base_reg);
3083 return \"movi %0,0\\n\\tst.b %0,%4\";
3085 return \"movi %0,0\\n\\tst.h %0,%4\";
3088 ; from sop11. get btsti's for (LT A 0) where A is a QI or HI value
3091 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3092 (sign_extend:SI (match_operand:QI 1 "mcore_arith_reg_operand" "0")))
3094 (lt:CC (match_dup 0)
3096 "mcore_is_dead (insn, operands[0])"
3100 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3101 (sign_extend:SI (match_operand:HI 1 "mcore_arith_reg_operand" "0")))
3103 (lt:CC (match_dup 0)
3105 "mcore_is_dead (insn, operands[0])"
3108 ; Pick up a tst. This combination happens because the immediate is not
3109 ; allowed to fold into one of the operands of the tst. Does not happen
3110 ; when relaxing immediates. BRC
3113 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3114 (match_operand:SI 1 "mcore_arith_reg_operand" ""))
3116 (and:SI (match_dup 0)
3117 (match_operand:SI 2 "mcore_literal_K_operand" "")))
3118 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
3119 "mcore_is_dead (insn, operands[0])"
3120 "movi %0,%2\;tst %1,%0")
3123 [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3124 (if_then_else:SI (ne (zero_extract:SI
3125 (match_operand:SI 1 "mcore_arith_reg_operand" "")
3127 (match_operand:SI 2 "mcore_literal_K_operand" ""))
3129 (match_operand:SI 3 "mcore_arith_imm_operand" "")
3130 (match_operand:SI 4 "mcore_arith_imm_operand" "")))
3131 (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))]
3135 unsigned int op0 = REGNO (operands[0]);
3137 if (GET_CODE (operands[3]) == REG)
3139 if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
3140 && INTVAL (operands[4]) == 0)
3141 return \"btsti %1,%2\\n\\tclrf %0\";
3142 else if (GET_CODE (operands[4]) == REG)
3144 if (REGNO (operands[4]) == op0)
3145 return \"btsti %1,%2\\n\\tmovf %0,%3\";
3146 else if (REGNO (operands[3]) == op0)
3147 return \"btsti %1,%2\\n\\tmovt %0,%4\";
3152 else if (GET_CODE (operands[3]) == CONST_INT
3153 && INTVAL (operands[3]) == 0
3154 && GET_CODE (operands[4]) == REG)
3155 return \"btsti %1,%2\\n\\tclrt %0\";
3161 ; experimental - do the constant folding ourselves. note that this isn't
3162 ; re-applied like we'd really want. ie., four ands collapse into two
3163 ; instead of one. this is because peepholes are applied as a sliding
3164 ; window. the peephole does not generate new rtl's, but instead slides
3165 ; across the rtl's generating machine instructions. it would be nice
3166 ; if the peephole optimizer is changed to re-apply patterns and to gen
3167 ; new rtl's. this is more flexible. the pattern below helps when we're
3168 ; not using relaxed immediates. BRC
3171 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
3172 ; (match_operand:SI 1 "const_int_operand" ""))
3173 ; (set (match_operand:SI 2 "mcore_arith_reg_operand" "")
3174 ; (and:SI (match_dup 2) (match_dup 0)))
3175 ; (set (match_dup 0)
3176 ; (match_operand:SI 3 "const_int_operand" ""))
3177 ; (set (match_dup 2)
3178 ; (and:SI (match_dup 2) (match_dup 0)))]
3179 ; "!TARGET_RELAX_IMM && mcore_is_dead (insn, operands[0]) &&
3180 ; mcore_const_ok_for_inline (INTVAL (operands[1]) & INTVAL (operands[3]))"
3183 ; rtx out_operands[2];
3184 ; out_operands[0] = operands[0];
3185 ; out_operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[3]));
3187 ; output_inline_const (SImode, out_operands);
3189 ; output_asm_insn (\"and %2,%0\", operands);
3194 ; BRC: for inlining get rid of extra test - experimental
3196 ; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "r")
3197 ; (ne:SI (reg:CC 17) (const_int 0)))
3198 ; (set (reg:CC 17) (ne:CC (match_dup 0) (const_int 0)))
3200 ; (if_then_else (eq (reg:CC 17) (const_int 0))
3201 ; (label_ref (match_operand 1 "" ""))
3206 ; if (get_attr_length (insn) == 10)
3208 ; output_asm_insn (\"bt 2f\\n\\tjmpi [1f]\", operands);
3209 ; output_asm_insn (\".align 2\\n1:\", operands);
3210 ; output_asm_insn (\".long %1\\n2:\", operands);
3213 ; return \"bf %l1\";
3217 ;;; Special patterns for dealing with the constant pool.
3219 ;;; 4 byte integer in line.
3221 (define_insn "consttable_4"
3222 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 0)]
3226 assemble_integer (operands[0], 4, BITS_PER_WORD, 1);
3229 [(set_attr "length" "4")])
3231 ;;; align to a four byte boundary.
3233 (define_insn "align_4"
3234 [(unspec_volatile [(const_int 0)] 1)]
3238 ;;; Handle extra constant pool entries created during final pass.
3240 (define_insn "consttable_end"
3241 [(unspec_volatile [(const_int 0)] 2)]
3243 "* return mcore_output_jump_label_table ();")
3246 ;; Stack allocation -- in particular, for alloca().
3247 ;; this is *not* what we use for entry into functions.
3249 ;; This is how we allocate stack space. If we are allocating a
3250 ;; constant amount of space and we know it is less than 4096
3251 ;; bytes, we need do nothing.
3253 ;; If it is more than 4096 bytes, we need to probe the stack
3256 ;; operands[1], the distance is a POSITIVE number indicating that we
3257 ;; are allocating stack space
3259 (define_expand "allocate_stack"
3262 (match_operand:SI 1 "general_operand" "")))
3263 (set (match_operand:SI 0 "register_operand" "=r")
3268 /* If he wants no probing, just do it for him. */
3269 if (mcore_stack_increment == 0)
3271 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,operands[1]));
3272 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3276 /* For small constant growth, we unroll the code. */
3277 if (GET_CODE (operands[1]) == CONST_INT
3278 && INTVAL (operands[1]) < 8 * STACK_UNITS_MAXSTEP)
3280 int left = INTVAL(operands[1]);
3282 /* If it's a long way, get close enough for a last shot. */
3283 if (left >= STACK_UNITS_MAXSTEP)
3285 rtx tmp = gen_reg_rtx (Pmode);
3286 emit_insn (gen_movsi (tmp, GEN_INT (STACK_UNITS_MAXSTEP)));
3289 rtx memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
3291 MEM_VOLATILE_P (memref) = 1;
3292 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3293 emit_insn (gen_movsi (memref, stack_pointer_rtx));
3294 left -= STACK_UNITS_MAXSTEP;
3296 while (left > STACK_UNITS_MAXSTEP);
3298 /* Perform the final adjustment. */
3299 emit_insn (gen_addsi3 (stack_pointer_rtx,stack_pointer_rtx,GEN_INT(-left)));
3300 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3306 rtx loop_label = gen_label_rtx ();
3307 rtx step = gen_reg_rtx (Pmode);
3308 rtx tmp = gen_reg_rtx (Pmode);
3312 emit_insn (gen_movsi (tmp, operands[1]));
3313 emit_insn (gen_movsi (step, GEN_INT(STACK_UNITS_MAXSTEP)));
3315 if (GET_CODE (operands[1]) != CONST_INT)
3317 out_label = gen_label_rtx ();
3318 emit_insn (gen_cmpsi (step, tmp)); /* quick out */
3319 emit_jump_insn (gen_bgeu (out_label));
3322 /* Run a loop that steps it incrementally. */
3323 emit_label (loop_label);
3325 /* Extend a step, probe, and adjust remaining count. */
3326 emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx, step));
3327 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
3328 MEM_VOLATILE_P (memref) = 1;
3329 emit_insn(gen_movsi(memref, stack_pointer_rtx));
3330 emit_insn(gen_subsi3(tmp, tmp, step));
3332 /* Loop condition -- going back up. */
3333 emit_insn (gen_cmpsi (step, tmp));
3334 emit_jump_insn (gen_bltu (loop_label));
3337 emit_label (out_label);
3339 /* Bump the residual. */
3340 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3341 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
3344 /* simple one-shot -- ensure register and do a subtract.
3345 * This does NOT comply with the ABI. */
3346 emit_insn (gen_movsi (tmp, operands[1]));
3347 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
3348 ;; emit_move_insn (operands[0], virtual_stack_dynamic_rtx);