gcc/ira.h

   1 /* Communication between the Integrated Register Allocator (IRA) and
   2    the rest of the compiler.
   3    Copyright (C) 2006-2017 Free Software Foundation, Inc.
   4    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_IRA_H
  23 #define GCC_IRA_H
  24
  25 #include "emit-rtl.h"
  26
  27 /* True when we use LRA instead of reload pass for the current
  28    function.  */
  29 extern bool ira_use_lra_p;
  30
  31 /* True if we have allocno conflicts.  It is false for non-optimized
  32    mode or when the conflict table is too big.  */
  33 extern bool ira_conflicts_p;
  34
  35 struct target_ira
  36 {
  37   /* Map: hard register number -> allocno class it belongs to.  If the
  38      corresponding class is NO_REGS, the hard register is not available
  39      for allocation.  */
  40   enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
  41
  42   /* Number of allocno classes.  Allocno classes are register classes
  43      which can be used for allocations of allocnos.  */
  44   int x_ira_allocno_classes_num;
  45
  46   /* The array containing allocno classes.  Only first
  47      IRA_ALLOCNO_CLASSES_NUM elements are used for this.  */
  48   enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
  49
  50   /* Map of all register classes to corresponding allocno classes
  51      containing the given class.  If given class is not a subset of an
  52      allocno class, we translate it into the cheapest allocno class.  */
  53   enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
  54
  55   /* Number of pressure classes.  Pressure classes are register
  56      classes for which we calculate register pressure.  */
  57   int x_ira_pressure_classes_num;
  58
  59   /* The array containing pressure classes.  Only first
  60      IRA_PRESSURE_CLASSES_NUM elements are used for this.  */
  61   enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
  62
  63   /* Map of all register classes to corresponding pressure classes
  64      containing the given class.  If given class is not a subset of an
  65      pressure class, we translate it into the cheapest pressure
  66      class.  */
  67   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
  68
  69   /* Biggest pressure register class containing stack registers.
  70      NO_REGS if there are no stack registers.  */
  71   enum reg_class x_ira_stack_reg_pressure_class;
  72
  73   /* Maps: register class x machine mode -> maximal/minimal number of
  74      hard registers of given class needed to store value of given
  75      mode.  */
  76   unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  77   unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  78
  79   /* Array analogous to target hook TARGET_MEMORY_MOVE_COST.  */
  80   short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
  81
  82   /* Array of number of hard registers of given class which are
  83      available for the allocation.  The order is defined by the
  84      allocation order.  */
  85   short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
  86
  87   /* The number of elements of the above array for given register
  88      class.  */
  89   int x_ira_class_hard_regs_num[N_REG_CLASSES];
  90
  91   /* Register class subset relation: TRUE if the first class is a subset
  92      of the second one considering only hard registers available for the
  93      allocation.  */
  94   int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
  95
  96   /* The biggest class inside of intersection of the two classes (that
  97      is calculated taking only hard registers available for allocation
  98      into account.  If the both classes contain no hard registers
  99      available for allocation, the value is calculated with taking all
 100      hard-registers including fixed ones into account.  */
 101   enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
 102
 103   /* True if the two classes (that is calculated taking only hard
 104      registers available for allocation into account; are
 105      intersected.  */
 106   bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
 107
 108   /* If class CL has a single allocatable register of mode M,
 109      index [CL][M] gives the number of that register, otherwise it is -1.  */
 110   short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
 111
 112   /* Function specific hard registers can not be used for the register
 113      allocation.  */
 114   HARD_REG_SET x_ira_no_alloc_regs;
 115
 116   /* Array whose values are hard regset of hard registers available for
 117      the allocation of given register class whose HARD_REGNO_MODE_OK
 118      values for given mode are zero.  */
 119   HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
 120 };
 121
 122 extern struct target_ira default_target_ira;
 123 #if SWITCHABLE_TARGET
 124 extern struct target_ira *this_target_ira;
 125 #else
 126 #define this_target_ira (&default_target_ira)
 127 #endif
 128
 129 #define ira_hard_regno_allocno_class \
 130   (this_target_ira->x_ira_hard_regno_allocno_class)
 131 #define ira_allocno_classes_num \
 132   (this_target_ira->x_ira_allocno_classes_num)
 133 #define ira_allocno_classes \
 134   (this_target_ira->x_ira_allocno_classes)
 135 #define ira_allocno_class_translate \
 136   (this_target_ira->x_ira_allocno_class_translate)
 137 #define ira_pressure_classes_num \
 138   (this_target_ira->x_ira_pressure_classes_num)
 139 #define ira_pressure_classes \
 140   (this_target_ira->x_ira_pressure_classes)
 141 #define ira_pressure_class_translate \
 142   (this_target_ira->x_ira_pressure_class_translate)
 143 #define ira_stack_reg_pressure_class \
 144   (this_target_ira->x_ira_stack_reg_pressure_class)
 145 #define ira_reg_class_max_nregs \
 146   (this_target_ira->x_ira_reg_class_max_nregs)
 147 #define ira_reg_class_min_nregs \
 148   (this_target_ira->x_ira_reg_class_min_nregs)
 149 #define ira_memory_move_cost \
 150   (this_target_ira->x_ira_memory_move_cost)
 151 #define ira_class_hard_regs \
 152   (this_target_ira->x_ira_class_hard_regs)
 153 #define ira_class_hard_regs_num \
 154   (this_target_ira->x_ira_class_hard_regs_num)
 155 #define ira_class_subset_p \
 156   (this_target_ira->x_ira_class_subset_p)
 157 #define ira_reg_class_subset \
 158   (this_target_ira->x_ira_reg_class_subset)
 159 #define ira_reg_classes_intersect_p \
 160   (this_target_ira->x_ira_reg_classes_intersect_p)
 161 #define ira_class_singleton \
 162   (this_target_ira->x_ira_class_singleton)
 163 #define ira_no_alloc_regs \
 164   (this_target_ira->x_ira_no_alloc_regs)
 165 #define ira_prohibited_class_mode_regs \
 166   (this_target_ira->x_ira_prohibited_class_mode_regs)
 167
 168 /* Major structure describing equivalence info for a pseudo.  */
 169 struct ira_reg_equiv_s
 170 {
 171   /* True if we can use this equivalence.  */
 172   bool defined_p;
 173   /* True if the usage of the equivalence is profitable.  */
 174   bool profitable_p;
 175   /* Equiv. memory, constant, invariant, and initializing insns of
 176      given pseudo-register or NULL_RTX.  */
 177   rtx memory;
 178   rtx constant;
 179   rtx invariant;
 180   /* Always NULL_RTX if defined_p is false.  */
 181   rtx_insn_list *init_insns;
 182 };
 183
 184 /* The length of the following array.  */
 185 extern int ira_reg_equiv_len;
 186
 187 /* Info about equiv. info for each register.  */
 188 extern struct ira_reg_equiv_s *ira_reg_equiv;
 189
 190 extern void ira_init_once (void);
 191 extern void ira_init (void);
 192 extern void ira_setup_eliminable_regset (void);
 193 extern rtx ira_eliminate_regs (rtx, machine_mode);
 194 extern void ira_set_pseudo_classes (bool, FILE *);
 195 extern void ira_expand_reg_equiv (void);
 196 extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
 197
 198 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);
 199 extern void ira_mark_allocation_change (int);
 200 extern void ira_mark_memory_move_deletion (int, int);
 201 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
 202                                   HARD_REG_SET *, bitmap);
 203 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
 204 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
 205 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx_insn *);
 206 extern bool ira_bad_reload_regno (int, rtx, rtx);
 207
 208 extern void ira_adjust_equiv_reg_cost (unsigned, int);
 209
 210 /* ira-costs.c */
 211 extern void ira_costs_c_finalize (void);
 212
 213 /* Spilling static chain pseudo may result in generation of wrong
 214    non-local goto code using frame-pointer to address saved stack
 215    pointer value after restoring old frame pointer value.  The
 216    function returns TRUE if REGNO is such a static chain pseudo.  */
 217 static inline bool
 218 non_spilled_static_chain_regno_p (int regno)
 219 {
 220   return (cfun->static_chain_decl && crtl->has_nonlocal_goto
 221           && REG_EXPR (regno_reg_rtx[regno]) == cfun->static_chain_decl);
 222 }
 223
 224 #endif /* GCC_IRA_H */