| blob | 737ec89689350990df8866f8199b9553b544a874 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshhold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
252 #if 0
254 #endif
284 rtx *));
368 {
369 rtx match;
370 rtx replacement;
371 rtx insn;
374 /* Nonzero iff INSN is between START and END, inclusive. */
375 #define INSN_IN_RANGE_P(INSN, START, END) \
376 (INSN_UID (INSN) < max_uid_for_loop \
377 && INSN_LUID (INSN) >= INSN_LUID (START) \
378 && INSN_LUID (INSN) <= INSN_LUID (END))
380 /* Indirect_jump_in_function is computed once per function. */
388 rtx));
389 \f
390 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
391 copy the value of the strength reduced giv to its original register. */
394 /* Cost of using a register, to normalize the benefits of a giv. */
397 void
399 {
405 }
406 \f
407 /* Compute the mapping from uids to luids.
408 LUIDs are numbers assigned to insns, like uids,
409 except that luids increase monotonically through the code.
410 Start at insn START and stop just before END. Assign LUIDs
411 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
412 static int
416 {
418 rtx insn;
421 {
424 /* Don't assign luids to line-number NOTEs, so that the distance in
425 luids between two insns is not affected by -g. */
429 else
430 /* Give a line number note the same luid as preceding insn. */
432 }
434 }
435 \f
436 /* Entry point of this file. Perform loop optimization
437 on the current function. F is the first insn of the function
438 and DUMPFILE is a stream for output of a trace of actions taken
439 (or 0 if none should be output). */
441 void
443 /* f is the first instruction of a chain of insns for one function */
444 rtx f;
447 {
448 rtx insn;
463 /* Count the number of loops. */
467 {
470 max_loop_num++;
471 }
473 /* Don't waste time if no loops. */
479 /* Get size to use for tables indexed by uids.
480 Leave some space for labels allocated by find_and_verify_loops. */
487 /* Allocate storage for array of loops. */
491 /* Find and process each loop.
492 First, find them, and record them in order of their beginnings. */
495 /* Allocate and initialize auxiliary loop information. */
500 /* Now find all register lifetimes. This must be done after
501 find_and_verify_loops, because it might reorder the insns in the
502 function. */
505 /* This must occur after reg_scan so that registers created by gcse
506 will have entries in the register tables.
508 We could have added a call to reg_scan after gcse_main in toplev.c,
509 but moving this call to init_alias_analysis is more efficient. */
512 /* See if we went too far. Note that get_max_uid already returns
513 one more that the maximum uid of all insn. */
516 /* Now reset it to the actual size we need. See above. */
519 /* find_and_verify_loops has already called compute_luids, but it
520 might have rearranged code afterwards, so we need to recompute
521 the luids now. */
524 /* Don't leave gaps in uid_luid for insns that have been
525 deleted. It is possible that the first or last insn
526 using some register has been deleted by cross-jumping.
527 Make sure that uid_luid for that former insn's uid
528 points to the general area where that insn used to be. */
530 {
534 }
539 /* Determine if the function has indirect jump. On some systems
540 this prevents low overhead loop instructions from being used. */
543 /* Now scan the loops, last ones first, since this means inner ones are done
544 before outer ones. */
546 {
551 }
555 /* Clean up. */
560 }
561 \f
562 /* Returns the next insn, in execution order, after INSN. START and
563 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
564 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
565 insn-stream; it is used with loops that are entered near the
566 bottom. */
568 static rtx
571 rtx insn;
572 {
576 {
578 /* Go to the top of the loop, and continue there. */
580 else
581 /* We're done. */
583 }
586 /* We're done. */
590 }
592 /* Optimize one loop described by LOOP. */
594 /* ??? Could also move memory writes out of loops if the destination address
595 is invariant, the source is invariant, the memory write is not volatile,
596 and if we can prove that no read inside the loop can read this address
597 before the write occurs. If there is a read of this address after the
598 write, then we can also mark the memory read as invariant. */
600 static void
604 {
610 rtx p;
611 /* 1 if we are scanning insns that could be executed zero times. */
613 /* 1 if we are scanning insns that might never be executed
614 due to a subroutine call which might exit before they are reached. */
616 /* Number of insns in the loop. */
620 /* The SET from an insn, if it is the only SET in the insn. */
622 /* Chain describing insns movable in current loop. */
624 /* Ratio of extra register life span we can justify
625 for saving an instruction. More if loop doesn't call subroutines
626 since in that case saving an insn makes more difference
627 and more registers are available. */
629 /* Nonzero if we are scanning instructions in a sub-loop. */
638 /* Determine whether this loop starts with a jump down to a test at
639 the end. This will occur for a small number of loops with a test
640 that is too complex to duplicate in front of the loop.
642 We search for the first insn or label in the loop, skipping NOTEs.
643 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
644 (because we might have a loop executed only once that contains a
645 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
646 (in case we have a degenerate loop).
648 Note that if we mistakenly think that a loop is entered at the top
649 when, in fact, it is entered at the exit test, the only effect will be
650 slightly poorer optimization. Making the opposite error can generate
651 incorrect code. Since very few loops now start with a jump to the
652 exit test, the code here to detect that case is very conservative. */
655 p != loop_end
661 ;
665 /* If loop end is the end of the current function, then emit a
666 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
667 note insn. This is the position we use when sinking insns out of
668 the loop. */
671 else
674 /* Set up variables describing this loop. */
678 /* If loop has a jump before the first label,
679 the true entry is the target of that jump.
680 Start scan from there.
681 But record in LOOP->TOP the place where the end-test jumps
682 back to so we can scan that after the end of the loop. */
684 /* Loop entry must be unconditional jump (and not a RETURN) */
687 /* Check to see whether the jump actually
688 jumps out of the loop (meaning it's no loop).
689 This case can happen for things like
690 do {..} while (0). If this label was generated previously
691 by loop, we can't tell anything about it and have to reject
692 the loop. */
694 {
697 }
699 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
700 as required by loop_reg_used_before_p. So skip such loops. (This
701 test may never be true, but it's best to play it safe.)
703 Also, skip loops where we do not start scanning at a label. This
704 test also rejects loops starting with a JUMP_INSN that failed the
705 test above. */
709 {
714 }
716 /* Allocate extra space for REGs that might be created by load_mems.
717 We allocate a little extra slop as well, in the hopes that we
718 won't have to reallocate the regs array. */
723 {
729 }
731 /* Scan through the loop finding insns that are safe to move.
732 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
733 this reg will be considered invariant for subsequent insns.
734 We consider whether subsequent insns use the reg
735 in deciding whether it is worth actually moving.
737 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
738 and therefore it is possible that the insns we are scanning
739 would never be executed. At such times, we must make sure
740 that it is safe to execute the insn once instead of zero times.
741 When MAYBE_NEVER is 0, all insns will be executed at least once
742 so that is not a problem. */
747 {
749 in_libcall--;
751 {
754 in_libcall++;
758 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
760 #endif
762 {
770 /* Figure out what to use as a source of this insn. If a
771 REG_EQUIV note is given or if a REG_EQUAL note with a
772 constant operand is specified, use it as the source and
773 mark that we should move this insn by calling
774 emit_move_insn rather that duplicating the insn.
776 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
777 note is present. */
781 else
782 {
787 {
789 /* A libcall block can use regs that don't appear in
790 the equivalent expression. To move the libcall,
791 we must move those regs too. */
793 }
794 }
796 /* For parallels, add any possible uses to the dependencies, as
797 we can't move the insn without resolving them first. */
799 {
801 {
804 dependencies
806 dependencies);
807 }
808 }
811 than the one where it is set (meaning that
812 something after this point in the loop might
813 depend on its value before the set). */
815 /* And the set is not guaranteed to be executed once
816 the loop starts, or the value before the set is
817 needed before the set occurs...
819 ??? Note we have quadratic behavior here, mitigated
820 by the fact that the previous test will often fail for
821 large loops. Rather than re-scanning the entire loop
822 each time for register usage, we should build tables
823 of the register usage and use them here instead. */
824 && (maybe_never
826 /* It is unsafe to move the set. However, it may be OK to
827 move the source into a new pseudo, and substitute a
828 reg-to-reg copy for the original insn.
830 This code used to consider it OK to move a set of a variable
831 which was not created by the user and not used in an exit
832 test.
833 That behavior is incorrect and was removed. */
836 /* Don't try to optimize a MODE_CC set with a constant
837 source. It probably will be combined with a conditional
838 jump. */
841 ;
842 /* Don't try to optimize a register that was made
843 by loop-optimization for an inner loop.
844 We don't know its life-span, so we can't compute
845 the benefit. */
847 ;
848 /* Don't move the source and add a reg-to-reg copy:
849 - with -Os (this certainly increases size),
850 - if the mode doesn't support copy operations (obviously),
851 - if the source is already a reg (the motion will gain nothing),
852 - if the source is a legitimate constant (likewise). */
854 && (optimize_size
859 ;
862 || (tem2
865 || (tem1
866 = consec_sets_invariant_p
869 p)))
870 /* If the insn can cause a trap (such as divide by zero),
871 can't move it unless it's guaranteed to be executed
872 once loop is entered. Even a function call might
873 prevent the trap insn from being reached
874 (since it might exit!) */
877 {
881 /* A potential lossage is where we have a case where two insns
882 can be combined as long as they are both in the loop, but
883 we move one of them outside the loop. For large loops,
884 this can lose. The most common case of this is the address
885 of a function being called.
887 Therefore, if this register is marked as being used
888 exactly once if we are in a loop with calls
889 (a "large loop"), see if we can replace the usage of
890 this register with the source of this SET. If we can,
891 delete this insn.
893 Don't do this if P has a REG_RETVAL note or if we have
894 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
906 && (! SMALL_REGISTER_CLASSES
910 /* This test is not redundant; SET_SRC (set) might be
911 a call-clobbered register and the life of REGNO
912 might span a call. */
919 {
920 /* Replace any usage in a REG_EQUAL note. Must copy
921 the new source, so that we don't get rtx sharing
922 between the SET_SOURCE and REG_NOTES of insn p. */
924 = (replace_rtx
930 i++)
933 }
942 m->consec
953 /* Set M->cond if either loop_invariant_p
954 or consec_sets_invariant_p returned 2
955 (only conditionally invariant). */
965 /* Add M to the end of the chain MOVABLES. */
969 {
970 /* It is possible for the first instruction to have a
971 REG_EQUAL note but a non-invariant SET_SRC, so we must
972 remember the status of the first instruction in case
973 the last instruction doesn't have a REG_EQUAL note. */
976 /* Skip this insn, not checking REG_LIBCALL notes. */
978 /* Skip the consecutive insns, if there are any. */
980 /* Back up to the last insn of the consecutive group. */
983 /* We must now reset m->move_insn, m->is_equiv, and
984 possibly m->set_src to correspond to the effects of
985 all the insns. */
989 else
990 {
994 else
997 }
998 m->is_equiv
1000 }
1001 }
1002 /* If this register is always set within a STRICT_LOW_PART
1003 or set to zero, then its high bytes are constant.
1004 So clear them outside the loop and within the loop
1005 just load the low bytes.
1006 We must check that the machine has an instruction to do so.
1007 Also, if the value loaded into the register
1008 depends on the same register, this cannot be done. */
1018 {
1021 {
1036 /* If the insn may not be executed on some cycles,
1037 we can't clear the whole reg; clear just high part.
1038 Not even if the reg is used only within this loop.
1039 Consider this:
1040 while (1)
1041 while (s != t) {
1042 if (foo ()) x = *s;
1043 use (x);
1044 }
1045 Clearing x before the inner loop could clobber a value
1046 being saved from the last time around the outer loop.
1047 However, if the reg is not used outside this loop
1048 and all uses of the register are in the same
1049 basic block as the store, there is no problem.
1051 If this insn was made by loop, we don't know its
1052 INSN_LUID and hence must make a conservative
1053 assumption. */
1056 || (labels_in_range_p
1060 else
1069 i++)
1071 /* Add M to the end of the chain MOVABLES. */
1073 }
1074 }
1075 }
1076 }
1077 /* Past a call insn, we get to insns which might not be executed
1078 because the call might exit. This matters for insns that trap.
1079 Constant and pure call insns always return, so they don't count. */
1082 /* Past a label or a jump, we get to insns for which we
1083 can't count on whether or how many times they will be
1084 executed during each iteration. Therefore, we can
1085 only move out sets of trivial variables
1086 (those not used after the loop). */
1087 /* Similar code appears twice in strength_reduce. */
1089 /* If we enter the loop in the middle, and scan around to the
1090 beginning, don't set maybe_never for that. This must be an
1091 unconditional jump, otherwise the code at the top of the
1092 loop might never be executed. Unconditional jumps are
1093 followed by a barrier then the loop_end. */
1099 {
1100 /* At the virtual top of a converted loop, insns are again known to
1101 be executed: logically, the loop begins here even though the exit
1102 code has been duplicated. */
1106 loop_depth++;
1108 loop_depth--;
1109 }
1110 }
1112 /* If one movable subsumes another, ignore that other. */
1116 /* For each movable insn, see if the reg that it loads
1117 leads when it dies right into another conditionally movable insn.
1118 If so, record that the second insn "forces" the first one,
1119 since the second can be moved only if the first is. */
1123 /* See if there are multiple movable insns that load the same value.
1124 If there are, make all but the first point at the first one
1125 through the `match' field, and add the priorities of them
1126 all together as the priority of the first. */
1130 /* Now consider each movable insn to decide whether it is worth moving.
1131 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1133 For machines with few registers this increases code size, so do not
1134 move moveables when optimizing for code size on such machines.
1135 (The 18 below is the value for i386.) */
1139 {
1142 /* Recalculate regs->array if move_movables has created new
1143 registers. */
1145 {
1151 ;
1156 }
1157 }
1159 /* Now candidates that still are negative are those not moved.
1160 Change regs->array[I].set_in_loop to indicate that those are not actually
1161 invariant. */
1166 /* Now that we've moved some things out of the loop, we might be able to
1167 hoist even more memory references. */
1170 /* Recalculate regs->array if load_mems has created new registers. */
1178 ;
1185 {
1187 /* Ensure our label doesn't go away. */
1198 }
1201 /* The movable information is required for strength reduction. */
1207 }
1208 \f
1209 /* Add elements to *OUTPUT to record all the pseudo-regs
1210 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1212 void
1216 {
1224 {
1242 }
1246 {
1250 {
1259 }
1260 }
1261 }
1262 \f
1263 /* Check what regs are referred to in the libcall block ending with INSN,
1264 aside from those mentioned in the equivalent value.
1265 If there are none, return 0.
1266 If there are one or more, return an EXPR_LIST containing all of them. */
1268 rtx
1271 {
1276 /* First, find all the regs used in the libcall block
1277 that are not mentioned as inputs to the result. */
1280 {
1285 }
1288 }
1289 \f
1290 /* Return 1 if all uses of REG
1291 are between INSN and the end of the basic block. */
1293 static int
1296 {
1298 rtx p;
1303 /* Search this basic block for the already recorded last use of the reg. */
1305 {
1307 {
1313 /* Ordinary insn: if this is the last use, we win. */
1319 /* Jump insn: if this is the last use, we win. */
1322 /* Otherwise, it's the end of the basic block, so we lose. */
1327 /* It's the end of the basic block, so we lose. */
1332 }
1333 }
1335 /* The "last use" that was recorded can't be found after the first
1336 use. This can happen when the last use was deleted while
1337 processing an inner loop, this inner loop was then completely
1338 unrolled, and the outer loop is always exited after the inner loop,
1339 so that everything after the first use becomes a single basic block. */
1341 }
1342 \f
1343 /* Compute the benefit of eliminating the insns in the block whose
1344 last insn is LAST. This may be a group of insns used to compute a
1345 value directly or can contain a library call. */
1347 static int
1349 rtx last;
1350 {
1351 rtx insn;
1356 {
1359 routine. */
1363 benefit++;
1364 }
1367 }
1368 \f
1369 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1371 static rtx
1373 rtx insn;
1375 {
1377 {
1378 rtx temp;
1380 /* If first insn of libcall sequence, skip to end. */
1381 /* Do this at start of loop, since INSN is guaranteed to
1382 be an insn here. */
1387 do
1390 }
1393 }
1395 /* Ignore any movable whose insn falls within a libcall
1396 which is part of another movable.
1397 We make use of the fact that the movable for the libcall value
1398 was made later and so appears later on the chain. */
1400 static void
1403 {
1407 {
1408 /* Is this a movable for the value of a libcall? */
1411 {
1412 rtx insn;
1413 /* Check for earlier movables inside that range,
1414 and mark them invalid. We cannot use LUIDs here because
1415 insns created by loop.c for prior loops don't have LUIDs.
1416 Rather than reject all such insns from movables, we just
1417 explicitly check each insn in the libcall (since invariant
1418 libcalls aren't that common). */
1423 }
1424 }
1425 }
1427 /* For each movable insn, see if the reg that it loads
1428 leads when it dies right into another conditionally movable insn.
1429 If so, record that the second insn "forces" the first one,
1430 since the second can be moved only if the first is. */
1432 static void
1435 {
1439 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1441 {
1444 /* ??? Could this be a bug? What if CSE caused the
1445 register of M1 to be used after this insn?
1446 Since CSE does not update regno_last_uid,
1447 this insn M->insn might not be where it dies.
1448 But very likely this doesn't matter; what matters is
1449 that M's reg is computed from M1's reg. */
1454 /* If m->consec, m->set_src isn't valid. */
1458 /* Increase the priority of the moving the first insn
1459 since it permits the second to be moved as well. */
1461 {
1465 }
1466 }
1467 }
1468 \f
1469 /* Find invariant expressions that are equal and can be combined into
1470 one register. */
1472 static void
1476 {
1481 /* Regs that are set more than once are not allowed to match
1482 or be matched. I'm no longer sure why not. */
1483 /* Only pseudo registers are allowed to match or be matched,
1484 since move_movables does not validate the change. */
1485 /* Perhaps testing m->consec_sets would be more appropriate here? */
1492 {
1499 /* We want later insns to match the first one. Don't make the first
1500 one match any later ones. So start this loop at m->next. */
1506 /* A reg used outside the loop mustn't be eliminated. */
1508 /* A reg used for zero-extending mustn't be eliminated. */
1511 ||
1512 (
1513 /* Can combine regs with different modes loaded from the
1514 same constant only if the modes are the same or
1515 if both are integer modes with M wider or the same
1516 width as M1. The check for integer is redundant, but
1517 safe, since the only case of differing destination
1518 modes with equal sources is when both sources are
1519 VOIDmode, i.e., CONST_INT. */
1525 /* See if the source of M1 says it matches M. */
1532 {
1538 }
1539 }
1541 /* Now combine the regs used for zero-extension.
1542 This can be done for those not marked `global'
1543 provided their lives don't overlap. */
1547 {
1550 /* Combine all the registers for extension from mode MODE.
1551 Don't combine any that are used outside this loop. */
1555 {
1562 {
1563 /* First one: don't check for overlap, just record it. */
1566 }
1568 /* Make sure they extend to the same mode.
1569 (Almost always true.) */
1573 /* We already have one: check for overlap with those
1574 already combined together. */
1581 /* No overlap: we can combine this with the others. */
1587 overlap:
1588 ;
1589 }
1590 }
1592 /* Clean up. */
1594 }
1596 /* Returns the number of movable instructions in LOOP that were not
1597 moved outside the loop. */
1599 static int
1602 {
1611 }
1613 \f
1614 /* Return 1 if regs X and Y will become the same if moved. */
1616 static int
1620 {
1637 }
1639 /* Return 1 if X and Y are identical-looking rtx's.
1640 This is the Lisp function EQUAL for rtx arguments.
1642 If two registers are matching movables or a movable register and an
1643 equivalent constant, consider them equal. */
1645 static int
1650 {
1664 /* If we have a register and a constant, they may sometimes be
1665 equal. */
1668 {
1673 }
1676 {
1681 }
1683 /* Otherwise, rtx's of different codes cannot be equal. */
1687 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1688 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1693 /* These three types of rtx's can be compared nonrecursively. */
1702 /* Compare the elements. If any pair of corresponding elements
1703 fail to match, return 0 for the whole things. */
1707 {
1709 {
1721 /* Two vectors must have the same length. */
1725 /* And the corresponding elements must match. */
1744 /* These are just backpointers, so they don't matter. */
1750 /* It is believed that rtx's at this level will never
1751 contain anything but integers and other rtx's,
1752 except for within LABEL_REFs and SYMBOL_REFs. */
1755 }
1756 }
1758 }
1759 \f
1760 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1761 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1762 references is incremented once for each added note. */
1764 static void
1766 rtx x;
1767 rtx insns;
1768 {
1772 rtx insn;
1775 {
1776 /* This code used to ignore labels that referred to dispatch tables to
1777 avoid flow generating (slighly) worse code.
1779 We no longer ignore such label references (see LABEL_REF handling in
1780 mark_jump_label for additional information). */
1783 {
1788 }
1789 }
1793 {
1799 }
1800 }
1801 \f
1802 /* Scan MOVABLES, and move the insns that deserve to be moved.
1803 If two matching movables are combined, replace one reg with the
1804 other throughout. */
1806 static void
1812 {
1817 rtx p;
1820 /* Map of pseudo-register replacements to handle combining
1821 when we move several insns that load the same value
1822 into different pseudo-registers. */
1827 {
1828 /* Describe this movable insn. */
1831 {
1852 }
1854 /* Ignore the insn if it's already done (it matched something else).
1855 Otherwise, see if it is now safe to move. */
1867 {
1869 rtx p;
1872 /* We have an insn that is safe to move.
1873 Compute its desirability. */
1884 /* An insn MUST be moved if we already moved something else
1885 which is safe only if this one is moved too: that is,
1886 if already_moved[REGNO] is nonzero. */
1888 /* An insn is desirable to move if the new lifetime of the
1889 register is no more than THRESHOLD times the old lifetime.
1890 If it's not desirable, it means the loop is so big
1891 that moving won't speed things up much,
1892 and it is liable to make register usage worse. */
1894 /* It is also desirable to move if it can be moved at no
1895 extra cost because something else was already moved. */
1898 || flag_move_all_movables
1903 {
1912 /* Now move the insns that set the reg. */
1915 {
1918 /* Find the end of this chain of matching regs.
1919 Thus, we load each reg in the chain from that one reg.
1920 And that reg is loaded with 0 directly,
1921 since it has ->match == 0. */
1927 /* Mark the moved, invariant reg as being allowed to
1928 share a hard reg with the other matching invariant. */
1932 regs_may_share
1935 regs_may_share));
1943 }
1944 /* If we are to re-generate the item being moved with a
1945 new move insn, first delete what we have and then emit
1946 the move insn before the loop. */
1948 {
1952 {
1953 /* If this is the first insn of a library call sequence,
1954 something is very wrong. */
1959 /* If this is the last insn of a libcall sequence, then
1960 delete every insn in the sequence except the last.
1961 The last insn is handled in the normal manner. */
1964 {
1968 }
1973 /* simplify_giv_expr expects that it can walk the insns
1974 at m->insn forwards and see this old sequence we are
1975 tossing here. delete_insn does preserve the next
1976 pointers, but when we skip over a NOTE we must fix
1977 it up. Otherwise that code walks into the non-deleted
1978 insn stream. */
1983 {
1984 /* Replace the original insn with a move from
1985 our newly created temp. */
1991 }
1992 }
2011 /* The more regs we move, the less we like moving them. */
2013 }
2014 else
2015 {
2017 {
2020 /* If first insn of libcall sequence, skip to end. */
2021 /* Do this at start of loop, since p is guaranteed to
2022 be an insn here. */
2027 /* If last insn of libcall sequence, move all
2028 insns except the last before the loop. The last
2029 insn is handled in the normal manner. */
2032 {
2040 {
2041 rtx body;
2042 rtx n;
2043 rtx next;
2050 /* Find the next insn after TEMP,
2051 not counting USE or NOTE insns. */
2059 /* If that is the call, this may be the insn
2060 that loads the function address.
2062 Extract the function address from the insn
2063 that loads it into a register.
2064 If this insn was cse'd, we get incorrect code.
2066 So emit a new move insn that copies the
2067 function address into the register that the
2068 call insn will use. flow.c will delete any
2069 redundant stores that we have created. */
2074 NULL_RTX)))
2075 {
2081 }
2082 /* We have the call insn.
2083 If it uses the register we suspect it might,
2084 load it with the correct address directly. */
2089 gen_move_insn
2093 {
2095 /* Because the USAGE information potentially
2096 contains objects other than hard registers
2097 we need to copy it. */
2101 }
2102 else
2111 }
2114 }
2116 {
2117 /* P sets REG to zero; but we should clear only
2118 the bits that are not covered by the mode
2119 m->savemode. */
2121 rtx sequence;
2122 rtx tem;
2125 tem = expand_simple_binop
2138 }
2140 {
2142 /* Because the USAGE information potentially
2143 contains objects other than hard registers
2144 we need to copy it. */
2148 }
2150 {
2151 rtx seq;
2152 /* The SET_SRC might not be invariant, so we must
2153 use the REG_EQUAL note. */
2165 }
2167 {
2175 }
2176 else
2180 {
2184 /* If there is a REG_EQUAL note present whose value
2185 is not loop invariant, then delete it, since it
2186 may cause problems with later optimization passes.
2187 It is possible for cse to create such notes
2188 like this as a result of record_jump_cond. */
2193 }
2202 /* If library call, now fix the REG_NOTES that contain
2203 insn pointers, namely REG_LIBCALL on FIRST
2204 and REG_RETVAL on I1. */
2206 {
2210 }
2216 /* simplify_giv_expr expects that it can walk the insns
2217 at m->insn forwards and see this old sequence we are
2218 tossing here. delete_insn does preserve the next
2219 pointers, but when we skip over a NOTE we must fix
2220 it up. Otherwise that code walks into the non-deleted
2221 insn stream. */
2226 {
2227 rtx seq;
2228 /* Replace the original insn with a move from
2229 our newly created temp. */
2235 }
2236 }
2238 /* The more regs we move, the less we like moving them. */
2240 }
2245 {
2246 /* Any other movable that loads the same register
2247 MUST be moved. */
2250 /* This reg has been moved out of one loop. */
2253 /* The reg set here is now invariant. */
2255 {
2259 }
2261 /* Change the length-of-life info for the register
2262 to say it lives at least the full length of this loop.
2263 This will help guide optimizations in outer loops. */
2266 /* This is the old insn before all the moved insns.
2267 We can't use the moved insn because it is out of range
2268 in uid_luid. Only the old insns have luids. */
2272 }
2274 /* Combine with this moved insn any other matching movables. */
2279 {
2280 rtx temp;
2282 /* Schedule the reg loaded by M1
2283 for replacement so that shares the reg of M.
2284 If the modes differ (only possible in restricted
2285 circumstances, make a SUBREG.
2287 Note this assumes that the target dependent files
2288 treat REG and SUBREG equally, including within
2289 GO_IF_LEGITIMATE_ADDRESS and in all the
2290 predicates since we never verify that replacing the
2291 original register with a SUBREG results in a
2292 recognizable insn. */
2295 else
2300 /* Get rid of the matching insn
2301 and prevent further processing of it. */
2304 /* if library call, delete all insns. */
2306 NULL_RTX)))
2308 else
2311 /* Any other movable that loads the same register
2312 MUST be moved. */
2315 /* The reg merged here is now invariant,
2316 if the reg it matches is invariant. */
2318 {
2322 i++)
2324 }
2325 }
2326 }
2329 }
2335 }
2340 /* Go through all the instructions in the loop, making
2341 all the register substitutions scheduled in REG_MAP. */
2345 {
2349 }
2351 /* Clean up. */
2354 }
2357 static void
2361 {
2364 else
2367 }
2370 static void
2373 {
2378 {
2381 }
2382 }
2383 \f
2384 #if 0
2385 /* Scan X and replace the address of any MEM in it with ADDR.
2386 REG is the address that MEM should have before the replacement. */
2388 static void
2391 {
2400 {
2412 /* Short cut for very common case. */
2417 /* Short cut for very common case. */
2422 /* If this MEM uses a reg other than the one we expected,
2423 something is wrong. */
2431 }
2435 {
2439 {
2443 }
2444 }
2445 }
2446 #endif
2447 \f
2448 /* Return the number of memory refs to addresses that vary
2449 in the rtx X. */
2451 static int
2454 rtx x;
2455 {
2466 {
2483 }
2488 {
2492 {
2496 }
2497 }
2499 }
2500 \f
2501 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2502 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2503 `unknown_address_altered', `unknown_constant_address_altered', and
2504 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2505 list `store_mems' in LOOP. */
2507 static void
2510 {
2512 rtx insn;
2516 /* The label after END. Jumping here is just like falling off the
2517 end of the loop. We use next_nonnote_insn instead of next_label
2518 as a hedge against the (pathological) case where some actual insn
2519 might end up between the two. */
2538 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2543 {
2545 {
2548 }
2549 }
2553 {
2555 {
2558 {
2560 /* Count number of loops contained in this one. */
2562 }
2569 {
2572 }
2579 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2580 attached FUNCTION_USAGE expression list, not accounted for by the
2581 code above. We should note these to avoid missing dependencies in
2582 later references. */
2583 {
2584 rtx fusage_entry;
2588 {
2594 {
2599 }
2600 }
2601 }
2606 {
2610 {
2615 {
2618 }
2619 else
2620 {
2623 }
2625 do
2626 {
2628 {
2630 {
2631 /* Something tricky. */
2634 }
2637 {
2638 /* A jump outside the current loop. */
2641 }
2642 }
2646 }
2648 }
2649 else
2650 {
2651 /* A return, or something tricky. */
2653 }
2654 }
2655 /* FALLTHRU */
2676 }
2677 }
2679 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2681 anywhere. */
2683 /* We don't want loads for MEMs moved to a location before the
2684 one at which their stack memory becomes allocated. (Note
2685 that this is not a problem for malloc, etc., since those
2686 require actual function calls. */
2687 && ! current_function_calls_alloca
2688 /* There are ways to leave the loop other than falling off the
2689 end. */
2695 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2696 that loop_invariant_p and load_mems can use true_dependence
2697 to determine what is really clobbered. */
2699 {
2702 loop_info->store_mems
2704 }
2706 {
2710 loop_info->store_mems
2712 }
2713 }
2714 \f
2715 /* Invalidate all loops containing LABEL. */
2717 static void
2719 rtx label;
2720 {
2724 }
2726 /* Scan the function looking for loops. Record the start and end of each loop.
2727 Also mark as invalid loops any loops that contain a setjmp or are branched
2728 to from outside the loop. */
2730 static void
2732 rtx f;
2734 {
2735 rtx insn;
2736 rtx label;
2746 /* If there are jumps to undefined labels,
2747 treat them as jumps out of any/all loops.
2748 This also avoids writing past end of tables when there are no loops. */
2751 /* Find boundaries of loops, mark which loops are contained within
2752 loops, and invalidate loops that have setjmp. */
2757 {
2760 {
2764 num_loops++;
2788 }
2792 {
2793 /* In this case, we must invalidate our current loop and any
2794 enclosing loop. */
2796 {
2802 }
2803 }
2805 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2806 enclosing loop, but this doesn't matter. */
2808 }
2810 /* Any loop containing a label used in an initializer must be invalidated,
2811 because it can be jumped into from anywhere. */
2815 /* Any loop containing a label used for an exception handler must be
2816 invalidated, because it can be jumped into from anywhere. */
2819 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2820 loop that it is not contained within, that loop is marked invalid.
2821 If any INSN or CALL_INSN uses a label's address, then the loop containing
2822 that label is marked invalid, because it could be jumped into from
2823 anywhere.
2825 Also look for blocks of code ending in an unconditional branch that
2826 exits the loop. If such a block is surrounded by a conditional
2827 branch around the block, move the block elsewhere (see below) and
2828 invert the jump to point to the code block. This may eliminate a
2829 label in our loop and will simplify processing by both us and a
2830 possible second cse pass. */
2834 {
2838 {
2842 }
2849 /* See if this is an unconditional branch outside the loop. */
2857 {
2858 rtx p;
2864 /* Go backwards until we reach the start of the loop, a label,
2865 or a JUMP_INSN. */
2872 ;
2874 /* Check for the case where we have a jump to an inner nested
2875 loop, and do not perform the optimization in that case. */
2878 {
2881 {
2886 }
2887 }
2889 /* Make sure that the target of P is within the current loop. */
2895 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2896 we have a block of code to try to move.
2898 We look backward and then forward from the target of INSN
2899 to find a BARRIER at the same loop depth as the target.
2900 If we find such a BARRIER, we make a new label for the start
2901 of the block, invert the jump in P and point it to that label,
2902 and move the block of code to the spot we found. */
2907 /* Just ignore jumps to labels that were never emitted.
2908 These always indicate compilation errors. */
2912 /* If it's not safe to move the sequence, then we
2913 mustn't try. */
2916 {
2917 rtx target
2921 rtx tmp;
2923 /* Search for possible garbage past the conditional jumps
2924 and look for the last barrier. */
2932 /* Don't move things inside a tablejump. */
2945 /* Don't move things inside a tablejump. */
2956 {
2960 /* Ensure our label doesn't go away. */
2963 /* Verify that uid_loop is large enough and that
2964 we can invert P. */
2966 {
2969 /* If no suitable BARRIER was found, create a suitable
2970 one before TARGET. Since TARGET is a fall through
2971 path, we'll need to insert a jump around our block
2972 and add a BARRIER before TARGET.
2974 This creates an extra unconditional jump outside
2975 the loop. However, the benefits of removing rarely
2976 executed instructions from inside the loop usually
2977 outweighs the cost of the extra unconditional jump
2978 outside the loop. */
2980 {
2981 rtx temp;
2988 }
2990 /* Include the BARRIER after INSN and copy the
2991 block after LOC. */
2996 /* All those insns are now in TARGET_LOOP. */
3002 /* The label jumped to by INSN is no longer a loop
3003 exit. Unless INSN does not have a label (e.g.,
3004 it is a RETURN insn), search loop->exit_labels
3005 to find its label_ref, and remove it. Also turn
3006 off LABEL_OUTSIDE_LOOP_P bit. */
3008 {
3010 r;
3013 {
3017 else
3020 }
3026 /* If we didn't find it, then something is
3027 wrong. */
3030 }
3032 /* P is now a jump outside the loop, so it must be put
3033 in loop->exit_labels, and marked as such.
3034 The easiest way to do this is to just call
3035 mark_loop_jump again for P. */
3038 /* If INSN now jumps to the insn after it,
3039 delete INSN. */
3044 }
3046 /* Continue the loop after where the conditional
3047 branch used to jump, since the only branch insn
3048 in the block (if it still remains) is an inter-loop
3049 branch and hence needs no processing. */
3055 /* This loop will be continued with NEXT_INSN (insn). */
3057 }
3058 }
3059 }
3060 }
3061 }
3063 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3064 loops it is contained in, mark the target loop invalid.
3066 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3068 static void
3070 rtx x;
3072 {
3078 {
3090 /* There could be a label reference in here. */
3102 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3114 /* Link together all labels that branch outside the loop. This
3115 is used by final_[bg]iv_value and the loop unrolling code. Also
3116 mark this LABEL_REF so we know that this branch should predict
3117 false. */
3119 /* A check to make sure the label is not in an inner nested loop,
3120 since this does not count as a loop exit. */
3122 {
3127 }
3128 else
3132 {
3141 }
3143 /* If this is inside a loop, but not in the current loop or one enclosed
3144 by it, it invalidates at least one loop. */
3149 /* We must invalidate every nested loop containing the target of this
3150 label, except those that also contain the jump insn. */
3153 {
3154 /* Stop when we reach a loop that also contains the jump insn. */
3159 /* If we get here, we know we need to invalidate a loop. */
3166 }
3170 /* If this is not setting pc, ignore. */
3192 /* Strictly speaking this is not a jump into the loop, only a possible
3193 jump out of the loop. However, we have no way to link the destination
3194 of this jump onto the list of exit labels. To be safe we mark this
3195 loop and any containing loops as invalid. */
3197 {
3199 {
3205 }
3206 }
3208 }
3209 }
3210 \f
3211 /* Return nonzero if there is a label in the range from
3212 insn INSN to and including the insn whose luid is END
3213 INSN must have an assigned luid (i.e., it must not have
3214 been previously created by loop.c). */
3216 static int
3218 rtx insn;
3220 {
3222 {
3226 }
3229 }
3231 /* Record that a memory reference X is being set. */
3233 static void
3235 rtx x;
3236 rtx y ATTRIBUTE_UNUSED;
3238 {
3244 /* Count number of memory writes.
3245 This affects heuristics in strength_reduce. */
3248 /* BLKmode MEM means all memory is clobbered. */
3250 {
3253 else
3257 }
3261 }
3263 /* X is a value modified by an INSN that references a biv inside a loop
3264 exit test (ie, X is somehow related to the value of the biv). If X
3265 is a pseudo that is used more than once, then the biv is (effectively)
3266 used more than once. DATA is a pointer to a loop_regs structure. */
3268 static void
3270 rtx x;
3271 rtx y ATTRIBUTE_UNUSED;
3273 {
3288 /* If we do not have usage information, or if we know the register
3289 is used more than once, note that fact for check_dbra_loop. */
3294 }
3295 \f
3296 /* Return nonzero if the rtx X is invariant over the current loop.
3298 The value is 2 if we refer to something only conditionally invariant.
3300 A memory ref is invariant if it is not volatile and does not conflict
3301 with anything stored in `loop_info->store_mems'. */
3303 int
3306 rtx x;
3307 {
3314 rtx mem_list_entry;
3320 {
3328 /* A LABEL_REF is normally invariant, however, if we are unrolling
3329 loops, and this label is inside the loop, then it isn't invariant.
3330 This is because each unrolled copy of the loop body will have
3331 a copy of this label. If this was invariant, then an insn loading
3332 the address of this label into a register might get moved outside
3333 the loop, and then each loop body would end up using the same label.
3335 We don't know the loop bounds here though, so just fail for all
3336 labels. */
3339 else
3348 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3349 since the reg might be set by initialization within the loop. */
3360 /* Out-of-range regs can occur when we are called from unrolling.
3361 These have always been created by the unroller and are set in
3362 the loop, hence are never invariant. */
3373 /* Volatile memory references must be rejected. Do this before
3374 checking for read-only items, so that volatile read-only items
3375 will be rejected also. */
3379 /* See if there is any dependence between a store and this load. */
3382 {
3388 }
3390 /* It's not invalidated by a store in memory
3391 but we must still verify the address is invariant. */
3395 /* Don't mess with insns declared volatile. */
3402 }
3406 {
3408 {
3414 }
3416 {
3419 {
3425 }
3427 }
3428 }
3431 }
3432 \f
3433 /* Return nonzero if all the insns in the loop that set REG
3434 are INSN and the immediately following insns,
3435 and if each of those insns sets REG in an invariant way
3436 (not counting uses of REG in them).
3438 The value is 2 if some of these insns are only conditionally invariant.
3440 We assume that INSN itself is the first set of REG
3441 and that its source is invariant. */
3443 static int
3448 {
3452 rtx temp;
3453 /* Number of sets we have to insist on finding after INSN. */
3459 /* If N_SETS hit the limit, we can't rely on its value. */
3466 {
3468 rtx set;
3473 /* If library call, skip to end of it. */
3482 {
3487 {
3488 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3489 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3490 notes are OK. */
3496 }
3497 }
3499 count--;
3501 {
3504 }
3505 }
3508 /* If loop_invariant_p ever returned 2, we return 2. */
3510 }
3512 #if 0
3513 /* I don't think this condition is sufficient to allow INSN
3514 to be moved, so we no longer test it. */
3516 /* Return 1 if all insns in the basic block of INSN and following INSN
3517 that set REG are invariant according to TABLE. */
3519 static int
3523 {
3528 {
3537 {
3540 }
3541 }
3542 }
3544 \f
3545 /* Look at all uses (not sets) of registers in X. For each, if it is
3546 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3547 a different insn, set USAGE[REGNO] to const0_rtx. */
3549 static void
3552 rtx insn;
3553 rtx x;
3554 {
3566 {
3567 /* Don't count SET_DEST if it is a REG; otherwise count things
3568 in SET_DEST because if a register is partially modified, it won't
3569 show up as a potential movable so we don't care how USAGE is set
3570 for it. */
3574 }
3575 else
3577 {
3583 }
3584 }
3585 \f
3586 /* Count and record any set in X which is contained in INSN. Update
3587 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3588 in X. */
3590 static void
3595 {
3597 /* Don't move a reg that has an explicit clobber.
3598 It's not worth the pain to try to do it correctly. */
3602 {
3610 {
3614 {
3615 /* If this is the first setting of this reg
3616 in current basic block, and it was set before,
3617 it must be set in two basic blocks, so it cannot
3618 be moved out of the loop. */
3622 /* If this is not first setting in current basic block,
3623 see if reg was used in between previous one and this.
3624 If so, neither one can be moved. */
3631 }
3632 }
3633 }
3634 }
3635 \f
3636 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3637 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3638 contained in insn INSN is used by any insn that precedes INSN in
3639 cyclic order starting from the loop entry point.
3641 We don't want to use INSN_LUID here because if we restrict INSN to those
3642 that have a valid INSN_LUID, it means we cannot move an invariant out
3643 from an inner loop past two loops. */
3645 static int
3649 {
3651 rtx p;
3653 /* Scan forward checking for register usage. If we hit INSN, we
3654 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3656 {
3662 }
3665 }
3666 \f
3668 /* Information we collect about arrays that we might want to prefetch. */
3669 struct prefetch_info
3670 {
3674 index. */
3675 HOST_WIDE_INT index;
3677 iteration. */
3679 prefetch area in one iteration. */
3681 This is set only for loops with known
3682 iteration counts and is 0xffffffff
3683 otherwise. */
3687 };
3689 /* Data used by check_store function. */
3690 struct check_store_data
3691 {
3692 rtx mem_address;
3694 };
3700 /* Set mem_write when mem_address is found. Used as callback to
3701 note_stores. */
3702 static void
3706 {
3711 }
3712 \f
3713 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3714 important to get some addresses combined. Later more sophisticated
3715 transformations can be added when necessary.
3717 ??? Same trick with swapping operand is done at several other places.
3718 It can be nice to develop some common way to handle this. */
3720 static int
3723 {
3737 {
3742 }
3743 /* Compare the elements. If any pair of corresponding elements fails to
3744 match, return 0 for the whole thing. */
3748 {
3750 {
3762 /* Two vectors must have the same length. */
3766 /* And the corresponding elements must match. */
3784 /* These are just backpointers, so they don't matter. */
3790 /* It is believed that rtx's at this level will never
3791 contain anything but integers and other rtx's,
3792 except for within LABEL_REFs and SYMBOL_REFs. */
3795 }
3796 }
3798 }
3799 \f
3800 /* Remove constant addition value from the expression X (when present)
3801 and return it. */
3803 static HOST_WIDE_INT
3806 {
3810 /* Avoid clobbering a shared CONST expression. */
3812 {
3816 {
3819 }
3821 }
3824 {
3827 }
3829 /* For plus expression recurse on ourself. */
3831 {
3835 /* In case our parameter was constant, remove extra zero from the
3836 expression. */
3841 }
3844 }
3846 /* Attempt to identify accesses to arrays that are most likely to cause cache
3847 misses, and emit prefetch instructions a few prefetch blocks forward.
3849 To detect the arrays we use the GIV information that was collected by the
3850 strength reduction pass.
3852 The prefetch instructions are generated after the GIV information is done
3853 and before the strength reduction process. The new GIVs are injected into
3854 the strength reduction tables, so the prefetch addresses are optimized as
3855 well.
3857 GIVs are split into base address, stride, and constant addition values.
3858 GIVs with the same address, stride and close addition values are combined
3859 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3860 for write instructions can be used for the block we write to, on machines
3861 that support write prefetches.
3863 Several heuristics are used to determine when to prefetch. They are
3864 controlled by defined symbols that can be overridden for each target. */
3866 static void
3869 {
3885 /* Consider only loops w/o calls. When a call is done, the loop is probably
3886 slow enough to read the memory. */
3888 {
3893 }
3895 /* Don't prefetch in loops known to have few iterations. */
3899 {
3904 }
3906 /* Search all induction variables and pick those interesting for the prefetch
3907 machinery. */
3909 {
3915 /* Expect all BIVs to be executed in each iteration. This makes our
3916 analysis more conservative. */
3918 {
3919 /* Discard non-constant additions that we can't handle well yet, and
3920 BIVs that are executed multiple times; such BIVs ought to be
3921 handled in the nested loop. We accept not_every_iteration BIVs,
3922 since these only result in larger strides and make our
3923 heuristics more conservative. */
3925 {
3927 {
3933 }
3935 }
3938 {
3940 {
3946 }
3948 }
3952 }
3958 {
3959 rtx address;
3960 rtx temp;
3969 /* See whether an induction variable is interesting to us and if
3970 not, report the reason. */
3974 /* We are interested only in constant stride memory references
3975 in order to be able to compute density easily. */
3979 else
3980 {
3983 {
3986 }
3988 /* On some targets, reversed order prefetches are not
3989 worthwhile. */
3993 /* Prefetch of accesses with an extreme stride might not be
3994 worthwhile, either. */
3999 /* Ignore GIVs with varying add values; we can't predict the
4000 value for the next iteration. */
4004 /* Ignore GIVs in the nested loops; they ought to have been
4005 handled already. */
4008 }
4011 {
4017 }
4019 /* Determine the pointer to the basic array we are examining. It is
4020 the sum of the BIV's initial value and the GIV's add_val. */
4030 /* When the GIV is not always executed, we might be better off by
4031 not dirtying the cache pages. */
4034 else
4035 {
4040 }
4042 /* Attempt to find another prefetch to the same array and see if we
4043 can merge this one. */
4047 {
4048 /* In case both access same array (same location
4049 just with small difference in constant indexes), merge
4050 the prefetches. Just do the later and the earlier will
4051 get prefetched from previous iteration.
4052 The artificial threshold should not be too small,
4053 but also not bigger than small portion of memory usually
4054 traversed by single loop. */
4057 {
4066 }
4070 {
4075 }
4076 }
4078 /* Merging failed. */
4080 {
4088 num_prefetches++;
4090 {
4095 }
4096 }
4097 }
4098 }
4101 {
4104 /* Attempt to calculate the total number of bytes fetched by all
4105 iterations of the loop. Avoid overflow. */
4110 else
4115 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4120 {
4125 }
4126 else
4127 {
4133 }
4134 else
4137 /* Find how many prefetch instructions we'll use within the loop. */
4139 {
4145 }
4146 }
4148 /* Determine how many iterations ahead to prefetch within the loop, based
4149 on how many prefetches we currently expect to do within the loop. */
4151 {
4153 {
4159 }
4160 }
4161 /* We'll also use AHEAD to determine how many prefetch instructions to
4162 emit before a loop, so don't leave it zero. */
4167 {
4168 /* Update if we've decided not to prefetch anything within the loop. */
4172 /* Find how many prefetch instructions we'll use before the loop. */
4174 {
4182 }
4185 {
4205 }
4206 }
4209 {
4210 /* Record that this loop uses prefetch instructions. */
4214 {
4219 }
4220 }
4223 {
4227 {
4229 rtx insn;
4233 rtx seq;
4235 /* We can save some effort by offsetting the address on
4236 architectures with offsettable memory references. */
4239 else
4240 {
4246 }
4249 /* Make sure the address operand is valid for prefetch. */
4259 /* Check all insns emitted and record the new GIV
4260 information. */
4263 {
4268 }
4269 }
4272 {
4273 /* Emit insns before the loop to fetch the first cache lines or,
4274 if we're not prefetching within the loop, everything we expect
4275 to need. */
4277 {
4285 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4286 non-constant INIT_VAL to have the same mode as REG, which
4287 in this case we know to be Pmode. */
4289 {
4290 rtx seq;
4297 }
4303 loop_start);
4304 }
4305 }
4306 }
4309 }
4310 \f
4311 /* A "basic induction variable" or biv is a pseudo reg that is set
4312 (within this loop) only by incrementing or decrementing it. */
4313 /* A "general induction variable" or giv is a pseudo reg whose
4314 value is a linear function of a biv. */
4316 /* Bivs are recognized by `basic_induction_var';
4317 Givs by `general_induction_var'. */
4319 /* Communication with routines called via `note_stores'. */
4323 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4327 /* ??? Unfinished optimizations, and possible future optimizations,
4328 for the strength reduction code. */
4330 /* ??? The interaction of biv elimination, and recognition of 'constant'
4331 bivs, may cause problems. */
4333 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4334 performance problems.
4336 Perhaps don't eliminate things that can be combined with an addressing
4337 mode. Find all givs that have the same biv, mult_val, and add_val;
4338 then for each giv, check to see if its only use dies in a following
4339 memory address. If so, generate a new memory address and check to see
4340 if it is valid. If it is valid, then store the modified memory address,
4341 otherwise, mark the giv as not done so that it will get its own iv. */
4343 /* ??? Could try to optimize branches when it is known that a biv is always
4344 positive. */
4346 /* ??? When replace a biv in a compare insn, we should replace with closest
4347 giv so that an optimized branch can still be recognized by the combiner,
4348 e.g. the VAX acb insn. */
4350 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4351 was rerun in loop_optimize whenever a register was added or moved.
4352 Also, some of the optimizations could be a little less conservative. */
4353 \f
4354 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4355 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4356 callback.
4358 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4359 least once for every loop iteration except for the last one.
4361 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4362 loop iteration.
4363 */
4364 void
4367 loop_insn_callback fncall;
4368 {
4373 rtx p;
4375 /* If loop_scan_start points to the loop exit test, we have to be wary of
4376 subversive use of gotos inside expression statements. */
4380 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4384 {
4387 /* Past CODE_LABEL, we get to insns that may be executed multiple
4388 times. The only way we can be sure that they can't is if every
4389 jump insn between here and the end of the loop either
4390 returns, exits the loop, is a jump to a location that is still
4391 behind the label, or is a jump to the loop start. */
4394 {
4400 {
4405 {
4408 else
4412 }
4420 {
4423 }
4424 }
4425 }
4427 /* Past a jump, we get to insns for which we can't count
4428 on whether they will be executed during each iteration. */
4429 /* This code appears twice in strength_reduce. There is also similar
4430 code in scan_loop. */
4432 /* If we enter the loop in the middle, and scan around to the
4433 beginning, don't set not_every_iteration for that.
4434 This can be any kind of jump, since we want to know if insns
4435 will be executed if the loop is executed. */
4440 {
4443 /* If this is a jump outside the loop, then it also doesn't
4444 matter. Check to see if the target of this branch is on the
4445 loop->exits_labels list. */
4453 }
4456 {
4457 /* At the virtual top of a converted loop, insns are again known to
4458 be executed each iteration: logically, the loop begins here
4459 even though the exit code has been duplicated.
4461 Insns are also again known to be executed each iteration at
4462 the LOOP_CONT note. */
4468 loop_depth++;
4470 loop_depth--;
4471 }
4473 /* Note if we pass a loop latch. If we do, then we can not clear
4474 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4475 a loop since a jump before the last CODE_LABEL may have started
4476 a new loop iteration.
4478 Note that LOOP_TOP is only set for rotated loops and we need
4479 this check for all loops, so compare against the CODE_LABEL
4480 which immediately follows LOOP_START. */
4485 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4486 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4487 or not an insn is known to be executed each iteration of the
4488 loop, whether or not any iterations are known to occur.
4490 Therefore, if we have just passed a label and have no more labels
4491 between here and the test insn of the loop, and we have not passed
4492 a jump to the top of the loop, then we know these insns will be
4493 executed each iteration. */
4496 && !past_loop_latch
4501 }
4502 }
4503 \f
4504 static void
4507 {
4510 /* Temporary list pointers for traversing ivs->list. */
4517 /* Scan ivs->list to remove all regs that proved not to be bivs.
4518 Make a sanity check against regs->n_times_set. */
4520 {
4522 /* Above happens if register modified by subreg, etc. */
4523 /* Make sure it is not recognized as a basic induction var: */
4525 /* If never incremented, it is invariant that we decided not to
4526 move. So leave it alone. */
4528 {
4539 }
4540 else
4541 {
4546 }
4547 }
4548 }
4551 /* Determine how BIVS are initialized by looking through pre-header
4552 extended basic block. */
4553 static void
4556 {
4558 /* Temporary list pointers for traversing ivs->list. */
4561 rtx p;
4563 /* Find initial value for each biv by searching backwards from loop_start,
4564 halting at first label. Also record any test condition. */
4568 {
4569 rtx test;
4579 /* Record any test of a biv that branches around the loop if no store
4580 between it and the start of loop. We only care about tests with
4581 constants and registers and only certain of those. */
4591 {
4592 /* If an NE test, we have an initial value! */
4594 {
4598 }
4599 else
4601 }
4602 }
4603 }
4606 /* Look at the each biv and see if we can say anything better about its
4607 initial value from any initializing insns set up above. (This is done
4608 in two passes to avoid missing SETs in a PARALLEL.) */
4609 static void
4612 {
4614 /* Temporary list pointers for traversing ivs->list. */
4619 {
4620 rtx src;
4621 rtx note;
4626 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4627 is a constant, use the value of that. */
4633 else
4646 {
4650 {
4653 }
4654 }
4655 /* If we can't make it a giv,
4656 let biv keep initial value of "itself". */
4659 }
4660 }
4663 /* Search the loop for general induction variables. */
4665 static void
4668 {
4670 }
4673 /* For each giv for which we still don't know whether or not it is
4674 replaceable, check to see if it is replaceable because its final value
4675 can be calculated. */
4677 static void
4680 {
4685 {
4691 }
4692 }
4695 /* Return nonzero if it is possible to eliminate the biv BL provided
4696 all givs are reduced. This is possible if either the reg is not
4697 used outside the loop, or we can compute what its final value will
4698 be. */
4700 static int
4706 {
4707 /* For architectures with a decrement_and_branch_until_zero insn,
4708 don't do this if we put a REG_NONNEG note on the endtest for this
4709 biv. */
4711 #ifdef HAVE_decrement_and_branch_until_zero
4713 {
4718 }
4719 #endif
4721 /* Check that biv is used outside loop or if it has a final value.
4722 Compare against bl->init_insn rather than loop->start. We aren't
4723 concerned with any uses of the biv between init_insn and
4724 loop->start since these won't be affected by the value of the biv
4725 elsewhere in the function, so long as init_insn doesn't use the
4726 biv itself. */
4737 {
4745 }
4747 }
4750 /* Reduce each giv of BL that we have decided to reduce. */
4752 static void
4756 {
4760 {
4763 {
4766 /* If the code for derived givs immediately below has already
4767 allocated a new_reg, we must keep it. */
4771 #ifdef AUTO_INC_DEC
4772 /* If the target has auto-increment addressing modes, and
4773 this is an address giv, then try to put the increment
4774 immediately after its use, so that flow can create an
4775 auto-increment addressing mode. */
4778 /* We don't handle reversed biv's because bl->biv->insn
4779 does not have a valid INSN_LUID. */
4783 {
4784 /* If other giv's have been combined with this one, then
4785 this will work only if all uses of the other giv's occur
4786 before this giv's insn. This is difficult to check.
4788 We simplify this by looking for the common case where
4789 there is one DEST_REG giv, and this giv's insn is the
4790 last use of the dest_reg of that DEST_REG giv. If the
4791 increment occurs after the address giv, then we can
4792 perform the optimization. (Otherwise, the increment
4793 would have to go before other_giv, and we would not be
4794 able to combine it with the address giv to get an
4795 auto-inc address.) */
4797 {
4802 {
4805 else
4807 }
4814 }
4815 /* Check for case where increment is before the address
4816 giv. Do this test in "loop order". */
4825 else
4828 #ifdef HAVE_cc0
4829 {
4830 rtx prev;
4832 /* We can't put an insn immediately after one setting
4833 cc0, or immediately before one using cc0. */
4840 }
4841 #endif
4845 }
4846 #endif
4848 /* For each place where the biv is incremented, add an insn
4849 to increment the new, reduced reg for the giv. */
4851 {
4852 rtx insert_before;
4854 /* Skip if location is the same as a previous one. */
4861 else
4869 /* A multiply is acceptable here
4870 since this is presumed to be seldom executed. */
4874 }
4876 /* Add code at loop start to initialize giv's reduced reg. */
4881 }
4882 }
4883 }
4886 /* Check for givs whose first use is their definition and whose
4887 last use is the definition of another giv. If so, it is likely
4888 dead and should not be used to derive another giv nor to
4889 eliminate a biv. */
4891 static void
4895 {
4899 {
4906 {
4912 }
4913 }
4914 }
4917 static void
4922 {
4926 {
4933 /* Update expression if this was combined, in case other giv was
4934 replaced. */
4939 /* See if this register is known to be a pointer to something. If
4940 so, see if we can find the alignment. First see if there is a
4941 destination register that is a pointer. If so, this shares the
4942 alignment too. Next see if we can deduce anything from the
4943 computational information. If not, and this is a DEST_ADDR
4944 giv, at least we know that it's a pointer, though we don't know
4945 the alignment. */
4953 {
4962 }
4966 {
4974 }
4979 /* Store reduced reg as the address in the memref where we found
4980 this giv. */
4983 {
4985 }
4986 else
4987 {
4989 rtx note;
4991 /* Not replaceable; emit an insn to set the original giv reg from
4992 the reduced giv, same as above. */
4997 /* The original insn may have a REG_EQUAL note. This note is
4998 now incorrect and may result in invalid substitutions later.
4999 The original insn is dead, but may be part of a libcall
5000 sequence, which doesn't seem worth the bother of handling. */
5004 }
5006 /* When a loop is reversed, givs which depend on the reversed
5007 biv, and which are live outside the loop, must be set to their
5008 correct final value. This insn is only needed if the giv is
5009 not replaceable. The correct final value is the same as the
5010 value that the giv starts the reversed loop with. */
5021 {
5026 }
5027 }
5028 }
5031 static int
5036 rtx test_reg;
5037 {
5046 /* Reduce benefit if not replaceable, since we will insert a
5047 move-insn to replace the insn that calculates this giv. Don't do
5048 this unless the giv is a user variable, since it will often be
5049 marked non-replaceable because of the duplication of the exit
5050 code outside the loop. In such a case, the copies we insert are
5051 dead and will be deleted. So they don't have a cost. Similar
5052 situations exist. */
5053 /* ??? The new final_[bg]iv_value code does a much better job of
5054 finding replaceable giv's, and hence this code may no longer be
5055 necessary. */
5060 /* Decrease the benefit to count the add-insns that we will insert
5061 to increment the reduced reg for the giv. ??? This can
5062 overestimate the run-time cost of the additional insns, e.g. if
5063 there are multiple basic blocks that increment the biv, but only
5064 one of these blocks is executed during each iteration. There is
5065 no good way to detect cases like this with the current structure
5066 of the loop optimizer. This code is more accurate for
5067 determining code size than run-time benefits. */
5070 /* Decide whether to strength-reduce this giv or to leave the code
5071 unchanged (recompute it from the biv each time it is used). This
5072 decision can be made independently for each giv. */
5074 #ifdef AUTO_INC_DEC
5075 /* Attempt to guess whether autoincrement will handle some of the
5076 new add insns; if so, increase BENEFIT (undo the subtraction of
5077 add_cost that was done above). */
5079 /* Increasing the benefit is risky, since this is only a guess.
5080 Avoid increasing register pressure in cases where there would
5081 be no other benefit from reducing this giv. */
5084 {
5099 }
5100 #endif
5103 }
5106 /* Free IV structures for LOOP. */
5108 static void
5111 {
5118 {
5124 {
5127 }
5129 {
5132 }
5136 }
5137 }
5140 /* Perform strength reduction and induction variable elimination.
5142 Pseudo registers created during this function will be beyond the
5143 last valid index in several tables including
5144 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5145 problem here, because the added registers cannot be givs outside of
5146 their loop, and hence will never be reconsidered. But scan_loop
5147 must check regnos to make sure they are in bounds. */
5149 static void
5153 {
5157 rtx p;
5158 /* Temporary list pointer for traversing ivs->list. */
5160 /* Ratio of extra register life span we can justify
5161 for saving an instruction. More if loop doesn't call subroutines
5162 since in that case saving an insn makes more difference
5163 and more registers are available. */
5164 /* ??? could set this to last value of threshold in move_movables */
5166 /* Map of pseudo-register replacements. */
5178 /* Find all BIVs in loop. */
5181 /* Exit if there are no bivs. */
5183 {
5184 /* Can still unroll the loop anyways, but indicate that there is no
5185 strength reduction info available. */
5191 }
5193 /* Determine how BIVS are initialized by looking through pre-header
5194 extended basic block. */
5197 /* Look at the each biv and see if we can say anything better about its
5198 initial value from any initializing insns set up above. */
5201 /* Search the loop for general induction variables. */
5204 /* Try to calculate and save the number of loop iterations. This is
5205 set to zero if the actual number can not be calculated. This must
5206 be called after all giv's have been identified, since otherwise it may
5207 fail if the iteration variable is a giv. */
5210 #ifdef HAVE_prefetch
5213 #endif
5215 /* Now for each giv for which we still don't know whether or not it is
5216 replaceable, check to see if it is replaceable because its final value
5217 can be calculated. This must be done after loop_iterations is called,
5218 so that final_giv_value will work correctly. */
5221 /* Try to prove that the loop counter variable (if any) is always
5222 nonnegative; if so, record that fact with a REG_NONNEG note
5223 so that "decrement and branch until zero" insn can be used. */
5226 /* Create reg_map to hold substitutions for replaceable giv regs.
5227 Some givs might have been made from biv increments, so look at
5228 ivs->reg_iv_type for a suitable size. */
5232 /* Examine each iv class for feasibility of strength reduction/induction
5233 variable elimination. */
5236 {
5240 /* Test whether it will be possible to eliminate this biv
5241 provided all givs are reduced. */
5244 /* This will be true at the end, if all givs which depend on this
5245 biv have been strength reduced.
5246 We can't (currently) eliminate the biv unless this is so. */
5249 /* Check each extension dependent giv in this class to see if its
5250 root biv is safe from wrapping in the interior mode. */
5253 /* Combine all giv's for this iv_class. */
5257 {
5265 /* If an insn is not to be strength reduced, then set its ignore
5266 flag, and clear bl->all_reduced. */
5268 /* A giv that depends on a reversed biv must be reduced if it is
5269 used after the loop exit, otherwise, it would have the wrong
5270 value after the loop exit. To make it simple, just reduce all
5271 of such giv's whether or not we know they are used after the loop
5272 exit. */
5277 {
5285 }
5286 else
5287 {
5288 /* Check that we can increment the reduced giv without a
5289 multiply insn. If not, reject it. */
5294 {
5302 }
5303 }
5304 }
5306 /* Check for givs whose first use is their definition and whose
5307 last use is the definition of another giv. If so, it is likely
5308 dead and should not be used to derive another giv nor to
5309 eliminate a biv. */
5312 /* Reduce each giv that we decided to reduce. */
5315 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5316 as not reduced.
5318 For each giv register that can be reduced now: if replaceable,
5319 substitute reduced reg wherever the old giv occurs;
5320 else add new move insn "giv_reg = reduced_reg". */
5323 /* All the givs based on the biv bl have been reduced if they
5324 merit it. */
5326 /* For each giv not marked as maybe dead that has been combined with a
5327 second giv, clear any "maybe dead" mark on that second giv.
5328 v->new_reg will either be or refer to the register of the giv it
5329 combined with.
5331 Doing this clearing avoids problems in biv elimination where
5332 a giv's new_reg is a complex value that can't be put in the
5333 insn but the giv combined with (with a reg as new_reg) is
5334 marked maybe_dead. Since the register will be used in either
5335 case, we'd prefer it be used from the simpler giv. */
5341 /* Try to eliminate the biv, if it is a candidate.
5342 This won't work if ! bl->all_reduced,
5343 since the givs we planned to use might not have been reduced.
5345 We have to be careful that we didn't initially think we could
5346 eliminate this biv because of a giv that we now think may be
5347 dead and shouldn't be used as a biv replacement.
5349 Also, there is the possibility that we may have a giv that looks
5350 like it can be used to eliminate a biv, but the resulting insn
5351 isn't valid. This can happen, for example, on the 88k, where a
5352 JUMP_INSN can compare a register only with zero. Attempts to
5353 replace it with a compare with a constant will fail.
5355 Note that in cases where this call fails, we may have replaced some
5356 of the occurrences of the biv with a giv, but no harm was done in
5357 doing so in the rare cases where it can occur. */
5361 {
5362 /* ?? If we created a new test to bypass the loop entirely,
5363 or otherwise drop straight in, based on this test, then
5364 we might want to rewrite it also. This way some later
5365 pass has more hope of removing the initialization of this
5366 biv entirely. */
5368 /* If final_value != 0, then the biv may be used after loop end
5369 and we must emit an insn to set it just in case.
5371 Reversed bivs already have an insn after the loop setting their
5372 value, so we don't need another one. We can't calculate the
5373 proper final value for such a biv here anyways. */
5382 }
5383 /* See above note wrt final_value. But since we couldn't eliminate
5384 the biv, we must set the value after the loop instead of before. */
5388 }
5390 /* Go through all the instructions in the loop, making all the
5391 register substitutions scheduled in REG_MAP. */
5396 {
5400 }
5403 {
5404 /* When we completely unroll a loop we will likely not need the increment
5405 of the loop BIV and we will not need the conditional branch at the
5406 end of the loop. */
5409 #ifdef HAVE_cc0
5410 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5411 need the comparison before the conditional branch at the end of the
5412 loop. */
5414 #endif
5416 /* We'll need one copy for each loop iteration. */
5419 /* A little slop to account for the ability to remove initialization
5420 code, better CSE, and other secondary benefits of completely
5421 unrolling some loops. */
5424 /* Clamp the value. */
5427 }
5429 /* Unroll loops from within strength reduction so that we can use the
5430 induction variable information that strength_reduce has already
5431 collected. Always unroll loops that would be as small or smaller
5432 unrolled than when rolled. */
5439 #ifdef HAVE_doloop_end
5444 /* In case number of iterations is known, drop branch prediction note
5445 in the branch. Do that only in second loop pass, as loop unrolling
5446 may change the number of iterations performed. */
5448 {
5449 unsigned HOST_WIDE_INT n
5454 }
5462 }
5463 \f
5464 /*Record all basic induction variables calculated in the insn. */
5465 static rtx
5468 rtx p;
5471 {
5473 rtx set;
5474 rtx dest_reg;
5475 rtx inc_val;
5476 rtx mult_val;
5482 {
5487 {
5492 {
5493 /* It is a possible basic induction variable.
5494 Create and initialize an induction structure for it. */
5502 }
5505 }
5506 }
5508 }
5509 \f
5510 /* Record all givs calculated in the insn.
5511 A register is a giv if: it is only set once, it is a function of a
5512 biv and a constant (or invariant), and it is not a biv. */
5513 static rtx
5516 rtx p;
5519 {
5522 rtx set;
5523 /* Look for a general induction variable in a register. */
5528 {
5529 rtx src_reg;
5530 rtx dest_reg;
5531 rtx add_val;
5532 rtx mult_val;
5533 rtx ext_val;
5536 rtx last_consec_insn;
5545 /* Equivalent expression is a giv. */
5550 /* Don't try to handle any regs made by loop optimization.
5551 We have nothing on them in regno_first_uid, etc. */
5553 /* Don't recognize a BASIC_INDUCT_VAR here. */
5555 /* This must be the only place where the register is set. */
5557 /* or all sets must be consecutive and make a giv. */
5562 {
5566 /* If this is a library call, increase benefit. */
5570 /* Skip the consecutive insns, if there are any. */
5578 }
5579 }
5581 #ifndef DONT_REDUCE_ADDR
5582 /* Look for givs which are memory addresses. */
5583 /* This resulted in worse code on a VAX 8600. I wonder if it
5584 still does. */
5587 maybe_multiple);
5588 #endif
5590 /* Update the status of whether giv can derive other givs. This can
5591 change when we pass a label or an insn that updates a biv. */
5596 }
5597 \f
5598 /* Return 1 if X is a valid source for an initial value (or as value being
5599 compared against in an initial test).
5601 X must be either a register or constant and must not be clobbered between
5602 the current insn and the start of the loop.
5604 INSN is the insn containing X. */
5606 static int
5608 rtx x;
5609 rtx insn;
5611 rtx loop_start;
5612 {
5616 /* Only consider pseudos we know about initialized in insns whose luids
5617 we know. */
5622 /* Don't use call-clobbered registers across a call which clobbers it. On
5623 some machines, don't use any hard registers at all. */
5625 && (SMALL_REGISTER_CLASSES
5629 /* Don't use registers that have been clobbered before the start of the
5630 loop. */
5635 }
5636 \f
5637 /* Scan X for memory refs and check each memory address
5638 as a possible giv. INSN is the insn whose pattern X comes from.
5639 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5640 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5641 more than once in each loop iteration. */
5643 static void
5646 rtx x;
5647 rtx insn;
5649 {
5659 {
5675 {
5676 rtx src_reg;
5677 rtx add_val;
5678 rtx mult_val;
5679 rtx ext_val;
5682 /* This code used to disable creating GIVs with mult_val == 1 and
5683 add_val == 0. However, this leads to lost optimizations when
5684 it comes time to combine a set of related DEST_ADDR GIVs, since
5685 this one would not be seen. */
5690 {
5691 /* Found one; record it. */
5700 }
5701 }
5706 }
5708 /* Recursively scan the subexpressions for other mem refs. */
5714 maybe_multiple);
5718 maybe_multiple);
5719 }
5720 \f
5721 /* Fill in the data about one biv update.
5722 V is the `struct induction' in which we record the biv. (It is
5723 allocated by the caller, with alloca.)
5724 INSN is the insn that sets it.
5725 DEST_REG is the biv's reg.
5727 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5728 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5729 being set to INC_VAL.
5731 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5732 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5733 can be executed more than once per iteration. If MAYBE_MULTIPLE
5734 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5735 executed exactly once per iteration. */
5737 static void
5742 rtx insn;
5743 rtx dest_reg;
5744 rtx inc_val;
5745 rtx mult_val;
5749 {
5766 /* Add this to the reg's iv_class, creating a class
5767 if this is the first incrementation of the reg. */
5771 {
5772 /* Create and initialize new iv_class. */
5782 /* Set initial value to the reg itself. */
5785 /* We haven't seen the initializing insn yet */
5795 /* Add this class to ivs->list. */
5799 /* Put it in the array of biv register classes. */
5801 }
5802 else
5803 {
5804 /* Check if location is the same as a previous one. */
5808 {
5811 }
5812 }
5814 /* Update IV_CLASS entry for this biv. */
5823 }
5824 \f
5825 /* Fill in the data about one giv.
5826 V is the `struct induction' in which we record the giv. (It is
5827 allocated by the caller, with alloca.)
5828 INSN is the insn that sets it.
5829 BENEFIT estimates the savings from deleting this insn.
5830 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5831 into a register or is used as a memory address.
5833 SRC_REG is the biv reg which the giv is computed from.
5834 DEST_REG is the giv's reg (if the giv is stored in a reg).
5835 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5836 LOCATION points to the place where this giv's value appears in INSN. */
5838 static void
5843 rtx insn;
5844 rtx src_reg;
5845 rtx dest_reg;
5851 {
5856 rtx temp;
5858 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5859 undo the MULT canonicalization that we performed earlier. */
5889 /* The v->always_computable field is used in update_giv_derive, to
5890 determine whether a giv can be used to derive another giv. For a
5891 DEST_REG giv, INSN computes a new value for the giv, so its value
5892 isn't computable if INSN insn't executed every iteration.
5893 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5894 it does not compute a new value. Hence the value is always computable
5895 regardless of whether INSN is executed each iteration. */
5899 else
5905 {
5908 }
5910 {
5915 /* If the lifetime is zero, it means that this register is
5916 really a dead store. So mark this as a giv that can be
5917 ignored. This will not prevent the biv from being eliminated. */
5923 }
5925 /* Add the giv to the class of givs computed from one biv. */
5929 {
5932 /* Don't count DEST_ADDR. This is supposed to count the number of
5933 insns that calculate givs. */
5937 }
5938 else
5939 /* Fatal error, biv missing for this giv? */
5943 {
5946 }
5947 else
5948 {
5949 /* The giv can be replaced outright by the reduced register only if all
5950 of the following conditions are true:
5951 - the insn that sets the giv is always executed on any iteration
5952 on which the giv is used at all
5953 (there are two ways to deduce this:
5954 either the insn is executed on every iteration,
5955 or all uses follow that insn in the same basic block),
5956 - the giv is not used outside the loop
5957 - no assignments to the biv occur during the giv's lifetime. */
5960 /* Previous line always fails if INSN was moved by loop opt. */
5963 && (! not_every_iteration
5965 {
5966 /* Now check that there are no assignments to the biv within the
5967 giv's lifetime. This requires two separate checks. */
5969 /* Check each biv update, and fail if any are between the first
5970 and last use of the giv.
5972 If this loop contains an inner loop that was unrolled, then
5973 the insn modifying the biv may have been emitted by the loop
5974 unrolling code, and hence does not have a valid luid. Just
5975 mark the biv as not replaceable in this case. It is not very
5976 useful as a biv, because it is used in two different loops.
5977 It is very unlikely that we would be able to optimize the giv
5978 using this biv anyways. */
5983 {
5989 {
5993 }
5994 }
5996 /* If there are any backwards branches that go from after the
5997 biv update to before it, then this giv is not replaceable. */
6001 {
6005 }
6006 }
6007 else
6008 {
6009 /* May still be replaceable, we don't have enough info here to
6010 decide. */
6013 }
6014 }
6016 /* Record whether the add_val contains a const_int, for later use by
6017 combine_givs. */
6018 {
6023 ;
6027 {
6029 {
6034 else
6036 }
6039 }
6040 }
6044 }
6046 /* All this does is determine whether a giv can be made replaceable because
6047 its final value can be calculated. This code can not be part of record_giv
6048 above, because final_giv_value requires that the number of loop iterations
6049 be known, and that can not be accurately calculated until after all givs
6050 have been identified. */
6052 static void
6056 {
6059 /* DEST_ADDR givs will never reach here, because they are always marked
6060 replaceable above in record_giv. */
6062 /* The giv can be replaced outright by the reduced register only if all
6063 of the following conditions are true:
6064 - the insn that sets the giv is always executed on any iteration
6065 on which the giv is used at all
6066 (there are two ways to deduce this:
6067 either the insn is executed on every iteration,
6068 or all uses follow that insn in the same basic block),
6069 - its final value can be calculated (this condition is different
6070 than the one above in record_giv)
6071 - it's not used before the it's set
6072 - no assignments to the biv occur during the giv's lifetime. */
6074 #if 0
6075 /* This is only called now when replaceable is known to be false. */
6076 /* Clear replaceable, so that it won't confuse final_giv_value. */
6078 #endif
6083 {
6086 rtx last_giv_use;
6091 /* When trying to determine whether or not a biv increment occurs
6092 during the lifetime of the giv, we can ignore uses of the variable
6093 outside the loop because final_value is true. Hence we can not
6094 use regno_last_uid and regno_first_uid as above in record_giv. */
6096 /* Search the loop to determine whether any assignments to the
6097 biv occur during the giv's lifetime. Start with the insn
6098 that sets the giv, and search around the loop until we come
6099 back to that insn again.
6101 Also fail if there is a jump within the giv's lifetime that jumps
6102 to somewhere outside the lifetime but still within the loop. This
6103 catches spaghetti code where the execution order is not linear, and
6104 hence the above test fails. Here we assume that the giv lifetime
6105 does not extend from one iteration of the loop to the next, so as
6106 to make the test easier. Since the lifetime isn't known yet,
6107 this requires two loops. See also record_giv above. */
6112 {
6115 {
6118 }
6124 {
6125 /* It is possible for the BIV increment to use the GIV if we
6126 have a cycle. Thus we must be sure to check each insn for
6127 both BIV and GIV uses, and we must check for BIV uses
6128 first. */
6135 {
6137 {
6141 }
6143 }
6144 }
6145 }
6147 /* Now that the lifetime of the giv is known, check for branches
6148 from within the lifetime to outside the lifetime if it is still
6149 replaceable. */
6152 {
6155 {
6168 {
6177 }
6178 }
6179 }
6181 /* If it is replaceable, then save the final value. */
6184 }
6189 }
6190 \f
6191 /* Update the status of whether a giv can derive other givs.
6193 We need to do something special if there is or may be an update to the biv
6194 between the time the giv is defined and the time it is used to derive
6195 another giv.
6197 In addition, a giv that is only conditionally set is not allowed to
6198 derive another giv once a label has been passed.
6200 The cases we look at are when a label or an update to a biv is passed. */
6202 static void
6205 rtx p;
6206 {
6210 rtx tem;
6213 /* Search all IV classes, then all bivs, and finally all givs.
6215 There are three cases we are concerned with. First we have the situation
6216 of a giv that is only updated conditionally. In that case, it may not
6217 derive any givs after a label is passed.
6219 The second case is when a biv update occurs, or may occur, after the
6220 definition of a giv. For certain biv updates (see below) that are
6221 known to occur between the giv definition and use, we can adjust the
6222 giv definition. For others, or when the biv update is conditional,
6223 we must prevent the giv from deriving any other givs. There are two
6224 sub-cases within this case.
6226 If this is a label, we are concerned with any biv update that is done
6227 conditionally, since it may be done after the giv is defined followed by
6228 a branch here (actually, we need to pass both a jump and a label, but
6229 this extra tracking doesn't seem worth it).
6231 If this is a jump, we are concerned about any biv update that may be
6232 executed multiple times. We are actually only concerned about
6233 backward jumps, but it is probably not worth performing the test
6234 on the jump again here.
6236 If this is a biv update, we must adjust the giv status to show that a
6237 subsequent biv update was performed. If this adjustment cannot be done,
6238 the giv cannot derive further givs. */
6244 {
6246 {
6247 /* If cant_derive is already true, there is no point in
6248 checking all of these conditions again. */
6252 /* If this giv is conditionally set and we have passed a label,
6253 it cannot derive anything. */
6257 /* Skip givs that have mult_val == 0, since
6258 they are really invariants. Also skip those that are
6259 replaceable, since we know their lifetime doesn't contain
6260 any biv update. */
6264 /* The only way we can allow this giv to derive another
6265 is if this is a biv increment and we can form the product
6266 of biv->add_val and giv->mult_val. In this case, we will
6267 be able to compute a compensation. */
6269 {
6270 rtx ext_val_dummy;
6281 tem = simplify_giv_expr
6288 else
6290 }
6294 }
6295 }
6296 }
6297 \f
6298 /* Check whether an insn is an increment legitimate for a basic induction var.
6299 X is the source of insn P, or a part of it.
6300 MODE is the mode in which X should be interpreted.
6302 DEST_REG is the putative biv, also the destination of the insn.
6303 We accept patterns of these forms:
6304 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6305 REG = INVARIANT + REG
6307 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6308 store the additive term into *INC_VAL, and store the place where
6309 we found the additive term into *LOCATION.
6311 If X is an assignment of an invariant into DEST_REG, we set
6312 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6314 We also want to detect a BIV when it corresponds to a variable
6315 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6316 of the variable may be a PLUS that adds a SUBREG of that variable to
6317 an invariant and then sign- or zero-extends the result of the PLUS
6318 into the variable.
6320 Most GIVs in such cases will be in the promoted mode, since that is the
6321 probably the natural computation mode (and almost certainly the mode
6322 used for addresses) on the machine. So we view the pseudo-reg containing
6323 the variable as the BIV, as if it were simply incremented.
6325 Note that treating the entire pseudo as a BIV will result in making
6326 simple increments to any GIVs based on it. However, if the variable
6327 overflows in its declared mode but not its promoted mode, the result will
6328 be incorrect. This is acceptable if the variable is signed, since
6329 overflows in such cases are undefined, but not if it is unsigned, since
6330 those overflows are defined. So we only check for SIGN_EXTEND and
6331 not ZERO_EXTEND.
6333 If we cannot find a biv, we return 0. */
6335 static int
6338 rtx x;
6340 rtx dest_reg;
6341 rtx p;
6345 {
6353 {
6359 {
6361 }
6366 {
6368 }
6369 else
6382 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6383 handle addition of promoted variables.
6384 ??? The comment at the start of this function is wrong: promoted
6385 variable increments don't look like it says they do. */
6391 /* If this register is assigned in a previous insn, look at its
6392 source, but don't go outside the loop or past a label. */
6394 /* If this sets a register to itself, we would repeat any previous
6395 biv increment if we applied this strategy blindly. */
6401 {
6402 rtx dest;
6403 do
6404 {
6406 }
6435 }
6436 /* Fall through. */
6438 /* Can accept constant setting of biv only when inside inner most loop.
6439 Otherwise, a biv of an inner loop may be incorrectly recognized
6440 as a biv of the outer loop,
6441 causing code to be moved INTO the inner loop. */
6448 /* convert_modes aborts if we try to convert to or from CCmode, so just
6449 exclude that case. It is very unlikely that a condition code value
6450 would be a useful iterator anyways. convert_modes aborts if we try to
6451 convert a float mode to non-float or vice versa too. */
6455 {
6456 /* Possible bug here? Perhaps we don't know the mode of X. */
6460 }
6461 else
6465 /* Ignore this BIV if signed arithmetic overflow is defined. */
6472 /* Similar, since this can be a sign extension. */
6477 ;
6491 location);
6496 }
6497 }
6498 \f
6499 /* A general induction variable (giv) is any quantity that is a linear
6500 function of a basic induction variable,
6501 i.e. giv = biv * mult_val + add_val.
6502 The coefficients can be any loop invariant quantity.
6503 A giv need not be computed directly from the biv;
6504 it can be computed by way of other givs. */
6506 /* Determine whether X computes a giv.
6507 If it does, return a nonzero value
6508 which is the benefit from eliminating the computation of X;
6509 set *SRC_REG to the register of the biv that it is computed from;
6510 set *ADD_VAL and *MULT_VAL to the coefficients,
6511 such that the value of X is biv * mult + add; */
6513 static int
6517 rtx x;
6525 {
6529 /* If this is an invariant, forget it, it isn't a giv. */
6540 {
6543 /* Since this is now an invariant and wasn't before, it must be a giv
6544 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6545 with. */
6552 /* This is equivalent to a BIV. */
6559 /* Either (plus (biv) (invar)) or
6560 (plus (mult (biv) (invar_1)) (invar_2)). */
6562 {
6565 }
6566 else
6567 {
6570 }
6575 /* ADD_VAL is zero. */
6583 }
6585 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6586 unless they are CONST_INT). */
6594 else
6597 /* Always return true if this is a giv so it will be detected as such,
6598 even if the benefit is zero or negative. This allows elimination
6599 of bivs that might otherwise not be eliminated. */
6601 }
6602 \f
6603 /* Given an expression, X, try to form it as a linear function of a biv.
6604 We will canonicalize it to be of the form
6605 (plus (mult (BIV) (invar_1))
6606 (invar_2))
6607 with possible degeneracies.
6609 The invariant expressions must each be of a form that can be used as a
6610 machine operand. We surround then with a USE rtx (a hack, but localized
6611 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6612 routine; it is the caller's responsibility to strip them.
6614 If no such canonicalization is possible (i.e., two biv's are used or an
6615 expression that is neither invariant nor a biv or giv), this routine
6616 returns 0.
6618 For a nonzero return, the result will have a code of CONST_INT, USE,
6619 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6621 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6626 static rtx
6629 rtx x;
6632 {
6637 rtx tem;
6639 /* If this is not an integer mode, or if we cannot do arithmetic in this
6640 mode, this can't be a giv. */
6647 {
6654 /* Put constant last, CONST_INT last if both constant. */
6662 /* Handle addition of zero, then addition of an invariant. */
6667 {
6670 /* Adding two invariants must result in an invariant, so enclose
6671 addition operation inside a USE and return it. */
6681 else
6690 /* biv + invar or mult + invar. Return sum. */
6694 /* (a + invar_1) + invar_2. Associate. */
6695 return
6701 arg1)),
6706 }
6708 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6709 MULT to reduce cases. */
6715 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6716 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6717 Recurse to associate the second PLUS. */
6722 return
6730 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6746 /* Handle "a - b" as "a + b * (-1)". */
6752 constm1_rtx)),
6761 /* Put constant last, CONST_INT last if both constant. */
6766 /* If second argument is not now constant, not giv. */
6770 /* Handle multiply by 0 or 1. */
6778 {
6780 /* biv * invar. Done. */
6784 /* Product of two constants. */
6788 /* invar * invar is a giv, but attempt to simplify it somehow. */
6794 {
6795 /* (invar_0 * invar_1) * invar_2. Associate. */
6802 arg1)),
6804 }
6805 /* Propagate the MULT expressions to the intermost nodes. */
6807 {
6808 /* (invar_0 + invar_1) * invar_2. Distribute. */
6814 arg1),
6818 arg1)),
6820 }
6824 /* (a * invar_1) * invar_2. Associate. */
6830 arg1)),
6834 /* (a + invar_1) * invar_2. Distribute. */
6839 arg1),
6842 arg1)),
6847 }
6850 /* Shift by constant is multiply by power of two. */
6854 return
6863 /* "-a" is "a * (-1)" */
6869 /* "~a" is "-a - 1". Silly, but easy. */
6873 const1_rtx),
6877 /* Already in proper form for invariant. */
6883 /* Conditionally recognize extensions of simple IVs. After we've
6884 computed loop traversal counts and verified the range of the
6885 source IV, we'll reevaluate this as a GIV. */
6887 {
6890 {
6893 }
6894 }
6898 /* If this is a new register, we can't deal with it. */
6902 /* Check for biv or giv. */
6904 {
6908 {
6911 /* Form expression from giv and add benefit. Ensure this giv
6912 can derive another and subtract any needed adjustment if so. */
6914 /* Increasing the benefit here is risky. The only case in which it
6915 is arguably correct is if this is the only use of V. In other
6916 cases, this will artificially inflate the benefit of the current
6917 giv, and lead to suboptimal code. Thus, it is disabled, since
6918 potentially not reducing an only marginally beneficial giv is
6919 less harmful than reducing many givs that are not really
6920 beneficial. */
6921 {
6925 }
6938 {
6941 }
6942 else
6943 {
6946 }
6948 }
6951 do_default:
6952 /* If it isn't an induction variable, and it is invariant, we
6953 may be able to simplify things further by looking through
6954 the bits we just moved outside the loop. */
6956 {
6962 {
6963 /* Ok, we found a match. Substitute and simplify. */
6965 /* If we match another movable, we must use that, as
6966 this one is going away. */
6971 /* If consec is nonzero, this is a member of a group of
6972 instructions that were moved together. We handle this
6973 case only to the point of seeking to the last insn and
6974 looking for a REG_EQUAL. Fail if we don't find one. */
6976 {
6979 do
6980 {
6982 }
6988 }
6989 else
6990 {
6994 }
6997 {
6998 /* What we are most interested in is pointer
6999 arithmetic on invariants -- only take
7000 patterns we may be able to do something with. */
7006 {
7008 benefit);
7011 }
7016 {
7021 }
7022 }
7024 }
7025 }
7027 }
7029 /* Fall through to general case. */
7031 /* If invariant, return as USE (unless CONST_INT).
7032 Otherwise, not giv. */
7037 {
7046 }
7047 else
7049 }
7050 }
7052 /* This routine folds invariants such that there is only ever one
7053 CONST_INT in the summation. It is only used by simplify_giv_expr. */
7055 static rtx
7058 {
7064 {
7067 }
7070 {
7073 }
7074 else
7075 {
7078 }
7079 }
7081 static rtx
7085 {
7087 {
7091 else
7094 }
7097 else
7100 }
7101 \f
7102 /* Help detect a giv that is calculated by several consecutive insns;
7103 for example,
7104 giv = biv * M
7105 giv = giv + A
7106 The caller has already identified the first insn P as having a giv as dest;
7107 we check that all other insns that set the same register follow
7108 immediately after P, that they alter nothing else,
7109 and that the result of the last is still a giv.
7111 The value is 0 if the reg set in P is not really a giv.
7112 Otherwise, the value is the amount gained by eliminating
7113 all the consecutive insns that compute the value.
7115 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7116 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7118 The coefficients of the ultimate giv value are stored in
7119 *MULT_VAL and *ADD_VAL. */
7121 static int
7126 rtx p;
7127 rtx src_reg;
7128 rtx dest_reg;
7133 {
7139 rtx temp;
7140 rtx set;
7142 /* Indicate that this is a giv so that we can update the value produced in
7143 each insn of the multi-insn sequence.
7145 This induction structure will be used only by the call to
7146 general_induction_var below, so we can allocate it on our stack.
7147 If this is a giv, our caller will replace the induct var entry with
7148 a new induction structure. */
7169 {
7173 /* If libcall, skip to end of call sequence. */
7184 /* Giv created by equivalent expression. */
7190 {
7194 count--;
7198 }
7200 {
7201 /* Allow insns that set something other than this giv to a
7202 constant. Such insns are needed on machines which cannot
7203 include long constants and should not disqualify a giv. */
7212 }
7213 }
7218 }
7219 \f
7220 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7221 represented by G1. If no such expression can be found, or it is clear that
7222 it cannot possibly be a valid address, 0 is returned.
7224 To perform the computation, we note that
7225 G1 = x * v + a and
7226 G2 = y * v + b
7227 where `v' is the biv.
7229 So G2 = (y/b) * G1 + (b - a*y/x).
7231 Note that MULT = y/x.
7233 Update: A and B are now allowed to be additive expressions such that
7234 B contains all variables in A. That is, computing B-A will not require
7235 subtracting variables. */
7237 static rtx
7240 {
7241 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7246 /* If MULT is not 1, we cannot handle A with non-constants, since we
7247 would then be required to subtract multiples of the registers in A.
7248 This is theoretically possible, and may even apply to some Fortran
7249 constructs, but it is a lot of work and we do not attempt it here. */
7254 /* In general these structures are sorted top to bottom (down the PLUS
7255 chain), but not left to right across the PLUS. If B is a higher
7256 order giv than A, we can strip one level and recurse. If A is higher
7257 order, we'll eventually bail out, but won't know that until the end.
7258 If they are the same, we'll strip one level around this loop. */
7261 {
7273 /* We matched: remove one reg completely. */
7276 /* An alternate match. */
7279 /* An alternate match. */
7281 else
7282 {
7283 /* Indicates an extra register in B. Strip one level from B and
7284 recurse, hoping B was the higher order expression. */
7289 }
7290 }
7292 /* Here we are at the last level of A, go through the cases hoping to
7293 get rid of everything but a constant. */
7296 {
7309 }
7311 {
7313 }
7315 {
7320 }
7322 {
7327 else
7329 }
7334 }
7336 rtx
7339 {
7342 /* The value that G1 will be multiplied by must be a constant integer. Also,
7343 the only chance we have of getting a valid address is if b*c/a (see above
7344 for notation) is also an integer. */
7347 {
7352 }
7355 else
7356 {
7357 /* ??? Find out if the one is a multiple of the other? */
7359 }
7363 {
7364 /* Failed. If we've got a multiplication factor between G1 and G2,
7365 scale G1's addend and try again. */
7367 {
7371 {
7372 HOST_WIDE_INT m;
7376 }
7377 else
7378 {
7380 mult);
7381 }
7384 }
7385 }
7389 /* Form simplified final result. */
7394 else
7399 else
7400 {
7403 {
7407 }
7410 }
7411 }
7412 \f
7413 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7414 represented by G1. This indicates that G2 should be combined with G1 and
7415 that G2 can use (either directly or via an address expression) a register
7416 used to represent G1. */
7418 static rtx
7421 {
7424 /* With the introduction of ext dependent givs, we must care for modes.
7425 G2 must not use a wider mode than G1. */
7435 /* If these givs are identical, they can be combined. We use the results
7436 of express_from because the addends are not in a canonical form, so
7437 rtx_equal_p is a weaker test. */
7438 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7439 combination to be the other way round. */
7442 {
7444 }
7446 /* If G2 can be expressed as a function of G1 and that function is valid
7447 as an address and no more expensive than using a register for G2,
7448 the expression of G2 in terms of G1 can be used. */
7455 }
7456 \f
7457 /* Check each extension dependent giv in this class to see if its
7458 root biv is safe from wrapping in the interior mode, which would
7459 make the giv illegal. */
7461 static void
7465 {
7468 HOST_WIDE_INT start_val;
7474 /* Make sure the iteration data is available. We must have
7475 constants in order to be certain of no overflow. */
7476 /* ??? An unknown iteration count with an increment of +-1
7477 combined with friendly exit tests of against an invariant
7478 value is also amenable to optimization. Not implemented. */
7484 /* Make sure the host can represent the arithmetic. */
7486 {
7488 HOST_WIDE_INT s_end_val;
7500 /* Check for host arithmetic overflow. */
7502 {
7504 HOST_WIDE_INT s_max;
7511 /* Check zero extension of biv ok. */
7513 /* Check for host arithmetic overflow. */
7514 && (neg_incr
7517 /* Check for target arithmetic overflow. */
7518 && (neg_incr
7521 {
7523 }
7525 /* Check sign extension of biv ok. */
7526 /* ??? While it is true that overflow with signed and pointer
7527 arithmetic is undefined, I fear too many programmers don't
7528 keep this fact in mind -- myself included on occasion.
7529 So leave alone with the signed overflow optimizations. */
7531 /* Check for host arithmetic overflow. */
7532 && (neg_incr
7535 /* Check for target arithmetic overflow. */
7536 && (neg_incr
7539 {
7541 }
7542 }
7543 }
7545 /* Invalidate givs that fail the tests. */
7548 {
7553 {
7562 /* We don't know whether this value is being used as either
7563 signed or unsigned, so to safely truncate we must satisfy
7564 both. The initial check here verifies the BIV itself;
7565 once that is successful we may check its range wrt the
7566 derived GIV. */
7568 {
7572 /* We know from the above that both endpoints are nonnegative,
7573 and that there is no wrapping. Verify that both endpoints
7574 are within the (signed) range of the outer mode. */
7577 }
7582 }
7585 {
7587 {
7591 }
7592 }
7593 else
7594 {
7596 {
7601 else
7602 {
7607 else
7609 }
7614 }
7617 }
7618 }
7619 }
7621 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7623 rtx
7626 rtx value;
7627 {
7633 /* Recall that check_ext_dependent_givs verified that the known bounds
7634 of a biv did not overflow or wrap with respect to the extension for
7635 the giv. Therefore, constants need no additional adjustment. */
7639 /* Otherwise, we must adjust the value to compensate for the
7640 differing modes of the biv and the giv. */
7642 }
7643 \f
7644 struct combine_givs_stats
7645 {
7648 };
7650 static int
7654 {
7661 /* Stabilize the sort. */
7665 }
7667 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7668 any other. If so, point SAME to the giv combined with and set NEW_REG to
7669 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7670 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7672 static void
7676 {
7677 /* Additional benefit to add for being combined multiple times. */
7685 /* Count givs, because bl->giv_count is incorrect here. */
7689 giv_count++;
7691 giv_array
7702 {
7704 rtx single_use;
7709 /* If a DEST_REG GIV is used only once, do not allow it to combine
7710 with anything, for in doing so we will gain nothing that cannot
7711 be had by simply letting the GIV with which we would have combined
7712 to be reduced on its own. The losage shows up in particular with
7713 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7714 be seen elsewhere as well. */
7721 /* Add an additional weight for zero addends. */
7726 {
7727 rtx this_combine;
7732 {
7735 }
7736 }
7738 }
7740 /* Iterate, combining until we can't. */
7741 restart:
7745 {
7748 {
7754 }
7756 }
7759 {
7765 /* If it has already been combined, skip. */
7770 {
7773 /* If it has already been combined, skip. */
7775 {
7780 /* For destination, we now may replace by mem expression instead
7781 of register. This changes the costs considerably, so add the
7782 compensation. */
7792 /* ??? The new final_[bg]iv_value code does a much better job
7793 of finding replaceable giv's, and hence this code may no
7794 longer be necessary. */
7798 /* To help optimize the next set of combinations, remove
7799 this giv from the benefits of other potential mates. */
7801 {
7805 }
7812 }
7813 }
7815 /* To help optimize the next set of combinations, remove
7816 this giv from the benefits of other potential mates. */
7818 {
7820 {
7824 }
7828 /* We've finished with this giv, and everything it touched.
7829 Restart the combination so that proper weights for the
7830 rest of the givs are properly taken into account. */
7831 /* ??? Ideally we would compact the arrays at this point, so
7832 as to not cover old ground. But sanely compacting
7833 can_combine is tricky. */
7835 }
7836 }
7838 /* Clean up. */
7841 }
7842 \f
7843 /* Generate sequence for REG = B * M + A. */
7845 static rtx
7851 {
7852 rtx seq;
7853 rtx result;
7856 /* Use unsigned arithmetic. */
7864 }
7867 /* Update registers created in insn sequence SEQ. */
7869 static void
7872 rtx seq;
7873 {
7874 rtx insn;
7876 /* Update register info for alias analysis. */
7882 {
7885 {
7892 }
7893 }
7897 }
7900 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7902 void
7909 basic_block before_bb;
7910 rtx before_insn;
7911 {
7912 rtx seq;
7915 {
7918 }
7920 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7923 /* Increase the lifetime of any invariants moved further in code. */
7930 /* It is possible that the expansion created lots of new registers.
7931 Iterate over the sequence we just created and record them all. */
7933 }
7936 /* Emit insns in loop pre-header to set REG = B * M + A. */
7938 void
7945 {
7946 rtx seq;
7948 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7951 /* Increase the lifetime of any invariants moved further in code.
7952 ???? Is this really necessary? */
7959 /* It is possible that the expansion created lots of new registers.
7960 Iterate over the sequence we just created and record them all. */
7962 }
7965 /* Emit insns after loop to set REG = B * M + A. */
7967 void
7974 {
7975 rtx seq;
7977 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7982 /* It is possible that the expansion created lots of new registers.
7983 Iterate over the sequence we just created and record them all. */
7985 }
7989 /* Similar to gen_add_mult, but compute cost rather than generating
7990 sequence. */
7992 static int
7998 {
8008 {
8013 }
8016 }
8017 \f
8018 /* Test whether A * B can be computed without
8019 an actual multiply insn. Value is 1 if so.
8021 ??? This function stinks because it generates a ton of wasted RTL
8022 ??? and as a result fragments GC memory to no end. There are other
8023 ??? places in the compiler which are invoked a lot and do the same
8024 ??? thing, generate wasted RTL just to see if something is possible. */
8026 static int
8028 rtx a;
8029 rtx b;
8030 {
8031 rtx tmp;
8034 /* If only one is constant, make it B. */
8038 /* If first constant, both constant, so don't need multiply. */
8042 /* If second not constant, neither is constant, so would need multiply. */
8046 /* One operand is constant, so might not need multiply insn. Generate the
8047 code for the multiply and see if a call or multiply, or long sequence
8048 of insns is generated. */
8057 {
8060 {
8070 {
8073 }
8076 }
8077 }
8087 }
8088 \f
8089 /* Check to see if loop can be terminated by a "decrement and branch until
8090 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
8091 Also try reversing an increment loop to a decrement loop
8092 to see if the optimization can be performed.
8093 Value is nonzero if optimization was performed. */
8095 /* This is useful even if the architecture doesn't have such an insn,
8096 because it might change a loops which increments from 0 to n to a loop
8097 which decrements from n to 0. A loop that decrements to zero is usually
8098 faster than one that increments from zero. */
8100 /* ??? This could be rewritten to use some of the loop unrolling procedures,
8101 such as approx_final_value, biv_total_increment, loop_iterations, and
8102 final_[bg]iv_value. */
8104 static int
8108 {
8113 rtx reg;
8114 rtx jump_label;
8115 rtx final_value;
8116 rtx start_value;
8117 rtx new_add_val;
8118 rtx comparison;
8119 rtx before_comparison;
8120 rtx p;
8121 rtx jump;
8122 rtx first_compare;
8127 /* If last insn is a conditional branch, and the insn before tests a
8128 register value, try to optimize it. Otherwise, we can't do anything. */
8137 /* Try to compute whether the compare/branch at the loop end is one or
8138 two instructions. */
8144 else
8147 {
8148 /* If more than one condition is present to control the loop, then
8149 do not proceed, as this function does not know how to rewrite
8150 loop tests with more than one condition.
8152 Look backwards from the first insn in the last comparison
8153 sequence and see if we've got another comparison sequence. */
8155 rtx jump1;
8159 }
8161 /* Check all of the bivs to see if the compare uses one of them.
8162 Skip biv's set more than once because we can't guarantee that
8163 it will be zero on the last iteration. Also skip if the biv is
8164 used between its update and the test insn. */
8167 {
8172 first_compare))
8174 }
8179 /* Look for the case where the basic induction variable is always
8180 nonnegative, and equals zero on the last iteration.
8181 In this case, add a reg_note REG_NONNEG, which allows the
8182 m68k DBRA instruction to be used. */
8190 {
8191 /* Initial value must be greater than 0,
8192 init_val % -dec_value == 0 to ensure that it equals zero on
8193 the last iteration */
8199 {
8200 /* register always nonnegative, add REG_NOTE to branch */
8208 }
8210 /* If the decrement is 1 and the value was tested as >= 0 before
8211 the loop, then we can safely optimize. */
8213 {
8226 {
8234 }
8235 }
8236 }
8239 {
8240 /* Try to change inc to dec, so can apply above optimization. */
8241 /* Can do this if:
8242 all registers modified are induction variables or invariant,
8243 all memory references have non-overlapping addresses
8244 (obviously true if only one write)
8245 allow 2 insns for the compare/jump at the end of the loop. */
8246 /* Also, we must avoid any instructions which use both the reversed
8247 biv and another biv. Such instructions will fail if the loop is
8248 reversed. We meet this condition by requiring that either
8249 no_use_except_counting is true, or else that there is only
8250 one biv. */
8252 /* 1 if the iteration var is used only to count iterations. */
8254 /* 1 if the loop has no memory store, or it has a single memory store
8255 which is reversible. */
8261 {
8265 /* If there are no givs for this biv, and the only exit is the
8266 fall through at the end of the loop, then
8267 see if perhaps there are no uses except to count. */
8271 {
8276 /* An insn that sets the biv is okay. */
8277 ;
8279 /* An insn that doesn't mention the biv is okay. */
8280 ;
8283 {
8284 /* If either of these insns uses the biv and sets a pseudo
8285 that has more than one usage, then the biv has uses
8286 other than counting since it's used to derive a value
8287 that is used more than one time. */
8289 regs);
8291 {
8294 }
8295 }
8296 else
8297 {
8300 }
8301 }
8303 /* A biv has uses besides counting if it is used to set
8304 another biv. */
8308 {
8311 }
8312 }
8315 /* No need to worry about MEMs. */
8316 ;
8318 {
8323 /* If the loop has a single store, and the destination address is
8324 invariant, then we can't reverse the loop, because this address
8325 might then have the wrong value at loop exit.
8326 This would work if the source was invariant also, however, in that
8327 case, the insn should have been moved out of the loop. */
8330 {
8333 /* If we could prove that each of the memory locations
8334 written to was different, then we could reverse the
8335 store -- but we don't presently have any way of
8336 knowing that. */
8339 /* If the store depends on a register that is set after the
8340 store, it depends on the initial value, and is thus not
8341 reversible. */
8343 {
8350 }
8351 }
8352 }
8353 else
8356 /* This code only acts for innermost loops. Also it simplifies
8357 the memory address check by only reversing loops with
8358 zero or one memory access.
8359 Two memory accesses could involve parts of the same array,
8360 and that can't be reversed.
8361 If the biv is used only for counting, than we don't need to worry
8362 about all these things. */
8368 && reversible_mem_store
8373 {
8374 rtx tem;
8376 /* Loop can be reversed. */
8380 /* Now check other conditions:
8382 The increment must be a constant, as must the initial value,
8383 and the comparison code must be LT.
8385 This test can probably be improved since +/- 1 in the constant
8386 can be obtained by changing LT to LE and vice versa; this is
8387 confusing. */
8390 /* for constants, LE gets turned into LT */
8394 {
8405 comparison_const_width
8407 else
8408 comparison_const_width
8412 comparison_sign_mask
8415 /* If the comparison value is not a loop invariant, then we
8416 can not reverse this loop.
8418 ??? If the insns which initialize the comparison value as
8419 a whole compute an invariant result, then we could move
8420 them out of the loop and proceed with loop reversal. */
8428 /* Normalize the initial value if it is an integer and
8429 has no other use except as a counter. This will allow
8430 a few more loops to be reversed. */
8434 {
8436 /* The code below requires comparison_val to be a multiple
8437 of add_val in order to do the loop reversal, so
8438 round up comparison_val to a multiple of add_val.
8439 Since comparison_value is constant, we know that the
8440 current comparison code is LT. */
8442 comparison_val
8444 /* We postpone overflow checks for COMPARISON_VAL here;
8445 even if there is an overflow, we might still be able to
8446 reverse the loop, if converting the loop exit test to
8447 NE is possible. */
8449 }
8451 /* First check if we can do a vanilla loop reversal. */
8453 /* If we have a decrement_and_branch_on_count,
8454 prefer the NE test, since this will allow that
8455 instruction to be generated. Note that we must
8456 use a vanilla loop reversal if the biv is used to
8457 calculate a giv or has a non-counting use. */
8458 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8459 && defined (HAVE_decrement_and_branch_on_count)
8463 #endif
8465 /* Now do postponed overflow checks on COMPARISON_VAL. */
8468 {
8469 /* Register will always be nonnegative, with value
8470 0 on last iteration */
8474 }
8478 {
8481 }
8482 else
8488 /* If the initial value is not zero, or if the comparison
8489 value is not an exact multiple of the increment, then we
8490 can not reverse this loop. */
8493 {
8496 }
8497 else
8498 {
8501 }
8505 /* Reset these in case we normalized the initial value
8506 and comparison value above. */
8509 {
8511 final_value
8513 }
8516 /* Save some info needed to produce the new insns. */
8521 /* Set start_value; if this is not a CONST_INT, we need
8522 to generate a SUB.
8523 Initialize biv to start_value before loop start.
8524 The old initializing insn will be deleted as a
8525 dead store by flow.c. */
8528 {
8531 }
8533 {
8541 start_value
8547 }
8549 {
8552 initial_value);
8556 start_value
8559 }
8560 else
8561 /* We could handle the other cases too, but it'll be
8562 better to have a testcase first. */
8565 /* We may not have a single insn which can increment a reg, so
8566 create a sequence to hold all the insns from expand_inc. */
8575 /* Update biv info to reflect its new status. */
8580 /* Update loop info. */
8589 /* Inc LABEL_NUSES so that delete_insn will
8590 not delete the label. */
8593 /* Emit an insn after the end of the loop to set the biv's
8594 proper exit value if it is used anywhere outside the loop. */
8600 /* Delete compare/branch at end of loop. */
8605 /* Add new compare/branch insn at end of loop. */
8617 ;
8623 {
8625 {
8626 /* Increment of LABEL_NUSES done above. */
8627 /* Register is now always nonnegative,
8628 so add REG_NONNEG note to the branch. */
8631 }
8633 }
8635 /* No insn may reference both the reversed and another biv or it
8636 will fail (see comment near the top of the loop reversal
8637 code).
8638 Earlier on, we have verified that the biv has no use except
8639 counting, or it is the only biv in this function.
8640 However, the code that computes no_use_except_counting does
8641 not verify reg notes. It's possible to have an insn that
8642 references another biv, and has a REG_EQUAL note with an
8643 expression based on the reversed biv. To avoid this case,
8644 remove all REG_EQUAL notes based on the reversed biv
8645 here. */
8648 {
8651 /* If this is a set of a GIV based on the reversed biv, any
8652 REG_EQUAL notes should still be correct. */
8659 {
8664 else
8666 }
8667 }
8669 /* Mark that this biv has been reversed. Each giv which depends
8670 on this biv, and which is also live past the end of the loop
8671 will have to be fixed up. */
8676 {
8680 else
8682 }
8685 }
8686 }
8687 }
8690 }
8691 \f
8692 /* Verify whether the biv BL appears to be eliminable,
8693 based on the insns in the loop that refer to it.
8695 If ELIMINATE_P is nonzero, actually do the elimination.
8697 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8698 determine whether invariant insns should be placed inside or at the
8699 start of the loop. */
8701 static int
8707 {
8710 rtx p;
8712 /* Scan all insns in the loop, stopping if we find one that uses the
8713 biv in a way that we cannot eliminate. */
8716 {
8720 rtx note;
8722 /* If this is a libcall that sets a giv, skip ahead to its end. */
8724 {
8728 {
8733 {
8740 }
8741 }
8742 }
8744 /* Closely examine the insn if the biv is mentioned. */
8749 {
8755 }
8757 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8762 }
8765 {
8770 }
8773 }
8774 \f
8775 /* INSN and REFERENCE are instructions in the same insn chain.
8776 Return nonzero if INSN is first. */
8778 int
8781 {
8785 {
8786 /* Start with test for not first so that INSN == REFERENCE yields not
8787 first. */
8793 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8794 previous insn, hence the <= comparison below does not work if
8795 P is a note. */
8806 }
8807 }
8809 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8810 the offset that we have to take into account due to auto-increment /
8811 div derivation is zero. */
8812 static int
8815 rtx insn;
8816 {
8817 /* If the giv V had the auto-inc address optimization applied
8818 to it, and INSN occurs between the giv insn and the biv
8819 insn, then we'd have to adjust the value used here.
8820 This is rare, so we don't bother to make this possible. */
8829 }
8831 /* If BL appears in X (part of the pattern of INSN), see if we can
8832 eliminate its use. If so, return 1. If not, return 0.
8834 If BIV does not appear in X, return 1.
8836 If ELIMINATE_P is nonzero, actually do the elimination.
8837 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8838 Depending on how many items have been moved out of the loop, it
8839 will either be before INSN (when WHERE_INSN is nonzero) or at the
8840 start of the loop (when WHERE_INSN is zero). */
8842 static int
8848 basic_block where_bb;
8849 rtx where_insn;
8850 {
8856 #ifdef HAVE_cc0
8858 #endif
8864 {
8866 /* If we haven't already been able to do something with this BIV,
8867 we can't eliminate it. */
8873 /* If this sets the BIV, it is not a problem. */
8877 /* If this is an insn that defines a giv, it is also ok because
8878 it will go away when the giv is reduced. */
8883 #ifdef HAVE_cc0
8885 {
8886 /* Can replace with any giv that was reduced and
8887 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8888 Require a constant for MULT_VAL, so we know it's nonzero.
8889 ??? We disable this optimization to avoid potential
8890 overflows. */
8898 {
8905 /* If the giv has the opposite direction of change,
8906 then reverse the comparison. */
8910 else
8913 /* We can probably test that giv's reduced reg. */
8916 }
8918 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8919 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8920 Require a constant for MULT_VAL, so we know it's nonzero.
8921 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8922 overflow problem. */
8934 {
8941 /* If the giv has the opposite direction of change,
8942 then reverse the comparison. */
8946 else
8950 /* Replace biv with the giv's reduced register. */
8955 /* Insn doesn't support that constant or invariant. Copy it
8956 into a register (it will be a loop invariant.) */
8963 /* Substitute the new register for its invariant value in
8964 the compare expression. */
8968 }
8969 }
8970 #endif
8977 /* See if either argument is the biv. */
8982 else
8986 {
8987 /* First try to replace with any giv that has constant positive
8988 mult_val and constant add_val. We might be able to support
8989 negative mult_val, but it seems complex to do it in general. */
9001 {
9005 /* Don't eliminate if the linear combination that makes up
9006 the giv overflows when it is applied to ARG. */
9008 {
9009 rtx add_val;
9013 else
9019 }
9024 /* Replace biv with the giv's reduced reg. */
9027 /* If all constants are actually constant integers and
9028 the derived constant can be directly placed in the COMPARE,
9029 do so. */
9032 {
9035 }
9036 else
9037 {
9038 /* Otherwise, load it into a register. */
9043 }
9049 }
9051 /* Look for giv with positive constant mult_val and nonconst add_val.
9052 Insert insns to calculate new compare value.
9053 ??? Turn this off due to possible overflow. */
9061 {
9062 rtx tem;
9072 /* Replace biv with giv's reduced register. */
9076 /* Compute value to compare against. */
9080 /* Use it in this insn. */
9084 }
9085 }
9087 {
9089 {
9090 /* Look for giv with constant positive mult_val and nonconst
9091 add_val. Insert insns to compute new compare value.
9092 ??? Turn this off due to possible overflow. */
9099 {
9100 rtx tem;
9110 /* Replace biv with giv's reduced register. */
9114 /* Compute value to compare against. */
9121 }
9122 }
9124 /* This code has problems. Basically, you can't know when
9125 seeing if we will eliminate BL, whether a particular giv
9126 of ARG will be reduced. If it isn't going to be reduced,
9127 we can't eliminate BL. We can try forcing it to be reduced,
9128 but that can generate poor code.
9130 The problem is that the benefit of reducing TV, below should
9131 be increased if BL can actually be eliminated, but this means
9132 we might have to do a topological sort of the order in which
9133 we try to process biv. It doesn't seem worthwhile to do
9134 this sort of thing now. */
9136 #if 0
9137 /* Otherwise the reg compared with had better be a biv. */
9142 /* Look for a pair of givs, one for each biv,
9143 with identical coefficients. */
9145 {
9157 {
9164 /* Replace biv with its giv's reduced reg. */
9166 /* Replace other operand with the other giv's
9167 reduced reg. */
9170 }
9171 }
9172 #endif
9173 }
9175 /* If we get here, the biv can't be eliminated. */
9179 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9180 biv is used in it, since it will be replaced. */
9188 }
9190 /* See if any subexpression fails elimination. */
9193 {
9195 {
9208 }
9209 }
9212 }
9213 \f
9214 /* Return nonzero if the last use of REG
9215 is in an insn following INSN in the same basic block. */
9217 static int
9219 rtx reg;
9220 rtx insn;
9221 {
9222 rtx n;
9226 {
9229 }
9231 }
9232 \f
9233 /* Called via `note_stores' to record the initial value of a biv. Here we
9234 just record the location of the set and process it later. */
9236 static void
9238 rtx dest;
9239 rtx set;
9241 {
9252 /* If this is the first set found, record it. */
9254 {
9257 }
9258 }
9259 \f
9260 /* If any of the registers in X are "old" and currently have a last use earlier
9261 than INSN, update them to have a last use of INSN. Their actual last use
9262 will be the previous insn but it will not have a valid uid_luid so we can't
9263 use it. X must be a source expression only. */
9265 static void
9267 rtx x;
9268 rtx insn;
9269 {
9270 /* Check for the case where INSN does not have a valid luid. In this case,
9271 there is no need to modify the regno_last_uid, as this can only happen
9272 when code is inserted after the loop_end to set a pseudo's final value,
9273 and hence this insn will never be the last use of x.
9274 ???? This comment is not correct. See for example loop_givs_reduce.
9275 This may insert an insn before another new insn. */
9279 {
9281 }
9282 else
9283 {
9287 {
9293 }
9294 }
9295 }
9296 \f
9297 /* Given an insn INSN and condition COND, return the condition in a
9298 canonical form to simplify testing by callers. Specifically:
9300 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9301 (2) Both operands will be machine operands; (cc0) will have been replaced.
9302 (3) If an operand is a constant, it will be the second operand.
9303 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9304 for GE, GEU, and LEU.
9306 If the condition cannot be understood, or is an inequality floating-point
9307 comparison which needs to be reversed, 0 will be returned.
9309 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9311 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9312 insn used in locating the condition was found. If a replacement test
9313 of the condition is desired, it should be placed in front of that
9314 insn and we will be sure that the inputs are still valid.
9316 If WANT_REG is nonzero, we wish the condition to be relative to that
9317 register, if possible. Therefore, do not canonicalize the condition
9318 further. */
9320 rtx
9322 rtx insn;
9323 rtx cond;
9326 rtx want_reg;
9327 {
9330 rtx set;
9331 rtx tem;
9349 /* If we are comparing a register with zero, see if the register is set
9350 in the previous insn to a COMPARE or a comparison operation. Perform
9351 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9352 in cse.c */
9357 {
9358 /* Set nonzero when we find something of interest. */
9361 #ifdef HAVE_cc0
9362 /* If comparison with cc0, import actual comparison from compare
9363 insn. */
9365 {
9376 }
9377 #endif
9379 /* If this is a COMPARE, pick up the two things being compared. */
9381 {
9385 }
9389 /* Go back to the previous insn. Stop if it is not an INSN. We also
9390 stop if it isn't a single set or if it has a REG_INC note because
9391 we don't want to bother dealing with it. */
9405 /* If this is setting OP0, get what it sets it to if it looks
9406 relevant. */
9408 {
9410 #ifdef FLOAT_STORE_FLAG_VALUE
9411 REAL_VALUE_TYPE fsfv;
9412 #endif
9414 /* ??? We may not combine comparisons done in a CCmode with
9415 comparisons not done in a CCmode. This is to aid targets
9416 like Alpha that have an IEEE compliant EQ instruction, and
9417 a non-IEEE compliant BEQ instruction. The use of CCmode is
9418 actually artificial, simply to prevent the combination, but
9419 should not affect other platforms.
9421 However, we must allow VOIDmode comparisons to match either
9422 CCmode or non-CCmode comparison, because some ports have
9423 modeless comparisons inside branch patterns.
9425 ??? This mode check should perhaps look more like the mode check
9426 in simplify_comparison in combine. */
9434 && (STORE_FLAG_VALUE
9437 #ifdef FLOAT_STORE_FLAG_VALUE
9442 #endif
9443 ))
9454 && (STORE_FLAG_VALUE
9457 #ifdef FLOAT_STORE_FLAG_VALUE
9462 #endif
9463 ))
9469 {
9472 }
9473 else
9475 }
9478 /* If this sets OP0, but not directly, we have to give up. */
9482 {
9486 {
9491 }
9496 }
9497 }
9499 /* If constant is first, put it last. */
9503 /* If OP0 is the result of a comparison, we weren't able to find what
9504 was really being compared, so fail. */
9508 /* Canonicalize any ordered comparison with integers involving equality
9509 if we can do computations in the relevant mode and we do not
9510 overflow. */
9515 {
9518 unsigned HOST_WIDE_INT max_val
9522 {
9528 /* When cross-compiling, const_val might be sign-extended from
9529 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9549 }
9550 }
9552 /* Never return CC0; return zero instead. */
9557 }
9559 /* Given a jump insn JUMP, return the condition that will cause it to branch
9560 to its JUMP_LABEL. If the condition cannot be understood, or is an
9561 inequality floating-point comparison which needs to be reversed, 0 will
9562 be returned.
9564 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9565 insn used in locating the condition was found. If a replacement test
9566 of the condition is desired, it should be placed in front of that
9567 insn and we will be sure that the inputs are still valid. */
9569 rtx
9571 rtx jump;
9573 {
9574 rtx cond;
9576 rtx set;
9578 /* If this is not a standard conditional jump, we can't parse it. */
9586 /* If this branches to JUMP_LABEL when the condition is false, reverse
9587 the condition. */
9588 reverse
9593 }
9595 /* Similar to above routine, except that we also put an invariant last
9596 unless both operands are invariants. */
9598 rtx
9601 rtx x;
9602 {
9612 }
9614 /* Scan the function and determine whether it has indirect (computed) jumps.
9616 This is taken mostly from flow.c; similar code exists elsewhere
9617 in the compiler. It may be useful to put this into rtlanal.c. */
9618 static int
9620 rtx start;
9621 {
9622 rtx insn;
9629 }
9631 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9632 documentation for LOOP_MEMS for the definition of `appropriate'.
9633 This function is called from prescan_loop via for_each_rtx. */
9635 static int
9639 {
9648 {
9653 /* We're not interested in MEMs that are only clobbered. */
9657 /* We're not interested in the MEM associated with a
9658 CONST_DOUBLE, so there's no need to traverse into this. */
9662 /* We're not interested in any MEMs that only appear in notes. */
9666 /* This is not a MEM. */
9668 }
9670 /* See if we've already seen this MEM. */
9673 {
9675 /* The modes of the two memory accesses are different. If
9676 this happens, something tricky is going on, and we just
9677 don't optimize accesses to this MEM. */
9681 }
9683 /* Resize the array, if necessary. */
9685 {
9688 else
9694 }
9696 /* Actually insert the MEM. */
9698 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9699 because we can't put it in a register. We still store it in the
9700 table, though, so that if we see the same address later, but in a
9701 non-BLK mode, we'll not think we can optimize it at that point. */
9707 }
9710 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9712 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9713 register that is modified by an insn between FROM and TO. If the
9714 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9715 more, stop incrementing it, to avoid overflow.
9717 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9718 register I is used, if it is only used once. Otherwise, it is set
9719 to 0 (for no uses) or const0_rtx for more than one use. This
9720 parameter may be zero, in which case this processing is not done.
9722 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9723 optimize register I. */
9725 static void
9729 {
9732 /* last_set[n] is nonzero iff reg n has been set in the current
9733 basic block. In that case, it is the insn that last set reg n. */
9735 rtx insn;
9741 /* Grow the regs array if not allocated or too small. */
9743 {
9749 /* Zero the new elements. */
9752 }
9754 /* Clear previously scanned fields but do not clear n_times_set. */
9756 {
9760 }
9764 /* Scan the loop, recording register usage. */
9767 {
9769 {
9770 /* Record registers that have exactly one use. */
9773 /* Include uses in REG_EQUAL notes. */
9781 {
9785 last_set);
9786 }
9787 }
9792 /* Invalidate all registers used for function argument passing.
9793 We check rtx_varies_p for the same reason as below, to allow
9794 optimizing PIC calculations. */
9796 {
9797 rtx link;
9799 link;
9801 {
9808 }
9809 }
9810 }
9812 /* Invalidate all hard registers clobbered by calls. With one exception:
9813 a call-clobbered PIC register is still function-invariant for our
9814 purposes, since we can hoist any PIC calculations out of the loop.
9815 Thus the call to rtx_varies_p. */
9820 {
9823 }
9825 #ifdef AVOID_CCMODE_COPIES
9826 /* Don't try to move insns which set CC registers if we should not
9827 create CCmode register copies. */
9831 #endif
9833 /* Set regs->array[I].n_times_set for the new registers. */
9838 }
9840 /* Returns the number of real INSNs in the LOOP. */
9842 static int
9845 {
9847 rtx insn;
9855 }
9857 /* Move MEMs into registers for the duration of the loop. */
9859 static void
9862 {
9869 rtx end_label;
9870 /* Nonzero if the next instruction may never be executed. */
9877 /* We cannot use next_label here because it skips over normal insns. */
9882 /* Check to see if it's possible that some instructions in the loop are
9883 never executed. Also check if there is a goto out of the loop other
9884 than right after the end of the loop. */
9888 {
9892 /* If we enter the loop in the middle, and scan
9893 around to the beginning, don't set maybe_never
9894 for that. This must be an unconditional jump,
9895 otherwise the code at the top of the loop might
9896 never be executed. Unconditional jumps are
9897 followed a by barrier then loop end. */
9902 {
9903 /* If this is a jump outside of the loop but not right
9904 after the end of the loop, we would have to emit new fixup
9905 sequences for each such label. */
9907 JUMP_INSN is executed, we must be conservative. */
9916 /* Something complicated. */
9918 else
9919 /* If there are any more instructions in the loop, they
9920 might not be reached. */
9922 }
9925 }
9927 /* Find start of the extended basic block that enters the loop. */
9931 ;
9936 /* Build table of mems that get set to constant values before the
9937 loop. */
9941 /* Actually move the MEMs. */
9943 {
9944 regset_head load_copies;
9945 regset_head store_copies;
9947 rtx reg;
9949 rtx mem_list_entry;
9953 /* There's no telling whether or not MEM is modified. */
9956 /* Go through the MEMs written to in the loop to see if this
9957 one is aliased by one of them. */
9960 {
9965 {
9966 /* MEM is indeed aliased by this store. */
9969 }
9971 }
9977 /* If this MEM is written to, we must be sure that there
9978 are no reads from another MEM that aliases this one. */
9980 {
9984 {
9988 VOIDmode,
9990 rtx_varies_p))
9991 {
9992 /* It's not safe to hoist loop_info->mems[i] out of
9993 the loop because writes to it might not be
9994 seen by reads from loop_info->mems[j]. */
9997 }
9998 }
9999 }
10002 /* We can't access the MEM outside the loop; it might
10003 cause a trap that wouldn't have happened otherwise. */
10007 /* We thought we were going to lift this MEM out of the
10008 loop, but later discovered that we could not. */
10014 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
10015 order to keep scan_loop from moving stores to this MEM
10016 out of the loop just because this REG is neither a
10017 user-variable nor used in the loop test. */
10022 /* Now, replace all references to the MEM with the
10023 corresponding pseudos. */
10028 {
10030 {
10031 rtx set;
10035 /* See if this copies the mem into a register that isn't
10036 modified afterwards. We'll try to do copy propagation
10037 a little further on. */
10039 /* @@@ This test is _way_ too conservative. */
10040 && ! maybe_never
10048 /* See if this copies the mem from a register that isn't
10049 modified afterwards. We'll try to remove the
10050 redundant copy later on by doing a little register
10051 renaming and copy propagation. This will help
10052 to untangle things for the BIV detection code. */
10054 && ! maybe_never
10062 /* If this is a call which uses / clobbers this memory
10063 location, we must not change the interface here. */
10067 {
10071 }
10072 else
10073 /* Replace the memory reference with the shadow register. */
10076 }
10081 }
10086 /* We couldn't replace all occurrences of the MEM. */
10088 else
10089 {
10090 /* Load the memory immediately before LOOP->START, which is
10091 the NOTE_LOOP_BEG. */
10093 rtx set;
10099 {
10103 {
10107 /* Extending hard register lifetimes causes crash
10108 on SRC targets. Doing so on non-SRC is
10109 probably also not good idea, since we most
10110 probably have pseudoregister equivalence as
10111 well. */
10114 }
10115 /* Use the constant equivalence if that is cheap enough. */
10121 {
10124 }
10126 /* If best_equiv is nonzero, we know that MEM is set to a
10127 constant or register before the loop. We will use this
10128 knowledge to initialize the shadow register with that
10129 constant or reg rather than by loading from MEM. */
10132 }
10137 {
10140 {
10143 }
10144 }
10150 {
10152 {
10155 }
10157 /* Store the memory immediately after END, which is
10158 the NOTE_LOOP_END. */
10161 }
10164 {
10169 }
10171 /* Attempt a bit of copy propagation. This helps untangle the
10172 data flow, and enables {basic,general}_induction_var to find
10173 more bivs/givs. */
10174 EXECUTE_IF_SET_IN_REG_SET
10176 {
10178 });
10181 EXECUTE_IF_SET_IN_REG_SET
10183 {
10185 });
10187 }
10188 }
10191 {
10192 /* Now, we need to replace all references to the previous exit
10193 label with the new one. */
10194 replace_label_data rr;
10200 {
10202 }
10203 }
10206 }
10208 /* For communication between note_reg_stored and its caller. */
10209 struct note_reg_stored_arg
10210 {
10212 rtx reg;
10213 };
10215 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10216 is equal to ARG. */
10217 static void
10221 {
10225 }
10227 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10228 There must be exactly one insn that sets this pseudo; it will be
10229 deleted if all replacements succeed and we can prove that the register
10230 is not used after the loop. */
10232 static void
10235 rtx replacement;
10237 {
10238 /* This is the reg that we are copying from. */
10241 rtx insn;
10242 /* These help keep track of whether we replaced all uses of the reg. */
10249 {
10250 rtx set;
10252 /* Only substitute within one extended basic block from the initializing
10253 insn. */
10260 /* Is this the initializing insn? */
10265 {
10272 }
10274 /* Only substitute after seeing the initializing insn. */
10276 {
10283 /* Stop replacing when REPLACEMENT is modified. */
10288 {
10291 /* It is possible that we've turned previously valid REG_EQUAL to
10292 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10293 REPLACEMENT is modified, we get different meaning. */
10297 }
10298 }
10299 }
10303 {
10307 {
10308 rtx first;
10309 rtx retval_note;
10311 /* Assume we're just deleting INIT_INSN. */
10313 /* Look for REG_RETVAL note. If we're deleting the end of
10314 the libcall sequence, the whole sequence can go. */
10316 /* If we found a REG_RETVAL note, find the first instruction
10317 in the sequence. */
10321 /* Delete the instructions. */
10323 }
10326 }
10327 }
10329 /* Replace all the instructions from FIRST up to and including LAST
10330 with NOTE_INSN_DELETED notes. */
10332 static void
10334 rtx first;
10335 rtx last;
10336 {
10338 {
10344 /* If this was the LAST instructions we're supposed to delete,
10345 we're done. */
10350 }
10351 }
10353 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10354 loop LOOP if the order of the sets of these registers can be
10355 swapped. There must be exactly one insn within the loop that sets
10356 this pseudo followed immediately by a move insn that sets
10357 REPLACEMENT with REGNO. */
10358 static void
10361 rtx replacement;
10363 {
10364 rtx insn;
10373 {
10374 /* Search for the insn that copies REGNO to NEW_REGNO? */
10382 }
10385 {
10386 rtx prev_insn;
10387 rtx prev_set;
10389 /* Some DEF-USE info would come in handy here to make this
10390 function more general. For now, just check the previous insn
10391 which is the most likely candidate for setting REGNO. */
10399 {
10400 /* We have:
10401 (set (reg regno) (expr))
10402 (set (reg new_regno) (reg regno))
10404 so try converting this to:
10405 (set (reg new_regno) (expr))
10406 (set (reg regno) (reg new_regno))
10408 The former construct is often generated when a global
10409 variable used for an induction variable is shadowed by a
10410 register (NEW_REGNO). The latter construct improves the
10411 chances of GIV replacement and BIV elimination. */
10421 {
10428 /* Update first use of REGNO. */
10432 /* Now perform copy propagation to hopefully
10433 remove all uses of REGNO within the loop. */
10435 }
10436 }
10437 }
10438 }
10440 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10442 static int
10446 {
10448 {
10452 }
10454 }
10456 /* Returns the first MEM found in NOTE by depth-first search. */
10458 static rtx
10460 rtx note;
10461 {
10465 }
10467 /* Replace MEM with its associated pseudo register. This function is
10468 called from load_mems via for_each_rtx. DATA is actually a pointer
10469 to a structure describing the instruction currently being scanned
10470 and the MEM we are currently replacing. */
10472 static int
10476 {
10484 {
10489 /* We're not interested in the MEM associated with a
10490 CONST_DOUBLE, so there's no need to traverse into one. */
10494 /* This is not a MEM. */
10496 }
10499 /* This is not the MEM we are currently replacing. */
10502 /* Actually replace the MEM. */
10506 }
10508 static void
10510 rtx insn;
10511 rtx mem;
10512 rtx reg;
10514 {
10515 loop_replace_args args;
10523 /* If we hoist a mem write out of the loop, then REG_EQUAL
10524 notes referring to the mem are no longer valid. */
10526 {
10531 {
10535 {
10536 /* Remove the note. */
10539 }
10540 }
10541 }
10542 }
10544 /* Replace one register with another. Called through for_each_rtx; PX points
10545 to the rtx being scanned. DATA is actually a pointer to
10546 a structure of arguments. */
10548 static int
10552 {
10563 }
10565 static void
10567 rtx insn;
10568 rtx reg;
10569 rtx replacement;
10570 {
10571 loop_replace_args args;
10578 }
10579 \f
10580 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10581 (ignored in the interim). */
10583 static rtx
10586 basic_block where_bb ATTRIBUTE_UNUSED;
10587 rtx where_insn;
10588 rtx pattern;
10589 {
10591 }
10594 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10595 in basic block WHERE_BB (ignored in the interim) within the loop
10596 otherwise hoist PATTERN into the loop pre-header. */
10598 rtx
10601 basic_block where_bb ATTRIBUTE_UNUSED;
10602 rtx where_insn;
10603 rtx pattern;
10604 {
10608 }
10611 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10612 WHERE_BB (ignored in the interim) within the loop. */
10614 static rtx
10617 basic_block where_bb ATTRIBUTE_UNUSED;
10618 rtx where_insn;
10619 rtx pattern;
10620 {
10622 }
10625 /* Hoist insn for PATTERN into the loop pre-header. */
10627 rtx
10630 rtx pattern;
10631 {
10633 }
10636 /* Hoist call insn for PATTERN into the loop pre-header. */
10638 static rtx
10641 rtx pattern;
10642 {
10644 }
10647 /* Sink insn for PATTERN after the loop end. */
10649 rtx
10652 rtx pattern;
10653 {
10655 }
10657 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10658 and constant. Emit sequence of instructions to load it into REG. */
10659 static rtx
10662 {
10663 rtx seq;
10671 }
10673 /* If the loop has multiple exits, emit insn for PATTERN before the
10674 loop to ensure that it will always be executed no matter how the
10675 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10676 since this is slightly more efficient. */
10678 static rtx
10681 rtx pattern;
10682 {
10685 else
10687 }
10688 \f
10689 static void
10694 {
10702 iv_num++;
10707 {
10710 }
10711 }
10714 static void
10719 {
10721 rtx incr;
10732 {
10735 }
10737 {
10740 }
10744 {
10748 }
10751 {
10755 }
10757 /* List the increments. */
10759 {
10763 }
10765 /* List the givs. */
10767 {
10772 else
10775 }
10776 }
10779 static void
10784 {
10795 {
10799 }
10802 }
10805 static void
10810 {
10817 else
10833 {
10835 {
10847 }
10848 }
10859 {
10863 }
10866 }
10869 void
10872 {
10874 }
10877 void
10880 {
10882 }
10885 void
10888 {
10890 }
10893 void
10896 {
10898 }
10901 #define LOOP_BLOCK_NUM_1(INSN) \
10902 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10904 /* The notes do not have an assigned block, so look at the next insn. */
10905 #define LOOP_BLOCK_NUM(INSN) \
10906 ((INSN) ? (GET_CODE (INSN) == NOTE \
10907 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10908 : LOOP_BLOCK_NUM_1 (INSN)) \
10909 : -1)
10911 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10913 static void
10918 {
10919 rtx label;
10924 /* Print diagnostics to compare our concept of a loop with
10925 what the loop notes say. */
10940 {
10960 {
10963 {
10966 }
10967 }
10970 /* This can happen when a marked loop appears as two nested loops,
10971 say from while (a || b) {}. The inner loop won't match
10972 the loop markers but the outer one will. */
10975 }
10976 }
10978 /* Call this function from the debugger to dump LOOP. */
10980 void
10983 {
10985 }
10987 /* Call this function from the debugger to dump LOOPS. */
10989 void
10992 {
10994 }