1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
64 #include "coretypes.h"
66 #include "hard-reg-set.h"
72 #include "insn-config.h"
73 #include "insn-attr.h"
78 #include "integrate.h"
82 #include "tree-pass.h"
87 /* Next quantity number available for allocation. */
91 /* Information we maintain about each quantity. */
94 /* The number of refs to quantity Q. */
98 /* The frequency of uses of quantity Q. */
102 /* Insn number (counting from head of basic block)
103 where quantity Q was born. -1 if birth has not been recorded. */
107 /* Insn number (counting from head of basic block)
108 where given quantity died. Due to the way tying is done,
109 and the fact that we consider in this pass only regs that die but once,
110 a quantity can die only once. Each quantity's life span
111 is a set of consecutive insns. -1 if death has not been recorded. */
115 /* Number of words needed to hold the data in given quantity.
116 This depends on its machine mode. It is used for these purposes:
117 1. It is used in computing the relative importance of qtys,
118 which determines the order in which we look for regs for them.
119 2. It is used in rules that prevent tying several registers of
120 different sizes in a way that is geometrically impossible
121 (see combine_regs). */
125 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
129 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
131 int freq_calls_crossed
;
133 /* Number of times a reg tied to given qty lives across a CALL_INSN
136 int n_throwing_calls_crossed
;
138 /* The register number of one pseudo register whose reg_qty value is Q.
139 This register should be the head of the chain
140 maintained in reg_next_in_qty. */
144 /* Reg class contained in (smaller than) the preferred classes of all
145 the pseudo regs that are tied in given quantity.
146 This is the preferred class for allocating that quantity. */
148 enum reg_class min_class
;
150 /* Register class within which we allocate given qty if we can't get
151 its preferred class. */
153 enum reg_class alternate_class
;
155 /* This holds the mode of the registers that are tied to given qty,
156 or VOIDmode if registers with differing modes are tied together. */
158 enum machine_mode mode
;
160 /* the hard reg number chosen for given quantity,
161 or -1 if none was found. */
166 static struct qty
*qty
;
168 /* These fields are kept separately to speedup their clearing. */
170 /* We maintain two hard register sets that indicate suggested hard registers
171 for each quantity. The first, phys_copy_sugg, contains hard registers
172 that are tied to the quantity by a simple copy. The second contains all
173 hard registers that are tied to the quantity via an arithmetic operation.
175 The former register set is given priority for allocation. This tends to
176 eliminate copy insns. */
178 /* Element Q is a set of hard registers that are suggested for quantity Q by
181 static HARD_REG_SET
*qty_phys_copy_sugg
;
183 /* Element Q is a set of hard registers that are suggested for quantity Q by
186 static HARD_REG_SET
*qty_phys_sugg
;
188 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
190 static short *qty_phys_num_copy_sugg
;
192 /* Element Q is the number of suggested registers in qty_phys_sugg. */
194 static short *qty_phys_num_sugg
;
196 /* If (REG N) has been assigned a quantity number, is a register number
197 of another register assigned the same quantity number, or -1 for the
198 end of the chain. qty->first_reg point to the head of this chain. */
200 static int *reg_next_in_qty
;
202 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
204 of -1 if this register cannot be allocated by local-alloc,
205 or -2 if not known yet.
207 Note that if we see a use or death of pseudo register N with
208 reg_qty[N] == -2, register N must be local to the current block. If
209 it were used in more than one block, we would have reg_qty[N] == -1.
210 This relies on the fact that if reg_basic_block[N] is >= 0, register N
211 will not appear in any other block. We save a considerable number of
212 tests by exploiting this.
214 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
219 /* The offset (in words) of register N within its quantity.
220 This can be nonzero if register N is SImode, and has been tied
221 to a subreg of a DImode register. */
223 static char *reg_offset
;
225 /* Vector of substitutions of register numbers,
226 used to map pseudo regs into hardware regs.
227 This is set up as a result of register allocation.
228 Element N is the hard reg assigned to pseudo reg N,
229 or is -1 if no hard reg was assigned.
230 If N is a hard reg number, element N is N. */
234 /* Set of hard registers live at the current point in the scan
235 of the instructions in a basic block. */
237 static HARD_REG_SET regs_live
;
239 /* Each set of hard registers indicates registers live at a particular
240 point in the basic block. For N even, regs_live_at[N] says which
241 hard registers are needed *after* insn N/2 (i.e., they may not
242 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
244 If an object is to conflict with the inputs of insn J but not the
245 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
246 if it is to conflict with the outputs of insn J but not the inputs of
247 insn J + 1, it is said to die at index J*2 + 1. */
249 static HARD_REG_SET
*regs_live_at
;
251 /* Communicate local vars `insn_number' and `insn'
252 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
253 static int this_insn_number
;
254 static rtx this_insn
;
258 /* Set when an attempt should be made to replace a register
259 with the associated src_p entry. */
263 /* Set when a REG_EQUIV note is found or created. Use to
264 keep track of what memory accesses might be created later,
271 /* Loop depth is used to recognize equivalences which appear
272 to be present within the same loop (or in an inner loop). */
276 /* The list of each instruction which initializes this register. */
280 /* Nonzero if this had a preexisting REG_EQUIV note. */
282 int is_arg_equivalence
;
285 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
286 structure for that register. */
288 static struct equivalence
*reg_equiv
;
290 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
291 static int recorded_label_ref
;
293 static void alloc_qty (int, enum machine_mode
, int, int);
294 static void validate_equiv_mem_from_store (rtx
, const_rtx
, void *);
295 static int validate_equiv_mem (rtx
, rtx
, rtx
);
296 static int equiv_init_varies_p (rtx
);
297 static int equiv_init_movable_p (rtx
, int);
298 static int contains_replace_regs (rtx
);
299 static int memref_referenced_p (rtx
, rtx
);
300 static int memref_used_between_p (rtx
, rtx
, rtx
);
301 static void update_equiv_regs (void);
302 static void no_equiv (rtx
, const_rtx
, void *);
303 static void block_alloc (int);
304 static int qty_sugg_compare (int, int);
305 static int qty_sugg_compare_1 (const void *, const void *);
306 static int qty_compare (int, int);
307 static int qty_compare_1 (const void *, const void *);
308 static int combine_regs (rtx
, rtx
, int, int, rtx
, int);
309 static int reg_meets_class_p (int, enum reg_class
);
310 static void update_qty_class (int, int);
311 static void reg_is_set (rtx
, const_rtx
, void *);
312 static void reg_is_born (rtx
, int);
313 static void wipe_dead_reg (rtx
, int);
314 static int find_free_reg (enum reg_class
, enum machine_mode
, int, int, int,
316 static void mark_life (int, enum machine_mode
, int);
317 static void post_mark_life (int, enum machine_mode
, int, int, int);
318 static int no_conflict_p (rtx
, rtx
, rtx
);
319 static int requires_inout (const char *);
321 /* Allocate a new quantity (new within current basic block)
322 for register number REGNO which is born at index BIRTH
323 within the block. MODE and SIZE are info on reg REGNO. */
326 alloc_qty (int regno
, enum machine_mode mode
, int size
, int birth
)
328 int qtyno
= next_qty
++;
330 reg_qty
[regno
] = qtyno
;
331 reg_offset
[regno
] = 0;
332 reg_next_in_qty
[regno
] = -1;
334 qty
[qtyno
].first_reg
= regno
;
335 qty
[qtyno
].size
= size
;
336 qty
[qtyno
].mode
= mode
;
337 qty
[qtyno
].birth
= birth
;
338 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
339 qty
[qtyno
].freq_calls_crossed
= REG_FREQ_CALLS_CROSSED (regno
);
340 qty
[qtyno
].n_throwing_calls_crossed
= REG_N_THROWING_CALLS_CROSSED (regno
);
341 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
342 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
343 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
344 qty
[qtyno
].freq
= REG_FREQ (regno
);
347 /* Main entry point of this file. */
356 /* We need to keep track of whether or not we recorded a LABEL_REF so
357 that we know if the jump optimizer needs to be rerun. */
358 recorded_label_ref
= 0;
360 /* Leaf functions and non-leaf functions have different needs.
361 If defined, let the machine say what kind of ordering we
363 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
364 ORDER_REGS_FOR_LOCAL_ALLOC
;
367 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
369 update_equiv_regs ();
371 /* This sets the maximum number of quantities we can have. Quantity
372 numbers start at zero and we can have one for each pseudo. */
373 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
375 /* Allocate vectors of temporary data.
376 See the declarations of these variables, above,
377 for what they mean. */
379 qty
= XNEWVEC (struct qty
, max_qty
);
380 qty_phys_copy_sugg
= XNEWVEC (HARD_REG_SET
, max_qty
);
381 qty_phys_num_copy_sugg
= XNEWVEC (short, max_qty
);
382 qty_phys_sugg
= XNEWVEC (HARD_REG_SET
, max_qty
);
383 qty_phys_num_sugg
= XNEWVEC (short, max_qty
);
385 reg_qty
= XNEWVEC (int, max_regno
);
386 reg_offset
= XNEWVEC (char, max_regno
);
387 reg_next_in_qty
= XNEWVEC (int, max_regno
);
389 /* Determine which pseudo-registers can be allocated by local-alloc.
390 In general, these are the registers used only in a single block and
393 We need not be concerned with which block actually uses the register
394 since we will never see it outside that block. */
396 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
398 if (REG_BASIC_BLOCK (i
) >= NUM_FIXED_BLOCKS
&& REG_N_DEATHS (i
) == 1)
404 /* Force loop below to initialize entire quantity array. */
407 /* Allocate each block's local registers, block by block. */
411 /* NEXT_QTY indicates which elements of the `qty_...'
412 vectors might need to be initialized because they were used
413 for the previous block; it is set to the entire array before
414 block 0. Initialize those, with explicit loop if there are few,
415 else with bzero and bcopy. Do not initialize vectors that are
416 explicit set by `alloc_qty'. */
420 for (i
= 0; i
< next_qty
; i
++)
422 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
423 qty_phys_num_copy_sugg
[i
] = 0;
424 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
425 qty_phys_num_sugg
[i
] = 0;
430 #define CLEAR(vector) \
431 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
433 CLEAR (qty_phys_copy_sugg
);
434 CLEAR (qty_phys_num_copy_sugg
);
435 CLEAR (qty_phys_sugg
);
436 CLEAR (qty_phys_num_sugg
);
441 block_alloc (b
->index
);
445 free (qty_phys_copy_sugg
);
446 free (qty_phys_num_copy_sugg
);
447 free (qty_phys_sugg
);
448 free (qty_phys_num_sugg
);
452 free (reg_next_in_qty
);
454 return recorded_label_ref
;
457 /* Used for communication between the following two functions: contains
458 a MEM that we wish to ensure remains unchanged. */
459 static rtx equiv_mem
;
461 /* Set nonzero if EQUIV_MEM is modified. */
462 static int equiv_mem_modified
;
464 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
465 Called via note_stores. */
468 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
469 void *data ATTRIBUTE_UNUSED
)
472 && reg_overlap_mentioned_p (dest
, equiv_mem
))
474 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
475 equiv_mem_modified
= 1;
478 /* Verify that no store between START and the death of REG invalidates
479 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
480 by storing into an overlapping memory location, or with a non-const
483 Return 1 if MEMREF remains valid. */
486 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
492 equiv_mem_modified
= 0;
494 /* If the memory reference has side effects or is volatile, it isn't a
495 valid equivalence. */
496 if (side_effects_p (memref
))
499 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
504 if (find_reg_note (insn
, REG_DEAD
, reg
))
507 if (CALL_P (insn
) && ! MEM_READONLY_P (memref
)
508 && ! RTL_CONST_OR_PURE_CALL_P (insn
))
511 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
513 /* If a register mentioned in MEMREF is modified via an
514 auto-increment, we lose the equivalence. Do the same if one
515 dies; although we could extend the life, it doesn't seem worth
518 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
519 if ((REG_NOTE_KIND (note
) == REG_INC
520 || REG_NOTE_KIND (note
) == REG_DEAD
)
521 && REG_P (XEXP (note
, 0))
522 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
529 /* Returns zero if X is known to be invariant. */
532 equiv_init_varies_p (rtx x
)
534 RTX_CODE code
= GET_CODE (x
);
541 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
553 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
556 if (MEM_VOLATILE_P (x
))
565 fmt
= GET_RTX_FORMAT (code
);
566 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
569 if (equiv_init_varies_p (XEXP (x
, i
)))
572 else if (fmt
[i
] == 'E')
575 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
576 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
583 /* Returns nonzero if X (used to initialize register REGNO) is movable.
584 X is only movable if the registers it uses have equivalent initializations
585 which appear to be within the same loop (or in an inner loop) and movable
586 or if they are not candidates for local_alloc and don't vary. */
589 equiv_init_movable_p (rtx x
, int regno
)
593 enum rtx_code code
= GET_CODE (x
);
598 return equiv_init_movable_p (SET_SRC (x
), regno
);
613 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
614 && reg_equiv
[REGNO (x
)].replace
)
615 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
&& ! rtx_varies_p (x
, 0));
617 case UNSPEC_VOLATILE
:
621 if (MEM_VOLATILE_P (x
))
630 fmt
= GET_RTX_FORMAT (code
);
631 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
635 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
639 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
640 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
648 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
651 contains_replace_regs (rtx x
)
655 enum rtx_code code
= GET_CODE (x
);
672 return reg_equiv
[REGNO (x
)].replace
;
678 fmt
= GET_RTX_FORMAT (code
);
679 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
683 if (contains_replace_regs (XEXP (x
, i
)))
687 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
688 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
696 /* TRUE if X references a memory location that would be affected by a store
700 memref_referenced_p (rtx memref
, rtx x
)
704 enum rtx_code code
= GET_CODE (x
);
722 return (reg_equiv
[REGNO (x
)].replacement
723 && memref_referenced_p (memref
,
724 reg_equiv
[REGNO (x
)].replacement
));
727 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
732 /* If we are setting a MEM, it doesn't count (its address does), but any
733 other SET_DEST that has a MEM in it is referencing the MEM. */
734 if (MEM_P (SET_DEST (x
)))
736 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
739 else if (memref_referenced_p (memref
, SET_DEST (x
)))
742 return memref_referenced_p (memref
, SET_SRC (x
));
748 fmt
= GET_RTX_FORMAT (code
);
749 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
753 if (memref_referenced_p (memref
, XEXP (x
, i
)))
757 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
758 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
766 /* TRUE if some insn in the range (START, END] references a memory location
767 that would be affected by a store to MEMREF. */
770 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
774 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
775 insn
= NEXT_INSN (insn
))
780 if (memref_referenced_p (memref
, PATTERN (insn
)))
783 /* Nonconst functions may access memory. */
784 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
791 /* Find registers that are equivalent to a single value throughout the
792 compilation (either because they can be referenced in memory or are set once
793 from a single constant). Lower their priority for a register.
795 If such a register is only referenced once, try substituting its value
796 into the using insn. If it succeeds, we can eliminate the register
799 Initialize the REG_EQUIV_INIT array of initializing insns. */
802 update_equiv_regs (void)
809 reg_equiv
= XCNEWVEC (struct equivalence
, max_regno
);
810 reg_equiv_init
= ggc_alloc_cleared (max_regno
* sizeof (rtx
));
811 reg_equiv_init_size
= max_regno
;
813 init_alias_analysis ();
815 /* Scan the insns and find which registers have equivalences. Do this
816 in a separate scan of the insns because (due to -fcse-follow-jumps)
817 a register can be set below its use. */
820 loop_depth
= bb
->loop_depth
;
822 for (insn
= BB_HEAD (bb
);
823 insn
!= NEXT_INSN (BB_END (bb
));
824 insn
= NEXT_INSN (insn
))
834 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
835 if (REG_NOTE_KIND (note
) == REG_INC
)
836 no_equiv (XEXP (note
, 0), note
, NULL
);
838 set
= single_set (insn
);
840 /* If this insn contains more (or less) than a single SET,
841 only mark all destinations as having no known equivalence. */
844 note_stores (PATTERN (insn
), no_equiv
, NULL
);
847 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
851 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
853 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
855 note_stores (part
, no_equiv
, NULL
);
859 dest
= SET_DEST (set
);
862 /* See if this is setting up the equivalence between an argument
863 register and its stack slot. */
864 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
867 gcc_assert (REG_P (dest
));
868 regno
= REGNO (dest
);
870 /* Note that we don't want to clear reg_equiv_init even if there
871 are multiple sets of this register. */
872 reg_equiv
[regno
].is_arg_equivalence
= 1;
874 /* Record for reload that this is an equivalencing insn. */
875 if (rtx_equal_p (src
, XEXP (note
, 0)))
876 reg_equiv_init
[regno
]
877 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[regno
]);
879 /* Continue normally in case this is a candidate for
886 /* We only handle the case of a pseudo register being set
887 once, or always to the same value. */
888 /* ??? The mn10200 port breaks if we add equivalences for
889 values that need an ADDRESS_REGS register and set them equivalent
890 to a MEM of a pseudo. The actual problem is in the over-conservative
891 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
892 calculate_needs, but we traditionally work around this problem
893 here by rejecting equivalences when the destination is in a register
894 that's likely spilled. This is fragile, of course, since the
895 preferred class of a pseudo depends on all instructions that set
899 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
900 || reg_equiv
[regno
].init_insns
== const0_rtx
901 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
902 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
904 /* This might be setting a SUBREG of a pseudo, a pseudo that is
905 also set somewhere else to a constant. */
906 note_stores (set
, no_equiv
, NULL
);
910 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
912 /* cse sometimes generates function invariants, but doesn't put a
913 REG_EQUAL note on the insn. Since this note would be redundant,
914 there's no point creating it earlier than here. */
915 if (! note
&& ! rtx_varies_p (src
, 0))
916 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
918 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
919 since it represents a function call */
920 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
923 if (DF_REG_DEF_COUNT (regno
) != 1
925 || rtx_varies_p (XEXP (note
, 0), 0)
926 || (reg_equiv
[regno
].replacement
927 && ! rtx_equal_p (XEXP (note
, 0),
928 reg_equiv
[regno
].replacement
))))
930 no_equiv (dest
, set
, NULL
);
933 /* Record this insn as initializing this register. */
934 reg_equiv
[regno
].init_insns
935 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
937 /* If this register is known to be equal to a constant, record that
938 it is always equivalent to the constant. */
939 if (DF_REG_DEF_COUNT (regno
) == 1
940 && note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
942 rtx note_value
= XEXP (note
, 0);
943 remove_note (insn
, note
);
944 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
947 /* If this insn introduces a "constant" register, decrease the priority
948 of that register. Record this insn if the register is only used once
949 more and the equivalence value is the same as our source.
951 The latter condition is checked for two reasons: First, it is an
952 indication that it may be more efficient to actually emit the insn
953 as written (if no registers are available, reload will substitute
954 the equivalence). Secondly, it avoids problems with any registers
955 dying in this insn whose death notes would be missed.
957 If we don't have a REG_EQUIV note, see if this insn is loading
958 a register used only in one basic block from a MEM. If so, and the
959 MEM remains unchanged for the life of the register, add a REG_EQUIV
962 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
964 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
965 && MEM_P (SET_SRC (set
))
966 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
967 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (SET_SRC (set
)));
971 int regno
= REGNO (dest
);
972 rtx x
= XEXP (note
, 0);
974 /* If we haven't done so, record for reload that this is an
975 equivalencing insn. */
976 if (!reg_equiv
[regno
].is_arg_equivalence
)
977 reg_equiv_init
[regno
]
978 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[regno
]);
980 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
981 We might end up substituting the LABEL_REF for uses of the
982 pseudo here or later. That kind of transformation may turn an
983 indirect jump into a direct jump, in which case we must rerun the
984 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
985 if (GET_CODE (x
) == LABEL_REF
986 || (GET_CODE (x
) == CONST
987 && GET_CODE (XEXP (x
, 0)) == PLUS
988 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)))
989 recorded_label_ref
= 1;
991 reg_equiv
[regno
].replacement
= x
;
992 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
993 reg_equiv
[regno
].loop_depth
= loop_depth
;
995 /* Don't mess with things live during setjmp. */
996 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
998 /* Note that the statement below does not affect the priority
1000 REG_LIVE_LENGTH (regno
) *= 2;
1002 /* If the register is referenced exactly twice, meaning it is
1003 set once and used once, indicate that the reference may be
1004 replaced by the equivalence we computed above. Do this
1005 even if the register is only used in one block so that
1006 dependencies can be handled where the last register is
1007 used in a different block (i.e. HIGH / LO_SUM sequences)
1008 and to reduce the number of registers alive across
1011 if (REG_N_REFS (regno
) == 2
1012 && (rtx_equal_p (x
, src
)
1013 || ! equiv_init_varies_p (src
))
1014 && NONJUMP_INSN_P (insn
)
1015 && equiv_init_movable_p (PATTERN (insn
), regno
))
1016 reg_equiv
[regno
].replace
= 1;
1025 /* A second pass, to gather additional equivalences with memory. This needs
1026 to be done after we know which registers we are going to replace. */
1028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1033 if (! INSN_P (insn
))
1036 set
= single_set (insn
);
1040 dest
= SET_DEST (set
);
1041 src
= SET_SRC (set
);
1043 /* If this sets a MEM to the contents of a REG that is only used
1044 in a single basic block, see if the register is always equivalent
1045 to that memory location and if moving the store from INSN to the
1046 insn that set REG is safe. If so, put a REG_EQUIV note on the
1049 Don't add a REG_EQUIV note if the insn already has one. The existing
1050 REG_EQUIV is likely more useful than the one we are adding.
1052 If one of the regs in the address has reg_equiv[REGNO].replace set,
1053 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
1054 optimization may move the set of this register immediately before
1055 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
1056 the mention in the REG_EQUIV note would be to an uninitialized
1059 if (MEM_P (dest
) && REG_P (src
)
1060 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1061 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
1062 && DF_REG_DEF_COUNT (regno
) == 1
1063 && reg_equiv
[regno
].init_insns
!= 0
1064 && reg_equiv
[regno
].init_insns
!= const0_rtx
1065 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
1066 REG_EQUIV
, NULL_RTX
)
1067 && ! contains_replace_regs (XEXP (dest
, 0)))
1069 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1070 if (validate_equiv_mem (init_insn
, src
, dest
)
1071 && ! memref_used_between_p (dest
, init_insn
, insn
)
1072 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
1074 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
1076 /* This insn makes the equivalence, not the one initializing
1078 reg_equiv_init
[regno
]
1079 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
1080 df_notes_rescan (init_insn
);
1085 cleared_regs
= BITMAP_ALLOC (NULL
);
1086 /* Now scan all regs killed in an insn to see if any of them are
1087 registers only used that once. If so, see if we can replace the
1088 reference with the equivalent form. If we can, delete the
1089 initializing reference and this register will go away. If we
1090 can't replace the reference, and the initializing reference is
1091 within the same loop (or in an inner loop), then move the register
1092 initialization just before the use, so that they are in the same
1094 FOR_EACH_BB_REVERSE (bb
)
1096 loop_depth
= bb
->loop_depth
;
1097 for (insn
= BB_END (bb
);
1098 insn
!= PREV_INSN (BB_HEAD (bb
));
1099 insn
= PREV_INSN (insn
))
1103 if (! INSN_P (insn
))
1106 /* Don't substitute into a non-local goto, this confuses CFG. */
1108 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1111 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1113 if (REG_NOTE_KIND (link
) == REG_DEAD
1114 /* Make sure this insn still refers to the register. */
1115 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1117 int regno
= REGNO (XEXP (link
, 0));
1120 if (! reg_equiv
[regno
].replace
1121 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1124 /* reg_equiv[REGNO].replace gets set only when
1125 REG_N_REFS[REGNO] is 2, i.e. the register is set
1126 once and used once. (If it were only set, but not used,
1127 flow would have deleted the setting insns.) Hence
1128 there can only be one insn in reg_equiv[REGNO].init_insns. */
1129 gcc_assert (reg_equiv
[regno
].init_insns
1130 && !XEXP (reg_equiv
[regno
].init_insns
, 1));
1131 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1133 /* We may not move instructions that can throw, since
1134 that changes basic block boundaries and we are not
1135 prepared to adjust the CFG to match. */
1136 if (can_throw_internal (equiv_insn
))
1139 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1140 && validate_replace_rtx (regno_reg_rtx
[regno
],
1141 *(reg_equiv
[regno
].src_p
), insn
))
1147 /* Find the last note. */
1148 for (last_link
= link
; XEXP (last_link
, 1);
1149 last_link
= XEXP (last_link
, 1))
1152 /* Append the REG_DEAD notes from equiv_insn. */
1153 equiv_link
= REG_NOTES (equiv_insn
);
1157 equiv_link
= XEXP (equiv_link
, 1);
1158 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1160 remove_note (equiv_insn
, note
);
1161 XEXP (last_link
, 1) = note
;
1162 XEXP (note
, 1) = NULL_RTX
;
1167 remove_death (regno
, insn
);
1168 SET_REG_N_REFS (regno
, 0);
1169 REG_FREQ (regno
) = 0;
1170 delete_insn (equiv_insn
);
1172 reg_equiv
[regno
].init_insns
1173 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1175 reg_equiv_init
[regno
] = NULL_RTX
;
1176 bitmap_set_bit (cleared_regs
, regno
);
1178 /* Move the initialization of the register to just before
1179 INSN. Update the flow information. */
1180 else if (PREV_INSN (insn
) != equiv_insn
)
1184 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1185 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1186 REG_NOTES (equiv_insn
) = 0;
1188 /* Make sure this insn is recognized before
1189 reload begins, otherwise
1190 eliminate_regs_in_insn will die. */
1191 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1193 delete_insn (equiv_insn
);
1195 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1197 REG_BASIC_BLOCK (regno
) = bb
->index
;
1198 REG_N_CALLS_CROSSED (regno
) = 0;
1199 REG_FREQ_CALLS_CROSSED (regno
) = 0;
1200 REG_N_THROWING_CALLS_CROSSED (regno
) = 0;
1201 REG_LIVE_LENGTH (regno
) = 2;
1203 if (insn
== BB_HEAD (bb
))
1204 BB_HEAD (bb
) = PREV_INSN (insn
);
1206 reg_equiv_init
[regno
]
1207 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
1208 bitmap_set_bit (cleared_regs
, regno
);
1215 if (!bitmap_empty_p (cleared_regs
))
1218 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
1219 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
1220 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
1221 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
1224 BITMAP_FREE (cleared_regs
);
1229 end_alias_analysis ();
1233 /* Mark REG as having no known equivalence.
1234 Some instructions might have been processed before and furnished
1235 with REG_EQUIV notes for this register; these notes will have to be
1237 STORE is the piece of RTL that does the non-constant / conflicting
1238 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1239 but needs to be there because this function is called from note_stores. */
1241 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
, void *data ATTRIBUTE_UNUSED
)
1248 regno
= REGNO (reg
);
1249 list
= reg_equiv
[regno
].init_insns
;
1250 if (list
== const0_rtx
)
1252 reg_equiv
[regno
].init_insns
= const0_rtx
;
1253 reg_equiv
[regno
].replacement
= NULL_RTX
;
1254 /* This doesn't matter for equivalences made for argument registers, we
1255 should keep their initialization insns. */
1256 if (reg_equiv
[regno
].is_arg_equivalence
)
1258 reg_equiv_init
[regno
] = NULL_RTX
;
1259 for (; list
; list
= XEXP (list
, 1))
1261 rtx insn
= XEXP (list
, 0);
1262 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1266 /* Allocate hard regs to the pseudo regs used only within block number B.
1267 Only the pseudos that die but once can be handled. */
1275 int insn_number
= 0;
1277 int max_uid
= get_max_uid ();
1279 int no_conflict_combined_regno
= -1;
1280 struct df_ref
** def_rec
;
1282 /* Count the instructions in the basic block. */
1284 insn
= BB_END (BASIC_BLOCK (b
));
1290 gcc_assert (insn_count
<= max_uid
);
1292 if (insn
== BB_HEAD (BASIC_BLOCK (b
)))
1294 insn
= PREV_INSN (insn
);
1297 /* +2 to leave room for a post_mark_life at the last insn and for
1298 the birth of a CLOBBER in the first insn. */
1299 regs_live_at
= XCNEWVEC (HARD_REG_SET
, 2 * insn_count
+ 2);
1301 /* Initialize table of hardware registers currently live. */
1303 REG_SET_TO_HARD_REG_SET (regs_live
, DF_LR_IN (BASIC_BLOCK (b
)));
1305 /* This is conservative, as this would include registers that are
1306 artificial-def'ed-but-not-used. However, artificial-defs are
1307 rare, and such uninitialized use is rarer still, and the chance
1308 of this having any performance impact is even less, while the
1309 benefit is not having to compute and keep the TOP set around. */
1310 for (def_rec
= df_get_artificial_defs (b
); *def_rec
; def_rec
++)
1312 int regno
= DF_REF_REGNO (*def_rec
);
1313 if (regno
< FIRST_PSEUDO_REGISTER
)
1314 SET_HARD_REG_BIT (regs_live
, regno
);
1317 /* This loop scans the instructions of the basic block
1318 and assigns quantities to registers.
1319 It computes which registers to tie. */
1321 insn
= BB_HEAD (BASIC_BLOCK (b
));
1331 rtx r0
, r1
= NULL_RTX
;
1332 int combined_regno
= -1;
1335 this_insn_number
= insn_number
;
1338 extract_insn (insn
);
1339 which_alternative
= -1;
1341 /* Is this insn suitable for tying two registers?
1342 If so, try doing that.
1343 Suitable insns are those with at least two operands and where
1344 operand 0 is an output that is a register that is not
1347 We can tie operand 0 with some operand that dies in this insn.
1348 First look for operands that are required to be in the same
1349 register as operand 0. If we find such, only try tying that
1350 operand or one that can be put into that operand if the
1351 operation is commutative. If we don't find an operand
1352 that is required to be in the same register as operand 0,
1353 we can tie with any operand.
1355 Subregs in place of regs are also ok.
1357 If tying is done, WIN is set nonzero. */
1360 && recog_data
.n_operands
> 1
1361 && recog_data
.constraints
[0][0] == '='
1362 && recog_data
.constraints
[0][1] != '&')
1364 /* If non-negative, is an operand that must match operand 0. */
1365 int must_match_0
= -1;
1366 /* Counts number of alternatives that require a match with
1368 int n_matching_alts
= 0;
1370 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1372 const char *p
= recog_data
.constraints
[i
];
1373 int this_match
= requires_inout (p
);
1375 n_matching_alts
+= this_match
;
1376 if (this_match
== recog_data
.n_alternatives
)
1380 r0
= recog_data
.operand
[0];
1381 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1383 /* Skip this operand if we found an operand that
1384 must match operand 0 and this operand isn't it
1385 and can't be made to be it by commutativity. */
1387 if (must_match_0
>= 0 && i
!= must_match_0
1388 && ! (i
== must_match_0
+ 1
1389 && recog_data
.constraints
[i
-1][0] == '%')
1390 && ! (i
== must_match_0
- 1
1391 && recog_data
.constraints
[i
][0] == '%'))
1394 /* Likewise if each alternative has some operand that
1395 must match operand zero. In that case, skip any
1396 operand that doesn't list operand 0 since we know that
1397 the operand always conflicts with operand 0. We
1398 ignore commutativity in this case to keep things simple. */
1399 if (n_matching_alts
== recog_data
.n_alternatives
1400 && 0 == requires_inout (recog_data
.constraints
[i
]))
1403 r1
= recog_data
.operand
[i
];
1405 /* If the operand is an address, find a register in it.
1406 There may be more than one register, but we only try one
1408 if (recog_data
.constraints
[i
][0] == 'p'
1409 || EXTRA_ADDRESS_CONSTRAINT (recog_data
.constraints
[i
][0],
1410 recog_data
.constraints
[i
]))
1411 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1414 /* Avoid making a call-saved register unnecessarily
1416 hard_reg
= get_hard_reg_initial_reg (r1
);
1417 if (hard_reg
!= NULL_RTX
)
1419 if (REG_P (hard_reg
)
1420 && REGNO (hard_reg
) < FIRST_PSEUDO_REGISTER
1421 && !call_used_regs
[REGNO (hard_reg
)])
1425 if (REG_P (r0
) || GET_CODE (r0
) == SUBREG
)
1427 /* We have two priorities for hard register preferences.
1428 If we have a move insn or an insn whose first input
1429 can only be in the same register as the output, give
1430 priority to an equivalence found from that insn. */
1432 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1434 if (REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1435 win
= combine_regs (r1
, r0
, may_save_copy
,
1436 insn_number
, insn
, 0);
1443 /* Recognize an insn sequence with an ultimate result
1444 which can safely overlap one of the inputs.
1445 The sequence begins with a CLOBBER of its result,
1446 and ends with an insn that copies the result to itself
1447 and has a REG_EQUAL note for an equivalent formula.
1448 That note indicates what the inputs are.
1449 The result and the input can overlap if each insn in
1450 the sequence either doesn't mention the input
1451 or has a REG_NO_CONFLICT note to inhibit the conflict.
1453 We do the combining test at the CLOBBER so that the
1454 destination register won't have had a quantity number
1455 assigned, since that would prevent combining. */
1458 && GET_CODE (PATTERN (insn
)) == CLOBBER
1459 && (r0
= XEXP (PATTERN (insn
), 0),
1461 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1462 && XEXP (link
, 0) != 0
1463 && NONJUMP_INSN_P (XEXP (link
, 0))
1464 && (set
= single_set (XEXP (link
, 0))) != 0
1465 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1466 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1469 if (r1
= XEXP (note
, 0), REG_P (r1
)
1470 /* Check that we have such a sequence. */
1471 && no_conflict_p (insn
, r0
, r1
))
1472 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1473 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1474 && (r1
= XEXP (XEXP (note
, 0), 0),
1475 REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1476 && no_conflict_p (insn
, r0
, r1
))
1477 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1479 /* Here we care if the operation to be computed is
1481 else if (COMMUTATIVE_P (XEXP (note
, 0))
1482 && (r1
= XEXP (XEXP (note
, 0), 1),
1483 (REG_P (r1
) || GET_CODE (r1
) == SUBREG
))
1484 && no_conflict_p (insn
, r0
, r1
))
1485 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1487 /* If we did combine something, show the register number
1488 in question so that we know to ignore its death. */
1490 no_conflict_combined_regno
= REGNO (r1
);
1493 /* If registers were just tied, set COMBINED_REGNO
1494 to the number of the register used in this insn
1495 that was tied to the register set in this insn.
1496 This register's qty should not be "killed". */
1500 while (GET_CODE (r1
) == SUBREG
)
1501 r1
= SUBREG_REG (r1
);
1502 combined_regno
= REGNO (r1
);
1505 /* Mark the death of everything that dies in this instruction,
1506 except for anything that was just combined. */
1508 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1509 if (REG_NOTE_KIND (link
) == REG_DEAD
1510 && REG_P (XEXP (link
, 0))
1511 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1512 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1513 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1515 wipe_dead_reg (XEXP (link
, 0), 0);
1517 /* Allocate qty numbers for all registers local to this block
1518 that are born (set) in this instruction.
1519 A pseudo that already has a qty is not changed. */
1521 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1523 /* If anything is set in this insn and then unused, mark it as dying
1524 after this insn, so it will conflict with our outputs. This
1525 can't match with something that combined, and it doesn't matter
1526 if it did. Do this after the calls to reg_is_set since these
1527 die after, not during, the current insn. */
1529 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1530 if (REG_NOTE_KIND (link
) == REG_UNUSED
1531 && REG_P (XEXP (link
, 0)))
1532 wipe_dead_reg (XEXP (link
, 0), 1);
1534 /* If this is an insn that has a REG_RETVAL note pointing at a
1535 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1536 block, so clear any register number that combined within it. */
1537 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1538 && NONJUMP_INSN_P (XEXP (note
, 0))
1539 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1540 no_conflict_combined_regno
= -1;
1543 /* Set the registers live after INSN_NUMBER. Note that we never
1544 record the registers live before the block's first insn, since no
1545 pseudos we care about are live before that insn. */
1547 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1548 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1550 if (insn
== BB_END (BASIC_BLOCK (b
)))
1553 insn
= NEXT_INSN (insn
);
1556 /* Now every register that is local to this basic block
1557 should have been given a quantity, or else -1 meaning ignore it.
1558 Every quantity should have a known birth and death.
1560 Order the qtys so we assign them registers in order of the
1561 number of suggested registers they need so we allocate those with
1562 the most restrictive needs first. */
1564 qty_order
= XNEWVEC (int, next_qty
);
1565 for (i
= 0; i
< next_qty
; i
++)
1568 #define EXCHANGE(I1, I2) \
1569 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1574 /* Make qty_order[2] be the one to allocate last. */
1575 if (qty_sugg_compare (0, 1) > 0)
1577 if (qty_sugg_compare (1, 2) > 0)
1580 /* ... Fall through ... */
1582 /* Put the best one to allocate in qty_order[0]. */
1583 if (qty_sugg_compare (0, 1) > 0)
1586 /* ... Fall through ... */
1590 /* Nothing to do here. */
1594 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1597 /* Try to put each quantity in a suggested physical register, if it has one.
1598 This may cause registers to be allocated that otherwise wouldn't be, but
1599 this seems acceptable in local allocation (unlike global allocation). */
1600 for (i
= 0; i
< next_qty
; i
++)
1603 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1604 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1605 0, 1, qty
[q
].birth
, qty
[q
].death
);
1607 qty
[q
].phys_reg
= -1;
1610 /* Order the qtys so we assign them registers in order of
1611 decreasing length of life. Normally call qsort, but if we
1612 have only a very small number of quantities, sort them ourselves. */
1614 for (i
= 0; i
< next_qty
; i
++)
1617 #define EXCHANGE(I1, I2) \
1618 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1623 /* Make qty_order[2] be the one to allocate last. */
1624 if (qty_compare (0, 1) > 0)
1626 if (qty_compare (1, 2) > 0)
1629 /* ... Fall through ... */
1631 /* Put the best one to allocate in qty_order[0]. */
1632 if (qty_compare (0, 1) > 0)
1635 /* ... Fall through ... */
1639 /* Nothing to do here. */
1643 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1646 /* Now for each qty that is not a hardware register,
1647 look for a hardware register to put it in.
1648 First try the register class that is cheapest for this qty,
1649 if there is more than one class. */
1651 for (i
= 0; i
< next_qty
; i
++)
1654 if (qty
[q
].phys_reg
< 0)
1656 #ifdef INSN_SCHEDULING
1657 /* These values represent the adjusted lifetime of a qty so
1658 that it conflicts with qtys which appear near the start/end
1659 of this qty's lifetime.
1661 The purpose behind extending the lifetime of this qty is to
1662 discourage the register allocator from creating false
1665 The adjustment value is chosen to indicate that this qty
1666 conflicts with all the qtys in the instructions immediately
1667 before and after the lifetime of this qty.
1669 Experiments have shown that higher values tend to hurt
1670 overall code performance.
1672 If allocation using the extended lifetime fails we will try
1673 again with the qty's unadjusted lifetime. */
1674 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1675 int fake_death
= MIN (insn_number
* 2 + 1,
1676 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1679 if (N_REG_CLASSES
> 1)
1681 #ifdef INSN_SCHEDULING
1682 /* We try to avoid using hard registers allocated to qtys which
1683 are born immediately after this qty or die immediately before
1686 This optimization is only appropriate when we will run
1687 a scheduling pass after reload and we are not optimizing
1689 if (flag_schedule_insns_after_reload
&& dbg_cnt (local_alloc_for_sched
)
1691 && !SMALL_REGISTER_CLASSES
)
1693 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1694 qty
[q
].mode
, q
, 0, 0,
1695 fake_birth
, fake_death
);
1696 if (qty
[q
].phys_reg
>= 0)
1700 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1701 qty
[q
].mode
, q
, 0, 0,
1702 qty
[q
].birth
, qty
[q
].death
);
1703 if (qty
[q
].phys_reg
>= 0)
1707 #ifdef INSN_SCHEDULING
1708 /* Similarly, avoid false dependencies. */
1709 if (flag_schedule_insns_after_reload
&& dbg_cnt (local_alloc_for_sched
)
1711 && !SMALL_REGISTER_CLASSES
1712 && qty
[q
].alternate_class
!= NO_REGS
)
1713 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1714 qty
[q
].mode
, q
, 0, 0,
1715 fake_birth
, fake_death
);
1717 if (qty
[q
].alternate_class
!= NO_REGS
)
1718 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1719 qty
[q
].mode
, q
, 0, 0,
1720 qty
[q
].birth
, qty
[q
].death
);
1724 /* Now propagate the register assignments
1725 to the pseudo regs belonging to the qtys. */
1727 for (q
= 0; q
< next_qty
; q
++)
1728 if (qty
[q
].phys_reg
>= 0)
1730 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1731 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1735 free (regs_live_at
);
1739 /* Compare two quantities' priority for getting real registers.
1740 We give shorter-lived quantities higher priority.
1741 Quantities with more references are also preferred, as are quantities that
1742 require multiple registers. This is the identical prioritization as
1743 done by global-alloc.
1745 We used to give preference to registers with *longer* lives, but using
1746 the same algorithm in both local- and global-alloc can speed up execution
1747 of some programs by as much as a factor of three! */
1749 /* Note that the quotient will never be bigger than
1750 the value of floor_log2 times the maximum number of
1751 times a register can occur in one insn (surely less than 100)
1752 weighted by frequency (max REG_FREQ_MAX).
1753 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1754 QTY_CMP_PRI is also used by qty_sugg_compare. */
1756 #define QTY_CMP_PRI(q) \
1757 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1758 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1761 qty_compare (int q1
, int q2
)
1763 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1767 qty_compare_1 (const void *q1p
, const void *q2p
)
1769 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1770 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1775 /* If qtys are equally good, sort by qty number,
1776 so that the results of qsort leave nothing to chance. */
1780 /* Compare two quantities' priority for getting real registers. This version
1781 is called for quantities that have suggested hard registers. First priority
1782 goes to quantities that have copy preferences, then to those that have
1783 normal preferences. Within those groups, quantities with the lower
1784 number of preferences have the highest priority. Of those, we use the same
1785 algorithm as above. */
1787 #define QTY_CMP_SUGG(q) \
1788 (qty_phys_num_copy_sugg[q] \
1789 ? qty_phys_num_copy_sugg[q] \
1790 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1793 qty_sugg_compare (int q1
, int q2
)
1795 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1800 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1804 qty_sugg_compare_1 (const void *q1p
, const void *q2p
)
1806 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1807 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1812 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1816 /* If qtys are equally good, sort by qty number,
1817 so that the results of qsort leave nothing to chance. */
1824 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1825 Returns 1 if have done so, or 0 if cannot.
1827 Combining registers means marking them as having the same quantity
1828 and adjusting the offsets within the quantity if either of
1831 We don't actually combine a hard reg with a pseudo; instead
1832 we just record the hard reg as the suggestion for the pseudo's quantity.
1833 If we really combined them, we could lose if the pseudo lives
1834 across an insn that clobbers the hard reg (eg, movmem).
1836 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1837 there is no REG_DEAD note on INSN. This occurs during the processing
1838 of REG_NO_CONFLICT blocks.
1840 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1841 SETREG or if the input and output must share a register.
1842 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1844 There are elaborate checks for the validity of combining. */
1847 combine_regs (rtx usedreg
, rtx setreg
, int may_save_copy
, int insn_number
,
1848 rtx insn
, int already_dead
)
1855 /* Determine the numbers and sizes of registers being used. If a subreg
1856 is present that does not change the entire register, don't consider
1857 this a copy insn. */
1859 while (GET_CODE (usedreg
) == SUBREG
)
1861 rtx subreg
= SUBREG_REG (usedreg
);
1865 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1868 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1869 offset
+= subreg_regno_offset (REGNO (subreg
),
1871 SUBREG_BYTE (usedreg
),
1872 GET_MODE (usedreg
));
1874 offset
+= (SUBREG_BYTE (usedreg
)
1875 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1881 if (!REG_P (usedreg
))
1884 ureg
= REGNO (usedreg
);
1885 if (ureg
< FIRST_PSEUDO_REGISTER
)
1886 usize
= hard_regno_nregs
[ureg
][GET_MODE (usedreg
)];
1888 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1889 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1890 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1892 while (GET_CODE (setreg
) == SUBREG
)
1894 rtx subreg
= SUBREG_REG (setreg
);
1898 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1901 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1902 offset
-= subreg_regno_offset (REGNO (subreg
),
1904 SUBREG_BYTE (setreg
),
1907 offset
-= (SUBREG_BYTE (setreg
)
1908 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1914 if (!REG_P (setreg
))
1917 sreg
= REGNO (setreg
);
1918 if (sreg
< FIRST_PSEUDO_REGISTER
)
1919 ssize
= hard_regno_nregs
[sreg
][GET_MODE (setreg
)];
1921 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1922 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1923 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1925 /* If UREG is a pseudo-register that hasn't already been assigned a
1926 quantity number, it means that it is not local to this block or dies
1927 more than once. In either event, we can't do anything with it. */
1928 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1929 /* Do not combine registers unless one fits within the other. */
1930 || (offset
> 0 && usize
+ offset
> ssize
)
1931 || (offset
< 0 && usize
+ offset
< ssize
)
1932 /* Do not combine with a smaller already-assigned object
1933 if that smaller object is already combined with something bigger. */
1934 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1935 && usize
< qty
[reg_qty
[ureg
]].size
)
1936 /* Can't combine if SREG is not a register we can allocate. */
1937 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1938 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1939 These have already been taken care of. This probably wouldn't
1940 combine anyway, but don't take any chances. */
1941 || (ureg
>= FIRST_PSEUDO_REGISTER
1942 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1943 /* Don't tie something to itself. In most cases it would make no
1944 difference, but it would screw up if the reg being tied to itself
1945 also dies in this insn. */
1947 /* Don't try to connect two different hardware registers. */
1948 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1949 /* Don't connect two different machine modes if they have different
1950 implications as to which registers may be used. */
1951 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1954 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1955 qty_phys_sugg for the pseudo instead of tying them.
1957 Return "failure" so that the lifespan of UREG is terminated here;
1958 that way the two lifespans will be disjoint and nothing will prevent
1959 the pseudo reg from being given this hard reg. */
1961 if (ureg
< FIRST_PSEUDO_REGISTER
)
1963 /* Allocate a quantity number so we have a place to put our
1965 if (reg_qty
[sreg
] == -2)
1966 reg_is_born (setreg
, 2 * insn_number
);
1968 if (reg_qty
[sreg
] >= 0)
1971 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1973 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1974 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1976 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1978 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1979 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1985 /* Similarly for SREG a hard register and UREG a pseudo register. */
1987 if (sreg
< FIRST_PSEUDO_REGISTER
)
1990 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1992 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1993 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1995 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1997 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1998 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
2003 /* At this point we know that SREG and UREG are both pseudos.
2004 Do nothing if SREG already has a quantity or is a register that we
2006 if (reg_qty
[sreg
] >= -1
2007 /* If we are not going to let any regs live across calls,
2008 don't tie a call-crossing reg to a non-call-crossing reg. */
2009 || (cfun
->has_nonlocal_label
2010 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
2011 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
2014 /* We don't already know about SREG, so tie it to UREG
2015 if this is the last use of UREG, provided the classes they want
2018 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
2019 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
2021 /* Add SREG to UREG's quantity. */
2022 sqty
= reg_qty
[ureg
];
2023 reg_qty
[sreg
] = sqty
;
2024 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
2025 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
2026 qty
[sqty
].first_reg
= sreg
;
2028 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
2029 update_qty_class (sqty
, sreg
);
2031 /* Update info about quantity SQTY. */
2032 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
2033 qty
[sqty
].freq_calls_crossed
+= REG_FREQ_CALLS_CROSSED (sreg
);
2034 qty
[sqty
].n_throwing_calls_crossed
2035 += REG_N_THROWING_CALLS_CROSSED (sreg
);
2036 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
2037 qty
[sqty
].freq
+= REG_FREQ (sreg
);
2042 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
2043 reg_offset
[i
] -= offset
;
2045 qty
[sqty
].size
= ssize
;
2046 qty
[sqty
].mode
= GET_MODE (setreg
);
2055 /* Return 1 if the preferred class of REG allows it to be tied
2056 to a quantity or register whose class is CLASS.
2057 True if REG's reg class either contains or is contained in CLASS. */
2060 reg_meets_class_p (int reg
, enum reg_class
class)
2062 enum reg_class rclass
= reg_preferred_class (reg
);
2063 return (reg_class_subset_p (rclass
, class)
2064 || reg_class_subset_p (class, rclass
));
2067 /* Update the class of QTYNO assuming that REG is being tied to it. */
2070 update_qty_class (int qtyno
, int reg
)
2072 enum reg_class rclass
= reg_preferred_class (reg
);
2073 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
2074 qty
[qtyno
].min_class
= rclass
;
2076 rclass
= reg_alternate_class (reg
);
2077 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
2078 qty
[qtyno
].alternate_class
= rclass
;
2081 /* Handle something which alters the value of an rtx REG.
2083 REG is whatever is set or clobbered. SETTER is the rtx that
2084 is modifying the register.
2086 If it is not really a register, we do nothing.
2087 The file-global variables `this_insn' and `this_insn_number'
2088 carry info from `block_alloc'. */
2091 reg_is_set (rtx reg
, const_rtx setter
, void *data ATTRIBUTE_UNUSED
)
2093 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2094 a hard register. These may actually not exist any more. */
2096 if (GET_CODE (reg
) != SUBREG
2100 /* Mark this register as being born. If it is used in a CLOBBER, mark
2101 it as being born halfway between the previous insn and this insn so that
2102 it conflicts with our inputs but not the outputs of the previous insn. */
2104 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2107 /* Handle beginning of the life of register REG.
2108 BIRTH is the index at which this is happening. */
2111 reg_is_born (rtx reg
, int birth
)
2115 if (GET_CODE (reg
) == SUBREG
)
2117 regno
= REGNO (SUBREG_REG (reg
));
2118 if (regno
< FIRST_PSEUDO_REGISTER
)
2119 regno
= subreg_regno (reg
);
2122 regno
= REGNO (reg
);
2124 if (regno
< FIRST_PSEUDO_REGISTER
)
2126 mark_life (regno
, GET_MODE (reg
), 1);
2128 /* If the register was to have been born earlier that the present
2129 insn, mark it as live where it is actually born. */
2130 if (birth
< 2 * this_insn_number
)
2131 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2135 if (reg_qty
[regno
] == -2)
2136 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2138 /* If this register has a quantity number, show that it isn't dead. */
2139 if (reg_qty
[regno
] >= 0)
2140 qty
[reg_qty
[regno
]].death
= -1;
2144 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2145 REG is an output that is dying (i.e., it is never used), otherwise it
2146 is an input (the normal case).
2147 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2150 wipe_dead_reg (rtx reg
, int output_p
)
2152 int regno
= REGNO (reg
);
2154 /* If this insn has multiple results,
2155 and the dead reg is used in one of the results,
2156 extend its life to after this insn,
2157 so it won't get allocated together with any other result of this insn.
2159 It is unsafe to use !single_set here since it will ignore an unused
2160 output. Just because an output is unused does not mean the compiler
2161 can assume the side effect will not occur. Consider if REG appears
2162 in the address of an output and we reload the output. If we allocate
2163 REG to the same hard register as an unused output we could set the hard
2164 register before the output reload insn. */
2165 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2166 && multiple_sets (this_insn
))
2169 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2171 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2172 if (GET_CODE (set
) == SET
2173 && !REG_P (SET_DEST (set
))
2174 && !rtx_equal_p (reg
, SET_DEST (set
))
2175 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2180 /* If this register is used in an auto-increment address, then extend its
2181 life to after this insn, so that it won't get allocated together with
2182 the result of this insn. */
2183 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2186 if (regno
< FIRST_PSEUDO_REGISTER
)
2188 mark_life (regno
, GET_MODE (reg
), 0);
2190 /* If a hard register is dying as an output, mark it as in use at
2191 the beginning of this insn (the above statement would cause this
2194 post_mark_life (regno
, GET_MODE (reg
), 1,
2195 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2198 else if (reg_qty
[regno
] >= 0)
2199 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2202 /* Find a block of SIZE words of hard regs in reg_class CLASS
2203 that can hold something of machine-mode MODE
2204 (but actually we test only the first of the block for holding MODE)
2205 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2206 and return the number of the first of them.
2207 Return -1 if such a block cannot be found.
2208 If QTYNO crosses calls, insist on a register preserved by calls,
2209 unless ACCEPT_CALL_CLOBBERED is nonzero.
2211 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2212 register is available. If not, return -1. */
2215 find_free_reg (enum reg_class
class, enum machine_mode mode
, int qtyno
,
2216 int accept_call_clobbered
, int just_try_suggested
,
2217 int born_index
, int dead_index
)
2220 HARD_REG_SET first_used
, used
;
2221 #ifdef ELIMINABLE_REGS
2222 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2225 /* Validate our parameters. */
2226 gcc_assert (born_index
>= 0 && born_index
<= dead_index
);
2228 /* Don't let a pseudo live in a reg across a function call
2229 if we might get a nonlocal goto. */
2230 if (cfun
->has_nonlocal_label
2231 && qty
[qtyno
].n_calls_crossed
> 0)
2234 if (accept_call_clobbered
)
2235 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2236 else if (qty
[qtyno
].n_calls_crossed
== 0)
2237 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2239 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2241 if (accept_call_clobbered
)
2242 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2244 for (ins
= born_index
; ins
< dead_index
; ins
++)
2245 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2247 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2249 /* Don't use the frame pointer reg in local-alloc even if
2250 we may omit the frame pointer, because if we do that and then we
2251 need a frame pointer, reload won't know how to move the pseudo
2252 to another hard reg. It can move only regs made by global-alloc.
2254 This is true of any register that can be eliminated. */
2255 #ifdef ELIMINABLE_REGS
2256 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2257 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2258 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2259 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2260 that it might be eliminated into. */
2261 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2264 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2267 #ifdef CANNOT_CHANGE_MODE_CLASS
2268 cannot_change_mode_set_regs (&used
, mode
, qty
[qtyno
].first_reg
);
2271 /* Normally, the registers that can be used for the first register in
2272 a multi-register quantity are the same as those that can be used for
2273 subsequent registers. However, if just trying suggested registers,
2274 restrict our consideration to them. If there are copy-suggested
2275 register, try them. Otherwise, try the arithmetic-suggested
2277 COPY_HARD_REG_SET (first_used
, used
);
2279 if (just_try_suggested
)
2281 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2282 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2284 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2287 /* If at least one would be suitable, test each hard reg. */
2288 if (!hard_reg_set_subset_p (reg_class_contents
[(int) ALL_REGS
], first_used
))
2289 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2291 #ifdef REG_ALLOC_ORDER
2292 int regno
= reg_alloc_order
[i
];
2296 if (!TEST_HARD_REG_BIT (first_used
, regno
)
2297 && HARD_REGNO_MODE_OK (regno
, mode
)
2298 && (qty
[qtyno
].n_calls_crossed
== 0
2299 || accept_call_clobbered
2300 || !HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2303 int size1
= hard_regno_nregs
[regno
][mode
];
2305 while (j
< size1
&& !TEST_HARD_REG_BIT (used
, regno
+ j
))
2309 /* Mark that this register is in use between its birth
2311 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2314 #ifndef REG_ALLOC_ORDER
2315 /* Skip starting points we know will lose. */
2321 /* If we are just trying suggested register, we have just tried copy-
2322 suggested registers, and there are arithmetic-suggested registers,
2325 /* If it would be profitable to allocate a call-clobbered register
2326 and save and restore it around calls, do that. */
2327 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2328 && qty_phys_num_sugg
[qtyno
] != 0)
2330 /* Don't try the copy-suggested regs again. */
2331 qty_phys_num_copy_sugg
[qtyno
] = 0;
2332 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2333 born_index
, dead_index
);
2336 /* We need not check to see if the current function has nonlocal
2337 labels because we don't put any pseudos that are live over calls in
2338 registers in that case. Avoid putting pseudos crossing calls that
2339 might throw into call used registers. */
2341 if (! accept_call_clobbered
2342 && flag_caller_saves
2343 && ! just_try_suggested
2344 && qty
[qtyno
].n_calls_crossed
!= 0
2345 && qty
[qtyno
].n_throwing_calls_crossed
== 0
2346 && CALLER_SAVE_PROFITABLE (optimize_size
? qty
[qtyno
].n_refs
: qty
[qtyno
].freq
,
2347 optimize_size
? qty
[qtyno
].n_calls_crossed
2348 : qty
[qtyno
].freq_calls_crossed
))
2350 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2352 caller_save_needed
= 1;
2358 /* Mark that REGNO with machine-mode MODE is live starting from the current
2359 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2363 mark_life (int regno
, enum machine_mode mode
, int life
)
2366 add_to_hard_reg_set (®s_live
, mode
, regno
);
2368 remove_from_hard_reg_set (®s_live
, mode
, regno
);
2371 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2372 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2373 to insn number DEATH (exclusive). */
2376 post_mark_life (int regno
, enum machine_mode mode
, int life
, int birth
,
2379 HARD_REG_SET this_reg
;
2381 CLEAR_HARD_REG_SET (this_reg
);
2382 add_to_hard_reg_set (&this_reg
, mode
, regno
);
2385 while (birth
< death
)
2387 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2391 while (birth
< death
)
2393 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2398 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2399 is the register being clobbered, and R1 is a register being used in
2400 the equivalent expression.
2402 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2403 in which it is used, return 1.
2405 Otherwise, return 0. */
2408 no_conflict_p (rtx insn
, rtx r0 ATTRIBUTE_UNUSED
, rtx r1
)
2411 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2414 /* If R1 is a hard register, return 0 since we handle this case
2415 when we scan the insns that actually use it. */
2418 || (REG_P (r1
) && REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2419 || (GET_CODE (r1
) == SUBREG
&& REG_P (SUBREG_REG (r1
))
2420 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2423 last
= XEXP (note
, 0);
2425 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2428 if (find_reg_note (p
, REG_DEAD
, r1
))
2431 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2432 some earlier optimization pass has inserted instructions into
2433 the sequence, and it is not safe to perform this optimization.
2434 Note that emit_no_conflict_block always ensures that this is
2435 true when these sequences are created. */
2436 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2443 /* Return the number of alternatives for which the constraint string P
2444 indicates that the operand must be equal to operand 0 and that no register
2448 requires_inout (const char *p
)
2452 int reg_allowed
= 0;
2453 int num_matching_alts
= 0;
2456 for ( ; (c
= *p
); p
+= len
)
2458 len
= CONSTRAINT_LEN (c
, p
);
2461 case '=': case '+': case '?':
2462 case '#': case '&': case '!':
2464 case 'm': case '<': case '>': case 'V': case 'o':
2465 case 'E': case 'F': case 'G': case 'H':
2466 case 's': case 'i': case 'n':
2467 case 'I': case 'J': case 'K': case 'L':
2468 case 'M': case 'N': case 'O': case 'P':
2470 /* These don't say anything we care about. */
2474 if (found_zero
&& ! reg_allowed
)
2475 num_matching_alts
++;
2477 found_zero
= reg_allowed
= 0;
2484 case '1': case '2': case '3': case '4': case '5':
2485 case '6': case '7': case '8': case '9':
2486 /* Skip the balance of the matching constraint. */
2489 while (ISDIGIT (*p
));
2494 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
2495 && !EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2505 if (found_zero
&& ! reg_allowed
)
2506 num_matching_alts
++;
2508 return num_matching_alts
;
2512 dump_local_alloc (FILE *file
)
2515 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2516 if (reg_renumber
[i
] != -1)
2517 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);
2522 find_stack_regs (void)
2524 bitmap stack_regs
= BITMAP_ALLOC (NULL
);
2526 HARD_REG_SET stack_hard_regs
, used
;
2529 /* Any register that MAY be allocated to a register stack (like the
2530 387) is treated poorly. Each such register is marked as being
2531 live everywhere. This keeps the register allocator and the
2532 subsequent passes from doing anything useful with these values.
2534 FIXME: This seems like an incredibly poor idea. */
2536 CLEAR_HARD_REG_SET (stack_hard_regs
);
2537 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
2538 SET_HARD_REG_BIT (stack_hard_regs
, i
);
2540 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2542 COPY_HARD_REG_SET (used
, reg_class_contents
[reg_preferred_class (i
)]);
2543 IOR_HARD_REG_SET (used
, reg_class_contents
[reg_alternate_class (i
)]);
2544 AND_HARD_REG_SET (used
, stack_hard_regs
);
2545 if (!hard_reg_set_empty_p (used
))
2546 bitmap_set_bit (stack_regs
, i
);
2550 bitmap_print (dump_file
, stack_regs
, "stack regs:", "\n");
2554 bitmap_ior_into (DF_LIVE_IN (bb
), stack_regs
);
2555 bitmap_and_into (DF_LIVE_IN (bb
), DF_LR_IN (bb
));
2556 bitmap_ior_into (DF_LIVE_OUT (bb
), stack_regs
);
2557 bitmap_and_into (DF_LIVE_OUT (bb
), DF_LR_OUT (bb
));
2559 BITMAP_FREE (stack_regs
);
2563 /* Run old register allocator. Return TRUE if we must exit
2564 rest_of_compilation upon return. */
2566 rest_of_handle_local_alloc (void)
2569 int max_regno
= max_reg_num ();
2571 df_note_add_problem ();
2575 df_live_add_problem ();
2576 df_live_set_all_dirty ();
2578 #ifdef ENABLE_CHECKING
2579 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
2586 regstat_init_n_sets_and_refs ();
2587 regstat_compute_ri ();
2589 /* If we are not optimizing, then this is the only place before
2590 register allocation where dataflow is done. And that is needed
2591 to generate these warnings. */
2593 generate_setjmp_warnings ();
2595 /* Determine if the current function is a leaf before running reload
2596 since this can impact optimizations done by the prologue and
2597 epilogue thus changing register elimination offsets. */
2598 current_function_is_leaf
= leaf_function_p ();
2600 /* And the reg_equiv_memory_loc array. */
2601 VEC_safe_grow (rtx
, gc
, reg_equiv_memory_loc_vec
, max_regno
);
2602 memset (VEC_address (rtx
, reg_equiv_memory_loc_vec
), 0,
2603 sizeof (rtx
) * max_regno
);
2604 reg_equiv_memory_loc
= VEC_address (rtx
, reg_equiv_memory_loc_vec
);
2606 allocate_initial_values (reg_equiv_memory_loc
);
2608 regclass (get_insns (), max_regno
);
2609 rebuild_notes
= local_alloc ();
2611 /* Local allocation may have turned an indirect jump into a direct
2612 jump. If so, we must rebuild the JUMP_LABEL fields of jumping
2616 timevar_push (TV_JUMP
);
2618 rebuild_jump_labels (get_insns ());
2619 purge_all_dead_edges ();
2620 timevar_pop (TV_JUMP
);
2623 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2625 timevar_push (TV_DUMP
);
2626 dump_flow_info (dump_file
, dump_flags
);
2627 dump_local_alloc (dump_file
);
2628 timevar_pop (TV_DUMP
);
2633 struct rtl_opt_pass pass_local_alloc
=
2639 rest_of_handle_local_alloc
, /* execute */
2642 0, /* static_pass_number */
2643 TV_LOCAL_ALLOC
, /* tv_id */
2644 0, /* properties_required */
2645 0, /* properties_provided */
2646 0, /* properties_destroyed */
2647 0, /* todo_flags_start */
2649 TODO_ggc_collect
/* todo_flags_finish */