1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998-2013 Free Software Foundation, Inc.
3 ;; Contributed by Axis Communications.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The original PO technology requires these to be ordered by speed,
22 ;; so that assigner will pick the fastest.
24 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
27 ;; The function cris_notice_update_cc in cris.c handles condition code
28 ;; updates for most instructions, helped by the "cc" attribute.
30 ;; There are several instructions that are orthogonal in size, and seems
31 ;; they could be matched by a single pattern without a specified size
32 ;; for the operand that is orthogonal. However, this did not work on
33 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
34 ;; constant is substituted into an operand, the actual mode must be
35 ;; deduced from the pattern. There is reasonable hope that that has been
36 ;; fixed, so FIXME: try again.
38 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
39 ;; are marked with a "!" constraint modifier to avoid being reloaded
40 ;; into. This is because gcc would otherwise prefer to use the constant
41 ;; pool and its offsettable address instead of reloading to an
42 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
43 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
45 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
46 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
47 ;; pointer). Thus the instructions that get into trouble have specific
48 ;; checks against matching frame_pointer_rtx.
49 ;; ??? But it should be re-checked for gcc > 2.7.2
50 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
52 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
53 ;; [rX=gotless_symbol].
54 ;; The movsi for a gotless symbol could be split (post reload).
59 ;; PLT reference from call expansion: operand 0 is the address,
60 ;; the mode is VOIDmode. Always wrapped in CONST.
61 ;; The value is relative to the GOT.
62 CRIS_UNSPEC_PLT_GOTREL
64 ;; PLT reference from call expansion: operand 0 is the address,
65 ;; the mode is VOIDmode. Always wrapped in CONST.
66 ;; The value is relative to the PC. It's arch-dependent whether
67 ;; the offset counts from the start or the end of the current item.
70 ;; The address of the global offset table as a source operand.
73 ;; The offset from the global offset table to the operand.
76 ;; The PC-relative offset to the operand. It's arch-dependent whether
77 ;; the offset counts from the start or the end of the current item.
80 ;; The index into the global offset table of a symbol, while
81 ;; also generating a GOT entry for the symbol.
84 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
85 CRIS_UNSPEC_PLTGOTREAD
87 ;; Condition for v32 casesi jump, since it needs to have if_then_else
88 ;; form with register as one branch and default label as other.
89 ;; Operand 0 is const_int 0.
92 ;; Stack frame deallocation barrier.
93 CRIS_UNSPEC_FRAME_DEALLOC
95 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
102 (CRIS_STATIC_CHAIN_REGNUM 7)
109 (CRIS_CC0_REGNUM 19)]
112 ;; We need an attribute to define whether an instruction can be put in
113 ;; a branch-delay slot or not, and whether it has a delay slot.
115 ;; Branches and return instructions have a delay slot, and cannot
116 ;; themselves be put in a delay slot. This has changed *for short
117 ;; branches only* between architecture variants, but the possible win
118 ;; is presumed negligible compared to the added complexity of the machine
119 ;; description: one would have to add always-correct infrastructure to
120 ;; distinguish short branches.
122 ;; Whether an instruction can be put in a delay slot depends on the
123 ;; instruction (all short instructions except jumps and branches)
124 ;; and the addressing mode (must not be prefixed or referring to pc).
125 ;; In short, any "slottable" instruction must be 16 bit and not refer
126 ;; to pc, or alter it.
128 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
129 ;; and "has_call_slot".
130 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
131 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
132 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
133 ;; call delay slot, as it's located in the address *after* the call insn,
134 ;; and the unwind machinery doesn't know about delay slots.
135 ;; Has_slot means that the insn is a branch insn (which are
136 ;; not considered slottable since that is generally true). Having the
137 ;; seemingly illogical value "has_slot" means we do not have to add
138 ;; another attribute just to say that an insn has a delay-slot, since it
139 ;; also infers that it is not slottable. Better names for the attribute
140 ;; were found to be longer and not add readability to the machine
142 ;; Has_return_slot is similar, for the return insn.
144 ;; The default that is defined here for this attribute is "no", not
145 ;; slottable, not having a delay-slot, so there's no need to worry about
146 ;; it being wrong for non-branch and return instructions.
147 ;; The default could depend on the kind of insn and the addressing
148 ;; mode, but that would need more attributes and hairier, more error
151 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
152 ;; register. The constraints 'Q' and '>' together match all possible
153 ;; memory operands that are slottable.
154 ;; For other operands, you need to check if it has a valid "slottable"
155 ;; quick-immediate operand, where the particular signedness-variation
156 ;; may match the constraints 'I' or 'J'.), and include it in the
157 ;; constraint pattern for the slottable pattern. An alternative using
158 ;; only "r" constraints is most often slottable.
160 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
163 ;; We also need attributes to sanely determine the condition code
164 ;; state. See cris_notice_update_cc for how this is used.
166 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
168 ;; At the moment, this attribute is just used to help bb-reorder do its
169 ;; work; the default 0 doesn't help it. Many insns have other lengths,
170 ;; though none are shorter.
171 (define_attr "length" "" (const_int 2))
173 ;; A branch has one delay-slot. The instruction in the
174 ;; delay-slot is always executed, independent of whether the branch is
175 ;; taken or not. Note that besides setting "slottable" to "has_slot",
176 ;; there also has to be a "%#" at the end of a "delayed" instruction
177 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
178 ;; catch it and print a "nop" if necessary. This method was stolen from
181 (define_delay (eq_attr "slottable" "has_slot")
182 [(eq_attr "slottable" "yes") (nil) (nil)])
184 ;; We can't put prologue insns in call-insn delay-slots when
185 ;; DWARF2 unwind info is emitted, because the unwinder matches the
186 ;; address after the insn. It must see the return address of a call at
187 ;; a position at least *one byte after* the insn, or it'll think that
188 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
189 ;; call, it's just *exactly* after the insn.
191 (define_delay (eq_attr "slottable" "has_call_slot")
192 [(and (eq_attr "slottable" "yes")
193 (ior (not (match_test "RTX_FRAME_RELATED_P (insn)"))
194 (not (match_test "flag_exceptions"))))
197 ;; The insn in the return insn slot must not be the
198 ;; return-address-register restore. FIXME: Use has_slot and express
199 ;; as a parallel with a use of the return-address-register (currently
200 ;; only SRP). However, this requires an amount of fixing tests for
201 ;; naked RETURN in middle-end.
202 (define_delay (eq_attr "slottable" "has_return_slot")
203 [(and (eq_attr "slottable" "yes")
204 (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")))
208 ;; Iterator definitions.
210 ;; For the "usual" pattern size alternatives.
211 (define_mode_iterator BWD [SI HI QI])
212 (define_mode_iterator WD [SI HI])
213 (define_mode_iterator BW [HI QI])
214 (define_mode_attr S [(SI "HI") (HI "QI")])
215 (define_mode_attr s [(SI "hi") (HI "qi")])
216 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
217 (define_mode_attr mm [(SI ".w") (HI ".b")])
218 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
220 ;; For the sign_extend+zero_extend variants.
221 (define_code_iterator szext [sign_extend zero_extend])
222 (define_code_attr u [(sign_extend "") (zero_extend "u")])
223 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
225 ;; For the shift variants.
226 (define_code_iterator shift [ashiftrt lshiftrt ashift])
227 (define_code_iterator shiftrt [ashiftrt lshiftrt])
228 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
229 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
231 (define_code_iterator ncond [eq ne gtu ltu geu leu])
232 (define_code_iterator ocond [gt le])
233 (define_code_iterator rcond [lt ge])
234 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
235 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
236 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
237 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
238 (define_code_attr oCC [(lt "mi") (ge "pl")])
239 (define_code_attr roCC [(lt "pl") (ge "mi")])
241 ;; Operand and operator predicates.
243 (include "predicates.md")
244 (include "constraints.md")
248 ;; No test insns with side-effect on the mem addressing.
250 ;; See note on cmp-insns with side-effects (or lack of them)
252 ;; Normal named test patterns from SI on.
254 (define_insn "*tstsi"
256 (compare (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m")
260 if (which_alternative == 0 && TARGET_V32)
264 [(set_attr "slottable" "yes,yes,no")])
266 (define_insn "*tst<mode>_cmp"
268 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
270 "cris_cc0_user_requires_cmp (insn)"
275 [(set_attr "slottable" "no,yes,no")])
277 (define_insn "*tst<mode>_non_cmp"
279 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
281 "!cris_cc0_user_requires_cmp (insn)"
286 [(set_attr "slottable" "yes,yes,no")
287 (set_attr "cc" "noov32,*,*")])
289 ;; It seems that the position of the sign-bit and the fact that 0.0 is
290 ;; all 0-bits would make "tstsf" a straight-forward implementation;
291 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
294 ;; FIXME: Do that some time; check next_cc0_user to determine if
295 ;; zero or negative is tested for.
299 ;; We could optimize the sizes of the immediate operands for various
300 ;; cases, but that is not worth it because of the very little usage of
301 ;; DImode for anything else but a structure/block-mode. Just do the
302 ;; obvious stuff for the straight-forward constraint letters.
304 (define_insn "*cmpdi_non_v32"
306 (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o")
307 (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))]
310 test.d %M0\;ax\;test.d %H0
311 cmpq %1,%M0\;ax\;cmpq 0,%H0
312 cmpq %1,%M0\;ax\;cmpq -1,%H0
313 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
314 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
315 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
316 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
317 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
319 (define_insn "*cmpdi_v32"
321 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r")
322 (match_operand:DI 1 "nonmemory_operand" "Kc,I,P,n,r")))]
325 cmpq %1,%M0\;ax\;cmpq 0,%H0
326 cmpq %1,%M0\;ax\;cmpq -1,%H0
327 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
328 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
329 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
331 ;; Note that compare insns with side effect addressing mode (e.g.):
333 ;; cmp.S [rx=ry+i],rz;
334 ;; cmp.S [%3=%1+%2],%0
336 ;; are *not* usable for gcc since the reloader *does not accept*
337 ;; cc0-changing insns with side-effects other than setting the condition
338 ;; codes. The reason is that the reload stage *may* cause another insn to
339 ;; be output after the main instruction, in turn invalidating cc0 for the
340 ;; insn using the test. (This does not apply to the CRIS case, since a
341 ;; reload for output -- move to memory -- does not change the condition
342 ;; code. Unfortunately we have no way to describe that at the moment. I
343 ;; think code would improve being in the order of one percent faster.
345 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
346 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
347 ;; constants, but sometimes gcc will find its way to use it for other
348 ;; (memory) operands. Avoid side-effect patterns, though (see above).
350 (define_insn "*cmp_ext<mode>"
353 (match_operand:SI 0 "register_operand" "r,r")
354 (match_operator:SI 2 "cris_extend_operator"
355 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
358 [(set_attr "slottable" "yes,no")])
360 ;; Swap operands; it seems the canonical look (if any) is not enforced.
362 ;; FIXME: Investigate that.
364 (define_insn "*cmp_swapext<mode>"
367 (match_operator:SI 2 "cris_extend_operator"
368 [(match_operand:BW 0 "memory_operand" "Q>,m")])
369 (match_operand:SI 1 "register_operand" "r,r")))]
372 [(set_attr "slottable" "yes,no")
373 (set_attr "cc" "rev")])
375 ;; The "normal" compare patterns, from SI on. Special-cases with zero
376 ;; are covered above.
378 (define_insn "*cmpsi"
381 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
382 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))]
392 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
393 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
395 (define_insn "*cmp<mode>"
397 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
398 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
406 [(set_attr "slottable" "yes,yes,yes,no,no")
407 (set_attr "cc" "normal,normal,rev,normal,rev")])
409 ;; Pattern matching the BTST insn.
410 ;; It is useful for "if (i & val)" constructs, where val is an exact
411 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
412 ;; of zeros starting at bit 0).
414 ;; SImode. This mode is the only one needed, since gcc automatically
415 ;; extends subregs for lower-size modes. FIXME: Add testcase.
420 (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp")
421 (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n")
422 (match_operand:SI 2 "nonmemory_operand" "M, M,Kc,n,r, r,r"))
424 ;; Either it is a single bit, or consecutive ones starting at 0.
425 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
426 "CONST_INT_P (operands[1])
427 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
428 && (REG_S_P (operands[0])
429 || (operands[1] == const1_rtx
430 && REG_S_P (operands[2])
431 && CONST_INT_P (operands[0])
432 && exact_log2 (INTVAL (operands[0])) >= 0))
435 ;; The next-to-last "&&" condition above should be caught by some kind of
436 ;; canonicalization in gcc, but we can easily help with it here.
437 ;; It results from expressions of the type
438 ;; "power_of_2_value & (1 << y)".
440 ;; Since there may be codes with tests in on bits (in constant position)
441 ;; beyond the size of a word, handle that by assuming those bits are 0.
442 ;; GCC should handle that, but it's a matter of easily-added belts while
443 ;; having suspenders.
453 [(set_attr "slottable" "yes")
454 (set_attr "cc" "noov32")])
458 ;; The whole mandatory movdi family is here; expander, "anonymous"
459 ;; recognizer and splitter. We're forced to have a movdi pattern,
460 ;; although GCC should be able to split it up itself. Normally it can,
461 ;; but if other insns have DI operands (as is the case here), reload
462 ;; must be able to generate or match a movdi. many testcases fail at
463 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
464 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
465 ;; However, a patch from Richard Kenner (similar to the cause of
466 ;; discussion at the URL above), indicates otherwise. See
467 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
468 ;; The truth has IMO is not been decided yet, so check from time to
469 ;; time by disabling the movdi patterns.
471 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
472 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
473 ;; A cmpdi RTX needs reloading (global):
474 ;; (insn 185 326 186 (set (cc0)
475 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
476 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
478 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
479 ;; out of the instruction (into a register), since one of the operands
480 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
481 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
482 ;; wrt. overlap). The bad things happen with the synthesis in
483 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
484 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
485 ;; 22 is recognized to have an equivalent in memory which is substituted
486 ;; straight in, and we end up with an unrecognizable insn:
487 ;; (insn 325 324 326 (set (reg:SI 9 r9)
488 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
489 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
491 ;; which is the first part of the reloaded synthesized "movdi".
492 ;; The right thing would be to add equivalent replacement locations for
493 ;; insn with pseudos that need more reloading. The question is where.
495 (define_expand "movdi"
496 [(set (match_operand:DI 0 "nonimmediate_operand" "")
497 (match_operand:DI 1 "general_operand" ""))]
500 if (MEM_P (operands[0])
501 && operands[1] != const0_rtx
502 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ())))
503 operands[1] = copy_to_mode_reg (DImode, operands[1]);
505 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
506 prefer to split up constants early, like this. The testcase in
507 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
508 resulting subreg sets when using the construct from mcore (as of FSF
509 CVS, version -r 1.5), and it believes that the high part (the last one
510 emitted) is the final value. */
511 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
512 && ! reload_completed
513 && ! reload_in_progress)
516 rtx op0 = operands[0];
517 rtx op1 = operands[1];
520 emit_move_insn (operand_subword (op0, 0, 1, DImode),
521 operand_subword (op1, 0, 1, DImode));
522 emit_move_insn (operand_subword (op0, 1, 1, DImode),
523 operand_subword (op1, 1, 1, DImode));
524 insns = get_insns ();
532 (define_insn_and_split "*movdi_insn_non_v32"
533 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
534 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
535 "(register_operand (operands[0], DImode)
536 || register_operand (operands[1], DImode)
537 || operands[1] == const0_rtx)
540 "&& reload_completed"
542 "operands[2] = cris_split_movdx (operands);")
544 ;; Overlapping (but non-identical) source memory address and destination
545 ;; register would be a compiler bug, so we don't have to specify that.
546 (define_insn "*movdi_v32"
548 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
549 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
552 switch (which_alternative)
554 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2,
555 particularly for cases where the address register is dead. */
557 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
558 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0";
559 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0)));
560 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
562 /* We could do away with the addq if we knew the address-register
563 isn't ACR. If we knew the address-register is dead, we could do
564 away with the subq too. */
565 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1";
567 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0";
569 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1";
571 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0";
577 ;; The non-split cases clobber cc0 because of their adds and subs.
578 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
579 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
581 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
582 ;; is handled so much better in cris_split_movdx.
584 [(set (match_operand:DI 0 "nonimmediate_operand" "")
585 (match_operand:DI 1 "general_operand" ""))]
588 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0)))
589 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))"
591 "operands[2] = cris_split_movdx (operands);")
593 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
594 ;; and move.S1 [rx=ry+i],rz
595 ;; Then movs.S1 and movu.S1 for both modes.
597 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
598 ;; FIXME: These could have anonymous mode for operand 0.
599 ;; FIXME: Special registers' alternatives too.
601 (define_insn "*mov_side<mode>_biap"
602 [(set (match_operand:BW 0 "register_operand" "=r,r")
604 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
605 (match_operand:SI 2 "const_int_operand" "n,n"))
606 (match_operand:SI 3 "register_operand" "r,r"))))
607 (set (match_operand:SI 4 "register_operand" "=*3,r")
608 (plus:SI (mult:SI (match_dup 1)
611 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
614 move<m> [%4=%3+%1%T2],%0")
616 (define_insn "*mov_sidesisf_biap"
617 [(set (match_operand 0 "register_operand" "=r,r,x,x")
619 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
620 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
621 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
622 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
623 (plus:SI (mult:SI (match_dup 1)
626 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
627 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
630 move.%s0 [%4=%3+%1%T2],%0
632 move [%4=%3+%1%T2],%0")
634 ;; move.S1 [rx=ry+i],rz
635 ;; avoiding move.S1 [ry=ry+i],rz
636 ;; and move.S1 [rz=ry+i],rz
637 ;; Note that "i" is allowed to be a register.
639 (define_insn "*mov_side<mode>"
640 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
642 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
643 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
644 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
645 (plus:SI (match_dup 1)
647 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
649 if ((which_alternative == 0 || which_alternative == 3)
650 && (!CONST_INT_P (operands[2])
651 || INTVAL (operands[2]) > 127
652 || INTVAL (operands[2]) < -128
653 || satisfies_constraint_N (operands[2])
654 || satisfies_constraint_J (operands[2])))
656 if (which_alternative == 4)
657 return "move<m> [%3=%2%S1],%0";
658 return "move<m> [%3=%1%S2],%0";
661 (define_insn "*mov_sidesisf"
662 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
665 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
666 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
667 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
668 (plus:SI (match_dup 1)
670 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
671 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
673 if ((which_alternative == 0
674 || which_alternative == 3
675 || which_alternative == 6
676 || which_alternative == 8)
677 && (!CONST_INT_P (operands[2])
678 || INTVAL (operands[2]) > 127
679 || INTVAL (operands[2]) < -128
680 || satisfies_constraint_N (operands[2])
681 || satisfies_constraint_J (operands[2])))
683 if (which_alternative < 3)
684 return "move.%s0 [%3=%1%S2],%0";
685 if (which_alternative == 7)
686 return "move.%s0 [%3=%2%S1],%0";
687 if (which_alternative == 9)
688 return "move [%3=%2%S1],%0";
689 return "move [%3=%1%S2],%0";
692 ;; Other way around; move to memory.
694 ;; Note that the condition (which for side-effect patterns is usually a
695 ;; call to cris_side_effect_mode_ok), isn't consulted for register
696 ;; allocation preferences -- constraints is the method for that. The
697 ;; drawback is that we can't exclude register allocation to cause
698 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
699 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
700 ;; Instead of that, we recognize and split the cases where dangerous
701 ;; register combinations are spotted: where a register is set in the
702 ;; side-effect, and used in the main insn. We don't handle the case where
703 ;; the set in the main insn overlaps the set in the side-effect; that case
704 ;; must be handled in gcc. We handle just the case where the set in the
705 ;; side-effect overlaps the input operand of the main insn (i.e. just
709 ;; move.s rz,[ry=rx+rw.S]
711 (define_insn "*mov_side<mode>_biap_mem"
712 [(set (mem:BW (plus:SI
713 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
714 (match_operand:SI 1 "const_int_operand" "n,n,n"))
715 (match_operand:SI 2 "register_operand" "r,r,r")))
716 (match_operand:BW 3 "register_operand" "r,r,r"))
717 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
718 (plus:SI (mult:SI (match_dup 0)
721 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
725 move<m> %3,[%4=%2+%0%T1]")
727 (define_insn "*mov_sidesisf_biap_mem"
729 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
730 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
731 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
732 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
733 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
734 (plus:SI (mult:SI (match_dup 0)
737 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
738 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
742 move.%s3 %3,[%4=%2+%0%T1]
745 move %3,[%4=%2+%0%T1]")
747 ;; Split for the case above where we're out of luck with register
748 ;; allocation (again, the condition isn't checked for that), and we end up
749 ;; with the set in the side-effect getting the same register as the input
754 [(set (match_operator
757 (mult:SI (match_operand:SI 0 "register_operand" "")
758 (match_operand:SI 1 "const_int_operand" ""))
759 (match_operand:SI 2 "register_operand" ""))])
760 (match_operand 3 "register_operand" ""))
761 (set (match_operand:SI 4 "register_operand" "")
762 (plus:SI (mult:SI (match_dup 0)
765 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
766 [(set (match_dup 5) (match_dup 3))
767 (set (match_dup 4) (match_dup 2))
769 (plus:SI (mult:SI (match_dup 0)
773 = replace_equiv_address (operands[6],
774 gen_rtx_PLUS (SImode,
775 gen_rtx_MULT (SImode,
780 ;; move.s rx,[ry=rz+i]
781 ;; FIXME: These could have anonymous mode for operand 2.
785 (define_insn "*mov_side<mode>_mem"
787 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
788 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
789 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
790 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
791 (plus:SI (match_dup 0)
793 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
795 if ((which_alternative == 0 || which_alternative == 4)
796 && (!CONST_INT_P (operands[1])
797 || INTVAL (operands[1]) > 127
798 || INTVAL (operands[1]) < -128
799 || satisfies_constraint_N (operands[1])
800 || satisfies_constraint_J (operands[1])))
802 if (which_alternative == 1 || which_alternative == 5)
804 if (which_alternative == 6)
805 return "move.%s2 %2,[%3=%1%S0]";
806 return "move<m> %2,[%3=%0%S1]";
811 (define_insn "*mov_sidesisf_mem"
815 0 "cris_bdap_operand"
816 "%r, r, r,r, r, r,r, R,R, R,R, R")
818 1 "cris_bdap_operand"
819 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
820 (match_operand 2 "register_operand"
821 "r, r, r,r, x, x,x, r,r, r,x, x"))
822 (set (match_operand:SI 3 "register_operand"
823 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
824 (plus:SI (match_dup 0)
826 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
827 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
829 if ((which_alternative == 0 || which_alternative == 4)
830 && (!CONST_INT_P (operands[1])
831 || INTVAL (operands[1]) > 127
832 || INTVAL (operands[1]) < -128
833 || satisfies_constraint_N (operands[1])
834 || satisfies_constraint_J (operands[1])))
836 if (which_alternative == 1
837 || which_alternative == 7
838 || which_alternative == 8
839 || which_alternative == 10)
841 if (which_alternative < 4)
842 return "move.%s2 %2,[%3=%0%S1]";
843 if (which_alternative == 9)
844 return "move.%s2 %2,[%3=%1%S0]";
845 if (which_alternative == 11)
846 return "move %2,[%3=%1%S0]";
847 return "move %2,[%3=%0%S1]";
850 ;; Like the biap case, a split where the set in the side-effect gets the
851 ;; same register as the input register to the main insn, since the
852 ;; condition isn't checked at register allocation.
856 [(set (match_operator
859 (match_operand:SI 0 "cris_bdap_operand" "")
860 (match_operand:SI 1 "cris_bdap_operand" ""))])
861 (match_operand 2 "register_operand" ""))
862 (set (match_operand:SI 3 "register_operand" "")
863 (plus:SI (match_dup 0) (match_dup 1)))])]
864 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
865 [(set (match_dup 4) (match_dup 2))
866 (set (match_dup 3) (match_dup 0))
867 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
870 ;; Clear memory side-effect patterns. It is hard to get to the mode if
871 ;; the MEM was anonymous, so there will be one for each mode.
873 ;; clear.[bwd] [ry=rx+rw.s2]
875 (define_insn "*clear_side<mode>_biap"
876 [(set (mem:BWD (plus:SI
877 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
878 (match_operand:SI 1 "const_int_operand" "n,n"))
879 (match_operand:SI 2 "register_operand" "r,r")))
881 (set (match_operand:SI 3 "register_operand" "=*2,r")
882 (plus:SI (mult:SI (match_dup 0)
885 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
888 clear<m> [%3=%2+%0%T1]")
890 ;; clear.[bwd] [ry=rz+i]
892 (define_insn "*clear_side<mode>"
894 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
895 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
897 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
898 (plus:SI (match_dup 0)
900 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
902 if ((which_alternative == 0 || which_alternative == 3)
903 && (!CONST_INT_P (operands[1])
904 || INTVAL (operands[1]) > 127
905 || INTVAL (operands[1]) < -128
906 || satisfies_constraint_N (operands[1])
907 || satisfies_constraint_J (operands[1])))
909 if (which_alternative == 4)
910 return "clear<m> [%2=%1%S0]";
911 return "clear<m> [%2=%0%S1]";
914 ;; Normal move patterns from SI on.
916 (define_expand "movsi"
918 (match_operand:SI 0 "nonimmediate_operand" "")
919 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
922 /* If the output goes to a MEM, make sure we have zero or a register as
924 if (MEM_P (operands[0])
925 && ! REG_S_P (operands[1])
926 && operands[1] != const0_rtx
927 && can_create_pseudo_p ())
928 operands[1] = force_reg (SImode, operands[1]);
930 /* If we're generating PIC and have an incoming symbol, validize it to a
931 general operand or something that will match a special pattern.
933 FIXME: Do we *have* to recognize anything that would normally be a
934 valid symbol? Can we exclude global PIC addresses with an added
937 && CONSTANT_ADDRESS_P (operands[1])
938 && !cris_valid_pic_const (operands[1], false))
940 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);
942 gcc_assert (t != cris_no_symbol);
944 if (! REG_S_P (operands[0]))
946 /* We must have a register as destination for what we're about to
947 do, and for the patterns we generate. */
948 CRIS_ASSERT (can_create_pseudo_p ());
949 operands[1] = force_reg (SImode, operands[1]);
953 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
954 destination register for the symbol. It might not be
955 worth it. Measure. */
956 crtl->uses_pic_offset_table = 1;
957 if (t == cris_rel_symbol)
959 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
961 "move.d (const (plus (unspec [sym]
962 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
964 "move.d (const (plus (unspec [sym]
965 CRIS_UNSPEC_PCREL) offs)),rN". */
966 rtx tem, rm, rn = operands[0];
967 rtx sym = GET_CODE (operands[1]) != CONST
968 ? operands[1] : get_related_value (operands[1]);
969 HOST_WIDE_INT offs = get_integer_term (operands[1]);
971 gcc_assert (can_create_pseudo_p ());
975 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
978 tem = plus_constant (Pmode, tem, offs);
980 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
984 /* We still uses GOT-relative addressing for
986 crtl->uses_pic_offset_table = 1;
987 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
990 tem = plus_constant (Pmode, tem, offs);
991 rm = gen_reg_rtx (Pmode);
992 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
993 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
994 rn, 0, OPTAB_LIB_WIDEN) != rn)
995 internal_error ("expand_binop failed in movsi gotrel");
999 else if (t == cris_got_symbol)
1001 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1002 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1003 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1004 the memory access marked as read-only. */
1005 rtx tem, mem, rm, ro, rn = operands[0];
1006 gcc_assert (can_create_pseudo_p ());
1007 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
1008 CRIS_UNSPEC_GOTREAD);
1009 rm = gen_reg_rtx (Pmode);
1010 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1011 ro = gen_reg_rtx (Pmode);
1012 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1013 ro, 0, OPTAB_LIB_WIDEN) != ro)
1014 internal_error ("expand_binop failed in movsi got");
1015 mem = gen_rtx_MEM (Pmode, ro);
1017 /* This MEM doesn't alias anything. Whether it
1018 aliases other same symbols is unimportant. */
1019 set_mem_alias_set (mem, new_alias_set ());
1020 MEM_NOTRAP_P (mem) = 1;
1022 /* We can set the GOT memory read of a non-called symbol
1023 to readonly, but not that of a call symbol, as those
1024 are subject to lazy evaluation and usually have the value
1025 changed from the first call to the second (but
1026 constant thereafter). */
1027 MEM_READONLY_P (mem) = 1;
1028 emit_move_insn (rn, mem);
1033 /* We get here when we have to change something that would
1034 be recognizable if it wasn't PIC. A ``sym'' is ok for
1035 PIC symbols both with and without a GOT entry. And ``sym
1036 + offset'' is ok for local symbols, so the only thing it
1037 could be, is a global symbol with an offset. Check and
1039 rtx reg = gen_reg_rtx (Pmode);
1040 rtx sym = get_related_value (operands[1]);
1041 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1043 gcc_assert (can_create_pseudo_p ()
1044 && t == cris_got_symbol_needing_fixup
1045 && sym != NULL_RTX && offs != 0);
1047 emit_move_insn (reg, sym);
1048 if (expand_binop (SImode, add_optab, reg,
1049 GEN_INT (offs), operands[0], 0,
1050 OPTAB_LIB_WIDEN) != operands[0])
1051 internal_error ("expand_binop failed in movsi got+offs");
1058 (define_insn "*movsi_got_load"
1059 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
1063 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1064 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1066 [(set_attr "cc" "clobber")])
1068 (define_insn "*movsi_internal"
1070 (match_operand:SI 0 "nonimmediate_operand"
1071 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1072 (match_operand:SI 1 "cris_general_operand_or_pic_source"
1073 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1074 ;; Note that we prefer not to use the S alternative (if for some reason
1075 ;; it competes with others) above, but g matches S.
1078 /* Better to have c-switch here; it is worth it to optimize the size of
1079 move insns. The alternative would be to try to find more constraint
1080 letters. FIXME: Check again. It seems this could shrink a bit. */
1081 switch (which_alternative)
1087 && (GET_CODE (operands[1]) == SYMBOL_REF
1088 || GET_CODE (operands[1]) == LABEL_REF
1089 || GET_CODE (operands[1]) == CONST))
1091 /* FIXME: Express this through (set_attr cc none) instead,
1092 since we can't express the ``none'' at this point. FIXME:
1093 Use lapc for everything except const_int and when next cc0
1094 user would want the flag setting. */
1096 return "lapc %1,%0";
1099 && GET_CODE (operands[1]) == CONST
1100 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
1101 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD)
1102 return "movu.w %1,%0";
1109 return "move.d %1,%0";
1115 return "move %d1,%0";
1120 return "clear.d %0";
1122 /* Constants -32..31 except 0. */
1124 return "moveq %1,%0";
1126 /* We can win a little on constants -32768..-33, 32..65535. */
1128 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1130 if (INTVAL (operands[1]) < 256)
1131 return "movu.b %1,%0";
1132 return "movu.w %1,%0";
1134 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1136 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1137 return "movs.b %1,%0";
1138 return "movs.w %1,%0";
1140 return "move.d %1,%0";
1144 rtx tem = operands[1];
1145 gcc_assert (GET_CODE (tem) == CONST);
1146 tem = XEXP (tem, 0);
1147 if (GET_CODE (tem) == PLUS
1148 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1149 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1150 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL)
1151 && CONST_INT_P (XEXP (tem, 1)))
1152 tem = XEXP (tem, 0);
1153 gcc_assert (GET_CODE (tem) == UNSPEC);
1154 switch (XINT (tem, 1))
1156 case CRIS_UNSPEC_GOTREAD:
1157 case CRIS_UNSPEC_PLTGOTREAD:
1158 /* Using sign-extend mostly to be consistent with the
1159 indexed addressing mode. */
1161 return "movs.w %1,%0";
1162 return "move.d %1,%0";
1164 case CRIS_UNSPEC_GOTREL:
1165 case CRIS_UNSPEC_PLT_GOTREL:
1166 gcc_assert (!TARGET_V32);
1167 return "move.d %1,%0";
1169 case CRIS_UNSPEC_PCREL:
1170 case CRIS_UNSPEC_PLT_PCREL:
1171 gcc_assert (TARGET_V32);
1172 return "lapc %1,%0";
1179 return "BOGUS: %1 to %0";
1182 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1183 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1185 ;; Extend operations with side-effect from mem to register, using
1186 ;; MOVS/MOVU. These are from mem to register only.
1192 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1193 ;; HImode by itself? Perhaps use only anonymous modes?
1195 (define_insn "*ext_sideqihi_biap"
1196 [(set (match_operand:HI 0 "register_operand" "=r,r")
1198 5 "cris_extend_operator"
1200 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1201 (match_operand:SI 2 "const_int_operand" "n,n"))
1202 (match_operand:SI 3 "register_operand" "r,r")))]))
1203 (set (match_operand:SI 4 "register_operand" "=*3,r")
1204 (plus:SI (mult:SI (match_dup 1)
1207 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1210 mov%e5.%m5 [%4=%3+%1%T2],%0")
1212 (define_insn "*ext_side<mode>si_biap"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r")
1215 5 "cris_extend_operator"
1217 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1218 (match_operand:SI 2 "const_int_operand" "n,n"))
1219 (match_operand:SI 3 "register_operand" "r,r")))]))
1220 (set (match_operand:SI 4 "register_operand" "=*3,r")
1221 (plus:SI (mult:SI (match_dup 1)
1224 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1227 mov%e5<m> [%4=%3+%1%T2],%0")
1229 ;; Same but [rx=ry+i]
1233 (define_insn "*ext_sideqihi"
1234 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1236 4 "cris_extend_operator"
1238 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1239 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1240 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1241 (plus:SI (match_dup 1)
1243 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1245 if ((which_alternative == 0 || which_alternative == 3)
1246 && (!CONST_INT_P (operands[2])
1247 || INTVAL (operands[2]) > 127
1248 || INTVAL (operands[2]) < -128
1249 || satisfies_constraint_N (operands[2])
1250 || satisfies_constraint_J (operands[2])))
1252 if (which_alternative == 4)
1253 return "mov%e4.%m4 [%3=%2%S1],%0";
1254 return "mov%e4.%m4 [%3=%1%S2],%0";
1257 (define_insn "*ext_side<mode>si"
1258 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1260 4 "cris_extend_operator"
1262 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1263 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1264 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1265 (plus:SI (match_dup 1)
1267 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1269 if ((which_alternative == 0 || which_alternative == 3)
1270 && (!CONST_INT_P (operands[2])
1271 || INTVAL (operands[2]) > 127
1272 || INTVAL (operands[2]) < -128
1273 || satisfies_constraint_N (operands[2])
1274 || satisfies_constraint_J (operands[2])))
1276 if (which_alternative == 4)
1277 return "mov%e4<m> [%3=%2%S1],%0";
1278 return "mov%e4<m> [%3=%1%S2],%0";
1281 ;; FIXME: See movsi.
1283 (define_insn "movhi"
1285 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1286 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1289 switch (which_alternative)
1296 return "move.w %1,%0";
1299 return "move %1,%0";
1303 return "clear.w %0";
1305 return "moveq %1,%0";
1308 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1310 if (INTVAL (operands[1]) > 0)
1311 return "movu.b %1,%0";
1312 return "movs.b %1,%0";
1314 return "move.w %1,%0";
1316 return "movEq %b1,%0";
1318 return "BOGUS: %1 to %0";
1321 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1322 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1324 (define_insn "movstricthi"
1327 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1328 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1339 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1341 (define_expand "reload_in<mode>"
1342 [(set (match_operand:BW 2 "register_operand" "=r")
1343 (match_operand:BW 1 "memory_operand" "m"))
1344 (set (match_operand:BW 0 "register_operand" "=x")
1349 (define_expand "reload_out<mode>"
1350 [(set (match_operand:BW 2 "register_operand" "=&r")
1351 (match_operand:BW 1 "register_operand" "x"))
1352 (set (match_operand:BW 0 "memory_operand" "=m")
1357 (define_insn "movqi"
1358 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1359 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1374 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1375 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1377 (define_insn "movstrictqi"
1378 [(set (strict_low_part
1379 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1380 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1391 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1393 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1394 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1395 ;; all ones); the worthwhile one is "0.0".
1396 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1398 (define_insn "movsf"
1399 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1400 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1417 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1419 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1420 ;; The V32 variants have an ordering matching the expectations of the
1421 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1422 ;; store R0 in the highest memory location.
1424 (define_expand "load_multiple"
1425 [(match_operand:SI 0 "register_operand" "")
1426 (match_operand:SI 1 "memory_operand" "")
1427 (match_operand:SI 2 "const_int_operand" "")]
1432 /* Apparently the predicate isn't checked, so we need to do so
1433 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1434 if (!MEM_P (operands[1]))
1437 indreg = XEXP (operands[1], 0);
1439 if (GET_CODE (indreg) == POST_INC)
1440 indreg = XEXP (indreg, 0);
1442 || GET_CODE (operands[2]) != CONST_INT
1443 || !REG_P (operands[0])
1444 || REGNO (operands[0]) != 0
1445 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1446 || (int) REGNO (indreg) < INTVAL (operands[2]))
1449 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0));
1453 (define_expand "store_multiple"
1454 [(match_operand:SI 0 "memory_operand" "")
1455 (match_operand:SI 1 "register_operand" "")
1456 (match_operand:SI 2 "const_int_operand" "")]
1461 /* See load_multiple. */
1462 if (!MEM_P (operands[0]))
1465 indreg = XEXP (operands[0], 0);
1467 if (GET_CODE (indreg) == POST_INC)
1468 indreg = XEXP (indreg, 0);
1470 || GET_CODE (operands[2]) != CONST_INT
1471 || !REG_P (operands[1])
1472 || REGNO (operands[1]) != 0
1473 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1474 || (int) REGNO (indreg) < INTVAL (operands[2]))
1477 cris_emit_movem_store (operands[0], operands[2], 0, false);
1481 (define_insn "*cris_load_multiple"
1482 [(match_parallel 0 "cris_load_multiple_op"
1483 [(set (match_operand:SI 1 "register_operand" "=r,r")
1484 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1487 [(set_attr "cc" "none")
1488 (set_attr "slottable" "yes,no")
1489 ;; Not true, but setting the length to 0 causes return sequences (ret
1490 ;; movem) to have the cost they had when (return) included the movem
1491 ;; and reduces the performance penalty taken for needing to emit an
1492 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1493 ;; FIXME: temporary change until all insn lengths are correctly
1494 ;; described. FIXME: have better target control over bb-reorder.
1495 (set_attr "length" "0")])
1497 (define_insn "*cris_store_multiple"
1498 [(match_parallel 0 "cris_store_multiple_op"
1499 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1500 (match_operand:SI 1 "register_operand" "r,r"))])]
1503 [(set_attr "cc" "none")
1504 (set_attr "slottable" "yes,no")])
1507 ;; Sign- and zero-extend insns with standard names.
1508 ;; Those for integer source operand are ordered with the widest source
1513 (define_insn "extendsidi2"
1514 [(set (match_operand:DI 0 "register_operand" "=r")
1515 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1517 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1519 (define_insn "extend<mode>di2"
1520 [(set (match_operand:DI 0 "register_operand" "=r")
1521 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1523 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1525 (define_insn "extend<mode>si2"
1526 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1527 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1530 [(set_attr "slottable" "yes,yes,no")])
1532 ;; To do a byte->word extension, extend to dword, except that the top half
1533 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1535 (define_insn "extendqihi2"
1536 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1537 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1540 [(set_attr "slottable" "yes,yes,no")])
1543 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1544 ;; specify them here.
1546 (define_insn "zero_extend<mode>si2"
1547 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1549 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1552 [(set_attr "slottable" "yes,yes,no")])
1554 ;; Same comment as sign-extend QImode to HImode above applies.
1556 (define_insn "zero_extendqihi2"
1557 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1559 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1562 [(set_attr "slottable" "yes,yes,no")])
1564 ;; All kinds of arithmetic and logical instructions.
1566 ;; First, anonymous patterns to match addressing modes with
1569 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1573 (define_insn "*op_side<mode>_biap"
1574 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1576 6 "cris_orthogonal_operator"
1577 [(match_operand:BWD 1 "register_operand" "0,0")
1579 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1580 (match_operand:SI 3 "const_int_operand" "n,n"))
1581 (match_operand:SI 4 "register_operand" "r,r")))]))
1582 (set (match_operand:SI 5 "register_operand" "=*4,r")
1583 (plus:SI (mult:SI (match_dup 2)
1586 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1589 %x6<m> [%5=%4+%2%T3],%0")
1591 ;; [rx=ry+i] ([%4=%2+%3])
1593 (define_insn "*op_side<mode>"
1594 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1596 5 "cris_orthogonal_operator"
1597 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1599 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1600 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1601 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1602 (plus:SI (match_dup 2)
1604 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1606 if ((which_alternative == 0 || which_alternative == 3)
1607 && (!CONST_INT_P (operands[3])
1608 || INTVAL (operands[3]) > 127
1609 || INTVAL (operands[3]) < -128
1610 || satisfies_constraint_N (operands[3])
1611 || satisfies_constraint_J (operands[3])))
1613 if (which_alternative == 4)
1614 return "%x5.%s0 [%4=%3%S2],%0";
1615 return "%x5<m> [%4=%2%S3],%0";
1618 ;; To match all cases for commutative operations we may have to have the
1619 ;; following pattern for add, or & and. I do not know really, but it does
1620 ;; not break anything.
1622 ;; FIXME: This really ought to be checked.
1624 ;; op.S [rx=ry+I],rz;
1628 (define_insn "*op_swap_side<mode>_biap"
1629 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1631 6 "cris_commutative_orth_op"
1633 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1634 (match_operand:SI 3 "const_int_operand" "n,n"))
1635 (match_operand:SI 4 "register_operand" "r,r")))
1636 (match_operand:BWD 1 "register_operand" "0,0")]))
1637 (set (match_operand:SI 5 "register_operand" "=*4,r")
1638 (plus:SI (mult:SI (match_dup 2)
1641 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1644 %x6<m> [%5=%4+%2%T3],%0")
1646 ;; [rx=ry+i] ([%4=%2+%3])
1647 ;; FIXME: These could have anonymous mode for operand 0.
1651 (define_insn "*op_swap_side<mode>"
1652 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1654 5 "cris_commutative_orth_op"
1656 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1657 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1658 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1659 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1660 (plus:SI (match_dup 2)
1662 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1664 if ((which_alternative == 0 || which_alternative == 3)
1665 && (!CONST_INT_P (operands[3])
1666 || INTVAL (operands[3]) > 127
1667 || INTVAL (operands[3]) < -128
1668 || satisfies_constraint_N (operands[3])
1669 || satisfies_constraint_J (operands[3])))
1671 if (which_alternative == 4)
1672 return "%x5<m> [%4=%3%S2],%0";
1673 return "%x5<m> [%4=%2%S3],%0";
1676 ;; Add operations, standard names.
1678 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1679 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1681 (define_expand "adddi3"
1682 [(set (match_operand:DI 0 "register_operand")
1683 (plus:DI (match_operand:DI 1 "register_operand")
1684 (match_operand:DI 2 "general_operand")))]
1687 if (MEM_P (operands[2]) && TARGET_V32)
1688 operands[2] = force_reg (DImode, operands[2]);
1691 (define_insn "*adddi3_non_v32"
1692 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1693 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1694 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1697 addq %2,%M0\;ax\;addq 0,%H0
1698 subq %n2,%M0\;ax\;subq 0,%H0
1699 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1700 add.d %M2,%M0\;ax\;add.d %H2,%H0
1701 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1703 ; It seems no use allowing a memory operand for this one, because we'd
1704 ; need a scratch register for incrementing the address.
1705 (define_insn "*adddi3_v32"
1706 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1707 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0")
1708 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))]
1711 addq %2,%M0\;addc 0,%H0
1712 subq %n2,%M0\;ax\;subq 0,%H0
1713 add%e2.%z2 %2,%M0\;addc %H2,%H0
1714 add.d %M2,%M0\;addc %H2,%H0
1715 add.d %M2,%M0\;addc %H2,%H0")
1717 (define_expand "add<mode>3"
1718 [(set (match_operand:BWD 0 "register_operand")
1720 (match_operand:BWD 1 "register_operand")
1721 (match_operand:BWD 2 "general_operand")))]
1725 (define_insn "*addsi3_non_v32"
1726 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1728 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1729 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1731 ;; The last constraint is due to that after reload, the '%' is not
1732 ;; honored, and canonicalization doesn't care about keeping the same
1733 ;; register as in destination. This will happen after insn splitting.
1734 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1738 switch (which_alternative)
1742 return "add.d %2,%0";
1744 return "addq %2,%0";
1746 return "subq %n2,%0";
1748 /* 'Known value', but not in -63..63.
1749 Check if addu/subu may be used. */
1750 if (INTVAL (operands[2]) > 0)
1752 if (INTVAL (operands[2]) < 256)
1753 return "addu.b %2,%0";
1754 if (INTVAL (operands[2]) < 65536)
1755 return "addu.w %2,%0";
1759 if (INTVAL (operands[2]) >= -255)
1760 return "subu.b %n2,%0";
1761 if (INTVAL (operands[2]) >= -65535)
1762 return "subu.w %n2,%0";
1764 return "add.d %2,%0";
1767 rtx tem = operands[2];
1768 gcc_assert (GET_CODE (tem) == CONST);
1769 tem = XEXP (tem, 0);
1770 if (GET_CODE (tem) == PLUS
1771 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1772 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1773 pc-relative operand in an add insn. */
1774 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1775 && CONST_INT_P (XEXP (tem, 1)))
1776 tem = XEXP (tem, 0);
1777 gcc_assert (GET_CODE (tem) == UNSPEC);
1778 switch (XINT (tem, 1))
1780 case CRIS_UNSPEC_GOTREAD:
1781 case CRIS_UNSPEC_PLTGOTREAD:
1782 /* Using sign-extend mostly to be consistent with the
1783 indexed addressing mode. */
1785 return "adds.w %2,%0";
1786 return "add.d %2,%0";
1788 case CRIS_UNSPEC_PLT_GOTREL:
1789 case CRIS_UNSPEC_GOTREL:
1790 return "add.d %2,%0";
1796 return "add%u2 %2,%0";
1798 return "add.d %2,%1,%0";
1800 return "add.d %1,%0";
1802 return "BOGUS addsi %2+%1 to %0";
1805 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1807 ; FIXME: Check what's best: having the three-operand ACR alternative
1808 ; before or after the corresponding-operand2 alternative. Check for
1809 ; *all* insns. FIXME: constant constraint letter for -128..127.
1810 (define_insn "*addsi3_v32"
1811 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1813 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r")
1814 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1830 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1831 (set_attr "cc" "*,none,*,none,*,*,none,*,none,*,*,*,none")])
1833 (define_insn "*addhi3_non_v32"
1834 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1835 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1836 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1845 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1846 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1848 (define_insn "*addhi3_v32"
1849 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1851 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r")
1852 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1864 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1865 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1867 (define_insn "*addqi3_non_v32"
1868 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1869 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1870 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1880 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1881 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1883 (define_insn "*addqi3_v32"
1884 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1886 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r")
1887 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1900 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1901 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1905 ;; Note that because of insn canonicalization these will *seldom* but
1906 ;; rarely be used with a known constant as an operand.
1908 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1909 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1911 (define_expand "subdi3"
1912 [(set (match_operand:DI 0 "register_operand")
1913 (minus:DI (match_operand:DI 1 "register_operand")
1914 (match_operand:DI 2 "general_operand")))]
1917 if (TARGET_V32 && MEM_P (operands[2]))
1918 operands[2] = force_reg (DImode, operands[2]);
1921 (define_insn "*subdi3_non_v32"
1922 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1923 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1924 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1927 subq %2,%M0\;ax\;subq 0,%H0
1928 addq %n2,%M0\;ax\;addq 0,%H0
1929 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1930 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1931 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1933 (define_insn "*subdi3_v32"
1934 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r")
1935 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0")
1936 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))]
1939 subq %2,%M0\;ax\;subq 0,%H0
1940 addq %n2,%M0\;ax\;addq 0,%H0
1941 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1942 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1944 (define_expand "sub<mode>3"
1945 [(set (match_operand:BWD 0 "register_operand")
1947 (match_operand:BWD 1 "register_operand")
1948 (match_operand:BWD 2 "general_operand")))]
1952 (define_insn "*subsi3_non_v32"
1953 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1955 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1956 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1959 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1960 ;; But then again, %2 should not be negative.
1971 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1973 (define_insn "*subsi3_v32"
1974 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1976 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0")
1977 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))]
1987 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
1989 (define_insn "*sub<mode>3_nonv32"
1990 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
1991 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
1992 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
2001 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2002 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2004 (define_insn "*sub<mode>3_v32"
2005 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
2006 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0")
2007 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))]
2015 [(set_attr "slottable" "yes,yes,yes,yes,no")
2016 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2018 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2019 ;; Although these perform sign/zero-extension to SImode, they are
2020 ;; equally applicable for the HImode case.
2021 ;; FIXME: Check; GCC should handle the widening.
2022 ;; Note that these must be located after the normal add/sub patterns,
2023 ;; so not to get constants into any less specific operands.
2025 ;; Extend with add/sub and side-effect.
2027 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2029 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2032 ;; FIXME: GCC should widen.
2034 (define_insn "*extopqihi_side_biap"
2035 [(set (match_operand:HI 0 "register_operand" "=r,r")
2037 6 "cris_additive_operand_extend_operator"
2038 [(match_operand:HI 1 "register_operand" "0,0")
2040 7 "cris_extend_operator"
2042 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2043 (match_operand:SI 3 "const_int_operand" "n,n"))
2044 (match_operand:SI 4 "register_operand" "r,r")))])]))
2045 (set (match_operand:SI 5 "register_operand" "=*4,r")
2046 (plus:SI (mult:SI (match_dup 2)
2049 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2052 %x6%e7.%m7 [%5=%4+%2%T3],%0")
2054 (define_insn "*extop<mode>si_side_biap"
2055 [(set (match_operand:SI 0 "register_operand" "=r,r")
2057 6 "cris_operand_extend_operator"
2058 [(match_operand:SI 1 "register_operand" "0,0")
2060 7 "cris_extend_operator"
2062 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2063 (match_operand:SI 3 "const_int_operand" "n,n"))
2064 (match_operand:SI 4 "register_operand" "r,r")))])]))
2065 (set (match_operand:SI 5 "register_operand" "=*4,r")
2066 (plus:SI (mult:SI (match_dup 2)
2069 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2070 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2073 %x6%e7<m> [%5=%4+%2%T3],%0")
2080 (define_insn "*extopqihi_side"
2081 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2083 5 "cris_additive_operand_extend_operator"
2084 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
2086 6 "cris_extend_operator"
2088 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2089 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2091 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2092 (plus:SI (match_dup 2)
2094 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2096 if ((which_alternative == 0 || which_alternative == 3)
2097 && (!CONST_INT_P (operands[3])
2098 || INTVAL (operands[3]) > 127
2099 || INTVAL (operands[3]) < -128
2100 || satisfies_constraint_N (operands[3])
2101 || satisfies_constraint_J (operands[3])))
2103 if (which_alternative == 4)
2104 return "%x5%E6.%m6 [%4=%3%S2],%0";
2105 return "%x5%E6.%m6 [%4=%2%S3],%0";
2108 (define_insn "*extop<mode>si_side"
2109 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2111 5 "cris_operand_extend_operator"
2112 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
2114 6 "cris_extend_operator"
2116 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2117 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2119 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2120 (plus:SI (match_dup 2)
2122 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2123 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2125 if ((which_alternative == 0 || which_alternative == 3)
2126 && (!CONST_INT_P (operands[3])
2127 || INTVAL (operands[3]) > 127
2128 || INTVAL (operands[3]) < -128
2129 || satisfies_constraint_N (operands[3])
2130 || satisfies_constraint_J (operands[3])))
2132 if (which_alternative == 4)
2133 return "%x5%E6<m> [%4=%3%S2],%0";
2134 return "%x5%E6<m> [%4=%2%S3],%0";
2138 ;; As with op.S we may have to add special pattern to match commuted
2139 ;; operands to adds/addu and bound
2141 ;; adds/addu/bound [rx=ry+rz.S]
2144 ;; FIXME: GCC should widen.
2146 (define_insn "*extopqihi_swap_side_biap"
2147 [(set (match_operand:HI 0 "register_operand" "=r,r")
2150 6 "cris_extend_operator"
2152 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2153 (match_operand:SI 3 "const_int_operand" "n,n"))
2154 (match_operand:SI 4 "register_operand" "r,r")))])
2155 (match_operand:HI 1 "register_operand" "0,0")))
2156 (set (match_operand:SI 5 "register_operand" "=*4,r")
2157 (plus:SI (mult:SI (match_dup 2)
2160 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2163 add%e6.b [%5=%4+%2%T3],%0")
2165 (define_insn "*extop<mode>si_swap_side_biap"
2166 [(set (match_operand:SI 0 "register_operand" "=r,r")
2168 7 "cris_plus_or_bound_operator"
2170 6 "cris_extend_operator"
2172 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2173 (match_operand:SI 3 "const_int_operand" "n,n"))
2174 (match_operand:SI 4 "register_operand" "r,r")))])
2175 (match_operand:SI 1 "register_operand" "0,0")]))
2176 (set (match_operand:SI 5 "register_operand" "=*4,r")
2177 (plus:SI (mult:SI (match_dup 2)
2180 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2181 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2184 %x7%E6<m> [%5=%4+%2%T3],%0")
2187 ;; FIXME: GCC should widen.
2191 (define_insn "*extopqihi_swap_side"
2192 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2195 5 "cris_extend_operator"
2197 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2198 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2199 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
2200 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2201 (plus:SI (match_dup 2)
2203 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2205 if ((which_alternative == 0 || which_alternative == 3)
2206 && (!CONST_INT_P (operands[3])
2207 || INTVAL (operands[3]) > 127
2208 || INTVAL (operands[3]) < -128
2209 || satisfies_constraint_N (operands[3])
2210 || satisfies_constraint_J (operands[3])))
2212 if (which_alternative == 4)
2213 return "add%e5.b [%4=%3%S2],%0";
2214 return "add%e5.b [%4=%2%S3],%0";
2217 (define_insn "*extop<mode>si_swap_side"
2218 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2220 6 "cris_plus_or_bound_operator"
2222 5 "cris_extend_operator"
2224 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2225 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2226 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
2227 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2228 (plus:SI (match_dup 2)
2230 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2231 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2233 if ((which_alternative == 0 || which_alternative == 3)
2234 && (!CONST_INT_P (operands[3])
2235 || INTVAL (operands[3]) > 127
2236 || INTVAL (operands[3]) < -128
2237 || satisfies_constraint_N (operands[3])
2238 || satisfies_constraint_J (operands[3])))
2240 if (which_alternative == 4)
2241 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
2242 return "%x6%E5<m> [%4=%2%S3],%0";
2245 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2248 ;; FIXME: GCC should widen.
2250 (define_insn "*extopqihi_non_v32"
2251 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2253 3 "cris_additive_operand_extend_operator"
2254 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2256 4 "cris_extend_operator"
2257 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2258 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2259 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2264 %x3%E4.%m4 %2,%1,%0"
2265 [(set_attr "slottable" "yes,yes,no,no")
2266 (set_attr "cc" "clobber")])
2268 (define_insn "*extopqihi_v32"
2269 [(set (match_operand:HI 0 "register_operand" "=r,r")
2271 3 "cris_additive_operand_extend_operator"
2272 [(match_operand:HI 1 "register_operand" "0,0")
2274 4 "cris_extend_operator"
2275 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))]
2278 [(set_attr "slottable" "yes")
2279 (set_attr "cc" "clobber")])
2283 (define_insn "*extop<mode>si_non_v32"
2284 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2286 3 "cris_operand_extend_operator"
2287 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2289 4 "cris_extend_operator"
2290 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2292 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2293 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2294 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2300 [(set_attr "slottable" "yes,yes,no,no")])
2302 (define_insn "*extop<mode>si_v32"
2303 [(set (match_operand:SI 0 "register_operand" "=r,r")
2305 3 "cris_additive_operand_extend_operator"
2306 [(match_operand:SI 1 "register_operand" "0,0")
2308 4 "cris_extend_operator"
2309 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))]
2312 [(set_attr "slottable" "yes")])
2314 ;; As with the side-effect patterns, may have to have swapped operands for add.
2315 ;; For commutative operands, these are the canonical forms.
2319 (define_insn "*addxqihi_swap_non_v32"
2320 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2323 3 "cris_extend_operator"
2324 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2325 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2326 "!TARGET_V32 && operands[1] != frame_pointer_rtx"
2332 [(set_attr "slottable" "yes,yes,no,no")
2333 (set_attr "cc" "clobber")])
2335 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2336 ;; only care to match the canonical form; there should be no other.
2338 (define_insn "*addsbw_v32"
2339 [(set (match_operand:HI 0 "register_operand" "=r,r,!a")
2342 (match_operand:QI 2 "nonimmediate_operand" "r,m,m"))
2343 (match_operand:HI 1 "register_operand" "0,0,r")))]
2349 [(set_attr "slottable" "yes")
2350 (set_attr "cc" "clobber,clobber,none")])
2352 (define_insn "*addubw_v32"
2353 [(set (match_operand:HI 0 "register_operand" "=r,r")
2356 (match_operand:QI 2 "nonimmediate_operand" "r,m"))
2357 (match_operand:HI 1 "register_operand" "0,0")))]
2360 [(set_attr "slottable" "yes")
2361 (set_attr "cc" "clobber")])
2363 (define_insn "*extop<mode>si_swap_non_v32"
2364 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2366 4 "cris_plus_or_bound_operator"
2368 3 "cris_extend_operator"
2369 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
2370 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2372 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2373 && operands[1] != frame_pointer_rtx"
2379 [(set_attr "slottable" "yes,yes,no,no")])
2381 (define_insn "*adds<mode>_v32"
2382 [(set (match_operand:SI 0 "register_operand" "=r,r,!a")
2385 (match_operand:BW 2 "nonimmediate_operand" "r,m,m"))
2386 (match_operand:SI 1 "register_operand" "0,0,r")))]
2392 [(set_attr "slottable" "yes")
2393 (set_attr "cc" "*,*,none")])
2395 (define_insn "*addu<mode>_v32"
2396 [(set (match_operand:SI 0 "register_operand" "=r,r")
2399 (match_operand:BW 2 "nonimmediate_operand" "r,m"))
2400 (match_operand:SI 1 "register_operand" "0,0")))]
2401 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2403 [(set_attr "slottable" "yes")])
2405 (define_insn "*bound<mode>_v32"
2406 [(set (match_operand:SI 0 "register_operand" "=r")
2409 (match_operand:BW 2 "register_operand" "r"))
2410 (match_operand:SI 1 "register_operand" "0")))]
2411 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2413 [(set_attr "slottable" "yes")])
2415 ;; This is the special case when we use what corresponds to the
2416 ;; instruction above in "casesi". Do *not* change it to use the generic
2417 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2418 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2419 ;; or replacing this pattern with something simpler, other variant
2420 ;; patterns were recognized or combined, including some prefix variants
2421 ;; where the value in pc is not that of the next instruction (which means
2422 ;; this instruction actually *is* special and *should* be marked as such).
2423 ;; When switching from the "generic pattern match" approach to this simpler
2424 ;; approach, there were insignificant differences in gcc, ipps and
2425 ;; product code, somehow due to scratching reload behind the ear or
2426 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2427 ;; product code became .001% smaller but "looked better". The testcase
2428 ;; "ipps" was just different at register allocation).
2430 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2431 ;; pattern with the default-label as the else, with the "if" being
2432 ;; index-is-less-than the max number of cases plus one. The default-label
2433 ;; is attached to the end of the case-table at time of output.
2435 (define_insn "*casesi_adds_w"
2438 (ltu (match_operand:SI 0 "register_operand" "r")
2439 (match_operand:SI 1 "const_int_operand" "n"))
2440 (plus:SI (sign_extend:SI
2442 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2445 (label_ref (match_operand 2 "" ""))))
2446 (use (label_ref (match_operand 3 "" "")))]
2447 "!TARGET_V32 && operands[0] != frame_pointer_rtx"
2448 "adds.w [$pc+%0.w],$pc"
2449 [(set_attr "cc" "clobber")])
2451 ;; For V32, we just have a jump, but we need to mark the table as used,
2452 ;; and the jump insn must have the if_then_else form expected by core
2453 ;; GCC. Since we don't want to prolong the lifetime of the original
2454 ;; index value, we compare against "unspec 0". It's a pity we have to
2455 ;; jump through to get the default label in place and to keep the jump
2456 ;; table around. FIXME: Look into it some time.
2458 (define_insn "*casesi_jump_v32"
2461 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI)
2462 (match_operand:SI 0 "const_int_operand" "n"))
2463 (match_operand:SI 1 "register_operand" "r")
2464 (label_ref (match_operand 2 "" ""))))
2465 (use (label_ref (match_operand 3 "" "")))]
2468 [(set_attr "cc" "clobber")
2469 (set_attr "slottable" "has_slot")])
2471 ;; Multiply instructions.
2473 ;; Sometimes powers of 2 (which are normally canonicalized to a
2474 ;; left-shift) appear here, as a result of address reloading.
2475 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2477 ;; FIXME: This may be unnecessary now.
2478 ;; Explicitly named for convenience of having a gen_... function.
2480 (define_insn "addi_mul"
2481 [(set (match_operand:SI 0 "register_operand" "=r")
2483 (match_operand:SI 1 "register_operand" "%0")
2484 (match_operand:SI 2 "const_int_operand" "n")))]
2485 "operands[0] != frame_pointer_rtx
2486 && operands[1] != frame_pointer_rtx
2487 && CONST_INT_P (operands[2])
2488 && (INTVAL (operands[2]) == 2
2489 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2490 || INTVAL (operands[2]) == 5)"
2492 if (INTVAL (operands[2]) == 2)
2494 else if (INTVAL (operands[2]) == 4)
2496 else if (INTVAL (operands[2]) == 3)
2497 return "addi %0.w,%0";
2498 else if (INTVAL (operands[2]) == 5)
2499 return "addi %0.d,%0";
2500 return "BAD: adr_mulsi: %0=%1*%2";
2502 [(set_attr "slottable" "yes")
2503 ;; No flags are changed if this insn is "addi", but it does not seem
2504 ;; worth the trouble to distinguish that to the lslq cases.
2505 (set_attr "cc" "clobber")])
2507 ;; The addi insn as it is normally used.
2509 ;; Make the ACR alternative taste bad enough to not choose it as a
2510 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2511 ;; FIXME: Revisit for new register allocator.
2513 (define_insn "*addi"
2514 [(set (match_operand:SI 0 "register_operand" "=r,!a")
2516 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2517 (match_operand:SI 3 "const_int_operand" "n,n"))
2518 (match_operand:SI 1 "register_operand" "0,r")))]
2519 "operands[0] != frame_pointer_rtx
2520 && operands[1] != frame_pointer_rtx
2521 && CONST_INT_P (operands[3])
2522 && (INTVAL (operands[3]) == 1
2523 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2527 [(set_attr "slottable" "yes")
2528 (set_attr "cc" "none")])
2530 ;; The mstep instruction. Probably not useful by itself; it's to
2531 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2534 (define_insn "mstep_shift"
2535 [(set (match_operand:SI 0 "register_operand" "=r")
2537 (lt:SI (cc0) (const_int 0))
2538 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2540 (match_operand:SI 2 "register_operand" "r"))
2541 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2545 [(set_attr "slottable" "yes")])
2547 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2548 ;; to canonicalize the multiplications.
2550 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2552 (define_insn "mstep_mul"
2553 [(set (match_operand:SI 0 "register_operand" "=r")
2555 (lt:SI (cc0) (const_int 0))
2556 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2558 (match_operand:SI 2 "register_operand" "r"))
2559 (mult:SI (match_operand:SI 3 "register_operand" "0")
2562 && operands[0] != frame_pointer_rtx
2563 && operands[1] != frame_pointer_rtx
2564 && operands[2] != frame_pointer_rtx
2565 && operands[3] != frame_pointer_rtx"
2567 [(set_attr "slottable" "yes")])
2569 (define_insn "<u>mul<s><mode>3"
2570 [(set (match_operand:WD 0 "register_operand" "=r")
2572 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2573 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2574 (clobber (match_scratch:SI 3 "=h"))]
2575 "TARGET_HAS_MUL_INSNS"
2576 "%!mul<su><mm> %2,%0"
2577 [(set (attr "slottable")
2578 (if_then_else (match_test "TARGET_MUL_BUG")
2580 (const_string "yes")))
2581 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2582 ;; For muls.b, this really extends to SImode, so cc should be
2583 ;; considered clobbered.
2584 ;; For muls.w, it's just N unusable here, but let's be safe.
2585 (set_attr "cc" "clobber")])
2587 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2588 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2589 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2590 ;; Inspection of optab code shows that there must be only one widening
2591 ;; multiplication per mode widened to.
2593 (define_insn "mulsi3"
2594 [(set (match_operand:SI 0 "register_operand" "=r")
2595 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2596 (match_operand:SI 2 "register_operand" "r")))
2597 (clobber (match_scratch:SI 3 "=h"))]
2598 "TARGET_HAS_MUL_INSNS"
2600 [(set (attr "slottable")
2601 (if_then_else (match_test "TARGET_MUL_BUG")
2603 (const_string "yes")))
2604 ;; Just N unusable here, but let's be safe.
2605 (set_attr "cc" "clobber")])
2607 ;; A few multiply variations.
2609 ;; When needed, we can get the high 32 bits from the overflow
2610 ;; register. We don't care to split and optimize these.
2612 ;; Note that cc0 is still valid after the move-from-overflow-register
2613 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2615 (define_insn "<u>mulsidi3"
2616 [(set (match_operand:DI 0 "register_operand" "=r")
2618 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2619 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2620 (clobber (match_scratch:SI 3 "=h"))]
2621 "TARGET_HAS_MUL_INSNS"
2622 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2624 ;; These two patterns may be expressible by other means, perhaps by making
2625 ;; [u]?mulsidi3 a define_expand.
2627 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2628 ;; cause a move into the clobbered register *before* the insn, then
2629 ;; after the insn, mof is moved too, rather than the clobber assigned
2630 ;; the last mof target. This became apparent when making MOF and SRP
2631 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2632 ;; Because these patterns are used in division by constants, that damage
2633 ;; is visible (ipps regression tests). Therefore the last two
2634 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2635 ;; punished by force of one "?". Check code from "int d (int a) {return
2636 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2638 (define_insn "<su>mulsi3_highpart"
2639 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
2643 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2644 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2646 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2647 "TARGET_HAS_MUL_INSNS"
2651 %!mul<su>.d %2,%1\;move $mof,%0
2652 %!mul<su>.d %1,%2\;move $mof,%0"
2653 [(set_attr "slottable" "yes,yes,no,no")
2654 (set_attr "cc" "clobber")])
2656 ;; Divide and modulus instructions. CRIS only has a step instruction.
2658 (define_insn "dstep_shift"
2659 [(set (match_operand:SI 0 "register_operand" "=r")
2661 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2663 (match_operand:SI 2 "register_operand" "r"))
2664 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2666 (match_operand:SI 4 "register_operand" "2"))
2667 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2671 [(set_attr "slottable" "yes")
2672 (set_attr "cc" "noov32")])
2674 ;; Here's a variant with mult instead of ashift.
2676 ;; FIXME: This should be investigated. Which one matches through combination?
2678 (define_insn "dstep_mul"
2679 [(set (match_operand:SI 0 "register_operand" "=r")
2681 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2683 (match_operand:SI 2 "register_operand" "r"))
2684 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2686 (match_operand:SI 4 "register_operand" "2"))
2687 (mult:SI (match_operand:SI 5 "register_operand" "0")
2689 "operands[0] != frame_pointer_rtx
2690 && operands[1] != frame_pointer_rtx
2691 && operands[2] != frame_pointer_rtx
2692 && operands[3] != frame_pointer_rtx"
2694 [(set_attr "slottable" "yes")
2695 (set_attr "cc" "noov32")])
2697 ;; Logical operators.
2701 ;; There is no use in defining "anddi3", because gcc can expand this by
2702 ;; itself, and make reasonable code without interference.
2704 ;; If the first operand is memory or a register and is the same as the
2705 ;; second operand, and the third operand is -256 or -65536, we can use
2706 ;; CLEAR instead. Or, if the first operand is a register, and the third
2707 ;; operand is 255 or 65535, we can zero_extend.
2708 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2709 ;; to be common enough to be worthwhile.
2710 ;; FIXME: This should be made obsolete.
2712 (define_expand "andsi3"
2713 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2714 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2715 (match_operand:SI 2 "general_operand" "")))]
2718 if (! (CONST_INT_P (operands[2])
2719 && (((INTVAL (operands[2]) == -256
2720 || INTVAL (operands[2]) == -65536)
2721 && rtx_equal_p (operands[1], operands[0]))
2722 || ((INTVAL (operands[2]) == 255
2723 || INTVAL (operands[2]) == 65535)
2724 && REG_P (operands[0])))))
2726 /* Make intermediate steps if operand0 is not a register or
2727 operand1 is not a register, and hope that the reload pass will
2728 make something useful out of it. Note that the operands are
2729 *not* canonicalized. For the moment, I chicken out on this,
2730 because all or most ports do not describe 'and' with
2731 canonicalized operands, and I seem to remember magic in reload,
2732 checking that operand1 has constraint '%0', in which case
2733 operand0 and operand1 must have similar predicates.
2734 FIXME: Investigate. */
2735 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2736 rtx reg1 = operands[1];
2740 emit_move_insn (reg0, reg1);
2744 emit_insn (gen_rtx_SET (SImode, reg0,
2745 gen_rtx_AND (SImode, reg1, operands[2])));
2747 /* Make sure we get the right *final* destination. */
2748 if (! REG_P (operands[0]))
2749 emit_move_insn (operands[0], reg0);
2755 ;; Some special cases of andsi3.
2757 (define_insn "*andsi_movu"
2758 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2759 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2760 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2761 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2762 && !side_effects_p (operands[1])"
2764 [(set_attr "slottable" "yes,yes,no")])
2766 (define_insn "*andsi_clear"
2767 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2768 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2769 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2770 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2771 && !side_effects_p (operands[0])"
2779 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2780 (set_attr "cc" "none")])
2782 ;; This is a catch-all pattern, taking care of everything that was not
2783 ;; matched in the insns above.
2785 ;; Sidenote: the tightening from "nonimmediate_operand" to
2786 ;; "register_operand" for operand 1 actually increased the register
2787 ;; pressure (worse code). That will hopefully change with an
2788 ;; improved reload pass.
2790 (define_insn "*expanded_andsi_non_v32"
2791 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2792 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2793 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2801 [(set_attr "slottable" "yes,yes,yes,no,no")])
2803 (define_insn "*expanded_andsi_v32"
2804 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2805 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
2806 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))]
2813 [(set_attr "slottable" "yes,yes,yes,no")
2814 (set_attr "cc" "noov32")])
2816 ;; For both QI and HI we may use the quick patterns. This results in
2817 ;; useless condition codes, but that is used rarely enough for it to
2818 ;; normally be a win (could check ahead for use of cc0, but seems to be
2819 ;; more pain than win).
2821 ;; FIXME: See note for andsi3
2823 (define_expand "andhi3"
2824 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2825 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2826 (match_operand:HI 2 "general_operand" "")))]
2829 if (! (CONST_INT_P (operands[2])
2830 && (((INTVAL (operands[2]) == -256
2831 || INTVAL (operands[2]) == 65280)
2832 && rtx_equal_p (operands[1], operands[0]))
2833 || (INTVAL (operands[2]) == 255
2834 && REG_P (operands[0])))))
2836 /* See comment for andsi3. */
2837 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2838 rtx reg1 = operands[1];
2842 emit_move_insn (reg0, reg1);
2846 emit_insn (gen_rtx_SET (HImode, reg0,
2847 gen_rtx_AND (HImode, reg1, operands[2])));
2849 /* Make sure we get the right destination. */
2850 if (! REG_P (operands[0]))
2851 emit_move_insn (operands[0], reg0);
2857 ;; Some fast andhi3 special cases.
2859 (define_insn "*andhi_movu"
2860 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2861 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2863 "!side_effects_p (operands[1])"
2865 [(set_attr "slottable" "yes,yes,no")])
2867 (define_insn "*andhi_clear"
2868 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2869 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2871 "!side_effects_p (operands[0])"
2873 [(set_attr "slottable" "yes,yes,no")
2874 (set_attr "cc" "none")])
2876 ;; Catch-all andhi3 pattern.
2878 (define_insn "*expanded_andhi_non_v32"
2879 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2880 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2881 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2883 ;; Sidenote: the tightening from "general_operand" to
2884 ;; "register_operand" for operand 1 actually increased the register
2885 ;; pressure (worse code). That will hopefully change with an
2886 ;; improved reload pass.
2897 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2898 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2900 (define_insn "*expanded_andhi_v32"
2901 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
2902 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
2903 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
2912 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2913 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2915 ;; A strict_low_part pattern.
2917 ;; Note the use of (match_dup 0) for the first operand of the operation
2918 ;; here. Reload can't handle an operand pair where one is read-write
2919 ;; and must match a read, like in:
2921 ;; (set (strict_low_part
2922 ;; (subreg:QI (reg/v:SI 0 r0 [orig:36 data ] [36]) 0))
2924 ;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0)
2925 ;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32}
2927 ;; In theory, it could reload this as a movstrictqi of the register
2928 ;; operand at the and:QI to the destination register and change the
2929 ;; and:QI operand to the same as the read-write output operand and the
2930 ;; result would be recognized, but it doesn't recognize that's a valid
2931 ;; reload for a strict_low_part-destination; it just sees a "+" at the
2932 ;; destination constraints. Better than adding complexity to reload is
2933 ;; to follow the lead of m68k (see comment that begins with "These insns
2934 ;; must use MATCH_DUP") since prehistoric times and make it just a
2935 ;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with
2936 ;; input-constraints matching input-output-constraints, e.g. "+r" <- "0".
2938 (define_insn "*andhi_lowpart_non_v32"
2939 [(set (strict_low_part
2940 (match_operand:HI 0 "register_operand" "+r,r,r"))
2941 (and:HI (match_dup 0)
2942 (match_operand:HI 1 "general_operand" "r,Q>,g")))]
2948 [(set_attr "slottable" "yes,yes,no")])
2950 (define_insn "*andhi_lowpart_v32"
2951 [(set (strict_low_part
2952 (match_operand:HI 0 "register_operand" "+r,r,r"))
2953 (and:HI (match_dup 0)
2954 (match_operand:HI 1 "general_operand" "r,Q>,g")))]
2960 [(set_attr "slottable" "yes,yes,no")
2961 (set_attr "cc" "noov32")])
2963 (define_expand "andqi3"
2964 [(set (match_operand:QI 0 "register_operand")
2965 (and:QI (match_operand:QI 1 "register_operand")
2966 (match_operand:QI 2 "general_operand")))]
2970 (define_insn "*andqi3_non_v32"
2971 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2972 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2973 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2982 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2983 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2985 (define_insn "*andqi3_v32"
2986 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
2987 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
2988 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
2996 [(set_attr "slottable" "yes,yes,yes,yes,no")
2997 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
2999 (define_insn "*andqi_lowpart_non_v32"
3000 [(set (strict_low_part
3001 (match_operand:QI 0 "register_operand" "+r,r,r"))
3002 (and:QI (match_dup 0)
3003 (match_operand:QI 1 "general_operand" "r,Q>,g")))]
3009 [(set_attr "slottable" "yes,yes,no")])
3011 (define_insn "*andqi_lowpart_v32"
3012 [(set (strict_low_part
3013 (match_operand:QI 0 "register_operand" "+r,r,r"))
3014 (and:QI (match_dup 0)
3015 (match_operand:QI 1 "general_operand" "r,Q>,g")))]
3021 [(set_attr "slottable" "yes,yes,no")
3022 (set_attr "cc" "noov32")])
3026 ;; Same comment as anddi3 applies here - no need for such a pattern.
3028 ;; It seems there's no need to jump through hoops to get good code such as
3031 (define_expand "ior<mode>3"
3032 [(set (match_operand:BWD 0 "register_operand")
3033 (ior:BWD (match_operand:BWD 1 "register_operand")
3034 (match_operand:BWD 2 "general_operand")))]
3038 (define_insn "*iorsi3_non_v32"
3039 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
3040 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
3041 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
3050 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3051 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3053 (define_insn "*iorsi3_v32"
3054 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
3055 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
3056 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))]
3064 [(set_attr "slottable" "yes,yes,yes,no,no")
3065 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3067 (define_insn "*iorhi3_non_v32"
3068 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
3069 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
3070 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3080 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3081 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3083 (define_insn "*iorhi3_v32"
3084 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
3085 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
3086 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
3095 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3096 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3098 (define_insn "*iorqi3_non_v32"
3099 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
3100 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3101 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3110 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3111 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3113 (define_insn "*iorqi3_v32"
3114 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3115 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3116 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3124 [(set_attr "slottable" "yes,yes,yes,yes,no")
3125 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3129 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3130 ;; FIXME: Do we really need the shorter variants?
3132 (define_insn "xorsi3"
3133 [(set (match_operand:SI 0 "register_operand" "=r")
3134 (xor:SI (match_operand:SI 1 "register_operand" "%0")
3135 (match_operand:SI 2 "register_operand" "r")))]
3138 [(set_attr "slottable" "yes")
3139 (set_attr "cc" "noov32")])
3141 (define_insn "xor<mode>3"
3142 [(set (match_operand:BW 0 "register_operand" "=r")
3143 (xor:BW (match_operand:BW 1 "register_operand" "%0")
3144 (match_operand:BW 2 "register_operand" "r")))]
3147 [(set_attr "slottable" "yes")
3148 (set_attr "cc" "clobber")])
3152 ;; Questionable use, here mostly as a (slightly usable) define_expand
3155 (define_expand "negsf2"
3158 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
3159 (neg:SF (match_operand:SF 1
3160 "register_operand" "0")))
3161 (use (match_dup 2))])]
3164 operands[2] = gen_reg_rtx (SImode);
3165 operands[3] = GEN_INT (1 << 31);
3168 (define_insn "*expanded_negsf2"
3169 [(set (match_operand:SF 0 "register_operand" "=r")
3170 (neg:SF (match_operand:SF 1 "register_operand" "0")))
3171 (use (match_operand:SI 2 "register_operand" "r"))]
3174 [(set_attr "slottable" "yes")])
3176 ;; No "negdi2" although we could make one up that may be faster than
3177 ;; the one in libgcc.
3179 (define_insn "neg<mode>2"
3180 [(set (match_operand:BWD 0 "register_operand" "=r")
3181 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
3184 [(set_attr "slottable" "yes")])
3188 ;; See comment on anddi3 - no need for a DImode pattern.
3189 ;; See also xor comment.
3191 (define_insn "one_cmplsi2"
3192 [(set (match_operand:SI 0 "register_operand" "=r")
3193 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3196 [(set_attr "slottable" "yes")
3197 (set_attr "cc" "noov32")])
3199 (define_insn "one_cmpl<mode>2"
3200 [(set (match_operand:BW 0 "register_operand" "=r")
3201 (not:BW (match_operand:BW 1 "register_operand" "0")))]
3204 [(set_attr "slottable" "yes")
3205 (set_attr "cc" "clobber")])
3207 ;; Arithmetic/Logical shift right (and SI left).
3209 (define_insn "<shlr>si3"
3210 [(set (match_operand:SI 0 "register_operand" "=r")
3211 (shift:SI (match_operand:SI 1 "register_operand" "0")
3212 (match_operand:SI 2 "nonmemory_operand" "Kcr")))]
3215 if (REG_S_P (operands[2]))
3216 return "<slr>.d %2,%0";
3218 return "<slr>q %2,%0";
3220 [(set_attr "slottable" "yes")
3221 (set_attr "cc" "noov32")])
3223 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3224 ;; the destination) when it changes shifts of lower modes into SImode,
3225 ;; it is better to make these expands an anonymous patterns instead of
3226 ;; the more correct define_insns. This occurs when gcc thinks that is
3227 ;; is better to widen to SImode and use immediate shift count.
3229 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3231 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3232 ;; mentioning "shiftrt"), so we need two patterns.
3233 (define_expand "ashr<mode>3"
3235 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3237 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3238 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3239 (set (match_operand:BW 0 "general_operand" "")
3240 (subreg:BW (match_dup 5) 0))]
3245 for (i = 3; i < 6; i++)
3246 operands[i] = gen_reg_rtx (SImode);
3249 (define_expand "lshr<mode>3"
3251 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3253 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3254 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3255 (set (match_operand:BW 0 "general_operand" "")
3256 (subreg:BW (match_dup 5) 0))]
3261 for (i = 3; i < 6; i++)
3262 operands[i] = gen_reg_rtx (SImode);
3265 (define_insn "*expanded_<shlr><mode>"
3266 [(set (match_operand:BW 0 "register_operand" "=r")
3267 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
3268 (match_operand:BW 2 "register_operand" "r")))]
3271 [(set_attr "slottable" "yes")
3272 (set_attr "cc" "noov32")])
3274 (define_insn "*<shlr><mode>_lowpart"
3275 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3276 (shiftrt:BW (match_dup 0)
3277 (match_operand:BW 1 "register_operand" "r")))]
3280 [(set_attr "slottable" "yes")
3281 (set_attr "cc" "noov32")])
3283 ;; Arithmetic/logical shift left.
3285 ;; For narrower modes than SI, we can use lslq although it makes cc
3286 ;; unusable. The win is that we do not have to reload the shift-count
3289 (define_insn "ashl<mode>3"
3290 [(set (match_operand:BW 0 "register_operand" "=r,r")
3291 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
3292 (match_operand:BW 2 "nonmemory_operand" "r,Kc")))]
3296 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
3298 : (CONSTANT_P (operands[2])
3299 ? "lslq %2,%0" : "lsl<m> %2,%0");
3301 [(set_attr "slottable" "yes")
3302 (set_attr "cc" "noov32,clobber")])
3304 ;; A strict_low_part matcher.
3306 (define_insn "*ashl<mode>_lowpart"
3307 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3308 (ashift:BW (match_dup 0)
3309 (match_operand:HI 1 "register_operand" "r")))]
3312 [(set_attr "slottable" "yes")
3313 (set_attr "cc" "noov32")])
3315 ;; Various strange insns that gcc likes.
3317 ;; Fortunately, it is simple to construct an abssf (although it may not
3318 ;; be very much used in practice).
3320 (define_insn "abssf2"
3321 [(set (match_operand:SF 0 "register_operand" "=r")
3322 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3324 "lslq 1,%0\;lsrq 1,%0")
3326 (define_insn "abssi2"
3327 [(set (match_operand:SI 0 "register_operand" "=r")
3328 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3331 [(set_attr "slottable" "yes")
3332 (set_attr "cc" "noov32")])
3334 ;; FIXME: GCC should be able to do these expansions itself.
3336 (define_expand "abs<mode>2"
3338 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
3339 (set (match_dup 3) (abs:SI (match_dup 2)))
3340 (set (match_operand:BW 0 "register_operand" "")
3341 (subreg:BW (match_dup 3) 0))]
3343 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3345 (define_insn "clzsi2"
3346 [(set (match_operand:SI 0 "register_operand" "=r")
3347 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
3350 [(set_attr "slottable" "yes")
3351 (set_attr "cc" "noov32")])
3353 (define_insn "bswapsi2"
3354 [(set (match_operand:SI 0 "register_operand" "=r")
3355 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
3358 [(set_attr "slottable" "yes")
3359 (set_attr "cc" "noov32")])
3361 ;; This instruction swaps all bits in a register.
3362 ;; That means that the most significant bit is put in the place
3363 ;; of the least significant bit, and so on.
3365 (define_insn "cris_swap_bits"
3366 [(set (match_operand:SI 0 "register_operand" "=r")
3367 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
3368 CRIS_UNSPEC_SWAP_BITS))]
3371 [(set_attr "slottable" "yes")
3372 (set_attr "cc" "noov32")])
3374 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3375 ;; Defines a scratch register to avoid clobbering input.
3377 (define_expand "ctzsi2"
3379 (match_operand:SI 1 "register_operand"))
3381 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
3382 (set (match_operand:SI 0 "register_operand")
3383 (clz:SI (match_dup 2)))]
3384 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3385 "operands[2] = gen_reg_rtx (SImode);")
3387 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3388 ;; operation supported by gcc. Used in casesi, but used now and then in
3391 (define_expand "uminsi3"
3392 [(set (match_operand:SI 0 "register_operand" "")
3393 (umin:SI (match_operand:SI 1 "register_operand" "")
3394 (match_operand:SI 2 "general_operand" "")))]
3397 if (MEM_P (operands[2]) && TARGET_V32)
3398 operands[2] = force_reg (SImode, operands[2]);
3401 (define_insn "*uminsi3_non_v32"
3402 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
3403 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
3404 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
3407 if (CONST_INT_P (operands[2]))
3409 /* Constant operands are zero-extended, so only 32-bit operands
3411 if (INTVAL (operands[2]) >= 0)
3413 if (INTVAL (operands[2]) < 256)
3414 return "bound.b %2,%0";
3416 if (INTVAL (operands[2]) < 65536)
3417 return "bound.w %2,%0";
3420 else if (which_alternative == 3)
3421 return "bound.d %2,%1,%0";
3423 return "bound.d %2,%0";
3425 [(set_attr "slottable" "yes,yes,no,no")])
3427 (define_insn "*uminsi3_v32"
3428 [(set (match_operand:SI 0 "register_operand" "=r,r")
3429 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
3430 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
3433 if (GET_CODE (operands[2]) == CONST_INT)
3435 /* Constant operands are zero-extended, so only 32-bit operands
3437 if (INTVAL (operands[2]) >= 0)
3439 if (INTVAL (operands[2]) < 256)
3440 return "bound.b %2,%0";
3442 if (INTVAL (operands[2]) < 65536)
3443 return "bound.w %2,%0";
3447 return "bound.d %2,%0";
3449 [(set_attr "slottable" "yes,no")])
3451 ;; Jump and branch insns.
3455 (label_ref (match_operand 0 "" "")))]
3458 [(set_attr "slottable" "has_slot")])
3460 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3461 ;; here, since the insn is not recognized as an indirect jump by
3462 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3463 ;; change from general_operand to nonimmediate_operand (at least the docs
3464 ;; should be changed), but then again the pattern is called indirect_jump.
3465 (define_expand "indirect_jump"
3466 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
3469 if (TARGET_V32 && MEM_P (operands[0]))
3470 operands[0] = force_reg (SImode, operands[0]);
3473 (define_insn "*indirect_jump_non_v32"
3474 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3478 (define_insn "*indirect_jump_v32"
3479 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3482 [(set_attr "slottable" "has_slot")])
3484 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3485 ;; a single ret or jump [sp+]. No allocated stack space or saved
3486 ;; registers are allowed.
3487 ;; Note that for this pattern, although named, it is ok to check the
3488 ;; context of the insn in the test, not only compiler switches.
3490 (define_expand "return"
3492 "cris_simple_epilogue ()"
3493 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3495 (define_insn "*return_expanded"
3499 return cris_return_address_on_stack_for_return ()
3500 ? "jump [$sp+]" : "ret%#";
3502 [(set (attr "slottable")
3504 (match_test "cris_return_address_on_stack_for_return ()")
3506 (const_string "has_return_slot")))])
3508 (define_expand "prologue"
3510 "TARGET_PROLOGUE_EPILOGUE"
3511 "cris_expand_prologue (); DONE;")
3513 ;; Note that the (return) from the expander itself is always the last
3514 ;; insn in the epilogue.
3515 (define_expand "epilogue"
3517 "TARGET_PROLOGUE_EPILOGUE"
3518 "cris_expand_epilogue (); DONE;")
3520 ;; Conditional branches.
3522 (define_expand "cbranch<mode>4"
3523 [(set (cc0) (compare
3524 (match_operand:BWD 1 "nonimmediate_operand")
3525 (match_operand:BWD 2 "general_operand")))
3527 (if_then_else (match_operator 0 "ordered_comparison_operator"
3528 [(cc0) (const_int 0)])
3529 (label_ref (match_operand 3 "" ""))
3534 (define_expand "cbranchdi4"
3536 (compare (match_operand:DI 1 "nonimmediate_operand" "")
3537 (match_operand:DI 2 "general_operand" "")))
3539 (if_then_else (match_operator 0 "ordered_comparison_operator"
3540 [(cc0) (const_int 0)])
3541 (label_ref (match_operand 3 "" ""))
3545 if (TARGET_V32 && !REG_P (operands[1]))
3546 operands[1] = force_reg (DImode, operands[1]);
3547 if (TARGET_V32 && MEM_P (operands[2]))
3548 operands[2] = force_reg (DImode, operands[2]);
3552 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3553 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3556 (define_insn "b<ncond:code>"
3558 (if_then_else (ncond (cc0)
3560 (label_ref (match_operand 0 "" ""))
3564 [(set_attr "slottable" "has_slot")])
3566 (define_insn "b<ocond:code>"
3568 (if_then_else (ocond (cc0)
3570 (label_ref (match_operand 0 "" ""))
3575 (cc_prev_status.flags & CC_NO_OVERFLOW)
3576 ? 0 : "b<CC> %l0%#";
3578 [(set_attr "slottable" "has_slot")])
3580 (define_insn "b<rcond:code>"
3582 (if_then_else (rcond (cc0)
3584 (label_ref (match_operand 0 "" ""))
3589 (cc_prev_status.flags & CC_NO_OVERFLOW)
3590 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3592 [(set_attr "slottable" "has_slot")])
3594 ;; Reversed anonymous patterns to the ones above, as mandated.
3596 (define_insn "*b<ncond:code>_reversed"
3598 (if_then_else (ncond (cc0)
3601 (label_ref (match_operand 0 "" ""))))]
3604 [(set_attr "slottable" "has_slot")])
3606 (define_insn "*b<ocond:code>_reversed"
3608 (if_then_else (ocond (cc0)
3611 (label_ref (match_operand 0 "" ""))))]
3615 (cc_prev_status.flags & CC_NO_OVERFLOW)
3616 ? 0 : "b<rCC> %l0%#";
3618 [(set_attr "slottable" "has_slot")])
3620 (define_insn "*b<rcond:code>_reversed"
3622 (if_then_else (rcond (cc0)
3625 (label_ref (match_operand 0 "" ""))))]
3629 (cc_prev_status.flags & CC_NO_OVERFLOW)
3630 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3632 [(set_attr "slottable" "has_slot")])
3634 ;; Set on condition: sCC.
3636 (define_expand "cstoredi4"
3637 [(set (cc0) (compare
3638 (match_operand:DI 2 "nonimmediate_operand")
3639 (match_operand:DI 3 "general_operand")))
3640 (set (match_operand:SI 0 "register_operand")
3641 (match_operator:SI 1 "ordered_comparison_operator"
3642 [(cc0) (const_int 0)]))]
3645 if (TARGET_V32 && !REG_P (operands[2]))
3646 operands[2] = force_reg (DImode, operands[2]);
3647 if (TARGET_V32 && MEM_P (operands[3]))
3648 operands[3] = force_reg (DImode, operands[3]);
3651 (define_expand "cstore<mode>4"
3652 [(set (cc0) (compare
3653 (match_operand:BWD 2 "nonimmediate_operand")
3654 (match_operand:BWD 3 "general_operand")))
3655 (set (match_operand:SI 0 "register_operand")
3656 (match_operator:SI 1 "ordered_comparison_operator"
3657 [(cc0) (const_int 0)]))]
3661 ;; Like bCC, we have to check the overflow bit for
3662 ;; signed conditions.
3664 (define_insn "s<ncond:code>"
3665 [(set (match_operand:SI 0 "register_operand" "=r")
3666 (ncond:SI (cc0) (const_int 0)))]
3669 [(set_attr "slottable" "yes")
3670 (set_attr "cc" "none")])
3672 (define_insn "s<rcond:code>"
3673 [(set (match_operand:SI 0 "register_operand" "=r")
3674 (rcond:SI (cc0) (const_int 0)))]
3678 (cc_prev_status.flags & CC_NO_OVERFLOW)
3679 ? "s<oCC> %0" : "s<CC> %0";
3681 [(set_attr "slottable" "yes")
3682 (set_attr "cc" "none")])
3684 (define_insn "s<ocond:code>"
3685 [(set (match_operand:SI 0 "register_operand" "=r")
3686 (ocond:SI (cc0) (const_int 0)))]
3690 (cc_prev_status.flags & CC_NO_OVERFLOW)
3693 [(set_attr "slottable" "yes")
3694 (set_attr "cc" "none")])
3698 ;; We need to make these patterns "expand", since the real operand is
3699 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3700 ;; and cannot be checked if it were a "normal" pattern.
3701 ;; Note that "call" and "call_value" are *always* called with a
3702 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3703 ;; instructions is a different issue.
3705 (define_expand "call"
3706 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3707 (match_operand 1 "general_operand" ""))
3708 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3711 gcc_assert (MEM_P (operands[0]));
3713 cris_expand_pic_call_address (&operands[0]);
3716 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3717 ;; order of preference.
3719 (define_insn "*expanded_call_non_v32"
3720 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
3721 (match_operand 1 "" ""))
3722 (clobber (reg:SI CRIS_SRP_REGNUM))]
3726 (define_insn "*expanded_call_v32"
3729 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3730 (match_operand 1 "" ""))
3731 (clobber (reg:SI CRIS_SRP_REGNUM))]
3738 [(set_attr "slottable" "has_call_slot")])
3740 ;; Parallel when calculating and reusing address of indirect pointer
3741 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3742 ;; wrong not to have the clobber last, but that's the way combine
3743 ;; generates it (except it doesn' look into the *inner* mem, so this
3744 ;; just matches a peephole2). FIXME: investigate that.
3745 (define_insn "*expanded_call_side"
3748 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
3749 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3750 (match_operand 2 "" ""))
3751 (clobber (reg:SI CRIS_SRP_REGNUM))
3752 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
3753 (plus:SI (match_dup 0)
3755 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3758 (define_expand "call_value"
3759 [(parallel [(set (match_operand 0 "" "")
3760 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3761 (match_operand 2 "" "")))
3762 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3765 gcc_assert (MEM_P (operands[1]));
3767 cris_expand_pic_call_address (&operands[1]);
3770 ;; Accept *anything* as operand 2. The validity other than "general" of
3771 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3772 ;; order of preference (Q includes r, but r is shorter, faster).
3773 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3774 ;; than requiring getting rPIC + sym:PLT into a register.
3776 (define_insn "*expanded_call_value_non_v32"
3777 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3778 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
3779 (match_operand 2 "" "")))
3780 (clobber (reg:SI CRIS_SRP_REGNUM))]
3783 [(set_attr "cc" "clobber")])
3785 ;; See similar call special-case.
3786 (define_insn "*expanded_call_value_side"
3787 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3791 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
3792 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3793 (match_operand 3 "" "")))
3794 (clobber (reg:SI CRIS_SRP_REGNUM))
3795 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3796 (plus:SI (match_dup 1)
3798 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3800 [(set_attr "cc" "clobber")])
3802 (define_insn "*expanded_call_value_v32"
3804 (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3807 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3808 (match_operand 2 "" "")))
3809 (clobber (reg:SI 16))]
3816 [(set_attr "cc" "clobber")
3817 (set_attr "slottable" "has_call_slot")])
3819 ;; Used in debugging. No use for the direct pattern; unfilled
3820 ;; delayed-branches are taken care of by other means.
3826 [(set_attr "cc" "none")])
3828 ;; Same as the gdb trap breakpoint, will cause a SIGTRAP for
3829 ;; cris-linux* and crisv32-linux*, as intended. Will work in
3830 ;; freestanding environments with sufficient framework.
3832 [(trap_if (const_int 1) (const_int 8))]
3833 "TARGET_TRAP_USING_BREAK8"
3836 ;; We need to stop accesses to the stack after the memory is
3837 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3838 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3839 ;; want to use a naked (unspec_volatile) as that would stop any
3840 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3841 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3842 ;; still has the effect of an unspec_volatile.
3843 (define_insn "cris_frame_deallocated_barrier"
3844 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3845 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3848 [(set_attr "length" "0")])
3850 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3851 ;; a table to pc" (adds.w [pc+%0.w],pc).
3853 ;; Note: if you change the "parallel" (or add anything after it) in
3854 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3855 ;; accordingly, to add the default case at the end of the jump-table.
3857 (define_expand "cris_casesi_non_v32"
3858 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3860 (minus:SI (match_dup 5)
3861 (match_operand:SI 1 "const_int_operand" "n")))
3863 (umin:SI (match_dup 6)
3864 (match_operand:SI 2 "const_int_operand" "n")))
3868 (ltu (match_dup 7) (match_dup 2))
3869 (plus:SI (sign_extend:SI
3871 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3874 (label_ref (match_operand 4 "" ""))))
3875 (use (label_ref (match_operand 3 "" "")))])]
3878 operands[2] = plus_constant (SImode, operands[2], 1);
3879 operands[5] = gen_reg_rtx (SImode);
3880 operands[6] = gen_reg_rtx (SImode);
3881 operands[7] = gen_reg_rtx (SImode);
3884 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3885 (define_expand "cris_casesi_v32"
3886 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
3888 (minus:SI (match_dup 5)
3889 (match_operand:SI 1 "const_int_operand")))
3891 (umin:SI (match_dup 6)
3892 (match_operand:SI 2 "const_int_operand")))
3893 (set (match_dup 8) (match_dup 11))
3895 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3898 (plus:SI (sign_extend:SI (mem:HI (match_dup 9)))
3903 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2))
3905 (label_ref (match_operand 4 "" ""))))
3906 (use (label_ref (match_dup 3)))])]
3910 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
3911 for (i = 5; i <= 10; i++)
3912 operands[i] = gen_reg_rtx (SImode);
3913 operands[2] = plus_constant (SImode, operands[2], 1);
3915 /* Don't forget to decorate labels too, for PIC. */
3916 operands[11] = flag_pic
3917 ? gen_rtx_CONST (Pmode,
3918 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel),
3923 (define_expand "casesi"
3924 [(match_operand:SI 0 "general_operand")
3925 (match_operand:SI 1 "const_int_operand")
3926 (match_operand:SI 2 "const_int_operand")
3927 (match_operand 3 "" "")
3928 (match_operand 4 "" "")]
3932 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2],
3933 operands[3], operands[4]));
3935 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2],
3936 operands[3], operands[4]));
3940 ;; Split-patterns. Some of them have modes unspecified. This
3941 ;; should always be ok; if for no other reason sparc.md has it as
3944 ;; When register_operand is specified for an operand, we can get a
3945 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3946 ;; for a register_operand and that REGNO can be used as is. It is best to
3947 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3949 ;; op [rx + 0],ry,rz
3950 ;; The index to rx is optimized into zero, and gone.
3952 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3953 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3957 ;; Lose if rz=ry or rx=rz.
3958 ;; Call this op-extend-split.
3959 ;; Do not match for V32; the addo and addi shouldn't be split
3963 [(set (match_operand 0 "register_operand" "")
3965 4 "cris_operand_extend_operator"
3966 [(match_operand 1 "register_operand" "")
3968 3 "cris_extend_operator"
3969 [(match_operand 2 "memory_operand" "")])]))]
3971 && REG_P (operands[0])
3972 && REG_P (operands[1])
3973 && REGNO (operands[1]) != REGNO (operands[0])
3974 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3975 && REG_P (XEXP (operands[2], 0))
3976 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3982 (match_op_dup 3 [(match_dup 2)])]))]
3985 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3988 ;; Do this for plus or bound only, being commutative operations, since we
3989 ;; have swapped the operands.
3990 ;; Call this op-extend-split-rx=rz
3993 [(set (match_operand 0 "register_operand" "")
3995 4 "cris_plus_or_bound_operator"
3996 [(match_operand 1 "register_operand" "")
3998 3 "cris_extend_operator"
3999 [(match_operand 2 "memory_operand" "")])]))]
4001 && REG_P (operands[0])
4002 && REG_P (operands[1])
4003 && REGNO (operands[1]) != REGNO (operands[0])
4004 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4005 && REG_P (XEXP (operands[2], 0))
4006 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4008 (match_op_dup 3 [(match_dup 2)]))
4015 ;; As the op-extend-split, but swapped operands, and only for
4016 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4017 ;; this needed? Is it?
4018 ;; Call this op-extend-split-swapped
4021 [(set (match_operand 0 "register_operand" "")
4023 4 "cris_plus_or_bound_operator"
4025 3 "cris_extend_operator"
4026 [(match_operand 2 "memory_operand" "")])
4027 (match_operand 1 "register_operand" "")]))]
4029 && REG_P (operands[0])
4030 && REG_P (operands[1])
4031 && REGNO (operands[1]) != REGNO (operands[0])
4032 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4033 && REG_P (XEXP (operands[2], 0))
4034 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4040 (match_op_dup 3 [(match_dup 2)])]))]
4043 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4044 ;; bound. Call this op-extend-split-swapped-rx=rz.
4047 [(set (match_operand 0 "register_operand" "")
4049 4 "cris_plus_or_bound_operator"
4051 3 "cris_extend_operator"
4052 [(match_operand 2 "memory_operand" "")])
4053 (match_operand 1 "register_operand" "")]))]
4055 && REG_P (operands[0])
4056 && REG_P (operands[1])
4057 && REGNO (operands[1]) != REGNO (operands[0])
4058 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4059 && REG_P (XEXP (operands[2], 0))
4060 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4062 (match_op_dup 3 [(match_dup 2)]))
4069 ;; As op-extend-split, but the mem operand is not extended.
4071 ;; op [rx],ry,rz changed into
4074 ;; lose if ry=rz or rx=rz
4075 ;; Call this op-extend.
4078 [(set (match_operand 0 "register_operand" "")
4080 3 "cris_orthogonal_operator"
4081 [(match_operand 1 "register_operand" "")
4082 (match_operand 2 "memory_operand" "")]))]
4084 && REG_P (operands[0])
4085 && REG_P (operands[1])
4086 && REGNO (operands[1]) != REGNO (operands[0])
4087 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4088 && REG_P (XEXP (operands[2], 0))
4089 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4098 ;; As op-extend-split-rx=rz, non-extended.
4099 ;; Call this op-split-rx=rz
4102 [(set (match_operand 0 "register_operand" "")
4104 3 "cris_commutative_orth_op"
4105 [(match_operand 2 "memory_operand" "")
4106 (match_operand 1 "register_operand" "")]))]
4108 && REG_P (operands[0])
4109 && REG_P (operands[1])
4110 && REGNO (operands[1]) != REGNO (operands[0])
4111 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4112 && REG_P (XEXP (operands[2], 0))
4113 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4122 ;; As op-extend-split-swapped, nonextended.
4123 ;; Call this op-split-swapped.
4126 [(set (match_operand 0 "register_operand" "")
4128 3 "cris_commutative_orth_op"
4129 [(match_operand 1 "register_operand" "")
4130 (match_operand 2 "memory_operand" "")]))]
4132 && REG_P (operands[0]) && REG_P (operands[1])
4133 && REGNO (operands[1]) != REGNO (operands[0])
4134 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4135 && REG_P (XEXP (operands[2], 0))
4136 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4145 ;; As op-extend-split-swapped-rx=rz, non-extended.
4146 ;; Call this op-split-swapped-rx=rz.
4149 [(set (match_operand 0 "register_operand" "")
4151 3 "cris_orthogonal_operator"
4152 [(match_operand 2 "memory_operand" "")
4153 (match_operand 1 "register_operand" "")]))]
4155 && REG_P (operands[0]) && REG_P (operands[1])
4156 && REGNO (operands[1]) != REGNO (operands[0])
4157 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4158 && REG_P (XEXP (operands[2], 0))
4159 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4170 ;; Splits for all cases in side-effect insns where (possibly after reload
4171 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4173 ;; move.S1 [rx=rx+rz.S2],ry
4177 [(set (match_operand 0 "register_operand" "")
4181 (mult:SI (match_operand:SI 1 "register_operand" "")
4182 (match_operand:SI 2 "const_int_operand" ""))
4183 (match_operand:SI 3 "register_operand" ""))]))
4184 (set (match_operand:SI 4 "register_operand" "")
4185 (plus:SI (mult:SI (match_dup 1)
4188 "REG_P (operands[3]) && REG_P (operands[4])
4189 && REGNO (operands[3]) == REGNO (operands[4])"
4190 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4192 (set (match_dup 0) (match_dup 5))]
4193 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4195 ;; move.S1 [rx=rx+i],ry
4199 [(set (match_operand 0 "register_operand" "")
4202 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4203 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4204 (set (match_operand:SI 3 "register_operand" "")
4205 (plus:SI (match_dup 1)
4207 "(rtx_equal_p (operands[3], operands[1])
4208 || rtx_equal_p (operands[3], operands[2]))"
4209 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4210 (set (match_dup 0) (match_dup 4))]
4212 operands[4] = replace_equiv_address (operands[5], operands[3]);
4213 cris_order_for_addsi3 (operands, 1);
4216 ;; move.S1 ry,[rx=rx+rz.S2]
4220 [(set (match_operator
4223 (mult:SI (match_operand:SI 0 "register_operand" "")
4224 (match_operand:SI 1 "const_int_operand" ""))
4225 (match_operand:SI 2 "register_operand" ""))])
4226 (match_operand 3 "register_operand" ""))
4227 (set (match_operand:SI 4 "register_operand" "")
4228 (plus:SI (mult:SI (match_dup 0)
4231 "REG_P (operands[2]) && REG_P (operands[4])
4232 && REGNO (operands[4]) == REGNO (operands[2])"
4233 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4235 (set (match_dup 5) (match_dup 3))]
4236 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4238 ;; move.S1 ry,[rx=rx+i]
4242 [(set (match_operator
4244 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4245 (match_operand:SI 1 "cris_bdap_operand" ""))])
4246 (match_operand 2 "register_operand" ""))
4247 (set (match_operand:SI 3 "register_operand" "")
4248 (plus:SI (match_dup 0)
4250 "(rtx_equal_p (operands[3], operands[0])
4251 || rtx_equal_p (operands[3], operands[1]))"
4252 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4253 (set (match_dup 5) (match_dup 2))]
4255 operands[5] = replace_equiv_address (operands[6], operands[3]);
4256 cris_order_for_addsi3 (operands, 0);
4259 ;; clear.[bwd] [rx=rx+rz.S2]
4263 [(set (mem:BWD (plus:SI
4264 (mult:SI (match_operand:SI 0 "register_operand" "")
4265 (match_operand:SI 1 "const_int_operand" ""))
4266 (match_operand:SI 2 "register_operand" "")))
4268 (set (match_operand:SI 3 "register_operand" "")
4269 (plus:SI (mult:SI (match_dup 0)
4272 "REG_P (operands[2]) && REG_P (operands[3])
4273 && REGNO (operands[3]) == REGNO (operands[2])"
4274 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4276 (set (mem:BWD (match_dup 3)) (const_int 0))]
4279 ;; clear.[bwd] [rx=rx+i]
4284 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4285 (match_operand:SI 1 "cris_bdap_operand" "")))
4287 (set (match_operand:SI 2 "register_operand" "")
4288 (plus:SI (match_dup 0)
4290 "(rtx_equal_p (operands[0], operands[2])
4291 || rtx_equal_p (operands[2], operands[1]))"
4292 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4293 (set (mem:BWD (match_dup 2)) (const_int 0))]
4294 "cris_order_for_addsi3 (operands, 0);")
4296 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4300 [(set (match_operand 0 "register_operand" "")
4302 5 "cris_extend_operator"
4304 (mult:SI (match_operand:SI 1 "register_operand" "")
4305 (match_operand:SI 2 "const_int_operand" ""))
4306 (match_operand:SI 3 "register_operand" "")))]))
4307 (set (match_operand:SI 4 "register_operand" "")
4308 (plus:SI (mult:SI (match_dup 1)
4311 "REG_P (operands[3])
4312 && REG_P (operands[4])
4313 && REGNO (operands[3]) == REGNO (operands[4])"
4314 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4316 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4317 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4319 ;; mov(s|u).S1 [rx=rx+i],ry
4323 [(set (match_operand 0 "register_operand" "")
4325 4 "cris_extend_operator"
4327 (match_operand:SI 1 "cris_bdap_operand" "")
4328 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4329 (set (match_operand:SI 3 "register_operand" "")
4330 (plus:SI (match_dup 1)
4332 "(rtx_equal_p (operands[1], operands[3])
4333 || rtx_equal_p (operands[2], operands[3]))"
4334 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4335 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4337 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
4338 cris_order_for_addsi3 (operands, 1);
4341 ;; op.S1 [rx=rx+i],ry
4345 [(set (match_operand 0 "register_operand" "")
4347 5 "cris_orthogonal_operator"
4348 [(match_operand 1 "register_operand" "")
4350 (match_operand:SI 2 "cris_bdap_operand" "")
4351 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4352 (set (match_operand:SI 4 "register_operand" "")
4353 (plus:SI (match_dup 2)
4355 "(rtx_equal_p (operands[4], operands[2])
4356 || rtx_equal_p (operands[4], operands[3]))"
4357 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4358 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4360 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
4361 cris_order_for_addsi3 (operands, 2);
4364 ;; op.S1 [rx=rx+rz.S2],ry
4368 [(set (match_operand 0 "register_operand" "")
4370 6 "cris_orthogonal_operator"
4371 [(match_operand 1 "register_operand" "")
4373 (mult:SI (match_operand:SI 2 "register_operand" "")
4374 (match_operand:SI 3 "const_int_operand" ""))
4375 (match_operand:SI 4 "register_operand" "")))]))
4376 (set (match_operand:SI 5 "register_operand" "")
4377 (plus:SI (mult:SI (match_dup 2)
4380 "REG_P (operands[4])
4381 && REG_P (operands[5])
4382 && REGNO (operands[5]) == REGNO (operands[4])"
4383 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4385 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4386 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4388 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4392 [(set (match_operand 0 "register_operand" "")
4394 6 "cris_commutative_orth_op"
4396 (mult:SI (match_operand:SI 2 "register_operand" "")
4397 (match_operand:SI 3 "const_int_operand" ""))
4398 (match_operand:SI 4 "register_operand" "")))
4399 (match_operand 1 "register_operand" "")]))
4400 (set (match_operand:SI 5 "register_operand" "")
4401 (plus:SI (mult:SI (match_dup 2)
4404 "REG_P (operands[4])
4405 && REG_P (operands[5])
4406 && REGNO (operands[5]) == REGNO (operands[4])"
4407 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4409 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4410 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4412 ;; op.S1 [rx=rx+i],ry (swapped)
4416 [(set (match_operand 0 "register_operand" "")
4418 5 "cris_commutative_orth_op"
4420 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4421 (match_operand:SI 3 "cris_bdap_operand" "")))
4422 (match_operand 1 "register_operand" "")]))
4423 (set (match_operand:SI 4 "register_operand" "")
4424 (plus:SI (match_dup 2)
4426 "(rtx_equal_p (operands[4], operands[2])
4427 || rtx_equal_p (operands[4], operands[3]))"
4428 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4429 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4431 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
4432 cris_order_for_addsi3 (operands, 2);
4435 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4439 [(set (match_operand 0 "register_operand" "")
4441 6 "cris_operand_extend_operator"
4442 [(match_operand 1 "register_operand" "")
4444 7 "cris_extend_operator"
4446 (mult:SI (match_operand:SI 2 "register_operand" "")
4447 (match_operand:SI 3 "const_int_operand" ""))
4448 (match_operand:SI 4 "register_operand" "")))])]))
4449 (set (match_operand:SI 5 "register_operand" "")
4450 (plus:SI (mult:SI (match_dup 2)
4453 "REG_P (operands[4])
4454 && REG_P (operands[5])
4455 && REGNO (operands[5]) == REGNO (operands[4])"
4456 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4458 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4459 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4460 replace_equiv_address (XEXP (operands[7], 0),
4463 ;; op(s|u).S1 [rx=rx+i],ry
4467 [(set (match_operand 0 "register_operand" "")
4469 5 "cris_operand_extend_operator"
4470 [(match_operand 1 "register_operand" "")
4472 6 "cris_extend_operator"
4474 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4475 (match_operand:SI 3 "cris_bdap_operand" "")
4477 (set (match_operand:SI 4 "register_operand" "")
4478 (plus:SI (match_dup 2)
4480 "(rtx_equal_p (operands[4], operands[2])
4481 || rtx_equal_p (operands[4], operands[3]))"
4482 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4483 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4485 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4486 replace_equiv_address (XEXP (operands[6], 0),
4488 cris_order_for_addsi3 (operands, 2);
4491 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4495 [(set (match_operand 0 "register_operand" "")
4497 7 "cris_plus_or_bound_operator"
4499 6 "cris_extend_operator"
4501 (mult:SI (match_operand:SI 2 "register_operand" "")
4502 (match_operand:SI 3 "const_int_operand" ""))
4503 (match_operand:SI 4 "register_operand" "")))])
4504 (match_operand 1 "register_operand" "")]))
4505 (set (match_operand:SI 5 "register_operand" "")
4506 (plus:SI (mult:SI (match_dup 2)
4509 "REG_P (operands[4]) && REG_P (operands[5])
4510 && REGNO (operands[5]) == REGNO (operands[4])"
4511 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4513 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4514 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4515 replace_equiv_address (XEXP (operands[6], 0),
4518 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4522 [(set (match_operand 0 "register_operand" "")
4524 6 "cris_plus_or_bound_operator"
4526 5 "cris_extend_operator"
4528 (match_operand:SI 2 "cris_bdap_operand" "")
4529 (match_operand:SI 3 "cris_bdap_operand" "")))])
4530 (match_operand 1 "register_operand" "")]))
4531 (set (match_operand:SI 4 "register_operand" "")
4532 (plus:SI (match_dup 2)
4534 "(rtx_equal_p (operands[4], operands[2])
4535 || rtx_equal_p (operands[4], operands[3]))"
4536 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4537 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4539 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4540 replace_equiv_address (XEXP (operands[5], 0),
4542 cris_order_for_addsi3 (operands, 2);
4545 ;; Splits for addressing prefixes that have no side-effects, so we can
4546 ;; fill a delay slot. Never split if we lose something, though.
4549 ;; move [indirect_ref],rx
4550 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4551 ;; move indirect_ref,rx
4553 ;; Take care not to allow indirect_ref = register.
4555 ;; We're not allowed to generate copies of registers with different mode
4556 ;; until after reload; copying pseudos upsets reload. CVS as of
4557 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4558 ;; cselib_invalidate_regno.
4560 (define_split ; indir_to_reg_split
4561 [(set (match_operand 0 "register_operand" "")
4562 (match_operand 1 "indirect_operand" ""))]
4564 && REG_P (operands[0])
4565 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4566 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
4567 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
4568 [(set (match_dup 2) (match_dup 4))
4569 (set (match_dup 0) (match_dup 3))]
4570 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4571 operands[3] = replace_equiv_address (operands[1], operands[2]);
4572 operands[4] = XEXP (operands[1], 0);")
4574 ;; As the above, but MOVS and MOVU.
4577 [(set (match_operand 0 "register_operand" "")
4579 4 "cris_extend_operator"
4580 [(match_operand 1 "indirect_operand" "")]))]
4582 && REG_P (operands[0])
4583 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4584 && (MEM_P (XEXP (operands[1], 0))
4585 || CONSTANT_P (XEXP (operands[1], 0)))"
4586 [(set (match_dup 2) (match_dup 5))
4587 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4588 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4589 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4590 operands[5] = XEXP (operands[1], 0);")
4592 ;; Various peephole optimizations.
4594 ;; Watch out: when you exchange one set of instructions for another, the
4595 ;; condition codes setting must be the same, or you have to CC_INIT or
4596 ;; whatever is appropriate, in the pattern before you emit the
4597 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4598 ;; to keep changes local to their cause.
4600 ;; Do not add patterns that you do not know will be matched.
4601 ;; Please also add a self-contained testcase.
4603 ;; We have trouble with and:s and shifts. Maybe something is broken in
4604 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4605 ;; suboptimal when not having extzv insns.
4606 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4608 (define_peephole2 ; asrandb (peephole casesi+31)
4609 [(set (match_operand:SI 0 "register_operand" "")
4610 (ashiftrt:SI (match_dup 0)
4611 (match_operand:SI 1 "const_int_operand" "")))
4613 (and:SI (match_dup 0)
4614 (match_operand 2 "const_int_operand" "")))]
4615 "INTVAL (operands[2]) > 31
4616 && INTVAL (operands[2]) < 255
4617 && INTVAL (operands[1]) > 23
4618 /* Check that the and-operation enables us to use logical-shift. */
4619 && (INTVAL (operands[2])
4620 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4621 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4622 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4623 ;; FIXME: CC0 is valid except for the M bit.
4625 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4626 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4629 (define_peephole2 ; asrandw (peephole casesi+32)
4630 [(set (match_operand:SI 0 "register_operand" "")
4631 (ashiftrt:SI (match_dup 0)
4632 (match_operand:SI 1 "const_int_operand" "")))
4634 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4635 "INTVAL (operands[2]) > 31
4636 && INTVAL (operands[2]) < 65535
4637 && INTVAL (operands[2]) != 255
4638 && INTVAL (operands[1]) > 15
4639 /* Check that the and-operation enables us to use logical-shift. */
4640 && (INTVAL (operands[2])
4641 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4642 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4643 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4644 ;; FIXME: CC0 is valid except for the M bit.
4646 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4647 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4650 (define_peephole2 ; lsrandb (peephole casesi+33)
4651 [(set (match_operand:SI 0 "register_operand" "")
4652 (lshiftrt:SI (match_dup 0)
4653 (match_operand:SI 1 "const_int_operand" "")))
4655 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4656 "INTVAL (operands[2]) > 31
4657 && INTVAL (operands[2]) < 255
4658 && INTVAL (operands[1]) > 23"
4659 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4660 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4661 ;; FIXME: CC0 is valid except for the M bit.
4663 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4664 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4667 (define_peephole2 ; lsrandw (peephole casesi+34)
4668 [(set (match_operand:SI 0 "register_operand" "")
4669 (lshiftrt:SI (match_dup 0)
4670 (match_operand:SI 1 "const_int_operand" "")))
4672 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4673 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4674 && INTVAL (operands[2]) != 255
4675 && INTVAL (operands[1]) > 15"
4676 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4677 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4678 ;; FIXME: CC0 is valid except for the M bit.
4680 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4681 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4689 ;; move [rx=rx+n],ry
4690 ;; when -128 <= n <= 127.
4691 ;; This will reduce the size of the assembler code for n = [-128..127],
4692 ;; and speed up accordingly. Don't match if the previous insn is
4693 ;; (set rx rz) because that combination is matched by another peephole.
4694 ;; No stable test-case.
4696 (define_peephole2 ; moversideqi (peephole casesi+35)
4697 [(set (match_operand:SI 0 "register_operand" "")
4698 (plus:SI (match_operand:SI 1 "register_operand" "")
4699 (match_operand:SI 2 "const_int_operand" "")))
4700 (set (match_operand 3 "register_operand" "")
4701 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4702 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4703 && REGNO (operands[3]) != REGNO (operands[0])
4704 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true))
4705 && !satisfies_constraint_J (operands[2])
4706 && !satisfies_constraint_N (operands[2])
4707 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4708 && TARGET_SIDE_EFFECT_PREFIXES"
4710 [(set (match_dup 3) (match_dup 5))
4711 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4712 ;; Checking the previous insn is a bit too awkward for the condition.
4714 rtx prev = prev_nonnote_insn (curr_insn);
4715 if (prev != NULL_RTX)
4717 rtx set = single_set (prev);
4719 && REG_S_P (SET_DEST (set))
4720 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4721 && REG_S_P (SET_SRC (set)))
4725 = replace_equiv_address (operands[4],
4726 gen_rtx_PLUS (SImode,
4727 operands[1], operands[2]));
4730 ;; Vice versa: move ry,[rx=rx+n]
4732 (define_peephole2 ; movemsideqi (peephole casesi+36)
4733 [(set (match_operand:SI 0 "register_operand" "")
4734 (plus:SI (match_operand:SI 1 "register_operand" "")
4735 (match_operand:SI 2 "const_int_operand" "")))
4736 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4737 (match_operand 4 "register_operand" ""))]
4738 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4739 && REGNO (operands[4]) != REGNO (operands[0])
4740 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true))
4741 && !satisfies_constraint_J (operands[2])
4742 && !satisfies_constraint_N (operands[2])
4743 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4744 && TARGET_SIDE_EFFECT_PREFIXES"
4746 [(set (match_dup 5) (match_dup 4))
4747 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4749 = replace_equiv_address (operands[3],
4750 gen_rtx_PLUS (SImode,
4751 operands[1], operands[2]));")
4753 ;; As above, change:
4757 ;; op.d [rx=rx+n],ry
4758 ;; Saves when n = [-128..127].
4760 ;; Splitting and joining combinations for side-effect modes are slightly
4761 ;; out of hand. They probably will not save the time they take typing in,
4762 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4763 ;; the splits and peepholes as possible.
4764 ;; No stable test-case.
4766 (define_peephole2 ; mover2side (peephole casesi+37)
4767 [(set (match_operand:SI 0 "register_operand" "")
4768 (plus:SI (match_operand:SI 1 "register_operand" "")
4769 (match_operand:SI 2 "const_int_operand" "")))
4770 (set (match_operand 3 "register_operand" "")
4771 (match_operator 4 "cris_orthogonal_operator"
4774 5 "cris_mem_op" [(match_dup 0)])]))]
4775 ;; FIXME: What about DFmode?
4776 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
4777 "GET_MODE (operands[3]) != DImode
4778 && REGNO (operands[0]) != REGNO (operands[3])
4779 && !satisfies_constraint_J (operands[2])
4780 && !satisfies_constraint_N (operands[2])
4781 && INTVAL (operands[2]) >= -128
4782 && INTVAL (operands[2]) <= 127
4783 && TARGET_SIDE_EFFECT_PREFIXES"
4785 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4786 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4788 = replace_equiv_address (operands[5],
4789 gen_rtx_PLUS (SImode,
4790 operands[1], operands[2]));")
4792 ;; Sometimes, for some reason the pattern
4796 ;; will occur. Solve this, and likewise for to-memory.
4797 ;; No stable test-case.
4799 (define_peephole2 ; moverside (peephole casesi+38)
4800 [(set (match_operand:SI 0 "register_operand" "")
4801 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4803 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4804 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4805 (set (match_operand 4 "register_operand" "")
4806 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4807 "(rtx_equal_p (operands[2], operands[0])
4808 || rtx_equal_p (operands[3], operands[0]))
4809 && cris_side_effect_mode_ok (PLUS, operands, 0,
4810 (REG_S_P (operands[1])
4812 : (rtx_equal_p (operands[2], operands[0])
4814 (! REG_S_P (operands[1])
4816 : (rtx_equal_p (operands[2], operands[0])
4820 [(set (match_dup 4) (match_dup 6))
4821 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4824 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4826 /* Make sure we have canonical RTX so we match the insn pattern -
4827 not a constant in the first operand. We also require the order
4828 (plus reg mem) to match the final pattern. */
4829 if (CONSTANT_P (otherop) || MEM_P (otherop))
4831 operands[7] = operands[1];
4832 operands[8] = otherop;
4836 operands[7] = otherop;
4837 operands[8] = operands[1];
4840 = replace_equiv_address (operands[5],
4841 gen_rtx_PLUS (SImode,
4842 operands[7], operands[8]));
4845 ;; As above but to memory.
4846 ;; FIXME: Split movemside and moverside into variants and prune
4847 ;; the ones that don't trig.
4848 ;; No stable test-case.
4850 (define_peephole2 ; movemside (peephole casesi+39)
4851 [(set (match_operand:SI 0 "register_operand" "")
4852 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4854 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4855 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4856 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4857 (match_operand 5 "register_operand" ""))]
4858 "(rtx_equal_p (operands[2], operands[0])
4859 || rtx_equal_p (operands[3], operands[0]))
4860 && cris_side_effect_mode_ok (PLUS, operands, 0,
4861 (REG_S_P (operands[1])
4863 : (rtx_equal_p (operands[2], operands[0])
4865 (! REG_S_P (operands[1])
4867 : (rtx_equal_p (operands[2], operands[0])
4871 [(set (match_dup 6) (match_dup 5))
4872 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4875 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4877 /* Make sure we have canonical RTX so we match the insn pattern -
4878 not a constant in the first operand. We also require the order
4879 (plus reg mem) to match the final pattern. */
4880 if (CONSTANT_P (otherop) || MEM_P (otherop))
4882 operands[7] = operands[1];
4883 operands[8] = otherop;
4887 operands[7] = otherop;
4888 operands[8] = operands[1];
4891 = replace_equiv_address (operands[4],
4892 gen_rtx_PLUS (SImode,
4893 operands[7], operands[8]));
4896 ;; Another spotted bad code:
4899 ;; No stable test-case.
4901 (define_peephole2 ; movei (peephole casesi+42)
4902 [(set (match_operand:SI 0 "register_operand" "")
4903 (match_operand:SI 1 "register_operand" ""))
4904 (set (match_operand 2 "register_operand" "")
4905 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4906 "REGNO (operands[0]) == REGNO (operands[2])
4907 && (REGNO_REG_CLASS (REGNO (operands[0]))
4908 == REGNO_REG_CLASS (REGNO (operands[1])))
4909 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4910 [(set (match_dup 2) (match_dup 4))]
4911 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4913 ;; move.d [r10+16],r9
4916 ;; and.d [r10+16],r12,r9
4917 ;; With generalization of the operation, the size and the addressing mode.
4918 ;; This seems to be the result of a quirk in register allocation
4919 ;; missing the three-operand cases when having different predicates.
4920 ;; Maybe that it matters that it is a commutative operation.
4921 ;; This pattern helps that situation, but there's still the increased
4922 ;; register pressure.
4923 ;; Note that adding the noncommutative variant did not show any matches
4924 ;; in ipps and cc1, so it's not here.
4925 ;; No stable test-case.
4927 (define_peephole2 ; op3 (peephole casesi+44)
4928 [(set (match_operand 0 "register_operand" "")
4932 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4933 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4936 5 "cris_commutative_orth_op"
4937 [(match_operand 3 "register_operand" "")
4938 (match_operand 4 "register_operand" "")]))]
4939 "(rtx_equal_p (operands[3], operands[0])
4940 || rtx_equal_p (operands[4], operands[0]))
4941 && ! rtx_equal_p (operands[3], operands[4])
4942 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4943 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4944 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4946 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4948 ;; There seems to be no other way to make GCC (including 4.8/trunk at
4949 ;; r186932) optimally reload an instruction that looks like
4950 ;; and.d reg_or_mem,const_32__65535,other_reg
4951 ;; where other_reg is the destination.
4953 ;; movu.[bw] reg_or_mem,reg_32
4954 ;; and.[bw] trunc_int_for_mode([bw], const_32__65535),reg_32 ;; or andq
4955 ;; but it turns into:
4956 ;; move.d reg_or_mem,reg_32
4957 ;; and.d const_32__65535,reg_32
4958 ;; Fix it with these two peephole2's.
4959 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4961 (define_peephole2 ; andu (casesi+45)
4962 [(set (match_operand:SI 0 "register_operand" "")
4963 (match_operand:SI 1 "nonimmediate_operand" ""))
4964 (set (match_operand:SI 2 "register_operand" "")
4965 (and:SI (match_dup 0)
4966 (match_operand:SI 3 "const_int_operand" "")))]
4967 ;; Since the size of the memory access could be made different here,
4968 ;; don't do this for a mem-volatile access.
4969 "REGNO (operands[2]) == REGNO (operands[0])
4970 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4971 && !satisfies_constraint_I (operands[3])
4972 && !side_effects_p (operands[1])
4973 && (!REG_P (operands[1])
4974 || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)"
4975 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4976 [(set (match_dup 0) (match_dup 4))
4977 (set (match_dup 5) (match_dup 6))]
4979 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
4980 enum machine_mode amode
4981 = satisfies_constraint_O (operands[3]) ? SImode : zmode;
4983 = (REG_S_P (operands[1])
4984 ? gen_rtx_REG (zmode, REGNO (operands[1]))
4985 : adjust_address (operands[1], zmode, 0));
4987 = gen_rtx_ZERO_EXTEND (SImode, op1);
4988 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
4990 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
4991 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
4993 ? QImode : amode)));
4996 ;; Since r186861, gcc.dg/cris-peep2-andu2.c trigs this pattern, with which
5003 ;; Only do this for values fitting the quick immediate operand.
5004 (define_peephole2 ; andqu (casesi+46)
5005 [(set (match_operand:SI 0 "register_operand")
5006 (match_operand:SI 1 "const_int_operand"))
5008 (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand")))]
5009 ;; Since the size of the memory access will be made different here,
5010 ;; don't do this for a volatile access or a post-incremented address.
5011 "satisfies_constraint_O (operands[1])
5012 && !side_effects_p (operands[2])
5013 && !reg_overlap_mentioned_p (operands[0], operands[2])"
5014 [(set (match_dup 0) (match_dup 3))
5015 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
5017 enum machine_mode zmode = INTVAL (operands[2]) <= 255 ? QImode : HImode;
5019 = (REG_S_P (operands[2])
5020 ? gen_rtx_REG (zmode, REGNO (operands[2]))
5021 : adjust_address (operands[2], zmode, 0));
5022 operands[3] = gen_rtx_ZERO_EXTEND (SImode, op1);
5023 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));
5026 ;; Try and avoid GOTPLT reads escaping a call: transform them into
5027 ;; PLT. Curiously (but thankfully), peepholes for instructions
5028 ;; *without side-effects* that just feed a call (or call_value) are
5029 ;; not matched neither in a build or test-suite, so those patterns are
5032 ;; A "normal" move where we don't check the consumer.
5034 (define_peephole2 ; gotplt-to-plt
5036 (match_operand:SI 0 "register_operand" "")
5040 (reg:SI CRIS_GOT_REGNUM)
5042 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
5043 CRIS_UNSPEC_PLTGOTREAD)))]))]
5045 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5046 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5047 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5048 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5051 ;; And one set with a side-effect getting the PLTGOT offset.
5052 ;; First call and call_value variants.
5054 (define_peephole2 ; gotplt-to-plt-side-call
5057 (match_operand:SI 0 "register_operand" "")
5061 (reg:SI CRIS_GOT_REGNUM)
5063 (unspec:SI [(match_operand:SI
5064 2 "cris_general_operand_or_symbol" "")]
5065 CRIS_UNSPEC_PLTGOTREAD)))]))
5066 (set (match_operand:SI 3 "register_operand" "")
5067 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5069 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5070 (parallel [(call (mem:QI (match_dup 0))
5071 (match_operand 4 "" ""))
5072 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5074 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5075 && peep2_reg_dead_p (2, operands[0])"
5076 [(parallel [(call (mem:QI (match_dup 1))
5078 (clobber (reg:SI CRIS_SRP_REGNUM))
5080 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5082 (unspec:SI [(match_dup 2)]
5083 CRIS_UNSPEC_PLTGOTREAD))))])]
5086 (define_peephole2 ; gotplt-to-plt-side-call-value
5089 (match_operand:SI 0 "register_operand" "")
5093 (reg:SI CRIS_GOT_REGNUM)
5095 (unspec:SI [(match_operand:SI
5096 2 "cris_general_operand_or_symbol" "")]
5097 CRIS_UNSPEC_PLTGOTREAD)))]))
5098 (set (match_operand:SI 3 "register_operand" "")
5099 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5101 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5102 (parallel [(set (match_operand 5 "" "")
5103 (call (mem:QI (match_dup 0))
5104 (match_operand 4 "" "")))
5105 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5107 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5108 && peep2_reg_dead_p (2, operands[0])"
5109 [(parallel [(set (match_dup 5)
5110 (call (mem:QI (match_dup 1))
5112 (clobber (reg:SI CRIS_SRP_REGNUM))
5114 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5116 (unspec:SI [(match_dup 2)]
5117 CRIS_UNSPEC_PLTGOTREAD))))])]
5120 (define_peephole2 ; gotplt-to-plt-side
5123 (match_operand:SI 0 "register_operand" "")
5127 (reg:SI CRIS_GOT_REGNUM)
5129 (unspec:SI [(match_operand:SI
5130 2 "cris_general_operand_or_symbol" "")]
5131 CRIS_UNSPEC_PLTGOTREAD)))]))
5132 (set (match_operand:SI 3 "register_operand" "")
5133 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5135 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5137 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5138 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5140 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
5141 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
5143 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5144 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5149 ;; comment-start: ";; "
5150 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5151 ;; eval: (modify-syntax-entry ?[ "(]")
5152 ;; eval: (modify-syntax-entry ?] ")[")
5153 ;; eval: (modify-syntax-entry ?{ "(}")
5154 ;; eval: (modify-syntax-entry ?} "){")
5155 ;; eval: (setq indent-tabs-mode t)