gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c

   1 /* Test that using a character splat to set up a shift-right logical
   2    for a doubleword vector works correctly after gimple folding.  */
   3
   4 /* { dg-do run { target { p8vector_hw } } } */
   5 /* { dg-options "-O2 -mvsx" } */
   6 /* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */
   7
   8 #include <altivec.h>
   9
  10 typedef __vector unsigned long long vui64_t;
  11
  12 static inline vui64_t
  13 vec_srdi (vui64_t vra, const unsigned int shb)
  14 {
  15   vui64_t rshift;
  16   vui64_t result;
  17
  18   /* Note legitimate use of wrong-type splat due to expectation that only
  19      lower 6-bits are read.  */
  20   rshift = (vui64_t) vec_splat_s8 (shb);
  21
  22   /* Vector Shift Right [Logical] Doublewords based on the lower 6-bits
  23      of corresponding element of rshift.  */
  24   result = vec_vsrd (vra, rshift);
  25
  26   return result;
  27 }
  28
  29 __attribute__ ((noinline)) vui64_t
  30 test_srdi_4 (vui64_t a)
  31 {
  32   return vec_srdi (a, 4);
  33 }
  34
  35 int
  36 main ()
  37 {
  38   vui64_t x = {1992357, 1025};
  39   x = test_srdi_4 (x);
  40   if (x[0] != 124522 || x[1] != 64)
  41     __builtin_abort ();
  42   return 0;
  43 }