gcc/testsuite/gcc.target/powerpc/pr71656-1.c

   1 /* Test for reload ICE arising from POWER9 Vector Dform code generation.  */
   2 /* { dg-do compile } */
   3 /* { dg-require-effective-target powerpc_vsx_ok } */
   4 /* { dg-options "-O1 -mvsx" } */
   5 /* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */
   6
   7 typedef __attribute__((altivec(vector__))) int type_t;
   8 type_t
   9 func (type_t *src)
  10 {
  11   asm volatile ("# force the base reg on the load below to be spilled"
  12                    : /* no outputs */
  13                    : /* no inputs */
  14                    : "r0", "r3", "r4", "r5", "r6", "r7",
  15                      "r8", "r9", "r10", "r11", "r12", "r14", "r15",
  16                      "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  17                      "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
  18   return src[1];
  19 }
  20