1 /* Verify that overloaded built-ins for vec_sl produce the right results. */
2 /* This test covers the shift left tests with the -fwrapv option. */
4 /* { dg-do compile } */
5 /* { dg-require-effective-target powerpc_vsx_ok } */
6 /* { dg-options "-mvsx -O2 -fwrapv" } */
7 /* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */
11 vector
signed long long
12 testsl_signed_longlong (vector
signed long long x
, vector
unsigned long long y
)
17 vector
unsigned long long
18 testsl_unsigned_longlong (vector
unsigned long long x
, vector
unsigned long long y
)
23 /* { dg-final { scan-assembler-times "vsld" 2 } } */