| blob | 473ffc4a1321a610c8de7e77858d6badd9894b65 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 machine_mode,
422 machine_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1218 }
1219 }
1223 /* Now scan all the insns in forward order. */
1231 {
1237 label_tick++;
1247 {
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1267 into SUBREGs. */
1270 /* Try this insn with each insn it links back to. */
1276 {
1279 }
1281 /* Try each sequence of three linked insns ending with this one. */
1285 {
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1297 {
1300 }
1301 }
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1315 {
1326 }
1328 /* Do the same for an insn that explicitly references CC0. */
1335 {
1346 }
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1352 {
1364 }
1366 /* Try combining an insn with two different insns whose results it
1367 uses. */
1377 {
1380 }
1382 /* Try four-instruction combinations. */
1385 {
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1395 {
1399 /* I0 -> I1 -> I2 -> I3. */
1405 {
1408 }
1409 /* I0, I1 -> I2, I2 -> I3. */
1416 {
1419 }
1420 }
1423 {
1427 /* I0 -> I2; I1, I2 -> I3. */
1433 {
1436 }
1437 /* I0 -> I1; I1, I2 -> I3. */
1443 {
1446 }
1447 }
1448 }
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1452 {
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1467 {
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1481 last_combined_insn);
1484 {
1487 }
1490 }
1491 }
1496 retry:
1497 ;
1498 }
1499 }
1506 /* Clean up. */
1512 {
1515 {
1518 }
1520 }
1530 /* Make recognizer allow volatile MEMs again. */
1534 }
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1538 static void
1540 {
1546 }
1547 \f
1548 /* Set up any promoted values for incoming argument registers. */
1550 static void
1552 {
1553 tree arg;
1558 {
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1588 /* The mode of the register in which the argument is being passed. */
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1601 ;
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1623 }
1624 }
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1632 kludge. */
1634 static rtx
1636 {
1644 }
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1647 and SET. */
1649 static void
1651 rtx x)
1652 {
1662 {
1666 }
1668 /* Don't call nonzero_bits if it cannot change anything. */
1670 {
1675 }
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1679 {
1682 {
1686 }
1689 }
1690 }
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1697 be happening.
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1701 by any set of X. */
1703 static void
1705 {
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1715 {
1719 {
1723 }
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1742 {
1749 {
1753 }
1754 }
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1767 else
1768 {
1771 }
1772 }
1773 }
1774 \f
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1784 will return 1. */
1786 static int
1790 {
1795 rtx link;
1800 {
1802 {
1807 }
1812 }
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1826 note.
1828 Get the source and destination of INSN. If more than one, can't
1829 combine. */
1835 {
1837 {
1841 {
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1850 I3 and INSN.
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1860 {
1865 do
1866 {
1876 }
1878 }
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1904 }
1905 }
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1912 }
1913 else
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1935 /* Don't eliminate a store in the stack pointer. */
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1940 /* Can't merge an ASM_OPERANDS. */
1942 /* Can't merge a function call. */
1944 /* Don't eliminate a function call argument. */
1950 /* Don't substitute into an incremented register. */
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1957 || (!all_adjacent
1958 && ((succ2
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1971 || (! all_adjacent
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1985 /* DEST must either be a REG or CC0. */
1987 {
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1995 register. */
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2003 is going on).
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2006 inputs. */
2010 }
2018 {
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2033 }
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2039 {
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2045 /* We'll check insns between INSN and I3 below. */
2046 }
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2061 ? volatile_refs_p
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2100 {
2105 }
2107 /* If we get here, we have passed all the tests and the combination is
2108 to be allowed. */
2114 }
2115 \f
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2123 Consider:
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2154 static int
2157 {
2161 {
2166 rtx subdest;
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2189 INNER_DEST.
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2226 {
2231 }
2232 }
2235 {
2242 }
2245 }
2246 \f
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2250 static int
2252 {
2254 {
2270 }
2271 }
2272 \f
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2277 static int
2279 {
2280 rtx set;
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2315 }
2317 struct likely_spilled_retval_info
2318 {
2321 };
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2325 static void
2327 {
2344 else
2347 }
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2354 static int
2356 {
2358 rtx reg;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2378 /* Disregard parts of the return value that are set later. */
2387 /* Check if any of the (probably) live return value registers is
2388 likely spilled. */
2389 nregs --;
2390 do
2391 {
2397 }
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2404 static void
2406 {
2407 /* For notes, be conservative and simply remove them. */
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2428 }
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2432 static bool
2434 {
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2447 /* Or a pseudo that is only used once. */
2450 && !added_sets
2452 }
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2458 static bool
2460 {
2461 /* Check that reg is an integer mode register. */
2472 }
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2479 static void
2481 {
2489 {
2494 /* Remove barriers from the footer if there are any. */
2497 {
2500 else
2504 }
2507 }
2508 }
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2512 static bool
2514 {
2533 }
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2538 static bool
2540 {
2548 {
2557 }
2560 }
2562 /* Try to combine the insns I0, I1 and I2 into I3.
2563 Here I0, I1 and I2 appear earlier than I3.
2564 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2565 I3.
2567 If we are combining more than two insns and the resulting insn is not
2568 recognized, try splitting it into two insns. If that happens, I2 and I3
2569 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2570 Otherwise, I0, I1 and I2 are pseudo-deleted.
2572 Return 0 if the combination does not work. Then nothing is changed.
2573 If we did the combination, return the insn at which combine should
2574 resume scanning.
2576 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2577 new direct jump instruction.
2579 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2580 been I3 passed to an earlier try_combine within the same basic
2581 block. */
2586 {
2587 /* New patterns for I3 and I2, respectively. */
2591 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2592 dead. */
2594 /* Total number of SETs to put into I3. */
2596 /* Nonzero if I2's or I1's body now appears in I3. */
2598 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2600 /* Contains I3 if the destination of I3 is used in its source, which means
2601 that the old life of I3 is being killed. If that usage is placed into
2602 I2 and not in I3, a REG_DEAD note must be made. */
2604 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2606 /* Copy of SET_SRC of I1 and I0, if needed. */
2608 /* Set if I2DEST was reused as a scratch register. */
2610 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2612 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2617 /* Notes that must be added to REG_NOTES in I3 and I2. */
2619 /* Notes that we substituted I3 into I2 instead of the normal case. */
2621 /* Notes that I1, I2 or I3 is a MULT operation. */
2628 rtx temp_expr;
2631 rtx new_other_notes;
2634 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2635 never be). */
2639 /* Only try four-insn combinations when there's high likelihood of
2640 success. Look for simple insns, such as loads of constants or
2641 binary operations involving a constant. */
2643 {
2653 {
2656 rtx src;
2661 {
2664 }
2666 ngood++;
2669 nshift++;
2670 }
2672 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2673 are likely manipulating its value. Ideally we'll be able to combine
2674 all four insns into a bitfield insertion of some kind.
2676 Note the source in I0 might be inside a sign/zero extension and the
2677 memory modes in I0 and I3 might be different. So extract the address
2678 from the destination of I3 and search for it in the source of I0.
2680 In the event that there's a match but the source/dest do not actually
2681 refer to the same memory, the worst that happens is we try some
2682 combinations that we wouldn't have otherwise. */
2684 /* Ensure the source of SET0 is a MEM, possibly buried inside
2685 an extension. */
2691 /* Ensure the destination of SET3 is a MEM. */
2693 /* Would it be better to extract the base address for the MEM
2694 in SET3 and look for that? I don't have cases where it matters
2695 but I could envision such cases. */
2701 }
2703 /* Exit early if one of the insns involved can't be used for
2704 combinations. */
2715 combine_attempts++;
2718 /* Reset the hard register usage information. */
2722 {
2729 else
2732 }
2734 /* If multiple insns feed into one of I2 or I3, they can be in any
2735 order. To simplify the code below, reorder them in sequence. */
2745 /* First check for one important special case that the code below will
2746 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2747 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2748 we may be able to replace that destination with the destination of I3.
2749 This occurs in the common code where we compute both a quotient and
2750 remainder into a structure, in which case we want to do the computation
2751 directly into the structure to avoid register-register copies.
2753 Note that this case handles both multiple sets in I2 and also cases
2754 where I2 has a number of CLOBBERs inside the PARALLEL.
2756 We make very conservative checks below and only try to handle the
2757 most common cases of this. For example, we only handle the case
2758 where I2 and I3 are adjacent to avoid making difficult register
2759 usage tests. */
2767 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2768 below would need to check what is inside (and reg_overlap_mentioned_p
2769 doesn't support those codes anyway). Don't allow those destinations;
2770 the resulting insn isn't likely to be recognized anyway. */
2776 {
2779 /* Make sure that the destination of I3,
2780 which we are going to substitute into one output of I2,
2781 is not used within another output of I2. We must avoid making this:
2782 (parallel [(set (mem (reg 69)) ...)
2783 (set (reg 69) ...)])
2784 which is not well-defined as to order of actions.
2785 (Besides, reload can't handle output reloads for this.)
2787 The problem can also happen if the dest of I3 is a memory ref,
2788 if another dest in I2 is an indirect memory ref. */
2796 /* Make sure this PARALLEL is not an asm. We do not allow combining
2797 that usually (see can_combine_p), so do not here either. */
2807 {
2808 combine_merges++;
2818 /* Replace the dest in I2 with our dest and make the resulting
2819 insn the new pattern for I3. Then skip to where we validate
2820 the pattern. Everything was set up above. */
2825 }
2826 }
2828 /* If I2 is setting a pseudo to a constant and I3 is setting some
2829 sub-part of it to another constant, merge them by making a new
2830 constant. */
2837 {
2843 {
2846 {
2852 }
2853 }
2854 else
2855 {
2860 }
2863 {
2864 /* If this is the low part, we're done. */
2866 ;
2867 /* Handle the case where inner is twice the size of outer. */
2871 /* Otherwise give up for now. */
2872 else
2874 }
2877 {
2881 wide_int o
2886 combine_merges++;
2893 /* Replace the source in I2 with the new constant and make the
2894 resulting insn the new pattern for I3. Then skip to where we
2895 validate the pattern. Everything was set up above. */
2901 /* The dest of I3 has been replaced with the dest of I2. */
2904 }
2905 }
2907 /* If we have no I1 and I2 looks like:
2908 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2909 (set Y OP)])
2910 make up a dummy I1 that is
2911 (set Y OP)
2912 and change I2 to be
2913 (set (reg:CC X) (compare:CC Y (const_int 0)))
2915 (We can ignore any trailing CLOBBERs.)
2917 This undoes a previous combination and allows us to match a branch-and-
2918 decrement insn. */
2930 {
2931 /* We make I1 with the same INSN_UID as I2. This gives it
2932 the same DF_INSN_LUID for value tracking. Our fake I1 will
2933 never appear in the insn stream so giving it the same INSN_UID
2934 as I2 will not cause a problem. */
2947 }
2949 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2950 make those two SETs separate I1 and I2 insns, and make an I0 that is
2951 the original I1. */
2957 {
2958 /* If there is no I1, there is no I0 either. */
2961 /* We make I1 with the same INSN_UID as I2. This gives it
2962 the same DF_INSN_LUID for value tracking. Our fake I1 will
2963 never appear in the insn stream so giving it the same INSN_UID
2964 as I2 will not cause a problem. */
2972 }
2974 /* Verify that I2 and I1 are valid for combining. */
2980 {
2983 }
2985 /* Record whether I2DEST is used in I2SRC and similarly for the other
2986 cases. Knowing this will help in register status updating below. */
2997 /* For the earlier insns, determine which of the subsequent ones they
2998 feed. */
3005 /* Ensure that I3's pattern can be the destination of combines. */
3011 {
3014 }
3016 /* See if any of the insns is a MULT operation. Unless one is, we will
3017 reject a combination that is, since it must be slower. Be conservative
3018 here. */
3026 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3027 We used to do this EXCEPT in one case: I3 has a post-inc in an
3028 output operand. However, that exception can give rise to insns like
3029 mov r3,(r3)+
3030 which is a famous insn on the PDP-11 where the value of r3 used as the
3031 source was model-dependent. Avoid this sort of thing. */
3033 #if 0
3039 /* It's not the exception. */
3040 #endif
3042 {
3043 rtx link;
3049 {
3052 }
3053 }
3055 /* See if the SETs in I1 or I2 need to be kept around in the merged
3056 instruction: whenever the value set there is still needed past I3.
3057 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3059 For the SET in I1, we have two cases: if I1 and I2 independently feed
3060 into I3, the set in I1 needs to be kept around unless I1DEST dies
3061 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3062 in I1 needs to be kept around unless I1DEST dies or is set in either
3063 I2 or I3. The same considerations apply to I0. */
3070 else
3078 else
3081 /* We are about to copy insns for the case where they need to be kept
3082 around. Check that they can be copied in the merged instruction. */
3088 {
3091 }
3093 /* If the set in I2 needs to be kept around, we must make a copy of
3094 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3095 PATTERN (I2), we are only substituting for the original I1DEST, not into
3096 an already-substituted copy. This also prevents making self-referential
3097 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3098 I2DEST. */
3101 {
3104 else
3106 }
3109 {
3112 else
3114 }
3117 {
3120 else
3122 }
3124 combine_merges++;
3126 /* Substitute in the latest insn for the regs set by the earlier ones. */
3132 /* Many machines that don't use CC0 have insns that can both perform an
3133 arithmetic operation and set the condition code. These operations will
3134 be represented as a PARALLEL with the first element of the vector
3135 being a COMPARE of an arithmetic operation with the constant zero.
3136 The second element of the vector will set some pseudo to the result
3137 of the same arithmetic operation. If we simplify the COMPARE, we won't
3138 match such a pattern and so will generate an extra insn. Here we test
3139 for this case, where both the comparison and the operation result are
3140 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3141 I2SRC. Later we will make the PARALLEL that contains I2. */
3147 {
3148 rtx newpat_dest;
3162 {
3167 }
3169 /* Do the rest only if op1 is const0_rtx, which may be the
3170 result of simplification. */
3172 {
3173 /* If a single use of the CC is found, prepare to modify it
3174 when SELECT_CC_MODE returns a new CC-class mode, or when
3175 the above simplify_compare_const() returned a new comparison
3176 operator. undobuf.other_insn is assigned the CC use insn
3177 when modifying it. */
3179 {
3180 #ifdef SELECT_CC_MODE
3181 machine_mode new_mode
3186 {
3191 else
3192 {
3195 }
3196 }
3197 #endif
3198 /* Cases for modifying the CC-using comparison. */
3200 /* ??? Do we need to verify the zero rtx? */
3202 {
3203 /* Replace cc_use_loc with entire new RTX. */
3208 }
3210 {
3211 /* Just replace the CC reg with a new mode. */
3214 }
3215 }
3217 /* Now we modify the current newpat:
3218 First, SET_DEST(newpat) is updated if the CC mode has been
3219 altered. For targets without SELECT_CC_MODE, this should be
3220 optimized away. */
3223 /* This is always done to propagate i2src into newpat. */
3226 /* Create new version of i2pat if needed; the below PARALLEL
3227 creation needs this to work correctly. */
3231 }
3232 }
3235 {
3236 /* It is possible that the source of I2 or I1 may be performing
3237 an unneeded operation, such as a ZERO_EXTEND of something
3238 that is known to have the high part zero. Handle that case
3239 by letting subst look at the inner insns.
3241 Another way to do this would be to have a function that tries
3242 to simplify a single insn instead of merging two or more
3243 insns. We don't do this because of the potential of infinite
3244 loops and because of the potential extra memory required.
3245 However, doing it the way we are is a bit of a kludge and
3246 doesn't catch all cases.
3248 But only do this if -fexpensive-optimizations since it slows
3249 things down and doesn't usually win.
3251 This is not done in the COMPARE case above because the
3252 unmodified I2PAT is used in the PARALLEL and so a pattern
3253 with a modified I2SRC would not match. */
3256 {
3257 /* Pass pc_rtx so no substitutions are done, just
3258 simplifications. */
3260 {
3263 }
3267 }
3272 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3273 copy of I2SRC each time we substitute it, in order to avoid creating
3274 self-referential RTL when we will be substituting I1SRC for I1DEST
3275 later. Likewise if I0 feeds into I2, either directly or indirectly
3276 through I1, and I0DEST is in I0SRC. */
3283 /* Record whether I2's body now appears within I3's body. */
3285 }
3287 /* If we already got a failure, don't try to do more. Otherwise, try to
3288 substitute I1 if we have it. */
3291 {
3292 /* Check that an autoincrement side-effect on I1 has not been lost.
3293 This happens if I1DEST is mentioned in I2 and dies there, and
3294 has disappeared from the new pattern. */
3296 && i1_feeds_i2_n
3299 /* Before we can do this substitution, we must redo the test done
3300 above (see detailed comments there) that ensures I1DEST isn't
3301 mentioned in any SETs in NEWPAT that are field assignments. */
3304 {
3307 }
3312 /* If the following substitution will modify I1SRC, make a copy of it
3313 for the case where it is substituted for I1DEST in I2PAT later. */
3317 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3318 copy of I1SRC each time we substitute it, in order to avoid creating
3319 self-referential RTL when we will be substituting I0SRC for I0DEST
3320 later. */
3325 /* Record whether I1's body now appears within I3's body. */
3327 }
3329 /* Likewise for I0 if we have it. */
3332 {
3339 {
3342 }
3344 /* If the following substitution will modify I0SRC, make a copy of it
3345 for the case where it is substituted for I0DEST in I1PAT later. */
3348 /* And a copy for I0DEST in I2PAT substitution. */
3357 }
3359 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3360 to count all the ways that I2SRC and I1SRC can be used. */
3371 /* Fail if we tried to make a new register. */
3373 /* Fail if we couldn't do something and have a CLOBBER. */
3375 /* Fail if this new pattern is a MULT and we didn't have one before
3376 at the outer level. */
3379 {
3382 }
3384 /* If the actions of the earlier insns must be kept
3385 in addition to substituting them into the latest one,
3386 we must make a new PARALLEL for the latest insn
3387 to hold additional the SETs. */
3390 {
3392 combine_extras++;
3395 {
3401 }
3402 else
3403 {
3408 }
3414 {
3420 }
3422 {
3431 }
3432 }
3434 validate_replacement:
3436 /* Note which hard regs this insn has as inputs. */
3439 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3440 consider splitting this pattern, we might need these clobbers. */
3443 {
3449 }
3451 /* We have recognized nothing yet. */
3454 /* See if this is a PARALLEL of two SETs where one SET's destination is
3455 a register that is unused and this isn't marked as an instruction that
3456 might trap in an EH region. In that case, we just need the other SET.
3457 We prefer this over the PARALLEL.
3459 This can occur when simplifying a divmod insn. We *must* test for this
3460 case here because the code below that splits two independent SETs doesn't
3461 handle this case correctly when it updates the register status.
3463 It's pointless doing this if we originally had two sets, one from
3464 i3, and one from i2. Combining then splitting the parallel results
3465 in the original i2 again plus an invalid insn (which we delete).
3466 The net effect is only to move instructions around, which makes
3467 debug info less accurate. */
3472 {
3483 {
3486 }
3495 {
3501 }
3505 }
3507 /* Is the result of combination a valid instruction? */
3511 /* If we were combining three insns and the result is a simple SET
3512 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3513 insns. There are two ways to do this. It can be split using a
3514 machine-specific method (like when you have an addition of a large
3515 constant) or by combine in the function find_split_point. */
3519 {
3523 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3524 use I2DEST as a scratch register will help. In the latter case,
3525 convert I2DEST to the mode of the source of NEWPAT if we can. */
3529 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3530 inputs of NEWPAT. */
3532 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3533 possible to try that as a scratch reg. This would require adding
3534 more code to make it work though. */
3537 {
3540 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3541 (temporarily, until we are committed to this instruction
3542 combination) does not work: for example, any call to nonzero_bits
3543 on the register (from a splitter in the MD file, for example)
3544 will get the old information, which is invalid.
3546 Since nowadays we can create registers during combine just fine,
3547 we should just create a new one here, not reuse i2dest. */
3549 /* First try to split using the original register as a
3550 scratch register. */
3554 i2dest)));
3557 /* If that didn't work, try changing the mode of I2DEST if
3558 we can. */
3563 {
3565 rtx ni2dest;
3569 else
3570 {
3573 }
3575 parallel = (gen_rtx_PARALLEL
3579 ni2dest))));
3584 {
3592 }
3593 }
3596 }
3598 /* If recog_for_combine has discarded clobbers, try to use them
3599 again for the split. */
3601 {
3604 }
3607 {
3612 }
3616 {
3626 /* If I2 or I3 has multiple SETs, we won't know how to track
3627 register status, so don't use these insns. If I2's destination
3628 is used between I2 and I3, we also can't use these insns. */
3638 /* It is possible that both insns now set the destination of I3.
3639 If so, we must show an extra use of it. */
3642 {
3661 }
3662 }
3664 /* If we can split it and use I2DEST, go ahead and see if that
3665 helps things be recognized. Verify that none of the registers
3666 are set between I2 and I3. */
3670 /* We need I2DEST in the proper mode. If it is a hard register
3671 or the only use of a pseudo, we can change its mode.
3672 Make sure we don't change a hard register to have a mode that
3673 isn't valid for it, or change the number of registers. */
3680 /* We can't overwrite I2DEST if its value is still used by
3681 NEWPAT. */
3683 {
3692 /* *SPLIT may be part of I2SRC, so make sure we have the
3693 original expression around for later debug processing.
3694 We should not need I2SRC any more in other cases. */
3697 else
3700 /* Get NEWDEST as a register in the proper mode. We have already
3701 validated that we can do this. */
3703 {
3706 else
3707 {
3710 }
3711 }
3713 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3714 an ASHIFT. This can occur if it was inside a PLUS and hence
3715 appeared to be a memory address. This is a kludge. */
3720 {
3723 /* Update split_code because we may not have a multiply
3724 anymore. */
3726 }
3728 /* Similarly for (plus (mult FOO (const_int pow2))). */
3734 {
3738 /* Update split_code because we may not have a multiply
3739 anymore. */
3741 }
3743 #ifdef INSN_SCHEDULING
3744 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3745 be written as a ZERO_EXTEND. */
3747 {
3748 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3749 what it really is. */
3754 else
3757 }
3758 #endif
3760 /* Attempt to split binary operators using arithmetic identities. */
3764 {
3771 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3773 {
3778 }
3779 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3786 {
3792 /* Split both "((X op Y) op X) op Y" and
3793 "((X op Y) op Y) op X" as "T op T" where T is
3794 "X op Y". */
3797 {
3802 }
3803 /* Split "((X op X) op Y) op Y)" as "T op T" where
3804 T is "X op Y". */
3806 {
3812 }
3813 }
3814 }
3817 {
3820 }
3824 /* recog_for_combine might have added CLOBBERs to newi2pat.
3825 Make sure NEWPAT does not depend on the clobbered regs. */
3829 {
3832 {
3835 }
3836 }
3838 /* If the split point was a MULT and we didn't have one before,
3839 don't use one now. */
3842 }
3843 }
3845 /* Check for a case where we loaded from memory in a narrow mode and
3846 then sign extended it, but we need both registers. In that case,
3847 we have a PARALLEL with both loads from the same memory location.
3848 We can split this into a load from memory followed by a register-register
3849 copy. This saves at least one insn, more if register allocation can
3850 eliminate the copy.
3852 We cannot do this if the destination of the first assignment is a
3853 condition code register or cc0. We eliminate this case by making sure
3854 the SET_DEST and SET_SRC have the same mode.
3856 We cannot do this if the destination of the second assignment is
3857 a register that we have already assumed is zero-extended. Similarly
3858 for a SUBREG of such a register. */
3893 {
3894 rtx ni2dest;
3908 }
3910 /* Similarly, check for a case where we have a PARALLEL of two independent
3911 SETs but we started with three insns. In this case, we can do the sets
3912 as two separate insns. This case occurs when some SET allows two
3913 other insns to combine, but the destination of that SET is still live.
3915 Also do this if we started with two insns and (at least) one of the
3916 resulting sets is a noop; this noop will be deleted later. */
3935 {
3939 /* Normally, it doesn't matter which of the two is done first,
3940 but the one that references cc0 can't be the second, and
3941 one which uses any regs/memory set in between i2 and i3 can't
3942 be first. The PARALLEL might also have been pre-existing in i3,
3943 so we need to make sure that we won't wrongly hoist a SET to i2
3944 that would conflict with a death note present in there. */
3952 /* If I3 is a jump, ensure that set0 is a jump so that
3953 we do not create invalid RTL. */
3955 )
3956 {
3959 }
3967 /* If I3 is a jump, ensure that set1 is a jump so that
3968 we do not create invalid RTL. */
3970 )
3971 {
3974 }
3975 else
3976 {
3979 }
3984 {
3985 /* recog_for_combine might have added CLOBBERs to newi2pat.
3986 Make sure NEWPAT does not depend on the clobbered regs. */
3988 {
3991 {
3994 {
3997 }
3998 }
3999 }
4002 }
4003 }
4005 /* If it still isn't recognized, fail and change things back the way they
4006 were. */
4008 /* Is the result a reasonable ASM_OPERANDS? */
4010 {
4013 }
4015 /* If we had to change another insn, make sure it is valid also. */
4017 {
4025 {
4028 }
4029 }
4031 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4032 they are adjacent to each other or not. */
4034 {
4038 {
4041 }
4042 }
4044 /* Only allow this combination if insn_rtx_costs reports that the
4045 replacement instructions are cheaper than the originals. */
4047 {
4050 }
4053 {
4058 {
4063 /* Temporarily revert mode back. */
4067 {
4068 /* If we used i2dest as a scratch register with a
4069 different mode, substitute it for the original
4070 i2src while its original mode is temporarily
4071 restored, and then clear i2scratch so that we don't
4072 do it again later. */
4074 this_basic_block);
4076 /* Put back the new mode. */
4078 }
4079 else
4080 {
4085 {
4088 }
4089 else
4090 {
4097 }
4099 /* We're dealing with a reg that changed mode but not
4100 meaning, so we want to turn it into a subreg for
4101 the new mode. However, because of REG sharing and
4102 because its mode had already changed, we have to do
4103 it in two steps. First, replace any debug uses of
4104 reg, with its original mode temporarily restored,
4105 with this copy we have created; then, replace the
4106 copy with the SUBREG of the original shared reg,
4107 once again changed to the new mode. */
4109 this_basic_block);
4113 this_basic_block);
4114 }
4115 }
4116 }
4118 /* If we will be able to accept this, we have made a
4119 change to the destination of I3. This requires us to
4120 do a few adjustments. */
4123 {
4126 }
4128 /* We now know that we can do this combination. Merge the insns and
4129 update the status of registers and LOG_LINKS. */
4132 {
4137 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4138 ensure that they are still valid. Then add any non-duplicate
4139 notes added by recog_for_combine. */
4141 {
4151 }
4155 NULL_RTX);
4156 }
4159 {
4162 rtx ni2dest;
4164 /* I3 now uses what used to be its destination and which is now
4165 I2's destination. This requires us to do a few adjustments. */
4169 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4170 so we still will.
4172 However, some later insn might be using I2's dest and have
4173 a LOG_LINK pointing at I3. We must remove this link.
4174 The simplest way to remove the link is to point it at I1,
4175 which we know will be a NOTE. */
4177 /* newi2pat is usually a SET here; however, recog_for_combine might
4178 have added some clobbers. */
4181 else
4188 {
4191 {
4197 }
4198 }
4199 }
4201 {
4206 /* Compute which registers we expect to eliminate. newi2pat may be setting
4207 either i3dest or i2dest, so we must check it. */
4210 || !i2dest_killed
4212 /* For i1, we need to compute both local elimination and global
4213 elimination information with respect to newi2pat because i1dest
4214 may be the same as i3dest, in which case newi2pat may be setting
4215 i1dest. Global information is used when distributing REG_DEAD
4216 note for i2 and i3, in which case it does matter if newi2pat sets
4217 i1dest or not.
4219 Local information is used when distributing REG_DEAD note for i1,
4220 in which case it doesn't matter if newi2pat sets i1dest or not.
4221 See PR62151, if we have four insns combination:
4222 i0: r0 <- i0src
4223 i1: r1 <- i1src (using r0)
4224 REG_DEAD (r0)
4225 i2: r0 <- i2src (using r1)
4226 i3: r3 <- i3src (using r0)
4227 ix: using r0
4228 From i1's point of view, r0 is eliminated, no matter if it is set
4229 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4230 should be discarded.
4232 Note local information only affects cases in forms like "I1->I2->I3",
4233 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4234 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4235 i0dest anyway. */
4237 || !i1dest_killed
4242 /* Same case as i1. */
4249 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4250 clear them. */
4258 /* Ensure that we do not have something that should not be shared but
4259 occurs multiple times in the new insns. Check this by first
4260 resetting all the `used' flags and then copying anything is shared. */
4284 {
4291 {
4292 /* I2SRC must still be meaningful at this point. Some splitting
4293 operations can invalidate I2SRC, but those operations do not
4294 apply to calls. */
4297 }
4305 }
4310 /* We had one special case above where I2 had more than one set and
4311 we replaced a destination of one of those sets with the destination
4312 of I3. In that case, we have to update LOG_LINKS of insns later
4313 in this basic block. Note that this (expensive) case is rare.
4315 Also, in this case, we must pretend that all REG_NOTEs for I2
4316 actually came from I3, so that REG_UNUSED notes from I2 will be
4317 properly handled. */
4320 {
4329 temp_insn
4339 {
4344 }
4345 else
4348 }
4356 {
4359 this_basic_block);
4362 }
4363 else
4364 {
4367 this_basic_block);
4369 }
4372 {
4377 this_basic_block);
4379 }
4382 {
4387 this_basic_block);
4389 }
4391 /* Get death notes for everything that is now used in either I3 or
4392 I2 and used to die in a previous insn. If we built two new
4393 patterns, move from I1 to I2 then I2 to I3 so that we get the
4394 proper movement on registers that I2 modifies. */
4400 else
4406 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4423 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4424 know these are REG_UNUSED and want them to go to the desired insn,
4425 so we always pass it as i3. */
4429 NULL_RTX);
4433 NULL_RTX);
4435 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4436 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4437 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4438 in that case, it might delete I2. Similarly for I2 and I1.
4439 Show an additional death due to the REG_DEAD note we make here. If
4440 we discard it in distribute_notes, we will decrement it again. */
4443 {
4448 else
4451 }
4454 {
4459 else
4462 }
4465 {
4470 else
4473 }
4476 {
4481 else
4484 }
4492 {
4497 /* The insn that used to set this register doesn't exist, and
4498 this life of the register may not exist either. See if one of
4499 I3's links points to an insn that sets I2DEST. If it does,
4500 that is now the last known value for I2DEST. If we don't update
4501 this and I2 set the register to a value that depended on its old
4502 contents, we will get confused. If this insn is used, thing
4503 will be set correctly in combine_instructions. */
4511 /* If the reg formerly set in I2 died only once and that was in I3,
4512 zero its use count so it won't make `reload' do any work. */
4515 && ! i2dest_in_i2src
4518 }
4521 {
4534 && ! i1dest_in_i1src
4537 }
4540 {
4553 && ! i0dest_in_i0src
4556 }
4558 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4559 been made to this insn. The order is important, because newi2pat
4560 can affect nonzero_bits of newpat. */
4564 }
4567 {
4569 {
4572 }
4574 }
4577 {
4579 {
4582 }
4584 }
4587 {
4589 {
4592 }
4594 }
4597 {
4599 {
4602 }
4604 }
4607 {
4609 {
4612 }
4614 }
4616 /* Set new_direct_jump_p if a new return or simple jump instruction
4617 has been created. Adjust the CFG accordingly. */
4619 {
4623 }
4628 {
4631 }
4635 {
4641 }
4646 {
4652 }
4654 /* A noop might also need cleaning up of CFG, if it comes from the
4655 simplification of a jump. */
4660 {
4663 }
4670 {
4673 }
4675 combine_successes++;
4682 else
4684 }
4685 \f
4686 /* Get a marker for undoing to the current state. */
4690 {
4692 }
4694 /* Undo the modifications up to the marker. */
4696 static void
4698 {
4702 {
4707 {
4722 }
4726 }
4729 }
4731 /* Undo all the modifications recorded in undobuf. */
4733 static void
4735 {
4737 }
4739 /* We've committed to accepting the changes we made. Move all
4740 of the undos to the free list. */
4742 static void
4744 {
4748 {
4752 }
4754 }
4755 \f
4756 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4757 where we have an arithmetic expression and return that point. LOC will
4758 be inside INSN.
4760 try_combine will call this function to see if an insn can be split into
4761 two insns. */
4765 {
4774 /* First special-case some codes. */
4776 {
4778 #ifdef INSN_SCHEDULING
4779 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4780 point. */
4783 #endif
4787 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4788 using LO_SUM and HIGH. */
4791 {
4799 }
4801 /* If we have a PLUS whose second operand is a constant and the
4802 address is not valid, perhaps will can split it up using
4803 the machine-specific way to split large constants. We use
4804 the first pseudo-reg (one of the virtual regs) as a placeholder;
4805 it will not remain in the result. */
4810 {
4813 subst_insn);
4815 /* This should have produced two insns, each of which sets our
4816 placeholder. If the source of the second is a valid address,
4817 we can make put both sources together and make a split point
4818 in the middle. */
4831 && memory_address_addr_space_p
4834 {
4838 /* Replace the placeholder in SRC2 with SRC1. If we can
4839 find where in SRC2 it was placed, that can become our
4840 split point and we can replace this address with SRC2.
4841 Just try two obvious places. */
4852 {
4855 }
4856 }
4858 /* If that didn't work, perhaps the first operand is complex and
4859 needs to be computed separately, so make a split point there.
4860 This will occur on machines that just support REG + CONST
4861 and have a constant moved through some previous computation. */
4867 }
4869 /* If we have a PLUS whose first operand is complex, try computing it
4870 separately by making a split there. */
4881 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4882 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4883 we need to put the operand into a register. So split at that
4884 point. */
4894 /* See if we can split SET_SRC as it stands. */
4899 /* See if we can split SET_DEST as it stands. */
4904 /* See if this is a bitfield assignment with everything constant. If
4905 so, this is an IOR of an AND, so split it into that. */
4915 {
4921 unsigned HOST_WIDE_INT mask
4923 rtx or_mask;
4932 else
4933 {
4939 or_mask));
4940 }
4947 }
4949 /* Otherwise, see if this is an operation that we can split into two.
4950 If so, try to split that. */
4954 {
4956 /* If we are AND'ing with a large constant that is only a single
4957 bit and the result is only being used in a context where we
4958 need to know if it is zero or nonzero, replace it with a bit
4959 extraction. This will avoid the large constant, which might
4960 have taken more than one insn to make. If the constant were
4961 not a valid argument to the AND but took only one insn to make,
4962 this is no worse, but if it took more than one insn, it will
4963 be better. */
4973 {
4978 {
4981 }
4982 }
4986 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4987 is known to be on, this can be converted into a NEG of a shift. */
4993 {
5005 }
5011 /* We can't optimize if either mode is a partial integer
5012 mode as we don't know how many bits are significant
5013 in those modes. */
5027 {
5035 }
5040 }
5044 {
5047 /* For unsigned, we have a choice of a shift followed by an
5048 AND or two shifts. Use two shifts for field sizes where the
5049 constant might be too large. We assume here that we can
5050 always at least get 8-bit constants in an AND insn, which is
5051 true for every current RISC. */
5054 {
5055 unsigned HOST_WIDE_INT mask
5059 gen_rtx_LSHIFTRT
5067 }
5068 else
5069 {
5071 gen_rtx_fmt_ee
5082 }
5083 }
5085 /* See if this is a simple operation with a constant as the second
5086 operand. It might be that this constant is out of range and hence
5087 could be used as a split point. */
5095 /* Finally, see if this is a simple operation with its first operand
5096 not in a register. The operation might require this operand in a
5097 register, so return it as a split point. We can always do this
5098 because if the first operand were another operation, we would have
5099 already found it as a split point. */
5108 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5109 it is better to write this as (not (ior A B)) so we can split it.
5110 Similarly for IOR. */
5112 {
5120 }
5122 /* Many RISC machines have a large set of logical insns. If the
5123 second operand is a NOT, put it first so we will try to split the
5124 other operand first. */
5126 {
5130 }
5135 /* Canonicalization can produce (minus A (mult B C)), where C is a
5136 constant. It may be better to try splitting (plus (mult B -C) A)
5137 instead if this isn't a multiply by a power of two. */
5141 {
5149 mode)),
5152 }
5154 /* Split at a multiply-accumulate instruction. However if this is
5155 the SET_SRC, we likely do not have such an instruction and it's
5156 worthless to try this split. */
5165 }
5167 /* Otherwise, select our actions depending on our rtx class. */
5169 {
5175 /* fall through */
5183 /* fall through */
5185 /* Some machines have (and (shift ...) ...) insns. If X is not
5186 an AND, but XEXP (X, 0) is, use it as our split point. */
5196 /* Otherwise, we don't have a split point. */
5198 }
5199 }
5200 \f
5201 /* Throughout X, replace FROM with TO, and return the result.
5202 The result is TO if X is FROM;
5203 otherwise the result is X, but its contents may have been modified.
5204 If they were modified, a record was made in undobuf so that
5205 undo_all will (among other things) return X to its original state.
5207 If the number of changes necessary is too much to record to undo,
5208 the excess changes are not made, so the result is invalid.
5209 The changes already made can still be undone.
5210 undobuf.num_undo is incremented for such changes, so by testing that
5211 the caller can tell whether the result is valid.
5213 `n_occurrences' is incremented each time FROM is replaced.
5215 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5217 IN_COND is nonzero if we are at the top level of a condition.
5219 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5220 by copying if `n_occurrences' is nonzero. */
5222 static rtx
5224 {
5229 rtx new_rtx;
5231 /* Two expressions are equal if they are identical copies of a shared
5232 RTX or if they are both registers with the same register number
5233 and mode. */
5235 #define COMBINE_RTX_EQUAL_P(X,Y) \
5236 ((X) == (Y) \
5237 || (REG_P (X) && REG_P (Y) \
5238 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5240 /* Do not substitute into clobbers of regs -- this will never result in
5241 valid RTL. */
5246 {
5247 n_occurrences++;
5249 }
5251 /* If X and FROM are the same register but different modes, they
5252 will not have been seen as equal above. However, the log links code
5253 will make a LOG_LINKS entry for that case. If we do nothing, we
5254 will try to rerecognize our original insn and, when it succeeds,
5255 we will delete the feeding insn, which is incorrect.
5257 So force this insn not to match in this (rare) case. */
5262 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5263 of which may contain things that can be combined. */
5267 /* It is possible to have a subexpression appear twice in the insn.
5268 Suppose that FROM is a register that appears within TO.
5269 Then, after that subexpression has been scanned once by `subst',
5270 the second time it is scanned, TO may be found. If we were
5271 to scan TO here, we would find FROM within it and create a
5272 self-referent rtl structure which is completely wrong. */
5276 /* Parallel asm_operands need special attention because all of the
5277 inputs are shared across the arms. Furthermore, unsharing the
5278 rtl results in recognition failures. Failure to handle this case
5279 specially can result in circular rtl.
5281 Solve this by doing a normal pass across the first entry of the
5282 parallel, and only processing the SET_DESTs of the subsequent
5283 entries. Ug. */
5288 {
5291 /* If this substitution failed, this whole thing fails. */
5299 {
5305 {
5308 /* If this substitution failed, this whole thing fails. */
5314 }
5315 }
5316 }
5317 else
5318 {
5322 /* We don't need to process a SET_DEST that is a register, CC0,
5323 or PC, so set up to skip this common case. All other cases
5324 where we want to suppress replacing something inside a
5325 SET_SRC are handled via the IN_DEST operand. */
5332 /* Trying to simplify the operands of a widening MULT is not likely
5333 to create RTL matching a machine insn. */
5345 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5346 constant. */
5351 {
5353 {
5356 {
5358 {
5361 n_occurrences++;
5362 }
5363 else
5364 {
5366 unique_copy);
5368 /* If this substitution failed, this whole thing
5369 fails. */
5373 }
5376 }
5377 }
5379 {
5380 /* If this is a register being set, ignore it. */
5387 ;
5390 {
5391 /* In general, don't install a subreg involving two
5392 modes not tieable. It can worsen register
5393 allocation, and can even make invalid reload
5394 insns, since the reg inside may need to be copied
5395 from in the outside mode, and that may be invalid
5396 if it is an fp reg copied in integer mode.
5398 We allow two exceptions to this: It is valid if
5399 it is inside another SUBREG and the mode of that
5400 SUBREG and the mode of the inside of TO is
5401 tieable and it is valid if X is a SET that copies
5402 FROM to CC0. */
5410 && (!HAVE_cc0
5425 n_occurrences++;
5426 }
5427 else
5428 /* If we are in a SET_DEST, suppress most cases unless we
5429 have gone inside a MEM, in which case we want to
5430 simplify the address. We assume here that things that
5431 are actually part of the destination have their inner
5432 parts in the first expression. This is true for SUBREG,
5433 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5434 things aside from REG and MEM that should appear in a
5435 SET_DEST. */
5437 (((in_dest
5443 unique_copy);
5445 /* If we found that we will have to reject this combination,
5446 indicate that by returning the CLOBBER ourselves, rather than
5447 an expression containing it. This will speed things up as
5448 well as prevent accidents where two CLOBBERs are considered
5449 to be equal, thus producing an incorrect simplification. */
5455 {
5463 }
5466 {
5470 }
5471 else
5473 }
5474 }
5475 }
5477 /* Check if we are loading something from the constant pool via float
5478 extension; in this case we would undo compress_float_constant
5479 optimization and degenerate constant load to an immediate value. */
5483 {
5487 }
5489 /* Try to simplify X. If the simplification changed the code, it is likely
5490 that further simplification will help, so loop, but limit the number
5491 of repetitions that will be performed. */
5494 {
5495 /* If X is sufficiently simple, don't bother trying to do anything
5496 with it. */
5505 /* We no longer know the original mode of operand 0 since we
5506 have changed the form of X) */
5508 }
5511 }
5512 \f
5513 /* If X is a commutative operation whose operands are not in the canonical
5514 order, use substitutions to swap them. */
5516 static void
5518 {
5521 {
5525 }
5526 }
5528 /* Simplify X, a piece of RTL. We just operate on the expression at the
5529 outer level; call `subst' to simplify recursively. Return the new
5530 expression.
5532 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5533 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5534 of a condition. */
5536 static rtx
5539 {
5542 rtx temp;
5545 /* If this is a commutative operation, put a constant last and a complex
5546 expression first. We don't need to do this for comparisons here. */
5549 /* Try to fold this expression in case we have constants that weren't
5550 present before. */
5553 {
5561 {
5564 {
5568 }
5571 }
5584 }
5587 {
5592 }
5594 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5595 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5596 things. Check for cases where both arms are testing the same
5597 condition.
5599 Don't do anything if all operands are very simple. */
5612 {
5617 /* If everything is a comparison, what we have is highly unlikely
5618 to be simpler, so don't use it. */
5621 {
5628 /* Simplify the alternative arms; this may collapse the true and
5629 false arms to store-flag values. Be careful to use copy_rtx
5630 here since true_rtx or false_rtx might share RTL with x as a
5631 result of the if_then_else_cond call above. */
5635 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5636 is unlikely to be simpler. */
5639 {
5642 /* Restarting if we generate a store-flag expression will cause
5643 us to loop. Just drop through in this case. */
5645 /* If the result values are STORE_FLAG_VALUE and zero, we can
5646 just make the comparison operation. */
5657 /* Likewise, we can make the negate of a comparison operation
5658 if the result values are - STORE_FLAG_VALUE and zero. */
5666 mode);
5677 mode);
5678 else
5681 mode,
5682 VOIDmode,
5683 cond,
5684 cop1),
5689 }
5690 }
5691 }
5693 /* First see if we can apply the inverse distributive law. */
5696 {
5700 }
5702 /* If CODE is an associative operation not otherwise handled, see if we
5703 can associate some operands. This can win if they are constants or
5704 if they are logically related (i.e. (a & b) & a). */
5710 {
5712 {
5716 rtx inner;
5718 /* Make sure we pass the constant operand if any as the second
5719 one if this is a commutative operation. */
5727 /* For commutative operations, try the other pair if that one
5728 didn't simplify. */
5730 {
5735 }
5739 }
5740 }
5742 /* A little bit of algebraic simplification here. */
5744 {
5746 /* Ensure that our address has any ASHIFTs converted to MULT in case
5747 address-recognizing predicates are called later. */
5756 /* See if this can be moved to simplify_subreg. */
5759 /* Don't call gen_lowpart if the inner mode
5760 is VOIDmode and we cannot simplify it, as SUBREG without
5761 inner mode is invalid. */
5768 {
5769 rtx temp;
5775 /* If op is known to have all lower bits zero, the result is zero. */
5785 }
5787 /* Don't change the mode of the MEM if that would change the meaning
5788 of the address. */
5795 /* Note that we cannot do any narrowing for non-constants since
5796 we might have been counting on using the fact that some bits were
5797 zero. We now do this in the SET. */
5804 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5805 replaced by (lshiftrt X C). This will convert
5806 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5814 /* If X has only a single bit that might be nonzero, say, bit I, convert
5815 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5816 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5817 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5818 or a SUBREG of one since we'd be making the expression more
5819 complex if it was just a register. */
5825 {
5826 rtx temp1 = simplify_shift_const
5832 /* If all we did was surround TEMP with the two shifts, we
5833 haven't improved anything, so don't use it. Otherwise,
5834 we are better off with TEMP1. */
5839 }
5843 /* We can't handle truncation to a partial integer mode here
5844 because we don't know the real bitsize of the partial
5845 integer mode. */
5854 /* We can truncate a constant value and return it. */
5858 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5859 whose value is a comparison can be replaced with a subreg if
5860 STORE_FLAG_VALUE permits. */
5869 /* (const (const X)) can become (const X). Do it this way rather than
5870 returning the inner CONST since CONST can be shared with a
5871 REG_EQUAL note. */
5877 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5878 can add in an offset. find_split_point will split this address up
5879 again if it doesn't match. */
5886 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5887 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5888 bit-field and can be replaced by either a sign_extend or a
5889 sign_extract. The `and' may be a zero_extend and the two
5890 <c>, -<c> constants may be reversed. */
5905 return simplify_shift_const
5912 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5913 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5914 the bitsize of the mode - 1. This allows simplification of
5915 "a = (b & 8) == 0;" */
5927 /* If we are adding two things that have no bits in common, convert
5928 the addition into an IOR. This will often be further simplified,
5929 for example in cases like ((a & 1) + (a & 2)), which can
5930 become a & 3. */
5935 {
5936 /* Try to simplify the expression further. */
5940 /* If we could, great. If not, do not go ahead with the IOR
5941 replacement, since PLUS appears in many special purpose
5942 address arithmetic instructions. */
5950 }
5952 /* Canonicalize x + x into x << 1. */
5961 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5962 (and <foo> (const_int pow2-1)) */
5972 /* If we have (mult (plus A B) C), apply the distributive law and then
5973 the inverse distributive law to see if things simplify. This
5974 occurs mostly in addresses, often when unrolling loops. */
5977 {
5981 }
5983 /* Try simplify a*(b/c) as (a*b)/c. */
5986 {
5992 }
5996 /* If this is a divide by a power of two, treat it as a shift if
5997 its first operand is a shift. */
6015 /* If the first operand is a condition code, we can't do anything
6016 with it. */
6020 {
6028 /* Simplify our comparison, if possible. */
6031 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6032 if only the low-order bit is possibly nonzero in X (such as when
6033 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6034 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6035 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6036 (plus X 1).
6038 Remove any ZERO_EXTRACT we made when thinking this was a
6039 comparison. It may now be simpler to use, e.g., an AND. If a
6040 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6041 the call to make_compound_operation in the SET case.
6043 Don't apply these optimizations if the caller would
6044 prefer a comparison rather than a value.
6045 E.g., for the condition in an IF_THEN_ELSE most targets need
6046 an explicit comparison. */
6049 ;
6065 {
6069 mode);
6070 }
6077 {
6081 const1_rtx);
6082 }
6090 {
6093 }
6095 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6096 those above. */
6098 ;
6114 {
6118 mode);
6119 }
6127 {
6131 mode);
6132 }
6134 /* If X is 0/1, (eq X 0) is X-1. */
6140 {
6143 }
6145 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6146 one bit that might be nonzero, we can convert (ne x 0) to
6147 (ashift x c) where C puts the bit in the sign bit. Remove any
6148 AND with STORE_FLAG_VALUE when we are done, since we are only
6149 going to test the sign bit. */
6156 {
6162 else
6164 }
6166 /* If the code changed, return a whole new comparison.
6167 We also need to avoid using SUBST in cases where
6168 simplify_comparison has widened a comparison with a CONST_INT,
6169 since in that case the wider CONST_INT may fail the sanity
6170 checks in do_SUBST. */
6177 /* Otherwise, keep this operation, but maybe change its operands.
6178 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6181 }
6191 /* If we are processing SET_DEST, we are done. */
6209 /* If this is a shift by a constant amount, simplify it. */
6217 (HOST_WIDE_INT_1U
6225 }
6228 }
6229 \f
6230 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6232 static rtx
6234 {
6241 rtx temp;
6244 rtx reversed;
6246 /* Simplify storing of the truth value. */
6251 /* Also when the truth value has to be reversed. */
6257 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6258 in it is being compared against certain values. Get the true and false
6259 comparisons and see if that says anything about the value of each arm. */
6265 {
6266 HOST_WIDE_INT nzb;
6272 /* If FALSE_CODE is EQ, swap the codes and arms. */
6275 {
6278 }
6280 /* If we are comparing against zero and the expression being tested has
6281 only a single bit that might be nonzero, that is its value when it is
6282 not equal to zero. Similarly if it is known to be -1 or 0. */
6286 {
6289 }
6293 {
6296 }
6298 /* Now simplify an arm if we know the value of the register in the
6299 branch and it is used in the arm. Be careful due to the potential
6300 of locally-shared RTL. */
6317 }
6319 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6320 reversed, do so to avoid needing two sets of patterns for
6321 subtract-and-branch insns. Similarly if we have a constant in the true
6322 arm, the false arm is the same as the first operand of the comparison, or
6323 the false arm is more complicated than the true arm. */
6336 {
6345 /* It is possible that the conditional has been simplified out. */
6348 }
6350 /* If the two arms are identical, we don't need the comparison. */
6355 /* Convert a == b ? b : a to "a". */
6367 /* Look for cases where we have (abs x) or (neg (abs X)). */
6370 && comparison_p
6377 {
6383 return
6386 mode);
6389 }
6391 /* Look for MIN or MAX. */
6394 && comparison_p
6399 {
6414 }
6416 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6417 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6418 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6419 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6420 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6421 neither 1 or -1, but it isn't worth checking for. */
6424 && comparison_p
6427 {
6443 /* If an identity-zero op is commutative, check whether there
6444 would be a match if we swapped the operands. */
6464 {
6468 }
6480 {
6484 }
6500 {
6504 }
6516 {
6520 }
6523 {
6529 const_true_rtx));
6537 }
6538 }
6540 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6541 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6542 negation of a single bit, we can convert this operation to a shift. We
6543 can actually do this more generally, but it doesn't seem worth it. */
6552 return
6556 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6557 non-zero bit in A is C1. */
6564 {
6571 }
6574 }
6575 \f
6576 /* Simplify X, a SET expression. Return the new expression. */
6578 static rtx
6580 {
6583 machine_mode mode
6588 /* (set (pc) (return)) gets written as (return). */
6592 /* Now that we know for sure which bits of SRC we are using, see if we can
6593 simplify the expression for the object knowing that we only need the
6594 low-order bits. */
6597 {
6600 }
6602 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6603 the comparison result and try to simplify it unless we already have used
6604 undobuf.other_insn. */
6612 {
6621 {
6624 {
6627 }
6628 }
6629 else
6637 {
6641 }
6642 else
6643 {
6648 /* Attempt to simplify CC user. */
6650 {
6654 }
6656 /* Convert X into a no-op move. */
6660 }
6662 /* Simplify our comparison, if possible. */
6665 #ifdef SELECT_CC_MODE
6666 /* If this machine has CC modes other than CCmode, check to see if we
6667 need to use a different CC mode here. */
6676 else
6679 /* If the mode changed, we have to change SET_DEST, the mode in the
6680 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6681 a hard register, just build new versions with the proper mode. If it
6682 is a pseudo, we lose unless it is only time we set the pseudo, in
6683 which case we can safely change its mode. */
6685 {
6687 {
6689 rtx new_dest;
6693 else
6694 {
6697 }
6704 }
6705 }
6708 /* If the code changed, we have to build a new comparison in
6709 undobuf.other_insn. */
6711 {
6720 /* If the only change we made was to change an EQ into an NE or
6721 vice versa, OP0 has only one bit that might be nonzero, and OP1
6722 is zero, check if changing the user of the condition code will
6723 produce a valid insn. If it won't, we can keep the original code
6724 in that insn by surrounding our operation with an XOR. */
6731 {
6736 {
6743 }
6744 }
6745 }
6750 /* Don't generate a compare of a CC with 0, just use that CC. */
6752 {
6755 }
6756 /* Otherwise, if we didn't previously have the same COMPARE we
6757 want, create it from scratch. */
6760 {
6763 }
6764 }
6765 else
6766 {
6767 /* Get SET_SRC in a form where we have placed back any
6768 compound expressions. Then do the checks below. */
6771 }
6773 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6774 and X being a REG or (subreg (reg)), we may be able to convert this to
6775 (set (subreg:m2 x) (op)).
6777 We can always do this if M1 is narrower than M2 because that means that
6778 we only care about the low bits of the result.
6780 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6781 perform a narrower operation than requested since the high-order bits will
6782 be undefined. On machine where it is defined, this transformation is safe
6783 as long as M1 and M2 have the same number of words. */
6791 && (WORD_REGISTER_OPERATIONS
6794 #ifdef CANNOT_CHANGE_MODE_CLASS
6799 #endif
6803 {
6806 dest));
6810 }
6812 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6813 in SRC. */
6819 {
6823 /* Here we make sure that we don't have a sign bit on. */
6826 {
6829 }
6830 }
6832 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6833 would require a paradoxical subreg. Replace the subreg with a
6834 zero_extend to avoid the reload that would otherwise be required. */
6840 {
6845 }
6847 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6848 are comparing an item known to be 0 or -1 against 0, use a logical
6849 operation instead. Check for one of the arms being an IOR of the other
6850 arm with some value. We compute three terms to be IOR'ed together. In
6851 practice, at most two will be nonzero. Then we do the IOR's. */
6859 && (!HAVE_conditional_move
6865 {
6891 false_rtx);
6897 term3));
6900 }
6902 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6903 whole thing fail. */
6908 else
6909 /* Convert this into a field assignment operation, if possible. */
6911 }
6912 \f
6913 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6914 result. */
6916 static rtx
6918 {
6924 {
6926 /* We can call simplify_and_const_int only if we don't lose
6927 any (sign) bits when converting INTVAL (op1) to
6928 "unsigned HOST_WIDE_INT". */
6932 {
6939 }
6941 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6942 apply the distributive law and then the inverse distributive
6943 law to see if things simplify. */
6945 {
6949 }
6951 {
6955 }
6959 /* If we have (ior (and A B) C), apply the distributive law and then
6960 the inverse distributive law to see if things simplify. */
6963 {
6967 }
6970 {
6974 }
6979 }
6982 }
6983 \f
6984 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6985 operations" because they can be replaced with two more basic operations.
6986 ZERO_EXTEND is also considered "compound" because it can be replaced with
6987 an AND operation, which is simpler, though only one operation.
6989 The function expand_compound_operation is called with an rtx expression
6990 and will convert it to the appropriate shifts and AND operations,
6991 simplifying at each stage.
6993 The function make_compound_operation is called to convert an expression
6994 consisting of shifts and ANDs into the equivalent compound expression.
6995 It is the inverse of this function, loosely speaking. */
6997 static rtx
6999 {
7003 rtx tem;
7006 {
7009 /* FALLTHRU */
7011 /* We can't necessarily use a const_int for a multiword mode;
7012 it depends on implicitly extending the value.
7013 Since we don't know the right way to extend it,
7014 we can't tell whether the implicit way is right.
7016 Even for a mode that is no wider than a const_int,
7017 we can't win, because we need to sign extend one of its bits through
7018 the rest of it, and we don't know which bit. */
7022 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7023 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7024 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7025 reloaded. If not for that, MEM's would very rarely be safe.
7027 Reject MODEs bigger than a word, because we might not be able
7028 to reference a two-register group starting with an arbitrary register
7029 (and currently gen_lowpart might crash for a SUBREG). */
7034 /* Reject MODEs that aren't scalar integers because turning vector
7035 or complex modes into shifts causes problems. */
7041 /* If the inner object has VOIDmode (the only way this can happen
7042 is if it is an ASM_OPERANDS), we can't do anything since we don't
7043 know how much masking to do. */
7052 /* fall through */
7055 /* If the operand is a CLOBBER, just return it. */
7064 /* Reject MODEs that aren't scalar integers because turning vector
7065 or complex modes into shifts causes problems. */
7073 /* This should stay within the object being extracted, fail otherwise. */
7084 }
7085 /* Convert sign extension to zero extension, if we know that the high
7086 bit is not set, as this is easier to optimize. It will be converted
7087 back to cheaper alternative in make_extraction. */
7095 {
7100 /* Make sure this is a profitable operation. */
7107 else
7109 }
7111 /* We can optimize some special cases of ZERO_EXTEND. */
7113 {
7114 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7115 know that the last value didn't have any inappropriate bits
7116 set. */
7124 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7133 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7134 is a comparison and STORE_FLAG_VALUE permits. This is like
7135 the first case, but it works even when GET_MODE (x) is larger
7136 than HOST_WIDE_INT. */
7145 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7155 }
7157 /* If we reach here, we want to return a pair of shifts. The inner
7158 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7159 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7160 logical depending on the value of UNSIGNEDP.
7162 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7163 converted into an AND of a shift.
7165 We must check for the case where the left shift would have a negative
7166 count. This can happen in a case like (x >> 31) & 255 on machines
7167 that can't shift by a constant. On those machines, we would first
7168 combine the shift with the AND to produce a variable-position
7169 extraction. Then the constant of 31 would be substituted in
7170 to produce such a position. */
7174 {
7183 }
7190 else
7191 /* Any other cases we can't handle. */
7194 /* If we couldn't do this for some reason, return the original
7195 expression. */
7200 }
7201 \f
7202 /* X is a SET which contains an assignment of one object into
7203 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7204 or certain SUBREGS). If possible, convert it into a series of
7205 logical operations.
7207 We half-heartedly support variable positions, but do not at all
7208 support variable lengths. */
7210 static const_rtx
7212 {
7213 rtx inner;
7217 machine_mode compute_mode;
7219 /* Loop until we find something we can't simplify. */
7221 {
7224 {
7228 }
7231 {
7236 /* A constant position should stay within the width of INNER. */
7242 {
7250 /* If position is ADJUST - X, new position is X. */
7252 else
7253 {
7258 pos);
7259 }
7260 }
7261 }
7263 /* A SUBREG between two modes that occupy the same numbers of words
7264 can be done by moving the SUBREG to the source. */
7266 /* We need SUBREGs to compute nonzero_bits properly. */
7267 && nonzero_sign_valid
7272 {
7274 gen_lowpart
7278 }
7279 else
7287 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7289 {
7290 machine_mode imode;
7292 /* Don't do anything for vector or complex integral types. */
7296 /* Try to find an integral mode to pun with. */
7303 }
7305 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7309 /* Don't try to compute in too wide unsupported modes. */
7313 /* Now compute the equivalent expression. Make a copy of INNER
7314 for the SET_DEST in case it is a MEM into which we will substitute;
7315 we don't want shared RTL in that case. */
7317 compute_mode);
7321 compute_mode,
7323 compute_mode),
7324 inner);
7329 mask),
7330 pos);
7335 }
7338 }
7339 \f
7340 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7341 it is an RTX that represents the (variable) starting position; otherwise,
7342 POS is the (constant) starting bit position. Both are counted from the LSB.
7344 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7346 IN_DEST is nonzero if this is a reference in the destination of a SET.
7347 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7348 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7349 be used.
7351 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7352 ZERO_EXTRACT should be built even for bits starting at bit 0.
7354 MODE is the desired mode of the result (if IN_DEST == 0).
7356 The result is an RTX for the extraction or NULL_RTX if the target
7357 can't handle it. */
7359 static rtx
7363 {
7364 /* This mode describes the size of the storage area
7365 to fetch the overall value from. Within that, we
7366 ignore the POS lowest bits, etc. */
7368 machine_mode inner_mode;
7369 machine_mode wanted_inner_mode;
7376 HOST_WIDE_INT orig_pos;
7382 {
7383 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7384 consider just the QI as the memory to extract from.
7385 The subreg adds or removes high bits; its mode is
7386 irrelevant to the meaning of this extraction,
7387 since POS and LEN count from the lsb. */
7391 }
7396 {
7397 /* We're extracting the least significant bits of an rtx
7398 (ashift X (const_int C)), where LEN > C. Extract the
7399 least significant (LEN - C) bits of X, giving an rtx
7400 whose mode is MODE, then shift it left C times. */
7406 }
7412 /* See if this can be done without an extraction. We never can if the
7413 width of the field is not the same as that of some integer mode. For
7414 registers, we can only avoid the extraction if the position is at the
7415 low-order bit and this is either not in the destination or we have the
7416 appropriate STRICT_LOW_PART operation available.
7418 For MEM, we can avoid an extract if the field starts on an appropriate
7419 boundary and we can change the mode of the memory reference. */
7429 && (! in_dest
7433 && (pos
7436 /* We can't do this if we are widening INNER_MODE (it
7437 may not be aligned, for one thing). */
7443 {
7444 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7445 field. If the original and current mode are the same, we need not
7446 adjust the offset. Otherwise, we do if bytes big endian.
7448 If INNER is not a MEM, get a piece consisting of just the field
7449 of interest (in this case POS % BITS_PER_WORD must be 0). */
7452 {
7453 HOST_WIDE_INT offset;
7455 /* POS counts from lsb, but make OFFSET count in memory order. */
7458 else
7462 }
7464 {
7466 {
7467 /* We can't call gen_lowpart in a DEST since we
7468 always want a SUBREG (see below) and it would sometimes
7469 return a new hard register. */
7471 {
7486 /* Avoid creating invalid subregs, for example when
7487 simplifying (x>>32)&255. */
7492 }
7493 else
7495 }
7496 else
7498 }
7499 else
7501 len >= HOST_BITS_PER_WIDE_INT
7502 ? HOST_WIDE_INT_M1U
7505 /* If this extraction is going into the destination of a SET,
7506 make a STRICT_LOW_PART unless we made a MEM. */
7521 /* If we know that no extraneous bits are set, and that the high
7522 bit is not set, convert the extraction to the cheaper of
7523 sign and zero extension, that are equivalent in these cases. */
7529 {
7533 /* Prefer ZERO_EXTENSION, since it gives more information to
7534 backends. */
7539 }
7541 /* Otherwise, sign- or zero-extend unless we already are in the
7542 proper mode. */
7546 }
7548 /* Unless this is a COMPARE or we have a funny memory reference,
7549 don't do anything with zero-extending field extracts starting at
7550 the low-order bit since they are simple AND operations. */
7555 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7556 if the position is not a constant and the length is not 1. In all
7557 other cases, we would only be going outside our object in cases when
7558 an original shift would have been undefined. */
7567 /* If INNER is not from memory, we want it to have the mode of a register
7568 extraction pattern's structure operand, or word_mode if there is no
7569 such pattern. The same applies to extraction_mode and pos_mode
7570 and their respective operands.
7572 For memory, assume that the desired extraction_mode and pos_mode
7573 are the same as for a register operation, since at present we don't
7574 have named patterns for aligned memory structures. */
7578 {
7582 }
7584 /* Never narrow an object, since that might not be safe. */
7592 else
7593 {
7594 /* Be careful not to go beyond the extracted object and maintain the
7595 natural alignment of the memory. */
7599 {
7602 }
7603 }
7608 {
7609 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7610 BITS_BIG_ENDIAN style. If position is constant, compute new
7611 position. Otherwise, build subtraction.
7612 Note that POS is relative to the mode of the original argument.
7613 If it's a MEM we need to recompute POS relative to that.
7614 However, if we're extracting from (or inserting into) a register,
7615 we want to recompute POS relative to wanted_inner_mode. */
7622 else
7623 pos_rtx
7626 pos_rtx);
7627 /* POS may be less than 0 now, but we check for that below.
7628 Note that it can only be less than 0 if !MEM_P (inner). */
7629 }
7631 /* If INNER has a wider mode, and this is a constant extraction, try to
7632 make it smaller and adjust the byte to point to the byte containing
7633 the value. */
7636 && ! pos_rtx
7641 {
7644 /* The computations below will be correct if the machine is big
7645 endian in both bits and bytes or little endian in bits and bytes.
7646 If it is mixed, we must adjust. */
7648 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7649 adjust OFFSET to compensate. */
7654 /* We can now move to the desired byte. */
7665 }
7667 /* If INNER is not memory, get it into the proper mode. If we are changing
7668 its mode, POS must be a constant and smaller than the size of the new
7669 mode. */
7671 {
7672 /* On the LHS, don't create paradoxical subregs implicitely truncating
7673 the register unless TRULY_NOOP_TRUNCATION. */
7676 wanted_inner_mode))
7688 pos_rtx
7690 ? HOST_WIDE_INT_M1U
7694 }
7696 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7697 have to zero extend. Otherwise, we can just use a SUBREG. */
7700 {
7704 /* If we know that no extraneous bits are set, and that the high
7705 bit is not set, convert extraction to cheaper one - either
7706 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7707 cases. */
7715 {
7719 /* Prefer ZERO_EXTENSION, since it gives more information to
7720 backends. */
7724 }
7726 }
7728 /* Make POS_RTX unless we already have it and it is correct. If we don't
7729 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7730 be a CONST_INT. */
7737 /* Make the required operation. See if we can use existing rtx. */
7744 }
7745 \f
7746 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7747 with any other operations in X. Return X without that shift if so. */
7749 static rtx
7751 {
7754 rtx tem;
7757 {
7759 /* This is the shift itself. If it is wide enough, we will return
7760 either the value being shifted if the shift count is equal to
7761 COUNT or a shift for the difference. */
7775 /* If we can safely shift this constant and we find the inner shift,
7776 make a new operation. */
7781 {
7785 }
7790 }
7793 }
7794 \f
7795 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7796 level of the expression and MODE is its mode. IN_CODE is as for
7797 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7798 that should be used when recursing on operands of *X_PTR.
7800 There are two possible actions:
7802 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7803 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7805 - Return a new rtx, which the caller returns directly. */
7807 static rtx
7811 {
7819 rtx tem;
7823 {
7826 }
7828 /* Process depending on the code of this operation. If NEW is set
7829 nonzero, it will be returned. */
7832 {
7834 /* Convert shifts by constants into multiplications if inside
7835 an address. */
7839 {
7845 {
7848 }
7851 }
7860 {
7864 }
7867 {
7871 mode));
7873 }
7874 else
7875 {
7878 }
7888 {
7892 }
7895 {
7899 mode));
7901 }
7902 else
7903 {
7907 }
7910 /* If the second operand is not a constant, we can't do anything
7911 with it. */
7915 /* If the constant is a power of two minus one and the first operand
7916 is a logical right shift, make an extraction. */
7919 {
7923 }
7925 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7930 {
7939 {
7940 /* If we narrowed the mode when dropping the subreg, then
7941 we must zero-extend to keep the semantics of the AND. */
7943 ;
7947 else
7949 }
7951 /* If that didn't give anything, see if the AND simplifies on
7952 its own. */
7954 {
7958 }
7959 }
7960 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7966 {
7967 /* Apply the distributive law, and then try to make extractions. */
7974 }
7976 /* If we are have (and (rotate X C) M) and C is larger than the number
7977 of bits in M, this is an extraction. */
7983 {
7989 }
7991 /* On machines without logical shifts, if the operand of the AND is
7992 a logical shift and our mask turns off all the propagated sign
7993 bits, we can replace the logical shift with an arithmetic shift. */
8001 {
8008 make_compound_operation
8011 }
8013 /* If the constant is one less than a power of two, this might be
8014 representable by an extraction even if no shift is present.
8015 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8016 we are in a COMPARE. */
8020 next_code),
8023 /* If we are in a comparison and this is an AND with a power of two,
8024 convert this into the appropriate bit extract. */
8030 next_code),
8033 /* If the one operand is a paradoxical subreg of a register or memory and
8034 the constant (limited to the smaller mode) has only zero bits where
8035 the sub expression has known zero bits, this can be expressed as
8036 a zero_extend. */
8038 {
8039 rtx sub;
8045 {
8049 /* original AND constant with all the known zero bits set */
8052 {
8057 }
8058 }
8059 }
8064 /* If the sign bit is known to be zero, replace this with an
8065 arithmetic shift. */
8070 {
8073 next_code),
8076 }
8078 /* fall through */
8084 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8085 this is a SIGN_EXTRACT. */
8092 {
8099 }
8101 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8102 If so, try to merge the shifts into a SIGN_EXTEND. We could
8103 also do this for some cases of SIGN_EXTRACT, but it doesn't
8104 seem worth the effort; the case checked for occurs on Alpha. */
8121 /* Call ourselves recursively on the inner expression. If we are
8122 narrowing the object and it has a different RTL code from
8123 what it originally did, do this SUBREG as a force_to_mode. */
8124 {
8128 /* If the SUBREG is masking of a logical right shift,
8129 make an extraction. */
8136 {
8145 }
8147 /* If in_code is COMPARE, it isn't always safe to pass it through
8148 to the recursive make_compound_operation call. */
8152 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8153 is (const_int 0), rather than
8154 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8164 simplified
8172 {
8173 rtx newer
8176 /* If we have something other than a SUBREG, we might have
8177 done an expansion, so rerun ourselves. */
8181 /* force_to_mode can expand compounds. If it just re-expanded the
8182 compound, use gen_lowpart to convert to the desired mode. */
8184 /* Likewise if it re-expanded the compound only partially.
8185 This happens for SUBREG of ZERO_EXTRACT if they extract
8186 the same number of bits. */
8195 }
8199 }
8204 }
8210 }
8212 /* Look at the expression rooted at X. Look for expressions
8213 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8214 Form these expressions.
8216 Return the new rtx, usually just X.
8218 Also, for machines like the VAX that don't have logical shift insns,
8219 try to convert logical to arithmetic shift operations in cases where
8220 they are equivalent. This undoes the canonicalizations to logical
8221 shifts done elsewhere.
8223 We try, as much as possible, to re-use rtl expressions to save memory.
8225 IN_CODE says what kind of expression we are processing. Normally, it is
8226 SET. In a memory address it is MEM. When processing the arguments of
8227 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8228 precisely it is an equality comparison against zero. */
8230 rtx
8232 {
8239 /* Select the code to be used in recursive calls. Once we are inside an
8240 address, we stay there. If we have a comparison, set to COMPARE,
8241 but once inside, go back to our default of SET. */
8249 {
8255 }
8257 /* Now recursively process each operand of this operation. We need to
8258 handle ZERO_EXTEND specially so that we don't lose track of the
8259 inner mode. */
8261 {
8269 }
8274 {
8277 }
8280 {
8283 }
8287 }
8288 \f
8289 /* Given M see if it is a value that would select a field of bits
8290 within an item, but not the entire word. Return -1 if not.
8291 Otherwise, return the starting position of the field, where 0 is the
8292 low-order bit.
8294 *PLEN is set to the length of the field. */
8296 static int
8298 {
8299 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8304 /* Now shift off the low-order zero bits and see if we have a
8305 power of two minus 1. */
8313 }
8314 \f
8315 /* If X refers to a register that equals REG in value, replace these
8316 references with REG. */
8317 static rtx
8319 {
8327 {
8360 /* FALLTHRU */
8364 {
8368 else
8370 }
8372 /* fall through */
8379 {
8382 {
8384 {
8387 }
8389 }
8390 }
8392 {
8395 {
8398 {
8400 {
8403 }
8405 }
8406 }
8407 }
8410 }
8413 }
8415 /* Return X converted to MODE. If the value is already truncated to
8416 MODE we can just return a subreg even though in the general case we
8417 would need an explicit truncation. */
8419 static rtx
8421 {
8426 {
8427 /* Bit-cast X into an integer mode. */
8432 }
8435 }
8437 /* See if X can be simplified knowing that we will only refer to it in
8438 MODE and will only refer to those bits that are nonzero in MASK.
8439 If other bits are being computed or if masking operations are done
8440 that select a superset of the bits in MASK, they can sometimes be
8441 ignored.
8443 Return a possibly simplified expression, but always convert X to
8444 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8446 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8447 are all off in X. This is used when X will be complemented, by either
8448 NOT, NEG, or XOR. */
8450 static rtx
8453 {
8456 machine_mode op_mode;
8460 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8461 code below will do the wrong thing since the mode of such an
8462 expression is VOIDmode.
8464 Also do nothing if X is a CLOBBER; this can happen if X was
8465 the return value from a call to gen_lowpart. */
8469 /* We want to perform the operation in its present mode unless we know
8470 that the operation is valid in MODE, in which case we do the operation
8471 in MODE. */
8476 /* It is not valid to do a right-shift in a narrower mode
8477 than the one it came in with. */
8482 /* Truncate MASK to fit OP_MODE. */
8486 /* When we have an arithmetic operation, or a shift whose count we
8487 do not know, we need to assume that all bits up to the highest-order
8488 bit in MASK will be needed. This is how we form such a mask. */
8491 else
8495 /* Determine what bits of X are guaranteed to be (non)zero. */
8498 /* If none of the bits in X are needed, return a zero. */
8502 /* If X is a CONST_INT, return a new one. Do this here since the
8503 test below will fail. */
8505 {
8508 else
8509 {
8512 }
8513 }
8515 /* If X is narrower than MODE and we want all the bits in X's mode, just
8516 get X in the proper mode. */
8521 /* We can ignore the effect of a SUBREG if it narrows the mode or
8522 if the constant masks to zero all the bits the mode doesn't have. */
8532 /* The arithmetic simplifications here only work for scalar integer modes. */
8537 {
8539 /* If X is a (clobber (const_int)), return it since we know we are
8540 generating something that won't match. */
8553 /* Similarly for a truncate. */
8557 /* If this is an AND with a constant, convert it into an AND
8558 whose constant is the AND of that constant with MASK. If it
8559 remains an AND of MASK, delete it since it is redundant. */
8562 {
8566 /* If X is still an AND, see if it is an AND with a mask that
8567 is just some low-order bits. If so, and it is MASK, we don't
8568 need it. */
8575 /* If it remains an AND, try making another AND with the bits
8576 in the mode mask that aren't in MASK turned on. If the
8577 constant in the AND is wide enough, this might make a
8578 cheaper constant. */
8583 {
8584 unsigned HOST_WIDE_INT cval
8587 rtx y;
8594 }
8597 }
8602 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8603 low-order bits (as in an alignment operation) and FOO is already
8604 aligned to that boundary, mask C1 to that boundary as well.
8605 This may eliminate that PLUS and, later, the AND. */
8607 {
8611 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8612 number, sign extend it. */
8625 }
8627 /* fall through */
8630 /* Substituting into the operands of a widening MULT is not likely to
8631 create RTL matching a machine insn. */
8641 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8642 most significant bit in MASK since carries from those bits will
8643 affect the bits we are interested in. */
8648 /* If X is (minus C Y) where C's least set bit is larger than any bit
8649 in the mask, then we may replace with (neg Y). */
8652 {
8656 }
8658 /* Similarly, if C contains every bit in the fuller_mask, then we may
8659 replace with (not Y). */
8662 {
8666 }
8673 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8674 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8675 operation which may be a bitfield extraction. Ensure that the
8676 constant we form is not wider than the mode of X. */
8688 {
8697 }
8699 binop:
8700 /* For most binary operations, just propagate into the operation and
8701 change the mode if we have an operation of that mode. */
8706 /* If we ended up truncating both operands, truncate the result of the
8707 operation instead. */
8710 {
8713 }
8723 /* For left shifts, do the same, but just for the first operand.
8724 However, we cannot do anything with shifts where we cannot
8725 guarantee that the counts are smaller than the size of the mode
8726 because such a count will have a different meaning in a
8727 wider mode. */
8737 /* If the shift count is a constant and we can do arithmetic in
8738 the mode of the shift, refine which bits we need. Otherwise, use the
8739 conservative form of the mask. */
8745 else
8757 /* Here we can only do something if the shift count is a constant,
8758 this shift constant is valid for the host, and we can do arithmetic
8759 in OP_MODE. */
8765 {
8769 /* Select the mask of the bits we need for the shift operand. */
8772 /* We can only change the mode of the shift if we can do arithmetic
8773 in the mode of the shift and INNER_MASK is no wider than the
8774 width of X's mode. */
8782 }
8784 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8785 shift and AND produces only copies of the sign bit (C2 is one less
8786 than a power of two), we can do this with just a shift. */
8790 /* The shift puts one of the sign bit copies in the least significant
8791 bit. */
8796 /* Number of bits left after the shift must be more than the mask
8797 needs. */
8800 /* Must be more sign bit copies than the mask needs. */
8810 /* If we are just looking for the sign bit, we don't need this shift at
8811 all, even if it has a variable count. */
8815 /* If this is a shift by a constant, get a mask that contains those bits
8816 that are not copies of the sign bit. We then have two cases: If
8817 MASK only includes those bits, this can be a logical shift, which may
8818 allow simplifications. If MASK is a single-bit field not within
8819 those bits, we are requesting a copy of the sign bit and hence can
8820 shift the sign bit to the appropriate location. */
8824 {
8827 /* If the considered data is wider than HOST_WIDE_INT, we can't
8828 represent a mask for all its bits in a single scalar.
8829 But we only care about the lower bits, so calculate these. */
8832 {
8835 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8836 is the number of bits a full-width mask would have set.
8837 We need only shift if these are fewer than nonzero can
8838 hold. If not, we must keep all bits set in nonzero. */
8843 + HOST_BITS_PER_WIDE_INT
8845 }
8846 else
8847 {
8850 }
8853 {
8858 }
8861 {
8862 x = simplify_shift_const
8868 }
8869 }
8871 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8872 even if the shift count isn't a constant. */
8877 shiftrt:
8879 /* If this is a zero- or sign-extension operation that just affects bits
8880 we don't care about, remove it. Be sure the call above returned
8881 something that is still a shift. */
8891 next_select);
8897 /* If the shift count is constant and we can do computations
8898 in the mode of X, compute where the bits we care about are.
8899 Otherwise, we can't do anything. Don't change the mode of
8900 the shift or propagate MODE into the shift, though. */
8903 {
8913 }
8917 /* If we just want the low-order bit, the NEG isn't needed since it
8918 won't change the low-order bit. */
8922 /* We need any bits less significant than the most significant bit in
8923 MASK since carries from those bits will affect the bits we are
8924 interested in. */
8929 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8930 same as the XOR case above. Ensure that the constant we form is not
8931 wider than the mode of X. */
8939 {
8948 }
8950 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8951 use the full mask inside the NOT. */
8954 unop:
8957 next_select));
8963 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8964 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8965 which is equal to STORE_FLAG_VALUE. */
8977 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8978 written in a narrower mode. We play it safe and do not do so. */
8994 }
8996 /* Ensure we return a value of the proper mode. */
8998 }
8999 \f
9000 /* Return nonzero if X is an expression that has one of two values depending on
9001 whether some other value is zero or nonzero. In that case, we return the
9002 value that is being tested, *PTRUE is set to the value if the rtx being
9003 returned has a nonzero value, and *PFALSE is set to the other alternative.
9005 If we return zero, we set *PTRUE and *PFALSE to X. */
9007 static rtx
9009 {
9015 /* If we are comparing a value against zero, we are done. */
9018 {
9022 }
9024 /* If this is a unary operation whose operand has one of two values, apply
9025 our opcode to compute those values. */
9028 {
9033 }
9035 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9036 make can't possibly match and would suppress other optimizations. */
9038 ;
9040 /* If this is a binary operation, see if either side has only one of two
9041 values. If either one does or if both do and they are conditional on
9042 the same value, compute the new true and false values. */
9044 {
9050 {
9051 /* If if_then_else_cond returned zero, then true/false are the
9052 same rtl. We must copy one of them to prevent invalid rtl
9053 sharing. */
9060 {
9065 }
9066 else
9067 {
9070 }
9073 }
9075 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9076 operands is zero when the other is nonzero, and vice-versa,
9077 and STORE_FLAG_VALUE is 1 or -1. */
9083 {
9100 {
9107 const_true_rtx);
9109 }
9110 }
9112 /* Similarly for MULT, AND and UMIN, except that for these the result
9113 is always zero. */
9117 {
9131 {
9134 }
9135 }
9136 }
9139 {
9140 /* If we have IF_THEN_ELSE already, extract the condition and
9141 canonicalize it if it is NE or EQ. */
9147 {
9150 }
9151 else
9153 }
9155 /* If X is a SUBREG, we can narrow both the true and false values
9156 if the inner expression, if there is a condition. */
9160 {
9166 {
9170 }
9171 }
9173 /* If X is a constant, this isn't special and will cause confusions
9174 if we treat it as such. Likewise if it is equivalent to a constant. */
9177 ;
9179 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9180 will be least confusing to the rest of the compiler. */
9182 {
9185 }
9187 /* If X is known to be either 0 or -1, those are the true and
9188 false values when testing X. */
9192 {
9195 }
9197 /* Likewise for 0 or a single bit. */
9200 {
9203 }
9205 /* Otherwise fail; show no condition with true and false values the same. */
9208 }
9209 \f
9210 /* Return the value of expression X given the fact that condition COND
9211 is known to be true when applied to REG as its first operand and VAL
9212 as its second. X is known to not be shared and so can be modified in
9213 place.
9215 We only handle the simplest cases, and specifically those cases that
9216 arise with IF_THEN_ELSE expressions. */
9218 static rtx
9220 {
9228 /* If either operand of the condition is a floating point value,
9229 then we have to avoid collapsing an EQ comparison. */
9239 /* If X is (abs REG) and we know something about REG's relationship
9240 with zero, we may be able to simplify this. */
9244 {
9253 }
9255 /* The only other cases we handle are MIN, MAX, and comparisons if the
9256 operands are the same as REG and VAL. */
9259 {
9261 {
9264 }
9267 {
9269 {
9277 else
9279 }
9282 {
9285 /* Do not reverse the condition when it is NE or EQ.
9286 This is because we cannot conclude anything about
9287 the value of 'SMAX (x, y)' when x is not equal to y,
9288 but we can when x equals y. */
9294 {
9305 }
9306 }
9307 }
9308 }
9310 {
9315 {
9316 /* We must simplify subreg here, before we lose track of the
9317 original inner_mode. */
9322 else
9324 }
9327 }
9328 /* We don't have to handle SIGN_EXTEND here, because even in the
9329 case of replacing something with a modeless CONST_INT, a
9330 CONST_INT is already (supposed to be) a valid sign extension for
9331 its narrower mode, which implies it's already properly
9332 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9333 story is different. */
9335 {
9340 {
9341 /* We must simplify the zero_extend here, before we lose
9342 track of the original inner_mode. */
9347 else
9349 }
9352 }
9356 {
9363 }
9366 }
9367 \f
9368 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9369 assignment as a field assignment. */
9371 static int
9373 {
9375 {
9380 /* For big endian, adjust the memory offset. */
9385 else
9387 }
9395 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9396 Note that all SUBREGs of MEM are paradoxical; otherwise they
9397 would have been rewritten. */
9410 /* We used to see if get_last_value of X and Y were the same but that's
9411 not correct. In one direction, we'll cause the assignment to have
9412 the wrong destination and in the case, we'll import a register into this
9413 insn that might have already have been dead. So fail if none of the
9414 above cases are true. */
9416 }
9417 \f
9418 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9419 Return that assignment if so.
9421 We only handle the most common cases. */
9423 static rtx
9425 {
9428 rtx assign;
9430 HOST_WIDE_INT c1;
9431 HOST_WIDE_INT pos;
9433 rtx other;
9434 machine_mode mode;
9436 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9437 a clear of a one-bit field. We will have changed it to
9438 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9439 for a SUBREG. */
9445 {
9451 }
9461 {
9468 }
9470 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9471 one-bit field. */
9475 {
9481 }
9483 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9484 SRC is an AND with all bits of that field set, then we can discard
9485 the AND. */
9490 {
9497 else
9500 /* Complete overlap. We can remove the source AND. */
9504 /* Partial overlap. We can reduce the source AND. */
9506 {
9511 }
9512 }
9514 /* The other case we handle is assignments into a constant-position
9515 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9516 a mask that has all one bits except for a group of zero bits and
9517 OTHER is known to have zeros where C1 has ones, this is such an
9518 assignment. Compute the position and length from C1. Shift OTHER
9519 to the appropriate position, force it to the required mode, and
9520 make the extraction. Check for the AND in both operands. */
9522 /* One or more SUBREGs might obscure the constant-position field
9523 assignment. The first one we are likely to encounter is an outer
9524 narrowing SUBREG, which we can just strip for the purposes of
9525 identifying the constant-field assignment. */
9539 /* The second SUBREG that might get in the way is a paradoxical
9540 SUBREG around the first operand of the AND. We want to
9541 pretend the operand is as wide as the destination here. We
9542 do this by adjusting the MEM to wider mode for the sole
9543 purpose of the call to rtx_equal_for_field_assignment_p. Also
9544 note this trick only works for MEMs. */
9556 /* The second SUBREG that might get in the way is a paradoxical
9557 SUBREG around the first operand of the AND. We want to
9558 pretend the operand is as wide as the destination here. We
9559 do this by adjusting the MEM to wider mode for the sole
9560 purpose of the call to rtx_equal_for_field_assignment_p. Also
9561 note this trick only works for MEMs. */
9569 else
9582 /* The mode to use for the source is the mode of the assignment, or of
9583 what is inside a possible STRICT_LOW_PART. */
9587 /* Shift OTHER right POS places and make it the source, restricting it
9588 to the proper length and mode. */
9593 dest);
9596 ? HOST_WIDE_INT_M1U
9600 /* If SRC is masked by an AND that does not make a difference in
9601 the value being stored, strip it. */
9612 }
9613 \f
9614 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9615 if so. */
9617 static rtx
9619 {
9623 rtx tem;
9625 /* Distributivity is not true for floating point as it can change the
9626 value. So we don't do it unless -funsafe-math-optimizations. */
9631 /* The outer operation can only be one of the following: */
9639 /* If either operand is a primitive we can't do anything, so get out
9640 fast. */
9650 /* See if the inner and outer operations distribute. */
9652 {
9657 /* These all distribute except over PLUS. */
9668 /* This is also a multiply, so it distributes over everything. */
9671 /* This used to handle SUBREG, but this turned out to be counter-
9672 productive, since (subreg (op ...)) usually is not handled by
9673 insn patterns, and this "optimization" therefore transformed
9674 recognizable patterns into unrecognizable ones. Therefore the
9675 SUBREG case was removed from here.
9677 It is possible that distributing SUBREG over arithmetic operations
9678 leads to an intermediate result than can then be optimized further,
9679 e.g. by moving the outer SUBREG to the other side of a SET as done
9680 in simplify_set. This seems to have been the original intent of
9681 handling SUBREGs here.
9683 However, with current GCC this does not appear to actually happen,
9684 at least on major platforms. If some case is found where removing
9685 the SUBREG case here prevents follow-on optimizations, distributing
9686 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9690 }
9692 /* Set LHS and RHS to the inner operands (A and B in the example
9693 above) and set OTHER to the common operand (C in the example).
9694 There is only one way to do this unless the inner operation is
9695 commutative. */
9707 else
9710 /* Form the new inner operation, seeing if it simplifies first. */
9713 /* There is one exception to the general way of distributing:
9714 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9716 {
9719 }
9721 /* We may be able to continuing distributing the result, so call
9722 ourselves recursively on the inner operation before forming the
9723 outer operation, which we return. */
9726 }
9728 /* See if X is of the form (* (+ A B) C), and if so convert to
9729 (+ (* A C) (* B C)) and try to simplify.
9731 Most of the time, this results in no change. However, if some of
9732 the operands are the same or inverses of each other, simplifications
9733 will result.
9735 For example, (and (ior A B) (not B)) can occur as the result of
9736 expanding a bit field assignment. When we apply the distributive
9737 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9738 which then simplifies to (and (A (not B))).
9740 Note that no checks happen on the validity of applying the inverse
9741 distributive law. This is pointless since we can do it in the
9742 few places where this routine is called.
9744 N is the index of the term that is decomposed (the arithmetic operation,
9745 i.e. (+ A B) in the first example above). !N is the index of the term that
9746 is distributed, i.e. of C in the first example above. */
9747 static rtx
9749 {
9750 machine_mode mode;
9754 /* Distributivity is not true for floating point as it can change the
9755 value. So we don't do it unless -funsafe-math-optimizations. */
9772 /* Special case (and (xor B C) (not A)), which is equivalent to
9773 (xor (ior A B) (ior A C)) */
9775 {
9778 }
9781 {
9782 /* Distribute the second term. */
9785 }
9786 else
9787 {
9788 /* Distribute the first term. */
9791 }
9801 }
9802 \f
9803 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9804 in MODE. Return an equivalent form, if different from (and VAROP
9805 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9807 static rtx
9810 {
9813 rtx orig_varop;
9821 /* Simplify VAROP knowing that we will be only looking at some of the
9822 bits in it.
9824 Note by passing in CONSTOP, we guarantee that the bits not set in
9825 CONSTOP are not significant and will never be examined. We must
9826 ensure that is the case by explicitly masking out those bits
9827 before returning. */
9830 /* If VAROP is a CLOBBER, we will fail so return it. */
9834 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9835 to VAROP and return the new constant. */
9839 /* See what bits may be nonzero in VAROP. Unlike the general case of
9840 a call to nonzero_bits, here we don't care about bits outside
9841 MODE. */
9845 /* Turn off all bits in the constant that are known to already be zero.
9846 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9847 which is tested below. */
9851 /* If we don't have any bits left, return zero. */
9855 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9856 a power of two, we can replace this with an ASHIFT. */
9861 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9862 or XOR, then try to apply the distributive law. This may eliminate
9863 operations if either branch can be simplified because of the AND.
9864 It may also make some cases more complex, but those cases probably
9865 won't match a pattern either with or without this. */
9868 return
9869 gen_lowpart
9871 apply_distributive_law
9876 constop),
9880 constop))));
9882 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9883 the AND and see if one of the operands simplifies to zero. If so, we
9884 may eliminate it. */
9888 {
9897 }
9899 /* Make a SUBREG if necessary. If we can't make it, fail. */
9904 /* If we are only masking insignificant bits, return VAROP. */
9911 /* Otherwise, return an AND. */
9913 }
9916 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9917 in MODE.
9919 Return an equivalent form, if different from X. Otherwise, return X. If
9920 X is zero, we are to always construct the equivalent form. */
9922 static rtx
9925 {
9936 }
9937 \f
9938 /* Given a REG, X, compute which bits in X can be nonzero.
9939 We don't care about bits outside of those defined in MODE.
9941 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9942 a shift, AND, or zero_extract, we can do better. */
9944 static rtx
9946 const_rtx known_x ATTRIBUTE_UNUSED,
9947 machine_mode known_mode ATTRIBUTE_UNUSED,
9950 {
9951 rtx tem;
9954 /* If X is a register whose nonzero bits value is current, use it.
9955 Otherwise, if X is a register whose value we can find, use that
9956 value. Otherwise, use the previously-computed global nonzero bits
9957 for this register. */
9971 && !REGNO_REG_SET_P
9974 {
9975 /* Note that, even if the precision of last_set_mode is lower than that
9976 of mode, record_value_for_reg invoked nonzero_bits on the register
9977 with nonzero_bits_mode (because last_set_mode is necessarily integral
9978 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9979 are all valid, hence in mode too since nonzero_bits_mode is defined
9980 to the largest HWI_COMPUTABLE_MODE_P mode. */
9983 }
9987 {
9993 }
9996 {
10000 /* We don't know anything about the upper bits. */
10004 }
10007 }
10009 /* Return the number of bits at the high-order end of X that are known to
10010 be equal to the sign bit. X will be used in mode MODE; if MODE is
10011 VOIDmode, X will be used in its own mode. The returned value will always
10012 be between 1 and the number of bits in MODE. */
10014 static rtx
10016 const_rtx known_x ATTRIBUTE_UNUSED,
10017 machine_mode known_mode
10018 ATTRIBUTE_UNUSED,
10021 {
10022 rtx tem;
10035 && !REGNO_REG_SET_P
10038 {
10041 }
10052 }
10053 \f
10054 /* Return the number of "extended" bits there are in X, when interpreted
10055 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10056 unsigned quantities, this is the number of high-order zero bits.
10057 For signed quantities, this is the number of copies of the sign bit
10058 minus 1. In both case, this function returns the number of "spare"
10059 bits. For example, if two quantities for which this function returns
10060 at least 1 are added, the addition is known not to overflow.
10062 This function will always return 0 unless called during combine, which
10063 implies that it must be called from a define_split. */
10065 unsigned int
10067 {
10077 }
10079 /* This function is called from `simplify_shift_const' to merge two
10080 outer operations. Specifically, we have already found that we need
10081 to perform operation *POP0 with constant *PCONST0 at the outermost
10082 position. We would now like to also perform OP1 with constant CONST1
10083 (with *POP0 being done last).
10085 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10086 the resulting operation. *PCOMP_P is set to 1 if we would need to
10087 complement the innermost operand, otherwise it is unchanged.
10089 MODE is the mode in which the operation will be done. No bits outside
10090 the width of this mode matter. It is assumed that the width of this mode
10091 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10093 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10094 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10095 result is simply *PCONST0.
10097 If the resulting operation cannot be expressed as one operation, we
10098 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10100 static int
10101 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10102 {
10109 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10113 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10114 if OP0 is SET. */
10123 {
10125 {
10143 }
10144 }
10146 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10150 /* If the two constants aren't the same, we can't do anything. The
10151 remaining six cases can all be done. */
10155 else
10157 {
10160 /* (a & b) | b == b */
10163 /* (a ^ b) | b == a | b */
10164 {;}
10169 /* (a & b) ^ b == (~a) & b */
10172 /* (a | b) ^ b == a & ~b */
10178 /* (a | b) & b == b */
10181 /* (a ^ b) & b) == (~a) & b */
10186 }
10188 /* Check for NO-OP cases. */
10201 /* ??? Slightly redundant with the above mask, but not entirely.
10202 Moving this above means we'd have to sign-extend the mode mask
10203 for the final test. */
10208 }
10209 \f
10210 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10211 the shift in. The original shift operation CODE is performed on OP in
10212 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10213 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10214 result of the shift is subject to operation OUTER_CODE with operand
10215 OUTER_CONST. */
10217 static machine_mode
10221 {
10226 /* In general we can't perform in wider mode for right shift and rotate. */
10228 {
10230 /* We can still widen if the bits brought in from the left are identical
10231 to the sign bit of ORIG_MODE. */
10239 /* Similarly here but with zero bits. */
10244 /* We can also widen if the bits brought in will be masked off. This
10245 operation is performed in ORIG_MODE. */
10247 {
10253 }
10254 /* fall through */
10264 }
10265 }
10267 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10268 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10269 if we cannot simplify it. Otherwise, return a simplified value.
10271 The shift is normally computed in the widest mode we find in VAROP, as
10272 long as it isn't a different number of words than RESULT_MODE. Exceptions
10273 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10275 static rtx
10278 {
10284 unsigned int mode_words
10286 /* We form (outer_op (code varop count) (outer_const)). */
10292 /* Make sure and truncate the "natural" shift on the way in. We don't
10293 want to do this inside the loop as it makes it more difficult to
10294 combine shifts. */
10298 /* If we were given an invalid count, don't do anything except exactly
10299 what was requested. */
10306 /* Unless one of the branches of the `if' in this loop does a `continue',
10307 we will `break' the loop after the `if'. */
10310 {
10311 /* If we have an operand of (clobber (const_int 0)), fail. */
10315 /* Convert ROTATERT to ROTATE. */
10317 {
10321 }
10327 /* Handle cases where the count is greater than the size of the mode
10328 minus 1. For ASHIFT, use the size minus one as the count (this can
10329 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10330 take the count modulo the size. For other shifts, the result is
10331 zero.
10333 Since these shifts are being produced by the compiler by combining
10334 multiple operations, each of which are defined, we know what the
10335 result is supposed to be. */
10338 {
10343 else
10344 {
10345 /* We can't simply return zero because there may be an
10346 outer op. */
10350 }
10351 }
10353 /* If we discovered we had to complement VAROP, leave. Making a NOT
10354 here would cause an infinite loop. */
10359 {
10360 /* An arithmetic right shift of a quantity known to be -1 or 0
10361 is a no-op. */
10365 {
10368 }
10370 /* If we are doing an arithmetic right shift and discarding all but
10371 the sign bit copies, this is equivalent to doing a shift by the
10372 bitsize minus one. Convert it into that shift because it will
10373 often allow other simplifications. */
10380 /* We simplify the tests below and elsewhere by converting
10381 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10382 `make_compound_operation' will convert it to an ASHIFTRT for
10383 those machines (such as VAX) that don't have an LSHIFTRT. */
10388 shift_unit_mode)))
10400 }
10403 {
10410 {
10413 }
10417 /* The following rules apply only to scalars. */
10421 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10422 minus the width of a smaller mode, we can do this with a
10423 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10430 {
10439 }
10443 /* The following rules apply only to scalars. */
10447 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10448 the same number of words as what we've seen so far. Then store
10449 the widest mode in MODE. */
10455 == mode_words
10458 {
10463 }
10467 /* Some machines use MULT instead of ASHIFT because MULT
10468 is cheaper. But it is still better on those machines to
10469 merge two shifts into one. */
10472 {
10473 varop
10479 }
10483 /* Similar, for when divides are cheaper. */
10486 {
10487 varop
10493 }
10497 /* If we are extracting just the sign bit of an arithmetic
10498 right shift, that shift is not needed. However, the sign
10499 bit of a wider mode may be different from what would be
10500 interpreted as the sign bit in a narrower mode, so, if
10501 the result is narrower, don't discard the shift. */
10506 {
10509 }
10511 /* fall through */
10516 /* The following rules apply only to scalars. */
10520 /* Here we have two nested shifts. The result is usually the
10521 AND of a new shift with a mask. We compute the result below. */
10527 {
10531 rtx mask_rtx;
10533 /* We have one common special case. We can't do any merging if
10534 the inner code is an ASHIFTRT of a smaller mode. However, if
10535 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10536 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10537 we can convert it to
10538 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10539 This simplifies certain SIGN_EXTEND operations. */
10543 {
10544 /* C3 has the low-order C1 bits zero. */
10556 }
10558 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10559 than C1 high-order bits equal to the sign bit, we can convert
10560 this to either an ASHIFT or an ASHIFTRT depending on the
10561 two counts.
10563 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10569 {
10573 {
10576 }
10579 }
10581 /* There are some cases we can't do. If CODE is ASHIFTRT,
10582 we can only do this if FIRST_CODE is also ASHIFTRT.
10584 We can't do the case when CODE is ROTATE and FIRST_CODE is
10585 ASHIFTRT.
10587 If the mode of this shift is not the mode of the outer shift,
10588 we can't do this if either shift is a right shift or ROTATE.
10590 Finally, we can't do any of these if the mode is too wide
10591 unless the codes are the same.
10593 Handle the case where the shift codes are the same
10594 first. */
10597 {
10606 }
10617 /* To compute the mask to apply after the shift, shift the
10618 nonzero bits of the inner shift the same way the
10619 outer shift will. */
10622 result_mode);
10624 mask_rtx
10628 /* Give up if we can't compute an outer operation to use. */
10636 /* If the shifts are in the same direction, we add the
10637 counts. Otherwise, we subtract them. */
10641 else
10644 /* If COUNT is positive, the new shift is usually CODE,
10645 except for the two exceptions below, in which case it is
10646 FIRST_CODE. If the count is negative, FIRST_CODE should
10647 always be used */
10657 }
10659 /* If we have (A << B << C) for any shift, we can convert this to
10660 (A << C << B). This wins if A is a constant. Only try this if
10661 B is not a constant. */
10666 {
10667 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10668 sure the result will be masked. See PR70222. */
10676 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10677 up outer sign extension (often left and right shift) is
10678 hardly more efficient than the original. See PR70429. */
10688 }
10692 /* The following rules apply only to scalars. */
10696 /* Make this fit the case below. */
10703 /* The following rules apply only to scalars. */
10707 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10708 with C the size of VAROP - 1 and the shift is logical if
10709 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10710 we have an (le X 0) operation. If we have an arithmetic shift
10711 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10712 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10720 {
10723 const0_rtx);
10729 }
10731 /* If we have (shift (logical)), move the logical to the outside
10732 to allow it to possibly combine with another logical and the
10733 shift to combine with another shift. This also canonicalizes to
10734 what a ZERO_EXTRACT looks like. Also, some machines have
10735 (and (shift)) insns. */
10738 /* We can't do this if we have (ashiftrt (xor)) and the
10739 constant has its sign bit set in shift_mode with shift_mode
10740 wider than result_mode. */
10744 shift_mode))
10752 {
10755 }
10757 /* If we can't do that, try to simplify the shift in each arm of the
10758 logical expression, make a new logical expression, and apply
10759 the inverse distributive law. This also can't be done for
10760 (ashiftrt (xor)) where we've widened the shift and the constant
10761 changes the sign bit. */
10766 shift_mode)))
10767 {
10779 }
10783 /* The following rules apply only to scalars. */
10787 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10788 says that the sign bit can be tested, FOO has mode MODE, C is
10789 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10790 that may be nonzero. */
10800 {
10804 }
10808 /* The following rules apply only to scalars. */
10812 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10813 than the number of bits in the mode is equivalent to A. */
10817 {
10821 }
10823 /* NEG commutes with ASHIFT since it is multiplication. Move the
10824 NEG outside to allow shifts to combine. */
10828 {
10831 }
10835 /* The following rules apply only to scalars. */
10839 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10840 is one less than the number of bits in the mode is
10841 equivalent to (xor A 1). */
10848 {
10852 }
10854 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10855 that might be nonzero in BAR are those being shifted out and those
10856 bits are known zero in FOO, we can replace the PLUS with FOO.
10857 Similarly in the other operand order. This code occurs when
10858 we are computing the size of a variable-size array. */
10865 {
10868 }
10876 result_mode)))
10877 {
10880 }
10882 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10892 {
10895 }
10897 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10898 signbit', and attempt to change the PLUS to an XOR and move it to
10899 the outer operation as is done above in the AND/IOR/XOR case
10900 leg for shift(logical). See details in logical handling above
10901 for reasoning in doing so. */
10912 {
10915 }
10920 /* The following rules apply only to scalars. */
10924 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10925 with C the size of VAROP - 1 and the shift is logical if
10926 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10927 we have a (gt X 0) operation. If the shift is arithmetic with
10928 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10929 we have a (neg (gt X 0)) operation. */
10938 {
10941 const0_rtx);
10947 }
10951 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10952 if the truncate does not affect the value. */
10959 {
10962 varop_inner
10965 GEN_INT
10970 }
10975 }
10978 }
10983 /* We have now finished analyzing the shift. The result should be
10984 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10985 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10986 to the result of the shift. OUTER_CONST is the relevant constant,
10987 but we must turn off all bits turned off in the shift. */
10995 /* Make a SUBREG if necessary. If we can't make it, fail. */
11000 /* If we have an outer operation and we just made a shift, it is
11001 possible that we could have simplified the shift were it not
11002 for the outer operation. So try to do the simplification
11003 recursively. */
11007 else
11013 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11014 turn off all the bits that the shift would have turned off. */
11019 /* Do the remainder of the processing in RESULT_MODE. */
11022 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11023 operation. */
11028 {
11036 {
11037 /* This means that we have determined that the result is
11038 equivalent to a constant. This should be rare. */
11041 }
11044 else
11047 }
11050 }
11052 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11053 The result of the shift is RESULT_MODE. If we cannot simplify it,
11054 return X or, if it is NULL, synthesize the expression with
11055 simplify_gen_binary. Otherwise, return a simplified value.
11057 The shift is normally computed in the widest mode we find in VAROP, as
11058 long as it isn't a different number of words than RESULT_MODE. Exceptions
11059 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11061 static rtx
11064 {
11074 }
11076 \f
11077 /* A subroutine of recog_for_combine. See there for arguments and
11078 return value. */
11080 static int
11082 {
11084 rtx pat_without_clobbers;
11092 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11093 we use to indicate that something didn't match. If we find such a
11094 thing, force rejection. */
11108 {
11111 else
11114 }
11116 /* If it isn't, there is the possibility that we previously had an insn
11117 that clobbered some register as a side effect, but the combined
11118 insn doesn't need to do that. So try once more without the clobbers
11119 unless this represents an ASM insn. */
11123 {
11128 {
11131 pos++;
11132 }
11142 {
11145 else
11148 }
11149 }
11156 /* Recognize all noop sets, these will be killed by followup pass. */
11160 /* If we had any clobbers to add, make a new pattern than contains
11161 them. Then check to make sure that all of them are dead. */
11163 {
11173 else
11180 {
11185 {
11189 }
11190 }
11192 }
11196 {
11203 /* Allow targets to reject combined insn. */
11205 {
11208 dump_file);
11210 /* Callers expect recog_for_combine to strip
11211 clobbers from the pattern on failure. */
11216 }
11221 }
11227 }
11229 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11230 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11231 Return whether anything was so changed. */
11233 static bool
11235 {
11241 {
11252 {
11263 else
11267 }
11274 {
11279 }
11285 {
11288 }
11289 else
11297 }
11308 {
11323 else
11331 }
11334 }
11336 /* Like recog, but we receive the address of a pointer to a new pattern.
11337 We try to match the rtx that the pointer points to.
11338 If that fails, we may try to modify or replace the pattern,
11339 storing the replacement into the same pointer object.
11341 Modifications include deletion or addition of CLOBBERs. If the
11342 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11343 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11344 (and undo if that fails).
11346 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11347 the CLOBBERs are placed.
11349 The value is the final insn code from the pattern ultimately matched,
11350 or -1. */
11352 static int
11354 {
11366 {
11369 {
11373 }
11374 }
11377 {
11382 }
11385 }
11386 \f
11387 /* Like gen_lowpart_general but for use by combine. In combine it
11388 is not possible to create any new pseudoregs. However, it is
11389 safe to create invalid memory addresses, because combine will
11390 try to recognize them and all they will do is make the combine
11391 attempt fail.
11393 If for some reason this cannot do its job, an rtx
11394 (clobber (const_int 0)) is returned.
11395 An insn containing that will not be recognized. */
11397 static rtx
11399 {
11403 rtx result;
11408 /* We can only support MODE being wider than a word if X is a
11409 constant integer or has a mode the same size. */
11414 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11415 won't know what to do. So we will strip off the SUBREG here and
11416 process normally. */
11418 {
11421 /* For use in case we fall down into the address adjustments
11422 further below, we need to adjust the known mode and size of
11423 x; imode and isize, since we just adjusted x. */
11430 }
11438 {
11441 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11442 address. */
11447 /* If we want to refer to something bigger than the original memref,
11448 generate a paradoxical subreg instead. That will force a reload
11449 of the original memref X. */
11456 /* Adjust the address so that the address-after-the-data is
11457 unchanged. */
11462 }
11464 /* If X is a comparison operator, rewrite it in a new mode. This
11465 probably won't match, but may allow further simplifications. */
11469 /* If we couldn't simplify X any other way, just enclose it in a
11470 SUBREG. Normally, this SUBREG won't match, but some patterns may
11471 include an explicit SUBREG or we may simplify it further in combine. */
11472 else
11473 {
11474 rtx res;
11477 {
11482 }
11486 }
11488 fail:
11490 }
11491 \f
11492 /* Try to simplify a comparison between OP0 and a constant OP1,
11493 where CODE is the comparison code that will be tested, into a
11494 (CODE OP0 const0_rtx) form.
11496 The result is a possibly different comparison code to use.
11497 *POP1 may be updated. */
11499 static enum rtx_code
11502 {
11506 /* Get the constant we are comparing against and turn off all bits
11507 not on in our mode. */
11511 /* If we are comparing against a constant power of two and the value
11512 being compared can only have that single bit nonzero (e.g., it was
11513 `and'ed with that bit), we can replace this with a comparison
11514 with zero. */
11522 {
11525 }
11527 /* Similarly, if we are comparing a value known to be either -1 or
11528 0 with -1, change it to the opposite comparison against zero. */
11533 {
11536 }
11538 /* Do some canonicalizations based on the comparison code. We prefer
11539 comparisons against zero and then prefer equality comparisons.
11540 If we can reduce the size of a constant, we will do that too. */
11542 {
11544 /* < C is equivalent to <= (C - 1) */
11546 {
11549 /* ... fall through to LE case below. */
11551 }
11552 else
11556 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11558 {
11561 }
11563 /* If we are doing a <= 0 comparison on a value known to have
11564 a zero sign bit, we can replace this with == 0. */
11574 /* >= C is equivalent to > (C - 1). */
11576 {
11579 /* ... fall through to GT below. */
11581 }
11582 else
11586 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11588 {
11591 }
11593 /* If we are doing a > 0 comparison on a value known to have
11594 a zero sign bit, we can replace this with != 0. */
11604 /* < C is equivalent to <= (C - 1). */
11606 {
11609 /* ... fall through ... */
11610 }
11611 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11615 {
11619 }
11620 else
11624 /* unsigned <= 0 is equivalent to == 0 */
11627 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11631 {
11634 }
11638 /* >= C is equivalent to > (C - 1). */
11640 {
11643 /* ... fall through ... */
11644 }
11646 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11650 {
11654 }
11655 else
11659 /* unsigned > 0 is equivalent to != 0 */
11662 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11666 {
11669 }
11674 }
11678 }
11679 \f
11680 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11681 comparison code that will be tested.
11683 The result is a possibly different comparison code to use. *POP0 and
11684 *POP1 may be updated.
11686 It is possible that we might detect that a comparison is either always
11687 true or always false. However, we do not perform general constant
11688 folding in combine, so this knowledge isn't useful. Such tautologies
11689 should have been detected earlier. Hence we ignore all such cases. */
11691 static enum rtx_code
11693 {
11700 /* Try a few ways of applying the same transformation to both operands. */
11702 {
11703 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11704 so check specially. */
11720 - (GET_MODE_PRECISION
11722 {
11725 }
11727 /* If both operands are the same constant shift, see if we can ignore the
11728 shift. We can if the shift is a rotate or if the bits shifted out of
11729 this shift are known to be zero for both inputs and if the type of
11730 comparison is compatible with the shift. */
11743 {
11756 else
11758 }
11760 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11761 SUBREGs are of the same mode, and, in both cases, the AND would
11762 be redundant if the comparison was done in the narrower mode,
11763 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11764 and the operand's possibly nonzero bits are 0xffffff01; in that case
11765 if we only care about QImode, we don't need the AND). This case
11766 occurs if the output mode of an scc insn is not SImode and
11767 STORE_FLAG_VALUE == 1 (e.g., the 386).
11769 Similarly, check for a case where the AND's are ZERO_EXTEND
11770 operations from some narrower mode even though a SUBREG is not
11771 present. */
11776 {
11793 {
11797 /* The resulting comparison is always unsigned since we masked
11798 off the original sign bit. */
11802 }
11809 {
11815 }
11819 }
11821 /* If both operands are NOT, we can strip off the outer operation
11822 and adjust the comparison code for swapped operands; similarly for
11823 NEG, except that this must be an equality comparison. */
11829 else
11831 }
11833 /* If the first operand is a constant, swap the operands and adjust the
11834 comparison code appropriately, but don't do this if the second operand
11835 is already a constant integer. */
11837 {
11840 }
11842 /* We now enter a loop during which we will try to simplify the comparison.
11843 For the most part, we only are concerned with comparisons with zero,
11844 but some things may really be comparisons with zero but not start
11845 out looking that way. */
11848 {
11855 HOST_WIDE_INT const_op;
11857 /* We only want to handle integral modes. This catches VOIDmode,
11858 CCmode, and the floating-point modes. An exception is that we
11859 can handle VOIDmode if OP0 is a COMPARE or a comparison
11860 operation. */
11867 /* Try to simplify the compare to constant, possibly changing the
11868 comparison op, and/or changing op1 to zero. */
11872 /* Compute some predicates to simplify code below. */
11879 /* If this is a sign bit comparison and we can do arithmetic in
11880 MODE, say that we will only be needing the sign bit of OP0. */
11883 HOST_WIDE_INT_1U
11887 /* Now try cases based on the opcode of OP0. If none of the cases
11888 does a "continue", we exit this loop immediately after the
11889 switch. */
11892 {
11894 /* If we are extracting a single bit from a variable position in
11895 a constant that has only a single bit set and are comparing it
11896 with zero, we can convert this into an equality comparison
11897 between the position and the location of the single bit. */
11898 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11899 have already reduced the shift count modulo the word size. */
11905 {
11913 /* Result is nonzero iff shift count is equal to I. */
11916 }
11918 /* fall through */
11923 {
11926 }
11930 /* If testing for equality, we can take the NOT of the constant. */
11933 {
11937 }
11939 /* If just looking at the sign bit, reverse the sense of the
11940 comparison. */
11942 {
11946 }
11950 /* If testing for equality, we can take the NEG of the constant. */
11953 {
11957 }
11959 /* The remaining cases only apply to comparisons with zero. */
11963 /* When X is ABS or is known positive,
11964 (neg X) is < 0 if and only if X != 0. */
11972 {
11976 }
11978 /* If we have NEG of something whose two high-order bits are the
11979 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11981 {
11985 }
11989 /* If we are testing equality and our count is a constant, we
11990 can perform the inverse operation on our RHS. */
11994 {
11998 }
12000 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12001 a particular bit. Convert it to an AND of a constant of that
12002 bit. This will be converted into a ZERO_EXTRACT. */
12006 {
12008 (HOST_WIDE_INT_1U
12013 }
12015 /* Fall through. */
12018 /* ABS is ignorable inside an equality comparison with zero. */
12020 {
12023 }
12027 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12028 (compare FOO CONST) if CONST fits in FOO's mode and we
12029 are either testing inequality or have an unsigned
12030 comparison with ZERO_EXTEND or a signed comparison with
12031 SIGN_EXTEND. But don't do it if we don't have a compare
12032 insn of the given mode, since we'd have to revert it
12033 later on, and then we wouldn't know whether to sign- or
12034 zero-extend. */
12037 && ! unsigned_comparison_p
12041 {
12044 }
12048 /* Check for the case where we are comparing A - C1 with C2, that is
12050 (subreg:MODE (plus (A) (-C1))) op (C2)
12052 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12053 comparison in the wider mode. One of the following two conditions
12054 must be true in order for this to be valid:
12056 1. The mode extension results in the same bit pattern being added
12057 on both sides and the comparison is equality or unsigned. As
12058 C2 has been truncated to fit in MODE, the pattern can only be
12059 all 0s or all 1s.
12061 2. The mode extension results in the sign bit being copied on
12062 each side.
12064 The difficulty here is that we have predicates for A but not for
12065 (A - C1) so we need to check that C1 is within proper bounds so
12066 as to perturbate A as little as possible. */
12073 {
12082 /* (A - C1) zero-extends if it is positive and sign-extends
12083 if it is negative, C2 both zero- and sign-extends. */
12087 /* (A - C1) sign-extends if it is positive and 1-extends
12088 if it is negative, C2 both sign- and 1-extends. */
12095 /* (A - C1) always sign-extends, like C2. */
12099 {
12102 }
12103 }
12105 /* If the inner mode is narrower and we are extracting the low part,
12106 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12109 ;
12120 {
12121 /* Remove outer subregs that don't do anything. */
12126 {
12130 }
12132 }
12133 else
12136 /* FALLTHROUGH */
12146 {
12149 }
12153 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12154 this for equality comparisons due to pathological cases involving
12155 overflows. */
12159 {
12163 }
12165 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12168 {
12172 }
12176 /* We used to optimize signed comparisons against zero, but that
12177 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12178 arrive here as equality comparisons, or (GEU, LTU) are
12179 optimized away. No need to special-case them. */
12181 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12182 (eq B (minus A C)), whichever simplifies. We can only do
12183 this for equality comparisons due to pathological cases involving
12184 overflows. */
12188 {
12192 }
12197 {
12201 }
12203 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12204 of bits in X minus 1, is one iff X > 0. */
12209 {
12213 }
12217 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12218 if C is zero or B is a constant. */
12222 {
12226 }
12234 /* We can't do anything if OP0 is a condition code value, rather
12235 than an actual data value. */
12241 /* Get the two operands being compared. */
12244 else
12247 /* Check for the cases where we simply want the result of the
12248 earlier test or the opposite of that result. */
12252 {
12256 else
12260 {
12265 }
12266 }
12270 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12271 iff X <= 0. */
12275 {
12279 }
12283 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12284 will be converted to a ZERO_EXTRACT later. */
12288 {
12293 }
12295 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12296 zero and X is a comparison and C1 and C2 describe only bits set
12297 in STORE_FLAG_VALUE, we can compare with X. */
12305 {
12312 {
12315 }
12316 }
12318 /* If we are doing an equality comparison of an AND of a bit equal
12319 to the sign bit, replace this with a LT or GE comparison of
12320 the underlying value. */
12327 {
12331 }
12333 /* If this AND operation is really a ZERO_EXTEND from a narrower
12334 mode, the constant fits within that mode, and this is either an
12335 equality or unsigned comparison, try to do this comparison in
12336 the narrower mode.
12338 Note that in:
12340 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12341 -> (ne:DI (reg:SI 4) (const_int 0))
12343 unless TRULY_NOOP_TRUNCATION allows it or the register is
12344 known to hold a value of the required mode the
12345 transformation is invalid. */
12353 {
12356 }
12358 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12359 fits in both M1 and M2 and the SUBREG is either paradoxical
12360 or represents the low part, permute the SUBREG and the AND
12361 and try again. */
12364 {
12367 /* Require an integral mode, to avoid creating something like
12368 (AND:SF ...). */
12370 /* It is unsafe to commute the AND into the SUBREG if the
12371 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12372 not defined. As originally written the upper bits
12373 have a defined value due to the AND operation.
12374 However, if we commute the AND inside the SUBREG then
12375 they no longer have defined values and the meaning of
12376 the code has been changed.
12377 Also C1 should not change value in the smaller mode,
12378 see PR67028 (a positive C1 can become negative in the
12379 smaller mode, so that the AND does no longer mask the
12380 upper bits). */
12381 && ((WORD_REGISTER_OPERATIONS
12393 {
12399 }
12400 }
12402 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12406 {
12411 }
12413 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12414 (eq (and (lshiftrt X) 1) 0).
12415 Also handle the case where (not X) is expressed using xor. */
12419 {
12429 == HOST_WIDE_INT_1U
12431 {
12432 op0
12437 }
12438 }
12442 /* If we have (compare (ashift FOO N) (const_int C)) and
12443 the high order N bits of FOO (N+1 if an inequality comparison)
12444 are known to be zero, we can do this by comparing FOO with C
12445 shifted right N bits so long as the low-order N bits of C are
12446 zero. */
12458 {
12459 /* We must perform a logical shift, not an arithmetic one,
12460 as we want the top N bits of C to be zero. */
12467 }
12469 /* If we are doing a sign bit comparison, it means we are testing
12470 a particular bit. Convert it to the appropriate AND. */
12473 {
12475 (HOST_WIDE_INT_1U
12480 }
12482 /* If this an equality comparison with zero and we are shifting
12483 the low bit to the sign bit, we can convert this to an AND of the
12484 low-order bit. */
12488 {
12491 }
12495 /* If this is an equality comparison with zero, we can do this
12496 as a logical shift, which might be much simpler. */
12499 {
12504 }
12506 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12507 do the comparison in a narrower mode. */
12517 {
12520 }
12522 /* Likewise if OP0 is a PLUS of a sign extension with a
12523 constant, which is usually represented with the PLUS
12524 between the shifts. */
12536 {
12544 new_const);
12546 }
12548 /* FALLTHROUGH */
12550 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12551 the low order N bits of FOO are known to be zero, we can do this
12552 by comparing FOO with C shifted left N bits so long as no
12553 overflow occurs. Even if the low order N bits of FOO aren't known
12554 to be zero, if the comparison is >= or < we can use the same
12555 optimization and for > or <= by setting all the low
12556 order N bits in the comparison constant. */
12567 {
12568 unsigned HOST_WIDE_INT low_bits
12570 & ((HOST_WIDE_INT_1U
12573 {
12574 /* If the shift was logical, then we must make the condition
12575 unsigned. */
12584 const_op
12589 }
12590 }
12592 /* If we are using this shift to extract just the sign bit, we
12593 can replace this with an LT or GE comparison. */
12598 {
12602 }
12607 }
12610 }
12612 /* Now make any compound operations involved in this comparison. Then,
12613 check for an outmost SUBREG on OP0 that is not doing anything or is
12614 paradoxical. The latter transformation must only be performed when
12615 it is known that the "extra" bits will be the same in op0 and op1 or
12616 that they don't matter. There are three cases to consider:
12618 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12619 care bits and we can assume they have any convenient value. So
12620 making the transformation is safe.
12622 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12623 In this case the upper bits of op0 are undefined. We should not make
12624 the simplification in that case as we do not know the contents of
12625 those bits.
12627 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12628 In that case we know those bits are zeros or ones. We must also be
12629 sure that they are the same as the upper bits of op1.
12631 We can never remove a SUBREG for a non-equality comparison because
12632 the sign bit is in a different place in the underlying object. */
12645 {
12647 {
12648 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12649 implemented. */
12651 {
12654 }
12655 }
12661 {
12667 }
12668 }
12670 /* We now do the opposite procedure: Some machines don't have compare
12671 insns in all modes. If OP0's mode is an integer mode smaller than a
12672 word and we can't do a compare in that mode, see if there is a larger
12673 mode for which we can do the compare. There are a number of cases in
12674 which we can use the wider mode. */
12684 {
12687 /* If this is a test for negative, we can make an explicit
12688 test of the sign bit. Test this first so we can use
12689 a paradoxical subreg to extend OP0. */
12693 {
12694 unsigned HOST_WIDE_INT sign
12701 }
12703 /* If the only nonzero bits in OP0 and OP1 are those in the
12704 narrower mode and this is an equality or unsigned comparison,
12705 we can use the wider mode. Similarly for sign-extended
12706 values, in which case it is true for all comparisons. */
12723 {
12724 /* If OP0 is an AND and we don't have an AND in MODE either,
12725 make a new AND in the proper mode. */
12733 else
12734 {
12736 {
12739 }
12740 else
12741 {
12744 }
12746 }
12747 }
12748 }
12750 /* We may have changed the comparison operands. Re-canonicalize. */
12752 {
12755 }
12757 /* If this machine only supports a subset of valid comparisons, see if we
12758 can convert an unsupported one into a supported one. */
12765 }
12766 \f
12767 /* Utility function for record_value_for_reg. Count number of
12768 rtxs in X. */
12769 static int
12771 {
12778 {
12798 }
12809 }
12810 \f
12811 /* Utility function for following routine. Called when X is part of a value
12812 being stored into last_set_value. Sets last_set_table_tick
12813 for each register mentioned. Similar to mention_regs in cse.c */
12815 static void
12817 {
12823 {
12829 {
12832 }
12835 }
12839 {
12840 /* Check for identical subexpressions. If x contains
12841 identical subexpression we only have to traverse one of
12842 them. */
12844 {
12845 /* Note that at this point x1 has already been
12846 processed. */
12850 /* If x0 and x1 are identical then there is no need to
12851 process x0. */
12855 /* If x0 is identical to a subexpression of x1 then while
12856 processing x1, x0 has already been processed. Thus we
12857 are done with x. */
12862 /* If x1 is identical to a subexpression of x0 then we
12863 still have to process the rest of x0. */
12866 {
12869 }
12870 }
12873 }
12877 }
12879 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12880 are saying that the register is clobbered and we no longer know its
12881 value. If INSN is zero, don't update reg_stat[].last_set; this is
12882 only permitted with VALUE also zero and is used to invalidate the
12883 register. */
12885 static void
12887 {
12893 /* If VALUE contains REG and we have a previous value for REG, substitute
12894 the previous value. */
12896 {
12897 rtx tem;
12899 /* Set things up so get_last_value is allowed to see anything set up to
12900 our insn. */
12904 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12905 it isn't going to be useful and will take a lot of time to process,
12906 so just use the CLOBBER. */
12909 {
12915 {
12916 /* If there are two or more occurrences of REG in VALUE,
12917 prevent the value from growing too much. */
12920 }
12923 }
12924 }
12926 /* For each register modified, show we don't know its value, that
12927 we don't know about its bitwise content, that its value has been
12928 updated, and that we don't know the location of the death of the
12929 register. */
12931 {
12943 }
12945 /* Mark registers that are being referenced in this value. */
12949 /* Now update the status of each register being set.
12950 If someone is using this register in this block, set this register
12951 to invalid since we will get confused between the two lives in this
12952 basic block. This makes using this register always invalid. In cse, we
12953 scan the table to invalidate all entries using this register, but this
12954 is too much work for us. */
12957 {
12963 else
12965 }
12967 /* The value being assigned might refer to X (like in "x++;"). In that
12968 case, we must replace it with (clobber (const_int 0)) to prevent
12969 infinite loops. */
12972 {
12976 }
12978 /* For the main register being modified, update the value, the mode, the
12979 nonzero bits, and the number of sign bit copies. */
12984 {
12992 rsp->last_set_sign_bit_copies
12994 }
12995 }
12997 /* Called via note_stores from record_dead_and_set_regs to handle one
12998 SET or CLOBBER in an insn. DATA is the instruction in which the
12999 set is occurring. */
13001 static void
13003 {
13010 {
13014 }
13017 {
13018 /* If we are setting the whole register, we know its value. Otherwise
13019 show that we don't know the value. We can handle SUBREG in
13020 some cases. */
13031 else
13033 }
13035 /* Ignore pushes, they clobber nothing. */
13038 }
13040 /* Update the records of when each REG was most recently set or killed
13041 for the things done by INSN. This is the last thing done in processing
13042 INSN in the combiner loop.
13044 We update reg_stat[], in particular fields last_set, last_set_value,
13045 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13046 last_death, and also the similar information mem_last_set (which insn
13047 most recently modified memory) and last_call_luid (which insn was the
13048 most recent subroutine call). */
13050 static void
13052 {
13053 rtx link;
13057 {
13060 {
13065 {
13070 }
13071 }
13074 }
13077 {
13078 hard_reg_set_iterator hrsi;
13080 {
13092 }
13096 /* We can't combine into a call pattern. Remember, though, that
13097 the return value register is set at this LUID. We could
13098 still replace a register with the return value from the
13099 wrong subroutine call! */
13101 }
13102 else
13104 }
13106 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13107 register present in the SUBREG, so for each such SUBREG go back and
13108 adjust nonzero and sign bit information of the registers that are
13109 known to have some zero/sign bits set.
13111 This is needed because when combine blows the SUBREGs away, the
13112 information on zero/sign bits is lost and further combines can be
13113 missed because of that. */
13115 static void
13117 {
13119 rtx set;
13127 {
13136 {
13139 }
13143 {
13146 }
13149 {
13152 }
13153 else
13155 }
13156 }
13158 /* Check if X, a register, is known to contain a value already
13159 truncated to MODE. In this case we can use a subreg to refer to
13160 the truncated value even though in the generic case we would need
13161 an explicit truncation. */
13163 static bool
13165 {
13177 }
13179 /* If X is a hard reg or a subreg record the mode that the register is
13180 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13181 to turn a truncate into a subreg using this information. Return true
13182 if traversing X is complete. */
13184 static bool
13186 {
13187 machine_mode truncated_mode;
13191 {
13202 }
13203 /* ??? For hard-regs we now record everything. We might be able to
13204 optimize this using last_set_mode. */
13207 else
13215 {
13218 }
13221 }
13223 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13224 the modes they are used in. This can help truning TRUNCATEs into
13225 SUBREGs. */
13227 static void
13229 {
13234 }
13236 /* Scan X for promoted SUBREGs. For each one found,
13237 note what it implies to the registers used in it. */
13239 static void
13241 {
13246 else
13247 {
13253 {
13263 }
13264 }
13265 }
13266 \f
13267 /* Verify that all the registers and memory references mentioned in *LOC are
13268 still valid. *LOC was part of a value set in INSN when label_tick was
13269 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13270 the invalid references with (clobber (const_int 0)) and return 1. This
13271 replacement is useful because we often can get useful information about
13272 the form of a value (e.g., if it was produced by a shift that always
13273 produces -1 or 0) even though we don't know exactly what registers it
13274 was produced from. */
13276 static int
13278 {
13285 {
13291 {
13294 /* If this is a pseudo-register that was only set once and not
13295 live at the beginning of the function, it is always valid. */
13299 && (!REGNO_REG_SET_P
13301 regno)))
13303 {
13307 }
13308 }
13311 }
13312 /* If this is a memory reference, make sure that there were no stores after
13313 it that might have clobbered the value. We don't have alias info, so we
13314 assume any store invalidates it. Moreover, we only have local UIDs, so
13315 we also assume that there were stores in the intervening basic blocks. */
13318 {
13322 }
13325 {
13327 {
13328 /* Check for identical subexpressions. If x contains
13329 identical subexpression we only have to traverse one of
13330 them. */
13332 {
13333 /* Note that at this point x0 has already been checked
13334 and found valid. */
13338 /* If x0 and x1 are identical then x is also valid. */
13342 /* If x1 is identical to a subexpression of x0 then
13343 while checking x0, x1 has already been checked. Thus
13344 it is valid and so as x. */
13349 /* If x0 is identical to a subexpression of x1 then x is
13350 valid iff the rest of x1 is valid. */
13353 return
13357 }
13362 }
13368 }
13370 /* If we haven't found a reason for it to be invalid, it is valid. */
13372 }
13374 /* Get the last value assigned to X, if known. Some registers
13375 in the value may be replaced with (clobber (const_int 0)) if their value
13376 is known longer known reliably. */
13378 static rtx
13380 {
13382 rtx value;
13385 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13386 then convert it to the desired mode. If this is a paradoxical SUBREG,
13387 we cannot predict what values the "extra" bits might have. */
13401 /* If we don't have a value, or if it isn't for this basic block and
13402 it's either a hard register, set more than once, or it's a live
13403 at the beginning of the function, return 0.
13405 Because if it's not live at the beginning of the function then the reg
13406 is always set before being used (is never used without being set).
13407 And, if it's set only once, and it's always set before use, then all
13408 uses must have the same last value, even if it's not from this basic
13409 block. */
13416 || REGNO_REG_SET_P
13420 /* If the value was set in a later insn than the ones we are processing,
13421 we can't use it even if the register was only set once. */
13426 /* If fewer bits were set than what we are asked for now, we cannot use
13427 the value. */
13432 /* If the value has all its registers valid, return it. */
13436 /* Otherwise, make a copy and replace any invalid register with
13437 (clobber (const_int 0)). If that fails for some reason, return 0. */
13444 }
13445 \f
13446 /* Return nonzero if expression X refers to a REG or to memory
13447 that is set in an instruction more recent than FROM_LUID. */
13449 static int
13451 {
13457 {
13461 #ifdef PUSH_ROUNDING
13462 /* Don't allow uses of the stack pointer to be moved,
13463 because we don't know whether the move crosses a push insn. */
13466 #endif
13468 {
13474 }
13476 }
13484 {
13486 {
13491 }
13495 }
13497 }
13498 \f
13499 /* Define three variables used for communication between the following
13500 routines. */
13505 /* Function called via note_stores from reg_dead_at_p.
13507 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13508 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13510 static void
13512 {
13522 }
13524 /* Return nonzero if REG is known to be dead at INSN.
13526 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13527 referencing REG, it is dead. If we hit a SET referencing REG, it is
13528 live. Otherwise, see if it is live or dead at the start of the basic
13529 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13530 must be assumed to be always live. */
13532 static int
13534 {
13535 basic_block block;
13538 /* Set variables for reg_dead_at_p_1. */
13544 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13545 we allow the machine description to decide whether use-and-clobber
13546 patterns are OK. */
13548 {
13552 }
13554 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13555 beginning of basic block. */
13558 {
13560 {
13570 }
13576 }
13578 /* Look at live-in sets for the basic block that we were in. */
13584 }
13585 \f
13586 /* Note hard registers in X that are used. */
13588 static void
13590 {
13596 {
13600 CASE_CONST_ANY:
13605 /* CC0 must die in the insn after it is set, so we don't need to take
13606 special note of it here. */
13611 /* If we are clobbering a MEM, mark any hard registers inside the
13612 address as used. */
13619 /* A hard reg in a wide mode may really be multiple registers.
13620 If so, mark all of them just like the first. */
13622 {
13623 /* None of this applies to the stack, frame or arg pointers. */
13625 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13633 }
13637 {
13638 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13639 the address. */
13651 }
13656 }
13658 /* Recursively scan the operands of this expression. */
13660 {
13664 {
13668 {
13673 }
13674 }
13675 }
13676 }
13677 \f
13678 /* Remove register number REGNO from the dead registers list of INSN.
13680 Return the note used to record the death, if there was one. */
13682 rtx
13684 {
13691 }
13693 /* For each register (hardware or pseudo) used within expression X, if its
13694 death is in an instruction with luid between FROM_LUID (inclusive) and
13695 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13696 list headed by PNOTES.
13698 That said, don't move registers killed by maybe_kill_insn.
13700 This is done when X is being merged by combination into TO_INSN. These
13701 notes will then be distributed as needed. */
13703 static void
13706 {
13712 {
13716 /* Don't move the register if it gets killed in between from and to. */
13725 {
13728 /* It is possible for the call above to return 0. This can occur
13729 when last_death points to I2 or I1 that we combined with.
13730 In that case make a new note.
13732 We must also check for the case where X is a hard register
13733 and NOTE is a death note for a range of hard registers
13734 including X. In that case, we must put REG_DEAD notes for
13735 the remaining registers in place of NOTE. */
13740 {
13749 }
13751 /* If we didn't find any note, or if we found a REG_DEAD note that
13752 covers only part of the given reg, and we have a multi-reg hard
13753 register, then to be safe we must check for REG_DEAD notes
13754 for each register other than the first. They could have
13755 their own REG_DEAD notes lying around. */
13762 {
13769 else
13775 }
13778 {
13781 }
13782 else
13784 }
13787 }
13790 {
13795 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13796 that accesses one word of a multi-word item, some
13797 piece of everything register in the expression is used by
13798 this insn, so remove any old death. */
13799 /* ??? So why do we test for equality of the sizes? */
13808 {
13811 }
13813 /* If this is some other SUBREG, we know it replaces the entire
13814 value, so use that as the destination. */
13818 /* If this is a MEM, adjust deaths of anything used in the address.
13819 For a REG (the only other possibility), the entire value is
13820 being replaced so the old value is not used in this insn. */
13826 }
13835 {
13837 {
13842 }
13845 }
13846 }
13847 \f
13848 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13849 pattern of an insn. X must be a REG. */
13851 static int
13853 {
13857 {
13859 rtx target;
13866 else
13883 }
13891 }
13892 \f
13893 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13894 as appropriate. I3 and I2 are the insns resulting from the combination
13895 insns including FROM (I2 may be zero).
13897 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13898 not need REG_DEAD notes because they are being substituted for. This
13899 saves searching in the most common cases.
13901 Each note in the list is either ignored or placed on some insns, depending
13902 on the type of note. */
13904 static void
13907 {
13909 rtx tem_note;
13913 {
13918 {
13921 /* Doesn't matter much where we put this, as long as it's somewhere.
13922 It is preferable to keep these notes on branches, which is most
13923 likely to be i3. */
13930 else
13931 {
13934 }
13938 /* These notes must remain with the call or trapping instruction. */
13943 else
13944 {
13950 /* ??? Otherwise assume we've combined things such that we
13951 can now prove that the instructions can't trap. Drop the
13952 note in this case. */
13953 }
13957 /* ??? How to distribute between i3-i1. Assume i3 contains the
13958 entire adjustment. Assert i3 contains at least some adjust. */
13960 {
13962 /* fixup_args_size_notes looks at REG_NORETURN note,
13963 so ensure the note is placed there first. */
13965 {
13969 {
13975 }
13976 }
13978 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13979 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13982 && !ACCUMULATE_OUTGOING_ARGS
13984 }
13991 /* These notes must remain with the call. It should not be
13992 possible for both I2 and I3 to be a call. */
13995 else
13996 {
13999 }
14003 /* Any clobbers for i3 may still exist, and so we must process
14004 REG_UNUSED notes from that insn.
14006 Any clobbers from i2 or i1 can only exist if they were added by
14007 recog_for_combine. In that case, recog_for_combine created the
14008 necessary REG_UNUSED notes. Trying to keep any original
14009 REG_UNUSED notes from these insns can cause incorrect output
14010 if it is for the same register as the original i3 dest.
14011 In that case, we will notice that the register is set in i3,
14012 and then add a REG_UNUSED note for the destination of i3, which
14013 is wrong. However, it is possible to have REG_UNUSED notes from
14014 i2 or i1 for register which were both used and clobbered, so
14015 we keep notes from i2 or i1 if they will turn into REG_DEAD
14016 notes. */
14018 /* If this register is set or clobbered in I3, put the note there
14019 unless there is one already. */
14021 {
14029 }
14030 /* Otherwise, if this register is used by I3, then this register
14031 now dies here, so we must put a REG_DEAD note here unless there
14032 is one already. */
14038 {
14041 }
14047 /* These notes say something about results of an insn. We can
14048 only support them if they used to be on I3 in which case they
14049 remain on I3. Otherwise they are ignored.
14051 If the note refers to an expression that is not a constant, we
14052 must also ignore the note since we cannot tell whether the
14053 equivalence is still true. It might be possible to do
14054 slightly better than this (we only have a problem if I2DEST
14055 or I1DEST is present in the expression), but it doesn't
14056 seem worth the trouble. */
14064 /* These notes say something about how a register is used. They must
14065 be present on any use of the register in I2 or I3. */
14070 {
14073 else
14075 }
14080 /* This can show up in several ways -- either directly in the
14081 pattern, or hidden off in the constant pool with (or without?)
14082 a REG_EQUAL note. */
14083 /* ??? Ignore the without-reg_equal-note problem for now. */
14095 {
14098 else
14100 }
14102 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14103 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14104 there. */
14109 {
14116 }
14122 {
14130 }
14134 /* This note says something about the value of a register prior
14135 to the execution of an insn. It is too much trouble to see
14136 if the note is still correct in all situations. It is better
14137 to simply delete it. */
14141 /* If we replaced the right hand side of FROM_INSN with a
14142 REG_EQUAL note, the original use of the dying register
14143 will not have been combined into I3 and I2. In such cases,
14144 FROM_INSN is guaranteed to be the first of the combined
14145 instructions, so we simply need to search back before
14146 FROM_INSN for the previous use or set of this register,
14147 then alter the notes there appropriately.
14149 If the register is used as an input in I3, it dies there.
14150 Similarly for I2, if it is nonzero and adjacent to I3.
14152 If the register is not used as an input in either I3 or I2
14153 and it is not one of the registers we were supposed to eliminate,
14154 there are two possibilities. We might have a non-adjacent I2
14155 or we might have somehow eliminated an additional register
14156 from a computation. For example, we might have had A & B where
14157 we discover that B will always be zero. In this case we will
14158 eliminate the reference to A.
14160 In both cases, we must search to see if we can find a previous
14161 use of A and put the death note there. */
14167 else
14168 {
14179 && !(i2mod
14181 i2mod_old_rhs)))
14186 /* If the new I2 sets the same register that is marked dead
14187 in the note, we do not know where to put the note.
14188 Give up. */
14191 }
14194 {
14198 {
14200 {
14204 }
14206 /* If the register is being set at TEM_INSN, see if that is all
14207 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14208 into a REG_UNUSED note instead. Don't delete sets to
14209 global register vars. */
14213 {
14224 ;
14226 /* Verify that it was the set, and not a clobber that
14227 modified the register.
14229 CC0 targets must be careful to maintain setter/user
14230 pairs. If we cannot delete the setter due to side
14231 effects, mark the user with an UNUSED note instead
14232 of deleting it. */
14236 && (!HAVE_cc0
14240 {
14241 /* Move the notes and links of TEM_INSN elsewhere.
14242 This might delete other dead insns recursively.
14243 First set the pattern to something that won't use
14244 any register. */
14258 /* Delete the setter too. */
14260 {
14273 }
14274 }
14275 else
14276 {
14279 /* If there isn't already a REG_UNUSED note, put one
14280 here. Do not place a REG_DEAD note, even if
14281 the register is also used here; that would not
14282 match the algorithm used in lifetime analysis
14283 and can cause the consistency check in the
14284 scheduler to fail. */
14289 }
14290 }
14294 {
14297 /* If we are doing a 3->2 combination, and we have a
14298 register which formerly died in i3 and was not used
14299 by i2, which now no longer dies in i3 and is used in
14300 i2 but does not die in i2, and place is between i2
14301 and i3, then we may need to move a link from place to
14302 i2. */
14304 && from_insn
14307 {
14311 }
14313 }
14317 }
14319 }
14321 /* If the register is set or already dead at PLACE, we needn't do
14322 anything with this note if it is still a REG_DEAD note.
14323 We check here if it is set at all, not if is it totally replaced,
14324 which is what `dead_or_set_p' checks, so also check for it being
14325 set partially. */
14328 {
14334 {
14335 /* Unless the register previously died in PLACE, clear
14336 last_death. [I no longer understand why this is
14337 being done.] */
14341 }
14342 else
14345 /* If this is a death note for a hard reg that is occupying
14346 multiple registers, ensure that we are still using all
14347 parts of the object. If we find a piece of the object
14348 that is unused, we must arrange for an appropriate REG_DEAD
14349 note to be added for it. However, we can't just emit a USE
14350 and tag the note to it, since the register might actually
14351 be dead; so we recourse, and the recursive call then finds
14352 the previous insn that used this register. */
14355 {
14364 {
14367 }
14370 {
14371 /* Put only REG_DEAD notes for pieces that are
14372 not already dead or set. */
14376 {
14383 {
14385 NULL_RTX);
14389 NULL_RTX);
14390 }
14395 {
14397 {
14401 }
14405 {
14408 }
14409 }
14410 }
14413 }
14414 }
14415 }
14419 /* Any other notes should not be present at this point in the
14420 compilation. */
14422 }
14425 {
14428 }
14432 }
14433 }
14434 \f
14435 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14436 I3, I2, and I1 to new locations. This is also called to add a link
14437 pointing at I3 when I3's destination is changed. */
14439 static void
14441 {
14445 {
14452 /* If the insn that this link points to is a NOTE, ignore it. */
14461 {
14464 {
14480 }
14483 }
14484 else
14494 /* A LOG_LINK is defined as being placed on the first insn that uses
14495 a register and points to the insn that sets the register. Start
14496 searching at the next insn after the target of the link and stop
14497 when we reach a set of the register or the end of the basic block.
14499 Note that this correctly handles the link that used to point from
14500 I3 to I2. Also note that not much searching is typically done here
14501 since most links don't point very far away. */
14510 {
14514 }
14517 {
14520 }
14524 /* If we found a place to put the link, place it there unless there
14525 is already a link to the same insn as LINK at that point. */
14528 {
14536 {
14540 /* Set added_links_insn to the earliest insn we added a
14541 link to. */
14545 }
14546 }
14547 }
14548 }
14549 \f
14550 /* Check for any register or memory mentioned in EQUIV that is not
14551 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14552 of EXPR where some registers may have been replaced by constants. */
14554 static bool
14556 {
14559 {
14564 }
14566 }
14567 \f
14568 DEBUG_FUNCTION void
14570 {
14571 fprintf
14573 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14575 }
14577 void
14579 {
14580 fprintf
14582 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14584 }
14585 \f
14586 /* Try combining insns through substitution. */
14587 static unsigned int
14589 {
14599 rebuild_jump_labels_after_combine
14602 /* Combining insns may have turned an indirect jump into a
14603 direct jump. Rebuild the JUMP_LABEL fields of jumping
14604 instructions. */
14606 {
14613 }
14617 }
14622 {
14632 };
14635 {
14639 {}
14641 /* opt_pass methods: */
14644 {
14646 }
14652 rtl_opt_pass *
14654 {
14656 }