gcc/config/ia64/ia64.h

   1 /* Definitions of target machine GNU compiler.  IA-64 version.
   2    Copyright (C) 1999-2018 Free Software Foundation, Inc.
   3    Contributed by James E. Wilson <wilson@cygnus.com> and
   4                   David Mosberger <davidm@hpl.hp.com>.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* ??? Look at ABI group documents for list of preprocessor macros and
  23    other features required for ABI compliance.  */
  24
  25 /* ??? Functions containing a non-local goto target save many registers.  Why?
  26    See for instance execute/920428-2.c.  */
  27
  28 \f
  29 /* Run-time target specifications */
  30
  31 /* Target CPU builtins.  */
  32 #define TARGET_CPU_CPP_BUILTINS()               \
  33 do {                                            \
  34         builtin_assert("cpu=ia64");             \
  35         builtin_assert("machine=ia64");         \
  36         builtin_define("__ia64");               \
  37         builtin_define("__ia64__");             \
  38         builtin_define("__itanium__");          \
  39         if (TARGET_BIG_ENDIAN)                  \
  40           builtin_define("__BIG_ENDIAN__");     \
  41 } while (0)
  42
  43 #ifndef SUBTARGET_EXTRA_SPECS
  44 #define SUBTARGET_EXTRA_SPECS
  45 #endif
  46
  47 #define EXTRA_SPECS \
  48   { "asm_extra", ASM_EXTRA_SPEC }, \
  49   SUBTARGET_EXTRA_SPECS
  50
  51 #define CC1_SPEC "%(cc1_cpu) "
  52
  53 #define ASM_EXTRA_SPEC ""
  54
  55 /* Variables which are this size or smaller are put in the sdata/sbss
  56    sections.  */
  57 extern unsigned int ia64_section_threshold;
  58
  59 /* If the assembler supports thread-local storage, assume that the
  60    system does as well.  If a particular target system has an
  61    assembler that supports TLS -- but the rest of the system does not
  62    support TLS -- that system should explicit define TARGET_HAVE_TLS
  63    to false in its own configuration file.  */
  64 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
  65 #define TARGET_HAVE_TLS true
  66 #endif
  67
  68 #define TARGET_TLS14            (ia64_tls_size == 14)
  69 #define TARGET_TLS22            (ia64_tls_size == 22)
  70 #define TARGET_TLS64            (ia64_tls_size == 64)
  71
  72 #define TARGET_HPUX             0
  73 #define TARGET_HPUX_LD          0
  74
  75 #define TARGET_ABI_OPEN_VMS 0
  76
  77 #ifndef TARGET_ILP32
  78 #define TARGET_ILP32 0
  79 #endif
  80
  81 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
  82 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
  83 #endif
  84
  85 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
  86    TARGET_INLINE_SQRT.  */
  87
  88 enum ia64_inline_type
  89 {
  90   INL_NO = 0,
  91   INL_MIN_LAT = 1,
  92   INL_MAX_THR = 2
  93 };
  94
  95 /* Default target_flags if no switches are specified  */
  96
  97 #ifndef TARGET_DEFAULT
  98 #define TARGET_DEFAULT (MASK_DWARF2_ASM)
  99 #endif
 100
 101 #ifndef TARGET_CPU_DEFAULT
 102 #define TARGET_CPU_DEFAULT 0
 103 #endif
 104 \f
 105 /* Driver configuration */
 106
 107 /* A C string constant that tells the GCC driver program options to pass to
 108    `cc1'.  It can also specify how to translate options you give to GCC into
 109    options for GCC to pass to the `cc1'.  */
 110
 111 #undef CC1_SPEC
 112 #define CC1_SPEC "%{G*}"
 113
 114 /* A C string constant that tells the GCC driver program options to pass to
 115    `cc1plus'.  It can also specify how to translate options you give to GCC
 116    into options for GCC to pass to the `cc1plus'.  */
 117
 118 /* #define CC1PLUS_SPEC "" */
 119 \f
 120 /* Storage Layout */
 121
 122 /* Define this macro to have the value 1 if the most significant bit in a byte
 123    has the lowest number; otherwise define it to have the value zero.  */
 124
 125 #define BITS_BIG_ENDIAN 0
 126
 127 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 128
 129 /* Define this macro to have the value 1 if, in a multiword object, the most
 130    significant word has the lowest number.  */
 131
 132 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 133
 134 #define UNITS_PER_WORD 8
 135
 136 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
 137
 138 /* A C expression whose value is zero if pointers that need to be extended
 139    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
 140    they are zero-extended and negative one if there is a ptr_extend operation.
 141
 142    You need not define this macro if the `POINTER_SIZE' is equal to the width
 143    of `Pmode'.  */
 144 /* Need this for 32-bit pointers, see hpux.h for setting it.  */
 145 /* #define POINTERS_EXTEND_UNSIGNED */
 146
 147 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
 148    which has the specified mode and signedness is to be stored in a register.
 149    This macro is only called when TYPE is a scalar type.  */
 150 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)                               \
 151 do                                                                      \
 152   {                                                                     \
 153     if (GET_MODE_CLASS (MODE) == MODE_INT                               \
 154         && GET_MODE_SIZE (MODE) < 4)                                    \
 155       (MODE) = SImode;                                                  \
 156   }                                                                     \
 157 while (0)
 158
 159 #define PARM_BOUNDARY 64
 160
 161 /* Define this macro if you wish to preserve a certain alignment for the stack
 162    pointer.  The definition is a C expression for the desired alignment
 163    (measured in bits).  */
 164
 165 #define STACK_BOUNDARY 128
 166
 167 /* Align frames on double word boundaries */
 168 #ifndef IA64_STACK_ALIGN
 169 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
 170 #endif
 171
 172 #define FUNCTION_BOUNDARY 128
 173
 174 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
 175    128-bit integers all require 128-bit alignment.  */
 176 #define BIGGEST_ALIGNMENT 128
 177
 178 /* If defined, a C expression to compute the alignment for a static variable.
 179    TYPE is the data type, and ALIGN is the alignment that the object
 180    would ordinarily have.  The value of this macro is used instead of that
 181    alignment to align the object.  */
 182
 183 #define DATA_ALIGNMENT(TYPE, ALIGN)             \
 184   (TREE_CODE (TYPE) == ARRAY_TYPE               \
 185    && TYPE_MODE (TREE_TYPE (TYPE)) == QImode    \
 186    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 187
 188 #define STRICT_ALIGNMENT 1
 189
 190 /* Define this if you wish to imitate the way many other C compilers handle
 191    alignment of bitfields and the structures that contain them.
 192    The behavior is that the type written for a bit-field (`int', `short', or
 193    other integer type) imposes an alignment for the entire structure, as if the
 194    structure really did contain an ordinary field of that type.  In addition,
 195    the bit-field is placed within the structure so that it would fit within such
 196    a field, not crossing a boundary for it.  */
 197 #define PCC_BITFIELD_TYPE_MATTERS 1
 198
 199 /* An integer expression for the size in bits of the largest integer machine
 200    mode that should actually be used.  */
 201
 202 /* Allow pairs of registers to be used, which is the intent of the default.  */
 203 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 204
 205 /* By default, the C++ compiler will use function addresses in the
 206    vtable entries.  Setting this nonzero tells the compiler to use
 207    function descriptors instead.  The value of this macro says how
 208    many words wide the descriptor is (normally 2).  It is assumed
 209    that the address of a function descriptor may be treated as a
 210    pointer to a function.
 211
 212    For reasons known only to HP, the vtable entries (as opposed to
 213    normal function descriptors) are 16 bytes wide in 32-bit mode as
 214    well, even though the 3rd and 4th words are unused.  */
 215 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
 216
 217 /* Due to silliness in the HPUX linker, vtable entries must be
 218    8-byte aligned even in 32-bit mode.  Rather than create multiple
 219    ABIs, force this restriction on everyone else too.  */
 220 #define TARGET_VTABLE_ENTRY_ALIGN  64
 221
 222 /* Due to the above, we need extra padding for the data entries below 0
 223    to retain the alignment of the descriptors.  */
 224 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
 225 \f
 226 /* Layout of Source Language Data Types */
 227
 228 #define INT_TYPE_SIZE 32
 229
 230 #define SHORT_TYPE_SIZE 16
 231
 232 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
 233
 234 #define LONG_LONG_TYPE_SIZE 64
 235
 236 #define FLOAT_TYPE_SIZE 32
 237
 238 #define DOUBLE_TYPE_SIZE 64
 239
 240 /* long double is XFmode normally, and TFmode for HPUX.  It should be
 241    TFmode for VMS as well but we only support up to DFmode now.  */
 242 #define LONG_DOUBLE_TYPE_SIZE \
 243   (TARGET_HPUX ? 128 \
 244    : TARGET_ABI_OPEN_VMS ? 64 \
 245    : 80)
 246
 247
 248 #define DEFAULT_SIGNED_CHAR 1
 249
 250 /* A C expression for a string describing the name of the data type to use for
 251    size values.  The typedef name `size_t' is defined using the contents of the
 252    string.  */
 253 /* ??? Needs to be defined for P64 code.  */
 254 /* #define SIZE_TYPE */
 255
 256 /* A C expression for a string describing the name of the data type to use for
 257    the result of subtracting two pointers.  The typedef name `ptrdiff_t' is
 258    defined using the contents of the string.  See `SIZE_TYPE' above for more
 259    information.  */
 260 /* ??? Needs to be defined for P64 code.  */
 261 /* #define PTRDIFF_TYPE */
 262
 263 /* A C expression for a string describing the name of the data type to use for
 264    wide characters.  The typedef name `wchar_t' is defined using the contents
 265    of the string.  See `SIZE_TYPE' above for more information.  */
 266 /* #define WCHAR_TYPE */
 267
 268 /* A C expression for the size in bits of the data type for wide characters.
 269    This is used in `cpp', which cannot make use of `WCHAR_TYPE'.  */
 270 /* #define WCHAR_TYPE_SIZE */
 271
 272 \f
 273 /* Register Basics */
 274
 275 /* Number of hardware registers known to the compiler.
 276    We have 128 general registers, 128 floating point registers,
 277    64 predicate registers, 8 branch registers, one frame pointer,
 278    and several "application" registers.  */
 279
 280 #define FIRST_PSEUDO_REGISTER 334
 281
 282 /* Ranges for the various kinds of registers.  */
 283 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
 284 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
 285 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
 286 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
 287 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
 288 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
 289 #define GENERAL_REGNO_P(REGNO) \
 290   (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
 291
 292 #define GR_REG(REGNO) ((REGNO) + 0)
 293 #define FR_REG(REGNO) ((REGNO) + 128)
 294 #define PR_REG(REGNO) ((REGNO) + 256)
 295 #define BR_REG(REGNO) ((REGNO) + 320)
 296 #define OUT_REG(REGNO) ((REGNO) + 120)
 297 #define IN_REG(REGNO) ((REGNO) + 112)
 298 #define LOC_REG(REGNO) ((REGNO) + 32)
 299
 300 #define AR_CCV_REGNUM   329
 301 #define AR_UNAT_REGNUM  330
 302 #define AR_PFS_REGNUM   331
 303 #define AR_LC_REGNUM    332
 304 #define AR_EC_REGNUM    333
 305
 306 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
 307 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
 308 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
 309
 310 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
 311                              || (REGNO) == AR_UNAT_REGNUM)
 312 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
 313                              && (REGNO) < FIRST_PSEUDO_REGISTER)
 314 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
 315                            && (REGNO) < FIRST_PSEUDO_REGISTER)
 316
 317
 318 /* ??? Don't really need two sets of macros.  I like this one better because
 319    it is less typing.  */
 320 #define R_GR(REGNO) GR_REG (REGNO)
 321 #define R_FR(REGNO) FR_REG (REGNO)
 322 #define R_PR(REGNO) PR_REG (REGNO)
 323 #define R_BR(REGNO) BR_REG (REGNO)
 324
 325 /* An initializer that says which registers are used for fixed purposes all
 326    throughout the compiled code and are therefore not available for general
 327    allocation.
 328
 329    r0: constant 0
 330    r1: global pointer (gp)
 331    r12: stack pointer (sp)
 332    r13: thread pointer (tp)
 333    f0: constant 0.0
 334    f1: constant 1.0
 335    p0: constant true
 336    fp: eliminable frame pointer */
 337
 338 /* The last 16 stacked regs are reserved for the 8 input and 8 output
 339    registers.  */
 340
 341 #define FIXED_REGISTERS \
 342 { /* General registers.  */                             \
 343   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0,       \
 344   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 345   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 346   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 347   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 348   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 349   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 350   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 351   /* Floating-point registers.  */                      \
 352   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 353   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 354   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 355   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 356   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 357   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 358   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 359   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 360   /* Predicate registers.  */                           \
 361   1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 362   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 363   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 364   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 365   /* Branch registers.  */                              \
 366   0, 0, 0, 0, 0, 0, 0, 0,                               \
 367   /*FP CCV UNAT PFS LC EC */                            \
 368      1,  1,   1,  1, 1, 1                               \
 369  }
 370
 371 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
 372    (in general) by function calls as well as for fixed registers.  This
 373    macro therefore identifies the registers that are not available for
 374    general allocation of values that must live across function calls.  */
 375
 376 #define CALL_USED_REGISTERS \
 377 { /* General registers.  */                             \
 378   1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,       \
 379   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 380   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 381   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 382   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 383   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 384   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 385   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,       \
 386   /* Floating-point registers.  */                      \
 387   1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 388   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 389   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 390   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 391   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 392   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 393   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 394   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 395   /* Predicate registers.  */                           \
 396   1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 397   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 398   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 399   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 400   /* Branch registers.  */                              \
 401   1, 0, 0, 0, 0, 0, 1, 1,                               \
 402   /*FP CCV UNAT PFS LC EC */                            \
 403      1,  1,   1,  1, 1, 1                               \
 404 }
 405
 406 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
 407    problem which makes CALL_USED_REGISTERS *always* include
 408    all the FIXED_REGISTERS.  Until this problem has been
 409    resolved this macro can be used to overcome this situation.
 410    In particular, block_propagate() requires this list
 411    be accurate, or we can remove registers which should be live.
 412    This macro is used in regs_invalidated_by_call.  */
 413
 414 #define CALL_REALLY_USED_REGISTERS \
 415 { /* General registers.  */                             \
 416   0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1,       \
 417   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 418   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 419   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 420   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 421   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 422   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 423   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,       \
 424   /* Floating-point registers.  */                      \
 425   0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 426   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 427   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 428   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 429   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 430   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 431   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 432   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 433   /* Predicate registers.  */                           \
 434   0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
 435   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 436   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 437   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
 438   /* Branch registers.  */                              \
 439   1, 0, 0, 0, 0, 0, 1, 1,                               \
 440   /*FP CCV UNAT PFS LC EC */                            \
 441      0,  1,   0,  1, 0, 0                               \
 442 }
 443
 444
 445 /* Define this macro if the target machine has register windows.  This C
 446    expression returns the register number as seen by the called function
 447    corresponding to the register number OUT as seen by the calling function.
 448    Return OUT if register number OUT is not an outbound register.  */
 449
 450 #define INCOMING_REGNO(OUT) \
 451   ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
 452
 453 /* Define this macro if the target machine has register windows.  This C
 454    expression returns the register number as seen by the calling function
 455    corresponding to the register number IN as seen by the called function.
 456    Return IN if register number IN is not an inbound register.  */
 457
 458 #define OUTGOING_REGNO(IN) \
 459   ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
 460
 461 /* Define this macro if the target machine has register windows.  This
 462    C expression returns true if the register is call-saved but is in the
 463    register window.  */
 464
 465 #define LOCAL_REGNO(REGNO) \
 466   (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
 467
 468 /* We define CCImode in ia64-modes.def so we need a selector.  */
 469
 470 #define SELECT_CC_MODE(OP,X,Y)  CCmode
 471 \f
 472 /* Order of allocation of registers */
 473
 474 /* If defined, an initializer for a vector of integers, containing the numbers
 475    of hard registers in the order in which GCC should prefer to use them
 476    (from most preferred to least).
 477
 478    If this macro is not defined, registers are used lowest numbered first (all
 479    else being equal).
 480
 481    One use of this macro is on machines where the highest numbered registers
 482    must always be saved and the save-multiple-registers instruction supports
 483    only sequences of consecutive registers.  On such machines, define
 484    `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
 485    allocatable register first.  */
 486
 487 /* ??? Should the GR return value registers come before or after the rest
 488    of the caller-save GRs?  */
 489
 490 #define REG_ALLOC_ORDER                                                    \
 491 {                                                                          \
 492   /* Caller-saved general registers.  */                                   \
 493   R_GR (14), R_GR (15), R_GR (16), R_GR (17),                              \
 494   R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23),        \
 495   R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29),        \
 496   R_GR (30), R_GR (31),                                                    \
 497   /* Output registers.  */                                                 \
 498   R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125),  \
 499   R_GR (126), R_GR (127),                                                  \
 500   /* Caller-saved general registers, also used for return values.  */      \
 501   R_GR (8), R_GR (9), R_GR (10), R_GR (11),                                \
 502   /* addl caller-saved general registers.  */                              \
 503   R_GR (2), R_GR (3),                                                      \
 504   /* Caller-saved FP registers.  */                                        \
 505   R_FR (6), R_FR (7),                                                      \
 506   /* Caller-saved FP registers, used for parameters and return values.  */ \
 507   R_FR (8), R_FR (9), R_FR (10), R_FR (11),                                \
 508   R_FR (12), R_FR (13), R_FR (14), R_FR (15),                              \
 509   /* Rotating caller-saved FP registers.  */                               \
 510   R_FR (32), R_FR (33), R_FR (34), R_FR (35),                              \
 511   R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41),        \
 512   R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47),        \
 513   R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53),        \
 514   R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59),        \
 515   R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65),        \
 516   R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71),        \
 517   R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77),        \
 518   R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83),        \
 519   R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89),        \
 520   R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95),        \
 521   R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101),      \
 522   R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107),  \
 523   R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113),  \
 524   R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119),  \
 525   R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125),  \
 526   R_FR (126), R_FR (127),                                                  \
 527   /* Caller-saved predicate registers.  */                                 \
 528   R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11),            \
 529   R_PR (12), R_PR (13), R_PR (14), R_PR (15),                              \
 530   /* Rotating caller-saved predicate registers.  */                        \
 531   R_PR (16), R_PR (17),                                                    \
 532   R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23),        \
 533   R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29),        \
 534   R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35),        \
 535   R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41),        \
 536   R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47),        \
 537   R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53),        \
 538   R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59),        \
 539   R_PR (60), R_PR (61), R_PR (62), R_PR (63),                              \
 540   /* Caller-saved branch registers.  */                                    \
 541   R_BR (6), R_BR (7),                                                      \
 542                                                                            \
 543   /* Stacked callee-saved general registers.  */                           \
 544   R_GR (32), R_GR (33), R_GR (34), R_GR (35),                              \
 545   R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41),        \
 546   R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47),        \
 547   R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53),        \
 548   R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59),        \
 549   R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65),        \
 550   R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71),        \
 551   R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77),        \
 552   R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83),        \
 553   R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89),        \
 554   R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95),        \
 555   R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101),      \
 556   R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107),  \
 557   R_GR (108),                                                              \
 558   /* Input registers.  */                                                  \
 559   R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117),  \
 560   R_GR (118), R_GR (119),                                                  \
 561   /* Callee-saved general registers.  */                                   \
 562   R_GR (4), R_GR (5), R_GR (6), R_GR (7),                                  \
 563   /* Callee-saved FP registers.  */                                        \
 564   R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17),            \
 565   R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23),        \
 566   R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29),        \
 567   R_FR (30), R_FR (31),                                                    \
 568   /* Callee-saved predicate registers.  */                                 \
 569   R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5),                        \
 570   /* Callee-saved branch registers.  */                                    \
 571   R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5),                        \
 572                                                                            \
 573   /* ??? Stacked registers reserved for fp, rp, and ar.pfs.  */            \
 574   R_GR (109), R_GR (110), R_GR (111),                                      \
 575                                                                            \
 576   /* Special general registers.  */                                        \
 577   R_GR (0), R_GR (1), R_GR (12), R_GR (13),                                \
 578   /* Special FP registers.  */                                             \
 579   R_FR (0), R_FR (1),                                                      \
 580   /* Special predicate registers.  */                                      \
 581   R_PR (0),                                                                \
 582   /* Special branch registers.  */                                         \
 583   R_BR (0),                                                                \
 584   /* Other fixed registers.  */                                            \
 585   FRAME_POINTER_REGNUM,                                                    \
 586   AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM,              \
 587   AR_EC_REGNUM                                                             \
 588 }
 589 \f
 590 /* How Values Fit in Registers */
 591
 592 /* Specify the modes required to caller save a given hard regno.
 593    We need to ensure floating pt regs are not saved as DImode.  */
 594
 595 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 596   ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode        \
 597    : choose_hard_reg_mode ((REGNO), (NREGS), false))
 598 \f
 599 /* Handling Leaf Functions */
 600
 601 /* A C initializer for a vector, indexed by hard register number, which
 602    contains 1 for a register that is allowable in a candidate for leaf function
 603    treatment.  */
 604 /* ??? This might be useful.  */
 605 /* #define LEAF_REGISTERS */
 606
 607 /* A C expression whose value is the register number to which REGNO should be
 608    renumbered, when a function is treated as a leaf function.  */
 609 /* ??? This might be useful.  */
 610 /* #define LEAF_REG_REMAP(REGNO) */
 611
 612 \f
 613 /* Register Classes */
 614
 615 /* An enumeral type that must be defined with all the register class names as
 616    enumeral values.  `NO_REGS' must be first.  `ALL_REGS' must be the last
 617    register class, followed by one more enumeral value, `LIM_REG_CLASSES',
 618    which is not a register class but rather tells how many classes there
 619    are.  */
 620 /* ??? When compiling without optimization, it is possible for the only use of
 621    a pseudo to be a parameter load from the stack with a REG_EQUIV note.
 622    Regclass handles this case specially and does not assign any costs to the
 623    pseudo.  The pseudo then ends up using the last class before ALL_REGS.
 624    Thus we must not let either PR_REGS or BR_REGS be the last class.  The
 625    testcase for this is gcc.c-torture/execute/va-arg-7.c.  */
 626 enum reg_class
 627 {
 628   NO_REGS,
 629   PR_REGS,
 630   BR_REGS,
 631   AR_M_REGS,
 632   AR_I_REGS,
 633   ADDL_REGS,
 634   GR_REGS,
 635   FP_REGS,
 636   FR_REGS,
 637   GR_AND_BR_REGS,
 638   GR_AND_FR_REGS,
 639   ALL_REGS,
 640   LIM_REG_CLASSES
 641 };
 642
 643 #define GENERAL_REGS GR_REGS
 644
 645 /* The number of distinct register classes.  */
 646 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
 647
 648 /* An initializer containing the names of the register classes as C string
 649    constants.  These names are used in writing some of the debugging dumps.  */
 650 #define REG_CLASS_NAMES \
 651 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
 652   "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
 653   "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
 654
 655 /* An initializer containing the contents of the register classes, as integers
 656    which are bit masks.  The Nth integer specifies the contents of class N.
 657    The way the integer MASK is interpreted is that register R is in the class
 658    if `MASK & (1 << R)' is 1.  */
 659 #define REG_CLASS_CONTENTS \
 660 {                                                       \
 661   /* NO_REGS.  */                                       \
 662   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 663     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 664     0x00000000, 0x00000000, 0x0000 },                   \
 665   /* PR_REGS.  */                                       \
 666   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 667     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 668     0xFFFFFFFF, 0xFFFFFFFF, 0x0000 },                   \
 669   /* BR_REGS.  */                                       \
 670   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 671     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 672     0x00000000, 0x00000000, 0x00FF },                   \
 673   /* AR_M_REGS.  */                                     \
 674   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 675     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 676     0x00000000, 0x00000000, 0x0600 },                   \
 677   /* AR_I_REGS.  */                                     \
 678   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 679     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 680     0x00000000, 0x00000000, 0x3800 },                   \
 681   /* ADDL_REGS.  */                                     \
 682   { 0x0000000F, 0x00000000, 0x00000000, 0x00000000,     \
 683     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 684     0x00000000, 0x00000000, 0x0000 },                   \
 685   /* GR_REGS.  */                                       \
 686   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 687     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 688     0x00000000, 0x00000000, 0x0100 },                   \
 689   /* FP_REGS.  */                                       \
 690   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 691     0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF,     \
 692     0x00000000, 0x00000000, 0x0000 },                   \
 693   /* FR_REGS.  */                                       \
 694   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 695     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 696     0x00000000, 0x00000000, 0x0000 },                   \
 697   /* GR_AND_BR_REGS.  */                                \
 698   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 699     0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
 700     0x00000000, 0x00000000, 0x01FF },                   \
 701   /* GR_AND_FR_REGS.  */                                \
 702   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 703     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 704     0x00000000, 0x00000000, 0x0100 },                   \
 705   /* ALL_REGS.  */                                      \
 706   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 707     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
 708     0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF },                   \
 709 }
 710
 711 /* A C expression whose value is a register class containing hard register
 712    REGNO.  In general there is more than one such class; choose a class which
 713    is "minimal", meaning that no smaller class also contains the register.  */
 714 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
 715    may call here with private (invalid) register numbers, such as
 716    REG_VOLATILE.  */
 717 #define REGNO_REG_CLASS(REGNO) \
 718 (ADDL_REGNO_P (REGNO) ? ADDL_REGS       \
 719  : GENERAL_REGNO_P (REGNO) ? GR_REGS    \
 720  : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
 721                         && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
 722  : PR_REGNO_P (REGNO) ? PR_REGS         \
 723  : BR_REGNO_P (REGNO) ? BR_REGS         \
 724  : AR_M_REGNO_P (REGNO) ? AR_M_REGS     \
 725  : AR_I_REGNO_P (REGNO) ? AR_I_REGS     \
 726  : NO_REGS)
 727
 728 /* A macro whose definition is the name of the class to which a valid base
 729    register must belong.  A base register is one used in an address which is
 730    the register value plus a displacement.  */
 731 #define BASE_REG_CLASS GENERAL_REGS
 732
 733 /* A macro whose definition is the name of the class to which a valid index
 734    register must belong.  An index register is one used in an address where its
 735    value is either multiplied by a scale factor or added to another register
 736    (as well as added to a displacement).  This is needed for POST_MODIFY.  */
 737 #define INDEX_REG_CLASS GENERAL_REGS
 738
 739 /* A C expression which is nonzero if register number NUM is suitable for use
 740    as a base register in operand addresses.  It may be either a suitable hard
 741    register or a pseudo register that has been allocated such a hard reg.  */
 742 #define REGNO_OK_FOR_BASE_P(REGNO) \
 743   (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
 744
 745 /* A C expression which is nonzero if register number NUM is suitable for use
 746    as an index register in operand addresses.  It may be either a suitable hard
 747    register or a pseudo register that has been allocated such a hard reg.
 748    This is needed for POST_MODIFY.  */
 749 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
 750
 751 /* You should define this macro to indicate to the reload phase that it may
 752    need to allocate at least one register for a reload in addition to the
 753    register to contain the data.  Specifically, if copying X to a register
 754    CLASS in MODE requires an intermediate register, you should define this
 755    to return the largest register class all of whose registers can be used
 756    as intermediate registers or scratch registers.  */
 757
 758 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
 759  ia64_secondary_reload_class (CLASS, MODE, X)
 760
 761 /* A C expression for the maximum number of consecutive registers of
 762    class CLASS needed to hold a value of mode MODE.
 763    This is closely related to TARGET_HARD_REGNO_NREGS.  */
 764
 765 #define CLASS_MAX_NREGS(CLASS, MODE) \
 766   ((MODE) == BImode && (CLASS) == PR_REGS ? 2                   \
 767    : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
 768    : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
 769    : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
 770    : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 771 \f
 772 /* Basic Stack Layout */
 773
 774 /* Define this macro if pushing a word onto the stack moves the stack pointer
 775    to a smaller address.  */
 776 #define STACK_GROWS_DOWNWARD 1
 777
 778 /* Define this macro to nonzero if the addresses of local variable slots
 779    are at negative offsets from the frame pointer.  */
 780 #define FRAME_GROWS_DOWNWARD 0
 781
 782 /* Offset from the stack pointer register to the first location at which
 783    outgoing arguments are placed.  If not specified, the default value of zero
 784    is used.  This is the proper value for most machines.  */
 785 /* IA64 has a 16 byte scratch area that is at the bottom of the stack.  */
 786 #define STACK_POINTER_OFFSET 16
 787
 788 /* Offset from the argument pointer register to the first argument's address.
 789    On some machines it may depend on the data type of the function.  */
 790 #define FIRST_PARM_OFFSET(FUNDECL) 0
 791
 792 /* A C expression whose value is RTL representing the value of the return
 793    address for the frame COUNT steps up from the current frame, after the
 794    prologue.  */
 795
 796 /* ??? Frames other than zero would likely require interpreting the frame
 797    unwind info, so we don't try to support them.  We would also need to define
 798    DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush).  */
 799
 800 #define RETURN_ADDR_RTX(COUNT, FRAME) \
 801   ia64_return_addr_rtx (COUNT, FRAME)
 802
 803 /* A C expression whose value is RTL representing the location of the incoming
 804    return address at the beginning of any function, before the prologue.  This
 805    RTL is either a `REG', indicating that the return value is saved in `REG',
 806    or a `MEM' representing a location in the stack.  This enables DWARF2
 807    unwind info for C++ EH.  */
 808 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, BR_REG (0))
 809
 810 /* A C expression whose value is an integer giving the offset, in bytes, from
 811    the value of the stack pointer register to the top of the stack frame at the
 812    beginning of any function, before the prologue.  The top of the frame is
 813    defined to be the value of the stack pointer in the previous frame, just
 814    before the call instruction.  */
 815 /* The CFA is past the red zone, not at the entry-point stack
 816    pointer.  */
 817 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
 818
 819 /* We shorten debug info by using CFA-16 as DW_AT_frame_base.  */
 820 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET)
 821
 822 \f
 823 /* Register That Address the Stack Frame.  */
 824
 825 /* The register number of the stack pointer register, which must also be a
 826    fixed register according to `FIXED_REGISTERS'.  On most machines, the
 827    hardware determines which register this is.  */
 828
 829 #define STACK_POINTER_REGNUM 12
 830
 831 /* The register number of the frame pointer register, which is used to access
 832    automatic variables in the stack frame.  On some machines, the hardware
 833    determines which register this is.  On other machines, you can choose any
 834    register you wish for this purpose.  */
 835
 836 #define FRAME_POINTER_REGNUM 328
 837
 838 /* Base register for access to local variables of the function.  */
 839 #define HARD_FRAME_POINTER_REGNUM  LOC_REG (79)
 840
 841 /* The register number of the arg pointer register, which is used to access the
 842    function's argument list.  */
 843 /* r0 won't otherwise be used, so put the always eliminated argument pointer
 844    in it.  */
 845 #define ARG_POINTER_REGNUM R_GR(0)
 846
 847 /* Due to the way varargs and argument spilling happens, the argument
 848    pointer is not 16-byte aligned like the stack pointer.  */
 849 #define INIT_EXPANDERS                                  \
 850   do {                                                  \
 851     ia64_init_expanders ();                             \
 852     if (crtl->emit.regno_pointer_align) \
 853       REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64;    \
 854   } while (0)
 855
 856 /* Register numbers used for passing a function's static chain pointer.  */
 857 /* ??? The ABI sez the static chain should be passed as a normal parameter.  */
 858 #define STATIC_CHAIN_REGNUM 15
 859 \f
 860 /* Eliminating the Frame Pointer and the Arg Pointer */
 861
 862 /* If defined, this macro specifies a table of register pairs used to eliminate
 863    unneeded registers that point into the stack frame.  */
 864
 865 #define ELIMINABLE_REGS                                                 \
 866 {                                                                       \
 867   {ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 868   {ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 869   {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 870   {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},                    \
 871 }
 872
 873 /* This macro returns the initial difference between the specified pair
 874    of registers.  */
 875 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 876   ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
 877 \f
 878 /* Passing Function Arguments on the Stack */
 879
 880 /* If defined, the maximum amount of space required for outgoing arguments will
 881    be computed and placed into the variable
 882    `crtl->outgoing_args_size'.  */
 883
 884 #define ACCUMULATE_OUTGOING_ARGS 1
 885
 886 \f
 887 /* Function Arguments in Registers */
 888
 889 #define MAX_ARGUMENT_SLOTS 8
 890 #define MAX_INT_RETURN_SLOTS 4
 891 #define GR_ARG_FIRST IN_REG (0)
 892 #define GR_RET_FIRST GR_REG (8)
 893 #define GR_RET_LAST  GR_REG (11)
 894 #define FR_ARG_FIRST FR_REG (8)
 895 #define FR_RET_FIRST FR_REG (8)
 896 #define FR_RET_LAST  FR_REG (15)
 897 #define AR_ARG_FIRST OUT_REG (0)
 898
 899 /* A C type for declaring a variable that is used as the first argument of
 900    `FUNCTION_ARG' and other related values.  For some target machines, the type
 901    `int' suffices and can hold the number of bytes of argument so far.  */
 902
 903 enum ivms_arg_type {I64, FF, FD, FG, FS, FT};
 904 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T.  */
 905
 906 typedef struct ia64_args
 907 {
 908   int words;                    /* # words of arguments so far  */
 909   int int_regs;                 /* # GR registers used so far  */
 910   int fp_regs;                  /* # FR registers used so far  */
 911   int prototype;                /* whether function prototyped  */
 912   enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */
 913 } CUMULATIVE_ARGS;
 914
 915 /* A C statement (sans semicolon) for initializing the variable CUM for the
 916    state at the beginning of the argument list.  */
 917
 918 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 919 do {                                                                    \
 920   (CUM).words = 0;                                                      \
 921   (CUM).int_regs = 0;                                                   \
 922   (CUM).fp_regs = 0;                                                    \
 923   (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME);    \
 924   (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64;            \
 925   (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64;            \
 926   (CUM).atypes[6] = (CUM).atypes[7] = I64;                              \
 927 } while (0)
 928
 929 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
 930    arguments for the function being compiled.  If this macro is undefined,
 931    `INIT_CUMULATIVE_ARGS' is used instead.  */
 932
 933 /* We set prototype to true so that we never try to return a PARALLEL from
 934    function_arg.  */
 935 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
 936 do {                                                                    \
 937   (CUM).words = 0;                                                      \
 938   (CUM).int_regs = 0;                                                   \
 939   (CUM).fp_regs = 0;                                                    \
 940   (CUM).prototype = 1;                                                  \
 941   (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64;            \
 942   (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64;            \
 943   (CUM).atypes[6] = (CUM).atypes[7] = I64;                              \
 944 } while (0)
 945
 946 /* A C expression that is nonzero if REGNO is the number of a hard register in
 947    which function arguments are sometimes passed.  This does *not* include
 948    implicit arguments such as the static chain and the structure-value address.
 949    On many machines, no registers can be used for this purpose since all
 950    function arguments are pushed on the stack.  */
 951 #define FUNCTION_ARG_REGNO_P(REGNO) \
 952 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
 953  || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
 954
 955 \f
 956 /* How Large Values are Returned */
 957
 958 #define DEFAULT_PCC_STRUCT_RETURN 0
 959
 960 \f
 961 /* Caller-Saves Register Allocation */
 962
 963 /* A C expression to determine whether it is worthwhile to consider placing a
 964    pseudo-register in a call-clobbered hard register and saving and restoring
 965    it around each function call.  The expression should be 1 when this is worth
 966    doing, and 0 otherwise.
 967
 968    If you don't define this macro, a default is used which is good on most
 969    machines: `4 * CALLS < REFS'.  */
 970 /* ??? Investigate.  */
 971 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
 972
 973 \f
 974 /* Function Entry and Exit */
 975
 976 /* Define this macro as a C expression that is nonzero if the return
 977    instruction or the function epilogue ignores the value of the stack pointer;
 978    in other words, if it is safe to delete an instruction to adjust the stack
 979    pointer before a return from the function.  */
 980
 981 #define EXIT_IGNORE_STACK 1
 982
 983 /* Define this macro as a C expression that is nonzero for registers
 984    used by the epilogue or the `return' pattern.  */
 985
 986 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
 987
 988 /* Nonzero for registers used by the exception handling mechanism.  */
 989
 990 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
 991
 992 /* Output part N of a function descriptor for DECL.  For ia64, both
 993    words are emitted with a single relocation, so ignore N > 0.  */
 994 #define ASM_OUTPUT_FDESC(FILE, DECL, PART)                              \
 995 do {                                                                    \
 996   if ((PART) == 0)                                                      \
 997     {                                                                   \
 998       if (TARGET_ILP32)                                                 \
 999         fputs ("\tdata8.ua @iplt(", FILE);                              \
1000       else                                                              \
1001         fputs ("\tdata16.ua @iplt(", FILE);                             \
1002       mark_decl_referenced (DECL);                                      \
1003       assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0));        \
1004       fputs (")\n", FILE);                                              \
1005       if (TARGET_ILP32)                                                 \
1006         fputs ("\tdata8.ua 0\n", FILE);                                 \
1007     }                                                                   \
1008 } while (0)
1009 \f
1010 /* Generating Code for Profiling.  */
1011
1012 /* A C statement or compound statement to output to FILE some assembler code to
1013    call the profiling subroutine `mcount'.  */
1014
1015 #undef FUNCTION_PROFILER
1016 #define FUNCTION_PROFILER(FILE, LABELNO) \
1017   ia64_output_function_profiler(FILE, LABELNO)
1018
1019 /* Neither hpux nor linux use profile counters.  */
1020 #define NO_PROFILE_COUNTERS 1
1021 \f
1022 /* Trampolines for Nested Functions.  */
1023
1024 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1025    the function containing a non-local goto target.  */
1026
1027 #define STACK_SAVEAREA_MODE(LEVEL) \
1028   ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1029
1030 /* A C expression for the size in bytes of the trampoline, as an integer.  */
1031
1032 #define TRAMPOLINE_SIZE         32
1033
1034 /* Alignment required for trampolines, in bits.  */
1035
1036 #define TRAMPOLINE_ALIGNMENT    64
1037 \f
1038 /* Addressing Modes */
1039
1040 /* Define this macro if the machine supports post-increment addressing.  */
1041
1042 #define HAVE_POST_INCREMENT 1
1043 #define HAVE_POST_DECREMENT 1
1044 #define HAVE_POST_MODIFY_DISP 1
1045 #define HAVE_POST_MODIFY_REG 1
1046
1047 /* A C expression that is 1 if the RTX X is a constant which is a valid
1048    address.  */
1049
1050 #define CONSTANT_ADDRESS_P(X) 0
1051
1052 /* The max number of registers that can appear in a valid memory address.  */
1053
1054 #define MAX_REGS_PER_ADDRESS 2
1055
1056 \f
1057 /* Condition Code Status */
1058
1059 /* One some machines not all possible comparisons are defined, but you can
1060    convert an invalid comparison into a valid one.  */
1061 /* ??? Investigate.  See the alpha definition.  */
1062 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1063
1064 \f
1065 /* Describing Relative Costs of Operations */
1066
1067 /* A C expression for the cost of a branch instruction.  A value of 1 is the
1068    default; other values are interpreted relative to that.  Used by the
1069    if-conversion code as max instruction count.  */
1070 /* ??? This requires investigation.  The primary effect might be how
1071    many additional insn groups we run into, vs how good the dynamic
1072    branch predictor is.  */
1073
1074 #define BRANCH_COST(speed_p, predictable_p) 6
1075
1076 /* Define this macro as a C expression which is nonzero if accessing less than
1077    a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1078    word of memory.  */
1079
1080 #define SLOW_BYTE_ACCESS 1
1081
1082 /* Define this macro if it is as good or better to call a constant function
1083    address than to call an address kept in a register.
1084
1085    Indirect function calls are more expensive that direct function calls, so
1086    don't cse function addresses.  */
1087
1088 #define NO_FUNCTION_CSE 1
1089
1090 \f
1091 /* Dividing the output into sections.  */
1092
1093 /* A C expression whose value is a string containing the assembler operation
1094    that should precede instructions and read-only data.  */
1095
1096 #define TEXT_SECTION_ASM_OP "\t.text"
1097
1098 /* A C expression whose value is a string containing the assembler operation to
1099    identify the following data as writable initialized data.  */
1100
1101 #define DATA_SECTION_ASM_OP "\t.data"
1102
1103 /* If defined, a C expression whose value is a string containing the assembler
1104    operation to identify the following data as uninitialized global data.  */
1105
1106 #define BSS_SECTION_ASM_OP "\t.bss"
1107
1108 #define IA64_DEFAULT_GVALUE 8
1109 \f
1110 /* Position Independent Code.  */
1111
1112 /* The register number of the register used to address a table of static data
1113    addresses in memory.  */
1114
1115 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1116    gen_rtx_REG (DImode, 1).  */
1117
1118 /* ??? Should we set flag_pic?  Probably need to define
1119    LEGITIMIZE_PIC_OPERAND_P to make that work.  */
1120
1121 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1122
1123 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1124    clobbered by calls.  */
1125
1126 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
1127
1128 \f
1129 /* The Overall Framework of an Assembler File.  */
1130
1131 /* A C string constant describing how to begin a comment in the target
1132    assembler language.  The compiler assumes that the comment will end at the
1133    end of the line.  */
1134
1135 #define ASM_COMMENT_START "//"
1136
1137 /* A C string constant for text to be output before each `asm' statement or
1138    group of consecutive ones.  */
1139
1140 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1141
1142 /* A C string constant for text to be output after each `asm' statement or
1143    group of consecutive ones.  */
1144
1145 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1146 \f
1147 /* Output and Generation of Labels.  */
1148
1149 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1150    assembler definition of a label named NAME.  */
1151
1152 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1153    why ia64_asm_output_label exists.  */
1154
1155 extern int ia64_asm_output_label;
1156 #define ASM_OUTPUT_LABEL(STREAM, NAME)                                  \
1157 do {                                                                    \
1158   ia64_asm_output_label = 1;                                            \
1159   assemble_name (STREAM, NAME);                                         \
1160   fputs (":\n", STREAM);                                                \
1161   ia64_asm_output_label = 0;                                            \
1162 } while (0)
1163
1164 /* Globalizing directive for a label.  */
1165 #define GLOBAL_ASM_OP "\t.global "
1166
1167 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1168    necessary for declaring the name of an external symbol named NAME which is
1169    referenced in this compilation but not defined.  */
1170
1171 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1172   ia64_asm_output_external (FILE, DECL, NAME)
1173
1174 /* A C statement to store into the string STRING a label whose name is made
1175    from the string PREFIX and the number NUM.  */
1176
1177 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1178 do {                                                                    \
1179   sprintf (LABEL, "*.%s%d", PREFIX, NUM);                               \
1180 } while (0)
1181
1182 /* ??? Not sure if using a ? in the name for Intel as is safe.  */
1183
1184 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1185
1186 /* A C statement to output to the stdio stream STREAM assembler code which
1187    defines (equates) the symbol NAME to have the value VALUE.  */
1188
1189 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1190 do {                                                                    \
1191   assemble_name (STREAM, NAME);                                         \
1192   fputs (" = ", STREAM);                                                \
1193   if (ISDIGIT (*VALUE))                                                 \
1194     ia64_asm_output_label = 1;                                          \
1195   assemble_name (STREAM, VALUE);                                        \
1196   fputc ('\n', STREAM);                                                 \
1197   ia64_asm_output_label = 0;                                            \
1198 } while (0)
1199
1200 \f
1201 /* Macros Controlling Initialization Routines.  */
1202
1203 /* This is handled by sysv4.h.  */
1204
1205 \f
1206 /* Output of Assembler Instructions.  */
1207
1208 /* A C initializer containing the assembler's names for the machine registers,
1209    each one as a C string constant.  */
1210
1211 #define REGISTER_NAMES \
1212 {                                                                       \
1213   /* General registers.  */                                             \
1214   "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",           \
1215   "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1216   "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1217   "r30", "r31",                                                         \
1218   /* Local registers.  */                                               \
1219   "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",       \
1220   "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",      \
1221   "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",      \
1222   "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",      \
1223   "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",      \
1224   "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",      \
1225   "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",      \
1226   "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",      \
1227   "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",      \
1228   "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79",      \
1229   /* Input registers.  */                                               \
1230   "in0",  "in1",  "in2",  "in3",  "in4",  "in5",  "in6",  "in7",        \
1231   /* Output registers.  */                                              \
1232   "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7",       \
1233   /* Floating-point registers.  */                                      \
1234   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",           \
1235   "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1236   "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1237   "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1238   "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1239   "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1240   "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1241   "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1242   "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1243   "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1244   "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1245   "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1246   "f120","f121","f122","f123","f124","f125","f126","f127",              \
1247   /* Predicate registers.  */                                           \
1248   "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9",           \
1249   "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1250   "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1251   "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1252   "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1253   "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1254   "p60", "p61", "p62", "p63",                                           \
1255   /* Branch registers.  */                                              \
1256   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",                       \
1257   /* Frame pointer.  Application registers.  */                         \
1258   "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec",       \
1259 }
1260
1261 /* If defined, a C initializer for an array of structures containing a name and
1262    a register number.  This macro defines additional names for hard registers,
1263    thus allowing the `asm' option in declarations to refer to registers using
1264    alternate names.  */
1265
1266 #define ADDITIONAL_REGISTER_NAMES \
1267 {                                                                       \
1268   { "gp", R_GR (1) },                                                   \
1269   { "sp", R_GR (12) },                                                  \
1270   { "in0", IN_REG (0) },                                                \
1271   { "in1", IN_REG (1) },                                                \
1272   { "in2", IN_REG (2) },                                                \
1273   { "in3", IN_REG (3) },                                                \
1274   { "in4", IN_REG (4) },                                                \
1275   { "in5", IN_REG (5) },                                                \
1276   { "in6", IN_REG (6) },                                                \
1277   { "in7", IN_REG (7) },                                                \
1278   { "out0", OUT_REG (0) },                                              \
1279   { "out1", OUT_REG (1) },                                              \
1280   { "out2", OUT_REG (2) },                                              \
1281   { "out3", OUT_REG (3) },                                              \
1282   { "out4", OUT_REG (4) },                                              \
1283   { "out5", OUT_REG (5) },                                              \
1284   { "out6", OUT_REG (6) },                                              \
1285   { "out7", OUT_REG (7) },                                              \
1286   { "loc0", LOC_REG (0) },                                              \
1287   { "loc1", LOC_REG (1) },                                              \
1288   { "loc2", LOC_REG (2) },                                              \
1289   { "loc3", LOC_REG (3) },                                              \
1290   { "loc4", LOC_REG (4) },                                              \
1291   { "loc5", LOC_REG (5) },                                              \
1292   { "loc6", LOC_REG (6) },                                              \
1293   { "loc7", LOC_REG (7) },                                              \
1294   { "loc8", LOC_REG (8) },                                              \
1295   { "loc9", LOC_REG (9) },                                              \
1296   { "loc10", LOC_REG (10) },                                            \
1297   { "loc11", LOC_REG (11) },                                            \
1298   { "loc12", LOC_REG (12) },                                            \
1299   { "loc13", LOC_REG (13) },                                            \
1300   { "loc14", LOC_REG (14) },                                            \
1301   { "loc15", LOC_REG (15) },                                            \
1302   { "loc16", LOC_REG (16) },                                            \
1303   { "loc17", LOC_REG (17) },                                            \
1304   { "loc18", LOC_REG (18) },                                            \
1305   { "loc19", LOC_REG (19) },                                            \
1306   { "loc20", LOC_REG (20) },                                            \
1307   { "loc21", LOC_REG (21) },                                            \
1308   { "loc22", LOC_REG (22) },                                            \
1309   { "loc23", LOC_REG (23) },                                            \
1310   { "loc24", LOC_REG (24) },                                            \
1311   { "loc25", LOC_REG (25) },                                            \
1312   { "loc26", LOC_REG (26) },                                            \
1313   { "loc27", LOC_REG (27) },                                            \
1314   { "loc28", LOC_REG (28) },                                            \
1315   { "loc29", LOC_REG (29) },                                            \
1316   { "loc30", LOC_REG (30) },                                            \
1317   { "loc31", LOC_REG (31) },                                            \
1318   { "loc32", LOC_REG (32) },                                            \
1319   { "loc33", LOC_REG (33) },                                            \
1320   { "loc34", LOC_REG (34) },                                            \
1321   { "loc35", LOC_REG (35) },                                            \
1322   { "loc36", LOC_REG (36) },                                            \
1323   { "loc37", LOC_REG (37) },                                            \
1324   { "loc38", LOC_REG (38) },                                            \
1325   { "loc39", LOC_REG (39) },                                            \
1326   { "loc40", LOC_REG (40) },                                            \
1327   { "loc41", LOC_REG (41) },                                            \
1328   { "loc42", LOC_REG (42) },                                            \
1329   { "loc43", LOC_REG (43) },                                            \
1330   { "loc44", LOC_REG (44) },                                            \
1331   { "loc45", LOC_REG (45) },                                            \
1332   { "loc46", LOC_REG (46) },                                            \
1333   { "loc47", LOC_REG (47) },                                            \
1334   { "loc48", LOC_REG (48) },                                            \
1335   { "loc49", LOC_REG (49) },                                            \
1336   { "loc50", LOC_REG (50) },                                            \
1337   { "loc51", LOC_REG (51) },                                            \
1338   { "loc52", LOC_REG (52) },                                            \
1339   { "loc53", LOC_REG (53) },                                            \
1340   { "loc54", LOC_REG (54) },                                            \
1341   { "loc55", LOC_REG (55) },                                            \
1342   { "loc56", LOC_REG (56) },                                            \
1343   { "loc57", LOC_REG (57) },                                            \
1344   { "loc58", LOC_REG (58) },                                            \
1345   { "loc59", LOC_REG (59) },                                            \
1346   { "loc60", LOC_REG (60) },                                            \
1347   { "loc61", LOC_REG (61) },                                            \
1348   { "loc62", LOC_REG (62) },                                            \
1349   { "loc63", LOC_REG (63) },                                            \
1350   { "loc64", LOC_REG (64) },                                            \
1351   { "loc65", LOC_REG (65) },                                            \
1352   { "loc66", LOC_REG (66) },                                            \
1353   { "loc67", LOC_REG (67) },                                            \
1354   { "loc68", LOC_REG (68) },                                            \
1355   { "loc69", LOC_REG (69) },                                            \
1356   { "loc70", LOC_REG (70) },                                            \
1357   { "loc71", LOC_REG (71) },                                            \
1358   { "loc72", LOC_REG (72) },                                            \
1359   { "loc73", LOC_REG (73) },                                            \
1360   { "loc74", LOC_REG (74) },                                            \
1361   { "loc75", LOC_REG (75) },                                            \
1362   { "loc76", LOC_REG (76) },                                            \
1363   { "loc77", LOC_REG (77) },                                            \
1364   { "loc78", LOC_REG (78) },                                            \
1365   { "loc79", LOC_REG (79) },                                            \
1366 }
1367
1368 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1369    `%I' options of `asm_fprintf' (see `final.c').  */
1370
1371 #define REGISTER_PREFIX ""
1372 #define LOCAL_LABEL_PREFIX "."
1373 #define USER_LABEL_PREFIX ""
1374 #define IMMEDIATE_PREFIX ""
1375
1376 \f
1377 /* Output of dispatch tables.  */
1378
1379 /* This macro should be provided on machines where the addresses in a dispatch
1380    table are relative to the table's own address.  */
1381
1382 /* ??? Depends on the pointer size.  */
1383
1384 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)      \
1385   do {                                                          \
1386   if (CASE_VECTOR_MODE == SImode)                               \
1387     fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE);          \
1388   else                                                          \
1389     fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE);          \
1390   } while (0)
1391
1392 /* Jump tables only need 4 or 8 byte alignment.  */
1393
1394 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3)
1395
1396 \f
1397 /* Assembler Commands for Exception Regions.  */
1398
1399 /* Select a format to encode pointers in exception handling data.  CODE
1400    is 0 for data, 1 for code labels, 2 for function pointers.  GLOBAL is
1401    true if the symbol may be affected by dynamic relocations.  */
1402 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL)       \
1403   (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel)  \
1404    | ((GLOBAL) ? DW_EH_PE_indirect : 0)                 \
1405    | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1406
1407 /* Handle special EH pointer encodings.  Absolute, pc-relative, and
1408    indirect are handled automatically.  */
1409 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1410   do {                                                                  \
1411     const char *reltag = NULL;                                          \
1412     if (((ENCODING) & 0xF0) == DW_EH_PE_textrel)                        \
1413       reltag = "@segrel(";                                              \
1414     else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel)                   \
1415       reltag = "@gprel(";                                               \
1416     if (reltag)                                                         \
1417       {                                                                 \
1418         fputs (integer_asm_op (SIZE, FALSE), FILE);                     \
1419         fputs (reltag, FILE);                                           \
1420         assemble_name (FILE, XSTR (ADDR, 0));                           \
1421         fputc (')', FILE);                                              \
1422         goto DONE;                                                      \
1423       }                                                                 \
1424   } while (0)
1425
1426 \f
1427 /* Assembler Commands for Alignment.  */
1428
1429 /* ??? Investigate.  */
1430
1431 /* The alignment (log base 2) to put in front of LABEL, which follows
1432    a BARRIER.  */
1433
1434 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1435
1436 /* The desired alignment for the location counter at the beginning
1437    of a loop.  */
1438
1439 /* #define LOOP_ALIGN(LABEL) */
1440
1441 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1442    section because it fails put zeros in the bytes that are skipped.  */
1443
1444 #define ASM_NO_SKIP_IN_TEXT 1
1445
1446 /* A C statement to output to the stdio stream STREAM an assembler command to
1447    advance the location counter to a multiple of 2 to the POWER bytes.  */
1448
1449 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1450   fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1451
1452 \f
1453 /* Macros Affecting all Debug Formats.  */
1454
1455 /* This is handled in sysv4.h.  */
1456
1457 \f
1458 /* Specific Options for DBX Output.  */
1459
1460 /* This is handled by dbxelf.h.  */
1461
1462 \f
1463 /* Open ended Hooks for DBX Output.  */
1464
1465 /* Likewise.  */
1466
1467 \f
1468 /* File names in DBX format.  */
1469
1470 /* Likewise.  */
1471
1472 \f
1473 /* Macros for Dwarf Output.  */
1474
1475 /* Define this macro if GCC should produce dwarf version 2 format debugging
1476    output in response to the `-g' option.  */
1477
1478 #define DWARF2_DEBUGGING_INFO 1
1479
1480 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1481
1482 /* Use tags for debug info labels, so that they don't break instruction
1483    bundles.  This also avoids getting spurious DV warnings from the
1484    assembler.  This is similar to (*targetm.asm_out.internal_label), except that we
1485    add brackets around the label.  */
1486
1487 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1488   fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1489
1490 /* Use section-relative relocations for debugging offsets.  Unlike other
1491    targets that fake this by putting the section VMA at 0, IA-64 has
1492    proper relocations for them.  */
1493 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \
1494   do {                                                          \
1495     fputs (integer_asm_op (SIZE, FALSE), FILE);                 \
1496     fputs ("@secrel(", FILE);                                   \
1497     assemble_name (FILE, LABEL);                                \
1498     if ((OFFSET) != 0)                                          \
1499       fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC,               \
1500                (HOST_WIDE_INT) (OFFSET));                       \
1501     fputc (')', FILE);                                          \
1502   } while (0)
1503
1504 /* Emit a PC-relative relocation.  */
1505 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL)       \
1506   do {                                                  \
1507     fputs (integer_asm_op (SIZE, FALSE), FILE);         \
1508     fputs ("@pcrel(", FILE);                            \
1509     assemble_name (FILE, LABEL);                        \
1510     fputc (')', FILE);                                  \
1511   } while (0)
1512 \f
1513 /* Register Renaming Parameters.  */
1514
1515 /* A C expression that is nonzero if hard register number REGNO2 can be
1516    considered for use as a rename register for REGNO1 */
1517
1518 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1519   ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1520
1521 \f
1522 /* Miscellaneous Parameters.  */
1523
1524 /* Flag to mark data that is in the small address area (addressable
1525    via "addl", that is, within a 2MByte offset of 0.  */
1526 #define SYMBOL_FLAG_SMALL_ADDR          (SYMBOL_FLAG_MACH_DEP << 0)
1527 #define SYMBOL_REF_SMALL_ADDR_P(X)      \
1528         ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1529
1530 /* An alias for a machine mode name.  This is the machine mode that elements of
1531    a jump-table should have.  */
1532
1533 #define CASE_VECTOR_MODE ptr_mode
1534
1535 /* Define as C expression which evaluates to nonzero if the tablejump
1536    instruction expects the table to contain offsets from the address of the
1537    table.  */
1538
1539 #define CASE_VECTOR_PC_RELATIVE 1
1540
1541 /* Define this macro if operations between registers with integral mode smaller
1542    than a word are always performed on the entire register.  */
1543
1544 #define WORD_REGISTER_OPERATIONS 1
1545
1546 /* Define this macro to be a C expression indicating when insns that read
1547    memory in MODE, an integral mode narrower than a word, set the bits outside
1548    of MODE to be either the sign-extension or the zero-extension of the data
1549    read.  */
1550
1551 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1552
1553 /* The maximum number of bytes that a single instruction can move quickly from
1554    memory to memory.  */
1555 #define MOVE_MAX 8
1556
1557 /* A C expression describing the value returned by a comparison operator with
1558    an integral mode and stored by a store-flag instruction (`sCOND') when the
1559    condition is true.  */
1560
1561 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1.  */
1562
1563 /* An alias for the machine mode for pointers.  */
1564
1565 /* ??? This would change if we had ILP32 support.  */
1566
1567 #define Pmode DImode
1568
1569 /* An alias for the machine mode used for memory references to functions being
1570    called, in `call' RTL expressions.  */
1571
1572 #define FUNCTION_MODE Pmode
1573
1574 /* A C expression for the maximum number of instructions to execute via
1575    conditional execution instructions instead of a branch.  A value of
1576    BRANCH_COST+1 is the default if the machine does not use
1577    cc0, and 1 if it does use cc0.  */
1578 /* ??? Investigate.  */
1579 #define MAX_CONDITIONAL_EXECUTE 12
1580
1581 extern int ia64_final_schedule;
1582
1583 #define TARGET_UNWIND_TABLES_DEFAULT true
1584
1585 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
1586
1587 /* This function contains machine specific function data.  */
1588 struct GTY(()) machine_function
1589 {
1590   /* The new stack pointer when unwinding from EH.  */
1591   rtx ia64_eh_epilogue_sp;
1592
1593   /* The new bsp value when unwinding from EH.  */
1594   rtx ia64_eh_epilogue_bsp;
1595
1596   /* The GP value save register.  */
1597   rtx ia64_gp_save;
1598
1599   /* The number of varargs registers to save.  */
1600   int n_varargs;
1601
1602   /* The number of the next unwind state to copy.  */
1603   int state_num;
1604 };
1605
1606 #define DONT_USE_BUILTIN_SETJMP
1607
1608 /* Output any profiling code before the prologue.  */
1609
1610 #undef  PROFILE_BEFORE_PROLOGUE
1611 #define PROFILE_BEFORE_PROLOGUE 1
1612
1613 /* Initialize library function table. */
1614 #undef TARGET_INIT_LIBFUNCS
1615 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
1616 \f
1617
1618 /* Switch on code for querying unit reservations.  */
1619 #define CPU_UNITS_QUERY 1
1620
1621 /* End of ia64.h */