2 /* { dg-require-effective-target sync_int_long } */
4 /* { dg-options "-march=i486" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
5 /* { dg-options "-mcpu=v9" { target sparc*-*-* } } */
7 /* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
9 /* Test basic functionality of the intrinsics. The operations should
10 not be optimized away if no one checks the return values. */
12 __extension__
typedef __SIZE_TYPE__
size_t;
14 extern void abort (void);
15 extern void *memcpy (void *, const void *, size_t);
18 static int init_noret_si
[12] = { 0, 0, 0, 1, 0, 0, 0 , 0 , -1, 0, 0, -1 };
19 static int test_noret_si
[12] = { 1, 1, 1, 0, 1, 4, 22, -12, 7 , 8, 9, ~7 };
24 __sync_val_compare_and_swap(AI
+0, 0, 1);
25 __sync_bool_compare_and_swap(AI
+1, 0, 1);
26 __sync_lock_test_and_set(AI
+2, 1);
27 __sync_lock_release(AI
+3);
29 __sync_fetch_and_add(AI
+4, 1);
30 __sync_fetch_and_add(AI
+5, 4);
31 __sync_fetch_and_add(AI
+6, 22);
32 __sync_fetch_and_sub(AI
+7, 12);
33 __sync_fetch_and_and(AI
+8, 7);
34 __sync_fetch_and_or(AI
+9, 8);
35 __sync_fetch_and_xor(AI
+10, 9);
36 __sync_fetch_and_nand(AI
+11, 7);
40 static long init_noret_di
[12] = { 0, 0, 0, 1, 0, 0, 0 , 0 , -1, 0, 0, -1 };
41 static long test_noret_di
[12] = { 1, 1, 1, 0, 1, 4, 22, -12, 7 , 8, 9, ~7 };
46 __sync_val_compare_and_swap(AL
+0, 0, 1);
47 __sync_bool_compare_and_swap(AL
+1, 0, 1);
48 __sync_lock_test_and_set(AL
+2, 1);
49 __sync_lock_release(AL
+3);
51 __sync_fetch_and_add(AL
+4, 1);
52 __sync_fetch_and_add(AL
+5, 4);
53 __sync_fetch_and_add(AL
+6, 22);
54 __sync_fetch_and_sub(AL
+7, 12);
55 __sync_fetch_and_and(AL
+8, 7);
56 __sync_fetch_and_or(AL
+9, 8);
57 __sync_fetch_and_xor(AL
+10, 9);
58 __sync_fetch_and_nand(AL
+11, 7);
63 memcpy(AI
, init_noret_si
, sizeof(init_noret_si
));
64 memcpy(AL
, init_noret_di
, sizeof(init_noret_di
));
69 if (memcmp (AI
, test_noret_si
, sizeof(test_noret_si
)))
71 if (memcmp (AL
, test_noret_di
, sizeof(test_noret_di
)))