| blob | 89bf0dff904b6b52b71841aec299541f01884f3d |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2022 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
23 #define INCLUDE_STRING
24 #define INCLUDE_ALGORITHM
86 /* This file should be included last. */
89 /* Defined for convenience. */
90 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
92 /* Information about a legitimate vector immediate operand. */
93 struct simd_immediate_info
94 {
106 /* The mode of the elements. */
107 scalar_mode elt_mode;
109 /* The instruction to use to move the immediate into a vector. */
110 insn_type insn;
112 union
113 {
114 /* For MOV and MVN. */
115 struct
116 {
117 /* The value of each element. */
118 rtx value;
120 /* The kind of shift modifier to use, and the number of bits to shift.
121 This is (LSL, 0) if no shift is needed. */
122 modifier_type modifier;
126 /* For INDEX. */
127 struct
128 {
129 /* The value of the first element and the step to be added for each
130 subsequent element. */
134 /* For PTRUE. */
135 aarch64_svpattern pattern;
137 };
139 /* Construct a floating-point immediate in which each element has mode
140 ELT_MODE_IN and value VALUE_IN. */
141 inline simd_immediate_info
144 {
148 }
150 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
151 and value VALUE_IN. The other parameters are as for the structure
152 fields. */
153 inline simd_immediate_info
159 {
163 }
165 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
166 and where element I is equal to BASE_IN + I * STEP_IN. */
167 inline simd_immediate_info
170 {
173 }
175 /* Construct a predicate that controls elements of mode ELT_MODE_IN
176 and has PTRUE pattern PATTERN_IN. */
177 inline simd_immediate_info
179 aarch64_svpattern pattern_in)
181 {
183 }
187 /* Describes types that map to Pure Scalable Types (PSTs) in the AAPCS64. */
188 class pure_scalable_type_info
189 {
191 /* Represents the result of analyzing a type. All values are nonzero,
192 in the possibly forlorn hope that accidental conversions to bool
193 trigger a warning. */
194 enum analysis_result
195 {
196 /* The type does not have an ABI identity; i.e. it doesn't contain
197 at least one object whose type is a Fundamental Data Type. */
200 /* The type is definitely a Pure Scalable Type. */
201 IS_PST,
203 /* The type is definitely not a Pure Scalable Type. */
204 ISNT_PST,
206 /* It doesn't matter for PCS purposes whether the type is a Pure
207 Scalable Type or not, since the type will be handled the same
208 way regardless.
210 Specifically, this means that if the type is a Pure Scalable Type,
211 there aren't enough argument registers to hold it, and so it will
212 need to be passed or returned in memory. If the type isn't a
213 Pure Scalable Type, it's too big to be passed or returned in core
214 or SIMD&FP registers, and so again will need to go in memory. */
215 DOESNT_MATTER
216 };
218 /* Aggregates of 17 bytes or more are normally passed and returned
219 in memory, so aggregates of that size can safely be analyzed as
220 DOESNT_MATTER. We need to be able to collect enough pieces to
221 represent a PST that is smaller than that. Since predicates are
222 2 bytes in size for -msve-vector-bits=128, that means we need to be
223 able to store at least 8 pieces.
225 We also need to be able to store enough pieces to represent
226 a single vector in each vector argument register and a single
227 predicate in each predicate argument register. This means that
228 we need at least 12 pieces. */
232 /* Describes one piece of a PST. Each piece is one of:
234 - a single Scalable Vector Type (SVT)
235 - a single Scalable Predicate Type (SPT)
236 - a PST containing 2, 3 or 4 SVTs, with no padding
238 It either represents a single built-in type or a PST formed from
239 multiple homogeneous built-in types. */
240 struct piece
241 {
244 /* The number of vector and predicate registers that the piece
245 occupies. One of the two is always zero. */
249 /* The mode of the registers described above. */
250 machine_mode mode;
252 /* If this piece is formed from multiple homogeneous built-in types,
253 this is the mode of the built-in types, otherwise it is MODE. */
254 machine_mode orig_mode;
256 /* The offset in bytes of the piece from the start of the type. */
257 poly_uint64_pod offset;
258 };
260 /* Divides types analyzed as IS_PST into individual pieces. The pieces
261 are in memory order. */
276 };
277 }
279 /* The current code model. */
282 /* The number of 64-bit elements in an SVE vector. */
283 poly_uint16 aarch64_sve_vg;
285 #ifdef HAVE_AS_TLS
286 #undef TARGET_HAVE_TLS
287 #define TARGET_HAVE_TLS 1
288 #endif
293 const_tree,
302 const_tree type,
307 aarch64_addr_query_type);
309 /* The processor for which instructions should be scheduled. */
312 /* Mask to specify which instruction scheduling options should be used. */
315 /* Global flag for PC relative loads. */
318 /* Global flag for whether frame pointer is enabled. */
321 #define BRANCH_PROTECT_STR_MAX 255
324 static enum aarch64_parse_opt_result
327 /* Support for command line parsing of boolean flags in the tuning
328 structures. */
329 struct aarch64_flag_desc
330 {
333 };
335 #define AARCH64_FUSION_PAIR(name, internal_name) \
336 { name, AARCH64_FUSE_##internal_name },
338 {
343 };
345 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
346 { name, AARCH64_EXTRA_TUNE_##internal_name },
348 {
353 };
355 /* Tuning parameters. */
358 {
359 {
364 },
373 };
376 {
377 {
382 },
391 };
394 {
395 {
400 },
409 };
412 {
413 {
418 },
427 };
430 {
431 {
436 },
445 };
448 {
449 {
454 },
463 };
466 {
467 {
472 },
481 };
484 {
485 {
490 },
499 };
502 {
503 {
508 },
517 };
520 {
521 {
526 },
535 };
538 {
539 {
544 },
553 };
556 {
558 /* Avoid the use of slow int<->fp moves for spilling by setting
559 their cost higher than memmov_cost. */
563 };
566 {
568 /* Avoid the use of slow int<->fp moves for spilling by setting
569 their cost higher than memmov_cost. */
573 };
576 {
578 /* Avoid the use of slow int<->fp moves for spilling by setting
579 their cost higher than memmov_cost. */
583 };
586 {
588 /* Avoid the use of slow int<->fp moves for spilling by setting
589 their cost higher than memmov_cost (actual, 4 and 9). */
593 };
596 {
601 };
604 {
606 /* Avoid the use of slow int<->fp moves for spilling by setting
607 their cost higher than memmov_cost. */
611 };
614 {
616 /* Avoid the use of int<->fp moves for spilling. */
620 };
623 {
625 /* Avoid the use of int<->fp moves for spilling. */
629 };
632 {
634 /* Avoid the use of int<->fp moves for spilling. */
638 };
641 {
643 /* Avoid the use of slow int<->fp moves for spilling by setting
644 their cost higher than memmov_cost. */
648 };
651 {
653 /* Avoid the use of slow int<->fp moves for spilling by setting
654 their cost higher than memmov_cost. */
658 };
661 {
663 /* Spilling to int<->fp instead of memory is recommended so set
664 realistic costs compared to memmov_cost. */
668 };
671 {
673 /* Spilling to int<->fp instead of memory is recommended so set
674 realistic costs compared to memmov_cost. */
678 };
681 {
683 /* Spilling to int<->fp instead of memory is recommended so set
684 realistic costs compared to memmov_cost. */
688 };
690 /* Generic costs for Advanced SIMD vector operations. */
692 {
713 };
715 /* Generic costs for SVE vector operations. */
717 {
718 {
739 },
747 };
749 /* Generic costs for vector insn classes. */
751 {
761 };
764 {
785 };
788 {
789 {
810 },
818 };
821 {
831 };
834 {
855 };
857 /* QDF24XX costs for vector insn classes. */
859 {
869 };
873 {
894 };
896 /* ThunderX costs for vector insn classes. */
898 {
908 };
911 {
932 };
935 {
945 };
948 {
969 };
971 /* Cortex-A57 costs for vector insn classes. */
973 {
983 };
986 {
1007 };
1010 {
1020 };
1023 {
1044 };
1046 /* Generic costs for vector insn classes. */
1048 {
1058 };
1061 {
1082 };
1084 /* Costs for vector insn classes for Vulcan. */
1086 {
1096 };
1099 {
1120 };
1123 {
1133 };
1136 {
1157 };
1159 /* Ampere-1 costs for vector insn classes. */
1161 {
1171 };
1173 /* Generic costs for branch instructions. */
1175 {
1178 };
1180 /* Generic approximation modes. */
1182 {
1185 AARCH64_APPROX_NONE /* recip_sqrt */
1186 };
1188 /* Approximation modes for Exynos M1. */
1190 {
1193 AARCH64_APPROX_ALL /* recip_sqrt */
1194 };
1196 /* Approximation modes for X-Gene 1. */
1198 {
1201 AARCH64_APPROX_ALL /* recip_sqrt */
1202 };
1204 /* Generic prefetch settings (which disable prefetch). */
1206 {
1214 };
1217 {
1225 };
1228 {
1236 };
1239 {
1247 };
1250 {
1258 };
1261 {
1269 };
1272 {
1280 };
1283 {
1291 };
1294 {
1302 };
1305 {
1313 };
1316 {
1324 };
1327 {
1355 /* Enabling AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS significantly benefits
1356 Neoverse V1. It does not have a noticeable effect on A64FX and should
1357 have at most a very minor effect on SVE2 cores. */
1359 &generic_prefetch_tune
1360 };
1363 {
1393 &generic_prefetch_tune
1394 };
1397 {
1427 &generic_prefetch_tune
1428 };
1431 {
1461 &generic_prefetch_tune
1462 };
1465 {
1495 &generic_prefetch_tune
1496 };
1499 {
1529 &generic_prefetch_tune
1530 };
1535 {
1564 &exynosm1_prefetch_tune
1565 };
1568 {
1597 &thunderxt88_prefetch_tune
1598 };
1601 {
1629 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
1631 &thunderx_prefetch_tune
1632 };
1635 {
1665 &tsv110_prefetch_tune
1666 };
1669 {
1698 &xgene1_prefetch_tune
1699 };
1702 {
1709 SVE_NOT_IMPLEMENTED,
1731 &xgene1_prefetch_tune
1732 };
1735 {
1765 &qdf24xx_prefetch_tune
1766 };
1768 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
1769 for now. */
1771 {
1801 &generic_prefetch_tune
1802 };
1805 {
1835 &thunderx2t99_prefetch_tune
1836 };
1839 {
1869 &thunderx3t110_prefetch_tune
1870 };
1873 {
1902 &generic_prefetch_tune
1903 };
1906 {
1925 AARCH64_FUSE_CMP_BRANCH),
1926 /* fusible_ops */
1939 &ere1_prefetch_tune
1940 };
1943 {
1963 AARCH64_FUSE_ADDSUB_2REG_CONST1),
1964 /* fusible_ops */
1977 &ere1_prefetch_tune
1978 };
1981 {
1996 /* This value is just inherited from the Cortex-A57 table. */
1998 /* This depends very much on what the scalar value is and
1999 where it comes from. E.g. some constants take two dependent
2000 instructions or a load, while others might be moved from a GPR.
2001 4 seems to be a reasonable compromise in practice. */
2005 /* Although stores have a latency of 2 and compete for the
2006 vector pipes, in practice it's better not to model that. */
2009 };
2012 {
2013 {
2020 /* Theoretically, a reduction involving 31 scalar ADDs could
2021 complete in ~9 cycles and would have a cost of 31. [SU]ADDV
2022 completes in 14 cycles, so give it a cost of 31 + 5. */
2024 /* Likewise for 15 scalar ADDs (~5 cycles) vs. 12: 15 + 7. */
2026 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 10: 7 + 7. */
2028 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 10: 3 + 8. */
2030 /* Theoretically, a reduction involving 15 scalar FADDs could
2031 complete in ~9 cycles and would have a cost of 30. FADDV
2032 completes in 13 cycles, so give it a cost of 30 + 4. */
2034 /* Likewise for 7 scalar FADDs (~6 cycles) vs. 11: 14 + 5. */
2036 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 9: 6 + 5. */
2039 /* This value is just inherited from the Cortex-A57 table. */
2041 /* See the comment above the Advanced SIMD versions. */
2045 /* Although stores have a latency of 2 and compete for the
2046 vector pipes, in practice it's better not to model that. */
2049 },
2057 };
2060 {
2066 };
2069 {
2070 {
2076 },
2080 };
2083 {
2084 {
2085 {
2091 },
2095 },
2102 };
2105 {
2108 &neoversev1_sve_issue_info
2109 };
2111 /* Neoverse V1 costs for vector insn classes. */
2113 {
2123 };
2126 {
2154 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2155 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2156 | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT
2158 &generic_prefetch_tune
2159 };
2162 {
2163 {
2170 /* Theoretically, a reduction involving 15 scalar ADDs could
2171 complete in ~5 cycles and would have a cost of 15. Assume that
2172 [SU]ADDV completes in 11 cycles and so give it a cost of 15 + 6. */
2174 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2176 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2178 /* Likewise for 1 scalar ADD (1 cycle) vs. 8: 1 + 7. */
2180 /* Theoretically, a reduction involving 7 scalar FADDs could
2181 complete in ~6 cycles and would have a cost of 14. Assume that
2182 FADDV completes in 8 cycles and so give it a cost of 14 + 2. */
2184 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2186 /* Likewise for 1 scalar FADD (2 cycles) vs. 4: 2 + 2. */
2189 /* This value is just inherited from the Cortex-A57 table. */
2191 /* This depends very much on what the scalar value is and
2192 where it comes from. E.g. some constants take two dependent
2193 instructions or a load, while others might be moved from a GPR.
2194 4 seems to be a reasonable compromise in practice. */
2198 /* Although stores generally have a latency of 2 and compete for the
2199 vector pipes, in practice it's better not to model that. */
2202 },
2207 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2208 (6 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2209 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2210 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2211 (cost 2) to that, to avoid the difference being lost in rounding.
2213 There is no easy comparison between a strided Advanced SIMD x32 load
2214 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2215 operation more than a 64-bit gather. */
2219 };
2222 {
2223 {
2224 {
2230 },
2234 },
2241 };
2244 {
2247 &neoverse512tvb_sve_issue_info
2248 };
2251 {
2261 };
2264 {
2292 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2293 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2295 &generic_prefetch_tune
2296 };
2299 {
2314 /* This value is just inherited from the Cortex-A57 table. */
2316 /* This depends very much on what the scalar value is and
2317 where it comes from. E.g. some constants take two dependent
2318 instructions or a load, while others might be moved from a GPR.
2319 4 seems to be a reasonable compromise in practice. */
2323 /* Although stores have a latency of 2 and compete for the
2324 vector pipes, in practice it's better not to model that. */
2327 };
2330 {
2331 {
2338 /* Theoretically, a reduction involving 15 scalar ADDs could
2339 complete in ~5 cycles and would have a cost of 15. [SU]ADDV
2340 completes in 11 cycles, so give it a cost of 15 + 6. */
2342 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2344 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2346 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2348 /* Theoretically, a reduction involving 7 scalar FADDs could
2349 complete in ~8 cycles and would have a cost of 14. FADDV
2350 completes in 6 cycles, so give it a cost of 14 - 2. */
2352 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 4: 6 - 0. */
2354 /* Likewise for 1 scalar FADD (~2 cycles) vs. 2: 2 - 0. */
2357 /* This value is just inherited from the Cortex-A57 table. */
2359 /* See the comment above the Advanced SIMD versions. */
2363 /* Although stores have a latency of 2 and compete for the
2364 vector pipes, in practice it's better not to model that. */
2367 },
2372 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2373 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2374 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2375 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2376 (cost 2) to that, to avoid the difference being lost in rounding.
2378 There is no easy comparison between a strided Advanced SIMD x32 load
2379 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2380 operation more than a 64-bit gather. */
2384 };
2387 {
2393 };
2396 {
2397 {
2403 },
2407 };
2410 {
2411 {
2412 {
2418 },
2422 },
2429 };
2432 {
2435 &neoversen2_sve_issue_info
2436 };
2438 /* Neoverse N2 costs for vector insn classes. */
2440 {
2450 };
2453 {
2481 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2482 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2483 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2485 &generic_prefetch_tune
2486 };
2489 {
2504 /* This value is just inherited from the Cortex-A57 table. */
2506 /* This depends very much on what the scalar value is and
2507 where it comes from. E.g. some constants take two dependent
2508 instructions or a load, while others might be moved from a GPR.
2509 4 seems to be a reasonable compromise in practice. */
2513 /* Although stores have a latency of 2 and compete for the
2514 vector pipes, in practice it's better not to model that. */
2517 };
2520 {
2521 {
2528 /* Theoretically, a reduction involving 15 scalar ADDs could
2529 complete in ~3 cycles and would have a cost of 15. [SU]ADDV
2530 completes in 11 cycles, so give it a cost of 15 + 8. */
2532 /* Likewise for 7 scalar ADDs (~2 cycles) vs. 9: 7 + 7. */
2534 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 4. */
2536 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2538 /* Theoretically, a reduction involving 7 scalar FADDs could
2539 complete in ~6 cycles and would have a cost of 14. FADDV
2540 completes in 8 cycles, so give it a cost of 14 + 2. */
2542 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2544 /* Likewise for 1 scalar FADD (~2 cycles) vs. 4: 2 + 2. */
2547 /* This value is just inherited from the Cortex-A57 table. */
2549 /* See the comment above the Advanced SIMD versions. */
2553 /* Although stores have a latency of 2 and compete for the
2554 vector pipes, in practice it's better not to model that. */
2557 },
2562 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2563 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2564 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2565 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2566 (cost 2) to that, to avoid the difference being lost in rounding.
2568 There is no easy comparison between a strided Advanced SIMD x32 load
2569 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2570 operation more than a 64-bit gather. */
2574 };
2577 {
2583 };
2586 {
2587 {
2593 },
2597 };
2600 {
2601 {
2602 {
2608 },
2612 },
2619 };
2622 {
2625 &neoversev2_sve_issue_info
2626 };
2628 /* Demeter costs for vector insn classes. */
2630 {
2640 };
2643 {
2671 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2672 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2673 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2675 &generic_prefetch_tune
2676 };
2679 {
2708 &a64fx_prefetch_tune
2709 };
2711 /* Support for fine-grained override of the tuning structures. */
2712 struct aarch64_tuning_override_function
2713 {
2716 };
2722 static const struct aarch64_tuning_override_function
2723 aarch64_tuning_override_functions[] =
2724 {
2729 };
2731 /* A processor implementing AArch64. */
2732 struct processor
2733 {
2735 aarch64_processor ident;
2736 aarch64_processor sched_core;
2737 aarch64_arch arch;
2738 aarch64_feature_flags flags;
2740 };
2742 /* Architectures implementing AArch64. */
2744 {
2745 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, D, E) \
2746 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, \
2747 feature_deps::ARCH_IDENT ().enable, NULL},
2750 };
2752 /* Processor cores implementing AArch64. */
2754 {
2755 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, E, COSTS, G, H, I) \
2756 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
2757 feature_deps::cpu_##IDENT, &COSTS##_tunings},
2762 };
2764 /* The current tuning set. */
2767 /* Check whether an 'aarch64_vector_pcs' attribute is valid. */
2769 static tree
2772 {
2773 /* Since we set fn_type_req to true, the caller should have checked
2774 this for us. */
2777 {
2784 name);
2791 }
2793 }
2795 /* Table of machine attributes. */
2797 {
2798 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
2799 affects_type_identity, handler, exclude } */
2804 NULL },
2809 };
2811 /* An ISA extension in the co-processor and main instruction set space. */
2812 struct aarch64_option_extension
2813 {
2817 };
2820 {
2824 }
2825 aarch64_cc;
2827 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
2829 struct aarch64_branch_protect_type
2830 {
2831 /* The type's name that the user passes to the branch-protection option
2832 string. */
2834 /* Function to handle the protection type and set global variables.
2835 First argument is the string token corresponding with this type and the
2836 second argument is the next token in the option string.
2837 Return values:
2838 * AARCH64_PARSE_OK: Handling was sucessful.
2839 * AARCH64_INVALID_ARG: The type is invalid in this context and the caller
2840 should print an error.
2841 * AARCH64_INVALID_FEATURE: The type is invalid and the handler prints its
2842 own error. */
2844 /* A list of types that can follow this type in the option string. */
2847 };
2849 static enum aarch64_parse_opt_result
2851 {
2855 {
2858 }
2860 }
2862 static enum aarch64_parse_opt_result
2864 {
2869 {
2872 }
2874 }
2876 static enum aarch64_parse_opt_result
2879 {
2883 }
2885 static enum aarch64_parse_opt_result
2888 {
2891 }
2893 static enum aarch64_parse_opt_result
2896 {
2899 }
2901 static enum aarch64_parse_opt_result
2904 {
2907 }
2913 };
2922 };
2924 /* The condition codes of the processor, and the inverse function. */
2926 {
2929 };
2931 /* The preferred condition codes for SVE conditions. */
2933 {
2936 };
2938 /* Return the assembly token for svpattern value VALUE. */
2942 {
2944 {
2945 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
2947 #undef CASE
2950 }
2952 }
2954 /* Return the location of a piece that is known to be passed or returned
2955 in registers. FIRST_ZR is the first unused vector argument register
2956 and FIRST_PR is the first unused predicate argument register. */
2958 rtx
2961 {
2973 }
2975 /* Return the total number of vector registers required by the PST. */
2977 unsigned int
2979 {
2984 }
2986 /* Return the total number of predicate registers required by the PST. */
2988 unsigned int
2990 {
2995 }
2997 /* Return the location of a PST that is known to be passed or returned
2998 in registers. FIRST_ZR is the first unused vector argument register
2999 and FIRST_PR is the first unused predicate argument register. */
3001 rtx
3005 {
3006 /* Try to return a single REG if possible. This leads to better
3007 code generation; it isn't required for correctness. */
3009 {
3012 }
3014 /* Build up a PARALLEL that contains the individual pieces. */
3017 {
3023 }
3025 }
3027 /* Analyze whether TYPE is a Pure Scalable Type according to the rules
3028 in the AAPCS64. */
3032 {
3033 /* Prevent accidental reuse. */
3036 /* No code will be generated for erroneous types, so we won't establish
3037 an ABI mapping. */
3041 /* Zero-sized types disappear in the language->ABI mapping. */
3045 /* Check for SVTs, SPTs, and built-in tuple types that map to PSTs. */
3046 piece p = {};
3048 {
3056 }
3058 /* Check for user-defined PSTs. */
3065 }
3067 /* Analyze a type that is known not to be passed or returned in memory.
3068 Return true if it has an ABI identity and is a Pure Scalable Type. */
3070 bool
3072 {
3076 }
3078 /* Subroutine of analyze for handling ARRAY_TYPEs. */
3082 {
3083 /* Analyze the element type. */
3084 pure_scalable_type_info element_info;
3089 /* An array of unknown, flexible or variable length will be passed and
3090 returned by reference whatever we do. */
3095 /* Likewise if the array is constant-sized but too big to be interesting.
3096 The double checks against MAX_PIECES are to protect against overflow. */
3104 /* The above checks should have weeded out elements of unknown size. */
3105 poly_uint64 element_bytes;
3109 /* Build up the list of individual vectors and predicates. */
3113 {
3117 }
3119 }
3121 /* Subroutine of analyze for handling RECORD_TYPEs. */
3125 {
3127 {
3131 /* Zero-sized fields disappear in the language->ABI mapping. */
3135 /* All fields with an ABI identity must be PSTs for the record as
3136 a whole to be a PST. If any individual field is too big to be
3137 interesting then the record is too. */
3138 pure_scalable_type_info field_info;
3145 /* Since all previous fields are PSTs, we ought to be able to track
3146 the field offset using poly_ints. */
3150 /* For the same reason, it shouldn't be possible to create a PST field
3151 whose offset isn't byte-aligned. */
3153 BITS_PER_UNIT);
3155 /* Punt if the record is too big to be interesting. */
3156 poly_uint64 bytepos;
3161 /* Add the individual vectors and predicates in the field to the
3162 record's list. */
3165 {
3169 }
3170 }
3171 /* Empty structures disappear in the language->ABI mapping. */
3173 }
3175 /* Add P to the list of pieces in the type. */
3177 void
3179 {
3180 /* Try to fold the new piece into the previous one to form a
3181 single-mode PST. For example, if we see three consecutive vectors
3182 of the same mode, we can represent them using the corresponding
3183 3-tuple mode.
3185 This is purely an optimization. */
3187 {
3199 {
3203 }
3204 }
3206 }
3208 /* Return true if at least one possible value of type TYPE includes at
3209 least one object of Pure Scalable Type, in the sense of the AAPCS64.
3211 This is a relatively expensive test for some types, so it should
3212 generally be made as late as possible. */
3214 static bool
3216 {
3233 }
3235 /* Return the descriptor of the SIMD ABI. */
3239 {
3242 {
3243 HARD_REG_SET full_reg_clobbers
3249 }
3251 }
3253 /* Return the descriptor of the SVE PCS. */
3257 {
3260 {
3261 HARD_REG_SET full_reg_clobbers
3268 }
3270 }
3272 /* If X is an UNSPEC_SALT_ADDR expression, return the address that it
3273 wraps, otherwise return X itself. */
3275 static rtx
3277 {
3284 }
3286 /* Like strip_offset, but also strip any UNSPEC_SALT_ADDR from the
3287 expression. */
3289 static rtx
3291 {
3293 }
3295 /* Generate code to enable conditional branches in functions over 1 MiB. */
3299 {
3316 }
3318 void
3320 {
3325 else
3328 else
3332 else
3335 }
3337 /* Report when we try to do something that requires SVE when SVE is disabled.
3338 This is an error of last resort and isn't very high-quality. It usually
3339 involves attempts to measure the vector length in some way. */
3340 static void
3342 {
3345 /* Avoid reporting a slew of messages for a single oversight. */
3351 " option %<-march%>, or by using the %<target%>"
3354 }
3356 /* Return true if REGNO is P0-P15 or one of the special FFR-related
3357 registers. */
3360 {
3362 }
3364 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
3365 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
3366 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
3367 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
3368 and GENERAL_REGS is lower than the memory cost (in this case the best class
3369 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
3370 cost results in bad allocations with many redundant int<->FP moves which
3371 are expensive on various cores.
3372 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
3373 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
3374 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
3375 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
3376 The result of this is that it is no longer inefficient to have a higher
3377 memory move cost than the register move cost.
3378 */
3380 static reg_class_t
3382 reg_class_t best_class)
3383 {
3384 machine_mode mode;
3396 }
3398 static unsigned int
3400 {
3404 }
3406 /* Return the reassociation width of treeop OPC with mode MODE. */
3407 static int
3409 {
3414 /* Reassociation reduces the number of FMAs which may result in worse
3415 performance. Use a per-CPU setting for FMA reassociation which allows
3416 narrow CPUs with few FP pipes to switch it off (value of 1), and wider
3417 CPUs with many FP pipes to enable reassociation.
3418 Since the reassociation pass doesn't understand FMA at all, assume
3419 that any FP addition might turn into FMA. */
3424 }
3426 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
3427 unsigned
3429 {
3441 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
3442 equivalent DWARF register. */
3444 }
3446 /* If X is a CONST_DOUBLE, return its bit representation as a constant
3447 integer, otherwise return X unmodified. */
3448 static rtx
3450 {
3454 }
3456 /* Return an estimate for the number of quadwords in an SVE vector. This is
3457 equivalent to the number of Advanced SIMD vectors in an SVE vector. */
3458 static unsigned int
3460 {
3462 }
3464 /* Return true if MODE is an SVE predicate mode. */
3465 static bool
3467 {
3473 }
3475 /* Three mutually-exclusive flags describing a vector or predicate type. */
3479 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
3480 a structure of 2, 3 or 4 vectors. */
3482 /* Can be used in combination with VEC_SVE_DATA to indicate that the
3483 vector has fewer significant bytes than a full SVE vector. */
3485 /* Useful combinations of the above. */
3489 /* Return a set of flags describing the vector properties of mode MODE.
3490 Ignore modes that are not supported by the current target. */
3491 static unsigned int
3493 {
3497 /* Make the decision based on the mode's enum value rather than its
3498 properties, so that we keep the correct classification regardless
3499 of -msve-vector-bits. */
3501 {
3502 /* Partial SVE QI vectors. */
3506 /* Partial SVE HI vectors. */
3509 /* Partial SVE SI vector. */
3511 /* Partial SVE HF vectors. */
3514 /* Partial SVE BF vectors. */
3517 /* Partial SVE SF vector. */
3531 /* x2 SVE vectors. */
3540 /* x3 SVE vectors. */
3549 /* x4 SVE vectors. */
3565 /* Structures of 64-bit Advanced SIMD vectors. */
3592 /* Structures of 128-bit Advanced SIMD vectors. */
3619 /* 64-bit Advanced SIMD vectors. */
3628 /* 128-bit Advanced SIMD vectors. */
3641 }
3642 }
3644 /* Return true if MODE is any of the Advanced SIMD structure modes. */
3645 bool
3647 {
3650 }
3652 /* Return true if MODE is an Advanced SIMD D-register structure mode. */
3653 static bool
3655 {
3658 }
3660 /* Return true if MODE is an Advanced SIMD Q-register structure mode. */
3661 static bool
3663 {
3665 }
3667 /* Return true if MODE is any of the data vector modes, including
3668 structure modes. */
3669 static bool
3671 {
3673 }
3675 /* Return true if MODE is any form of SVE mode, including predicates,
3676 vectors and structures. */
3677 bool
3679 {
3681 }
3683 /* Return true if MODE is an SVE data vector mode; either a single vector
3684 or a structure of vectors. */
3685 static bool
3687 {
3689 }
3691 /* Return the number of defined bytes in one constituent vector of
3692 SVE mode MODE, which has vector flags VEC_FLAGS. */
3693 static poly_int64
3695 {
3697 /* A single partial vector. */
3701 /* A single vector or a tuple. */
3704 /* A single predicate. */
3707 }
3709 /* If MODE holds an array of vectors, return the number of vectors
3710 in the array, otherwise return 1. */
3712 static unsigned int
3714 {
3724 }
3726 /* Given an Advanced SIMD vector mode MODE and a tuple size NELEMS, return the
3727 corresponding vector structure mode. */
3728 static opt_machine_mode
3731 {
3736 machine_mode struct_mode;
3744 }
3746 /* Return the SVE vector mode that has NUNITS elements of mode INNER_MODE. */
3748 opt_machine_mode
3750 {
3753 machine_mode mode;
3760 }
3762 /* Implement target hook TARGET_ARRAY_MODE. */
3763 static opt_machine_mode
3765 {
3775 }
3777 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
3778 static bool
3781 {
3789 }
3791 /* MODE is some form of SVE vector mode. For data modes, return the number
3792 of vector register bits that each element of MODE occupies, such as 64
3793 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored
3794 in a 64-bit container). For predicate modes, return the number of
3795 data bits controlled by each significant predicate bit. */
3797 static unsigned int
3799 {
3802 ? BITS_PER_SVE_VECTOR
3805 }
3807 /* Return the SVE predicate mode to use for elements that have
3808 ELEM_NBYTES bytes, if such a mode exists. */
3810 opt_machine_mode
3812 {
3814 {
3823 }
3825 }
3827 /* Return the SVE predicate mode that should be used to control
3828 SVE mode MODE. */
3830 machine_mode
3832 {
3835 }
3837 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
3839 static opt_machine_mode
3841 {
3847 }
3849 /* Return the integer element mode associated with SVE mode MODE. */
3851 static scalar_int_mode
3853 {
3855 ? BITS_PER_SVE_VECTOR
3860 }
3862 /* Return an integer element mode that contains exactly
3863 aarch64_sve_container_bits (MODE) bits. This is wider than
3864 aarch64_sve_element_int_mode if MODE is a partial vector,
3865 otherwise it's the same. */
3867 static scalar_int_mode
3869 {
3871 }
3873 /* Return the integer vector mode associated with SVE mode MODE.
3874 Unlike related_int_vector_mode, this can handle the case in which
3875 MODE is a predicate (and thus has a different total size). */
3877 machine_mode
3879 {
3882 }
3884 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
3886 static opt_machine_mode
3888 scalar_mode element_mode,
3889 poly_uint64 nunits)
3890 {
3893 /* If we're operating on SVE vectors, try to return an SVE mode. */
3894 poly_uint64 sve_nunits;
3898 {
3899 machine_mode sve_mode;
3901 {
3902 /* Try to find a full or partial SVE mode with exactly
3903 NUNITS units. */
3908 }
3909 else
3910 {
3911 /* Take the preferred number of units from the number of bytes
3912 that fit in VECTOR_MODE. We always start by "autodetecting"
3913 a full vector mode with preferred_simd_mode, so vectors
3914 chosen here will also be full vector modes. Then
3915 autovectorize_vector_modes tries smaller starting modes
3916 and thus smaller preferred numbers of units. */
3921 }
3922 }
3924 /* Prefer to use 1 128-bit vector instead of 2 64-bit vectors. */
3931 {
3935 }
3938 }
3940 /* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
3941 prefer to use the first arithmetic operand as the else value if
3942 the else value doesn't matter, since that exactly matches the SVE
3943 destructive merging form. For ternary operations we could either
3944 pick the first operand and use FMAD-like instructions or the last
3945 operand and use FMLA-like instructions; the latter seems more
3946 natural. */
3948 static tree
3950 {
3952 }
3954 /* Implement TARGET_HARD_REGNO_NREGS. */
3956 static unsigned int
3958 {
3959 /* ??? Logically we should only need to provide a value when
3960 HARD_REGNO_MODE_OK says that the combination is valid,
3961 but at the moment we need to handle all modes. Just ignore
3962 any runtime parts for registers that can't store them. */
3965 {
3969 {
3977 }
3986 }
3988 }
3990 /* Implement TARGET_HARD_REGNO_MODE_OK. */
3992 static bool
3994 {
4003 /* This must have the same size as _Unwind_Word. */
4014 /* The purpose of comparing with ptr_mode is to support the
4015 global register variable associated with the stack pointer
4016 register via the syntax of asm ("wsp") in ILP32. */
4023 {
4030 }
4032 {
4035 else
4037 }
4040 }
4042 /* Return true if a function with type FNTYPE returns its value in
4043 SVE vector or predicate registers. */
4045 static bool
4047 {
4050 pure_scalable_type_info pst_info;
4052 {
4064 }
4066 }
4068 /* Return true if a function with type FNTYPE takes arguments in
4069 SVE vector or predicate registers. */
4071 static bool
4073 {
4074 CUMULATIVE_ARGS args_so_far_v;
4082 {
4089 pure_scalable_type_info pst_info;
4091 {
4096 }
4099 }
4101 }
4103 /* Implement TARGET_FNTYPE_ABI. */
4107 {
4116 }
4118 /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */
4120 static bool
4122 {
4125 }
4127 /* Return true if we should emit CFI for register REGNO. */
4129 static bool
4131 {
4134 }
4136 /* Return the mode we should use to save and restore register REGNO. */
4138 static machine_mode
4140 {
4146 {
4148 /* Only the low 64 bits are saved by the base PCS. */
4152 /* The vector PCS saves the low 128 bits (which is the full
4153 register on non-SVE targets). */
4157 /* Use vectors of DImode for registers that need frame
4158 information, so that the first 64 bytes of the save slot
4159 are always the equivalent of what storing D<n> would give. */
4163 /* Use vectors of bytes otherwise, so that the layout is
4164 endian-agnostic, and so that we can use LDR and STR for
4165 big-endian targets. */
4171 }
4174 /* Save the full predicate register. */
4178 }
4180 /* Implement TARGET_INSN_CALLEE_ABI. */
4184 {
4191 }
4193 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
4194 the lower 64 bits of a 128-bit register. Tell the compiler the callee
4195 clobbers the top 64 bits when restoring the bottom 64 bits. */
4197 static bool
4200 machine_mode mode)
4201 {
4203 {
4211 }
4213 }
4215 /* Implement REGMODE_NATURAL_SIZE. */
4216 poly_uint64
4218 {
4219 /* The natural size for SVE data modes is one SVE data vector,
4220 and similarly for predicates. We can't independently modify
4221 anything smaller than that. */
4222 /* ??? For now, only do this for variable-width SVE registers.
4223 Doing it for constant-sized registers breaks lower-subreg.cc. */
4224 /* ??? And once that's fixed, we should probably have similar
4225 code for Advanced SIMD. */
4227 {
4233 }
4235 }
4237 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
4238 machine_mode
4240 machine_mode mode)
4241 {
4242 /* The predicate mode determines which bits are significant and
4243 which are "don't care". Decreasing the number of lanes would
4244 lose data while increasing the number of lanes would make bits
4245 unnecessarily significant. */
4250 else
4252 }
4254 /* Return true if I's bits are consecutive ones from the MSB. */
4255 bool
4257 {
4259 }
4261 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
4262 that strcpy from constants will be faster. */
4264 static HOST_WIDE_INT
4266 {
4270 }
4272 /* Return true if calls to DECL should be treated as
4273 long-calls (ie called via a register). */
4274 static bool
4276 {
4278 }
4280 /* Return true if calls to symbol-ref SYM should be treated as
4281 long-calls (ie called via a register). */
4282 bool
4284 {
4286 }
4288 /* Return true if calls to symbol-ref SYM should not go through
4289 plt stubs. */
4291 bool
4293 {
4297 && decl
4298 && (!flag_plt
4304 }
4306 /* Emit an insn that's a simple single-set. Both the operands must be
4307 known to be valid. */
4310 {
4312 }
4314 /* X and Y are two things to compare using CODE. Emit the compare insn and
4315 return the rtx for register 0 in the proper mode. */
4316 rtx
4318 {
4320 machine_mode cc_mode;
4321 rtx cc_reg;
4324 {
4339 }
4340 else
4341 {
4345 }
4347 }
4349 /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
4351 static rtx
4353 machine_mode y_mode)
4354 {
4356 {
4358 {
4361 }
4362 else
4363 {
4365 machine_mode cc_mode;
4373 }
4374 }
4380 }
4382 /* Consider the operation:
4384 OPERANDS[0] = CODE (OPERANDS[1], OPERANDS[2]) + OPERANDS[3]
4386 where:
4388 - CODE is [SU]MAX or [SU]MIN
4389 - OPERANDS[2] and OPERANDS[3] are constant integers
4390 - OPERANDS[3] is a positive or negative shifted 12-bit immediate
4391 - all operands have mode MODE
4393 Decide whether it is possible to implement the operation using:
4395 SUBS <tmp>, OPERANDS[1], -OPERANDS[3]
4396 or
4397 ADDS <tmp>, OPERANDS[1], OPERANDS[3]
4399 followed by:
4401 <insn> OPERANDS[0], <tmp>, [wx]zr, <cond>
4403 where <insn> is one of CSEL, CSINV or CSINC. Return true if so.
4404 If GENERATE_P is true, also update OPERANDS as follows:
4406 OPERANDS[4] = -OPERANDS[3]
4407 OPERANDS[5] = the rtl condition representing <cond>
4408 OPERANDS[6] = <tmp>
4409 OPERANDS[7] = 0 for CSEL, -1 for CSINV or 1 for CSINC. */
4410 bool
4412 {
4419 /* max (x, y) - z == (x >= y + 1 ? x : y) - z
4420 == (x >= y ? x : y) - z
4421 == (x > y ? x : y) - z
4422 == (x > y - 1 ? x : y) - z
4424 min (x, y) - z == (x <= y - 1 ? x : y) - z
4425 == (x <= y ? x : y) - z
4426 == (x < y ? x : y) - z
4427 == (x < y + 1 ? x : y) - z
4429 Check whether z is in { y - 1, y, y + 1 } and pick the form(s) for
4430 which x is compared with z. Set DIFF to y - z. Thus the supported
4431 combinations are as follows, with DIFF being the value after the ":":
4433 max (x, y) - z == x >= y + 1 ? x - (y + 1) : -1 [z == y + 1]
4434 == x >= y ? x - y : 0 [z == y]
4435 == x > y ? x - y : 0 [z == y]
4436 == x > y - 1 ? x - (y - 1) : 1 [z == y - 1]
4438 min (x, y) - z == x <= y - 1 ? x - (y - 1) : 1 [z == y - 1]
4439 == x <= y ? x - y : 0 [z == y]
4440 == x < y ? x - y : 0 [z == y]
4441 == x < y + 1 ? x - (y + 1) : -1 [z == y + 1]. */
4454 rtx_code cmp;
4456 {
4471 }
4478 else
4483 }
4486 /* Build the SYMBOL_REF for __tls_get_addr. */
4490 rtx
4492 {
4496 }
4498 /* Return the TLS model to use for ADDR. */
4500 static enum tls_model
4502 {
4504 poly_int64 offset;
4510 }
4512 /* We'll allow lo_sum's in addresses in our legitimate addresses
4513 so that combine would take care of combining addresses where
4514 necessary, but for generation purposes, we'll generate the address
4515 as :
4516 RTL Absolute
4517 tmp = hi (symbol_ref); adrp x1, foo
4518 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
4519 nop
4521 PIC TLS
4522 adrp x1, :got:foo adrp tmp, :tlsgd:foo
4523 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
4524 bl __tls_get_addr
4525 nop
4527 Load TLS symbol, depending on TLS mechanism and TLS access model.
4529 Global Dynamic - Traditional TLS:
4530 adrp tmp, :tlsgd:imm
4531 add dest, tmp, #:tlsgd_lo12:imm
4532 bl __tls_get_addr
4534 Global Dynamic - TLS Descriptors:
4535 adrp dest, :tlsdesc:imm
4536 ldr tmp, [dest, #:tlsdesc_lo12:imm]
4537 add dest, dest, #:tlsdesc_lo12:imm
4538 blr tmp
4539 mrs tp, tpidr_el0
4540 add dest, dest, tp
4542 Initial Exec:
4543 mrs tp, tpidr_el0
4544 adrp tmp, :gottprel:imm
4545 ldr dest, [tmp, #:gottprel_lo12:imm]
4546 add dest, dest, tp
4548 Local Exec:
4549 mrs tp, tpidr_el0
4550 add t0, tp, #:tprel_hi12:imm, lsl #12
4551 add t0, t0, #:tprel_lo12_nc:imm
4552 */
4554 static void
4557 {
4559 {
4561 {
4562 /* In ILP32, the mode of dest can be either SImode or DImode. */
4574 }
4581 {
4584 rtx insn;
4585 rtx mem;
4587 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
4588 here before rtl expand. Tree IVOPT will generate rtl pattern to
4589 decide rtx costs, in which case pic_offset_table_rtx is not
4590 initialized. For that case no need to generate the first adrp
4591 instruction as the final cost for global variable access is
4592 one instruction. */
4594 {
4595 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
4596 using the page base as GOT base, the first page may be wasted,
4597 in the worst scenario, there is only 28K space for GOT).
4599 The generate instruction sequence for accessing global variable
4600 is:
4602 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
4604 Only one instruction needed. But we must initialize
4605 pic_offset_table_rtx properly. We generate initialize insn for
4606 every global access, and allow CSE to remove all redundant.
4608 The final instruction sequences will look like the following
4609 for multiply global variables access.
4611 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
4613 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
4614 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
4615 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
4616 ... */
4625 }
4628 {
4631 else
4635 }
4636 else
4637 {
4642 }
4644 /* The operand is expected to be MEM. Whenever the related insn
4645 pattern changed, above code which calculate mem should be
4646 updated. */
4652 }
4659 {
4661 /* The return type of __tls_get_addr is the C pointer type
4662 so use ptr_mode. */
4672 else
4679 /* Convert back to the mode of the dest adding a zero_extend
4680 from SImode (ptr_mode) to DImode (Pmode). */
4684 }
4687 {
4690 rtx tp;
4694 /* In ILP32, the got entry is always of SImode size. Unlike
4695 small GOT, the dest is fixed at reg 0. */
4698 else
4709 }
4712 {
4713 /* In ILP32, the mode of dest can be either SImode or DImode,
4714 while the got entry is always of SImode size. The mode of
4715 dest depends on how dest is used: if dest is assigned to a
4716 pointer (e.g. in the memory), it has SImode; it may have
4717 DImode if dest is dereferenced to access the memeory.
4718 This is why we have to handle three different tlsie_small
4719 patterns here (two patterns for ILP32). */
4725 {
4728 else
4729 {
4732 }
4733 }
4734 else
4735 {
4738 }
4744 }
4750 {
4758 {
4781 }
4786 }
4789 {
4790 rtx insn;
4795 else
4796 {
4799 }
4803 }
4806 {
4811 {
4814 else
4815 {
4818 }
4819 }
4820 else
4821 {
4824 }
4829 }
4833 }
4834 }
4836 /* Emit a move from SRC to DEST. Assume that the move expanders can
4837 handle all moves if !can_create_pseudo_p (). The distinction is
4838 important because, unlike emit_move_insn, the move expanders know
4839 how to force Pmode objects into the constant pool even when the
4840 constant pool address is not itself legitimate. */
4841 static rtx
4843 {
4847 }
4849 /* Apply UNOPTAB to OP and store the result in DEST. */
4851 static void
4853 {
4857 }
4859 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
4861 static void
4863 {
4865 OPTAB_DIRECT);
4868 }
4870 /* Split a 128-bit move operation into two 64-bit move operations,
4871 taking care to handle partial overlap of register to register
4872 copies. Special cases are needed when moving between GP regs and
4873 FP regs. SRC can be a register, constant or memory; DST a register
4874 or memory. If either operand is memory it must not have any side
4875 effects. */
4876 void
4878 {
4889 {
4893 /* Handle FP <-> GP regs. */
4895 {
4902 }
4904 {
4911 }
4912 }
4919 /* At most one pairing may overlap. */
4921 {
4924 }
4925 else
4926 {
4929 }
4930 }
4932 /* Return true if we should split a move from 128-bit value SRC
4933 to 128-bit register DEST. */
4935 bool
4937 {
4940 /* All moves to GPRs need to be split. */
4942 }
4944 /* Split a complex SIMD move. */
4946 void
4948 {
4955 {
4958 }
4959 }
4961 bool
4964 {
4968 }
4970 /* Return TARGET if it is nonnull and a register of mode MODE.
4971 Otherwise, return a fresh register of mode MODE if we can,
4972 or TARGET reinterpreted as MODE if we can't. */
4974 static rtx
4976 {
4980 {
4983 }
4985 }
4987 /* Return a register that contains the constant in BUILDER, given that
4988 the constant is a legitimate move operand. Use TARGET as the register
4989 if it is nonnull and convenient. */
4991 static rtx
4993 {
4998 }
5000 static rtx
5002 {
5005 else
5006 {
5010 }
5011 }
5013 /* Return true if predicate value X is a constant in which every element
5014 is a CONST_INT. When returning true, describe X in BUILDER as a VNx16BI
5015 value, i.e. as a predicate in which all bits are significant. */
5017 static bool
5019 {
5031 {
5039 }
5042 }
5044 /* BUILDER contains a predicate constant of mode VNx16BI. Return the
5045 widest predicate element size it can have (that is, the largest size
5046 for which each element would still be 0 or 1). */
5048 unsigned int
5050 {
5051 /* Start with the most optimistic assumption: that we only need
5052 one bit per pattern. This is what we will use if only the first
5053 bit in each pattern is ever set. */
5057 /* Look for set bits. */
5061 {
5065 }
5067 }
5069 /* If VNx16BImode rtx X is a canonical PTRUE for a predicate mode,
5070 return that predicate mode, otherwise return opt_machine_mode (). */
5072 opt_machine_mode
5074 {
5088 }
5090 /* BUILDER is a predicate constant of mode VNx16BI. Consider the value
5091 that the constant would have with predicate element size ELT_SIZE
5092 (ignoring the upper bits in each element) and return:
5094 * -1 if all bits are set
5095 * N if the predicate has N leading set bits followed by all clear bits
5096 * 0 if the predicate does not have any of these forms. */
5098 int
5101 {
5102 /* If nelts_per_pattern is 3, we have set bits followed by clear bits
5103 followed by set bits. */
5107 /* Skip over leading set bits. */
5115 /* Check for the all-true case. */
5119 /* If nelts_per_pattern is 1, then either VL is zero, or we have a
5120 repeating pattern of set bits followed by clear bits. */
5124 /* We have a "foreground" value and a duplicated "background" value.
5125 If the background might repeat and the last set bit belongs to it,
5126 we might have set bits followed by clear bits followed by set bits. */
5130 /* Make sure that the rest are all clear. */
5136 }
5138 /* See if there is an svpattern that encodes an SVE predicate of mode
5139 PRED_MODE in which the first VL bits are set and the rest are clear.
5140 Return the pattern if so, otherwise return AARCH64_NUM_SVPATTERNS.
5141 A VL of -1 indicates an all-true vector. */
5143 aarch64_svpattern
5145 {
5160 {
5163 /* These would only trigger for non-power-of-2 lengths. */
5170 }
5172 }
5174 /* Return a VNx16BImode constant in which every sequence of ELT_SIZE
5175 bits has the lowest bit set and the upper bits clear. This is the
5176 VNx16BImode equivalent of a PTRUE for controlling elements of
5177 ELT_SIZE bytes. However, because the constant is VNx16BImode,
5178 all bits are significant, even the upper zeros. */
5180 rtx
5182 {
5188 }
5190 /* Return an all-true predicate register of mode MODE. */
5192 rtx
5194 {
5198 }
5200 /* Return an all-false predicate register of mode MODE. */
5202 rtx
5204 {
5208 }
5210 /* PRED1[0] is a PTEST predicate and PRED1[1] is an aarch64_sve_ptrue_flag
5211 for it. PRED2[0] is the predicate for the instruction whose result
5212 is tested by the PTEST and PRED2[1] is again an aarch64_sve_ptrue_flag
5213 for it. Return true if we can prove that the two predicates are
5214 equivalent for PTEST purposes; that is, if we can replace PRED2[0]
5215 with PRED1[0] without changing behavior. */
5217 bool
5219 {
5231 }
5233 /* Emit a comparison CMP between OP0 and OP1, both of which have mode
5234 DATA_MODE, and return the result in a predicate of mode PRED_MODE.
5235 Use TARGET as the target register if nonnull and convenient. */
5237 static rtx
5240 {
5250 }
5252 /* Use a comparison to convert integer vector SRC into MODE, which is
5253 the corresponding SVE predicate mode. Use TARGET for the result
5254 if it's nonnull and convenient. */
5256 rtx
5258 {
5262 }
5264 /* Return the assembly token for svprfop value PRFOP. */
5268 {
5270 {
5271 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
5273 #undef CASE
5276 }
5278 }
5280 /* Return the assembly string for an SVE prefetch operation with
5281 mnemonic MNEMONIC, given that PRFOP_RTX is the prefetch operation
5282 and that SUFFIX is the format for the remaining operands. */
5287 {
5294 }
5296 /* Check whether we can calculate the number of elements in PATTERN
5297 at compile time, given that there are NELTS_PER_VQ elements per
5298 128-bit block. Return the value if so, otherwise return -1. */
5300 HOST_WIDE_INT
5302 {
5309 {
5310 /* There are two vector granules per quadword. */
5313 {
5319 }
5320 }
5321 else
5324 /* There are two vector granules per quadword. */
5329 /* Requesting more elements than are available results in a PFALSE. */
5334 }
5336 /* Return true if we can move VALUE into a register using a single
5337 CNT[BHWD] instruction. */
5339 static bool
5341 {
5343 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
5348 }
5350 /* Likewise for rtx X. */
5352 bool
5354 {
5355 poly_int64 value;
5357 }
5359 /* Return the asm string for an instruction with a CNT-like vector size
5360 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5361 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5362 first part of the operands template (the part that comes before the
5363 vector size itself). PATTERN is the pattern to use. FACTOR is the
5364 number of quadwords. NELTS_PER_VQ, if nonzero, is the number of elements
5365 in each quadword. If it is zero, we can use any element size. */
5369 aarch64_svpattern pattern,
5372 {
5376 /* There is some overlap in the ranges of the four CNT instructions.
5377 Here we always use the smallest possible element size, so that the
5378 multiplier is 1 whereever possible. */
5392 else
5395 factor);
5398 }
5400 /* Return the asm string for an instruction with a CNT-like vector size
5401 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5402 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5403 first part of the operands template (the part that comes before the
5404 vector size itself). X is the value of the vector size operand,
5405 as a polynomial integer rtx; we need to convert this into an "all"
5406 pattern with a multiplier. */
5410 rtx x)
5411 {
5416 }
5418 /* Return the asm string for an instruction with a CNT-like vector size
5419 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5420 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5421 first part of the operands template (the part that comes before the
5422 vector size itself). CNT_PAT[0..2] are the operands of the
5423 UNSPEC_SVE_CNT_PAT; see aarch64_sve_cnt_pat for details. */
5428 {
5434 }
5436 /* Return true if we can add X using a single SVE INC or DEC instruction. */
5438 bool
5440 {
5441 poly_int64 value;
5445 }
5447 /* Return the asm string for adding SVE INC/DEC immediate OFFSET to
5448 operand 0. */
5452 {
5458 else
5461 }
5463 /* Return true if we can add VALUE to a register using a single ADDVL
5464 or ADDPL instruction. */
5466 static bool
5468 {
5472 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
5473 and a value of 16 is one vector width. */
5476 }
5478 /* Likewise for rtx X. */
5480 bool
5482 {
5483 poly_int64 value;
5486 }
5488 /* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
5489 to operand 1 and storing the result in operand 0. */
5493 {
5501 else
5504 }
5506 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5507 instruction. If it is, store the number of elements in each vector
5508 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
5509 factor in *FACTOR_OUT (if nonnull). */
5511 bool
5514 {
5515 rtx elt;
5516 poly_int64 value;
5524 /* There's no vector INCB. */
5531 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
5541 }
5543 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5544 instruction. */
5546 bool
5548 {
5550 }
5552 /* Return the asm template for an SVE vector INC or DEC instruction.
5553 OPERANDS gives the operands before the vector count and X is the
5554 value of the vector count operand itself. */
5558 {
5566 else
5569 }
5571 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5574 {
5580 };
5584 /* Return true if 64-bit VAL is a valid bitmask immediate. */
5585 static bool
5587 {
5591 /* Check for a single sequence of one bits and return quickly if so.
5592 The special cases of all ones and all zeroes returns false. */
5598 /* Invert if the immediate doesn't start with a zero bit - this means we
5599 only need to search for sequences of one bits. */
5603 /* Find the first set bit and set tmp to val with the first sequence of one
5604 bits removed. Return success if there is a single sequence of ones. */
5611 /* Find the next set bit and compute the difference in bit position. */
5616 /* Check the bit position difference is a power of 2, and that the first
5617 sequence of one bits fits within 'bits' bits. */
5621 /* Check the sequence of one bits is repeated 64/bits times. */
5623 }
5626 /* Return true if VAL is a valid bitmask immediate for MODE. */
5627 bool
5629 {
5636 /* Replicate small immediates to fit 64 bits. */
5642 }
5645 /* Return true if the immediate VAL can be a bitfield immediate
5646 by changing the given MASK bits in VAL to zeroes, ones or bits
5647 from the other half of VAL. Return the new immediate in VAL2. */
5652 {
5667 }
5670 /* Return true if VAL is a valid MOVZ immediate. */
5673 {
5675 }
5678 /* Return true if immediate VAL can be created by a 64-bit MOVI/MOVN/MOVZ. */
5679 bool
5681 {
5684 }
5687 /* Return true if VAL is an immediate that can be created by a single
5688 MOV instruction. */
5689 bool
5691 {
5705 }
5708 static int
5710 machine_mode mode)
5711 {
5722 {
5726 }
5729 {
5731 {
5736 else
5739 }
5741 }
5743 /* Remaining cases are all for DImode. */
5751 /* Try a bitmask immediate and a movk to generate the immediate
5752 in 2 instructions. */
5755 {
5757 {
5764 }
5767 {
5769 {
5773 }
5775 }
5776 }
5778 /* Try a bitmask plus 2 movk to generate the immediate in 3 instructions. */
5780 {
5784 {
5786 {
5792 }
5794 }
5795 }
5797 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
5798 are emitted by the initial mov. If one_match > zero_match, skip set bits,
5799 otherwise skip zero bits. */
5811 {
5817 num_insns ++;
5818 }
5821 }
5823 /* Return whether imm is a 128-bit immediate which is simple enough to
5824 expand inline. */
5825 bool
5827 {
5838 }
5841 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5842 a left shift of 0 or 12 bits. */
5843 bool
5845 {
5847 }
5849 /* Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate
5850 that can be created with a left shift of 0 or 12. */
5851 static HOST_WIDE_INT
5853 {
5854 /* Check to see if the value fits in 24 bits, as that is the maximum we can
5855 handle correctly. */
5862 }
5865 /* Test whether:
5867 X = (X & AND_VAL) | IOR_VAL;
5869 can be implemented using:
5871 MOVK X, #(IOR_VAL >> shift), LSL #shift
5873 Return the shift if so, otherwise return -1. */
5874 int
5877 {
5881 {
5885 }
5887 }
5889 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5890 Assumed precondition: VAL_IN Is not zero. */
5892 unsigned HOST_WIDE_INT
5894 {
5901 }
5903 /* Create constant where bits outside of lowest bit set to highest bit set
5904 are set to 1. */
5906 unsigned HOST_WIDE_INT
5908 {
5910 }
5912 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5914 bool
5916 {
5917 scalar_int_mode int_mode;
5930 }
5932 /* Return the number of temporary registers that aarch64_add_offset_1
5933 would need to add OFFSET to a register. */
5935 static unsigned int
5937 {
5939 }
5941 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
5942 a non-polynomial OFFSET. MODE is the mode of the addition.
5943 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
5944 be set and CFA adjustments added to the generated instructions.
5946 TEMP1, if nonnull, is a register of mode MODE that can be used as a
5947 temporary if register allocation is already complete. This temporary
5948 register may overlap DEST but must not overlap SRC. If TEMP1 is known
5949 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
5950 the immediate again.
5952 Since this function may be used to adjust the stack pointer, we must
5953 ensure that it cannot cause transient stack deallocation (for example
5954 by first incrementing SP and then decrementing when adjusting by a
5955 large immediate). */
5957 static void
5961 {
5969 {
5971 {
5974 }
5976 }
5978 /* Single instruction adjustment. */
5980 {
5984 }
5986 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
5987 and either:
5989 a) the offset cannot be loaded by a 16-bit move or
5990 b) there is no spare register into which we can move it. */
5994 {
6003 }
6005 /* Emit a move immediate if required and an addition/subtraction. */
6007 {
6011 }
6016 {
6020 }
6021 }
6023 /* Return the number of temporary registers that aarch64_add_offset
6024 would need to move OFFSET into a register or add OFFSET to a register;
6025 ADD_P is true if we want the latter rather than the former. */
6027 static unsigned int
6029 {
6030 /* This follows the same structure as aarch64_add_offset. */
6039 /* Need one register for the ADDVL/ADDPL result. */
6042 {
6045 /* Need one register for the CNT result and one for the multiplication
6046 factor. If necessary, the second temporary can be reused for the
6047 constant part of the offset. */
6049 /* Need one register for the CNT result (which might then
6050 be shifted). */
6052 }
6054 }
6056 /* If X can be represented as a poly_int64, return the number
6057 of temporaries that are required to add it to a register.
6058 Return -1 otherwise. */
6060 int
6062 {
6063 poly_int64 offset;
6067 }
6069 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
6070 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
6071 be set and CFA adjustments added to the generated instructions.
6073 TEMP1, if nonnull, is a register of mode MODE that can be used as a
6074 temporary if register allocation is already complete. This temporary
6075 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
6076 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
6077 false to avoid emitting the immediate again.
6079 TEMP2, if nonnull, is a second temporary register that doesn't
6080 overlap either DEST or REG.
6082 Since this function may be used to adjust the stack pointer, we must
6083 ensure that it cannot cause transient stack deallocation (for example
6084 by first incrementing SP and then decrementing when adjusting by a
6085 large immediate). */
6087 static void
6091 {
6095 || !frame_related_p
6099 /* Try using ADDVL or ADDPL to add the whole value. */
6101 {
6106 }
6108 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
6109 SVE vector register, over and above the minimum size of 128 bits.
6110 This is equivalent to half the value returned by CNTD with a
6111 vector shape of ALL. */
6115 /* Try using ADDVL or ADDPL to add the VG-based part. */
6119 {
6122 {
6126 }
6127 else
6128 {
6133 }
6134 }
6135 /* Otherwise use a CNT-based sequence. */
6137 {
6138 /* Use a subtraction if we have a negative factor. */
6141 {
6144 }
6146 /* Calculate CNTD * FACTOR / 2. First try to fold the division
6147 into the multiplication. */
6148 rtx val;
6151 /* Use a right shift by 1. */
6153 else
6157 {
6159 {
6160 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
6161 the value with the minimum multiplier and shift it into
6162 position. */
6166 }
6168 }
6169 else
6170 {
6171 /* Base the factor on LOW_BIT if we can calculate LOW_BIT
6172 directly, since that should increase the chances of being
6173 able to use a shift and add sequence. If LOW_BIT itself
6174 is out of range, just use CNTD. */
6177 else
6184 {
6187 }
6188 else
6189 {
6190 /* Go back to using a negative multiplication factor if we have
6191 no register from which to subtract. */
6193 {
6196 }
6200 }
6201 }
6204 {
6205 /* Multiply by 1 << SHIFT. */
6208 }
6210 {
6211 /* Divide by 2. */
6214 }
6216 /* Calculate SRC +/- CNTD * FACTOR / 2. */
6218 {
6221 }
6223 {
6226 }
6229 {
6232 {
6236 poly_offset)));
6237 }
6241 }
6242 else
6243 {
6247 }
6250 }
6254 }
6256 /* Like aarch64_add_offset, but the offset is given as an rtx rather
6257 than a poly_int64. */
6259 void
6262 {
6265 }
6267 /* Add DELTA to the stack pointer, marking the instructions frame-related.
6268 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
6269 if TEMP1 already contains abs (DELTA). */
6273 {
6276 }
6278 /* Subtract DELTA from the stack pointer, marking the instructions
6279 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
6280 if nonnull. */
6285 {
6288 }
6290 /* Set DEST to (vec_series BASE STEP). */
6292 static void
6294 {
6298 /* Each operand can be a register or an immediate in the range [-16, 15]. */
6305 }
6307 /* Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE
6308 register of mode MODE. Use TARGET for the result if it's nonnull
6309 and convenient.
6311 The two vector modes must have the same element mode. The behavior
6312 is to duplicate architectural lane N of SRC into architectural lanes
6313 N + I * STEP of the result. On big-endian targets, architectural
6314 lane 0 of an Advanced SIMD vector is the last element of the vector
6315 in memory layout, so for big-endian targets this operation has the
6316 effect of reversing SRC before duplicating it. Callers need to
6317 account for this. */
6319 rtx
6321 {
6324 insn_code icode = (BYTES_BIG_ENDIAN
6333 {
6334 /* Create a PARALLEL describing the reversal of SRC. */
6339 }
6342 }
6344 /* Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch
6345 the memory image into DEST. Return true on success. */
6347 static bool
6349 {
6354 /* Make sure that the address is legitimate. */
6356 {
6359 }
6366 }
6368 /* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed
6369 by N "background" values. Try to move it into TARGET using:
6371 PTRUE PRED.<T>, VL<N>
6372 MOV TRUE.<T>, #<foreground>
6373 MOV FALSE.<T>, #<background>
6374 SEL TARGET.<T>, PRED.<T>, TRUE.<T>, FALSE.<T>
6376 The PTRUE is always a single instruction but the MOVs might need a
6377 longer sequence. If the background value is zero (as it often is),
6378 the sequence can sometimes collapse to a PTRUE followed by a
6379 zero-predicated move.
6381 Return the target on success, otherwise return null. */
6383 static rtx
6385 {
6388 /* Make sure that the PTRUE is valid. */
6400 {
6403 }
6405 {
6408 }
6416 }
6418 /* Return a register containing CONST_VECTOR SRC, given that SRC has an
6419 SVE data mode and isn't a legitimate constant. Use TARGET for the
6420 result if convenient.
6422 The returned register can have whatever mode seems most natural
6423 given the contents of SRC. */
6425 static rtx
6427 {
6439 {
6440 /* We have a partial vector mode and a constant whose full-vector
6441 equivalent would occupy a repeating 128-bit sequence. Build that
6442 full-vector equivalent instead, so that we have the option of
6443 using LD1RQ and Advanced SIMD operations. */
6452 }
6455 {
6456 /* The constant is a duplicated quadword but can't be narrowed
6457 beyond a quadword. Get the memory image of the first quadword
6458 as a 128-bit vector and try using LD1RQ to load it from memory.
6460 The effect for both endiannesses is to load memory lane N into
6461 architectural lanes N + I * STEP of the result. On big-endian
6462 targets, the layout of the 128-bit vector in an Advanced SIMD
6463 register would be different from its layout in an SVE register,
6464 but this 128-bit vector is a memory value only. */
6469 }
6472 {
6473 /* The vector is a repeating sequence of 64 bits or fewer.
6474 See if we can load them using an Advanced SIMD move and then
6475 duplicate it to fill a vector. This is better than using a GPR
6476 move because it keeps everything in the same register file. */
6480 {
6481 /* We want memory lane N to go into architectural lane N,
6482 so reverse for big-endian targets. The DUP .Q pattern
6483 has a compensating reverse built-in. */
6486 }
6489 {
6492 }
6494 /* Get an integer representation of the repeating part of Advanced
6495 SIMD vector VQ_SRC. This preserves the endianness of VQ_SRC,
6496 which for big-endian targets is lane-swapped wrt a normal
6497 Advanced SIMD vector. This means that for both endiannesses,
6498 memory lane N of SVE vector SRC corresponds to architectural
6499 lane N of a register holding VQ_SRC. This in turn means that
6500 memory lane 0 of SVE vector SRC is in the lsb of VQ_SRC (viewed
6501 as a single 128-bit value) and thus that memory lane 0 of SRC is
6502 in the lsb of the integer. Duplicating the integer therefore
6503 ensures that memory lane N of SRC goes into architectural lane
6504 N + I * INDEX of the SVE register. */
6508 {
6509 /* Pretend that we had a vector of INT_MODE to start with. */
6513 /* If the integer can be moved into a general register by a
6514 single instruction, do that and duplicate the result. */
6517 {
6520 }
6521 }
6523 /* We're duplicating a single value, but can't do better than
6524 force it to memory and load from there. This handles things
6525 like symbolic constants. */
6529 {
6530 /* Load the element from memory if we can, otherwise move it into
6531 a register and use a DUP. */
6536 }
6537 }
6539 /* Try using INDEX. */
6542 {
6545 }
6547 /* From here on, it's better to force the whole constant to memory
6548 if we can. */
6556 /* Expand each pattern individually. */
6558 rtx_vector_builder builder;
6561 {
6566 }
6568 /* Use permutes to interleave the separate vectors. */
6570 {
6573 {
6578 }
6579 }
6582 }
6584 /* Use WHILE to set a predicate register of mode MODE in which the first
6585 VL bits are set and the rest are clear. Use TARGET for the register
6586 if it's nonnull and convenient. */
6588 static rtx
6591 {
6597 }
6599 static rtx
6602 /* BUILDER is a constant predicate in which the index of every set bit
6603 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6604 by inverting every element at a multiple of ELT_SIZE and EORing the
6605 result with an ELT_SIZE PTRUE.
6607 Return a register that contains the constant on success, otherwise
6608 return null. Use TARGET as the register if it is nonnull and
6609 convenient. */
6611 static rtx
6614 {
6615 /* Invert every element at a multiple of ELT_SIZE, keeping the
6616 other bits zero. */
6622 else
6626 /* See if we can load the constant cheaply. */
6631 /* EOR the result with an ELT_SIZE PTRUE. */
6638 }
6640 /* BUILDER is a constant predicate in which the index of every set bit
6641 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6642 using a TRN1 of size PERMUTE_SIZE, which is >= ELT_SIZE. Return the
6643 register on success, otherwise return null. Use TARGET as the register
6644 if nonnull and convenient. */
6646 static rtx
6650 {
6651 /* We're going to split the constant into two new constants A and B,
6652 with element I of BUILDER going into A if (I & PERMUTE_SIZE) == 0
6653 and into B otherwise. E.g. for PERMUTE_SIZE == 4 && ELT_SIZE == 1:
6655 A: { 0, 1, 2, 3, _, _, _, _, 8, 9, 10, 11, _, _, _, _ }
6656 B: { 4, 5, 6, 7, _, _, _, _, 12, 13, 14, 15, _, _, _, _ }
6658 where _ indicates elements that will be discarded by the permute.
6660 First calculate the ELT_SIZEs for A and B. */
6665 {
6668 else
6670 }
6674 /* Now construct the vectors themselves. */
6682 {
6685 }
6687 {
6688 /* The A and B elements are significant. */
6691 }
6692 else
6693 {
6694 /* The A and B elements are going to be discarded, so pick whatever
6695 is likely to give a nice constant. We are targeting element
6696 sizes A_ELT_SIZE and B_ELT_SIZE for A and B respectively,
6697 with the aim of each being a sequence of ones followed by
6698 a sequence of zeros. So:
6700 * if X_ELT_SIZE <= PERMUTE_SIZE, the best approach is to
6701 duplicate the last X_ELT_SIZE element, to extend the
6702 current sequence of ones or zeros.
6704 * if X_ELT_SIZE > PERMUTE_SIZE, the best approach is to add a
6705 zero, so that the constant really does have X_ELT_SIZE and
6706 not a smaller size. */
6709 else
6713 else
6715 }
6719 /* Try loading A into a register. */
6725 /* Try loading B into a register. */
6728 {
6731 {
6734 }
6735 }
6737 /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI
6738 operands but permutes them as though they had mode MODE. */
6744 }
6746 /* Subroutine of aarch64_expand_sve_const_pred. Try to load the VNx16BI
6747 constant in BUILDER into an SVE predicate register. Return the register
6748 on success, otherwise return null. Use TARGET for the register if
6749 nonnull and convenient.
6751 ALLOW_RECURSE_P is true if we can use methods that would call this
6752 function recursively. */
6754 static rtx
6757 {
6759 /* A PFALSE or a PTRUE .B ALL. */
6764 {
6765 /* If we can load the constant using PTRUE, use it as-is. */
6770 /* Otherwise use WHILE to set the first VL bits. */
6772 }
6777 /* Try inverting the vector in element size ELT_SIZE and then EORing
6778 the result with an ELT_SIZE PTRUE. */
6781 elt_size))
6784 /* Try using TRN1 to permute two simpler constants. */
6791 }
6793 /* Return an SVE predicate register that contains the VNx16BImode
6794 constant in BUILDER, without going through the move expanders.
6796 The returned register can have whatever mode seems most natural
6797 given the contents of BUILDER. Use TARGET for the result if
6798 convenient. */
6800 static rtx
6802 {
6803 /* Try loading the constant using pure predicate operations. */
6807 /* Try forcing the constant to memory. */
6810 {
6814 }
6816 /* The last resort is to load the constant as an integer and then
6817 compare it against zero. Use -1 for set bits in order to increase
6818 the changes of using SVE DUPM or an Advanced SIMD byte mask. */
6826 }
6828 /* Set DEST to immediate IMM. */
6830 void
6832 {
6835 /* Check on what type of symbol it is. */
6836 scalar_int_mode int_mode;
6842 {
6843 rtx mem;
6844 poly_int64 offset;
6845 HOST_WIDE_INT const_offset;
6848 /* If we have (const (plus symbol offset)), separate out the offset
6849 before we start classifying the symbol. */
6852 /* We must always add an offset involving VL separately, rather than
6853 folding it into the relocation. */
6855 {
6857 {
6860 }
6863 else
6864 {
6865 /* Do arithmetic on 32-bit values if the result is smaller
6866 than that. */
6868 {
6869 /* It is invalid to do symbol calculations in modes
6870 narrower than SImode. */
6874 }
6876 {
6880 }
6881 else
6884 }
6886 }
6890 {
6897 {
6903 }
6908 /* If we aren't generating PC relative literals, then
6909 we need to expand the literal pool access carefully.
6910 This is something that needs to be done in a number
6911 of places, so could well live as a separate function. */
6913 {
6920 }
6937 {
6943 }
6944 /* FALLTHRU */
6957 }
6958 }
6961 {
6963 {
6964 /* Only the low bit of each .H, .S and .D element is defined,
6965 so we can set the upper bits to whatever we like. If the
6966 predicate is all-true in MODE, prefer to set all the undefined
6967 bits as well, so that we can share a single .B predicate for
6968 all modes. */
6972 /* All methods for constructing predicate modes wider than VNx16BI
6973 will set the upper bits of each element to zero. Expose this
6974 by moving such constants as a VNx16BI, so that all bits are
6975 significant and so that constants for different modes can be
6976 shared. The wider constant will still be available as a
6977 REG_EQUAL note. */
6978 rtx_vector_builder builder;
6980 {
6985 }
6986 }
6990 {
6993 }
6997 {
7001 }
7007 }
7010 }
7012 /* Return the MEM rtx that provides the canary value that should be used
7013 for stack-smashing protection. MODE is the mode of the memory.
7014 For SSP_GLOBAL, DECL_RTL is the MEM rtx for the canary variable
7015 (__stack_chk_guard), otherwise it has no useful value. SALT_TYPE
7016 indicates whether the caller is performing a SET or a TEST operation. */
7018 rtx
7020 aarch64_salt_type salt_type)
7021 {
7022 rtx addr;
7024 {
7027 poly_int64 offset;
7036 }
7037 else
7038 {
7039 /* Calculate the address from the system register. */
7044 else
7045 {
7048 }
7050 }
7052 }
7054 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
7055 that is known to contain PTRUE. */
7057 void
7059 {
7067 }
7069 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
7070 operand is in memory. In this case we need to use the predicated LD1
7071 and ST1 instead of LDR and STR, both for correctness on big-endian
7072 targets and because LD1 and ST1 support a wider range of addressing modes.
7073 PRED_MODE is the mode of the predicate.
7075 See the comment at the head of aarch64-sve.md for details about the
7076 big-endian handling. */
7078 void
7080 {
7085 {
7089 else
7092 }
7094 }
7096 /* Called only on big-endian targets. See whether an SVE vector move
7097 from SRC to DEST is effectively a REV[BHW] instruction, because at
7098 least one operand is a subreg of an SVE vector that has wider or
7099 narrower elements. Return true and emit the instruction if so.
7101 For example:
7103 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
7105 represents a VIEW_CONVERT between the following vectors, viewed
7106 in memory order:
7108 R2: { [0].high, [0].low, [1].high, [1].low, ... }
7109 R1: { [0], [1], [2], [3], ... }
7111 The high part of lane X in R2 should therefore correspond to lane X*2
7112 of R1, but the register representations are:
7114 msb lsb
7115 R2: ...... [1].high [1].low [0].high [0].low
7116 R1: ...... [3] [2] [1] [0]
7118 where the low part of lane X in R2 corresponds to lane X*2 in R1.
7119 We therefore need a reverse operation to swap the high and low values
7120 around.
7122 This is purely an optimization. Without it we would spill the
7123 subreg operand to the stack in one mode and reload it in the
7124 other mode, which has the same effect as the REV. */
7126 bool
7128 {
7131 /* Do not try to optimize subregs that LRA has created for matched
7132 reloads. These subregs only exist as a temporary measure to make
7133 the RTL well-formed, but they are exempt from the usual
7134 TARGET_CAN_CHANGE_MODE_CLASS rules.
7136 For example, if we have:
7138 (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2)))
7140 and the constraints require R1 and R2 to be in the same register,
7141 LRA may need to create RTL such as:
7143 (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2))
7144 (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0)))
7145 (set (reg:VNx8HI R1) (reg:VNx8HI TMP))
7147 which forces both the input and output of the original instruction
7148 to use the same hard register. But for this to work, the normal
7149 rules have to be suppressed on the subreg input, otherwise LRA
7150 would need to reload that input too, meaning that the process
7151 would never terminate. To compensate for this, the normal rules
7152 are also suppressed for the subreg output of the first move.
7153 Ignoring the special case and handling the first move normally
7154 would therefore generate wrong code: we would reverse the elements
7155 for the first subreg but not reverse them back for the second subreg. */
7161 /* The optimization handles two single SVE REGs with different element
7162 sizes. */
7171 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
7174 UNSPEC_REV_SUBREG);
7177 }
7179 /* Return a copy of X with mode MODE, without changing its other
7180 attributes. Unlike gen_lowpart, this doesn't care whether the
7181 mode change is valid. */
7183 rtx
7185 {
7192 }
7194 /* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
7195 stored in wider integer containers. */
7197 static unsigned int
7199 {
7201 {
7205 }
7207 }
7209 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
7210 operands. */
7212 void
7214 {
7215 /* Decide which REV operation we need. The mode with wider elements
7216 determines the mode of the operands and the mode with the narrower
7217 elements determines the reverse width. */
7227 /* Get the operands in the appropriate modes and emit the instruction. */
7233 }
7235 static bool
7237 {
7242 }
7244 /* Subroutine of aarch64_pass_by_reference for arguments that are not
7245 passed in SVE registers. */
7247 static bool
7250 {
7251 HOST_WIDE_INT size;
7252 machine_mode dummymode;
7255 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
7258 else
7259 /* No frontends can create types with variable-sized modes, so we
7260 shouldn't be asked to pass or return them. */
7263 /* Aggregates are passed by reference based on their size. */
7267 /* Variable sized arguments are always returned by reference. */
7271 /* Can this be a candidate to be passed in fp/simd register(s)? */
7277 /* Arguments which are variable sized or larger than 2 registers are
7278 passed by reference unless they are a homogenous floating point
7279 aggregate. */
7281 }
7283 /* Implement TARGET_PASS_BY_REFERENCE. */
7285 static bool
7288 {
7294 pure_scalable_type_info pst_info;
7296 {
7299 /* We can't gracefully recover at this point, so make this a
7300 fatal error. */
7304 /* Variadic SVE types are passed by reference. Normal non-variadic
7305 arguments are too if we've run out of registers. */
7317 }
7319 }
7321 /* Return TRUE if VALTYPE is padded to its least significant bits. */
7322 static bool
7324 {
7325 machine_mode dummy_mode;
7328 /* Never happens in little-endian mode. */
7332 /* Only composite types smaller than or equal to 16 bytes can
7333 be potentially returned in registers. */
7339 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
7340 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
7341 is always passed/returned in the least significant bits of fp/simd
7342 register(s). */
7348 /* Likewise pure scalable types for SVE vector and predicate registers. */
7349 pure_scalable_type_info pst_info;
7354 }
7356 /* Implement TARGET_FUNCTION_VALUE.
7357 Define how to find the value returned by a function. */
7359 static rtx
7362 {
7363 machine_mode mode;
7370 pure_scalable_type_info pst_info;
7374 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7375 are returned in memory, not by value. */
7380 {
7384 {
7387 }
7388 }
7391 machine_mode ag_mode;
7394 {
7397 {
7400 }
7407 else
7408 {
7410 rtx par;
7414 {
7419 }
7421 }
7422 }
7423 else
7424 {
7426 {
7427 /* Vector types can acquire a partial SVE mode using things like
7428 __attribute__((vector_size(N))), and this is potentially useful.
7429 However, the choice of mode doesn't affect the type's ABI
7430 identity, so we should treat the types as though they had
7431 the associated integer mode, just like they did before SVE
7432 was introduced.
7434 We know that the vector must be 128 bits or smaller,
7435 otherwise we'd have returned it in memory instead. */
7444 }
7446 }
7447 }
7449 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
7450 Return true if REGNO is the number of a hard register in which the values
7451 of called function may come back. */
7453 static bool
7455 {
7456 /* Maximum of 16 bytes can be returned in the general registers. Examples
7457 of 16-byte return values are: 128-bit integers and 16-byte small
7458 structures (excluding homogeneous floating-point aggregates). */
7462 /* Up to four fp/simd registers can return a function value, e.g. a
7463 homogeneous floating-point aggregate having four members. */
7468 }
7470 /* Subroutine for aarch64_return_in_memory for types that are not returned
7471 in SVE registers. */
7473 static bool
7475 {
7476 HOST_WIDE_INT size;
7477 machine_mode ag_mode;
7483 /* Simple scalar types always returned in registers. */
7490 /* Types larger than 2 registers returned in memory. */
7493 }
7495 /* Implement TARGET_RETURN_IN_MEMORY.
7497 If the type T of the result of a function is such that
7498 void func (T arg)
7499 would require that arg be passed as a value in a register (or set of
7500 registers) according to the parameter passing rules, then the result
7501 is returned in the same registers as would be used for such an
7502 argument. */
7504 static bool
7506 {
7507 pure_scalable_type_info pst_info;
7509 {
7521 }
7523 }
7525 static bool
7528 {
7533 }
7535 /* Given MODE and TYPE of a function argument, return the alignment in
7536 bits. The idea is to suppress any stronger alignment requested by
7537 the user and opt for the natural alignment (specified in AAPCS64 \S
7538 4.1). ABI_BREAK is set to true if the alignment was incorrectly
7539 calculated in versions of GCC prior to GCC-9. This is a helper
7540 function for local use only. */
7542 static unsigned int
7545 {
7565 {
7566 /* Note that we explicitly consider zero-sized fields here,
7567 even though they don't map to AAPCS64 machine types.
7568 For example, in:
7570 struct __attribute__((aligned(8))) empty {};
7572 struct s {
7573 [[no_unique_address]] empty e;
7574 int x;
7575 };
7577 "s" contains only one Fundamental Data Type (the int field)
7578 but gains 8-byte alignment and size thanks to "e". */
7581 bitfield_alignment
7584 }
7587 {
7590 }
7593 }
7595 /* Layout a function argument according to the AAPCS64 rules. The rule
7596 numbers refer to the rule numbers in the AAPCS64. ORIG_MODE is the
7597 mode that was originally given to us by the target hook, whereas the
7598 mode in ARG might be the result of replacing partial SVE modes with
7599 the equivalent integer mode. */
7601 static void
7603 {
7609 HOST_WIDE_INT size;
7612 /* We need to do this once per argument. */
7618 pure_scalable_type_info pst_info;
7620 {
7621 /* The PCS says that it is invalid to pass an SVE value to an
7622 unprototyped function. There is no ABI-defined location we
7623 can return in this case, so we have no real choice but to raise
7624 an error immediately, even though this is only a query function. */
7626 {
7630 /* Avoid repeating the message, and avoid tripping the assert
7631 below. */
7633 }
7635 /* We would have converted the argument into pass-by-reference
7636 form if it didn't fit in registers. */
7646 }
7648 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7649 are passed by reference, not by value. */
7653 /* Vector types can acquire a partial SVE mode using things like
7654 __attribute__((vector_size(N))), and this is potentially useful.
7655 However, the choice of mode doesn't affect the type's ABI
7656 identity, so we should treat the types as though they had
7657 the associated integer mode, just like they did before SVE
7658 was introduced.
7660 We know that the vector must be 128 bits or smaller,
7661 otherwise we'd have passed it in memory instead. */
7666 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
7669 else
7670 /* No frontends can create types with variable-sized modes, so we
7671 shouldn't be asked to pass or return them. */
7677 mode,
7678 type,
7682 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
7683 The following code thus handles passing by SIMD/FP registers first. */
7687 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
7688 and homogenous short-vector aggregates (HVA). */
7690 {
7695 {
7698 {
7701 }
7708 else
7709 {
7710 rtx par;
7714 {
7717 rtx offset = gen_int_mode
7721 }
7723 }
7725 }
7726 else
7727 {
7728 /* C.3 NSRN is set to 8. */
7731 }
7732 }
7737 /* C6 - C9. though the sign and zero extension semantics are
7738 handled elsewhere. This is the case where the argument fits
7739 entirely general registers. */
7741 {
7744 /* C.8 if the argument has an alignment of 16 then the NGRN is
7745 rounded up to the next even number. */
7748 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
7749 comparison is there because for > 16 * BITS_PER_UNIT
7750 alignment nregs should be > 2 and therefore it should be
7751 passed by reference rather than value. */
7754 {
7760 }
7762 /* If an argument with an SVE mode needs to be shifted up to the
7763 high part of the register, treat it as though it had an integer mode.
7764 Using the normal (parallel [...]) would suppress the shifting. */
7766 && BYTES_BIG_ENDIAN
7769 {
7772 }
7774 /* NREGS can be 0 when e.g. an empty structure is to be passed.
7775 A reg is still generated for it, but the caller should be smart
7776 enough not to use it. */
7781 else
7782 {
7783 rtx par;
7788 {
7796 }
7798 }
7802 }
7804 /* C.11 */
7807 /* The argument is passed on stack; record the needed number of words for
7808 this argument and align the total size if necessary. */
7809 on_stack:
7814 {
7817 {
7822 }
7823 }
7825 }
7827 /* Implement TARGET_FUNCTION_ARG. */
7829 static rtx
7831 {
7842 }
7844 void
7846 const_tree fntype,
7847 rtx libname ATTRIBUTE_UNUSED,
7848 const_tree fndecl ATTRIBUTE_UNUSED,
7851 {
7860 else
7869 && !TARGET_FLOAT
7871 {
7878 }
7881 && !TARGET_SVE
7883 {
7884 /* We can't gracefully recover at this point, so make this a
7885 fatal error. */
7888 fndecl);
7889 else
7892 }
7893 }
7895 static void
7898 {
7903 {
7914 }
7915 }
7917 bool
7919 {
7922 }
7924 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
7925 PARM_BOUNDARY bits of alignment, but will be given anything up
7926 to STACK_BOUNDARY bits if the type requires it. This makes sure
7927 that both before and after the layout of each argument, the Next
7928 Stacked Argument Address (NSAA) will have a minimum alignment of
7929 8 bytes. */
7931 static unsigned int
7933 {
7939 {
7944 }
7947 }
7949 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
7951 static fixed_size_mode
7953 {
7955 /* Don't use the SVE part of the register for __builtin_apply and
7956 __builtin_return. The SVE registers aren't used by the normal PCS,
7957 so using them there would be a waste of time. The PCS extensions
7958 for SVE types are fundamentally incompatible with the
7959 __builtin_return/__builtin_apply interface. */
7962 }
7964 /* Implement TARGET_FUNCTION_ARG_PADDING.
7966 Small aggregate types are placed in the lowest memory address.
7968 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
7970 static pad_direction
7972 {
7973 /* On little-endian targets, the least significant byte of every stack
7974 argument is passed at the lowest byte address of the stack slot. */
7978 /* Otherwise, integral, floating-point and pointer types are padded downward:
7979 the least significant byte of a stack argument is passed at the highest
7980 byte address of the stack slot. */
7987 /* Everything else padded upward, i.e. data in first byte of stack slot. */
7989 }
7991 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7993 It specifies padding for the last (may also be the only)
7994 element of a block move between registers and memory. If
7995 assuming the block is in the memory, padding upward means that
7996 the last element is padded after its highest significant byte,
7997 while in downward padding, the last element is padded at the
7998 its least significant byte side.
8000 Small aggregates and small complex types are always padded
8001 upwards.
8003 We don't need to worry about homogeneous floating-point or
8004 short-vector aggregates; their move is not affected by the
8005 padding direction determined here. Regardless of endianness,
8006 each element of such an aggregate is put in the least
8007 significant bits of a fp/simd register.
8009 Return !BYTES_BIG_ENDIAN if the least significant byte of the
8010 register has useful data, and return the opposite if the most
8011 significant byte does. */
8013 bool
8016 {
8018 /* Aside from pure scalable types, small composite types are always
8019 padded upward. */
8021 {
8022 HOST_WIDE_INT size;
8025 else
8026 /* No frontends can create types with variable-sized modes, so we
8027 shouldn't be asked to pass or return them. */
8030 {
8031 pure_scalable_type_info pst_info;
8035 }
8036 }
8038 /* Otherwise, use the default padding. */
8040 }
8042 static scalar_int_mode
8044 {
8046 }
8048 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
8050 /* We use the 12-bit shifted immediate arithmetic instructions so values
8051 must be multiple of (1 << 12), i.e. 4096. */
8052 #define ARITH_FACTOR 4096
8054 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
8055 #error Cannot use simple address calculation for stack probing
8056 #endif
8058 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
8059 inclusive. These are offsets from the current stack pointer. */
8061 static void
8063 {
8064 HOST_WIDE_INT size;
8066 {
8069 }
8073 /* See the same assertion on PROBE_INTERVAL above. */
8076 /* See if we have a constant small number of probes to generate. If so,
8077 that's the easy case. */
8079 {
8086 }
8088 /* The run-time loop is made up of 8 insns in the generic case while the
8089 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
8091 {
8096 stack_pointer_rtx,
8100 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
8101 it exceeds SIZE. If only two probes are needed, this will not
8102 generate any code. Then probe at FIRST + SIZE. */
8104 {
8108 }
8112 {
8117 }
8118 else
8120 }
8122 /* Otherwise, do the same as above, but in a loop. Note that we must be
8123 extra careful with variables wrapping around because we might be at
8124 the very top (or the very bottom) of the address space and we have
8125 to be able to handle this case properly; in particular, we use an
8126 equality test for the loop condition. */
8127 else
8128 {
8131 /* Step 1: round SIZE to the previous multiple of the interval. */
8136 /* Step 2: compute initial and final value of the loop counter. */
8138 /* TEST_ADDR = SP + FIRST. */
8142 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
8145 {
8149 }
8150 else
8154 /* Step 3: the loop
8156 do
8157 {
8158 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
8159 probe at TEST_ADDR
8160 }
8161 while (TEST_ADDR != LAST_ADDR)
8163 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
8164 until it is equal to ROUNDED_SIZE. */
8169 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
8170 that SIZE is equal to ROUNDED_SIZE. */
8173 {
8177 {
8182 }
8183 else
8185 }
8186 }
8188 /* Make sure nothing is scheduled before we are done. */
8190 }
8192 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
8193 absolute addresses. */
8197 {
8204 /* Loop. */
8207 HOST_WIDE_INT stack_clash_probe_interval
8210 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
8212 HOST_WIDE_INT interval;
8215 else
8223 /* If doing stack clash protection then we probe up by the ABI specified
8224 amount. We do this because we're dropping full pages at a time in the
8225 loop. But if we're doing non-stack clash probing, probe at SP 0. */
8228 else
8231 /* Probe at TEST_ADDR. If we're inside the loop it is always safe to probe
8232 by this amount for each iteration. */
8235 /* Test if TEST_ADDR == LAST_ADDR. */
8239 /* Branch. */
8245 }
8247 /* Emit the probe loop for doing stack clash probes and stack adjustments for
8248 SVE. This emits probes from BASE to BASE - ADJUSTMENT based on a guard size
8249 of GUARD_SIZE. When a probe is emitted it is done at most
8250 MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of
8251 at most MIN_PROBE_THRESHOLD. By the end of this function
8252 BASE = BASE - ADJUSTMENT. */
8257 {
8258 /* This function is not allowed to use any instruction generation function
8259 like gen_ and friends. If you do you'll likely ICE during CFG validation,
8260 so instead emit the code you want using output_asm_insn. */
8265 /* The minimum required allocation before the residual requires probing. */
8268 /* Clamp the value down to the nearest value that can be used with a cmp. */
8283 /* Emit loop start label. */
8286 /* ADJUSTMENT < RESIDUAL_PROBE_GUARD. */
8291 /* Branch to end if not enough adjustment to probe. */
8296 /* BASE = BASE - RESIDUAL_PROBE_GUARD. */
8301 /* Probe at BASE. */
8305 /* ADJUSTMENT = ADJUSTMENT - RESIDUAL_PROBE_GUARD. */
8310 /* Branch to start if still more bytes to allocate. */
8315 /* No probe leave. */
8318 /* BASE = BASE - ADJUSTMENT. */
8323 }
8325 /* Determine whether a frame chain needs to be generated. */
8326 static bool
8328 {
8329 /* Force a frame chain for EH returns so the return address is at FP+8. */
8333 /* A leaf function cannot have calls or write LR. */
8336 /* Don't use a frame chain in leaf functions if leaf frame pointers
8337 are disabled. */
8342 }
8344 /* Mark the registers that need to be saved by the callee and calculate
8345 the size of the callee-saved registers area and frame record (both FP
8346 and LR may be omitted). */
8347 static void
8349 {
8359 /* Adjust the outgoing arguments size if required. Keep it in sync with what
8360 the mid-end is doing. */
8363 #define SLOT_NOT_REQUIRED (-2)
8364 #define SLOT_REQUIRED (-1)
8370 /* First mark all the registers that really need to be saved... */
8374 /* ... that includes the eh data registers (if needed)... */
8379 /* ... and any callee saved register that dataflow says is live. */
8391 {
8396 }
8398 /* Big-endian SVE frames need a spare predicate register in order
8399 to save Z8-Z15. Decide which register they should use. Prefer
8400 an unused argument register if possible, so that we don't force P4
8401 to be saved unnecessarily. */
8405 {
8414 }
8422 /* With stack-clash, LR must be saved in non-leaf functions. The saving of
8423 LR counts as an implicit probe which allows us to maintain the invariant
8424 described in the comment at expand_prologue. */
8428 /* Now assign stack slots for the registers. Start with the predicate
8429 registers, since predicate LDR and STR have a relatively small
8430 offset range. These saves happen below the hard frame pointer. */
8433 {
8436 }
8439 {
8440 /* If we have any vector registers to save above the predicate registers,
8441 the offset of the vector register save slots need to be a multiple
8442 of the vector size. This lets us use the immediate forms of LDR/STR
8443 (or LD1/ST1 for big-endian).
8445 A vector register is 8 times the size of a predicate register,
8446 and we need to save a maximum of 12 predicate registers, so the
8447 first vector register will be at either #1, MUL VL or #2, MUL VL.
8449 If we don't have any vector registers to save, and we know how
8450 big the predicate save area is, we can just round it up to the
8451 next 16-byte boundary. */
8454 else
8455 {
8460 else
8462 }
8463 }
8465 /* If we need to save any SVE vector registers, add them next. */
8469 {
8472 }
8474 /* OFFSET is now the offset of the hard frame pointer from the bottom
8475 of the callee save area. */
8479 {
8480 /* FP and LR are placed in the linkage record. */
8486 }
8490 {
8497 }
8505 {
8506 /* If there is an alignment gap between integer and fp callee-saves,
8507 allocate the last fp register to it if possible. */
8509 && has_align_gap
8512 {
8515 }
8524 }
8532 poly_int64 above_outgoing_args
8537 frame.hard_fp_offset
8540 /* Both these values are already aligned. */
8556 /* Shadow call stack only deals with functions where the LR is pushed
8557 onto the stack and without specifying the "no_sanitize" attribute
8558 with the argument "shadow-call-stack". */
8559 frame.is_scs_enabled
8564 /* When shadow call stack is enabled, the scs_pop in the epilogue will
8565 restore x30, and we don't need to pop x30 again in the traditional
8566 way. Pop candidates record the registers that need to be popped
8567 eventually. */
8569 {
8574 }
8576 /* If candidate2 is INVALID_REGNUM, we need to adjust max_push_offset to
8577 256 to ensure that the offset meets the requirements of emit_move_insn.
8578 Similarly, if candidate1 is INVALID_REGNUM, we need to set
8579 max_push_offset to 0, because no registers are popped at this time,
8580 so callee_adjust cannot be adjusted. */
8588 HOST_WIDE_INT const_saved_regs_size;
8592 {
8593 /* Simple, small frame with no outgoing arguments:
8595 stp reg1, reg2, [sp, -frame_size]!
8596 stp reg3, reg4, [sp, 16] */
8598 }
8602 /* We could handle this case even with outgoing args, provided
8603 that the number of args left us with valid offsets for all
8604 predicate and vector save slots. It's such a rare case that
8605 it hardly seems worth the effort though. */
8610 {
8611 /* Frame with small outgoing arguments:
8613 sub sp, sp, frame_size
8614 stp reg1, reg2, [sp, outgoing_args_size]
8615 stp reg3, reg4, [sp, outgoing_args_size + 16] */
8618 }
8622 {
8623 /* Frame in which all saves are SVE saves:
8625 sub sp, sp, hard_fp_offset + below_hard_fp_saved_regs_size
8626 save SVE registers relative to SP
8627 sub sp, sp, outgoing_args_size */
8631 }
8634 {
8635 /* Frame with large outgoing arguments or SVE saves, but with
8636 a small local area:
8638 stp reg1, reg2, [sp, -hard_fp_offset]!
8639 stp reg3, reg4, [sp, 16]
8640 [sub sp, sp, below_hard_fp_saved_regs_size]
8641 [save SVE registers relative to SP]
8642 sub sp, sp, outgoing_args_size */
8646 }
8647 else
8648 {
8649 /* Frame with large local area and outgoing arguments or SVE saves,
8650 using frame pointer:
8652 sub sp, sp, hard_fp_offset
8653 stp x29, x30, [sp, 0]
8654 add x29, sp, 0
8655 stp reg3, reg4, [sp, 16]
8656 [sub sp, sp, below_hard_fp_saved_regs_size]
8657 [save SVE registers relative to SP]
8658 sub sp, sp, outgoing_args_size */
8662 }
8664 /* Make sure the individual adjustments add up to the full frame size. */
8671 {
8672 /* We've decided not to associate any register saves with the initial
8673 stack allocation. */
8676 }
8679 }
8681 /* Return true if the register REGNO is saved on entry to
8682 the current function. */
8684 static bool
8686 {
8688 }
8690 /* Return the next register up from REGNO up to LIMIT for the callee
8691 to save. */
8693 static unsigned
8695 {
8697 regno ++;
8699 }
8701 /* Push the register number REGNO of mode MODE to the stack with write-back
8702 adjusting the stack by ADJUSTMENT. */
8704 static void
8706 HOST_WIDE_INT adjustment)
8707 {
8718 }
8720 /* Generate and return an instruction to store the pair of registers
8721 REG and REG2 of mode MODE to location BASE with write-back adjusting
8722 the stack location BASE by ADJUSTMENT. */
8724 static rtx
8726 HOST_WIDE_INT adjustment)
8727 {
8729 {
8744 }
8745 }
8747 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
8748 stack pointer by ADJUSTMENT. */
8750 static void
8752 {
8767 }
8769 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
8770 adjusting it by ADJUSTMENT afterwards. */
8772 static rtx
8774 HOST_WIDE_INT adjustment)
8775 {
8777 {
8789 }
8790 }
8792 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
8793 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
8794 into CFI_OPS. */
8796 static void
8799 {
8806 {
8810 }
8811 else
8812 {
8817 }
8818 }
8820 /* Generate and return a store pair instruction of mode MODE to store
8821 register REG1 to MEM1 and register REG2 to MEM2. */
8823 static rtx
8825 rtx reg2)
8826 {
8828 {
8846 }
8847 }
8849 /* Generate and regurn a load pair isntruction of mode MODE to load register
8850 REG1 from MEM1 and register REG2 from MEM2. */
8852 static rtx
8854 rtx mem2)
8855 {
8857 {
8872 }
8873 }
8875 /* Return TRUE if return address signing should be enabled for the current
8876 function, otherwise return FALSE. */
8878 bool
8880 {
8881 /* This function should only be called after frame laid out. */
8884 /* Turn return address signing off in any function that uses
8885 __builtin_eh_return. The address passed to __builtin_eh_return
8886 is not signed so either it has to be signed (with original sp)
8887 or the code path that uses it has to avoid authenticating it.
8888 Currently eh return introduces a return to anywhere gadget, no
8889 matter what we do here since it uses ret with user provided
8890 address. An ideal fix for that is to use indirect branch which
8891 can be protected with BTI j (to some extent). */
8895 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
8896 if its LR is pushed onto stack. */
8900 }
8902 /* Return TRUE if Branch Target Identification Mechanism is enabled. */
8903 bool
8905 {
8907 }
8909 /* The caller is going to use ST1D or LD1D to save or restore an SVE
8910 register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
8911 the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
8913 (1) updating BASE_RTX + OFFSET so that it is a legitimate ST1D
8914 or LD1D address
8916 (2) setting PRED to a valid predicate register for the ST1D or LD1D,
8917 if the variable isn't already nonnull
8919 (1) is needed when OFFSET is in the range [8, 16] * GET_MODE_SIZE (MODE).
8920 Handle this case using a temporary base register that is suitable for
8921 all offsets in that range. Use ANCHOR_REG as this base register if it
8922 is nonnull, otherwise create a new register and store it in ANCHOR_REG. */
8928 {
8930 {
8931 /* This is the maximum valid offset of the anchor from the base.
8932 Lower values would be valid too. */
8935 {
8939 }
8942 }
8944 {
8949 }
8950 }
8952 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
8953 is saved at BASE + OFFSET. */
8955 static void
8958 {
8962 }
8964 /* Emit code to save the callee-saved registers from register number START
8965 to LIMIT to the stack at the location starting at offset START_OFFSET,
8966 skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P
8967 is true if the hard frame pointer has been set up. */
8969 static void
8973 {
8982 {
8984 poly_int64 offset;
9001 HOST_WIDE_INT const_offset;
9007 {
9009 poly_int64 fp_offset
9013 else
9014 {
9016 {
9020 }
9022 }
9024 }
9034 {
9036 rtx mem2;
9041 reg2));
9043 /* The first part of a frame-related parallel insn is
9044 always assumed to be relevant to the frame
9045 calculations; subsequent parts, are only
9046 frame-related if explicitly marked. */
9048 {
9052 else
9054 }
9057 }
9059 {
9062 }
9065 else
9071 }
9072 }
9074 /* Emit code to restore the callee registers from register number START
9075 up to and including LIMIT. Restore from the stack offset START_OFFSET,
9076 skipping any write-back candidates if SKIP_WB is true. Write the
9077 appropriate REG_CFA_RESTORE notes into CFI_OPS. */
9079 static void
9082 {
9085 poly_int64 offset;
9091 {
9118 {
9120 rtx mem2;
9128 }
9133 else
9137 }
9138 }
9140 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
9141 of MODE. */
9145 {
9146 HOST_WIDE_INT multiple;
9149 }
9151 /* Return true if OFFSET is a signed 6-bit value multiplied by the size
9152 of MODE. */
9156 {
9157 HOST_WIDE_INT multiple;
9160 }
9162 /* Return true if OFFSET is an unsigned 6-bit value multiplied by the size
9163 of MODE. */
9167 {
9168 HOST_WIDE_INT multiple;
9171 }
9173 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
9174 of MODE. */
9176 bool
9178 {
9179 HOST_WIDE_INT multiple;
9182 }
9184 /* Return true if OFFSET is a signed 9-bit value. */
9186 bool
9188 poly_int64 offset)
9189 {
9190 HOST_WIDE_INT const_offset;
9193 }
9195 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
9196 of MODE. */
9200 {
9201 HOST_WIDE_INT multiple;
9204 }
9206 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
9207 of MODE. */
9211 {
9212 HOST_WIDE_INT multiple;
9215 }
9217 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
9219 static sbitmap
9221 {
9225 /* The registers we need saved to the frame. */
9228 {
9229 /* Punt on saves and restores that use ST1D and LD1D. We could
9230 try to be smarter, but it would involve making sure that the
9231 spare predicate register itself is safe to use at the save
9232 and restore points. Also, when a frame pointer is being used,
9233 the slots are often out of reach of ST1D and LD1D anyway. */
9240 /* If the register is saved in the first SVE save slot, we use
9241 it as a stack probe for -fstack-clash-protection. */
9247 /* Get the offset relative to the register we'll use. */
9250 else
9253 /* Check that we can access the stack slot of the register with one
9254 direct load with no adjustments needed. */
9259 }
9261 /* Don't mess with the hard frame pointer. */
9265 /* If the spare predicate register used by big-endian SVE code
9266 is call-preserved, it must be saved in the main prologue
9267 before any saves that use it. */
9273 /* If registers have been chosen to be stored/restored with
9274 writeback don't interfere with them to avoid having to output explicit
9275 stack adjustment instructions. */
9285 }
9287 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
9289 static sbitmap
9291 {
9299 /* Clobbered registers don't generate values in any meaningful sense,
9300 since nothing after the clobber can rely on their value. And we can't
9301 say that partially-clobbered registers are unconditionally killed,
9302 because whether they're killed or not depends on the mode of the
9303 value they're holding. Thus partially call-clobbered registers
9304 appear in neither the kill set nor the gen set.
9306 Check manually for any calls that clobber more of a register than the
9307 current function can. */
9308 function_abi_aggregator callee_abis;
9315 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
9323 {
9326 /* If there is a callee-save at an adjacent offset, add it too
9327 to increase the use of LDP/STP. */
9332 {
9338 }
9339 }
9342 }
9344 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
9345 Nothing to do for aarch64. */
9347 static void
9349 {
9350 }
9352 /* Return the next set bit in BMP from START onwards. Return the total number
9353 of bits in BMP if no set bit is found at or after START. */
9355 static unsigned int
9357 {
9368 }
9370 /* Do the work for aarch64_emit_prologue_components and
9371 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
9372 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
9373 for these components or the epilogue sequence. That is, it determines
9374 whether we should emit stores or loads and what kind of CFA notes to attach
9375 to the insns. Otherwise the logic for the two sequences is very
9376 similar. */
9378 static void
9380 {
9382 ? HARD_FRAME_POINTER_REGNUM
9390 {
9398 else
9406 /* No more registers to handle after REGNO.
9407 Emit a single save/restore and exit. */
9409 {
9412 {
9416 else
9418 }
9420 }
9423 /* The next register is not of the same class or its offset is not
9424 mergeable with the current one into a pair. */
9431 {
9434 {
9438 else
9440 }
9444 }
9448 /* REGNO2 can be saved/restored in a pair with REGNO. */
9452 else
9461 else
9465 {
9468 {
9473 }
9474 else
9475 {
9480 }
9481 }
9484 }
9485 }
9487 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
9489 static void
9491 {
9493 }
9495 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
9497 static void
9499 {
9501 }
9503 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
9505 static void
9507 {
9511 }
9513 /* On AArch64 we have an ABI defined safe buffer. This constant is used to
9514 determining the probe offset for alloca. */
9516 static HOST_WIDE_INT
9518 {
9520 }
9523 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
9524 registers. If POLY_SIZE is not large enough to require a probe this function
9525 will only adjust the stack. When allocating the stack space
9526 FRAME_RELATED_P is then used to indicate if the allocation is frame related.
9527 FINAL_ADJUSTMENT_P indicates whether we are allocating the outgoing
9528 arguments. If we are then we ensure that any allocation larger than the ABI
9529 defined buffer needs a probe so that the invariant of having a 1KB buffer is
9530 maintained.
9532 We emit barriers after each stack adjustment to prevent optimizations from
9533 breaking the invariant that we never drop the stack more than a page. This
9534 invariant is needed to make it easier to correctly handle asynchronous
9535 events, e.g. if we were to allow the stack to be dropped by more than a page
9536 and then have multiple probes up and we take a signal somewhere in between
9537 then the signal handler doesn't know the state of the stack and can make no
9538 assumptions about which pages have been probed. */
9540 static void
9542 poly_int64 poly_size,
9545 {
9546 HOST_WIDE_INT guard_size
9549 HOST_WIDE_INT min_probe_threshold
9550 = (final_adjustment_p
9551 ? guard_used_by_caller
9553 /* When doing the final adjustment for the outgoing arguments, take into
9554 account any unprobed space there is above the current SP. There are
9555 two cases:
9557 - When saving SVE registers below the hard frame pointer, we force
9558 the lowest save to take place in the prologue before doing the final
9559 adjustment (i.e. we don't allow the save to be shrink-wrapped).
9560 This acts as a probe at SP, so there is no unprobed space.
9562 - When there are no SVE register saves, we use the store of the link
9563 register as a probe. We can't assume that LR was saved at position 0
9564 though, so treat any space below it as unprobed. */
9567 {
9571 else
9573 }
9577 /* We should always have a positive probe threshold. */
9581 {
9587 {
9589 }
9593 {
9595 }
9596 }
9598 /* If SIZE is not large enough to require probing, just adjust the stack and
9599 exit. */
9602 {
9605 }
9607 HOST_WIDE_INT size;
9608 /* Handle the SVE non-constant case first. */
9610 {
9612 {
9616 }
9618 /* First calculate the amount of bytes we're actually spilling. */
9625 {
9626 /* This is done to provide unwinding information for the stack
9627 adjustments we're about to do, however to prevent the optimizers
9628 from removing the R11 move and leaving the CFA note (which would be
9629 very wrong) we tie the old and new stack pointer together.
9630 The tie will expand to nothing but the optimizers will not touch
9631 the instruction. */
9636 /* We want the CFA independent of the stack pointer for the
9637 duration of the loop. */
9640 }
9649 /* Now reset the CFA register if needed. */
9651 {
9656 }
9659 }
9663 "Stack clash AArch64 prologue: " HOST_WIDE_INT_PRINT_DEC
9666 /* Round size to the nearest multiple of guard_size, and calculate the
9667 residual as the difference between the original size and the rounded
9668 size. */
9672 /* We can handle a small number of allocations/probes inline. Otherwise
9673 punt to a loop. */
9675 {
9677 {
9680 guard_used_by_caller));
9682 }
9684 }
9685 else
9686 {
9687 /* Compute the ending address. */
9692 /* For the initial allocation, we don't have a frame pointer
9693 set up, so we always need CFI notes. If we're doing the
9694 final allocation, then we may have a frame pointer, in which
9695 case it is the CFA, otherwise we need CFI notes.
9697 We can determine which allocation we are doing by looking at
9698 the value of FRAME_RELATED_P since the final allocations are not
9699 frame related. */
9701 {
9702 /* We want the CFA independent of the stack pointer for the
9703 duration of the loop. */
9707 }
9709 /* This allocates and probes the stack. Note that this re-uses some of
9710 the existing Ada stack protection code. However we are guaranteed not
9711 to enter the non loop or residual branches of that code.
9713 The non-loop part won't be entered because if our allocation amount
9714 doesn't require a loop, the case above would handle it.
9716 The residual amount won't be entered because TEMP1 is a mutliple of
9717 the allocation size. The residual will always be 0. As such, the only
9718 part we are actually using from that code is the loop setup. The
9719 actual probing is done in aarch64_output_probe_stack_range. */
9723 /* Now reset the CFA register if needed. */
9725 {
9729 }
9733 }
9735 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
9736 be probed. This maintains the requirement that each page is probed at
9737 least once. For initial probing we probe only if the allocation is
9738 more than GUARD_SIZE - buffer, and for the outgoing arguments we probe
9739 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
9740 GUARD_SIZE. This works that for any allocation that is large enough to
9741 trigger a probe here, we'll have at least one, and if they're not large
9742 enough for this code to emit anything for them, The page would have been
9743 probed by the saving of FP/LR either by this function or any callees. If
9744 we don't have any callees then we won't have more stack adjustments and so
9745 are still safe. */
9747 {
9749 /* If we're doing final adjustments, and we've done any full page
9750 allocations then any residual needs to be probed. */
9753 /* If doing a small final adjustment, we always probe at offset 0.
9754 This is done to avoid issues when LR is not at position 0 or when
9755 the final adjustment is smaller than the probing offset. */
9761 {
9764 "Stack clash AArch64 prologue residuals: "
9765 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
9769 residual_probe_offset));
9771 }
9772 }
9773 }
9775 /* Return 1 if the register is used by the epilogue. We need to say the
9776 return register is used, but only after epilogue generation is complete.
9777 Note that in the case of sibcalls, the values "used by the epilogue" are
9778 considered live at the start of the called function.
9780 For SIMD functions we need to return 1 for FP registers that are saved and
9781 restored by a function but are not zero in call_used_regs. If we do not do
9782 this optimizations may remove the restore of the register. */
9784 int
9786 {
9788 {
9791 }
9793 }
9795 /* AArch64 stack frames generated by this compiler look like:
9797 +-------------------------------+
9798 | |
9799 | incoming stack arguments |
9800 | |
9801 +-------------------------------+
9802 | | <-- incoming stack pointer (aligned)
9803 | callee-allocated save area |
9804 | for register varargs |
9805 | |
9806 +-------------------------------+
9807 | local variables | <-- frame_pointer_rtx
9808 | |
9809 +-------------------------------+
9810 | padding | \
9811 +-------------------------------+ |
9812 | callee-saved registers | | frame.saved_regs_size
9813 +-------------------------------+ |
9814 | LR' | |
9815 +-------------------------------+ |
9816 | FP' | |
9817 +-------------------------------+ |<- hard_frame_pointer_rtx (aligned)
9818 | SVE vector registers | | \
9819 +-------------------------------+ | | below_hard_fp_saved_regs_size
9820 | SVE predicate registers | / /
9821 +-------------------------------+
9822 | dynamic allocation |
9823 +-------------------------------+
9824 | padding |
9825 +-------------------------------+
9826 | outgoing stack arguments | <-- arg_pointer
9827 | |
9828 +-------------------------------+
9829 | | <-- stack_pointer_rtx (aligned)
9831 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
9832 but leave frame_pointer_rtx and hard_frame_pointer_rtx
9833 unchanged.
9835 By default for stack-clash we assume the guard is at least 64KB, but this
9836 value is configurable to either 4KB or 64KB. We also force the guard size to
9837 be the same as the probing interval and both values are kept in sync.
9839 With those assumptions the callee can allocate up to 63KB (or 3KB depending
9840 on the guard size) of stack space without probing.
9842 When probing is needed, we emit a probe at the start of the prologue
9843 and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter.
9845 We have to track how much space has been allocated and the only stores
9846 to the stack we track as implicit probes are the FP/LR stores.
9848 For outgoing arguments we probe if the size is larger than 1KB, such that
9849 the ABI specified buffer is maintained for the next callee.
9851 The following registers are reserved during frame layout and should not be
9852 used for any other purpose:
9854 - r11: Used by stack clash protection when SVE is enabled, and also
9855 as an anchor register when saving and restoring registers
9856 - r12(EP0) and r13(EP1): Used as temporaries for stack adjustment.
9857 - r14 and r15: Used for speculation tracking.
9858 - r16(IP0), r17(IP1): Used by indirect tailcalls.
9859 - r30(LR), r29(FP): Used by standard frame layout.
9861 These registers must be avoided in frame layout related code unless the
9862 explicit intention is to interact with one of the features listed above. */
9864 /* Generate the prologue instructions for entry into a function.
9865 Establish the stack frame by decreasing the stack pointer with a
9866 properly calculated size and, if necessary, create a frame record
9867 filled with the values of LR and previous frame pointer. The
9868 current FP is also set up if it is in use. */
9870 void
9872 {
9879 poly_int64 below_hard_fp_saved_regs_size
9887 {
9888 /* Fold the SVE allocation into the initial allocation.
9889 We don't do this in aarch64_layout_arg to avoid pessimizing
9890 the epilogue code. */
9893 }
9895 /* Sign return address for functions. */
9897 {
9899 {
9908 }
9911 }
9913 /* Push return address to shadow call stack. */
9921 {
9923 {
9927 (frame_size
9929 }
9932 }
9937 /* In theory we should never have both an initial adjustment
9938 and a callee save adjustment. Verify that is the case since the
9939 code below does not handle it for -fstack-clash-protection. */
9942 /* Will only probe if the initial adjustment is larger than the guard
9943 less the amount of the guard reserved for use by the caller's
9944 outgoing args. */
9951 /* The offset of the frame chain record (if any) from the current SP. */
9956 /* The offset of the bottom of the save area from the current SP. */
9960 {
9962 {
9967 }
9968 else
9974 {
9975 /* Variable-sized frames need to describe the save slot
9976 address using DW_CFA_expression rather than DW_CFA_offset.
9977 This means that, without taking further action, the
9978 locations of the registers that we've already saved would
9979 remain based on the stack pointer even after we redefine
9980 the CFA based on the frame pointer. We therefore need new
9981 DW_CFA_expressions to re-express the save slots with addresses
9982 based on the frame pointer. */
9986 /* Add an explicit CFA definition if this was previously
9987 implicit. */
9989 {
9991 callee_offset);
9994 }
9996 /* Change the save slot expressions for the registers that
9997 we've already saved. */
10002 }
10004 }
10008 emit_frame_chain);
10010 {
10014 sve_callee_adjust,
10017 }
10022 emit_frame_chain);
10024 /* We may need to probe the final adjustment if it is larger than the guard
10025 that is assumed by the called. */
10028 }
10030 /* Return TRUE if we can use a simple_return insn.
10032 This function checks whether the callee saved stack is empty, which
10033 means no restore actions are need. The pro_and_epilogue will use
10034 this to check whether shrink-wrapping opt is feasible. */
10036 bool
10038 {
10046 }
10048 /* Generate the epilogue instructions for returning from a function.
10049 This is almost exactly the reverse of the prolog sequence, except
10050 that we need to insert barriers to avoid scheduling loads that read
10051 from a deallocated stack, and we optimize the unwind records by
10052 emitting them all together if possible. */
10053 void
10055 {
10061 poly_int64 below_hard_fp_saved_regs_size
10069 /* A stack clash protection prologue may not have left EP0_REGNUM or
10070 EP1_REGNUM in a usable state. The same is true for allocations
10071 with an SVE component, since we then need both temporary registers
10072 for each allocation. For stack clash we are in a usable state if
10073 the adjustment is less than GUARD_SIZE - GUARD_USED_BY_CALLER. */
10074 HOST_WIDE_INT guard_size
10078 /* We can re-use the registers when:
10080 (a) the deallocation amount is the same as the corresponding
10081 allocation amount (which is false if we combine the initial
10082 and SVE callee save allocations in the prologue); and
10084 (b) the allocation amount doesn't need a probe (which is false
10085 if the amount is guard_size - guard_used_by_caller or greater).
10087 In such situations the register should remain live with the correct
10088 value. */
10091 && (!flag_stack_clash_protection
10096 /* We need to add memory barrier to prevent read from deallocated stack. */
10097 bool need_barrier_p
10101 /* Emit a barrier to prevent loads from a deallocated stack. */
10105 {
10108 }
10110 /* Restore the stack pointer from the frame pointer if it may not
10111 be the same as the stack pointer. */
10116 /* If writeback is used when restoring callee-saves, the CFA
10117 is restored on the instruction doing the writeback. */
10119 hard_frame_pointer_rtx,
10122 else
10123 /* The case where we need to re-use the register here is very rare, so
10124 avoid the complicated condition and just always emit a move if the
10125 immediate doesn't fit. */
10128 /* Restore the vector registers before the predicate registers,
10129 so that we can use P4 as a temporary for big-endian SVE frames. */
10137 /* When shadow call stack is enabled, the scs_pop in the epilogue will
10138 restore x30, we don't need to restore x30 again in the traditional
10139 way. */
10150 /* If we have no register restore information, the CFA must have been
10151 defined in terms of the stack pointer since the end of the prologue. */
10155 {
10156 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
10162 }
10164 /* Liveness of EP0_REGNUM can not be trusted across function calls either, so
10165 add restriction on emit_move optimization to leaf functions. */
10171 {
10172 /* Emit delayed restores and reset the CFA to be SP. */
10177 }
10179 /* Pop return address from shadow call stack. */
10181 {
10188 }
10190 /* We prefer to emit the combined return/authenticate instruction RETAA,
10191 however there are three cases in which we must instead emit an explicit
10192 authentication instruction.
10194 1) Sibcalls don't return in a normal way, so if we're about to call one
10195 we must authenticate.
10197 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
10198 generating code for !TARGET_ARMV8_3 we can't use it and must
10199 explicitly authenticate.
10200 */
10203 {
10205 {
10214 }
10217 }
10219 /* Stack adjustment for exception handler. */
10221 {
10222 /* We need to unwind the stack by the offset computed by
10223 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
10224 to be SP; letting the CFA move during this adjustment
10225 is just as correct as retaining the CFA from the body
10226 of the function. Therefore, do nothing special. */
10228 }
10233 }
10235 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
10236 normally or return to a previous frame after unwinding.
10238 An EH return uses a single shared return sequence. The epilogue is
10239 exactly like a normal epilogue except that it has an extra input
10240 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
10241 that must be applied after the frame has been destroyed. An extra label
10242 is inserted before the epilogue which initializes this register to zero,
10243 and this is the entry point for a normal return.
10245 An actual EH return updates the return address, initializes the stack
10246 adjustment and jumps directly into the epilogue (bypassing the zeroing
10247 of the adjustment). Since the return address is typically saved on the
10248 stack when a function makes a call, the saved LR must be updated outside
10249 the epilogue.
10251 This poses problems as the store is generated well before the epilogue,
10252 so the offset of LR is not known yet. Also optimizations will remove the
10253 store as it appears dead, even after the epilogue is generated (as the
10254 base or offset for loading LR is different in many cases).
10256 To avoid these problems this implementation forces the frame pointer
10257 in eh_return functions so that the location of LR is fixed and known early.
10258 It also marks the store volatile, so no optimization is permitted to
10259 remove the store. */
10260 rtx
10262 {
10266 /* Mark the store volatile, so no optimization is permitted to remove it. */
10269 }
10271 /* Output code to add DELTA to the first argument, and then jump
10272 to FUNCTION. Used for C++ multiple inheritance. */
10273 static void
10275 HOST_WIDE_INT delta,
10276 HOST_WIDE_INT vcall_offset,
10277 tree function)
10278 {
10279 /* The this pointer is always in x0. Note that this differs from
10280 Arm where the this pointer maybe bumped to r1 if r0 is required
10281 to return a pointer to an aggregate. On AArch64 a result value
10282 pointer will be in x8. */
10300 else
10301 {
10306 {
10310 else
10313 }
10317 else
10324 else
10325 {
10327 Pmode);
10329 }
10333 else
10339 }
10341 /* Generate a tail call to the target function. */
10343 {
10346 }
10362 /* Stop pretending to be a post-reload pass. */
10364 }
10366 static bool
10368 {
10373 {
10377 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
10378 TLS offsets, not real symbol references. */
10381 }
10383 }
10386 static bool
10388 {
10392 /* There's no way to calculate VL-based values using relocations. */
10398 poly_int64 offset;
10401 {
10402 /* We checked for POLY_INT_CST offsets above. */
10406 else
10407 /* Avoid generating a 64-bit relocation in ILP32; leave
10408 to aarch64_expand_mov_immediate to handle it properly. */
10410 }
10413 }
10415 /* Implement TARGET_CASE_VALUES_THRESHOLD.
10416 The expansion for a table switch is quite expensive due to the number
10417 of instructions, the table lookup and hard to predict indirect jump.
10418 When optimizing for speed, and -O3 enabled, use the per-core tuning if
10419 set, otherwise use tables for >= 11 cases as a tradeoff between size and
10420 performance. When optimizing for size, use 8 for smallest codesize. */
10422 static unsigned int
10424 {
10425 /* Use the specified limit for the number of cases before using jump
10426 tables at higher optimization levels. */
10430 else
10432 }
10434 /* Return true if register REGNO is a valid index register.
10435 STRICT_P is true if REG_OK_STRICT is in effect. */
10437 bool
10439 {
10441 {
10449 }
10451 }
10453 /* Return true if register REGNO is a valid base register for mode MODE.
10454 STRICT_P is true if REG_OK_STRICT is in effect. */
10456 bool
10458 {
10460 {
10468 }
10470 /* The fake registers will be eliminated to either the stack or
10471 hard frame pointer, both of which are usually valid base registers.
10472 Reload deals with the cases where the eliminated form isn't valid. */
10477 }
10479 /* Return true if X is a valid base register for mode MODE.
10480 STRICT_P is true if REG_OK_STRICT is in effect. */
10482 static bool
10484 {
10491 }
10493 /* Return true if address offset is a valid index. If it is, fill in INFO
10494 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
10496 static bool
10499 {
10501 rtx index;
10504 /* (reg:P) */
10507 {
10511 }
10512 /* (sign_extend:DI (reg:SI)) */
10517 {
10522 }
10523 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
10530 {
10535 }
10536 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
10543 {
10548 }
10549 /* (and:DI (mult:DI (reg:DI) (const_int scale))
10550 (const_int 0xffffffff<<shift)) */
10557 {
10563 }
10564 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
10565 (const_int 0xffffffff<<shift)) */
10572 {
10578 }
10579 /* (mult:P (reg:P) (const_int scale)) */
10584 {
10588 }
10589 /* (ashift:P (reg:P) (const_int shift)) */
10594 {
10598 }
10599 else
10608 {
10612 }
10613 else
10614 {
10619 }
10623 {
10628 }
10631 }
10633 /* Return true if MODE is one of the modes for which we
10634 support LDP/STP operations. */
10636 static bool
10638 {
10647 }
10649 /* Return true if REGNO is a virtual pointer register, or an eliminable
10650 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
10651 include stack_pointer or hard_frame_pointer. */
10652 static bool
10654 {
10659 }
10661 /* Return true if X is a valid address of type TYPE for machine mode MODE.
10662 If it is, fill in INFO appropriately. STRICT_P is true if
10663 REG_OK_STRICT is in effect. */
10665 bool
10668 aarch64_addr_query_type type)
10669 {
10672 poly_int64 offset;
10674 HOST_WIDE_INT const_size;
10676 /* Whether a vector mode is partial doesn't affect address legitimacy.
10677 Partial vectors like VNx8QImode allow the same indexed addressing
10678 mode and MUL VL addressing mode as full vectors like VNx16QImode;
10679 in both cases, MUL VL counts multiples of GET_MODE_SIZE. */
10683 /* On BE, we use load/store pair for all large int mode load/stores.
10684 TI/TF/TDmode may also use a load/store pair. */
10693 /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
10694 corresponds to the actual size of the memory being loaded/stored and the
10695 mode of the corresponding addressing mode is half of that. */
10697 {
10702 else
10704 }
10712 /* For SVE, only accept [Rn], [Rn, #offset, MUL VL] and [Rn, Rm, LSL #shift].
10713 The latter is not valid for SVE predicates, and that's rejected through
10714 allow_reg_index_p above. */
10719 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
10720 REG addressing. */
10722 && TARGET_SIMD
10723 && !BYTES_BIG_ENDIAN
10731 {
10748 {
10755 }
10760 {
10766 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10767 registers and individual Q registers. The available
10768 address modes are:
10769 X,X: 7-bit signed scaled offset
10770 Q: 9-bit signed offset
10771 We conservatively require an offset representable in either mode.
10772 When performing the check for pairs of X registers i.e. LDP/STP
10773 pass down DImode since that is the natural size of the LDP/STP
10774 instruction memory accesses. */
10784 /* A 7bit offset check because OImode will emit a ldp/stp
10785 instruction (only !TARGET_SIMD or big endian will get here).
10786 For ldp/stp instructions, the offset is scaled for the size of a
10787 single element of the pair. */
10795 /* Three 9/12 bit offsets checks because CImode will emit three
10796 ldr/str instructions (only !TARGET_SIMD or big endian will
10797 get here). */
10813 /* Two 7bit offsets checks because XImode will emit two ldp/stp
10814 instructions (only big endian will get here). */
10826 /* Make "m" use the LD1 offset range for SVE data modes, so
10827 that pre-RTL optimizers like ivopts will work to that
10828 instead of the wider LDR/STR range. */
10835 {
10836 poly_int64 end_offset = (offset
10843 end_offset)));
10844 }
10854 else
10857 }
10860 {
10861 /* Look for base + (scaled/extended) index register. */
10864 {
10867 }
10870 {
10873 }
10874 }
10895 {
10899 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10900 registers and individual Q registers. The available
10901 address modes are:
10902 X,X: 7-bit signed scaled offset
10903 Q: 9-bit signed offset
10904 We conservatively require an offset representable in either mode.
10905 */
10915 else
10917 }
10923 /* load literal: pc-relative constant pool entry. Only supported
10924 for SI mode or larger. */
10930 {
10931 poly_int64 offset;
10937 }
10946 {
10947 poly_int64 offset;
10948 HOST_WIDE_INT const_offset;
10954 {
10955 /* The symbol and offset must be aligned to the access size. */
10961 {
10965 }
10971 else
10980 }
10981 }
10986 }
10987 }
10989 /* Return true if the address X is valid for a PRFM instruction.
10990 STRICT_P is true if we should do strict checking with
10991 aarch64_classify_address. */
10993 bool
10995 {
10998 /* PRFM accepts the same addresses as DImode... */
11003 /* ... except writeback forms. */
11005 }
11007 bool
11009 {
11010 poly_int64 offset;
11013 }
11015 /* Classify the base of symbolic expression X. */
11017 enum aarch64_symbol_type
11019 {
11020 rtx offset;
11024 }
11027 /* Return TRUE if X is a legitimate address for accessing memory in
11028 mode MODE. */
11029 static bool
11031 {
11035 }
11037 /* Return TRUE if X is a legitimate address of type TYPE for accessing
11038 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
11039 bool
11041 aarch64_addr_query_type type)
11042 {
11046 }
11048 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
11050 static bool
11052 poly_int64 orig_offset,
11053 machine_mode mode)
11054 {
11055 HOST_WIDE_INT size;
11057 {
11060 /* A general SVE offset is A * VQ + B. Remove the A component from
11061 coefficient 0 in order to get the constant B. */
11064 /* Split an out-of-range address displacement into a base and
11065 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
11066 range otherwise to increase opportunities for sharing the base
11067 address of different sizes. Unaligned accesses use the signed
11068 9-bit range, TImode/TFmode/TDmode use the intersection of signed
11069 scaled 7-bit and signed 9-bit offset. */
11074 else
11080 /* Split the offset into second_offset and the rest. */
11084 }
11085 else
11086 {
11087 /* Get the mode we should use as the basis of the range. For structure
11088 modes this is the mode of one vector. */
11090 machine_mode step_mode
11093 /* Get the "mul vl" multiplier we'd like to use. */
11097 /* LDR supports a 9-bit range, but the move patterns for
11098 structure modes require all vectors to be in range of the
11099 same base. The simplest way of accomodating that while still
11100 promoting reuse of anchor points between different modes is
11101 to use an 8-bit range unconditionally. */
11103 else
11104 /* Predicates are only handled singly, so we might as well use
11105 the full range. */
11110 /* Convert the "mul vl" multiplier into a byte offset. */
11115 /* Split the offset into second_offset and the rest. */
11119 }
11120 }
11122 /* Return the binary representation of floating point constant VALUE in INTVAL.
11123 If the value cannot be converted, return false without setting INTVAL.
11124 The conversion is done in the given MODE. */
11125 bool
11127 {
11129 /* We make a general exception for 0. */
11131 {
11134 }
11136 scalar_float_mode mode;
11140 /* Only support up to DF mode. */
11152 {
11156 }
11157 else
11162 }
11164 /* Return TRUE if rtx X is an immediate constant that can be moved using a
11165 single MOV(+MOVK) followed by an FMOV. */
11166 bool
11168 {
11173 /* Determine whether it's cheaper to write float constants as
11174 mov/movk pairs over ldr/adrp pairs. */
11180 {
11185 }
11188 }
11190 /* Return TRUE if rtx X is immediate constant 0.0 (but not in Decimal
11191 Floating Point). */
11192 bool
11194 {
11195 /* 0.0 in Decimal Floating Point cannot be represented by #0 or
11196 zr as our callers expect, so no need to check the actual
11197 value if X is of Decimal Floating Point type. */
11204 }
11206 /* Return TRUE if rtx X is immediate constant that fits in a single
11207 MOVI immediate operation. */
11208 bool
11210 {
11214 machine_mode vmode;
11215 scalar_int_mode imode;
11220 {
11224 /* We make a general exception for 0. */
11229 }
11233 else
11236 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
11237 a 128 bit vector mode. */
11244 }
11247 /* Return the fixed registers used for condition codes. */
11249 static bool
11251 {
11255 }
11257 /* This function is used by the call expanders of the machine description.
11258 RESULT is the register in which the result is returned. It's NULL for
11259 "call" and "sibcall".
11260 MEM is the location of the function call.
11261 CALLEE_ABI is a const_int that gives the arm_pcs of the callee.
11262 SIBCALL indicates whether this function call is normal call or sibling call.
11263 It will generate different pattern accordingly. */
11265 void
11267 {
11269 rtvec vec;
11270 machine_mode mode;
11277 /* Decide if we should generate indirect calls by loading the
11278 address of the callee into a register before performing
11279 the branch-and-link. */
11293 else
11298 UNSPEC_CALLEE_ABI);
11304 }
11306 /* Emit call insn with PAT and do aarch64-specific handling. */
11308 void
11310 {
11316 }
11318 machine_mode
11320 {
11324 /* All floating point compares return CCFP if it is an equality
11325 comparison, and CCFPE otherwise. */
11327 {
11329 {
11350 }
11351 }
11353 /* Equality comparisons of short modes against zero can be performed
11354 using the TST instruction with the appropriate bitmask. */
11360 /* Similarly, comparisons of zero_extends from shorter modes can
11361 be performed using an ANDS with an immediate mask. */
11368 /* Zero extracts support equality comparisons. */
11376 /* ANDS/BICS/TST support equality and all signed comparisons. */
11384 /* ADDS/SUBS correctly set N and Z flags. */
11391 /* A compare with a shifted operand. Because of canonicalization,
11392 the comparison will have to be swapped when we emit the assembly
11393 code. */
11401 /* Similarly for a negated operand, but we can only do this for
11402 equalities. */
11409 /* A test for unsigned overflow from an addition. */
11416 /* A test for unsigned overflow from an add with carry. */
11426 /* A test for signed overflow. */
11433 /* For everything else, return CCmode. */
11435 }
11437 static int
11440 int
11442 {
11449 }
11451 static int
11453 {
11455 {
11459 {
11473 }
11478 {
11490 }
11495 {
11507 }
11512 {
11522 }
11527 {
11535 }
11540 {
11546 }
11551 {
11555 }
11560 {
11564 }
11569 {
11573 }
11578 {
11582 }
11587 }
11590 }
11592 bool
11594 HOST_WIDE_INT minval,
11595 HOST_WIDE_INT maxval)
11596 {
11597 rtx elt;
11601 }
11603 bool
11605 {
11607 }
11609 /* Return true if VEC is a constant in which every element is in the range
11610 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
11612 static bool
11614 HOST_WIDE_INT minval,
11615 HOST_WIDE_INT maxval)
11616 {
11628 {
11633 }
11635 }
11637 /* N Z C V. */
11638 #define AARCH64_CC_V 1
11639 #define AARCH64_CC_C (1 << 1)
11640 #define AARCH64_CC_Z (1 << 2)
11641 #define AARCH64_CC_N (1 << 3)
11643 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
11645 {
11662 };
11664 /* Print floating-point vector immediate operand X to F, negating it
11665 first if NEGATE is true. Return true on success, false if it isn't
11666 a constant we can handle. */
11668 static bool
11670 {
11671 rtx elt;
11680 /* Handle the SVE single-bit immediates specially, since they have a
11681 fixed form in the assembly syntax. */
11690 else
11691 {
11697 }
11700 }
11702 /* Return the equivalent letter for size. */
11703 static char
11705 {
11707 {
11713 }
11714 }
11716 /* Print operand X to file F in a target specific manner according to CODE.
11717 The acceptable formatting commands given by CODE are:
11718 'c': An integer or symbol address without a preceding #
11719 sign.
11720 'C': Take the duplicated element in a vector constant
11721 and print it in hex.
11722 'D': Take the duplicated element in a vector constant
11723 and print it as an unsigned integer, in decimal.
11724 'e': Print the sign/zero-extend size as a character 8->b,
11725 16->h, 32->w. Can also be used for masks:
11726 0xff->b, 0xffff->h, 0xffffffff->w.
11727 'I': If the operand is a duplicated vector constant,
11728 replace it with the duplicated scalar. If the
11729 operand is then a floating-point constant, replace
11730 it with the integer bit representation. Print the
11731 transformed constant as a signed decimal number.
11732 'p': Prints N such that 2^N == X (X must be power of 2 and
11733 const int).
11734 'P': Print the number of non-zero bits in X (a const_int).
11735 'H': Print the higher numbered register of a pair (TImode)
11736 of regs.
11737 'm': Print a condition (eq, ne, etc).
11738 'M': Same as 'm', but invert condition.
11739 'N': Take the duplicated element in a vector constant
11740 and print the negative of it in decimal.
11741 'b/h/s/d/q': Print a scalar FP/SIMD register name.
11742 'S/T/U/V': Print a FP/SIMD register name for a register list.
11743 The register printed is the FP/SIMD register name
11744 of X + 0/1/2/3 for S/T/U/V.
11745 'R': Print a scalar Integer/FP/SIMD register name + 1.
11746 'X': Print bottom 16 bits of integer constant in hex.
11747 'w/x': Print a general register name or the zero register
11748 (32-bit or 64-bit).
11749 '0': Print a normal operand, if it's a general register,
11750 then we assume DImode.
11751 'k': Print NZCV for conditional compare instructions.
11752 'A': Output address constant representing the first
11753 argument of X, specifying a relocation offset
11754 if appropriate.
11755 'L': Output constant address specified by X
11756 with a relocation offset if appropriate.
11757 'G': Prints address of X, specifying a PC relative
11758 relocation mode if appropriate.
11759 'y': Output address of LDP or STP - this is used for
11760 some LDP/STPs which don't use a PARALLEL in their
11761 pattern (so the mode needs to be adjusted).
11762 'z': Output address of a typical LDP or STP. */
11764 static void
11766 {
11767 rtx elt;
11769 {
11773 else
11774 {
11775 poly_int64 offset;
11779 else
11781 }
11785 {
11788 {
11791 }
11800 else
11801 {
11804 }
11805 }
11809 {
11813 {
11816 }
11819 }
11824 {
11827 }
11834 {
11837 }
11840 {
11843 }
11849 {
11853 else
11854 {
11857 }
11859 }
11863 {
11865 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
11867 {
11871 }
11874 {
11877 }
11885 else
11887 }
11892 {
11895 }
11901 ;
11902 else
11903 {
11906 }
11915 {
11916 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
11918 }
11927 {
11928 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
11930 }
11944 else
11946 code);
11951 {
11954 }
11959 {
11960 /* Print a replicated constant in hex. */
11962 {
11965 }
11968 }
11972 {
11973 /* Print a replicated constant in decimal, treating it as
11974 unsigned. */
11976 {
11979 }
11982 }
11989 {
11992 }
11995 {
11998 }
12001 {
12004 }
12006 /* Fall through */
12010 {
12013 }
12016 {
12019 {
12022 else
12023 {
12024 char suffix
12029 }
12030 }
12031 else
12050 {
12053 }
12054 /* fall through */
12058 {
12061 }
12067 ;
12068 else
12069 {
12072 }
12076 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
12077 be getting CONST_DOUBLEs holding integers. */
12080 {
12083 }
12085 {
12086 #define buf_size 20
12094 #undef buf_size
12095 }
12101 }
12109 {
12136 }
12142 {
12177 }
12183 {
12189 }
12194 {
12195 HOST_WIDE_INT cond_code;
12198 {
12201 }
12206 }
12211 {
12218 {
12221 }
12225 ? ADDR_QUERY_LDP_STP_N
12228 }
12234 }
12235 }
12237 /* Print address 'x' of a memory access with mode 'mode'.
12238 'op' is the context required by aarch64_classify_address. It can either be
12239 MEM for a normal memory access or PARALLEL for LDP/STP. */
12240 static bool
12242 aarch64_addr_query_type type)
12243 {
12247 /* Check all addresses are Pmode - including ILP32. */
12251 {
12254 }
12258 {
12261 {
12264 }
12268 {
12269 HOST_WIDE_INT vnum
12275 }
12285 else
12294 else
12303 else
12309 /* Writeback is only supported for fixed-width modes. */
12312 {
12335 }
12347 }
12350 }
12352 /* Print address 'x' of a memory access with mode 'mode'. */
12353 static void
12355 {
12358 }
12360 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
12362 static bool
12364 {
12366 {
12369 }
12371 }
12373 bool
12375 {
12382 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
12383 referencing instruction, but they are constant offsets, not
12384 symbols. */
12390 {
12392 {
12398 }
12401 }
12404 }
12406 /* Implement REGNO_REG_CLASS. */
12408 enum reg_class
12410 {
12435 }
12437 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
12438 If OFFSET is out of range, return an offset of an anchor point
12439 that is in range. Return 0 otherwise. */
12441 static HOST_WIDE_INT
12443 machine_mode mode)
12444 {
12445 /* Does it look like we'll need a 16-byte load/store-pair operation? */
12449 /* For offsets that aren't a multiple of the access size, the limit is
12450 -256...255. */
12452 {
12453 /* BLKmode typically uses LDP of X-registers. */
12457 }
12459 /* Small negative offsets are supported. */
12466 /* Use 12-bit offset by access size. */
12468 }
12470 static rtx
12472 {
12473 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
12474 where mask is selected by alignment and size of the offset.
12475 We try to pick as large a range for the offset as possible to
12476 maximize the chance of a CSE. However, for aligned addresses
12477 we limit the range to 4k so that structures with different sized
12478 elements are likely to use the same base. We need to be careful
12479 not to split a CONST for some forms of address expression, otherwise
12480 it will generate sub-optimal code. */
12483 {
12489 {
12493 /* Force any scaling into a temp for CSE. */
12497 /* Let the pointer register be in op0. */
12501 /* If the pointer is virtual or frame related, then we know that
12502 virtual register instantiation or register elimination is going
12503 to apply a second constant. We want the two constants folded
12504 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
12506 {
12510 }
12512 /* Otherwise, in order to encourage CSE (and thence loop strength
12513 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
12517 }
12519 HOST_WIDE_INT size;
12521 {
12523 mode);
12525 {
12529 }
12530 }
12531 }
12534 }
12536 static reg_class_t
12538 reg_class_t rclass,
12539 machine_mode mode,
12541 {
12542 /* Use aarch64_sve_reload_mem for SVE memory reloads that cannot use
12543 LDR and STR. See the comment at the head of aarch64-sve.md for
12544 more details about the big-endian handling. */
12552 {
12555 }
12557 /* If we have to disable direct literal pool loads and stores because the
12558 function is too big, then we need a scratch register. */
12563 {
12566 }
12568 /* Without the TARGET_SIMD instructions we cannot move a Q register
12569 to a Q register directly. We need a scratch. */
12576 && !TARGET_SIMD
12579 {
12582 }
12584 /* A TFmode, TImode or TDmode memory access should be handled via an FP_REGS
12585 because AArch64 has richer addressing modes for LDR/STR instructions
12586 than LDP/STP instructions. */
12597 }
12599 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. */
12601 static bool
12603 reg_class_t class2)
12604 {
12608 {
12609 /* We can't do a 128-bit FPR-to-FPR move without TARGET_SIMD,
12610 so we can't easily split a move involving tuples of 128-bit
12611 vectors. Force the copy through memory instead.
12613 (Tuples of 64-bit vectors are fine.) */
12617 }
12619 }
12621 static bool
12623 {
12626 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
12627 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
12631 }
12633 poly_int64
12635 {
12637 {
12644 }
12647 {
12651 }
12654 }
12657 /* Get return address without mangling. */
12659 rtx
12661 {
12663 /* Note: aarch64_return_address_signing_enabled only
12664 works after cfun->machine->frame.laid_out is set,
12665 so here we don't know if the return address will
12666 be signed or not. */
12671 }
12674 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
12675 previous frame. */
12677 rtx
12679 {
12683 }
12685 static void
12687 {
12688 /* Even if the current function doesn't have branch protection, some
12689 later function might, so since this template is only generated once
12690 we have to add a BTI just in case. */
12694 {
12697 }
12698 else
12699 {
12702 }
12705 /* We always emit a speculation barrier.
12706 This is because the same trampoline template is used for every nested
12707 function. Since nested functions are not particularly common or
12708 performant we don't worry too much about the extra instructions to copy
12709 around.
12710 This is not yet a problem, since we have not yet implemented function
12711 specific attributes to choose between hardening against straight line
12712 speculation or not, but such function specific attributes are likely to
12713 happen in the future. */
12718 }
12720 static void
12722 {
12726 /* Don't need to copy the trailing D-words, we fill those in below. */
12727 /* We create our own memory address in Pmode so that `emit_block_move` can
12728 use parts of the backend which expect Pmode addresses. */
12742 /* XXX We should really define a "clear_cache" pattern and use
12743 gen_clear_cache(). */
12747 a_tramp,
12748 TRAMPOLINE_SIZE));
12749 }
12751 static unsigned char
12753 {
12754 /* ??? Logically we should only need to provide a value when
12755 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
12756 can hold MODE, but at the moment we need to handle all modes.
12757 Just ignore any runtime parts for registers that can't store them. */
12761 {
12792 }
12794 }
12796 static reg_class_t
12798 {
12803 {
12809 }
12811 /* Register eliminiation can result in a request for
12812 SP+constant->FP_REGS. We cannot support such operations which
12813 use SP as source and an FP_REG as destination, so reject out
12814 right now. */
12816 {
12819 /* Look through a possible SUBREG introduced by ILP32. */
12825 POINTER_REGS));
12827 }
12830 }
12832 void
12834 {
12836 }
12838 static void
12840 {
12843 else
12844 {
12846 /* While priority is known to be in range [0, 65535], so 18 bytes
12847 would be enough, the compiler might not know that. To avoid
12848 -Wformat-truncation false positive, use a larger size. */
12855 }
12856 }
12858 static void
12860 {
12863 else
12864 {
12866 /* While priority is known to be in range [0, 65535], so 18 bytes
12867 would be enough, the compiler might not know that. To avoid
12868 -Wformat-truncation false positive, use a larger size. */
12875 }
12876 }
12880 {
12886 {
12887 {
12890 },
12891 {
12894 },
12895 {
12898 },
12899 /* We assume that DImode is only generated when not optimizing and
12900 that we don't really need 64-bit address offsets. That would
12901 imply an object file with 8GB of code in a single function! */
12902 {
12905 }
12906 };
12915 /* Need to implement table size reduction, by chaning the code below. */
12924 operands);
12927 }
12930 /* Return size in bits of an arithmetic operand which is shifted/scaled and
12931 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
12932 operator. */
12934 int
12936 {
12938 {
12941 {
12945 }
12946 }
12948 }
12950 /* Constant pools are per function only when PC relative
12951 literal loads are true or we are in the large memory
12952 model. */
12956 {
12959 }
12961 static bool
12963 {
12964 /* We can't use blocks for constants when we're using a per-function
12965 constant pool. */
12967 }
12969 /* Select appropriate section for constants depending
12970 on where we place literal pools. */
12974 rtx x,
12976 {
12981 }
12983 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
12984 void
12986 HOST_WIDE_INT offset)
12987 {
12988 /* When using per-function literal pools, we must ensure that any code
12989 section is aligned to the minimal instruction length, lest we get
12990 errors from the assembler re "unaligned instructions". */
12993 }
12995 /* Costs. */
12997 /* Helper function for rtx cost calculation. Strip a shift expression
12998 from X. Returns the inner operand if successful, or the original
12999 expression on failure. */
13000 static rtx
13002 {
13005 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
13006 we can convert both to ROR during final output. */
13021 }
13023 /* Helper function for rtx cost calculation. Strip an extend
13024 expression from X. Returns the inner operand if successful, or the
13025 original expression on failure. We deal with a number of possible
13026 canonicalization variations here. If STRIP_SHIFT is true, then
13027 we can strip off a shift also. */
13028 static rtx
13030 {
13031 scalar_int_mode mode;
13045 /* Now handle extended register, as this may also have an optional
13046 left shift by 1..4. */
13061 }
13063 /* Helper function for rtx cost calculation. Strip extension as well as any
13064 inner VEC_SELECT high-half from X. Returns the inner vector operand if
13065 successful, or the original expression on failure. */
13066 static rtx
13068 {
13070 {
13076 }
13078 }
13080 /* Helper function for rtx cost calculation. Strip VEC_DUPLICATE as well as
13081 any subsequent extend and VEC_SELECT from X. Returns the inner scalar
13082 operand if successful, or the original expression on failure. */
13083 static rtx
13085 {
13088 {
13095 }
13097 }
13099 /* Return true iff CODE is a shift supported in combination
13100 with arithmetic instructions. */
13102 static bool
13104 {
13106 }
13109 /* Return true iff X is a cheap shift without a sign extend. */
13111 static bool
13113 {
13139 }
13141 /* Helper function for rtx cost calculation. Calculate the cost of
13142 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
13143 Return the calculated cost of the expression, recursing manually in to
13144 operands where needed. */
13146 static int
13148 {
13162 {
13165 {
13166 /* The select-operand-high-half versions of the instruction have the
13167 same cost as the three vector version - don't add the costs of the
13168 extension or selection into the costs of the multiply. */
13171 /* The by-element versions of the instruction have the same costs as
13172 the normal 3-vector version. We make an assumption that the input
13173 to the VEC_DUPLICATE is already on the FP & SIMD side. This means
13174 costing of a MUL by element pre RA is a bit optimistic. */
13177 }
13181 {
13184 /* This is to catch the SSRA costing currently flowing here. */
13185 else
13187 }
13189 }
13191 /* Integer multiply/fma. */
13193 {
13194 /* The multiply will be canonicalized as a shift, cost it as such. */
13198 {
13202 {
13204 {
13205 /* If the shift is considered cheap,
13206 then don't add any cost. */
13208 ;
13210 /* ARITH + shift-by-register. */
13213 /* ARITH + extended register. We don't have a cost field
13214 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
13216 else
13217 /* ARITH + shift-by-immediate. */
13219 }
13220 else
13221 /* LSL (immediate). */
13224 }
13225 /* Strip extends as we will have costed them in the case above. */
13232 }
13234 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
13235 compound and let the below cases handle it. After all, MNEG is a
13236 special-case alias of MSUB. */
13238 {
13241 }
13243 /* Integer multiplies or FMAs have zero/sign extending variants. */
13248 {
13253 {
13255 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
13257 else
13258 /* MUL/SMULL/UMULL. */
13260 }
13263 }
13265 /* This is either an integer multiply or a MADD. In both cases
13266 we want to recurse and cost the operands. */
13271 {
13273 /* MADD/MSUB. */
13275 else
13276 /* MUL. */
13278 }
13281 }
13282 else
13283 {
13285 {
13286 /* Floating-point FMA/FMUL can also support negations of the
13287 operands, unless the rounding mode is upward or downward in
13288 which case FNMUL is different than FMUL with operand negation. */
13292 {
13297 }
13300 /* FMADD/FNMADD/FNMSUB/FMSUB. */
13302 else
13303 /* FMUL/FNMUL. */
13305 }
13310 }
13311 }
13313 static int
13315 machine_mode mode,
13316 addr_space_t as ATTRIBUTE_UNUSED,
13318 {
13326 {
13328 {
13329 /* This is a CONST or SYMBOL ref which will be split
13330 in a different way depending on the code model in use.
13331 Cost it through the generic infrastructure. */
13333 /* Divide through by the cost of one instruction to
13334 bring it to the same units as the address costs. */
13336 /* The cost is then the cost of preparing the address,
13337 followed by an immediate (possibly 0) offset. */
13339 }
13340 else
13341 {
13342 /* This is most likely a jump table from a case
13343 statement. */
13345 }
13346 }
13349 {
13360 {
13366 else
13368 }
13369 else
13388 }
13392 {
13393 /* For the sake of calculating the cost of the shifted register
13394 component, we can treat same sized modes in the same way. */
13401 else
13402 /* We can't tell, or this is a 128-bit vector. */
13404 }
13407 }
13409 /* Return the cost of a branch. If SPEED_P is true then the compiler is
13410 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
13411 to be taken. */
13413 int
13415 {
13416 /* When optimizing for speed, use the cost of unpredictable branches. */
13422 else
13424 }
13426 /* Return true if X is a zero or sign extract
13427 usable in an ADD or SUB (extended register) instruction. */
13428 static bool
13430 {
13431 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
13432 No shift. */
13438 }
13440 static bool
13442 {
13444 {
13456 }
13457 }
13459 /* Return true iff X is an rtx that will match an extr instruction
13460 i.e. as described in the *extr<mode>5_insn family of patterns.
13461 OP0 and OP1 will be set to the operands of the shifts involved
13462 on success and will be NULL_RTX otherwise. */
13464 static bool
13466 {
13468 scalar_int_mode mode;
13483 {
13484 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
13496 {
13500 }
13501 }
13504 }
13506 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
13507 storing it in *COST. Result is true if the total cost of the operation
13508 has now been calculated. */
13509 static bool
13511 {
13512 rtx inner;
13513 rtx comparator;
13519 {
13523 }
13524 else
13525 {
13529 }
13532 {
13533 /* Conditional branch. */
13536 else
13537 {
13539 {
13541 {
13542 /* TBZ/TBNZ/CBZ/CBNZ. */
13544 /* TBZ/TBNZ. */
13547 else
13548 /* CBZ/CBNZ. */
13552 }
13555 {
13556 /* SUB and SUBS. */
13561 }
13562 }
13564 {
13565 /* TBZ/TBNZ. */
13568 }
13569 }
13570 }
13572 {
13573 /* CCMP. */
13575 {
13576 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
13580 {
13585 else
13587 }
13589 }
13591 /* It's a conditional operation based on the status flags,
13592 so it must be some flavor of CSEL. */
13594 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
13600 {
13601 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
13604 }
13606 {
13609 /* CSINV/NEG with zero extend + const 0 (*csinv3_uxtw_insn3). */
13611 }
13616 }
13618 /* We don't know what this is, cost all operands. */
13620 }
13622 /* Check whether X is a bitfield operation of the form shift + extend that
13623 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
13624 operand to which the bitfield operation is applied. Otherwise return
13625 NULL_RTX. */
13627 static rtx
13629 {
13643 {
13661 }
13664 }
13666 /* Return true if the mask and a shift amount from an RTX of the form
13667 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
13668 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
13670 bool
13672 rtx shft_amnt)
13673 {
13680 }
13682 /* Return true if the masks and a shift amount from an RTX of the form
13683 ((x & MASK1) | ((y << SHIFT_AMNT) & MASK2)) are valid to combine into
13684 a BFI instruction of mode MODE. See *arch64_bfi patterns. */
13686 bool
13691 {
13694 /* Verify that there is no overlap in what bits are set in the two masks. */
13698 /* Verify that mask2 is not all zeros or ones. */
13702 /* The shift amount should always be less than the mode size. */
13705 /* Verify that the mask being shifted is contiguous and would be in the
13706 least significant bits after shifting by shft_amnt. */
13709 }
13711 /* Calculate the cost of calculating X, storing it in *COST. Result
13712 is true if the total cost of the operation has now been calculated. */
13713 static bool
13716 {
13721 scalar_int_mode int_mode;
13723 /* By default, assume that everything has equivalent cost to the
13724 cheapest instruction. Any additional costs are applied as a delta
13725 above this default. */
13729 {
13731 /* The cost depends entirely on the operands to SET. */
13737 {
13740 {
13754 }
13763 /* Fall through. */
13765 /* The cost is one per vector-register copied. */
13767 {
13770 }
13771 /* const0_rtx is in general free, but we will use an
13772 instruction to set a register to 0. */
13774 {
13775 /* The cost is 1 per register copied. */
13778 }
13779 else
13780 /* Cost is just the cost of the RHS of the set. */
13786 /* Bit-field insertion. Strip any redundant widening of
13787 the RHS to meet the width of the target. */
13798 {
13799 /* MOV immediate is assumed to always be cheap. */
13801 }
13802 else
13803 {
13804 /* BFM. */
13808 }
13813 /* We can't make sense of this, assume default cost. */
13816 }
13820 /* If an instruction can incorporate a constant within the
13821 instruction, the instruction's expression avoids calling
13822 rtx_cost() on the constant. If rtx_cost() is called on a
13823 constant, then it is usually because the constant must be
13824 moved into a register by one or more instructions.
13826 The exception is constant 0, which can be expressed
13827 as XZR/WZR and is therefore free. The exception to this is
13828 if we have (set (reg) (const0_rtx)) in which case we must cost
13829 the move. However, we can catch that when we cost the SET, so
13830 we don't need to consider that here. */
13833 else
13834 {
13835 /* To an approximation, building any other constant is
13836 proportionally expensive to the number of instructions
13837 required to build that constant. This is true whether we
13838 are compiling for SPEED or otherwise. */
13843 }
13848 /* First determine number of instructions to do the move
13849 as an integer constant. */
13853 {
13864 }
13867 {
13868 /* mov[df,sf]_aarch64. */
13870 /* FMOV (scalar immediate). */
13873 {
13874 /* This will be a load from memory. */
13877 else
13879 }
13880 else
13881 /* Otherwise this is +0.0. We get this using MOVI d0, #0
13882 or MOV v0.s[0], wzr - neither of which are modeled by the
13883 cost tables. Just use the default cost. */
13884 {
13885 }
13886 }
13892 {
13893 /* For loads we want the base cost of a load, plus an
13894 approximation for the additional cost of the addressing
13895 mode. */
13909 }
13917 {
13919 {
13920 /* FNEG. */
13922 }
13924 }
13927 {
13930 {
13931 /* CSETM. */
13934 }
13936 /* Cost this as SUB wzr, X. */
13940 }
13943 {
13944 /* Support (neg(fma...)) as a single instruction only if
13945 sign of zeros is unimportant. This matches the decision
13946 making in aarch64.md. */
13948 {
13949 /* FNMADD. */
13952 }
13954 {
13955 /* FNMUL. */
13958 }
13960 /* FNEG. */
13963 }
13970 {
13973 else
13975 }
13992 {
13996 }
13999 {
14000 /* TODO: A write to the CC flags possibly costs extra, this
14001 needs encoding in the cost tables. */
14004 /* ANDS. */
14006 {
14009 }
14012 {
14013 /* ADDS (and CMN alias). */
14016 }
14019 {
14020 /* SUBS. */
14023 }
14028 {
14029 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
14030 Handle it here directly rather than going to cost_logic
14031 since we know the immediate generated for the TST is valid
14032 so we can avoid creating an intermediate rtx for it only
14033 for costing purposes. */
14040 }
14043 {
14044 /* CMN. */
14051 }
14053 /* CMP.
14055 Compare can freely swap the order of operands, and
14056 canonicalization puts the more complex operation first.
14057 But the integer MINUS logic expects the shift/extend
14058 operation in op1. */
14061 {
14064 }
14066 }
14069 {
14070 /* FCMP. */
14075 {
14077 /* FCMP supports constant 0.0 for no extra cost. */
14079 }
14081 }
14084 {
14085 /* Vector compare. */
14090 {
14091 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
14092 cost. */
14094 }
14096 }
14100 {
14104 cost_minus:
14106 {
14107 /* SUBL2 and SUBW2. */
14110 {
14111 /* The select-operand-high-half versions of the sub instruction
14112 have the same cost as the regular three vector version -
14113 don't add the costs of the select into the costs of the sub.
14114 */
14117 }
14118 }
14122 /* Detect valid immediates. */
14128 {
14130 /* SUB(S) (immediate). */
14133 }
14135 /* Look for SUB (extended register). */
14138 {
14146 }
14150 /* Cost this as an FMA-alike operation. */
14154 {
14157 speed);
14159 }
14164 {
14166 {
14167 /* Vector SUB. */
14169 }
14171 {
14172 /* SUB(S). */
14174 }
14176 {
14177 /* FSUB. */
14179 }
14180 }
14182 }
14185 {
14186 rtx new_op0;
14191 cost_plus:
14193 {
14194 /* ADDL2 and ADDW2. */
14197 {
14198 /* The select-operand-high-half versions of the add instruction
14199 have the same cost as the regular three vector version -
14200 don't add the costs of the select into the costs of the add.
14201 */
14204 }
14205 }
14209 {
14210 /* CSINC. */
14214 }
14219 {
14223 {
14224 /* ADD (immediate). */
14227 /* Some tunings prefer to not use the VL-based scalar ops.
14228 Increase the cost of the poly immediate to prevent their
14229 formation. */
14234 }
14236 }
14240 /* Look for ADD (extended register). */
14243 {
14251 }
14253 /* Strip any extend, leave shifts behind as we will
14254 cost them through mult_cost. */
14259 {
14261 speed);
14263 }
14268 {
14270 {
14271 /* Vector ADD. */
14273 }
14275 {
14276 /* ADD. */
14278 }
14280 {
14281 /* FADD. */
14283 }
14284 }
14286 }
14292 {
14295 else
14297 }
14302 {
14306 {
14309 else
14311 }
14313 }
14316 {
14323 }
14324 /* Fall through. */
14327 cost_logic:
14332 {
14336 }
14344 {
14345 /* This is a UBFM/SBFM. */
14350 }
14353 {
14355 {
14356 /* We have a mask + shift version of a UBFIZ
14357 i.e. the *andim_ashift<mode>_bfiz pattern. */
14361 {
14368 }
14370 {
14371 /* We possibly get the immediate for free, this is not
14372 modelled. */
14379 }
14380 }
14381 else
14382 {
14385 /* Handle ORN, EON, or BIC. */
14391 /* If we had a shift on op0 then this is a logical-shift-
14392 by-register/immediate operation. Otherwise, this is just
14393 a logical operation. */
14395 {
14397 {
14398 /* Shift by immediate. */
14401 else
14403 }
14404 else
14406 }
14408 /* In both cases we want to cost both operands. */
14415 }
14416 }
14424 {
14425 /* Vector NOT. */
14428 }
14430 /* MVN-shifted-reg. */
14432 {
14439 }
14440 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
14441 Handle the second form here taking care that 'a' in the above can
14442 be a shift. */
14444 {
14453 {
14456 else
14458 }
14461 }
14462 /* MVN. */
14471 /* If a value is written in SI mode, then zero extended to DI
14472 mode, the operation will in general be free as a write to
14473 a 'w' register implicitly zeroes the upper bits of an 'x'
14474 register. However, if this is
14476 (set (reg) (zero_extend (reg)))
14478 we must cost the explicit register move. */
14481 {
14484 /* If OP_COST is non-zero, then the cost of the zero extend
14485 is effectively the cost of the inner operation. Otherwise
14486 we have a MOV instruction and we take the cost from the MOV
14487 itself. This is true independently of whether we are
14488 optimizing for space or time. */
14493 }
14495 {
14496 /* All loads can zero extend to any size for free. */
14499 }
14503 {
14508 }
14511 {
14513 {
14514 /* UMOV. */
14516 }
14517 else
14518 {
14519 /* We generate an AND instead of UXTB/UXTH. */
14521 }
14522 }
14527 {
14528 /* LDRSH. */
14530 {
14537 }
14539 }
14543 {
14548 }
14551 {
14554 else
14556 }
14564 {
14566 {
14568 {
14569 /* Vector shift (immediate). */
14571 }
14572 else
14573 {
14574 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
14575 aliases. */
14577 }
14578 }
14580 /* We can incorporate zero/sign extend for free. */
14587 }
14588 else
14589 {
14591 {
14593 /* Vector shift (register). */
14595 }
14596 else
14597 {
14599 /* LSLV. */
14606 {
14608 /* We already demanded XEXP (op1, 0) to be REG_P, so
14609 don't recurse into it. */
14611 }
14612 }
14614 }
14624 {
14625 /* ASR (immediate) and friends. */
14627 {
14630 else
14632 }
14636 }
14637 else
14638 {
14640 {
14642 /* Vector shift (register). */
14644 }
14645 else
14646 {
14648 /* ASR (register) and friends. */
14655 {
14657 /* We already demanded XEXP (op1, 0) to be REG_P, so
14658 don't recurse into it. */
14660 }
14661 }
14663 }
14669 {
14670 /* LDR. */
14673 }
14676 {
14677 /* ADRP, followed by ADD. */
14681 }
14684 {
14685 /* ADR. */
14688 }
14691 {
14692 /* One extra load instruction, after accessing the GOT. */
14696 }
14701 /* ADRP/ADD (immediate). */
14708 /* UBFX/SBFX. */
14710 {
14713 else
14715 }
14717 /* We can trust that the immediates used will be correct (there
14718 are no by-register forms), so we need only cost op0. */
14724 /* aarch64_rtx_mult_cost always handles recursion to its
14725 operands. */
14729 /* We can expand signed mod by power of 2 using a NEGS, two parallel
14730 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
14731 an unconditional negate. This case should only ever be reached through
14732 the set_smod_pow2_cheap check in expmed.cc. */
14736 {
14737 /* We expand to 4 instructions. Reset the baseline. */
14745 }
14747 /* Fall-through. */
14750 {
14751 /* Slighly prefer UMOD over SMOD. */
14758 }
14765 {
14769 /* There is no integer SQRT, so only DIV and UDIV can get
14770 here. */
14772 /* Slighly prefer UDIV over SDIV. */
14774 else
14776 }
14802 {
14805 else
14807 }
14809 /* FMSUB, FNMADD, and FNMSUB are free. */
14816 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
14817 and the by-element operand as operand 0. */
14821 /* Catch vector-by-element operations. The by-element operand can
14822 either be (vec_duplicate (vec_select (x))) or just
14823 (vec_select (x)), depending on whether we are multiplying by
14824 a vector or a scalar.
14826 Canonicalization is not very good in these cases, FMA4 will put the
14827 by-element operand as operand 0, FNMA4 will have it as operand 1. */
14838 /* If the remaining parameters are not registers,
14839 get the cost to put them into registers. */
14853 {
14855 {
14856 /*Vector truncate. */
14858 }
14859 else
14861 }
14866 {
14868 {
14869 /*Vector conversion. */
14871 }
14872 else
14874 }
14880 /* Strip the rounding part. They will all be implemented
14881 by the fcvt* family of instructions anyway. */
14883 {
14892 }
14895 {
14898 else
14900 }
14902 /* We can combine fmul by a power of 2 followed by a fcvt into a single
14903 fixed-point fcvt. */
14908 {
14912 }
14919 {
14920 /* ABS (vector). */
14923 }
14925 {
14928 /* FABD, which is analogous to FADD. */
14930 {
14937 }
14938 /* Simple FABS is analogous to FNEG. */
14941 }
14942 else
14943 {
14944 /* Integer ABS will either be split to
14945 two arithmetic instructions, or will be an ABS
14946 (scalar), which we don't model. */
14950 }
14956 {
14959 else
14960 {
14961 /* FMAXNM/FMINNM/FMAX/FMIN.
14962 TODO: This may not be accurate for all implementations, but
14963 we do not model this in the cost tables. */
14965 }
14966 }
14970 /* The floating point round to integer frint* instructions. */
14972 {
14977 }
14980 {
14985 }
14990 /* Decompose <su>muldi3_highpart. */
14992 mode == DImode
14993 /* (lshiftrt:TI */
14996 /* (mult:TI */
14998 /* (ANY_EXTEND:TI (reg:DI))
14999 (ANY_EXTEND:TI (reg:DI))) */
15006 /* (const_int 64) */
15009 {
15010 /* UMULH/SMULH. */
15018 }
15021 {
15022 /* Load using MOVI/MVNI. */
15028 }
15030 /* depending on the operation, either DUP or INS.
15031 For now, keep default costing. */
15034 /* Load using a DUP. */
15038 {
15042 /* cost subreg of 0 as free, otherwise as DUP */
15045 ;
15048 else
15051 }
15054 }
15062 }
15064 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
15065 calculated for X. This cost is stored in *COST. Returns true
15066 if the total cost of X was calculated. */
15067 static bool
15070 {
15075 {
15080 }
15083 }
15085 static int
15088 {
15094 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
15103 /* Make RDFFR very expensive. In particular, if we know that the FFR
15104 contains a PTRUE (e.g. after a SETFFR), we must never use RDFFR
15105 as a way of obtaining a PTRUE. */
15111 /* Moving between GPR and stack cost is the same as GP2GP. */
15116 /* To/From the stack register, we move via the gprs. */
15124 {
15125 /* 128-bit operations on general registers require 2 instructions. */
15133 /* When AdvSIMD instructions are disabled it is not possible to move
15134 a 128-bit value directly between Q registers. This is handled in
15135 secondary reload. A general register is used as a scratch to move
15136 the upper DI value and the lower DI value is moved directly,
15137 hence the cost is the sum of three moves. */
15142 }
15152 {
15153 /* Needs a round-trip through memory, which can use LDP/STP for pairs.
15154 The cost must be greater than 2 units to indicate that direct
15155 moves aren't possible. */
15159 }
15162 }
15164 /* Implements TARGET_MEMORY_MOVE_COST. */
15165 static int
15167 {
15186 }
15188 /* Implement TARGET_INIT_BUILTINS. */
15189 static void
15191 {
15194 #ifdef SUBTARGET_INIT_BUILTINS
15195 SUBTARGET_INIT_BUILTINS;
15196 #endif
15197 }
15199 /* Implement TARGET_FOLD_BUILTIN. */
15200 static tree
15202 {
15207 {
15213 }
15215 }
15217 /* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
15218 static bool
15220 {
15227 {
15235 }
15242 }
15244 /* Implement TARGET_EXPAND_BUILTIN. */
15245 static rtx
15247 {
15252 {
15258 }
15260 }
15262 /* Implement TARGET_BUILTIN_DECL. */
15263 static tree
15265 {
15268 {
15274 }
15276 }
15278 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
15279 to optimize 1.0/sqrt. */
15281 static bool
15283 {
15285 && flag_unsafe_math_optimizations
15289 }
15291 /* Function to decide when to use the approximate reciprocal square root
15292 builtin. */
15294 static tree
15296 {
15304 {
15310 }
15312 }
15314 /* Emit code to perform the floating-point operation:
15316 DST = SRC1 * SRC2
15318 where all three operands are already known to be registers.
15319 If the operation is an SVE one, PTRUE is a suitable all-true
15320 predicate. */
15322 static void
15324 {
15329 else
15331 }
15333 /* Emit instruction sequence to compute either the approximate square root
15334 or its approximate reciprocal, depending on the flag RECP, and return
15335 whether the sequence was emitted or not. */
15337 bool
15339 {
15343 {
15346 }
15349 {
15356 || flag_trapping_math
15357 || !flag_unsafe_math_optimizations
15360 }
15361 else
15362 /* Caller assumes we cannot fail. */
15373 {
15374 /* When calculating the approximate square root, compare the
15375 argument with 0.0 and create a mask. */
15378 {
15383 }
15384 else
15385 {
15390 }
15391 }
15393 /* Estimate the approximate reciprocal square root. */
15397 /* Iterate over the series twice for SF and thrice for DF. */
15400 /* Optionally iterate over the series once less for faster performance
15401 while sacrificing the accuracy. */
15404 iterations--;
15406 /* Iterate over the series to calculate the approximate reciprocal square
15407 root. */
15410 {
15418 }
15421 {
15423 /* Multiply nonzero source values by the corresponding intermediate
15424 result elements, so that the final calculation is the approximate
15425 square root rather than its reciprocal. Select a zero result for
15426 zero source values, to avoid the Inf * 0 -> NaN that we'd get
15427 otherwise. */
15430 else
15431 {
15432 /* Qualify the approximate reciprocal square root when the
15433 argument is 0.0 by squashing the intermediary result to 0.0. */
15439 /* Calculate the approximate square root. */
15441 }
15442 }
15444 /* Finalize the approximation. */
15448 }
15450 /* Emit the instruction sequence to compute the approximation for the division
15451 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
15453 bool
15455 {
15466 || flag_trapping_math
15467 || !flag_unsafe_math_optimizations
15479 /* Estimate the approximate reciprocal. */
15483 /* Iterate over the series twice for SF and thrice for DF. */
15486 /* Optionally iterate over the series less for faster performance,
15487 while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */
15490 ? aarch64_double_recp_precision
15493 /* Iterate over the series to calculate the approximate reciprocal. */
15496 {
15501 }
15504 {
15505 /* As the approximate reciprocal of DEN is already calculated, only
15506 calculate the approximate division when NUM is not 1.0. */
15509 }
15511 /* Finalize the approximation. */
15514 }
15516 /* Return the number of instructions that can be issued per cycle. */
15517 static int
15519 {
15521 }
15523 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15524 static int
15526 {
15538 }
15540 static int
15542 {
15546 }
15549 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
15550 autopref_multipass_dfa_lookahead_guard from haifa-sched.cc. It only
15551 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
15553 static int
15556 {
15558 }
15561 /* Vectorizer cost model target hooks. */
15563 /* Information about how the CPU would issue the scalar, Advanced SIMD
15564 or SVE version of a vector loop, using the scheme defined by the
15565 aarch64_base_vec_issue_info hierarchy of structures. */
15566 class aarch64_vec_op_count
15567 {
15587 /* The number of individual "general" operations. See the comments
15588 in aarch64_base_vec_issue_info for details. */
15591 /* The number of load and store operations, under the same scheme
15592 as above. */
15596 /* The minimum number of cycles needed to execute all loop-carried
15597 operations, which in the vector code become associated with
15598 reductions. */
15601 /* The number of individual predicate operations. See the comments
15602 in aarch64_sve_vec_issue_info for details. */
15606 /* The issue information for the core. */
15609 /* - If M_VEC_FLAGS is zero then this structure describes scalar code
15610 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then this structure describes
15611 Advanced SIMD code.
15612 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then this structure describes
15613 SVE code. */
15616 /* Assume that, when the code is executing on the core described
15617 by M_ISSUE_INFO, one iteration of the loop will handle M_VF_FACTOR
15618 times more data than the vectorizer anticipates.
15620 This is only ever different from 1 for SVE. It allows us to consider
15621 what would happen on a 256-bit SVE target even when the -mtune
15622 parameters say that the “likely” SVE length is 128 bits. */
15624 };
15632 {
15633 }
15635 /* Return the base issue information (i.e. the parts that make sense
15636 for both scalar and vector code). Return null if we have no issue
15637 information. */
15640 {
15644 }
15646 /* If the structure describes vector code and we have associated issue
15647 information, return that issue information, otherwise return null. */
15650 {
15656 }
15658 /* If the structure describes SVE code and we have associated issue
15659 information, return that issue information, otherwise return null. */
15662 {
15666 }
15668 /* Estimate the minimum number of cycles per iteration needed to rename
15669 the instructions.
15671 ??? For now this is done inline rather than via cost tables, since it
15672 isn't clear how it should be parameterized for the general case. */
15673 fractional_cost
15675 {
15679 /* + 1 for an addition. We've already counted a general op for each
15680 store, so we don't need to account for stores separately. The branch
15681 reads no registers and so does not need to be counted either.
15683 ??? This value is very much on the pessimistic side, but seems to work
15684 pretty well in practice. */
15688 }
15690 /* Like min_cycles_per_iter, but excluding predicate operations. */
15691 fractional_cost
15693 {
15704 }
15706 /* Like min_cycles_per_iter, but including only the predicate operations. */
15707 fractional_cost
15709 {
15713 }
15715 /* Estimate the minimum number of cycles needed to issue the operations.
15716 This is a very simplistic model! */
15717 fractional_cost
15719 {
15722 }
15724 /* Dump information about the structure. */
15725 void
15727 {
15744 {
15746 " estimated min cycles per iteration"
15750 " estimated min cycles per iteration"
15752 }
15757 }
15759 /* Information about vector code that we're in the process of costing. */
15761 {
15776 aarch64_vec_op_count *);
15785 /* True if we have performed one-time initialization based on the
15786 vec_info. */
15789 /* This loop uses an average operation that is not supported by SVE, but is
15790 supported by Advanced SIMD and SVE2. */
15793 /* - If M_VEC_FLAGS is zero then we're costing the original scalar code.
15794 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then we're costing Advanced
15795 SIMD code.
15796 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then we're costing SVE code. */
15799 /* At the moment, we do not model LDP and STP in the vector and scalar costs.
15800 This means that code such as:
15802 a[0] = x;
15803 a[1] = x;
15805 will be costed as two scalar instructions and two vector instructions
15806 (a scalar_to_vec and an unaligned_store). For SLP, the vector form
15807 wins if the costs are equal, because of the fact that the vector costs
15808 include constant initializations whereas the scalar costs don't.
15809 We would therefore tend to vectorize the code above, even though
15810 the scalar version can use a single STP.
15812 We should eventually fix this and model LDP and STP in the main costs;
15813 see the comment in aarch64_sve_adjust_stmt_cost for some of the problems.
15814 Until then, we look specifically for code that does nothing more than
15815 STP-like operations. We cost them on that basis in addition to the
15816 normal latency-based costs.
15818 If the scalar or vector code could be a sequence of STPs +
15819 initialization, this variable counts the cost of the sequence,
15820 with 2 units per instruction. The variable is ~0U for other
15821 kinds of code. */
15824 /* On some CPUs, SVE and Advanced SIMD provide the same theoretical vector
15825 throughput, such as 4x128 Advanced SIMD vs. 2x256 SVE. In those
15826 situations, we try to predict whether an Advanced SIMD implementation
15827 of the loop could be completely unrolled and become straight-line code.
15828 If so, it is generally better to use the Advanced SIMD version rather
15829 than length-agnostic SVE, since the SVE loop would execute an unknown
15830 number of times and so could not be completely unrolled in the same way.
15832 If we're applying this heuristic, M_UNROLLED_ADVSIMD_NITERS is the
15833 number of Advanced SIMD loop iterations that would be unrolled and
15834 M_UNROLLED_ADVSIMD_STMTS estimates the total number of statements
15835 in the unrolled loop. Both values are zero if we're not applying
15836 the heuristic. */
15840 /* If we're vectorizing a loop that executes a constant number of times,
15841 this variable gives the number of times that the vector loop would
15842 iterate, otherwise it is zero. */
15845 /* Used only when vectorizing loops. Estimates the number and kind of
15846 operations that would be needed by one iteration of the scalar
15847 or vector loop. There is one entry for each tuning option of
15848 interest. */
15850 };
15857 {
15859 {
15862 {
15865 vf_factor });
15866 }
15867 }
15868 }
15870 /* Implement TARGET_VECTORIZE_CREATE_COSTS. */
15871 vector_costs *
15873 {
15875 }
15877 /* Return true if the current CPU should use the new costs defined
15878 in GCC 11. This should be removed for GCC 12 and above, with the
15879 costs applying to all CPUs instead. */
15880 static bool
15882 {
15885 }
15887 /* Return the appropriate SIMD costs for vectors of type VECTYPE. */
15890 {
15897 }
15899 /* Return the appropriate SIMD costs for vectors with VEC_* flags FLAGS. */
15902 {
15907 }
15909 /* If STMT_INFO is a memory reference, return the scalar memory type,
15910 otherwise return null. */
15911 static tree
15913 {
15917 }
15919 /* Decide whether to use the unrolling heuristic described above
15920 m_unrolled_advsimd_niters, updating that field if so. LOOP_VINFO
15921 describes the loop that we're vectorizing. */
15922 void
15925 {
15926 /* The heuristic only makes sense on targets that have the same
15927 vector throughput for SVE and Advanced SIMD. */
15932 /* We only want to apply the heuristic if LOOP_VINFO is being
15933 vectorized for SVE. */
15937 /* Check whether it is possible in principle to use Advanced SIMD
15938 instead. */
15942 /* We don't want to apply the heuristic to outer loops, since it's
15943 harder to track two levels of unrolling. */
15947 /* Only handle cases in which the number of Advanced SIMD iterations
15948 would be known at compile time but the number of SVE iterations
15949 would not. */
15954 /* Guess how many times the Advanced SIMD loop would iterate and make
15955 sure that it is within the complete unrolling limit. Even if the
15956 number of iterations is small enough, the number of statements might
15957 not be, which is why we need to estimate the number of statements too. */
15960 unsigned HOST_WIDE_INT unrolled_advsimd_niters
15965 /* Record that we're applying the heuristic and should try to estimate
15966 the number of statements in the Advanced SIMD loop. */
15968 }
15970 /* Do one-time initialization of the aarch64_vector_costs given that we're
15971 costing the loop vectorization described by LOOP_VINFO. */
15972 void
15974 {
15975 /* Record the number of times that the vector loop would execute,
15976 if known. */
15980 {
15984 else
15986 }
15988 /* Detect whether we're vectorizing for SVE and should apply the unrolling
15989 heuristic described above m_unrolled_advsimd_niters. */
15992 /* Record the issue information for any SVE WHILE instructions that the
15993 loop needs. */
15995 {
16005 }
16006 }
16008 /* Implement targetm.vectorize.builtin_vectorization_cost. */
16009 static int
16011 tree vectype,
16013 {
16024 {
16077 }
16078 }
16080 /* Return true if an access of kind KIND for STMT_INFO represents one
16081 vector of an LD[234] or ST[234] operation. Return the total number of
16082 vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
16083 static int
16085 {
16091 {
16096 }
16098 }
16100 /* Return true if creating multiple copies of STMT_INFO for Advanced SIMD
16101 vectors would produce a series of LDP or STP operations. KIND is the
16102 kind of statement that STMT_INFO represents. */
16103 static bool
16105 stmt_vec_info stmt_info)
16106 {
16108 {
16117 }
16124 }
16126 /* Return true if STMT_INFO is the second part of a two-statement multiply-add
16127 or multiply-subtract sequence that might be suitable for fusing into a
16128 single instruction. If VEC_FLAGS is zero, analyze the operation as
16129 a scalar one, otherwise analyze it as an operation on vectors with those
16130 VEC_* flags. */
16131 static bool
16134 {
16147 {
16149 /* ??? Should we try to check for a single use as well? */
16162 {
16163 /* Scalar and SVE code can tie the result to any FMLA input (or none,
16164 although that requires a MOVPRFX for SVE). However, Advanced SIMD
16165 only supports MLA forms, so will require a move if the result
16166 cannot be tied to the accumulator. The most important case in
16167 which this is true is when the accumulator input is invariant. */
16175 }
16178 }
16180 }
16182 /* We are considering implementing STMT_INFO using SVE. If STMT_INFO is an
16183 in-loop reduction that SVE supports directly, return its latency in cycles,
16184 otherwise return zero. SVE_COSTS specifies the latencies of the relevant
16185 instructions. */
16186 static unsigned int
16188 stmt_vec_info stmt_info,
16190 {
16192 {
16198 {
16211 }
16213 }
16216 }
16218 /* STMT_INFO describes a loop-carried operation in the original scalar code
16219 that we are considering implementing as a reduction. Return one of the
16220 following values, depending on VEC_FLAGS:
16222 - If VEC_FLAGS is zero, return the loop carry latency of the original
16223 scalar operation.
16225 - If VEC_FLAGS & VEC_ADVSIMD, return the loop carry latency of the
16226 Advanced SIMD implementation.
16228 - If VEC_FLAGS & VEC_ANY_SVE, return the loop carry latency of the
16229 SVE implementation. */
16230 static unsigned int
16233 {
16239 /* If the caller is asking for the SVE latency, check for forms of reduction
16240 that only SVE can handle directly. */
16242 {
16243 unsigned int latency
16247 }
16249 /* Handle scalar costs. */
16252 {
16256 }
16258 /* Otherwise, the loop body just contains normal integer or FP operations,
16259 with a vector reduction outside the loop. */
16265 }
16267 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16268 for STMT_INFO, which has cost kind KIND. If this is a scalar operation,
16269 try to subdivide the target-independent categorization provided by KIND
16270 to get a more accurate cost. */
16271 static fractional_cost
16273 stmt_vec_info stmt_info,
16274 fractional_cost stmt_cost)
16275 {
16276 /* Detect an extension of a loaded value. In general, we'll be able to fuse
16277 the extension with the load. */
16282 }
16284 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16285 for the vectorized form of STMT_INFO, which has cost kind KIND and which
16286 when vectorized would operate on vector type VECTYPE. Try to subdivide
16287 the target-independent categorization provided by KIND to get a more
16288 accurate cost. WHERE specifies where the cost associated with KIND
16289 occurs. */
16290 static fractional_cost
16294 fractional_cost stmt_cost)
16295 {
16301 /* It's generally better to avoid costing inductions, since the induction
16302 will usually be hidden by other operations. This is particularly true
16303 for things like COND_REDUCTIONS. */
16307 /* Detect cases in which vec_to_scalar is describing the extraction of a
16308 vector element in preparation for a scalar store. The store itself is
16309 costed separately. */
16313 /* Detect SVE gather loads, which are costed as a single scalar_load
16314 for each element. We therefore need to divide the full-instruction
16315 cost by the number of elements in the vector. */
16317 && sve_costs
16319 {
16324 }
16326 /* Detect cases in which a scalar_store is really storing one element
16327 in a scatter operation. */
16329 && sve_costs
16333 /* Detect cases in which vec_to_scalar represents an in-loop reduction. */
16337 {
16338 unsigned int latency
16342 }
16344 /* Detect cases in which vec_to_scalar represents a single reduction
16345 instruction like FADDP or MAXV. */
16350 {
16375 }
16377 /* Otherwise stick with the original categorization. */
16379 }
16381 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16382 for STMT_INFO, which has cost kind KIND and which when vectorized would
16383 operate on vector type VECTYPE. Adjust the cost as necessary for SVE
16384 targets. */
16385 static fractional_cost
16388 fractional_cost stmt_cost)
16389 {
16390 /* Unlike vec_promote_demote, vector_stmt conversions do not change the
16391 vector register size or number of units. Integer promotions of this
16392 type therefore map to SXT[BHW] or UXT[BHW].
16394 Most loads have extending forms that can do the sign or zero extension
16395 on the fly. Optimistically assume that a load followed by an extension
16396 will fold to this form during combine, and that the extension therefore
16397 comes for free. */
16401 /* For similar reasons, vector_stmt integer truncations are a no-op,
16402 because we can just ignore the unused upper bits of the source. */
16406 /* Advanced SIMD can load and store pairs of registers using LDP and STP,
16407 but there are no equivalent instructions for SVE. This means that
16408 (all other things being equal) 128-bit SVE needs twice as many load
16409 and store instructions as Advanced SIMD in order to process vector pairs.
16411 Also, scalar code can often use LDP and STP to access pairs of values,
16412 so it is too simplistic to say that one SVE load or store replaces
16413 VF scalar loads and stores.
16415 Ideally we would account for this in the scalar and Advanced SIMD
16416 costs by making suitable load/store pairs as cheap as a single
16417 load/store. However, that would be a very invasive change and in
16418 practice it tends to stress other parts of the cost model too much.
16419 E.g. stores of scalar constants currently count just a store,
16420 whereas stores of vector constants count a store and a vec_init.
16421 This is an artificial distinction for AArch64, where stores of
16422 nonzero scalar constants need the same kind of register invariant
16423 as vector stores.
16425 An alternative would be to double the cost of any SVE loads and stores
16426 that could be paired in Advanced SIMD (and possibly also paired in
16427 scalar code). But this tends to stress other parts of the cost model
16428 in the same way. It also means that we can fall back to Advanced SIMD
16429 even if full-loop predication would have been useful.
16431 Here we go for a more conservative version: double the costs of SVE
16432 loads and stores if one iteration of the scalar loop processes enough
16433 elements for it to use a whole number of Advanced SIMD LDP or STP
16434 instructions. This makes it very likely that the VF would be 1 for
16435 Advanced SIMD, and so no epilogue should be needed. */
16437 {
16444 }
16447 }
16449 /* STMT_COST is the cost calculated for STMT_INFO, which has cost kind KIND
16450 and which when vectorized would operate on vector type VECTYPE. Add the
16451 cost of any embedded operations. */
16452 static fractional_cost
16455 {
16457 {
16460 /* Detect cases in which a vector load or store represents an
16461 LD[234] or ST[234] instruction. */
16463 {
16475 }
16479 {
16482 else
16484 }
16485 }
16489 {
16492 else
16494 }
16497 }
16499 /* COUNT, KIND and STMT_INFO are the same as for vector_costs::add_stmt_cost
16500 and they describe an operation in the body of a vector loop. Record issue
16501 information relating to the vector operation in OPS. */
16502 void
16504 stmt_vec_info stmt_info,
16506 {
16513 /* Calculate the minimum cycles per iteration imposed by a reduction
16514 operation. */
16517 {
16518 unsigned int base
16521 /* ??? Ideally we'd do COUNT reductions in parallel, but unfortunately
16522 that's not yet the case. */
16524 }
16526 /* Assume that multiply-adds will become a single operation. */
16530 /* Count the basic operation cost associated with KIND. */
16532 {
16537 /* We currently don't expect these to be used in a loop body. */
16565 }
16567 /* Add any embedded comparison operations. */
16572 /* COND_REDUCTIONS need two sets of VEC_COND_EXPRs, whereas so far we
16573 have only accounted for one. */
16578 /* Count the predicate operations needed by an SVE comparison. */
16581 {
16586 }
16588 /* Add any extra overhead associated with LD[234] and ST[234] operations. */
16591 {
16603 }
16605 /* Add any overhead associated with gather loads and scatter stores. */
16609 {
16613 }
16614 }
16616 /* Return true if STMT_INFO contains a memory access and if the constant
16617 component of the memory address is aligned to SIZE bytes. */
16618 static bool
16620 poly_uint64 size)
16621 {
16628 /* Needed for gathers & scatters, for example. */
16633 }
16635 /* Check if a scalar or vector stmt could be part of a region of code
16636 that does nothing more than store values to memory, in the scalar
16637 case using STP. Return the cost of the stmt if so, counting 2 for
16638 one instruction. Return ~0U otherwise.
16640 The arguments are a subset of those passed to add_stmt_cost. */
16641 unsigned int
16644 {
16645 /* Code that stores vector constants uses a vector_load to create
16646 the constant. We don't apply the heuristic to that case for two
16647 main reasons:
16649 - At the moment, STPs are only formed via peephole2, and the
16650 constant scalar moves would often come between STRs and so
16651 prevent STP formation.
16653 - The scalar code also has to load the constant somehow, and that
16654 isn't costed. */
16656 {
16658 /* Count 2 insns for a GPR->SIMD dup and 1 insn for a FPR->SIMD dup. */
16663 /* Count 1 insn for the maximum number of FP->SIMD INS
16664 instructions. */
16667 /* Count 2 insns for a GPR->SIMD move and 2 insns for the
16668 maximum number of GPR->SIMD INS instructions. */
16673 /* Count 1 insn per vector if we can't form STP Q pairs. */
16681 {
16682 /* Assume we won't be able to use STP if the constant offset
16683 component of the address is misaligned. ??? This could be
16684 removed if we formed STP pairs earlier, rather than relying
16685 on peephole2. */
16689 }
16694 {
16695 /* Check for a mode in which STP pairs can be formed. */
16700 /* Assume we won't be able to use STP if the constant offset
16701 component of the address is misaligned. ??? This could be
16702 removed if we formed STP pairs earlier, rather than relying
16703 on peephole2. */
16706 }
16711 }
16712 }
16714 unsigned
16718 vect_cost_model_location where)
16719 {
16720 fractional_cost stmt_cost
16724 && stmt_info
16727 /* Do one-time initialization based on the vinfo. */
16730 {
16735 }
16737 /* Apply the heuristic described above m_stp_sequence_cost. */
16739 {
16743 }
16745 /* Try to get a more accurate cost by looking at STMT_INFO instead
16746 of just looking at KIND. */
16748 {
16749 /* If we scalarize a strided store, the vectorizer costs one
16750 vec_to_scalar for each element. However, we can store the first
16751 element using an FP store without a separate extract step. */
16762 }
16764 /* Do any SVE-specific adjustments to the cost. */
16770 {
16771 /* Account for any extra "embedded" costs that apply additively
16772 to the base cost calculated above. */
16774 stmt_cost);
16776 /* If we're recording a nonzero vector loop body cost for the
16777 innermost loop, also estimate the operations that would need
16778 to be issued by all relevant implementations of the loop. */
16786 /* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
16787 estimate the number of statements in the unrolled Advanced SIMD
16788 loop. For simplicitly, we assume that one iteration of the
16789 Advanced SIMD loop would need the same number of statements
16790 as one iteration of the SVE loop. */
16794 /* Detect the use of an averaging operation. */
16798 {
16800 {
16806 }
16807 }
16808 }
16810 }
16812 /* Return true if (a) we're applying the Advanced SIMD vs. SVE unrolling
16813 heuristic described above m_unrolled_advsimd_niters and (b) the heuristic
16814 says that we should prefer the Advanced SIMD loop. */
16815 bool
16817 {
16823 " unrolled Advanced SIMD loop = "
16825 m_unrolled_advsimd_stmts);
16827 /* The balance here is tricky. On the one hand, we can't be sure whether
16828 the code is vectorizable with Advanced SIMD or not. However, even if
16829 it isn't vectorizable with Advanced SIMD, there's a possibility that
16830 the scalar code could also be unrolled. Some of the code might then
16831 benefit from SLP, or from using LDP and STP. We therefore apply
16832 the heuristic regardless of can_use_advsimd_p. */
16834 && (m_unrolled_advsimd_stmts
16836 }
16838 /* Subroutine of adjust_body_cost for handling SVE. Use ISSUE_INFO to work out
16839 how fast the SVE code can be issued and compare it to the equivalent value
16840 for scalar code (SCALAR_CYCLES_PER_ITER). If COULD_USE_ADVSIMD is true,
16841 also compare it to the issue rate of Advanced SIMD code
16842 (ADVSIMD_CYCLES_PER_ITER).
16844 ORIG_BODY_COST is the cost originally passed to adjust_body_cost and
16845 *BODY_COST is the current value of the adjusted cost. *SHOULD_DISPARAGE
16846 is true if we think the loop body is too expensive. */
16848 fractional_cost
16851 fractional_cost scalar_cycles_per_iter,
16854 {
16861 /* If the scalar version of the loop could issue at least as
16862 quickly as the predicate parts of the SVE loop, make the SVE loop
16863 prohibitively expensive. In this case vectorization is adding an
16864 overhead that the original scalar code didn't have.
16866 This is mostly intended to detect cases in which WHILELOs dominate
16867 for very tight loops, which is something that normal latency-based
16868 costs would not model. Adding this kind of cliffedge would be
16869 too drastic for scalar_cycles_per_iter vs. sve_cycles_per_iter;
16870 code in the caller handles that case in a more conservative way. */
16873 {
16874 unsigned int min_cost
16877 {
16880 "Increasing body cost to %d because the"
16881 " scalar code could issue within the limit"
16883 min_cost);
16886 }
16887 }
16890 }
16892 unsigned int
16894 {
16896 /* If we are trying to unroll an Advanced SIMD main loop that contains
16897 an averaging operation that we do not support with SVE and we might use a
16898 predicated epilogue, we need to be conservative and block unrolling as
16899 this might lead to a less optimal loop for the first and only epilogue
16900 using the original loop's vectorization factor.
16901 TODO: Remove this constraint when we add support for multiple epilogue
16902 vectorization. */
16908 {
16913 /* Limit unroll factor to a value adjustable by the user, the default
16914 value is 4. */
16916 unsigned int factor
16920 /* Sanity check, this should never happen. */
16924 /* Check stores. */
16926 {
16930 }
16932 /* Check loads + stores. */
16934 {
16938 }
16940 /* Check general ops. */
16942 {
16946 }
16948 }
16950 /* Make sure unroll factor is power of 2. */
16952 }
16954 /* BODY_COST is the cost of a vector loop body. Adjust the cost as necessary
16955 and return the new cost. */
16956 unsigned int
16961 {
16975 fractional_cost scalar_cycles_per_iter
16981 {
16985 m_num_vector_iterations);
16989 " estimated cycles per vector iteration"
16992 }
16995 {
16998 vector_cycles_per_iter
17003 {
17004 /* Also take Neoverse V1 tuning into account, doubling the
17005 scalar and Advanced SIMD estimates to account for the
17006 doubling in SVE vector length. */
17013 }
17014 }
17015 else
17016 {
17018 {
17022 }
17023 }
17025 /* Decide whether to stick to latency-based costs or whether to try to
17026 take issue rates into account. */
17033 {
17036 "Low iteration count, so using pure latency"
17038 }
17039 /* Increase the cost of the vector code if it looks like the scalar code
17040 could issue more quickly. These values are only rough estimates,
17041 so minor differences should only result in minor changes. */
17043 {
17045 scalar_cycles_per_iter);
17048 "Increasing body cost to %d because scalar code"
17050 }
17051 /* In general, it's expected that the proposed vector code would be able
17052 to issue more quickly than the original scalar code. This should
17053 already be reflected to some extent in the latency-based costs.
17055 However, the latency-based costs effectively assume that the scalar
17056 code and the vector code execute serially, which tends to underplay
17057 one important case: if the real (non-serialized) execution time of
17058 a scalar iteration is dominated by loop-carried dependencies,
17059 and if the vector code is able to reduce both the length of
17060 the loop-carried dependencies *and* the number of cycles needed
17061 to issue the code in general, we can be more confident that the
17062 vector code is an improvement, even if adding the other (non-loop-carried)
17063 latencies tends to hide this saving. We therefore reduce the cost of the
17064 vector loop body in proportion to the saving. */
17069 {
17071 scalar_cycles_per_iter);
17074 "Decreasing body cost to %d account for smaller"
17076 }
17079 }
17081 void
17083 {
17088 && m_vec_flags
17090 {
17094 }
17096 /* Apply the heuristic described above m_stp_sequence_cost. Prefer
17097 the scalar code in the event of a tie, since there is more chance
17098 of scalar code being optimized with surrounding operations. */
17100 && scalar_costs
17106 }
17108 bool
17111 {
17125 /* Apply the unrolling heuristic described above
17126 m_unrolled_advsimd_niters. */
17129 {
17133 {
17136 "Preferring Advanced SIMD loop because"
17139 }
17140 }
17143 {
17145 {
17157 }
17164 /* If it appears that one loop could process the same amount of data
17165 in fewer cycles, prefer that loop over the other one. */
17166 fractional_cost this_cost
17168 fractional_cost other_cost
17171 {
17180 }
17182 {
17185 "Preferring loop with lower cycles"
17188 }
17190 /* If the issue rate of SVE code is limited by predicate operations
17191 (i.e. if sve_pred_cycles_per_iter > sve_nonpred_cycles_per_iter),
17192 and if Advanced SIMD code could issue within the limit imposed
17193 by the predicate operations, the predicate operations are adding an
17194 overhead that the original code didn't have and so we should prefer
17195 the Advanced SIMD version. */
17198 {
17202 {
17205 "Preferring Advanced SIMD loop since"
17208 }
17210 };
17215 }
17218 }
17222 /* Parse the TO_PARSE string and put the architecture struct that it
17223 selects into RES and the architectural features into ISA_FLAGS.
17224 Return an aarch64_parse_opt_result describing the parse result.
17225 If there is an error parsing, RES and ISA_FLAGS are left unchanged.
17226 When the TO_PARSE string contains an invalid extension,
17227 a copy of the string is created and stored to INVALID_EXTENSION. */
17229 static enum aarch64_parse_opt_result
17233 {
17242 else
17249 /* Loop through the list of supported ARCHes to find a match. */
17251 {
17254 {
17258 {
17259 /* TO_PARSE string contains at least one extension. */
17260 enum aarch64_parse_opt_result ext_res
17265 }
17266 /* Extension parsing was successful. Confirm the result
17267 arch and ISA flags. */
17271 }
17272 }
17274 /* ARCH name not found in list. */
17276 }
17278 /* Parse the TO_PARSE string and put the result tuning in RES and the
17279 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
17280 describing the parse result. If there is an error parsing, RES and
17281 ISA_FLAGS are left unchanged.
17282 When the TO_PARSE string contains an invalid extension,
17283 a copy of the string is created and stored to INVALID_EXTENSION. */
17285 static enum aarch64_parse_opt_result
17289 {
17298 else
17305 /* Loop through the list of supported CPUs to find a match. */
17307 {
17309 {
17313 {
17314 /* TO_PARSE string contains at least one extension. */
17315 enum aarch64_parse_opt_result ext_res
17320 }
17321 /* Extension parsing was successfull. Confirm the result
17322 cpu and ISA flags. */
17326 }
17327 }
17329 /* CPU name not found in list. */
17331 }
17333 /* Parse the TO_PARSE string and put the cpu it selects into RES.
17334 Return an aarch64_parse_opt_result describing the parse result.
17335 If the parsing fails the RES does not change. */
17337 static enum aarch64_parse_opt_result
17339 {
17342 /* Loop through the list of supported CPUs to find a match. */
17344 {
17346 {
17349 }
17350 }
17352 /* CPU name not found in list. */
17354 }
17356 /* Parse TOKEN, which has length LENGTH to see if it is an option
17357 described in FLAG. If it is, return the index bit for that fusion type.
17358 If not, error (printing OPTION_NAME) and return zero. */
17360 static unsigned int
17365 {
17367 {
17371 }
17375 }
17377 /* Parse OPTION which is a comma-separated list of flags to enable.
17378 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
17379 default state we inherit from the CPU tuning structures. OPTION_NAME
17380 gives the top-level option we are parsing in the -moverride string,
17381 for use in error messages. */
17383 static unsigned int
17388 {
17395 {
17398 token_length,
17399 flags,
17400 option_name);
17401 /* If we find "none" (or, for simplicity's sake, an error) anywhere
17402 in the token stream, reset the supported operations. So:
17404 adrp+add.cmp+branch.none.adrp+add
17406 would have the result of turning on only adrp+add fusion. */
17412 }
17414 /* We ended with a comma, print something. */
17416 {
17419 }
17421 /* We still have one more token to parse. */
17424 token_length,
17425 flags,
17426 option_name);
17432 }
17434 /* Support for overriding instruction fusion. */
17436 static void
17439 {
17441 aarch64_fusible_pairs,
17444 }
17446 /* Support for overriding other tuning flags. */
17448 static void
17451 {
17452 tune->extra_tuning_flags
17454 aarch64_tuning_flags,
17457 }
17459 /* Parse the sve_width tuning moverride string in TUNE_STRING.
17460 Accept the valid SVE vector widths allowed by
17461 aarch64_sve_vector_bits_enum and use it to override sve_width
17462 in TUNE. */
17464 static void
17467 {
17472 {
17475 }
17477 {
17486 }
17488 }
17490 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
17491 we understand. If it is, extract the option string and handoff to
17492 the appropriate function. */
17494 void
17498 {
17504 {
17507 }
17509 /* Get the length of the option name. */
17511 /* Skip the '=' to get to the option string. */
17512 option_part++;
17515 {
17517 {
17520 }
17521 }
17525 }
17527 /* A checking mechanism for the implementation of the tls size. */
17529 static void
17531 {
17536 {
17538 /* Both the default and maximum TLS size allowed under tiny is 1M which
17539 needs two instructions to address, so we clamp the size to 24. */
17544 /* The maximum TLS size allowed under small is 4G. */
17549 /* The maximum TLS size allowed under large is 16E.
17550 FIXME: 16E should be 64bit, we only support 48bit offset now. */
17556 }
17559 }
17561 /* Return the CPU corresponding to the enum CPU. */
17565 {
17569 }
17571 /* Return the architecture corresponding to the enum ARCH. */
17575 {
17579 }
17581 /* Parse STRING looking for options in the format:
17582 string :: option:string
17583 option :: name=substring
17584 name :: {a-z}
17585 substring :: defined by option. */
17587 static void
17590 {
17601 {
17603 /* Make this substring look like a string. */
17607 }
17609 /* One last option to parse. */
17612 }
17614 /* Adjust CURRENT_TUNE (a generic tuning struct) with settings that
17615 are best for a generic target with the currently-enabled architecture
17616 extensions. */
17617 static void
17619 {
17620 /* Neoverse V1 is the only core that is known to benefit from
17621 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no
17622 point enabling it for SVE2 and above. */
17624 current_tune.extra_tuning_flags
17626 }
17628 static void
17630 {
17632 {
17633 opts->x_aarch64_branch_protection_string
17635 }
17637 /* PR 70044: We have to be careful about being called multiple times for the
17638 same function. This means all changes should be repeatable. */
17640 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
17641 Disable the frame pointer flag so the mid-end will not use a frame
17642 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
17643 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
17644 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
17649 /* If not optimizing for size, set the default
17650 alignment to what the target wants. */
17652 {
17659 }
17661 /* We default to no pc-relative literal loads. */
17665 /* If -mpc-relative-literal-loads is set on the command line, this
17666 implies that the user asked for PC relative literal loads. */
17670 /* In the tiny memory model it makes no sense to disallow PC relative
17671 literal pool loads. */
17676 /* When enabling the lower precision Newton series for the square root, also
17677 enable it for the reciprocal square root, since the latter is an
17678 intermediary step for the former. */
17681 }
17683 /* 'Unpack' up the internal tuning structs and update the options
17684 in OPTS. The caller must have set up selected_tune and selected_arch
17685 as all the other target-specific codegen decisions are
17686 derived from them. */
17688 void
17690 {
17694 /* Make a copy of the tuning parameters attached to the core, which
17695 we may later overwrite. */
17704 /* This target defaults to strict volatile bitfields. */
17710 {
17713 aarch64_stack_protector_guard_offset_str);
17714 }
17719 {
17721 "%<-mstack-protector-guard-reg%> must be used "
17723 }
17726 {
17729 }
17732 {
17741 }
17752 {
17764 }
17766 /* We don't mind passing in global_options_set here as we don't use
17767 the *options_set structs anyway. */
17771 /* If using Advanced SIMD only for autovectorization disable SVE vector costs
17772 comparison. */
17777 /* Set up parameters to be used in prefetching algorithm. Do not
17778 override the defaults unless we are tuning for a core we have
17779 researched values for. */
17782 param_simultaneous_prefetches,
17786 param_l1_cache_size,
17790 param_l1_cache_line_size,
17794 {
17796 param_destruct_interfere_size,
17799 param_construct_interfere_size,
17801 }
17802 else
17803 {
17804 /* For a generic AArch64 target, cover the current range of cache line
17805 sizes. */
17807 param_destruct_interfere_size,
17810 param_construct_interfere_size,
17812 }
17816 param_l2_cache_size,
17823 param_prefetch_minimum_stride,
17826 /* Use the alternative scheduling-pressure algorithm by default. */
17828 param_sched_pressure_algorithm,
17829 SCHED_PRESSURE_MODEL);
17831 /* Validate the guard size. */
17839 /* Enforce that interval is the same size as size so the mid-end does the
17840 right thing. */
17842 param_stack_clash_protection_probe_interval,
17843 guard_size);
17845 /* The maybe_set calls won't update the value if the user has explicitly set
17846 one. Which means we need to validate that probing interval and guard size
17847 are equal. */
17848 int probe_interval
17854 /* Enable sw prefetching at specified optimization level for
17855 CPUS that have prefetch. Lower optimization level threshold by 1
17856 when profiling is enabled. */
17864 }
17866 /* Print a hint with a suggestion for a core or architecture name that
17867 most closely resembles what the user passed in STR. ARCH is true if
17868 the user is asking for an architecture name. ARCH is false if the user
17869 is asking for a core name. */
17871 static void
17873 {
17879 #ifdef HAVE_LOCAL_CPU_DETECT
17880 /* Add also "native" as possible value. */
17883 #endif
17890 else
17894 }
17896 /* Print a hint with a suggestion for a core name that most closely resembles
17897 what the user passed in STR. */
17901 {
17903 }
17905 /* Print a hint with a suggestion for an architecture name that most closely
17906 resembles what the user passed in STR. */
17910 {
17912 }
17915 /* Print a hint with a suggestion for an extension name
17916 that most closely resembles what the user passed in STR. */
17918 void
17920 {
17928 else
17932 }
17934 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
17935 specified in STR and throw errors if appropriate. Put the results if
17936 they are valid in RES and ISA_FLAGS. Return whether the option is
17937 valid. */
17939 static bool
17942 {
17944 enum aarch64_parse_opt_result parse_res
17951 {
17966 }
17969 }
17971 /* Straight line speculation indicators. */
17972 enum aarch64_sls_hardening_type
17973 {
17978 };
17981 /* Return whether we should mitigatate Straight Line Speculation for the RET
17982 and BR instructions. */
17983 bool
17985 {
17987 }
17989 /* Return whether we should mitigatate Straight Line Speculation for the BLR
17990 instruction. */
17991 bool
17993 {
17995 }
17997 /* As of yet we only allow setting these options globally, in the future we may
17998 allow setting them per function. */
17999 static void
18001 {
18006 {
18009 }
18011 {
18014 }
18023 {
18029 {
18032 }
18033 else
18034 {
18037 }
18039 }
18042 }
18044 /* Parses CONST_STR for branch protection features specified in
18045 aarch64_branch_protect_types, and set any global variables required. Returns
18046 the parsing result and assigns LAST_STR to the last processed token from
18047 CONST_STR so that it can be used for error reporting. */
18049 static enum
18052 {
18059 else
18060 {
18062 /* Reset the branch protection features to their defaults. */
18066 {
18069 /* Search for this type. */
18071 {
18073 {
18078 }
18079 else
18080 type++;
18081 }
18083 {
18085 /* Loop through each token until we find one that isn't a
18086 subtype. */
18088 {
18091 /* Search for the subtype. */
18094 {
18096 {
18101 }
18102 else
18103 subtype++;
18104 }
18105 }
18106 }
18109 }
18110 }
18111 /* Copy the last processed token into the argument to pass it back.
18112 Used by option and attribute validation to print the offending token. */
18114 {
18117 }
18119 {
18120 /* If needed, alloc the accepted string then copy in const_str.
18121 Used by override_option_after_change_1. */
18124 BRANCH_PROTECT_STR_MAX
18128 /* Forcibly null-terminate. */
18130 }
18132 }
18134 static bool
18136 {
18146 }
18148 /* Validate a command-line -march option. Parse the arch and extensions
18149 (if any) specified in STR and throw errors if appropriate. Put the
18150 results, if they are valid, in RES and ISA_FLAGS. Return whether the
18151 option is valid. */
18153 static bool
18156 {
18158 enum aarch64_parse_opt_result parse_res
18165 {
18172 /* A common user error is confusing -march and -mcpu.
18173 If the -march string matches a known CPU suggest -mcpu. */
18185 }
18188 }
18190 /* Validate a command-line -mtune option. Parse the cpu
18191 specified in STR and throw errors if appropriate. Put the
18192 result, if it is valid, in RES. Return whether the option is
18193 valid. */
18195 static bool
18197 {
18198 enum aarch64_parse_opt_result parse_res
18205 {
18215 }
18217 }
18219 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
18221 static poly_uint16
18223 {
18224 /* 128-bit SVE and Advanced SIMD modes use different register layouts
18225 on big-endian targets, so we would need to forbid subregs that convert
18226 from one to the other. By default a reinterpret sequence would then
18227 involve a store to memory in one mode and a load back in the other.
18228 Even if we optimize that sequence using reverse instructions,
18229 it would still be a significant potential overhead.
18231 For now, it seems better to generate length-agnostic code for that
18232 case instead. */
18236 else
18238 }
18240 /* Set the global aarch64_asm_isa_flags to FLAGS and update
18241 aarch64_isa_flags accordingly. */
18243 void
18245 {
18247 }
18249 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
18250 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
18251 tuning structs. In particular it must set selected_tune and
18252 aarch64_asm_isa_flags that define the available ISA features and tuning
18253 decisions. It must also set selected_arch as this will be used to
18254 output the .arch asm tags for each function. */
18256 static void
18258 {
18273 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
18274 If either of -march or -mtune is given, they override their
18275 respective component of -mcpu. */
18285 #ifdef SUBTARGET_OVERRIDE_OPTIONS
18286 SUBTARGET_OVERRIDE_OPTIONS;
18287 #endif
18290 {
18291 /* If both -mcpu and -march are specified, warn if they are not
18292 architecturally compatible and prefer the -march ISA flags. */
18294 {
18296 aarch64_cpu_string,
18297 aarch64_arch_string);
18298 }
18302 }
18304 {
18307 }
18309 {
18313 }
18314 else
18315 {
18316 /* No -mcpu or -march specified, so use the default CPU. */
18320 }
18325 {
18326 #ifdef TARGET_ENABLE_BTI
18328 #else
18330 #endif
18331 }
18333 /* Return address signing is currently not supported for ILP32 targets. For
18334 LP64 targets use the configured option in the absence of a command-line
18335 option for -mbranch-protection. */
18337 {
18338 #ifdef TARGET_ENABLE_PAC_RET
18340 #else
18342 #endif
18343 }
18345 #ifndef HAVE_AS_MABI_OPTION
18346 /* The compiler may have been configured with 2.23.* binutils, which does
18347 not have support for ILP32. */
18350 #endif
18352 /* Convert -msve-vector-bits to a VG count. */
18358 /* The pass to insert speculation tracking runs before
18359 shrink-wrapping and the latter does not know how to update the
18360 tracking status. So disable it in this case. */
18366 /* Save these options as the default ones in case we push and pop them later
18367 while processing functions with potential target attributes. */
18368 target_option_default_node = target_option_current_node
18370 }
18372 /* Implement targetm.override_options_after_change. */
18374 static void
18376 {
18378 }
18380 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
18383 {
18386 else
18388 }
18392 {
18396 }
18398 void
18400 {
18402 }
18404 /* A checking mechanism for the implementation of the various code models. */
18405 static void
18407 {
18410 {
18417 {
18418 #ifdef HAVE_AS_SMALL_PIC_RELOCS
18420 ? AARCH64_CMODEL_SMALL_PIC
18422 #else
18424 #endif
18425 }
18438 }
18439 }
18441 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
18442 using the information saved in PTR. */
18444 static void
18448 {
18450 }
18452 /* Implement TARGET_OPTION_PRINT. */
18454 static void
18456 {
18467 }
18471 void
18473 {
18475 }
18477 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
18478 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
18479 make sure optab availability predicates are recomputed when necessary. */
18481 void
18483 {
18488 else
18490 }
18492 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
18493 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
18494 of the function, if such exists. This function may be called multiple
18495 times on a single function so use aarch64_previous_fndecl to avoid
18496 setting up identical state. */
18498 static void
18500 {
18504 tree old_tree = (aarch64_previous_fndecl
18510 /* If current function has no attributes but the previous one did,
18511 use the default node. */
18515 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
18516 the default have been handled by aarch64_save_restore_target_globals from
18517 aarch64_pragma_target_parse. */
18523 /* First set the target options. */
18528 }
18530 /* Enum describing the various ways we can handle attributes.
18531 In many cases we can reuse the generic option handling machinery. */
18533 enum aarch64_attr_opt_type
18534 {
18538 aarch64_attr_custom /* Attribute requires a custom handling function. */
18539 };
18541 /* All the information needed to handle a target attribute.
18542 NAME is the name of the attribute.
18543 ATTR_TYPE specifies the type of behavior of the attribute as described
18544 in the definition of enum aarch64_attr_opt_type.
18545 ALLOW_NEG is true if the attribute supports a "no-" form.
18546 HANDLER is the function that takes the attribute string as an argument
18547 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
18548 OPT_NUM is the enum specifying the option that the attribute modifies.
18549 This is needed for attributes that mirror the behavior of a command-line
18550 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
18551 aarch64_attr_enum. */
18553 struct aarch64_attribute_info
18554 {
18560 };
18562 /* Handle the ARCH_STR argument to the arch= target attribute. */
18564 static bool
18566 {
18569 aarch64_feature_flags tmp_flags;
18570 enum aarch64_parse_opt_result parse_res
18574 {
18579 }
18582 {
18597 }
18600 }
18602 /* Handle the argument CPU_STR to the cpu= target attribute. */
18604 static bool
18606 {
18609 aarch64_feature_flags tmp_flags;
18610 enum aarch64_parse_opt_result parse_res
18614 {
18620 }
18623 {
18638 }
18641 }
18643 /* Handle the argument STR to the branch-protection= attribute. */
18645 static bool
18647 {
18653 {
18664 /* Fall through. */
18669 }
18672 }
18674 /* Handle the argument STR to the tune= target attribute. */
18676 static bool
18678 {
18680 enum aarch64_parse_opt_result parse_res
18684 {
18688 }
18691 {
18698 }
18701 }
18703 /* Parse an architecture extensions target attribute string specified in STR.
18704 For example "+fp+nosimd". Show any errors if needed. Return TRUE
18705 if successful. Update aarch64_isa_flags to reflect the ISA features
18706 modified. */
18708 static bool
18710 {
18714 /* We allow "+nothing" in the beginning to clear out all architectural
18715 features if the user wants to handpick specific features. */
18717 {
18720 }
18726 {
18729 }
18732 {
18744 }
18747 }
18749 /* The target attributes that we support. On top of these we also support just
18750 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
18751 handled explicitly in aarch64_process_one_target_attr. */
18754 {
18756 OPT_mgeneral_regs_only },
18758 OPT_mfix_cortex_a53_835769 },
18760 OPT_mfix_cortex_a53_843419 },
18764 OPT_momit_leaf_frame_pointer },
18767 OPT_march_ },
18770 OPT_mtune_ },
18774 OPT_msign_return_address_ },
18776 OPT_moutline_atomics},
18778 };
18780 /* Parse ARG_STR which contains the definition of one target attribute.
18781 Show appropriate errors if any or return true if the attribute is valid. */
18783 static bool
18785 {
18791 {
18794 }
18799 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
18800 It is easier to detect and handle it explicitly here rather than going
18801 through the machinery for the rest of the target attributes in this
18802 function. */
18807 {
18810 }
18813 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
18814 and point ARG to "foo". */
18816 {
18818 arg++;
18819 }
18823 {
18824 /* If the names don't match up, or the user has given an argument
18825 to an attribute that doesn't accept one, or didn't give an argument
18826 to an attribute that expects one, fail to match. */
18835 {
18838 }
18840 /* If the name matches but the attribute does not allow "no-" versions
18841 then we can't match. */
18843 {
18846 }
18849 {
18850 /* Has a custom handler registered.
18851 For example, cpu=, arch=, tune=. */
18858 /* Either set or unset a boolean option. */
18860 {
18868 }
18869 /* Set or unset a bit in the target_flags. aarch64_handle_option
18870 should know what mask to apply given the option number. */
18872 {
18874 /* We only need to specify the option number.
18875 aarch64_handle_option will know which mask to apply. */
18881 }
18882 /* Use the option setting machinery to set an option to an enum. */
18884 {
18891 {
18894 global_dc);
18895 }
18896 else
18897 {
18899 }
18901 }
18904 }
18905 }
18907 /* If we reached here we either have found an attribute and validated
18908 it or didn't match any. If we matched an attribute but its arguments
18909 were malformed we will have returned false already. */
18911 }
18913 /* Count how many times the character C appears in
18914 NULL-terminated string STR. */
18916 static unsigned int
18918 {
18921 {
18923 res++;
18925 str++;
18926 }
18929 }
18931 /* Parse the tree in ARGS that contains the target attribute information
18932 and update the global target options space. */
18934 bool
18936 {
18938 {
18939 do
18940 {
18943 {
18946 }
18951 }
18954 {
18957 }
18964 {
18967 }
18969 /* Used to catch empty spaces between commas i.e.
18970 attribute ((target ("attr1,,attr2"))). */
18973 /* Handle multiple target attributes separated by ','. */
18978 {
18979 num_attrs++;
18981 {
18982 /* Check if token is possibly an arch extension without
18983 leading '+'. */
18986 enum aarch64_parse_opt_result ext_res
18991 token);
18992 else
18995 }
18998 }
19001 {
19004 }
19007 }
19009 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
19010 process attribute ((target ("..."))). */
19012 static bool
19014 {
19017 tree old_optimize;
19021 /* If what we're processing is the current pragma string then the
19022 target option node is already stored in target_option_current_node
19023 by aarch64_pragma_target_parse in aarch64-c.cc. Use that to avoid
19024 having to re-parse the string. This is especially useful to keep
19025 arm_neon.h compile times down since that header contains a lot
19026 of intrinsics enclosed in pragmas. */
19028 {
19031 }
19034 old_optimize
19038 /* If the function changed the optimization levels as well as setting
19039 target options, start with the optimizations specified. */
19044 /* Save the current target options to restore at the end. */
19047 /* If fndecl already has some target attributes applied to it, unpack
19048 them so that we add this attribute on top of them, rather than
19049 overwriting them. */
19051 {
19057 existing_options);
19058 }
19059 else
19065 /* Set up any additional state. */
19067 {
19071 }
19072 else
19079 {
19084 }
19092 }
19094 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
19095 tri-bool options (yes, no, don't care) and the default value is
19096 DEF, determine whether to reject inlining. */
19098 static bool
19101 {
19102 /* If the callee doesn't care, always allow inlining. */
19106 /* If the caller doesn't care, always allow inlining. */
19110 /* Otherwise, allow inlining if either the callee and caller values
19111 agree, or if the callee is using the default value. */
19113 }
19115 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
19116 to inline CALLEE into CALLER based on target-specific info.
19117 Make sure that the caller and callee have compatible architectural
19118 features. Then go through the other possible target attributes
19119 and see if they can block inlining. Try not to reject always_inline
19120 callees unless they are incompatible architecturally. */
19122 static bool
19124 {
19136 /* Callee's ISA flags should be a subset of the caller's. */
19145 /* Allow non-strict aligned functions inlining into strict
19146 aligned ones. */
19156 /* If the architectural features match up and the callee is always_inline
19157 then the other attributes don't matter. */
19169 /* Honour explicit requests to workaround errata. */
19182 /* If the user explicitly specified -momit-leaf-frame-pointer for the
19183 caller and calle and they don't match up, reject inlining. */
19190 /* If the callee has specific tuning overrides, respect them. */
19195 /* If the user specified tuning override strings for the
19196 caller and callee and they don't match up, reject inlining.
19197 We just do a string compare here, we don't analyze the meaning
19198 of the string, as it would be too costly for little gain. */
19206 }
19208 /* Return the ID of the TLDESC ABI, initializing the descriptor if hasn't
19209 been already. */
19211 unsigned int
19213 {
19216 {
19217 HARD_REG_SET full_reg_clobbers;
19224 }
19226 }
19228 /* Return true if SYMBOL_REF X binds locally. */
19230 static bool
19232 {
19236 }
19238 /* Return true if SYMBOL_REF X is thread local */
19239 static bool
19241 {
19250 }
19252 /* Classify a TLS symbol into one of the TLS kinds. */
19253 enum aarch64_symbol_type
19255 {
19259 {
19266 {
19272 }
19283 else
19292 }
19293 }
19295 /* Return the correct method for accessing X + OFFSET, where X is either
19296 a SYMBOL_REF or LABEL_REF. */
19298 enum aarch64_symbol_type
19300 {
19304 {
19306 {
19321 }
19322 }
19325 {
19330 {
19333 /* With -fPIC non-local symbols use the GOT. For orthogonality
19334 always use the GOT for extern weak symbols. */
19339 /* When we retrieve symbol + offset address, we have to make sure
19340 the offset does not cause overflow of the final address. But
19341 we have no way of knowing the address of symbol at compile time
19342 so we can't accurately say if the distance between the PC and
19343 symbol + offset is outside the addressible range of +/-1MB in the
19344 TINY code model. So we limit the maximum offset to +/-64KB and
19345 assume the offset to the symbol is not larger than +/-(1MB - 64KB).
19346 If offset_within_block_p is true we allow larger offsets. */
19362 /* Same reasoning as the tiny code model, but the offset cap here is
19363 1MB, allowing +/-3.9GB for the offset to the symbol. */
19371 /* This is alright even in PIC code as the constant
19372 pool reference is always PC relative and within
19373 the same translation unit. */
19376 else
19381 }
19382 }
19384 /* By default push everything into the constant pool. */
19386 }
19388 bool
19390 {
19392 }
19394 bool
19396 {
19397 poly_int64 offset;
19403 }
19405 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
19406 that should be rematerialized rather than spilled. */
19408 static bool
19410 {
19411 /* Support CSE and rematerialization of common constants. */
19416 /* Only accept variable-length vector constants if they can be
19417 handled directly.
19419 ??? It would be possible (but complex) to handle rematerialization
19420 of other constants via secondary reloads. */
19424 /* Otherwise, accept any CONST_VECTOR that, if all else fails, can at
19425 least be forced to memory and loaded from there. */
19429 /* Do not allow vector struct mode constants for Advanced SIMD.
19430 We could support 0 and -1 easily, but they need support in
19431 aarch64-simd.md. */
19439 /* Accept polynomial constants that can be calculated by using the
19440 destination of a move as the sole temporary. Constants that
19441 require a second temporary cannot be rematerialized (they can't be
19442 forced to memory and also aren't legitimate constants). */
19443 poly_int64 offset;
19447 /* If an offset is being added to something else, we need to allow the
19448 base to be moved into the destination register, meaning that there
19449 are no free temporaries for the offset. */
19454 /* Do not allow const (plus (anchor_symbol, const_int)). */
19458 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
19459 so spilling them is better than rematerialization. */
19463 /* Label references are always constant. */
19468 }
19470 rtx
19472 {
19478 /* Can return in any reg. */
19481 }
19483 /* On AAPCS systems, this is the "struct __va_list". */
19486 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
19487 Return the type to use as __builtin_va_list.
19489 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
19491 struct __va_list
19492 {
19493 void *__stack;
19494 void *__gr_top;
19495 void *__vr_top;
19496 int __gr_offs;
19497 int __vr_offs;
19498 }; */
19500 static tree
19502 {
19503 tree va_list_name;
19506 /* Create the type. */
19508 /* Give it the required name. */
19510 TYPE_DECL,
19512 va_list_type);
19517 /* Create the fields. */
19520 ptr_type_node);
19523 ptr_type_node);
19526 ptr_type_node);
19529 integer_type_node);
19532 integer_type_node);
19534 /* Tell tree-stdarg pass about our internal offset fields.
19535 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
19536 purpose to identify whether the code is updating va_list internal
19537 offset fields through irregular way. */
19559 /* Compute its layout. */
19563 }
19565 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
19566 static void
19568 {
19572 tree t;
19586 {
19589 }
19598 NULL_TREE);
19600 NULL_TREE);
19602 NULL_TREE);
19604 NULL_TREE);
19606 NULL_TREE);
19608 /* Emit code to initialize STACK, which points to the next varargs stack
19609 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
19610 by named arguments. STACK is 8-byte aligned. */
19617 /* Emit code to initialize GRTOP, the top of the GR save area.
19618 virtual_incoming_args_rtx should have been 16 byte aligned. */
19623 /* Emit code to initialize VRTOP, the top of the VR save area.
19624 This address is gr_save_area_bytes below GRTOP, rounded
19625 down to the next 16-byte boundary. */
19635 /* Emit code to initialize GROFF, the offset from GRTOP of the
19636 next GPR argument. */
19641 /* Likewise emit code to initialize VROFF, the offset from FTOP
19642 of the next VR argument. */
19646 }
19648 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
19650 static tree
19653 {
19654 tree addr;
19660 machine_mode mode;
19684 align
19691 {
19692 /* No frontends can create types with variable-sized modes, so we
19693 shouldn't be asked to pass or return them. */
19696 /* TYPE passed in fp/simd registers. */
19708 {
19711 }
19714 {
19716 }
19717 }
19718 else
19719 {
19720 /* TYPE passed in general registers. */
19729 {
19734 }
19738 {
19740 }
19741 }
19743 /* Get a local temporary for the field value. */
19746 /* Emit code to branch if off >= 0. */
19752 {
19753 /* Emit: offs = (offs + 15) & -16. */
19759 }
19760 else
19763 /* Update ap.__[g|v]r_offs */
19768 /* String up. */
19772 /* [cond2] if (ap.__[g|v]r_offs > 0) */
19777 /* String up: make sure the assignment happens before the use. */
19781 /* Prepare the trees handling the argument that is passed on the stack;
19782 the top level node will store in ON_STACK. */
19785 {
19786 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
19791 }
19792 else
19794 /* Advance ap.__stack */
19799 /* String up roundup and advance. */
19802 /* String up with arg */
19804 /* Big-endianness related address adjustment. */
19807 {
19811 }
19816 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
19826 {
19827 /* type ha; // treat as "struct {ftype field[n];}"
19828 ... [computing offs]
19829 for (i = 0; i <nregs; ++i, offs += 16)
19830 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
19831 return ha; */
19835 /* Declare a local variable. */
19839 /* Establish the base type. */
19841 {
19876 {
19880 }
19884 }
19886 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
19895 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
19897 {
19907 }
19911 }
19921 }
19923 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
19925 static void
19929 {
19931 CUMULATIVE_ARGS local_cum;
19935 /* The caller has advanced CUM up to, but not beyond, the last named
19936 argument. Advance a local copy of CUM past the last "real" named
19937 argument, to find out how many registers are left over. */
19942 /* Found out how many registers we need to save.
19943 Honor tree-stdvar analysis results. */
19952 {
19955 }
19958 {
19960 {
19963 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
19971 }
19973 {
19974 /* We can't use move_block_from_reg, because it will use
19975 the wrong mode, storing D regs only. */
19979 /* Set OFF to the offset from virtual_incoming_args_rtx of
19980 the first vector register. The VR save area lies below
19981 the GR one, and is aligned to 16 bytes. */
19988 {
19996 }
19997 }
19998 }
20000 /* We don't save the size into *PRETEND_SIZE because we want to avoid
20001 any complication of having crtl->args.pretend_args_size changed. */
20006 }
20008 static void
20010 {
20013 {
20015 {
20019 }
20020 }
20023 {
20026 }
20028 /* Only allow the FFR and FFRT to be accessed via special patterns. */
20032 /* When tracking speculation, we need a couple of call-clobbered registers
20033 to track the speculation state. It would be nice to just use
20034 IP0 and IP1, but currently there are numerous places that just
20035 assume these registers are free for other uses (eg pointer
20036 authentication). */
20038 {
20043 }
20044 }
20046 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. */
20048 bool
20050 {
20051 /* For records we're passed a FIELD_DECL, for arrays we're passed
20052 an ARRAY_TYPE. In both cases we're interested in the TREE_TYPE. */
20055 /* Assign BLKmode to anything that contains multiple SVE predicates.
20056 For structures, the "multiple" case is indicated by MODE being
20057 VOIDmode. */
20060 {
20065 }
20068 }
20070 /* Bitmasks that indicate whether earlier versions of GCC would have
20071 taken a different path through the ABI logic. This should result in
20072 a -Wpsabi warning if the earlier path led to a different ABI decision.
20074 WARN_PSABI_EMPTY_CXX17_BASE
20075 Indicates that the type includes an artificial empty C++17 base field
20076 that, prior to GCC 10.1, would prevent the type from being treated as
20077 a HFA or HVA. See PR94383 for details.
20079 WARN_PSABI_NO_UNIQUE_ADDRESS
20080 Indicates that the type includes an empty [[no_unique_address]] field
20081 that, prior to GCC 10.1, would prevent the type from being treated as
20082 a HFA or HVA. */
20087 /* Walk down the type tree of TYPE counting consecutive base elements.
20088 If *MODEP is VOIDmode, then set it to the first valid floating point
20089 type. If a non-floating point type is found, or if a floating point
20090 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
20091 otherwise return the count in the sub-tree.
20093 The WARN_PSABI_FLAGS argument allows the caller to check whether this
20094 function has changed its behavior relative to earlier versions of GCC.
20095 Normally the argument should be nonnull and point to a zero-initialized
20096 variable. The function then records whether the ABI decision might
20097 be affected by a known fix to the ABI logic, setting the associated
20098 WARN_PSABI_* bits if so.
20100 When the argument is instead a null pointer, the function tries to
20101 simulate the behavior of GCC before all such ABI fixes were made.
20102 This is useful to check whether the function returns something
20103 different after the ABI fixes. */
20104 static int
20107 {
20108 machine_mode mode;
20109 HOST_WIDE_INT size;
20115 {
20146 /* Use V2SImode and V4SImode as representatives of all 64-bit
20147 and 128-bit vector types. */
20150 {
20159 }
20164 /* Vector modes are considered to be opaque: two vectors are
20165 equivalent for the purposes of being homogeneous aggregates
20166 if they are the same size. */
20173 {
20177 /* Can't handle incomplete types nor sizes that are not
20178 fixed. */
20184 warn_psabi_flags);
20186 || !index
20197 /* There must be no padding. */
20203 }
20206 {
20209 tree field;
20211 /* Can't handle incomplete types nor sizes that are not
20212 fixed. */
20218 {
20223 {
20224 /* See whether this is something that earlier versions of
20225 GCC failed to ignore. */
20232 else
20233 /* No compatibility problem. */
20236 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
20238 {
20241 }
20242 }
20243 /* A zero-width bitfield may affect layout in some
20244 circumstances, but adds no members. The determination
20245 of whether or not a type is an HFA is performed after
20246 layout is complete, so if the type still looks like an
20247 HFA afterwards, it is still classed as one. This is
20248 potentially an ABI break for the hard-float ABI. */
20251 {
20252 /* Prior to GCC-12 these fields were striped early,
20253 hiding them from the back-end entirely and
20254 resulting in the correct behaviour for argument
20255 passing. Simulate that old behaviour without
20256 generating a warning. */
20260 {
20263 }
20264 }
20267 warn_psabi_flags);
20271 }
20273 /* There must be no padding. */
20279 }
20283 {
20284 /* These aren't very interesting except in a degenerate case. */
20287 tree field;
20289 /* Can't handle incomplete types nor sizes that are not
20290 fixed. */
20296 {
20301 warn_psabi_flags);
20305 }
20307 /* There must be no padding. */
20313 }
20317 }
20320 }
20322 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
20323 type as described in AAPCS64 \S 4.1.2.
20325 See the comment above aarch64_composite_type_p for the notes on MODE. */
20327 static bool
20329 machine_mode mode)
20330 {
20334 {
20338 }
20341 {
20342 /* The containing "else if" is too loose: it means that we look at TYPE
20343 if the type is a vector type (good), but that we otherwise ignore TYPE
20344 and look only at the mode. This is wrong because the type describes
20345 the language-level information whereas the mode is purely an internal
20346 GCC concept. We can therefore reach here for types that are not
20347 vectors in the AAPCS64 sense.
20349 We can't "fix" that for the traditional Advanced SIMD vector modes
20350 without breaking backwards compatibility. However, there's no such
20351 baggage for the structure modes, which were introduced in GCC 12. */
20355 /* For similar reasons, rely only on the type, not the mode, when
20356 processing SVE types. */
20358 /* Leave later code to report an error if SVE is disabled. */
20360 else
20362 }
20364 {
20365 /* 64-bit and 128-bit vectors should only acquire an SVE mode if
20366 they are being treated as scalable AAPCS64 types. */
20370 }
20372 }
20374 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
20375 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
20376 array types. The C99 floating-point complex types are also considered
20377 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
20378 types, which are GCC extensions and out of the scope of AAPCS64, are
20379 treated as composite types here as well.
20381 Note that MODE itself is not sufficient in determining whether a type
20382 is such a composite type or not. This is because
20383 stor-layout.cc:compute_record_mode may have already changed the MODE
20384 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
20385 structure with only one field may have its MODE set to the mode of the
20386 field. Also an integer mode whose size matches the size of the
20387 RECORD_TYPE type may be used to substitute the original mode
20388 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
20389 solely relied on. */
20391 static bool
20393 machine_mode mode)
20394 {
20407 }
20409 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
20410 shall be passed or returned in simd/fp register(s) (providing these
20411 parameter passing registers are available).
20413 Upon successful return, *COUNT returns the number of needed registers,
20414 *BASE_MODE returns the mode of the individual register and when IS_HA
20415 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
20416 floating-point aggregate or a homogeneous short-vector aggregate.
20418 SILENT_P is true if the function should refrain from reporting any
20419 diagnostics. This should only be used if the caller is certain that
20420 any ABI decisions would eventually come through this function with
20421 SILENT_P set to false. */
20423 static bool
20425 const_tree type,
20430 {
20440 {
20443 }
20445 {
20449 }
20451 {
20456 {
20461 && warn_psabi
20462 && warn_psabi_flags
20466 {
20473 /* Use TYPE_MAIN_VARIANT to strip any redundant const
20474 qualification. */
20477 "type %qT with %<[[no_unique_address]]%> members "
20482 "type %qT when C++17 is enabled changed to match "
20489 }
20493 }
20494 else
20496 }
20497 else
20503 }
20505 /* Implement TARGET_STRUCT_VALUE_RTX. */
20507 static rtx
20510 {
20512 }
20514 /* Implements target hook vector_mode_supported_p. */
20515 static bool
20517 {
20520 }
20522 /* Return the full-width SVE vector mode for element mode MODE, if one
20523 exists. */
20524 opt_machine_mode
20526 {
20528 {
20547 }
20548 }
20550 /* Return the 128-bit Advanced SIMD vector mode for element mode MODE,
20551 if it exists. */
20552 opt_machine_mode
20554 {
20556 {
20575 }
20576 }
20578 /* Return appropriate SIMD container
20579 for MODE within a vector of WIDTH bits. */
20580 static machine_mode
20582 {
20590 {
20593 else
20595 {
20610 }
20611 }
20613 }
20615 /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M
20616 and return whether the SVE mode should be preferred over the
20617 Advanced SIMD one in aarch64_autovectorize_vector_modes. */
20618 static bool
20620 {
20621 /* Take into account the aarch64-autovec-preference param if non-zero. */
20630 /* The preference in case of a tie in costs. */
20636 /* If the CPU information does not have an SVE width registered use the
20637 generic poly_int comparison that prefers SVE. If a preference is
20638 explicitly requested avoid this path. */
20640 && !prefer_asimd
20644 /* Otherwise estimate the runtime width of the modes involved. */
20648 /* Preferring SVE means picking it first unless the Advanced SIMD mode
20649 is clearly wider. */
20652 /* Conversely, preferring Advanced SIMD means picking SVE only if SVE
20653 is clearly wider. */
20657 /* In the default case prefer Advanced SIMD over SVE in case of a tie. */
20659 }
20661 /* Return 128-bit container as the preferred SIMD mode for MODE. */
20662 static machine_mode
20664 {
20665 /* Take into account explicit auto-vectorization ISA preferences through
20666 aarch64_cmp_autovec_modes. */
20672 }
20674 /* Return a list of possible vector sizes for the vectorizer
20675 to iterate over. */
20676 static unsigned int
20678 {
20680 /* Try using full vectors for all element types. */
20681 VNx16QImode,
20683 /* Try using 16-bit containers for 8-bit elements and full vectors
20684 for wider elements. */
20685 VNx8QImode,
20687 /* Try using 32-bit containers for 8-bit and 16-bit elements and
20688 full vectors for wider elements. */
20689 VNx4QImode,
20691 /* Try using 64-bit containers for all element types. */
20692 VNx2QImode
20693 };
20696 /* Try using 128-bit vectors for all element types. */
20697 V16QImode,
20699 /* Try using 64-bit vectors for 8-bit elements and 128-bit vectors
20700 for wider elements. */
20701 V8QImode,
20703 /* Try using 64-bit vectors for 16-bit elements and 128-bit vectors
20704 for wider elements.
20706 TODO: We could support a limited form of V4QImode too, so that
20707 we use 32-bit vectors for 8-bit elements. */
20708 V4HImode,
20710 /* Try using 64-bit vectors for 32-bit elements and 128-bit vectors
20711 for 64-bit elements.
20713 TODO: We could similarly support limited forms of V2QImode and V2HImode
20714 for this case. */
20715 V2SImode
20716 };
20718 /* Try using N-byte SVE modes only after trying N-byte Advanced SIMD mode.
20719 This is because:
20721 - If we can't use N-byte Advanced SIMD vectors then the placement
20722 doesn't matter; we'll just continue as though the Advanced SIMD
20723 entry didn't exist.
20725 - If an SVE main loop with N bytes ends up being cheaper than an
20726 Advanced SIMD main loop with N bytes then by default we'll replace
20727 the Advanced SIMD version with the SVE one.
20729 - If an Advanced SIMD main loop with N bytes ends up being cheaper
20730 than an SVE main loop with N bytes then by default we'll try to
20731 use the SVE loop to vectorize the epilogue instead. */
20740 {
20745 else
20747 }
20752 /* Consider enabling VECT_COMPARE_COSTS for SVE, both so that we
20753 can compare SVE against Advanced SIMD and so that we can compare
20754 multiple SVE vectorization approaches against each other. There's
20755 not really any point doing this for Advanced SIMD only, since the
20756 first mode that works should always be the best. */
20760 }
20762 /* Implement TARGET_MANGLE_TYPE. */
20766 {
20767 /* The AArch64 ABI documents say that "__va_list" has to be
20768 mangled as if it is in the "std" namespace. */
20772 /* Half-precision floating point types. */
20774 {
20779 else
20781 }
20783 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
20784 builtin types. */
20786 {
20791 }
20793 /* Use the default mangling. */
20795 }
20797 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
20799 static bool
20802 {
20804 }
20806 /* Find the first rtx_insn before insn that will generate an assembly
20807 instruction. */
20811 {
20815 do
20816 {
20818 }
20822 }
20824 static bool
20826 {
20828 /* A number of these may be AArch32 only. */
20833 };
20836 {
20839 }
20842 }
20844 /* Check if there is a register dependency between a load and the insn
20845 for which we hold recog_data. */
20847 static bool
20849 {
20850 rtx load_reg;
20860 {
20866 }
20868 }
20871 /* When working around the Cortex-A53 erratum 835769,
20872 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
20873 instruction and has a preceding memory instruction such that a NOP
20874 should be inserted between them. */
20876 bool
20878 {
20881 rtx body;
20894 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
20895 Restore recog state to INSN to avoid state corruption. */
20903 /* If the previous insn is a memory op and there is no dependency between
20904 it and the DImode madd, emit a NOP between them. If body is NULL then we
20905 have a complex memory operation, probably a load/store pair.
20906 Be conservative for now and emit a NOP. */
20913 }
20916 /* Implement FINAL_PRESCAN_INSN. */
20918 void
20920 {
20923 }
20926 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
20927 instruction. */
20929 bool
20931 {
20934 }
20936 /* Return true if X is a valid immediate for the SVE ADD and SUB instructions
20937 when applied to mode MODE. Negate X first if NEGATE_P is true. */
20939 bool
20941 {
20954 }
20956 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
20957 instructions when applied to mode MODE. Negate X first if NEGATE_P
20958 is true. */
20960 bool
20962 {
20966 /* After the optional negation, the immediate must be nonnegative.
20967 E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
20968 instead of SQADD Zn.B, Zn.B, #129. */
20971 }
20973 /* Return true if X is a valid immediate operand for an SVE logical
20974 instruction such as AND. */
20976 bool
20978 {
20979 rtx elt;
20985 }
20987 /* Return true if X is a valid immediate for the SVE DUP and CPY
20988 instructions. */
20990 bool
20992 {
21001 }
21003 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
21004 SIGNED_P says whether the operand is signed rather than unsigned. */
21006 bool
21008 {
21011 && (signed_p
21014 }
21016 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
21017 instruction. Negate X first if NEGATE_P is true. */
21019 bool
21021 {
21022 rtx elt;
21023 REAL_VALUE_TYPE r;
21039 }
21041 /* Return true if X is a valid immediate operand for an SVE FMUL
21042 instruction. */
21044 bool
21046 {
21047 rtx elt;
21053 }
21055 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
21056 for the Advanced SIMD operation described by WHICH and INSN. If INFO
21057 is nonnull, use it to describe valid immediates. */
21058 static bool
21063 {
21064 /* Try a 4-byte immediate with LSL. */
21067 {
21072 }
21074 /* Try a 2-byte immediate with LSL. */
21079 {
21084 }
21086 /* Try a 4-byte immediate with MSL, except for cases that MVN
21087 can handle. */
21090 {
21093 {
21098 }
21099 }
21102 }
21104 /* Return true if replicating VAL64 is a valid immediate for the
21105 Advanced SIMD operation described by WHICH. If INFO is nonnull,
21106 use it to describe valid immediates. */
21107 static bool
21111 {
21117 {
21128 /* Try using a replicated byte. */
21132 {
21136 }
21137 }
21139 /* Try using a bit-to-bytemask. */
21141 {
21144 {
21148 }
21150 {
21154 }
21155 }
21157 }
21159 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
21160 instruction. If INFO is nonnull, use it to describe valid immediates. */
21162 static bool
21165 {
21169 {
21173 {
21178 }
21179 }
21182 {
21183 /* DUP with no shift. */
21187 }
21189 {
21190 /* DUP with LSL #8. */
21194 }
21196 {
21197 /* DUPM. */
21201 }
21203 }
21205 /* Return true if X is an UNSPEC_PTRUE constant of the form:
21207 (const (unspec [PATTERN ZERO] UNSPEC_PTRUE))
21209 where PATTERN is the svpattern as a CONST_INT and where ZERO
21210 is a zero constant of the required PTRUE mode (which can have
21211 fewer elements than X's mode, if zero bits are significant).
21213 If so, and if INFO is nonnull, describe the immediate in INFO. */
21214 bool
21216 {
21225 {
21226 aarch64_svpattern pattern
21231 }
21233 }
21235 /* Return true if X is a valid SVE predicate. If INFO is nonnull, use
21236 it to describe valid immediates. */
21238 static bool
21240 {
21245 {
21249 }
21251 /* Analyze the value as a VNx16BImode. This should be relatively
21252 efficient, since rtx_vector_builder has enough built-in capacity
21253 to store all VLA predicate constants without needing the heap. */
21254 rtx_vector_builder builder;
21260 {
21264 {
21266 {
21269 }
21271 }
21272 }
21274 }
21276 /* Return true if OP is a valid SIMD immediate for the operation
21277 described by WHICH. If INFO is nonnull, use it to describe valid
21278 immediates. */
21279 bool
21282 {
21302 {
21309 {
21310 /* Get the corresponding container mode. E.g. an INDEX on V2SI
21311 should yield two integer values per 128-bit block, meaning
21312 that we need to treat it in the same way as V2DI and then
21313 ignore the upper 32 bits of each element. */
21316 }
21318 }
21322 else
21325 scalar_float_mode elt_float_mode;
21328 {
21332 {
21336 }
21337 }
21339 /* If all elements in an SVE vector have the same value, we have a free
21340 choice between using the element mode and using the container mode.
21341 Using the element mode means that unused parts of the vector are
21342 duplicates of the used elements, while using the container mode means
21343 that the unused parts are an extension of the used elements. Using the
21344 element mode is better for (say) VNx4HI 0x101, since 0x01010101 is valid
21345 for its container mode VNx4SI while 0x00000101 isn't.
21347 If not all elements in an SVE vector have the same value, we need the
21348 transition from one element to the next to occur at container boundaries.
21349 E.g. a fixed-length VNx4HI containing { 1, 2, 3, 4 } should be treated
21350 in the same way as a VNx4SI containing { 1, 2, 3, 4 }. */
21351 scalar_int_mode elt_int_mode;
21354 else
21361 /* Expand the vector constant out into a byte vector, with the least
21362 significant byte of the register first. */
21366 {
21367 /* The vector is provided in gcc endian-neutral fashion.
21368 For aarch64_be Advanced SIMD, it must be laid out in the vector
21369 register in reverse order. */
21381 {
21384 }
21385 }
21387 /* The immediate must repeat every eight bytes. */
21393 /* Get the repeating 8-byte value as an integer. No endian correction
21394 is needed here because bytes is already in lsb-first order. */
21402 else
21404 }
21406 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
21407 has a step in the range of INDEX. Return the index expression if so,
21408 otherwise return null. */
21409 rtx
21411 {
21418 }
21420 /* Check of immediate shift constants are within range. */
21421 bool
21423 {
21430 else
21432 }
21434 /* Return the bitmask CONST_INT to select the bits required by a zero extract
21435 operation of width WIDTH at bit position POS. */
21437 rtx
21439 {
21443 unsigned HOST_WIDE_INT mask
21446 }
21448 bool
21450 {
21459 {
21460 /* Require predicate constants to be VNx16BI before RA, so that we
21461 force everything to have a canonical form. */
21463 && !reload_completed
21469 }
21471 /* Remove UNSPEC_SALT_ADDR before checking symbol reference. */
21474 /* GOT accesses are valid moves. */
21487 }
21489 /* Create a 0 constant that is based on V4SI to allow CSE to optimally share
21490 the constant creation. */
21492 rtx
21494 {
21499 }
21501 /* Return a const_int vector of VAL. */
21502 rtx
21504 {
21507 }
21509 /* Check OP is a legal scalar immediate for the MOVI instruction. */
21511 bool
21513 {
21514 machine_mode vmode;
21519 }
21521 /* Construct and return a PARALLEL RTX vector with elements numbering the
21522 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
21523 the vector - from the perspective of the architecture. This does not
21524 line up with GCC's perspective on lane numbers, so we end up with
21525 different masks depending on our target endian-ness. The diagram
21526 below may help. We must draw the distinction when building masks
21527 which select one half of the vector. An instruction selecting
21528 architectural low-lanes for a big-endian target, must be described using
21529 a mask selecting GCC high-lanes.
21531 Big-Endian Little-Endian
21533 GCC 0 1 2 3 3 2 1 0
21534 | x | x | x | x | | x | x | x | x |
21535 Architecture 3 2 1 0 3 2 1 0
21537 Low Mask: { 2, 3 } { 0, 1 }
21538 High Mask: { 0, 1 } { 2, 3 }
21540 MODE Is the mode of the vector and NUNITS is the number of units in it. */
21542 rtx
21544 {
21549 rtx t1;
21554 else
21562 }
21564 /* Check OP for validity as a PARALLEL RTX vector with elements
21565 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
21566 from the perspective of the architecture. See the diagram above
21567 aarch64_simd_vect_par_cnst_half for more details. */
21569 bool
21572 {
21586 {
21593 }
21595 }
21597 /* Return a PARALLEL containing NELTS elements, with element I equal
21598 to BASE + I * STEP. */
21600 rtx
21602 {
21607 }
21609 /* Return true if OP is a PARALLEL of CONST_INTs that form a linear
21610 series with step STEP. */
21612 bool
21614 {
21625 }
21627 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
21628 HIGH (exclusive). */
21629 void
21631 const_tree exp)
21632 {
21633 HOST_WIDE_INT lane;
21638 {
21642 else
21644 }
21645 }
21647 /* Peform endian correction on lane number N, which indexes a vector
21648 of mode MODE, and return the result as an SImode rtx. */
21650 rtx
21652 {
21654 }
21656 /* Return TRUE if OP is a valid vector addressing mode. */
21658 bool
21660 {
21663 }
21665 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
21667 bool
21669 {
21671 scalar_mode mode;
21678 }
21680 /* Return true if OP is a valid MEM operand for an SVE LD1R{Q,O} instruction
21681 where the size of the read data is specified by `mode` and the size of the
21682 vector elements are specified by `elem_mode`. */
21683 bool
21685 scalar_mode elem_mode)
21686 {
21699 }
21701 /* Return true if OP is a valid MEM operand for an SVE LD1RQ instruction. */
21702 bool
21704 {
21707 }
21709 /* Return true if OP is a valid MEM operand for an SVE LD1RO instruction for
21710 accessing a vector where the element size is specified by `elem_mode`. */
21711 bool
21713 {
21715 }
21717 /* Return true if OP is a valid MEM operand for an SVE LDFF1 instruction. */
21718 bool
21720 {
21732 }
21734 /* Return true if OP is a valid MEM operand for an SVE LDNF1 instruction. */
21735 bool
21737 {
21744 }
21746 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
21747 The conditions for STR are the same. */
21748 bool
21750 {
21757 }
21759 /* Return true if OP is a valid address for an SVE PRF[BHWD] instruction,
21760 addressing memory of mode MODE. */
21761 bool
21763 {
21772 }
21774 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
21775 We need to be able to access the individual pieces, so the range
21776 is different from LD[234] and ST[234]. */
21777 bool
21779 {
21786 ADDR_QUERY_ANY)
21794 }
21796 /* Emit a register copy from operand to operand, taking care not to
21797 early-clobber source registers in the process.
21799 COUNT is the number of components into which the copy needs to be
21800 decomposed. */
21801 void
21804 {
21814 else
21818 }
21820 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
21821 one of VSTRUCT modes: OI, CI, or XI. */
21822 int
21824 {
21825 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
21827 }
21829 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
21830 alignment of a vector to 128 bits. SVE predicates have an alignment of
21831 16 bits. */
21832 static HOST_WIDE_INT
21834 {
21835 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
21836 be set for non-predicate vectors of booleans. Modes are the most
21837 direct way we have of identifying real SVE predicate types. */
21840 widest_int min_size
21843 }
21845 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
21846 static poly_uint64
21848 {
21850 {
21851 /* If the length of the vector is a fixed power of 2, try to align
21852 to that length, otherwise don't try to align at all. */
21853 HOST_WIDE_INT result;
21858 }
21860 }
21862 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
21863 static bool
21865 {
21869 /* For fixed-length vectors, check that the vectorizer will aim for
21870 full-vector alignment. This isn't true for generic GCC vectors
21871 that are wider than the ABI maximum of 128 bits. */
21872 poly_uint64 preferred_alignment =
21876 preferred_alignment))
21879 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
21881 }
21883 /* Return true if the vector misalignment factor is supported by the
21884 target. */
21885 static bool
21889 {
21891 {
21892 /* Return if movmisalign pattern is not supported for this mode. */
21896 /* Misalignment factor is unknown at compile time. */
21899 }
21901 is_packed);
21902 }
21904 /* If VALS is a vector constant that can be loaded into a register
21905 using DUP, generate instructions to do so and return an RTX to
21906 assign to the register. Otherwise return NULL_RTX. */
21907 static rtx
21909 {
21912 rtx x;
21917 /* We can load this constant by using DUP and a constant in a
21918 single ARM register. This will be cheaper than a vector
21919 load. */
21922 }
21925 /* Generate code to load VALS, which is a PARALLEL containing only
21926 constants (for vec_init) or CONST_VECTOR, efficiently into a
21927 register. Returns an RTX to copy into the register, or NULL_RTX
21928 for a PARALLEL that cannot be converted into a CONST_VECTOR. */
21929 static rtx
21931 {
21933 rtx const_dup;
21941 {
21942 /* A CONST_VECTOR must contain only CONST_INTs and
21943 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
21944 Only store valid constants in a CONST_VECTOR. */
21947 {
21950 n_const++;
21951 }
21954 }
21955 else
21960 /* Load using MOVI/MVNI. */
21963 /* Loaded using DUP. */
21966 /* Load from constant pool. We cannot take advantage of single-cycle
21967 LD1 because we need a PC-relative addressing mode. */
21969 else
21970 /* A PARALLEL containing something not valid inside CONST_VECTOR.
21971 We cannot construct an initializer. */
21973 }
21975 /* Expand a vector initialisation sequence, such that TARGET is
21976 initialised to contain VALS. */
21978 void
21980 {
21983 /* The number of vector elements. */
21985 /* The number of vector elements which are not constant. */
21988 /* The first element of vals. */
21992 /* This is a special vec_init<M><N> where N is not an element mode but a
21993 vector mode with half the elements of M. We expect to find two entries
21994 of mode N in VALS and we must put their concatentation into TARGET. */
21996 {
22005 }
22007 /* Count the number of variable elements to initialise. */
22009 {
22013 else
22017 }
22019 /* No variable elements, hand off to aarch64_simd_make_constant which knows
22020 how best to handle this. */
22022 {
22025 {
22028 }
22029 }
22031 /* Splat a single non-constant element if we can. */
22033 {
22037 }
22039 /* Check for interleaving case.
22040 For eg if initializer is (int16x8_t) {x, y, x, y, x, y, x, y}.
22041 Generate following code:
22042 dup v0.h, x
22043 dup v1.h, y
22044 zip1 v0.h, v0.h, v1.h
22045 for "large enough" initializer. */
22048 {
22055 {
22060 {
22063 }
22068 }
22069 }
22074 /* If there are only variable elements, try to optimize
22075 the insertion using dup for the most common element
22076 followed by insertions. */
22078 /* The algorithm will fill matches[*][0] with the earliest matching element,
22079 and matches[X][1] with the count of duplicate elements (if X is the
22080 earliest element which has duplicates). */
22083 {
22086 {
22088 {
22090 {
22094 }
22095 }
22096 }
22101 {
22104 }
22106 /* Create a duplicate of the most common element, unless all elements
22107 are equally useless to us, in which case just immediately set the
22108 vector register using the first element. */
22111 {
22112 /* For vectors of two 64-bit elements, we can do even better. */
22117 {
22120 /* Combine can pick up this case, but handling it directly
22121 here leaves clearer RTL.
22123 This is load_pair_lanes<mode>, and also gives us a clean-up
22124 for store_pair_lanes<mode>. */
22128 {
22129 rtx t;
22132 else
22136 }
22137 }
22138 /* The subreg-move sequence below will move into lane zero of the
22139 vector register. For big-endian we want that position to hold
22140 the last element of VALS. */
22144 }
22145 else
22146 {
22149 }
22151 /* Insert the rest. */
22153 {
22159 }
22161 }
22163 /* Initialise a vector which is part-variable. We want to first try
22164 to build those lanes which are constant in the most efficient way we
22165 can. */
22167 {
22170 /* Load constant part of vector. We really don't care what goes into the
22171 parts we will overwrite, but we're more likely to be able to load the
22172 constant efficiently if it has fewer, larger, repeating parts
22173 (see aarch64_simd_valid_immediate). */
22175 {
22181 {
22182 /* Look in the copied vector, as more elements are const. */
22185 {
22188 }
22189 }
22191 }
22193 }
22195 /* Insert the variable lanes directly. */
22197 {
22203 }
22204 }
22206 /* Emit RTL corresponding to:
22207 insr TARGET, ELEM. */
22209 static void
22211 {
22219 }
22221 /* Subroutine of aarch64_sve_expand_vector_init for handling
22222 trailing constants.
22223 This function works as follows:
22224 (a) Create a new vector consisting of trailing constants.
22225 (b) Initialize TARGET with the constant vector using emit_move_insn.
22226 (c) Insert remaining elements in TARGET using insr.
22227 NELTS is the total number of elements in original vector while
22228 while NELTS_REQD is the number of elements that are actually
22229 significant.
22231 ??? The heuristic used is to do above only if number of constants
22232 is at least half the total number of elements. May need fine tuning. */
22234 static bool
22235 aarch64_sve_expand_vector_init_handle_trailing_constants
22237 {
22244 i--)
22245 n_trailing_constants++;
22248 {
22249 /* Try to use the natural pattern of BUILDER to extend the trailing
22250 constant elements to a full vector. Replace any variables in the
22251 extra elements with zeros.
22253 ??? It would be better if the builders supported "don't care"
22254 elements, with the builder filling in whichever elements
22255 give the most compact encoding. */
22258 {
22263 }
22271 }
22274 }
22276 /* Subroutine of aarch64_sve_expand_vector_init.
22277 Works as follows:
22278 (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
22279 (b) Skip trailing elements from BUILDER, which are the same as
22280 element NELTS_REQD - 1.
22281 (c) Insert earlier elements in reverse order in TARGET using insr. */
22283 static void
22287 {
22302 }
22304 /* Subroutine of aarch64_sve_expand_vector_init to handle case
22305 when all trailing elements of builder are same.
22306 This works as follows:
22307 (a) Use expand_insn interface to broadcast last vector element in TARGET.
22308 (b) Insert remaining elements in TARGET using insr.
22310 ??? The heuristic used is to do above if number of same trailing elements
22311 is at least 3/4 of total number of elements, loosely based on
22312 heuristic from mostly_zeros_p. May need fine-tuning. */
22314 static bool
22315 aarch64_sve_expand_vector_init_handle_trailing_same_elem
22317 {
22320 {
22324 }
22327 }
22329 /* Initialize register TARGET from BUILDER. NELTS is the constant number
22330 of elements in BUILDER.
22332 The function tries to initialize TARGET from BUILDER if it fits one
22333 of the special cases outlined below.
22335 Failing that, the function divides BUILDER into two sub-vectors:
22336 v_even = even elements of BUILDER;
22337 v_odd = odd elements of BUILDER;
22339 and recursively calls itself with v_even and v_odd.
22341 if (recursive call succeeded for v_even or v_odd)
22342 TARGET = zip (v_even, v_odd)
22344 The function returns true if it managed to build TARGET from BUILDER
22345 with one of the special cases, false otherwise.
22347 Example: {a, 1, b, 2, c, 3, d, 4}
22349 The vector gets divided into:
22350 v_even = {a, b, c, d}
22351 v_odd = {1, 2, 3, 4}
22353 aarch64_sve_expand_vector_init(v_odd) hits case 1 and
22354 initialize tmp2 from constant vector v_odd using emit_move_insn.
22356 aarch64_sve_expand_vector_init(v_even) fails since v_even contains
22357 4 elements, so we construct tmp1 from v_even using insr:
22358 tmp1 = dup(d)
22359 insr tmp1, c
22360 insr tmp1, b
22361 insr tmp1, a
22363 And finally:
22364 TARGET = zip (tmp1, tmp2)
22365 which sets TARGET to {a, 1, b, 2, c, 3, d, 4}. */
22367 static bool
22370 {
22373 /* Case 1: Vector contains trailing constants. */
22379 /* Case 2: Vector contains leading constants. */
22388 {
22391 }
22393 /* Case 3: Vector contains trailing same element. */
22399 /* Case 4: Vector contains leading same element. */
22403 {
22406 }
22408 /* Avoid recursing below 4-elements.
22409 ??? The threshold 4 may need fine-tuning. */
22418 {
22421 }
22437 /* Initialize v_even and v_odd using INSR if it didn't match any of the
22438 special cases and zip v_even, v_odd. */
22449 }
22451 /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
22453 void
22455 {
22464 /* If neither sub-vectors of v could be initialized specially,
22465 then use INSR to insert all elements from v into TARGET.
22466 ??? This might not be optimal for vectors with large
22467 initializers like 16-element or above.
22468 For nelts < 4, it probably isn't useful to handle specially. */
22473 }
22475 /* Check whether VALUE is a vector constant in which every element
22476 is either a power of 2 or a negated power of 2. If so, return
22477 a constant vector of log2s, and flip CODE between PLUS and MINUS
22478 if VALUE contains negated powers of 2. Return NULL_RTX otherwise. */
22480 static rtx
22482 {
22486 rtx_vector_builder builder;
22491 /* 1 if the result of the multiplication must be negated,
22492 0 if it mustn't, or -1 if we don't yet care. */
22496 {
22503 {
22504 /* It matters whether we negate or not. Make that choice,
22505 and make sure that it's consistent with previous elements. */
22511 }
22512 /* POW2 is now the value that we want to be a power of 2. */
22517 }
22519 /* PLUS and MINUS are equivalent; canonicalize on PLUS. */
22524 }
22526 /* Prepare for an integer SVE multiply-add or multiply-subtract pattern;
22527 CODE is PLUS for the former and MINUS for the latter. OPERANDS is the
22528 operands array, in the same order as for fma_optab. Return true if
22529 the function emitted all the necessary instructions, false if the caller
22530 should generate the pattern normally with the new OPERANDS array. */
22532 bool
22534 {
22537 {
22542 OPTAB_DIRECT);
22544 }
22547 }
22549 /* Likewise, but for a conditional pattern. */
22551 bool
22553 {
22556 {
22562 }
22565 }
22567 static unsigned HOST_WIDE_INT
22569 {
22573 }
22575 /* Select a format to encode pointers in exception handling data. */
22576 int
22578 {
22581 {
22587 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
22588 for everything. */
22592 /* No assumptions here. 8-byte relocs required. */
22595 }
22597 }
22599 /* Output .variant_pcs for aarch64_vector_pcs function symbols. */
22601 static void
22603 {
22605 {
22608 {
22612 }
22613 }
22614 }
22616 /* The last .arch and .tune assembly strings that we printed. */
22620 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
22621 by the function fndecl. */
22623 void
22625 tree fndecl)
22626 {
22632 else
22643 /* Only update the assembler .arch string if it is distinct from the last
22644 such string we printed. */
22647 {
22650 }
22652 /* Print the cpu name we're tuning for in the comments, might be
22653 useful to readers of the generated asm. Do it only when it changes
22654 from function to function and verbose assembly is requested. */
22659 {
22663 }
22667 /* Don't forget the type directive for ELF. */
22672 }
22674 /* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. Check if the patch area is after
22675 the function label and emit a BTI if necessary. */
22677 void
22681 {
22685 {
22686 /* Remove the BTI that follows the patch area and insert a new BTI
22687 before the patch area right after the function label. */
22695 }
22698 }
22700 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
22702 void
22704 {
22709 }
22711 /* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined
22712 function symbol references. */
22714 void
22716 {
22719 }
22721 /* Triggered after a .cfi_startproc directive is emitted into the assembly file.
22722 Used to output the .cfi_b_key_frame directive when signing the current
22723 function with the B key. */
22725 void
22727 {
22731 }
22733 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
22735 static void
22737 {
22754 }
22756 /* Emit load exclusive. */
22758 static void
22761 {
22766 else
22768 }
22770 /* Emit store exclusive. */
22772 static void
22775 {
22780 else
22782 }
22784 /* Mark the previous jump instruction as unlikely. */
22786 static void
22788 {
22791 }
22793 /* We store the names of the various atomic helpers in a 5x5 array.
22794 Return the libcall function given MODE, MODEL and NAMES. */
22796 rtx
22799 {
22804 {
22822 }
22825 {
22847 }
22850 VISIBILITY_HIDDEN);
22851 }
22853 #define DEF0(B, N) \
22860 #define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
22861 { NULL, NULL, NULL, NULL }
22862 #define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
22871 #undef DEF0
22872 #undef DEF4
22873 #undef DEF5
22875 /* Expand a compare and swap pattern. */
22877 void
22879 {
22893 /* Normally the succ memory model must be stronger than fail, but in the
22894 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
22895 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
22902 {
22905 }
22908 {
22909 /* The CAS insn requires oldval and rval overlap, but we need to
22910 have a copy of oldval saved across the operation to tell if
22911 the operation is successful. */
22914 else
22920 }
22922 {
22923 /* Oldval must satisfy compare afterward. */
22931 }
22932 else
22933 {
22934 /* The oldval predicate varies by mode. Test it and force to reg. */
22942 }
22950 }
22952 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
22953 sequence implementing an atomic operation. */
22955 static void
22957 {
22964 {
22966 }
22967 }
22969 /* Split a compare and swap pattern. */
22971 void
22973 {
22974 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
22978 machine_mode mode;
22993 /* When OLDVAL is zero and we want the strong version we can emit a tighter
22994 loop:
22995 .label1:
22996 LD[A]XR rval, [mem]
22997 CBNZ rval, .label2
22998 ST[L]XR scratch, newval, [mem]
22999 CBNZ scratch, .label1
23000 .label2:
23001 CMP rval, 0. */
23007 {
23010 }
23013 /* The initial load can be relaxed for a __sync operation since a final
23014 barrier will be emitted to stop code hoisting. */
23017 else
23022 else
23023 {
23026 }
23034 {
23036 {
23037 /* Emit an explicit compare instruction, so that we can correctly
23038 track the condition codes. */
23041 }
23042 else
23048 }
23049 else
23054 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
23055 to set the condition flags. If this is not used it will be removed by
23056 later passes. */
23060 /* Emit any final barrier needed for a __sync operation. */
23063 }
23065 /* Split an atomic operation. */
23067 void
23070 {
23071 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
23079 rtx x;
23081 /* Split the atomic operation into a sequence. */
23089 else
23093 /* The initial load can be relaxed for a __sync operation since a final
23094 barrier will be emitted to stop code hoisting. */
23098 else
23102 {
23116 {
23119 }
23120 /* Fall through. */
23126 }
23132 {
23133 /* Emit an explicit compare instruction, so that we can correctly
23134 track the condition codes. */
23137 }
23138 else
23145 /* Emit any final barrier needed for a __sync operation. */
23148 }
23150 static void
23152 {
23153 /* Half-precision float operations. The compiler handles all operations
23154 with NULL libfuncs by converting to SFmode. */
23156 /* Conversions. */
23160 /* Arithmetic. */
23167 /* Comparisons. */
23175 }
23177 /* Target hook for c_mode_for_suffix. */
23178 static machine_mode
23180 {
23185 }
23187 /* We can only represent floating point constants which will fit in
23188 "quarter-precision" values. These values are characterised by
23189 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
23190 by:
23192 (-1)^s * (n/16) * 2^r
23194 Where:
23195 's' is the sign bit.
23196 'n' is an integer in the range 16 <= n <= 31.
23197 'r' is an integer in the range -3 <= r <= 4. */
23199 /* Return true iff X can be represented by a quarter-precision
23200 floating point immediate operand X. Note, we cannot represent 0.0. */
23201 bool
23203 {
23204 /* This represents our current view of how many bits
23205 make up the mantissa. */
23222 /* We cannot represent infinities, NaNs or +/-zero. We won't
23223 know if we have +zero until we analyse the mantissa, but we
23224 can reject the other invalid values. */
23229 /* Extract exponent. */
23233 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
23234 highest (sign) bit, with a fixed binary point at bit point_pos.
23235 m1 holds the low part of the mantissa, m2 the high part.
23236 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
23237 bits for the mantissa, this can fail (low bits will be lost). */
23241 /* If the low part of the mantissa has bits set we cannot represent
23242 the value. */
23245 /* We have rejected the lower HOST_WIDE_INT, so update our
23246 understanding of how many bits lie in the mantissa and
23247 look only at the high HOST_WIDE_INT. */
23251 /* We can only represent values with a mantissa of the form 1.xxxx. */
23256 /* Having filtered unrepresentable values, we may now remove all
23257 but the highest 5 bits. */
23260 /* We cannot represent the value 0.0, so reject it. This is handled
23261 elsewhere. */
23265 /* Then, as bit 4 is always set, we can mask it off, leaving
23266 the mantissa in the range [0, 15]. */
23270 /* GCC internally does not use IEEE754-like encoding (where normalized
23271 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
23272 Our mantissa values are shifted 4 places to the left relative to
23273 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
23274 by 5 places to correct for GCC's representation. */
23278 }
23280 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
23281 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
23282 output MOVI/MVNI, ORR or BIC immediate. */
23286 {
23296 /* This will return true to show const_vector is legal for use as either
23297 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
23298 It will also update INFO to show how the immediate should be generated.
23299 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
23307 {
23310 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
23311 move immediate path. */
23314 else
23315 {
23324 else
23328 }
23329 }
23334 {
23346 else
23350 }
23351 else
23352 {
23353 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
23360 else
23364 }
23366 }
23370 {
23372 /* If a floating point number was passed and we desire to use it in an
23373 integer mode do the conversion to integer. */
23375 {
23380 }
23382 machine_mode vmode;
23383 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
23384 a 128 bit vector mode. */
23390 }
23392 /* Return the output string to use for moving immediate CONST_VECTOR
23393 into an SVE register. */
23397 {
23409 {
23412 {
23415 }
23416 else
23417 {
23424 else
23427 }
23429 }
23432 {
23438 }
23441 {
23444 else
23445 {
23455 }
23456 }
23461 }
23463 /* Return the asm template for a PTRUES. CONST_UNSPEC is the
23464 aarch64_sve_ptrue_svpattern_immediate that describes the predicate
23465 pattern. */
23469 {
23480 }
23482 /* Split operands into moves from op[1] + op[2] into op[0]. */
23484 void
23486 {
23497 {
23498 /* No-op move. Can't split to nothing; emit something. */
23501 }
23503 /* Preserve register attributes for variable tracking. */
23508 /* Special case of reversed high/low parts. */
23511 {
23515 }
23517 {
23518 /* Try to avoid unnecessary moves if part of the result
23519 is in the right place already. */
23524 }
23525 else
23526 {
23531 }
23532 }
23534 /* vec_perm support. */
23536 struct expand_vec_perm_d
23537 {
23539 vec_perm_indices perm;
23540 machine_mode vmode;
23541 machine_mode op_mode;
23546 };
23550 /* Generate a variable permutation. */
23552 static void
23554 {
23565 {
23567 {
23568 /* Expand the argument to a V16QI mode by duplicating it. */
23572 }
23573 else
23574 {
23576 }
23577 }
23578 else
23579 {
23580 rtx pair;
23583 {
23587 }
23588 else
23589 {
23593 }
23594 }
23595 }
23597 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
23598 NELT is the number of elements in the vector. */
23600 void
23603 {
23606 rtx mask;
23608 /* The TBL instruction does not use a modulo index, so we must take care
23609 of that ourselves. */
23614 /* For big-endian, we also need to reverse the index within the vector
23615 (but not which vector). */
23617 {
23618 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
23623 }
23625 }
23627 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
23629 static void
23631 {
23635 }
23637 /* Expand an SVE vec_perm with the given operands. */
23639 void
23641 {
23644 /* Enforced by the pattern condition. */
23647 /* Note: vec_perm indices are supposed to wrap when they go beyond the
23648 size of the two value vectors, i.e. the upper bits of the indices
23649 are effectively ignored. SVE TBL instead produces 0 for any
23650 out-of-range indices, so we need to modulo all the vec_perm indices
23651 to ensure they are all in range. */
23654 /* Check if the sel only references the first values vector. */
23657 {
23660 }
23662 /* Check if the two values vectors are the same. */
23664 {
23670 }
23672 /* Run TBL on for each value vector and combine the results. */
23679 {
23684 }
23691 else
23693 }
23695 /* Recognize patterns suitable for the TRN instructions. */
23696 static bool
23698 {
23699 HOST_WIDE_INT odd;
23707 /* Note that these are little-endian tests.
23708 We correct for big-endian later. */
23715 /* Success! */
23721 /* We don't need a big-endian lane correction for SVE; see the comment
23722 at the head of aarch64-sve.md for details. */
23724 {
23727 }
23733 }
23735 /* Try to re-encode the PERM constant so it combines odd and even elements.
23736 This rewrites constants such as {0, 1, 4, 5}/V4SF to {0, 2}/V2DI.
23737 We retry with this new constant with the full suite of patterns. */
23738 static bool
23740 {
23741 expand_vec_perm_d newd;
23747 /* Get the new mode. Always twice the size of the inner
23748 and half the elements. */
23757 /* to_constant is safe since this routine is specific to Advanced SIMD
23758 vectors. */
23761 vec_perm_builder newpermconst;
23764 /* Convert the perm constant if we can. Require even, odd as the pairs. */
23766 {
23769 poly_int64 newelt;
23773 }
23788 }
23790 /* Recognize patterns suitable for the UZP instructions. */
23791 static bool
23793 {
23794 HOST_WIDE_INT odd;
23801 /* Note that these are little-endian tests.
23802 We correct for big-endian later. */
23808 /* Success! */
23814 /* We don't need a big-endian lane correction for SVE; see the comment
23815 at the head of aarch64-sve.md for details. */
23817 {
23820 }
23826 }
23828 /* Recognize patterns suitable for the ZIP instructions. */
23829 static bool
23831 {
23840 /* Note that these are little-endian tests.
23841 We correct for big-endian later. */
23849 /* Success! */
23855 /* We don't need a big-endian lane correction for SVE; see the comment
23856 at the head of aarch64-sve.md for details. */
23858 {
23861 }
23867 }
23869 /* Recognize patterns for the EXT insn. */
23871 static bool
23873 {
23874 HOST_WIDE_INT location;
23875 rtx offset;
23877 /* The first element always refers to the first vector.
23878 Check if the extracted indices are increasing by one. */
23884 /* Success! */
23888 /* The case where (location == 0) is a no-op for both big- and little-endian,
23889 and is removed by the mid-end at optimization levels -O1 and higher.
23891 We don't need a big-endian lane correction for SVE; see the comment
23892 at the head of aarch64-sve.md for details. */
23894 {
23895 /* After setup, we want the high elements of the first vector (stored
23896 at the LSB end of the register), and the low elements of the second
23897 vector (stored at the MSB end of the register). So swap. */
23899 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
23900 to_constant () is safe since this is restricted to Advanced SIMD
23901 vectors. */
23903 }
23909 UNSPEC_EXT));
23911 }
23913 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
23914 within each 64-bit, 32-bit or 16-bit granule. */
23916 static bool
23918 {
23919 HOST_WIDE_INT diff;
23921 machine_mode pred_mode;
23931 else
23934 {
23937 }
23939 {
23942 }
23944 {
23947 }
23948 else
23956 /* Success! */
23961 {
23966 }
23970 }
23972 /* Recognize patterns for the REV insn, which reverses elements within
23973 a full vector. */
23975 static bool
23977 {
23986 /* Success! */
23993 }
23995 static bool
23997 {
23999 rtx in0;
24000 HOST_WIDE_INT elt;
24002 rtx lane;
24013 /* Success! */
24017 /* The generic preparation in aarch64_expand_vec_perm_const_1
24018 swaps the operand order and the permute indices if it finds
24019 d->perm[0] to be in the second operand. Thus, we can always
24020 use d->op0 and need not do any extra arithmetic to get the
24021 correct lane number. */
24029 }
24031 static bool
24033 {
24037 /* Make sure that the indices are constant. */
24046 /* Generic code will try constant permutation twice. Once with the
24047 original mode and again with the elements lowered to QImode.
24048 So wait and don't do the selector expansion ourselves. */
24052 /* to_constant is safe since this routine is specific to Advanced SIMD
24053 vectors. */
24056 /* If big-endian and two vectors we end up with a weird mixed-endian
24057 mode on NEON. Reverse the index within each word but not the word
24058 itself. to_constant is safe because we checked is_constant above. */
24068 }
24070 /* Try to implement D using an SVE TBL instruction. */
24072 static bool
24074 {
24077 /* Permuting two variable-length vectors could overflow the
24078 index range. */
24089 else
24092 }
24094 /* Try to implement D using SVE dup instruction. */
24096 static bool
24098 {
24119 }
24121 /* Try to implement D using SVE SEL instruction. */
24123 static bool
24125 {
24151 /* Build a predicate that is true when op0 elements should be used. */
24154 {
24158 }
24162 /* TARGET = PRED ? OP0 : OP1. */
24165 }
24167 /* Recognize patterns suitable for the INS instructions. */
24168 static bool
24170 {
24177 /* to_constant is safe since this routine is specific to Advanced SIMD
24178 vectors. */
24185 {
24186 HOST_WIDE_INT elt;
24192 {
24195 }
24197 }
24200 {
24203 {
24209 }
24213 }
24223 {
24226 }
24239 }
24241 static bool
24243 {
24246 /* The pattern matching functions above are written to look for a small
24247 number to begin the sequence (0, 1, N/2). If we begin with an index
24248 from the second operand, we can swap the operands. */
24251 {
24254 }
24261 {
24263 {
24289 }
24290 else
24291 {
24294 }
24295 }
24297 }
24299 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
24301 static bool
24305 {
24308 /* Check whether the mask can be applied to a single vector. */
24313 {
24316 }
24318 {
24321 }
24322 else
24335 else
24347 }
24349 /* Implement TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST. */
24351 bool
24355 {
24366 /* SVE actually has a div operator, we may have gotten here through
24367 that route. */
24372 /* We can use the optimized pattern. */
24386 }
24388 /* Generate a byte permute mask for a register of mode MODE,
24389 which has NUNITS units. */
24391 rtx
24393 {
24394 /* We have to reverse each vector because we dont have
24395 a permuted load that can reverse-load according to ABI rules. */
24396 rtx mask;
24409 }
24411 /* Expand an SVE integer comparison using the SVE equivalent of:
24413 (set TARGET (CODE OP0 OP1)). */
24415 void
24417 {
24424 }
24426 /* Return the UNSPEC_COND_* code for comparison CODE. */
24428 static unsigned int
24430 {
24432 {
24449 }
24450 }
24452 /* Emit:
24454 (set TARGET (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24456 where <X> is the operation associated with comparison CODE.
24457 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24459 static void
24462 {
24468 }
24470 /* Emit the SVE equivalent of:
24472 (set TMP1 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X1>))
24473 (set TMP2 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X2>))
24474 (set TARGET (ior:PRED_MODE TMP1 TMP2))
24476 where <Xi> is the operation associated with comparison CODEi.
24477 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24479 static void
24482 {
24489 }
24491 /* Emit the SVE equivalent of:
24493 (set TMP (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24494 (set TARGET (not TMP))
24496 where <X> is the operation associated with comparison CODE.
24497 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24499 static void
24502 {
24507 }
24509 /* Expand an SVE floating-point comparison using the SVE equivalent of:
24511 (set TARGET (CODE OP0 OP1))
24513 If CAN_INVERT_P is true, the caller can also handle inverted results;
24514 return true if the result is in fact inverted. */
24516 bool
24519 {
24525 {
24527 /* UNORDERED has no immediate form. */
24529 /* fall through */
24536 {
24537 /* There is native support for the comparison. */
24540 }
24543 /* This is a trapping operation (LT or GT). */
24549 {
24550 /* This would trap for signaling NaNs. */
24555 }
24556 /* fall through */
24562 {
24563 /* Work out which elements are ordered. */
24569 /* Test the opposite condition for the ordered elements,
24570 then invert the result. */
24573 else
24576 {
24580 }
24584 }
24588 /* ORDERED has no immediate form. */
24594 }
24596 /* There is native support for the inverse comparison. */
24599 {
24602 }
24605 }
24607 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
24608 of the data being selected and CMP_MODE is the mode of the values being
24609 compared. */
24611 void
24614 {
24618 {
24622 }
24623 else
24628 /* The "false" value can only be zero if the "true" value is a constant. */
24635 }
24637 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
24638 true. However due to issues with register allocation it is preferable
24639 to avoid tieing integer scalar and FP scalar modes. Executing integer
24640 operations in general registers is better than treating them as scalar
24641 vector operations. This reduces latency and avoids redundant int<->FP
24642 moves. So tie modes if they are either the same class, or vector modes
24643 with other vector modes, vector structs or any scalar mode. */
24645 static bool
24647 {
24657 /* We specifically want to allow elements of "structure" modes to
24658 be tieable to the structure. This more general condition allows
24659 other rarer situations too. The reason we don't extend this to
24660 predicate modes is that there are no predicate structure modes
24661 nor any specific instructions for extracting part of a predicate
24662 register. */
24667 /* Also allow any scalar modes with vectors. */
24673 }
24675 /* Return a new RTX holding the result of moving POINTER forward by
24676 AMOUNT bytes. */
24678 static rtx
24680 {
24685 }
24687 /* Return a new RTX holding the result of moving POINTER forward by the
24688 size of the mode it points to. */
24690 static rtx
24692 {
24694 }
24696 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
24697 MODE bytes. */
24699 static void
24701 machine_mode mode)
24702 {
24703 /* Handle 256-bit memcpy separately. We do this by making 2 adjacent memory
24704 address copies using V4SImode so that we can use Q registers. */
24706 {
24710 /* "Cast" the pointers to the correct mode. */
24713 /* Emit the memcpy. */
24718 /* Move the pointers forward. */
24722 }
24726 /* "Cast" the pointers to the correct mode. */
24729 /* Emit the memcpy. */
24732 /* Move the pointers forward. */
24735 }
24737 /* Expand a cpymem using the MOPS extension. OPERANDS are taken
24738 from the cpymem pattern. Return true iff we succeeded. */
24739 static bool
24741 {
24745 /* All three registers are changed by the instruction, so each one
24746 must be a fresh pseudo. */
24755 }
24757 /* Expand cpymem, as if from a __builtin_memcpy. Return true if
24758 we succeed, otherwise return false, indicating that a libcall to
24759 memcpy should be emitted. */
24761 bool
24763 {
24767 rtx base;
24770 /* Variable-sized memcpy can go through the MOPS expansion if available. */
24776 /* Try to inline up to 256 bytes or use the MOPS threshold if available. */
24777 unsigned HOST_WIDE_INT max_copy_size
24782 /* Large constant-sized cpymem should go through MOPS when possible.
24783 It should be a win even for size optimization in the general case.
24784 For speed optimization the choice between MOPS and the SIMD sequence
24785 depends on the size of the copy, rather than number of instructions,
24786 alignment etc. */
24792 /* Default to 256-bit LDP/STP on large copies, however small copies, no SIMD
24793 support or slow 256-bit LDP/STP fall back to 128-bit chunks. */
24795 || !TARGET_SIMD
24800 /* Emit an inline load+store sequence and count the number of operations
24801 involved. We use a simple count of just the loads and stores emitted
24802 rather than rtx_insn count as all the pointer adjustments and reg copying
24803 in this function will get optimized away later in the pipeline. */
24813 /* Convert size to bits to make the rest of the code simpler. */
24817 {
24818 /* Find the largest mode in which to do the copy in without over reading
24819 or writing. */
24820 opt_scalar_int_mode mode_iter;
24829 /* Prefer Q-register accesses for the last bytes. */
24834 /* A single block copy is 1 load + 1 store. */
24838 /* Emit trailing copies using overlapping unaligned accesses
24839 (when !STRICT_ALIGNMENT) - this is smaller and faster. */
24841 {
24848 }
24849 }
24852 /* MOPS sequence requires 3 instructions for the memory copying + 1 to move
24853 the constant size into a register. */
24856 /* If MOPS is available at this point we don't consider the libcall as it's
24857 not a win even on code size. At this point only consider MOPS if
24858 optimizing for size. For speed optimizations we will have chosen between
24859 the two based on copy size already. */
24861 {
24866 }
24868 /* A memcpy libcall in the worst case takes 3 instructions to prepare the
24869 arguments + 1 for the call. When MOPS is not available and we're
24870 optimizing for size a libcall may be preferable. */
24877 }
24879 /* Like aarch64_copy_one_block_and_progress_pointers, except for memset where
24880 SRC is a register we have created with the duplicated value to be set. */
24881 static void
24883 machine_mode mode)
24884 {
24885 /* If we are copying 128bits or 256bits, we can do that straight from
24886 the SIMD register we prepared. */
24888 {
24890 /* "Cast" the *dst to the correct mode. */
24892 /* Emit the memset. */
24896 /* Move the pointers forward. */
24899 }
24901 {
24902 /* "Cast" the *dst to the correct mode. */
24904 /* Emit the memset. */
24906 /* Move the pointers forward. */
24909 }
24910 /* For copying less, we have to extract the right amount from src. */
24913 /* "Cast" the *dst to the correct mode. */
24915 /* Emit the memset. */
24917 /* Move the pointer forward. */
24919 }
24921 /* Expand a setmem using the MOPS instructions. OPERANDS are the same
24922 as for the setmem pattern. Return true iff we succeed. */
24923 static bool
24925 {
24929 /* The first two registers are changed by the instruction, so both
24930 of them must be a fresh pseudo. */
24939 }
24941 /* Expand setmem, as if from a __builtin_memset. Return true if
24942 we succeed, otherwise return false. */
24944 bool
24946 {
24951 rtx base;
24954 /* If we don't have SIMD registers or the size is variable use the MOPS
24955 inlined sequence if possible. */
24961 /* Default the maximum to 256-bytes when considering only libcall vs
24962 SIMD broadcast sequence. */
24970 /* The MOPS sequence takes:
24971 3 instructions for the memory storing
24972 + 1 to move the constant size into a reg
24973 + 1 if VAL is a non-zero constant to move into a reg
24974 (zero constants can use XZR directly). */
24976 /* A libcall to memset in the worst case takes 3 instructions to prepare
24977 the arguments + 1 for the call. */
24980 /* Upper bound check. For large constant-sized setmem use the MOPS sequence
24981 when available. */
24986 /* Attempt a sequence with a vector broadcast followed by stores.
24987 Count the number of operations involved to see if it's worth it
24988 against the alternatives. A simple counter simd_ops on the
24989 algorithmically-relevant operations is used rather than an rtx_insn count
24990 as all the pointer adjusmtents and mode reinterprets will be optimized
24991 away later. */
24998 /* Prepare the val using a DUP/MOVI v0.16B, val. */
25001 simd_ops++;
25002 /* Convert len to bits to make the rest of the code simpler. */
25005 /* Maximum amount to copy in one go. We allow 256-bit chunks based on the
25006 AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. */
25012 {
25013 /* Find the largest mode in which to do the copy without
25014 over writing. */
25015 opt_scalar_int_mode mode_iter;
25024 simd_ops++;
25027 /* Do certain trailing copies as overlapping if it's going to be
25028 cheaper. i.e. less instructions to do so. For instance doing a 15
25029 byte copy it's more efficient to do two overlapping 8 byte copies than
25030 8 + 4 + 2 + 1. Only do this when -mstrict-align is not supplied. */
25032 {
25038 }
25039 }
25044 {
25045 /* When optimizing for size we have 3 options: the SIMD broadcast sequence,
25046 call to memset or the MOPS expansion. */
25051 /* If MOPS is not available or not shorter pick a libcall if the SIMD
25052 sequence is too long. */
25057 }
25059 /* At this point the SIMD broadcast sequence is the best choice when
25060 optimizing for speed. */
25063 }
25066 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
25067 SImode stores. Handle the case when the constant has identical
25068 bottom and top halves. This is beneficial when the two stores can be
25069 merged into an STP and we avoid synthesising potentially expensive
25070 immediates twice. Return true if such a split is possible. */
25072 bool
25074 {
25083 unsigned int orig_cost
25085 unsigned int lo_cost
25088 /* We want to transform:
25089 MOV x1, 49370
25090 MOVK x1, 0x140, lsl 16
25091 MOVK x1, 0xc0da, lsl 32
25092 MOVK x1, 0x140, lsl 48
25093 STR x1, [x0]
25094 into:
25095 MOV w1, 49370
25096 MOVK w1, 0x140, lsl 16
25097 STP w1, w1, [x0]
25098 So we want to perform this only when we save two instructions
25099 or more. When optimizing for size, however, accept any code size
25100 savings we can. */
25115 /* Don't emit an explicit store pair as this may not be always profitable.
25116 Let the sched-fusion logic decide whether to merge them. */
25121 }
25123 /* Generate RTL for a conditional branch with rtx comparison CODE in
25124 mode CC_MODE. The destination of the unlikely conditional branch
25125 is LABEL_REF. */
25127 void
25129 rtx label_ref)
25130 {
25131 rtx x;
25134 const0_rtx);
25138 pc_rtx);
25140 }
25142 /* Generate DImode scratch registers for 128-bit (TImode) addition.
25144 OP1 represents the TImode destination operand 1
25145 OP2 represents the TImode destination operand 2
25146 LOW_DEST represents the low half (DImode) of TImode operand 0
25147 LOW_IN1 represents the low half (DImode) of TImode operand 1
25148 LOW_IN2 represents the low half (DImode) of TImode operand 2
25149 HIGH_DEST represents the high half (DImode) of TImode operand 0
25150 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25151 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
25153 void
25158 {
25167 }
25169 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
25171 This function differs from 'arch64_addti_scratch_regs' in that
25172 OP1 can be an immediate constant (zero). We must call
25173 subreg_highpart_offset with DImode and TImode arguments, otherwise
25174 VOIDmode will be used for the const_int which generates an internal
25175 error from subreg_size_highpart_offset which does not expect a size of zero.
25177 OP1 represents the TImode destination operand 1
25178 OP2 represents the TImode destination operand 2
25179 LOW_DEST represents the low half (DImode) of TImode operand 0
25180 LOW_IN1 represents the low half (DImode) of TImode operand 1
25181 LOW_IN2 represents the low half (DImode) of TImode operand 2
25182 HIGH_DEST represents the high half (DImode) of TImode operand 0
25183 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25184 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
25187 void
25192 {
25205 }
25207 /* Generate RTL for 128-bit (TImode) subtraction with overflow.
25209 OP0 represents the TImode destination operand 0
25210 LOW_DEST represents the low half (DImode) of TImode operand 0
25211 LOW_IN1 represents the low half (DImode) of TImode operand 1
25212 LOW_IN2 represents the low half (DImode) of TImode operand 2
25213 HIGH_DEST represents the high half (DImode) of TImode operand 0
25214 HIGH_IN1 represents the high half (DImode) of TImode operand 1
25215 HIGH_IN2 represents the high half (DImode) of TImode operand 2
25216 UNSIGNED_P is true if the operation is being performed on unsigned
25217 values. */
25218 void
25222 {
25224 {
25229 else
25231 }
25232 else
25233 {
25237 else
25238 {
25241 }
25246 else
25248 }
25253 }
25255 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
25257 static unsigned HOST_WIDE_INT
25259 {
25262 else
25264 }
25266 static rtx
25269 {
25273 insn_code icode;
25284 {
25312 }
25317 {
25320 }
25329 {
25332 }
25338 }
25340 static rtx
25343 {
25347 insn_code icode;
25359 {
25383 }
25390 {
25393 }
25401 {
25402 /* Treat the ccmp patterns as canonical and use them where possible,
25403 but fall back to ccmp_rev patterns if there's no other option. */
25412 else
25413 {
25416 }
25418 }
25429 {
25432 }
25438 }
25440 #undef TARGET_GEN_CCMP_FIRST
25441 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
25443 #undef TARGET_GEN_CCMP_NEXT
25444 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
25446 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
25447 instruction fusion of some sort. */
25449 static bool
25451 {
25453 }
25456 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
25457 should be kept together during scheduling. */
25459 static bool
25461 {
25462 rtx set_dest;
25465 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
25472 {
25473 /* We are trying to match:
25474 prev (mov) == (set (reg r0) (const_int imm16))
25475 curr (movk) == (set (zero_extract (reg r0)
25476 (const_int 16)
25477 (const_int 16))
25478 (const_int imm16_1)) */
25490 {
25492 }
25493 }
25496 {
25498 /* We're trying to match:
25499 prev (adrp) == (set (reg r1)
25500 (high (symbol_ref ("SYM"))))
25501 curr (add) == (set (reg r0)
25502 (lo_sum (reg r1)
25503 (symbol_ref ("SYM"))))
25504 Note that r0 need not necessarily be the same as r1, especially
25505 during pre-regalloc scheduling. */
25509 {
25517 }
25518 }
25521 {
25523 /* We're trying to match:
25524 prev (movk) == (set (zero_extract (reg r0)
25525 (const_int 16)
25526 (const_int 32))
25527 (const_int imm16_1))
25528 curr (movk) == (set (zero_extract (reg r0)
25529 (const_int 16)
25530 (const_int 48))
25531 (const_int imm16_2)) */
25547 }
25549 {
25550 /* We're trying to match:
25551 prev (adrp) == (set (reg r0)
25552 (high (symbol_ref ("SYM"))))
25553 curr (ldr) == (set (reg r1)
25554 (mem (lo_sum (reg r0)
25555 (symbol_ref ("SYM")))))
25556 or
25557 curr (ldr) == (set (reg r1)
25558 (zero_extend (mem
25559 (lo_sum (reg r0)
25560 (symbol_ref ("SYM")))))) */
25563 {
25576 }
25577 }
25579 /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */
25587 /* Fuse flag-setting ALU instructions and conditional branch. */
25590 {
25592 rtx cc_reg_1;
25597 && prev
25599 {
25602 /* FIXME: this misses some which is considered simple arthematic
25603 instructions for ThunderX. Simple shifts are missed here. */
25609 }
25610 }
25612 /* Fuse ALU instructions and CBZ/CBNZ. */
25614 && curr_set
25617 {
25618 /* We're trying to match:
25619 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
25620 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
25621 (const_int 0))
25622 (label_ref ("SYM"))
25623 (pc)) */
25630 {
25631 /* Fuse ALU operations followed by conditional branch instruction. */
25633 {
25654 }
25655 }
25656 }
25658 /* Fuse A+B+1 and A-B-1 */
25661 {
25662 /* We're trying to match:
25663 prev == (set (r0) (plus (r0) (r1)))
25664 curr == (set (r0) (plus (r0) (const_int 1)))
25665 or:
25666 prev == (set (r0) (minus (r0) (r1)))
25667 curr == (set (r0) (plus (r0) (const_int -1))) */
25683 }
25686 }
25688 /* Return true iff the instruction fusion described by OP is enabled. */
25690 bool
25692 {
25694 }
25696 /* If MEM is in the form of [base+offset], extract the two parts
25697 of address and set to BASE and OFFSET, otherwise return false
25698 after clearing BASE and OFFSET. */
25700 bool
25702 {
25703 rtx addr;
25710 {
25714 }
25718 {
25722 }
25728 }
25730 /* Types for scheduling fusion. */
25731 enum sched_fusion_type
25732 {
25734 SCHED_FUSION_LD_SIGN_EXTEND,
25735 SCHED_FUSION_LD_ZERO_EXTEND,
25736 SCHED_FUSION_LD,
25737 SCHED_FUSION_ST,
25738 SCHED_FUSION_NUM
25739 };
25741 /* If INSN is a load or store of address in the form of [base+offset],
25742 extract the two parts and set to BASE and OFFSET. Return scheduling
25743 fusion type this INSN is. */
25745 static enum sched_fusion_type
25747 {
25765 {
25770 }
25772 {
25777 }
25782 {
25785 }
25786 else
25793 }
25795 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
25797 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
25798 and PRI are only calculated for these instructions. For other instruction,
25799 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
25800 type instruction fusion can be added by returning different priorities.
25802 It's important that irrelevant instructions get the largest FUSION_PRI. */
25804 static void
25807 {
25817 {
25821 }
25823 /* Set FUSION_PRI according to fusion type and base register. */
25826 /* Calculate PRI. */
25829 /* INSN with smaller offset goes first. */
25833 else
25838 }
25840 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
25841 Adjust priority of sha1h instructions so they are scheduled before
25842 other SHA1 instructions. */
25844 static int
25846 {
25850 {
25855 }
25858 }
25860 /* If REVERSED is null, return true if memory reference *MEM2 comes
25861 immediately after memory reference *MEM1. Do not change the references
25862 in this case.
25864 Otherwise, check if *MEM1 and *MEM2 are consecutive memory references and,
25865 if they are, try to make them use constant offsets from the same base
25866 register. Return true on success. When returning true, set *REVERSED
25867 to true if *MEM1 comes after *MEM2, false if *MEM1 comes before *MEM2. */
25868 static bool
25870 {
25888 /* Make sure at least one memory is in base+offset form. */
25892 /* If both mems already use the same base register, just check the
25893 offsets. */
25895 {
25903 {
25906 }
25909 }
25911 /* Otherwise, check whether the MEM_EXPRs and MEM_OFFSETs together
25912 guarantee that the values are consecutive. */
25917 {
25918 poly_int64 expr_offset1;
25919 poly_int64 expr_offset2;
25925 || !expr_base2
25934 ;
25937 else
25941 {
25943 {
25947 }
25948 else
25949 {
25953 }
25954 }
25956 }
25959 }
25961 /* Return true if MEM1 and MEM2 can be combined into a single access
25962 of mode MODE, with the combined access having the same address as MEM1. */
25964 bool
25966 {
25970 }
25972 /* Given OPERANDS of consecutive load/store, check if we can merge
25973 them into ldp/stp. LOAD is true if they are load instructions.
25974 MODE is the mode of memory operands. */
25976 bool
25978 machine_mode mode)
25979 {
25984 {
25994 }
25995 else
25996 {
26001 }
26003 /* The mems cannot be volatile. */
26007 /* If we have SImode and slow unaligned ldp,
26008 check the alignment to be at least 8 byte. */
26012 && !optimize_size
26016 /* Check if the addresses are in the form of [base+offset]. */
26021 /* The operands must be of the same size. */
26025 /* One of the memory accesses must be a mempair operand.
26026 If it is not the first one, they need to be swapped by the
26027 peephole. */
26034 else
26039 else
26042 /* Check if the registers are of same class. */
26047 }
26049 /* Given OPERANDS of consecutive load/store that can be merged,
26050 swap them if they are not in ascending order. */
26051 void
26053 {
26061 {
26062 /* Irrespective of whether this is a load or a store,
26063 we do the same swap. */
26066 }
26067 }
26069 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
26070 comparison between the two. */
26071 int
26073 {
26076 }
26078 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
26079 other pointing to a REG rtx containing an offset, compare the offsets
26080 of the two pairs.
26082 Return:
26084 1 iff offset (X) > offset (Y)
26085 0 iff offset (X) == offset (Y)
26086 -1 iff offset (X) < offset (Y) */
26087 int
26089 {
26096 else
26101 else
26104 /* Extract the offsets. */
26111 }
26113 /* Given OPERANDS of consecutive load/store, check if we can merge
26114 them into ldp/stp by adjusting the offset. LOAD is true if they
26115 are load instructions. MODE is the mode of memory operands.
26117 Given below consecutive stores:
26119 str w1, [xb, 0x100]
26120 str w1, [xb, 0x104]
26121 str w1, [xb, 0x108]
26122 str w1, [xb, 0x10c]
26124 Though the offsets are out of the range supported by stp, we can
26125 still pair them after adjusting the offset, like:
26127 add scratch, xb, 0x100
26128 stp w1, w1, [scratch]
26129 stp w1, w1, [scratch, 0x8]
26131 The peephole patterns detecting this opportunity should guarantee
26132 the scratch register is avaliable. */
26134 bool
26136 machine_mode mode)
26137 {
26144 {
26146 {
26151 }
26153 /* Do not attempt to merge the loads if the loads clobber each other. */
26158 }
26159 else
26161 {
26164 }
26166 /* Skip if memory operand is by itself valid for ldp/stp. */
26171 {
26172 /* The mems cannot be volatile. */
26176 /* Check if the addresses are in the form of [base+offset]. */
26180 }
26182 /* Check if the registers are of same class. */
26188 {
26191 }
26192 else
26193 {
26196 }
26198 /* Only the last register in the order in which they occur
26199 may be clobbered by the load. */
26205 /* Check if the bases are same. */
26215 /* Check if the offsets can be put in the right order to do a ldp/stp. */
26217 aarch64_host_wide_int_compare);
26223 /* Check that offsets are within range of each other. The ldp/stp
26224 instructions have 7 bit immediate offsets, so use 0x80. */
26228 /* The offsets must be aligned with respect to each other. */
26232 /* If we have SImode and slow unaligned ldp,
26233 check the alignment to be at least 8 byte. */
26237 && !optimize_size
26242 }
26244 /* Given OPERANDS of consecutive load/store, this function pairs them
26245 into LDP/STP after adjusting the offset. It depends on the fact
26246 that the operands can be sorted so the offsets are correct for STP.
26247 MODE is the mode of memory operands. CODE is the rtl operator
26248 which should be applied to all memory operands, it's SIGN_EXTEND,
26249 ZERO_EXTEND or UNKNOWN. */
26251 bool
26254 {
26261 /* We make changes on a copy as we may still bail out. */
26265 /* Sort the operands. Note for cases as below:
26266 [base + 0x310] = A
26267 [base + 0x320] = B
26268 [base + 0x330] = C
26269 [base + 0x320] = D
26270 We need stable sorting otherwise wrong data may be store to offset 0x320.
26271 Also note the dead store in above case should be optimized away, but no
26272 guarantees here. */
26274 aarch64_ldrstr_offset_compare);
26276 /* Copy the memory operands so that if we have to bail for some
26277 reason the original addresses are unchanged. */
26279 {
26284 }
26285 else
26286 {
26292 }
26299 /* Adjust offset so it can fit in LDP/STP instruction. */
26307 /* The base offset is optimally half way between the two STP/LDP offsets. */
26310 else
26311 /* However, due to issues with negative LDP/STP offset generation for
26312 larger modes, for DF, DD, DI and vector modes. we must not use negative
26313 addresses smaller than 9 signed unadjusted bits can store. This
26314 provides the most range in this case. */
26317 /* Adjust the base so that it is aligned with the addresses but still
26318 optimal. */
26320 /* Fix the offset, bearing in mind we want to make it bigger not
26321 smaller. */
26324 /* The negative range of LDP/STP is one larger than the positive range. */
26327 /* Check if base offset is too big or too small. We can attempt to resolve
26328 this issue by setting it to the maximum value and seeing if the offsets
26329 still fit. */
26331 {
26333 /* We must still make sure that the base offset is aligned with respect
26334 to the address. But it may not be made any bigger. */
26336 }
26338 /* Likewise for the case where the base is too small. */
26340 {
26343 }
26345 /* Offset of the first STP/LDP. */
26348 /* Offset of the second STP/LDP. */
26351 /* The offsets must be within the range of the LDP/STP instructions. */
26370 {
26375 }
26377 {
26382 }
26385 {
26394 }
26395 else
26396 {
26405 }
26407 /* Emit adjusting instruction. */
26409 /* Emit ldp/stp instructions. */
26417 }
26419 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
26420 it isn't worth branching around empty masked ops (including masked
26421 stores). */
26423 static bool
26425 {
26427 }
26429 /* Return 1 if pseudo register should be created and used to hold
26430 GOT address for PIC code. */
26432 bool
26434 {
26436 }
26438 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
26440 static int
26442 {
26444 {
26451 }
26454 }
26457 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
26458 return the log2 of that value. Otherwise return -1. */
26460 int
26462 {
26477 }
26479 /* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
26480 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
26481 return n. Otherwise return -1. */
26483 int
26485 {
26486 REAL_VALUE_TYPE r0;
26494 {
26498 }
26500 }
26502 /* If X is a vector of equal CONST_DOUBLE values and that value is
26503 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
26505 int
26507 {
26525 }
26527 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
26528 to float.
26530 __fp16 always promotes through this hook.
26531 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
26532 through the generic excess precision logic rather than here. */
26534 static tree
26536 {
26542 }
26544 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
26546 static bool
26548 optimization_type opt_type)
26549 {
26551 {
26557 }
26558 }
26560 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
26562 static unsigned int
26565 {
26566 /* Polynomial invariant 1 == (VG / 2) - 1. */
26571 }
26573 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
26574 if MODE is HFmode, and punt to the generic implementation otherwise. */
26576 static bool
26578 {
26582 }
26584 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
26585 if MODE is HFmode, and punt to the generic implementation otherwise. */
26587 static bool
26589 {
26596 }
26598 /* Set the value of FLT_EVAL_METHOD.
26599 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
26601 0: evaluate all operations and constants, whose semantic type has at
26602 most the range and precision of type float, to the range and
26603 precision of float; evaluate all other operations and constants to
26604 the range and precision of the semantic type;
26606 N, where _FloatN is a supported interchange floating type
26607 evaluate all operations and constants, whose semantic type has at
26608 most the range and precision of _FloatN type, to the range and
26609 precision of the _FloatN type; evaluate all other operations and
26610 constants to the range and precision of the semantic type;
26612 If we have the ARMv8.2-A extensions then we support _Float16 in native
26613 precision, so we should set this to 16. Otherwise, we support the type,
26614 but want to evaluate expressions in float precision, so set this to
26615 0. */
26617 static enum flt_eval_method
26619 {
26621 {
26624 /* We can calculate either in 16-bit range and precision or
26625 32-bit range and precision. Make that decision based on whether
26626 we have native support for the ARMv8.2-A 16-bit floating-point
26627 instructions or not. */
26629 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
26636 }
26638 }
26640 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
26641 scheduled for speculative execution. Reject the long-running division
26642 and square-root instructions. */
26644 static bool
26646 {
26648 {
26666 }
26667 }
26669 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
26671 static int
26673 {
26677 /* PR_REGS isn't a useful pressure class because many predicate pseudo
26678 registers need to go in PR_LO_REGS at some point during their
26679 lifetime. Splitting it into two halves has the effect of making
26680 all predicates count against PR_LO_REGS, so that we try whenever
26681 possible to restrict the number of live predicates to 8. This
26682 greatly reduces the amount of spilling in certain loops. */
26686 }
26688 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
26690 static bool
26693 {
26710 /* Don't allow changes between predicate modes and other modes.
26711 Only predicate registers can hold predicate modes and only
26712 non-predicate registers can hold non-predicate modes, so any
26713 attempt to mix them would require a round trip through memory. */
26717 /* Don't allow changes between partial SVE modes and other modes.
26718 The contents of partial SVE modes are distributed evenly across
26719 the register, whereas GCC expects them to be clustered together. */
26723 /* Similarly reject changes between partial SVE modes that have
26724 different patterns of significant and insignificant bits. */
26730 /* Don't allow changes between partial and full Advanced SIMD structure
26731 modes. */
26736 {
26737 /* Don't allow changes between SVE modes and other modes that might
26738 be bigger than 128 bits. In particular, OImode, CImode and XImode
26739 divide into 128-bit quantities while SVE modes divide into
26740 BITS_PER_SVE_VECTOR quantities. */
26745 }
26748 {
26749 /* Don't allow changes between SVE data modes and non-SVE modes.
26750 See the comment at the head of aarch64-sve.md for details. */
26754 /* Don't allow changes in element size: lane 0 of the new vector
26755 would not then be lane 0 of the old vector. See the comment
26756 above aarch64_maybe_expand_sve_subreg_move for a more detailed
26757 description.
26759 In the worst case, this forces a register to be spilled in
26760 one mode and reloaded in the other, which handles the
26761 endianness correctly. */
26764 }
26766 }
26768 /* Implement TARGET_EARLY_REMAT_MODES. */
26770 static void
26772 {
26773 /* SVE values are not normally live across a call, so it should be
26774 worth doing early rematerialization even in VL-specific mode. */
26778 }
26780 /* Override the default target speculation_safe_value. */
26781 static rtx
26784 {
26785 /* Maybe we should warn if falling back to hard barriers. They are
26786 likely to be noticably more expensive than the alternative below. */
26798 }
26800 /* Implement TARGET_ESTIMATED_POLY_VALUE.
26801 Look into the tuning structure for an estimate.
26802 KIND specifies the type of requested estimate: min, max or likely.
26803 For cores with a known SVE width all three estimates are the same.
26804 For generic SVE tuning we want to distinguish the maximum estimate from
26805 the minimum and likely ones.
26806 The likely estimate is the same as the minimum in that case to give a
26807 conservative behavior of auto-vectorizing with SVE when it is a win
26808 even for 128-bit SVE.
26809 When SVE width information is available VAL.coeffs[1] is multiplied by
26810 the number of VQ chunks over the initial Advanced SIMD 128 bits. */
26812 static HOST_WIDE_INT
26814 poly_value_estimate_kind kind
26816 {
26819 /* If there is no core-specific information then the minimum and likely
26820 values are based on 128-bit vectors and the maximum is based on
26821 the architectural maximum of 2048 bits. */
26824 {
26830 }
26832 /* Allow sve_width to be a bitmask of different VL, treating the lowest
26833 as likely. This could be made more general if future -mtune options
26834 need it to be. */
26837 else
26840 /* If the core provides width information, use that. */
26843 }
26846 /* Return true for types that could be supported as SIMD return or
26847 argument types. */
26849 static bool
26851 {
26853 {
26856 }
26858 }
26860 /* Return true for types that currently are supported as SIMD return
26861 or argument types. */
26863 static bool
26865 {
26873 }
26875 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
26877 static int
26882 {
26886 poly_uint64 vec_bits;
26891 /* For now, SVE simdclones won't produce illegal simdlen, So only check
26892 const simdlens here. */
26898 {
26903 }
26908 {
26910 ;
26913 "GCC does not currently support mixed size types "
26917 "GCC does not currently support return type %qT "
26919 else
26922 ret_type);
26924 }
26932 {
26937 {
26939 ;
26942 "GCC does not currently support mixed size types "
26944 else
26946 "GCC does not currently support argument type %qT "
26949 }
26950 }
26956 {
26960 }
26961 else
26962 {
26965 /* For now, SVE simdclones won't produce illegal simdlen, So only check
26966 const simdlens here. */
26969 {
26972 "GCC does not currently support simdlen %wd for "
26976 }
26977 }
26981 }
26983 /* Implement TARGET_SIMD_CLONE_ADJUST. */
26985 static void
26987 {
26988 /* Add aarch64_vector_pcs target attribute to SIMD clones so they
26989 use the correct ABI. */
26994 }
26996 /* Implement TARGET_SIMD_CLONE_USABLE. */
26998 static int
27000 {
27002 {
27009 }
27010 }
27012 /* Implement TARGET_COMP_TYPE_ATTRIBUTES */
27014 static int
27016 {
27024 };
27035 }
27037 /* Implement TARGET_GET_MULTILIB_ABI_NAME */
27041 {
27045 }
27047 /* Implement TARGET_STACK_PROTECT_GUARD. In case of a
27048 global variable based guard use the default else
27049 return a null tree. */
27050 static tree
27052 {
27057 }
27059 /* Return the diagnostic message string if conversion from FROMTYPE to
27060 TOTYPE is not allowed, NULL otherwise. */
27064 {
27066 {
27067 /* Do no allow conversions to/from BFmode scalar types. */
27072 }
27074 /* Conversion allowed. */
27076 }
27078 /* Return the diagnostic message string if the unary operation OP is
27079 not permitted on TYPE, NULL otherwise. */
27083 {
27084 /* Reject all single-operand operations on BFmode except for &. */
27088 /* Operation allowed. */
27090 }
27092 /* Return the diagnostic message string if the binary operation OP is
27093 not permitted on TYPE1 and TYPE2, NULL otherwise. */
27097 const_tree type2)
27098 {
27099 /* Reject all 2-operand operations on BFmode. */
27112 /* Operation allowed. */
27114 }
27116 /* Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES. Here we tell the rest of the
27117 compiler that we automatically ignore the top byte of our pointers, which
27118 allows using -fsanitize=hwaddress. */
27119 bool
27121 {
27123 }
27125 /* Implement TARGET_ASM_FILE_END for AArch64. This adds the AArch64 GNU NOTE
27126 section at the end if needed. */
27127 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
27128 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
27129 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
27130 void
27132 {
27143 {
27144 /* Generate .note.gnu.property section. */
27148 /* PT_NOTE header: namesz, descsz, type.
27149 namesz = 4 ("GNU\0")
27150 descsz = 16 (Size of the program property array)
27151 [(12 + padding) * Number of array elements]
27152 type = 5 (NT_GNU_PROPERTY_TYPE_0). */
27158 /* PT_NOTE name. */
27161 /* PT_NOTE contents for NT_GNU_PROPERTY_TYPE_0:
27162 type = GNU_PROPERTY_AARCH64_FEATURE_1_AND
27163 datasz = 4
27164 data = feature_1_and. */
27169 /* Pad the size of the note to the required alignment. */
27171 }
27172 }
27173 #undef GNU_PROPERTY_AARCH64_FEATURE_1_PAC
27174 #undef GNU_PROPERTY_AARCH64_FEATURE_1_BTI
27175 #undef GNU_PROPERTY_AARCH64_FEATURE_1_AND
27177 /* Helper function for straight line speculation.
27178 Return what barrier should be emitted for straight line speculation
27179 mitigation.
27180 When not mitigating against straight line speculation this function returns
27181 an empty string.
27182 When mitigating against straight line speculation, use:
27183 * SB when the v8.5-A SB extension is enabled.
27184 * DSB+ISB otherwise. */
27187 {
27188 return mitigation_required
27191 }
27226 };
27228 /* Function to create a BLR thunk. This thunk is used to mitigate straight
27229 line speculation. Instead of a simple BLR that can be speculated past,
27230 we emit a BL to this thunk, and this thunk contains a BR to the relevant
27231 register. These thunks have the relevant speculation barries put after
27232 their indirect branch so that speculation is blocked.
27234 We use such a thunk so the speculation barriers are kept off the
27235 architecturally executed path in order to reduce the performance overhead.
27237 When optimizing for size we use stubs shared by the linked object.
27238 When optimizing for performance we emit stubs for each function in the hope
27239 that the branch predictor can better train on jumps specific for a given
27240 function. */
27241 rtx
27243 {
27246 {
27247 /* For the thunks shared between different functions in this compilation
27248 unit we use a named symbol -- this is just for users to more easily
27249 understand the generated assembly. */
27253 {
27254 /* Build a decl representing this function stub and record it for
27255 later. We build a decl here so we can use the GCC machinery for
27256 handling sections automatically (through `get_named_section` and
27257 `make_decl_one_only`). That saves us a lot of trouble handling
27258 the specifics of different output file formats. */
27262 NULL_TREE));
27272 }
27275 }
27281 }
27283 /* Helper function for aarch64_sls_emit_blr_function_thunks and
27284 aarch64_sls_emit_shared_blr_thunks below. */
27285 static void
27287 {
27288 /* Save in x16 and branch to that function so this transformation does
27289 not prevent jumping to `BTI c` instructions. */
27292 }
27294 /* Emit all BLR stubs for this particular function.
27295 Here we emit all the BLR stubs needed for the current function. Since we
27296 emit these stubs in a consecutive block we know there will be no speculation
27297 gadgets between each stub, and hence we only emit a speculation barrier at
27298 the end of the stub sequences.
27300 This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
27301 void
27303 {
27308 /* We must save and restore the current function section since this assembly
27309 is emitted at the end of the function. This means it can be emitted *just
27310 after* the cold section of a function. That cold part would be emitted in
27311 a different section. That switch would trigger a `.cfi_endproc` directive
27312 to be emitted in the original section and a `.cfi_startproc` directive to
27313 be emitted in the new section. Switching to the original section without
27314 restoring would mean that the `.cfi_endproc` emitted as a function ends
27315 would happen in a different section -- leaving an unmatched
27316 `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
27317 in the standard text section. */
27321 {
27330 }
27332 /* Can use the SB if needs be here, since this stub will only be used
27333 by the current function, and hence for the current target. */
27336 }
27338 /* Emit shared BLR stubs for the current compilation unit.
27339 Over the course of compiling this unit we may have converted some BLR
27340 instructions to a BL to a shared stub function. This is where we emit those
27341 stub functions.
27342 This function is for the stubs shared between different functions in this
27343 compilation unit. We share when optimizing for size instead of speed.
27345 This function is called through the TARGET_ASM_FILE_END hook. */
27346 void
27348 {
27353 {
27362 /* Only emits if the compiler is configured for an assembler that can
27363 handle visibility directives. */
27368 /* Use the most conservative target to ensure it can always be used by any
27369 function in the translation unit. */
27372 }
27373 }
27375 /* Implement TARGET_ASM_FILE_END. */
27376 void
27378 {
27380 /* Since this function will be called for the ASM_FILE_END hook, we ensure
27381 that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
27382 for FreeBSD) still gets called. */
27383 #ifdef TARGET_ASM_FILE_END
27385 #endif
27386 }
27390 {
27393 {
27396 }
27397 else
27400 }
27402 /* Target-specific selftests. */
27404 #if CHECKING_P
27408 /* Selftest for the RTL loader.
27409 Verify that the RTL loader copes with a dump from
27410 print_rtx_function. This is essentially just a test that class
27411 function_reader can handle a real dump, but it also verifies
27412 that lookup_reg_by_dump_name correctly handles hard regs.
27413 The presence of hard reg names in the dump means that the test is
27414 target-specific, hence it is in this file. */
27416 static void
27418 {
27430 /* Verify crtl->return_rtx. */
27434 }
27436 /* Test the fractional_cost class. */
27438 static void
27440 {
27527 }
27529 /* Run all target-specific selftests. */
27531 static void
27533 {
27536 }
27542 #undef TARGET_STACK_PROTECT_GUARD
27543 #define TARGET_STACK_PROTECT_GUARD aarch64_stack_protect_guard
27545 #undef TARGET_ADDRESS_COST
27546 #define TARGET_ADDRESS_COST aarch64_address_cost
27548 /* This hook will determines whether unnamed bitfields affect the alignment
27549 of the containing structure. The hook returns true if the structure
27550 should inherit the alignment requirements of an unnamed bitfield's
27551 type. */
27552 #undef TARGET_ALIGN_ANON_BITFIELD
27553 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
27555 #undef TARGET_ASM_ALIGNED_DI_OP
27558 #undef TARGET_ASM_ALIGNED_HI_OP
27561 #undef TARGET_ASM_ALIGNED_SI_OP
27564 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
27565 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
27566 hook_bool_const_tree_hwi_hwi_const_tree_true
27568 #undef TARGET_ASM_FILE_START
27569 #define TARGET_ASM_FILE_START aarch64_start_file
27571 #undef TARGET_ASM_OUTPUT_MI_THUNK
27572 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
27574 #undef TARGET_ASM_SELECT_RTX_SECTION
27575 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
27577 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
27578 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
27580 #undef TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY
27581 #define TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY aarch64_print_patchable_function_entry
27583 #undef TARGET_BUILD_BUILTIN_VA_LIST
27584 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
27586 #undef TARGET_CALLEE_COPIES
27587 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_arg_info_false
27589 #undef TARGET_CAN_ELIMINATE
27590 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
27592 #undef TARGET_CAN_INLINE_P
27593 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
27595 #undef TARGET_CANNOT_FORCE_CONST_MEM
27596 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
27598 #undef TARGET_CASE_VALUES_THRESHOLD
27599 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
27601 #undef TARGET_CONDITIONAL_REGISTER_USAGE
27602 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
27604 #undef TARGET_MEMBER_TYPE_FORCES_BLK
27605 #define TARGET_MEMBER_TYPE_FORCES_BLK aarch64_member_type_forces_blk
27607 /* Only the least significant bit is used for initialization guard
27608 variables. */
27609 #undef TARGET_CXX_GUARD_MASK_BIT
27610 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
27612 #undef TARGET_C_MODE_FOR_SUFFIX
27613 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
27615 #ifdef TARGET_BIG_ENDIAN_DEFAULT
27616 #undef TARGET_DEFAULT_TARGET_FLAGS
27617 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
27618 #endif
27620 #undef TARGET_CLASS_MAX_NREGS
27621 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
27623 #undef TARGET_BUILTIN_DECL
27624 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
27626 #undef TARGET_BUILTIN_RECIPROCAL
27627 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
27629 #undef TARGET_C_EXCESS_PRECISION
27630 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
27632 #undef TARGET_EXPAND_BUILTIN
27633 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
27635 #undef TARGET_EXPAND_BUILTIN_VA_START
27636 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
27638 #undef TARGET_FOLD_BUILTIN
27639 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
27641 #undef TARGET_FUNCTION_ARG
27642 #define TARGET_FUNCTION_ARG aarch64_function_arg
27644 #undef TARGET_FUNCTION_ARG_ADVANCE
27645 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
27647 #undef TARGET_FUNCTION_ARG_BOUNDARY
27648 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
27650 #undef TARGET_FUNCTION_ARG_PADDING
27651 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
27653 #undef TARGET_GET_RAW_RESULT_MODE
27654 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
27655 #undef TARGET_GET_RAW_ARG_MODE
27656 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
27658 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
27659 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
27661 #undef TARGET_FUNCTION_VALUE
27662 #define TARGET_FUNCTION_VALUE aarch64_function_value
27664 #undef TARGET_FUNCTION_VALUE_REGNO_P
27665 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
27667 #undef TARGET_GIMPLE_FOLD_BUILTIN
27668 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
27670 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
27671 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
27673 #undef TARGET_INIT_BUILTINS
27674 #define TARGET_INIT_BUILTINS aarch64_init_builtins
27676 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
27677 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
27678 aarch64_ira_change_pseudo_allocno_class
27680 #undef TARGET_LEGITIMATE_ADDRESS_P
27681 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
27683 #undef TARGET_LEGITIMATE_CONSTANT_P
27684 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
27686 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
27687 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
27688 aarch64_legitimize_address_displacement
27690 #undef TARGET_LIBGCC_CMP_RETURN_MODE
27691 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
27693 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
27694 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
27695 aarch64_libgcc_floating_mode_supported_p
27697 #undef TARGET_MANGLE_TYPE
27698 #define TARGET_MANGLE_TYPE aarch64_mangle_type
27700 #undef TARGET_INVALID_CONVERSION
27701 #define TARGET_INVALID_CONVERSION aarch64_invalid_conversion
27703 #undef TARGET_INVALID_UNARY_OP
27704 #define TARGET_INVALID_UNARY_OP aarch64_invalid_unary_op
27706 #undef TARGET_INVALID_BINARY_OP
27707 #define TARGET_INVALID_BINARY_OP aarch64_invalid_binary_op
27709 #undef TARGET_VERIFY_TYPE_CONTEXT
27710 #define TARGET_VERIFY_TYPE_CONTEXT aarch64_verify_type_context
27712 #undef TARGET_MEMORY_MOVE_COST
27713 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
27715 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
27716 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
27718 #undef TARGET_MUST_PASS_IN_STACK
27719 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
27721 /* This target hook should return true if accesses to volatile bitfields
27722 should use the narrowest mode possible. It should return false if these
27723 accesses should use the bitfield container type. */
27724 #undef TARGET_NARROW_VOLATILE_BITFIELD
27725 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
27727 #undef TARGET_OPTION_OVERRIDE
27728 #define TARGET_OPTION_OVERRIDE aarch64_override_options
27730 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
27731 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
27732 aarch64_override_options_after_change
27734 #undef TARGET_OFFLOAD_OPTIONS
27735 #define TARGET_OFFLOAD_OPTIONS aarch64_offload_options
27737 #undef TARGET_OPTION_RESTORE
27738 #define TARGET_OPTION_RESTORE aarch64_option_restore
27740 #undef TARGET_OPTION_PRINT
27741 #define TARGET_OPTION_PRINT aarch64_option_print
27743 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
27744 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
27746 #undef TARGET_SET_CURRENT_FUNCTION
27747 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
27749 #undef TARGET_PASS_BY_REFERENCE
27750 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
27752 #undef TARGET_PREFERRED_RELOAD_CLASS
27753 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
27755 #undef TARGET_SCHED_REASSOCIATION_WIDTH
27756 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
27758 #undef TARGET_PROMOTED_TYPE
27759 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
27761 #undef TARGET_SECONDARY_RELOAD
27762 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
27764 #undef TARGET_SECONDARY_MEMORY_NEEDED
27765 #define TARGET_SECONDARY_MEMORY_NEEDED aarch64_secondary_memory_needed
27767 #undef TARGET_SHIFT_TRUNCATION_MASK
27768 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
27770 #undef TARGET_SETUP_INCOMING_VARARGS
27771 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
27773 #undef TARGET_STRUCT_VALUE_RTX
27774 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
27776 #undef TARGET_REGISTER_MOVE_COST
27777 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
27779 #undef TARGET_RETURN_IN_MEMORY
27780 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
27782 #undef TARGET_RETURN_IN_MSB
27783 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
27785 #undef TARGET_RTX_COSTS
27786 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
27788 #undef TARGET_SCALAR_MODE_SUPPORTED_P
27789 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
27791 #undef TARGET_SCHED_ISSUE_RATE
27792 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
27794 #undef TARGET_SCHED_VARIABLE_ISSUE
27795 #define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue
27797 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
27798 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
27799 aarch64_sched_first_cycle_multipass_dfa_lookahead
27801 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
27802 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
27803 aarch64_first_cycle_multipass_dfa_lookahead_guard
27805 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
27806 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
27807 aarch64_get_separate_components
27809 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
27810 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
27811 aarch64_components_for_bb
27813 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
27814 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
27815 aarch64_disqualify_components
27817 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
27818 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
27819 aarch64_emit_prologue_components
27821 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
27822 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
27823 aarch64_emit_epilogue_components
27825 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
27826 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
27827 aarch64_set_handled_components
27829 #undef TARGET_TRAMPOLINE_INIT
27830 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
27832 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
27833 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
27835 #undef TARGET_VECTOR_MODE_SUPPORTED_P
27836 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
27838 #undef TARGET_COMPATIBLE_VECTOR_TYPES_P
27839 #define TARGET_COMPATIBLE_VECTOR_TYPES_P aarch64_compatible_vector_types_p
27841 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
27842 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
27843 aarch64_builtin_support_vector_misalignment
27845 #undef TARGET_ARRAY_MODE
27846 #define TARGET_ARRAY_MODE aarch64_array_mode
27848 #undef TARGET_ARRAY_MODE_SUPPORTED_P
27849 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
27851 #undef TARGET_VECTORIZE_CREATE_COSTS
27852 #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs
27854 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
27855 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
27856 aarch64_builtin_vectorization_cost
27858 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
27859 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
27861 #undef TARGET_VECTORIZE_BUILTINS
27862 #define TARGET_VECTORIZE_BUILTINS
27864 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
27865 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
27866 aarch64_autovectorize_vector_modes
27868 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
27869 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
27870 aarch64_atomic_assign_expand_fenv
27872 /* Section anchor support. */
27874 #undef TARGET_MIN_ANCHOR_OFFSET
27875 #define TARGET_MIN_ANCHOR_OFFSET -256
27877 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
27878 byte offset; we can do much more for larger data types, but have no way
27879 to determine the size of the access. We assume accesses are aligned. */
27880 #undef TARGET_MAX_ANCHOR_OFFSET
27881 #define TARGET_MAX_ANCHOR_OFFSET 4095
27883 #undef TARGET_VECTOR_ALIGNMENT
27884 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
27886 #undef TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST
27887 #define TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST \
27888 aarch64_vectorize_can_special_div_by_constant
27890 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
27891 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
27892 aarch64_vectorize_preferred_vector_alignment
27893 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
27894 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
27895 aarch64_simd_vector_alignment_reachable
27897 /* vec_perm support. */
27899 #undef TARGET_VECTORIZE_VEC_PERM_CONST
27900 #define TARGET_VECTORIZE_VEC_PERM_CONST \
27901 aarch64_vectorize_vec_perm_const
27903 #undef TARGET_VECTORIZE_RELATED_MODE
27904 #define TARGET_VECTORIZE_RELATED_MODE aarch64_vectorize_related_mode
27905 #undef TARGET_VECTORIZE_GET_MASK_MODE
27906 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
27907 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
27908 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
27909 aarch64_empty_mask_is_expensive
27910 #undef TARGET_PREFERRED_ELSE_VALUE
27911 #define TARGET_PREFERRED_ELSE_VALUE \
27912 aarch64_preferred_else_value
27914 #undef TARGET_INIT_LIBFUNCS
27915 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
27917 #undef TARGET_FIXED_CONDITION_CODE_REGS
27918 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
27920 #undef TARGET_FLAGS_REGNUM
27921 #define TARGET_FLAGS_REGNUM CC_REGNUM
27923 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
27924 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
27926 #undef TARGET_ASAN_SHADOW_OFFSET
27927 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
27929 #undef TARGET_LEGITIMIZE_ADDRESS
27930 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
27932 #undef TARGET_SCHED_CAN_SPECULATE_INSN
27933 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
27935 #undef TARGET_CAN_USE_DOLOOP_P
27936 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
27938 #undef TARGET_SCHED_ADJUST_PRIORITY
27939 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
27941 #undef TARGET_SCHED_MACRO_FUSION_P
27942 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
27944 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
27945 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
27947 #undef TARGET_SCHED_FUSION_PRIORITY
27948 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
27950 #undef TARGET_UNSPEC_MAY_TRAP_P
27951 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
27953 #undef TARGET_USE_PSEUDO_PIC_REG
27954 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
27956 #undef TARGET_PRINT_OPERAND
27957 #define TARGET_PRINT_OPERAND aarch64_print_operand
27959 #undef TARGET_PRINT_OPERAND_ADDRESS
27960 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
27962 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
27963 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA aarch64_output_addr_const_extra
27965 #undef TARGET_OPTAB_SUPPORTED_P
27966 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
27968 #undef TARGET_OMIT_STRUCT_RETURN_REG
27969 #define TARGET_OMIT_STRUCT_RETURN_REG true
27971 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
27972 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
27973 aarch64_dwarf_poly_indeterminate_value
27975 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
27976 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
27977 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
27979 #undef TARGET_HARD_REGNO_NREGS
27980 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
27981 #undef TARGET_HARD_REGNO_MODE_OK
27982 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
27984 #undef TARGET_MODES_TIEABLE_P
27985 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
27987 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
27988 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
27989 aarch64_hard_regno_call_part_clobbered
27991 #undef TARGET_INSN_CALLEE_ABI
27992 #define TARGET_INSN_CALLEE_ABI aarch64_insn_callee_abi
27994 #undef TARGET_CONSTANT_ALIGNMENT
27995 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
27997 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
27998 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
27999 aarch64_stack_clash_protection_alloca_probe_range
28001 #undef TARGET_COMPUTE_PRESSURE_CLASSES
28002 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
28004 #undef TARGET_CAN_CHANGE_MODE_CLASS
28005 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
28007 #undef TARGET_SELECT_EARLY_REMAT_MODES
28008 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
28010 #undef TARGET_SPECULATION_SAFE_VALUE
28011 #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value
28013 #undef TARGET_ESTIMATED_POLY_VALUE
28014 #define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
28016 #undef TARGET_ATTRIBUTE_TABLE
28017 #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
28019 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
28020 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
28021 aarch64_simd_clone_compute_vecsize_and_simdlen
28023 #undef TARGET_SIMD_CLONE_ADJUST
28024 #define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust
28026 #undef TARGET_SIMD_CLONE_USABLE
28027 #define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable
28029 #undef TARGET_COMP_TYPE_ATTRIBUTES
28030 #define TARGET_COMP_TYPE_ATTRIBUTES aarch64_comp_type_attributes
28032 #undef TARGET_GET_MULTILIB_ABI_NAME
28033 #define TARGET_GET_MULTILIB_ABI_NAME aarch64_get_multilib_abi_name
28035 #undef TARGET_FNTYPE_ABI
28036 #define TARGET_FNTYPE_ABI aarch64_fntype_abi
28038 #undef TARGET_MEMTAG_CAN_TAG_ADDRESSES
28039 #define TARGET_MEMTAG_CAN_TAG_ADDRESSES aarch64_can_tag_addresses
28041 #if CHECKING_P
28042 #undef TARGET_RUN_TARGET_SELFTESTS
28043 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
28046 #undef TARGET_ASM_POST_CFI_STARTPROC
28047 #define TARGET_ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
28049 #undef TARGET_STRICT_ARGUMENT_NAMING
28050 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
28052 #undef TARGET_MD_ASM_ADJUST
28053 #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
28055 #undef TARGET_ASM_FILE_END
28056 #define TARGET_ASM_FILE_END aarch64_asm_file_end
28058 #undef TARGET_ASM_FUNCTION_EPILOGUE
28059 #define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks
28061 #undef TARGET_HAVE_SHADOW_CALL_STACK
28062 #define TARGET_HAVE_SHADOW_CALL_STACK true