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1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #ifndef GCC_MCORE_H
24 #define GCC_MCORE_H
26 /* RBE: need to move these elsewhere. */
27 #undef LIKE_PPC_ABI
28 #define MCORE_STRUCT_ARGS
29 /* RBE: end of "move elsewhere". */
31 /* Run-time Target Specification. */
32 #define TARGET_MCORE
34 /* Get tree.c to declare a target-specific specialization of
35 merge_decl_attributes. */
36 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
38 /* Support the __declspec keyword by turning them into attributes.
39 We currently only support: dllexport and dllimport.
40 Note that the current way we do this may result in a collision with
41 predefined attributes later on. This can be solved by using one attribute,
42 say __declspec__, and passing args to it. The problem with that approach
43 is that args are not accumulated: each new appearance would clobber any
44 existing args. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
51 if (TARGET_LITTLE_END) \
53 else \
55 if (TARGET_M340) \
57 else \
59 } \
60 while (0)
62 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
63 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */
64 #undef CPP_SPEC
67 /* We don't have a -lg library, so don't put it in the list. */
68 #undef LIB_SPEC
71 #undef ASM_SPEC
74 #undef LINK_SPEC
77 /* Can only count on 16 bits of availability; change to long would affect
78 many architecture specific files (other architectures...). */
92 #define TARGET_DEFAULT \
93 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
95 #ifndef MULTILIB_DEFAULTS
97 #endif
99 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
100 /* The ability to have 4 byte alignment is being suppressed for now.
101 If this ability is reenabled, you must enable the definition below
102 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
103 #if 0
104 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
105 #else
106 #define TARGET_8ALIGN 1
107 #endif
108 #define TARGET_DIV (target_flags & DIV_BIT)
109 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
110 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
111 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
112 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
113 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
114 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
115 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
116 #define TARGET_M340 (target_flags & M340_BIT)
119 #define TARGET_SWITCHES \
163 }
167 /* Target specific options (as opposed to the switches above). */
170 #define TARGET_OPTIONS \
171 { \
174 }
176 /* The MCore ABI says that bitfields are unsigned by default. */
179 /* What options are we going to default to specific settings when
180 -O* happens; the user can subsequently override these settings.
182 Omitting the frame pointer is a very good idea on the MCore.
183 Scheduling isn't worth anything on the current MCore implementation. */
184 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
185 { \
186 if (LEVEL) \
187 { \
188 flag_no_function_cse = 1; \
189 flag_omit_frame_pointer = 1; \
190 \
191 if (LEVEL >= 2) \
192 { \
193 flag_caller_saves = 0; \
194 flag_schedule_insns = 0; \
195 flag_schedule_insns_after_reload = 0; \
196 } \
197 } \
198 if (SIZE) \
199 { \
200 target_flags &= ~ HARDLIT_BIT; \
201 } \
202 }
204 /* What options are we going to force to specific settings,
205 regardless of what the user thought he wanted.
206 We also use this for some post-processing of options. */
207 #define OVERRIDE_OPTIONS mcore_override_options ()
209 /* Target machine storage Layout. */
211 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
212 if (GET_MODE_CLASS (MODE) == MODE_INT \
213 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
214 { \
215 (MODE) = SImode; \
216 (UNSIGNEDP) = 1; \
217 }
219 /* Define this if most significant bit is lowest numbered
220 in instructions that operate on numbered bit-fields. */
221 #define BITS_BIG_ENDIAN 0
223 /* Define this if most significant byte of a word is the lowest numbered. */
224 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
226 /* Define this if most significant word of a multiword number is the lowest
227 numbered. */
228 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
230 #define LIBGCC2_WORDS_BIG_ENDIAN 1
231 #ifdef __MCORELE__
232 #undef LIBGCC2_WORDS_BIG_ENDIAN
233 #define LIBGCC2_WORDS_BIG_ENDIAN 0
234 #endif
236 #define MAX_BITS_PER_WORD 32
238 /* Width of a word, in units (bytes). */
239 #define UNITS_PER_WORD 4
241 /* A C expression for the size in bits of the type `long long' on the
242 target machine. If you don't define this, the default is two
243 words. */
244 #define LONG_LONG_TYPE_SIZE 64
246 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
247 #define PARM_BOUNDARY 32
249 /* Doubles must be aligned to an 8 byte boundary. */
250 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
251 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
252 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
254 /* Boundary (in *bits*) on which stack pointer should be aligned. */
255 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
257 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
259 #define STACK_UNITS_MAXSTEP 4096
261 /* Allocation boundary (in *bits*) for the code of a function. */
262 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
264 /* Alignment of field after `int : 0' in a structure. */
265 #define EMPTY_FIELD_BOUNDARY 32
267 /* No data type wants to be aligned rounder than this. */
268 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
270 /* The best alignment to use in cases where we have a choice. */
271 #define FASTEST_ALIGNMENT 32
273 /* Every structures size must be a multiple of 8 bits. */
274 #define STRUCTURE_SIZE_BOUNDARY 8
276 /* Look at the fundamental type that is used for a bit-field and use
277 that to impose alignment on the enclosing structure.
278 struct s {int a:8}; should have same alignment as "int", not "char". */
279 #define PCC_BITFIELD_TYPE_MATTERS 1
281 /* Largest integer machine mode for structures. If undefined, the default
282 is GET_MODE_SIZE(DImode). */
283 #define MAX_FIXED_MODE_SIZE 32
285 /* Make strings word-aligned so strcpy from constants will be faster. */
286 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
287 ((TREE_CODE (EXP) == STRING_CST \
288 && (ALIGN) < FASTEST_ALIGNMENT) \
289 ? FASTEST_ALIGNMENT : (ALIGN))
291 /* Make arrays of chars word-aligned for the same reasons. */
292 #define DATA_ALIGNMENT(TYPE, ALIGN) \
293 (TREE_CODE (TYPE) == ARRAY_TYPE \
294 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
295 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
297 /* Set this nonzero if move instructions will actually fail to work
298 when given unaligned data. */
299 #define STRICT_ALIGNMENT 1
301 /* Standard register usage. */
303 /* Register allocation for our first guess
305 r0 stack pointer
306 r1 scratch, target reg for xtrb?
307 r2-r7 arguments.
308 r8-r14 call saved
309 r15 link register
310 ap arg pointer (doesn't really exist, always eliminated)
311 c c bit
312 fp frame pointer (doesn't really exist, always eliminated)
313 x19 two control registers. */
315 /* Number of actual hardware registers.
316 The hardware registers are assigned numbers for the compiler
317 from 0 to just below FIRST_PSEUDO_REGISTER.
318 All registers that the compiler knows about must be given numbers,
319 even those that are not normally considered general registers.
321 MCore has 16 integer registers and 2 control registers + the arg
322 pointer. */
324 #define FIRST_PSEUDO_REGISTER 20
329 /* RBE: mcore.md depends on CC_REG being set to 17. */
333 /* Specify the registers used for certain standard purposes.
334 The values of these macros are register numbers. */
341 /* The assembler's names for the registers. RFP need not always be used as
342 the Real framepointer; it can also be used as a normal general register.
343 Note that the name `fp' is horribly misleading since `fp' is in fact only
344 the argument-and-return-context pointer. */
345 #define REGISTER_NAMES \
346 { \
350 }
352 /* 1 for registers that have pervasive standard uses
353 and are not available for the register allocator. */
354 #define FIXED_REGISTERS \
356 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
358 /* 1 for registers not available across function calls.
359 These must include the FIXED_REGISTERS and also any
360 registers that can be used without being saved.
361 The latter must include the registers where values are returned
362 and the register where structure-value addresses are passed.
363 Aside from that, you can include as many other registers as you like. */
365 /* RBE: r15 {link register} not available across calls,
366 But we don't mark it that way here.... */
367 #define CALL_USED_REGISTERS \
369 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
371 /* The order in which register should be allocated. */
372 #define REG_ALLOC_ORDER \
374 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
376 /* Return number of consecutive hard regs needed starting at reg REGNO
377 to hold something of mode MODE.
378 This is ordinarily the length in words of a value of mode MODE
379 but can be less for certain modes in special long registers.
381 On the MCore regs are UNITS_PER_WORD bits wide; */
382 #define HARD_REGNO_NREGS(REGNO, MODE) \
383 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
385 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
386 We may keep double values in even registers. */
387 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
388 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
390 /* Value is 1 if it is a good idea to tie two pseudo registers
391 when one has mode MODE1 and one has mode MODE2.
392 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
393 for any hard reg, then this must be 0 for correct output. */
394 #define MODES_TIEABLE_P(MODE1, MODE2) \
395 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
397 /* Value should be nonzero if functions must have frame pointers.
398 Zero means the frame pointer need not be set up (and parms may be accessed
399 via the stack pointer) in functions that seem suitable. */
400 #define FRAME_POINTER_REQUIRED 0
402 /* Definitions for register eliminations.
404 We have two registers that can be eliminated on the MCore. First, the
405 frame pointer register can often be eliminated in favor of the stack
406 pointer register. Secondly, the argument pointer register can always be
407 eliminated; it is replaced with either the stack or frame pointer. */
409 /* Base register for access to arguments of the function. */
410 #define ARG_POINTER_REGNUM 16
412 /* Register in which the static-chain is passed to a function. */
413 #define STATIC_CHAIN_REGNUM 1
415 /* This is an array of structures. Each structure initializes one pair
416 of eliminable registers. The "from" register number is given first,
417 followed by "to". Eliminations of the same "from" register are listed
418 in order of preference. */
419 #define ELIMINABLE_REGS \
420 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
421 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
422 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
424 /* Given FROM and TO register numbers, say whether this elimination
425 is allowed. */
426 #define CAN_ELIMINATE(FROM, TO) \
427 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
429 /* Define the offset between two registers, one to be eliminated, and the other
430 its replacement, at the start of a routine. */
431 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
432 OFFSET = mcore_initial_elimination_offset (FROM, TO)
434 /* Define the classes of registers for register constraints in the
435 machine description. Also define ranges of constants.
437 One of the classes must always be named ALL_REGS and include all hard regs.
438 If there is more than one class, another class must be named NO_REGS
439 and contain no registers.
441 The name GENERAL_REGS must be the name of a class (or an alias for
442 another name such as ALL_REGS). This is the class of registers
443 that is allowed by "g" or "r" in a register constraint.
444 Also, registers outside this class are allocated only when
445 instructions express preferences for them.
447 The classes must be numbered in nondecreasing order; that is,
448 a larger-numbered class must never be contained completely
449 in a smaller-numbered class.
451 For any two classes, it is very desirable that there be another
452 class that represents their union. */
454 /* The MCore has only general registers. There are
455 also some special purpose registers: the T bit register, the
456 procedure Link and the Count Registers. */
457 enum reg_class
458 {
459 NO_REGS,
460 ONLYR1_REGS,
461 LRW_REGS,
462 GENERAL_REGS,
463 C_REGS,
464 ALL_REGS,
465 LIM_REG_CLASSES
466 };
468 #define N_REG_CLASSES (int) LIM_REG_CLASSES
470 /* Give names of register classes as strings for dump file. */
471 #define REG_CLASS_NAMES \
472 { \
479 }
481 /* Define which registers fit in which classes.
482 This is an initializer for a vector of HARD_REG_SET
483 of length N_REG_CLASSES. */
485 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
486 #define REG_CLASS_CONTENTS \
487 { \
494 }
496 /* The same information, inverted:
497 Return the class number of the smallest class containing
498 reg number REGNO. This could be a conditional expression
499 or could index an array. */
502 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
504 /* When defined, the compiler allows registers explicitly used in the
505 rtl to be used as spill registers but prevents the compiler from
506 extending the lifetime of these registers. */
507 #define SMALL_REGISTER_CLASSES 1
509 /* The class value for index registers, and the one for base regs. */
510 #define INDEX_REG_CLASS NO_REGS
511 #define BASE_REG_CLASS GENERAL_REGS
513 /* Get reg_class from a letter such as appears in the machine
514 description. */
517 #define REG_CLASS_FROM_LETTER(C) \
520 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
521 can be used to stand for particular ranges of immediate operands.
522 This macro defines what the ranges are.
523 C is the letter, and VALUE is a constant value.
524 Return 1 if VALUE is in the range specified by C.
525 I: loadable by movi (0..127)
526 J: arithmetic operand 1..32
527 K: shift operand 0..31
528 L: negative arithmetic operand -1..-32
529 M: powers of two, constants loadable by bgeni
530 N: powers of two minus 1, constants loadable by bmaski, including -1
531 O: allowed by cmov with two constants +/- 1 of each other
532 P: values we will generate 'inline' -- without an 'lrw'
534 Others defined for use after reload
535 Q: constant 1
536 R: a label
537 S: 0/1/2 cleared bits out of 32 [for bclri's]
538 T: 2 set bits out of 32 [for bseti's]
539 U: constant 0
540 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
541 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
542 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
543 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
544 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
545 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
546 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
547 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
548 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
549 CONST_OK_FOR_M(VALUE) || \
550 CONST_OK_FOR_N(VALUE) || \
551 CONST_OK_FOR_M((int)(VALUE) - 1) || \
552 CONST_OK_FOR_N((int)(VALUE) + 1))
554 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
556 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
565 : 0)
567 /* Similar, but for floating constants, and defining letters G and H.
568 Here VALUE is the CONST_DOUBLE rtx itself. */
569 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
571 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
572 : 0)
574 /* Letters in the range `Q' through `U' in a register constraint string
575 may be defined in a machine-dependent fashion to stand for arbitrary
576 operand types. */
577 #define EXTRA_CONSTRAINT(OP, C) \
579 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
581 && mcore_num_zeros (INTVAL (OP)) <= 2) \
583 && mcore_num_ones (INTVAL (OP)) == 2) \
585 && INTVAL(OP) == 1) \
587 && INTVAL(OP) == 0) \
588 : 0)
590 /* Given an rtx X being reloaded into a reg required to be
591 in class CLASS, return the class of reg to actually use.
592 In general this is just CLASS; but on some machines
593 in some cases it is preferable to use a more restrictive class. */
594 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
596 /* Return the register class of a scratch register needed to copy IN into
597 or out of a register in CLASS in MODE. If it can be done directly,
598 NO_REGS is returned. */
599 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
600 mcore_secondary_reload_class (CLASS, MODE, X)
602 /* Return the maximum number of consecutive registers
603 needed to represent mode MODE in a register of class CLASS.
605 On MCore this is the size of MODE in words. */
606 #define CLASS_MAX_NREGS(CLASS, MODE) \
607 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
609 /* Stack layout; function entry, exit and calling. */
611 /* Define the number of register that can hold parameters.
612 These two macros are used only in other macro definitions below. */
613 #define NPARM_REGS 6
614 #define FIRST_PARM_REG 2
615 #define FIRST_RET_REG 2
617 /* Define this if pushing a word on the stack
618 makes the stack pointer a smaller address. */
619 #define STACK_GROWS_DOWNWARD
621 /* Offset within stack frame to start allocating local variables at.
622 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
623 first local allocated. Otherwise, it is the offset to the BEGINNING
624 of the first local allocated. */
625 #define STARTING_FRAME_OFFSET 0
627 /* If defined, the maximum amount of space required for outgoing arguments
628 will be computed and placed into the variable
629 `current_function_outgoing_args_size'. No space will be pushed
630 onto the stack for each call; instead, the function prologue should
631 increase the stack frame size by this amount. */
632 #define ACCUMULATE_OUTGOING_ARGS 1
634 /* Offset of first parameter from the argument pointer register value. */
635 #define FIRST_PARM_OFFSET(FNDECL) 0
637 /* Value is the number of byte of arguments automatically
638 popped when returning from a subroutine call.
639 FUNTYPE is the data type of the function (as a tree),
640 or for a library call it is an identifier node for the subroutine name.
641 SIZE is the number of bytes of arguments passed on the stack.
643 On the MCore, the callee does not pop any of its arguments that were passed
644 on the stack. */
645 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
647 /* Define how to find the value returned by a function.
648 VALTYPE is the data type of the value (as a tree).
649 If the precise function being called is known, FUNC is its FUNCTION_DECL;
650 otherwise, FUNC is 0. */
651 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
653 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
654 we want to retain compatibility with older gcc versions. */
655 #define DEFAULT_PCC_STRUCT_RETURN 0
657 /* Define how to find the value returned by a library function
658 assuming the value has mode MODE. */
659 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RET_REG)
661 /* 1 if N is a possible register number for a function value.
662 On the MCore, only r4 can return results. */
663 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
665 /* 1 if N is a possible register number for function argument passing. */
666 #define FUNCTION_ARG_REGNO_P(REGNO) \
667 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
669 /* Define a data type for recording info about an argument list
670 during the scan of that argument list. This data type should
671 hold all necessary information about the function itself
672 and about the args processed so far, enough to enable macros
673 such as FUNCTION_ARG to determine where the next arg should go.
675 On MCore, this is a single integer, which is a number of words
676 of arguments scanned so far (including the invisible argument,
677 if any, which holds the structure-value-address).
678 Thus NARGREGS or more means all following args should go on the stack. */
679 #define CUMULATIVE_ARGS int
681 #define ROUND_ADVANCE(SIZE) \
682 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
684 /* Round a register number up to a proper boundary for an arg of mode
685 MODE.
687 We round to an even reg for things larger than a word. */
688 #define ROUND_REG(X, MODE) \
689 ((TARGET_8ALIGN \
690 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
691 ? ((X) + ((X) & 1)) : (X))
694 /* Initialize a variable CUM of type CUMULATIVE_ARGS
695 for a call to a function whose data type is FNTYPE.
696 For a library call, FNTYPE is 0.
698 On MCore, the offset always starts at 0: the first parm reg is always
699 the same reg. */
700 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
701 ((CUM) = 0)
703 /* Update the data in CUM to advance over an argument
704 of mode MODE and data type TYPE.
705 (TYPE is null for libcalls where that information may not be
706 available.) */
707 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
708 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
709 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
711 /* Define where to put the arguments to a function. */
712 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
713 mcore_function_arg (CUM, MODE, TYPE, NAMED)
715 /* For an arg passed partly in registers and partly in memory,
716 this is the number of registers used.
717 For args passed entirely in registers or entirely in memory, zero.
718 Any arg that starts in the first NPARM_REGS regs but won't entirely
719 fit in them needs partial registers on the MCore. */
720 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
721 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
723 /* Call the function profiler with a given profile label. */
724 #define FUNCTION_PROFILER(STREAM,LABELNO) \
725 { \
729 }
731 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
732 the stack pointer does not matter. The value is tested only in
733 functions that have frame pointers.
734 No definition is equivalent to always zero. */
735 #define EXIT_IGNORE_STACK 0
737 /* Output assembler code for a block containing the constant parts
738 of a trampoline, leaving space for the variable parts.
740 On the MCore, the trampoline looks like:
741 lrw r1, function
742 lrw r13, area
743 jmp r13
744 or r0, r0
745 .literals */
746 #define TRAMPOLINE_TEMPLATE(FILE) \
747 { \
754 }
756 /* Length in units of the trampoline for entering a nested function. */
757 #define TRAMPOLINE_SIZE 12
759 /* Alignment required for a trampoline in bits. */
760 #define TRAMPOLINE_ALIGNMENT 32
762 /* Emit RTL insns to initialize the variable parts of a trampoline.
763 FNADDR is an RTX for the address of the function's pure code.
764 CXT is an RTX for the static chain value for the function. */
765 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
766 { \
767 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
768 (CXT)); \
769 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
770 (FNADDR)); \
771 }
773 /* Macros to check register numbers against specific register classes. */
775 /* These assume that REGNO is a hard or pseudo reg number.
776 They give nonzero only if REGNO is a hard reg of the suitable class
777 or a pseudo reg currently allocated to a suitable hard reg.
778 Since they use reg_renumber, they are safe only once reg_renumber
779 has been allocated, which happens in local-alloc.c. */
780 #define REGNO_OK_FOR_BASE_P(REGNO) \
781 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
783 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
785 /* Maximum number of registers that can appear in a valid memory
786 address. */
787 #define MAX_REGS_PER_ADDRESS 1
789 /* Recognize any constant value that is a valid address. */
790 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
792 /* Nonzero if the constant value X is a legitimate general operand.
793 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
795 On the MCore, allow anything but a double. */
796 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
798 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
799 and check its validity for a certain class.
800 We have two alternate definitions for each of them.
801 The usual definition accepts all pseudo regs; the other rejects
802 them unless they have been allocated suitable hard regs.
803 The symbol REG_OK_STRICT causes the latter definition to be used. */
804 #ifndef REG_OK_STRICT
806 /* Nonzero if X is a hard reg that can be used as a base reg
807 or if it is a pseudo reg. */
808 #define REG_OK_FOR_BASE_P(X) \
809 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
811 /* Nonzero if X is a hard reg that can be used as an index
812 or if it is a pseudo reg. */
813 #define REG_OK_FOR_INDEX_P(X) 0
815 #else
817 /* Nonzero if X is a hard reg that can be used as a base reg. */
818 #define REG_OK_FOR_BASE_P(X) \
819 REGNO_OK_FOR_BASE_P (REGNO (X))
821 /* Nonzero if X is a hard reg that can be used as an index. */
822 #define REG_OK_FOR_INDEX_P(X) 0
824 #endif
825 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
826 that is a valid memory address for an instruction.
827 The MODE argument is the machine mode for the MEM expression
828 that wants to use this address.
830 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
831 #define BASE_REGISTER_RTX_P(X) \
832 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
834 #define INDEX_REGISTER_RTX_P(X) \
835 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
838 /* Jump to LABEL if X is a valid address RTX. This must also take
839 REG_OK_STRICT into account when deciding about valid registers, but it uses
840 the above macros so we are in luck.
842 Allow REG
843 REG+disp
845 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
846 and for DI is 0..56 because we use two SI loads, etc. */
847 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
848 do \
849 { \
850 if (GET_CODE (OP) == CONST_INT) \
851 { \
852 if (GET_MODE_SIZE (MODE) >= 4 \
853 && (((unsigned)INTVAL (OP)) % 4) == 0 \
854 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
855 goto LABEL; \
856 if (GET_MODE_SIZE (MODE) == 2 \
857 && (((unsigned)INTVAL (OP)) % 2) == 0 \
858 && ((unsigned)INTVAL (OP)) <= 30) \
859 goto LABEL; \
860 if (GET_MODE_SIZE (MODE) == 1 \
861 && ((unsigned)INTVAL (OP)) <= 15) \
862 goto LABEL; \
863 } \
864 } \
865 while (0)
867 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
868 { \
869 if (BASE_REGISTER_RTX_P (X)) \
870 goto LABEL; \
871 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
872 { \
873 rtx xop0 = XEXP (X,0); \
874 rtx xop1 = XEXP (X,1); \
875 if (BASE_REGISTER_RTX_P (xop0)) \
876 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
877 if (BASE_REGISTER_RTX_P (xop1)) \
878 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
879 } \
880 }
882 /* Go to LABEL if ADDR (a legitimate address expression)
883 has an effect that depends on the machine mode it is used for. */
884 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
885 { \
886 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
887 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
888 goto LABEL; \
889 }
891 /* Specify the machine mode that this machine uses
892 for the index in the tablejump instruction. */
893 #define CASE_VECTOR_MODE SImode
895 /* 'char' is signed by default. */
896 #define DEFAULT_SIGNED_CHAR 0
898 /* The type of size_t unsigned int. */
901 /* Max number of bytes we can move from memory to memory
902 in one reasonably fast instruction. */
903 #define MOVE_MAX 4
905 /* Define if operations between registers always perform the operation
906 on the full register even if a narrower mode is specified. */
907 #define WORD_REGISTER_OPERATIONS
909 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
910 will either zero-extend or sign-extend. The value of this macro should
911 be the code that says which one of the two operations is implicitly
912 done, NIL if none. */
913 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
915 /* Nonzero if access to memory by bytes is slow and undesirable. */
916 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
918 /* Immediate shift counts are truncated by the output routines (or was it
919 the assembler?). Shift counts in a register are truncated by ARM. Note
920 that the native compiler puts too large (> 32) immediate shift counts
921 into a register and shifts by the register, letting the ARM decide what
922 to do instead of doing that itself. */
923 #define SHIFT_COUNT_TRUNCATED 1
925 /* All integers have the same format so truncation is easy. */
926 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
928 /* Define this if addresses of constant functions
929 shouldn't be put through pseudo regs where they can be cse'd.
930 Desirable on machines where ordinary constants are expensive
931 but a CALL with constant address is cheap. */
932 /* Why is this defined??? -- dac */
933 #define NO_FUNCTION_CSE 1
935 /* The machine modes of pointers and functions. */
936 #define Pmode SImode
937 #define FUNCTION_MODE Pmode
939 /* Compute extra cost of moving data between one register class
940 and another. All register moves are cheap. */
941 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
943 #define WORD_REGISTER_OPERATIONS
945 /* Assembler output control. */
953 /* Switch to the text or data segment. */
957 #undef EXTRA_SECTIONS
958 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
960 #undef EXTRA_SECTION_FUNCTIONS
961 #define EXTRA_SECTION_FUNCTIONS \
962 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
963 SWITCH_SECTION_FUNCTION
965 /* Switch to SECTION (an `enum in_section').
967 ??? This facility should be provided by GCC proper.
968 The problem is that we want to temporarily switch sections in
969 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
970 afterwards. */
971 #define SWITCH_SECTION_FUNCTION \
972 static void switch_to_section (enum in_section, tree); \
973 static void \
974 switch_to_section (enum in_section section, tree decl) \
975 { \
976 switch (section) \
977 { \
978 case in_text: text_section (); break; \
979 case in_data: data_section (); break; \
980 case in_named: named_section (decl, NULL, 0); break; \
981 SUBTARGET_SWITCH_SECTIONS \
982 default: abort (); break; \
983 } \
984 }
986 /* Switch into a generic section. */
987 #undef TARGET_ASM_NAMED_SECTION
988 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
990 /* This is how to output an insn to push a register on the stack.
991 It need not be very fast code. */
992 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
994 reg_names[STACK_POINTER_REGNUM], \
995 (STACK_BOUNDARY / BITS_PER_UNIT), \
996 reg_names[REGNO], \
997 reg_names[STACK_POINTER_REGNUM])
999 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1000 #define REG_PUSH_LENGTH 2
1002 /* This is how to output an insn to pop a register from the stack. */
1003 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1005 reg_names[REGNO], \
1006 reg_names[STACK_POINTER_REGNUM], \
1007 reg_names[STACK_POINTER_REGNUM], \
1008 (STACK_BOUNDARY / BITS_PER_UNIT))
1011 /* Output a reference to a label. */
1012 #undef ASM_OUTPUT_LABELREF
1013 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1015 (* targetm.strip_name_encoding) (NAME))
1017 /* This is how to output an assembler line
1018 that says to advance the location counter
1019 to a multiple of 2**LOG bytes. */
1020 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1021 if ((LOG) != 0) \
1024 #ifndef ASM_DECLARE_RESULT
1025 #define ASM_DECLARE_RESULT(FILE, RESULT)
1026 #endif
1028 #define MULTIPLE_SYMBOL_SPACES 1
1030 #define SUPPORTS_ONE_ONLY 1
1032 /* A pair of macros to output things for the callgraph data.
1033 VALUE means (to the tools that reads this info later):
1034 0 a call from src to dst
1035 1 the call is special (e.g. dst is "unknown" or "alloca")
1036 2 the call is special (e.g., the src is a table instead of routine)
1038 Frame sizes are augmented with timestamps to help later tools
1039 differentiate between static entities with same names in different
1040 files. */
1042 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1043 do \
1044 { \
1045 if (mcore_current_compilation_timestamp == 0) \
1046 mcore_current_compilation_timestamp = time (0); \
1048 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1049 } \
1050 while (0)
1052 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1053 do \
1054 { \
1056 (SRCNAME), (DSTNAME), (VALUE)); \
1057 } \
1058 while (0)
1060 /* Globalizing directive for a label. */
1063 /* The prefix to add to user-visible assembler symbols. */
1064 #undef USER_LABEL_PREFIX
1067 /* Make an internal label into a string. */
1068 #undef ASM_GENERATE_INTERNAL_LABEL
1069 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1072 /* Jump tables must be 32 bit aligned. */
1073 #undef ASM_OUTPUT_CASE_LABEL
1074 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1077 /* Output a relative address. Not needed since jump tables are absolute
1078 but we must define it anyway. */
1079 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1082 /* Output an element of a dispatch table. */
1083 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1086 /* Output various types of constants. */
1088 /* This is how to output an assembler line
1089 that says to advance the location counter by SIZE bytes. */
1090 #undef ASM_OUTPUT_SKIP
1091 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1094 /* This says how to output an assembler line
1095 to define a global common symbol, with alignment information. */
1096 /* XXX - for now we ignore the alignment. */
1097 #undef ASM_OUTPUT_ALIGNED_COMMON
1098 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1099 do \
1100 { \
1101 if (mcore_dllexport_name_p (NAME)) \
1102 MCORE_EXPORT_NAME (FILE, NAME) \
1103 if (! mcore_dllimport_name_p (NAME)) \
1104 { \
1106 assemble_name (FILE, NAME); \
1108 } \
1109 } \
1110 while (0)
1112 /* This says how to output an assembler line
1113 to define a local common symbol.... */
1114 #undef ASM_OUTPUT_LOCAL
1115 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1117 assemble_name (FILE, NAME), \
1120 /* ... and how to define a local common symbol whose alignment
1121 we wish to specify. ALIGN comes in as bits, we have to turn
1122 it into bytes. */
1123 #undef ASM_OUTPUT_ALIGNED_LOCAL
1124 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1125 do \
1126 { \
1128 assemble_name ((FILE), (NAME)); \
1130 } \
1131 while (0)
1133 /* Print operand X (an rtx) in assembler syntax to file FILE.
1134 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1135 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1136 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1138 /* Print a memory address as an operand to reference that memory location. */
1139 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1141 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1144 #define PREDICATE_CODES \