1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Maximum size we are allowed to grow the stack in a single operation.
50 If we want more, we must do it in increments of at most this size.
51 If this value is 0, we don't check at all. */
52 const char * mcore_stack_increment_string
= 0;
53 int mcore_stack_increment
= STACK_UNITS_MAXSTEP
;
55 /* For dumping information about frame sizes. */
56 char * mcore_current_function_name
= 0;
57 long mcore_current_compilation_timestamp
= 0;
59 /* Global variables for machine-dependent things. */
61 /* Saved operands from the last compare to use when we generate an scc
66 /* Provides the class number of the smallest class containing
68 const int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
70 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
71 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
72 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
73 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
74 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
77 /* Provide reg_class from a letter such as appears in the machine
79 const enum reg_class reg_class_from_letter
[] =
81 /* a */ LRW_REGS
, /* b */ ONLYR1_REGS
, /* c */ C_REGS
, /* d */ NO_REGS
,
82 /* e */ NO_REGS
, /* f */ NO_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
83 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ NO_REGS
, /* l */ NO_REGS
,
84 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
85 /* q */ NO_REGS
, /* r */ GENERAL_REGS
, /* s */ NO_REGS
, /* t */ NO_REGS
,
86 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ NO_REGS
, /* x */ ALL_REGS
,
87 /* y */ NO_REGS
, /* z */ NO_REGS
92 int arg_size
; /* Stdarg spills (bytes). */
93 int reg_size
; /* Non-volatile reg saves (bytes). */
94 int reg_mask
; /* Non-volatile reg saves. */
95 int local_size
; /* Locals. */
96 int outbound_size
; /* Arg overflow on calls out. */
100 /* Describe the steps we'll use to grow it. */
101 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
102 int growth
[MAX_STACK_GROWS
];
120 static void output_stack_adjust (int, int);
121 static int calc_live_regs (int *);
122 static int const_ok_for_mcore (int);
123 static int try_constant_tricks (long, int *, int *);
124 static const char * output_inline_const (enum machine_mode
, rtx
*);
125 static void block_move_sequence (rtx
, rtx
, rtx
, rtx
, int, int, int);
126 static void layout_mcore_frame (struct mcore_frame
*);
127 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int);
128 static cond_type
is_cond_candidate (rtx
);
129 static rtx
emit_new_cond_insn (rtx
, int);
130 static rtx
conditionalize_block (rtx
);
131 static void conditionalize_optimization (void);
132 static void mcore_reorg (void);
133 static rtx
handle_structs_in_regs (enum machine_mode
, tree
, int);
134 static void mcore_mark_dllexport (tree
);
135 static void mcore_mark_dllimport (tree
);
136 static int mcore_dllexport_p (tree
);
137 static int mcore_dllimport_p (tree
);
138 const struct attribute_spec mcore_attribute_table
[];
139 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
140 #ifdef OBJECT_FORMAT_ELF
141 static void mcore_asm_named_section (const char *,
144 static void mcore_unique_section (tree
, int);
145 static void mcore_encode_section_info (tree
, rtx
, int);
146 static const char *mcore_strip_name_encoding (const char *);
147 static int mcore_const_costs (rtx
, RTX_CODE
);
148 static int mcore_and_cost (rtx
);
149 static int mcore_ior_cost (rtx
);
150 static bool mcore_rtx_costs (rtx
, int, int, int *);
151 static void mcore_external_libcall (rtx
);
152 static bool mcore_return_in_memory (tree
, tree
);
155 /* Initialize the GCC target structure. */
156 #undef TARGET_ASM_EXTERNAL_LIBCALL
157 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
159 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
160 #undef TARGET_MERGE_DECL_ATTRIBUTES
161 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
164 #ifdef OBJECT_FORMAT_ELF
165 #undef TARGET_ASM_UNALIGNED_HI_OP
166 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
167 #undef TARGET_ASM_UNALIGNED_SI_OP
168 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
171 #undef TARGET_ATTRIBUTE_TABLE
172 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
173 #undef TARGET_ASM_UNIQUE_SECTION
174 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
175 #undef TARGET_ENCODE_SECTION_INFO
176 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
177 #undef TARGET_STRIP_NAME_ENCODING
178 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
179 #undef TARGET_RTX_COSTS
180 #define TARGET_RTX_COSTS mcore_rtx_costs
181 #undef TARGET_ADDRESS_COST
182 #define TARGET_ADDRESS_COST hook_int_rtx_0
183 #undef TARGET_MACHINE_DEPENDENT_REORG
184 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
186 #undef TARGET_PROMOTE_FUNCTION_ARGS
187 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
188 #undef TARGET_PROMOTE_FUNCTION_RETURN
189 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
190 #undef TARGET_PROMOTE_PROTOTYPES
191 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
193 #undef TARGET_RETURN_IN_MEMORY
194 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
195 #undef TARGET_MUST_PASS_IN_STACK
196 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
197 #undef TARGET_PASS_BY_REFERENCE
198 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
200 #undef TARGET_SETUP_INCOMING_VARARGS
201 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
203 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
204 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
206 struct gcc_target targetm
= TARGET_INITIALIZER
;
208 /* Adjust the stack and return the number of bytes taken to do it. */
210 output_stack_adjust (int direction
, int size
)
212 /* If extending stack a lot, we do it incrementally. */
213 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
215 rtx tmp
= gen_rtx_REG (SImode
, 1);
218 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
221 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
222 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
223 MEM_VOLATILE_P (memref
) = 1;
224 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
225 size
-= mcore_stack_increment
;
227 while (size
> mcore_stack_increment
);
229 /* SIZE is now the residual for the last adjustment,
230 which doesn't require a probe. */
236 rtx val
= GEN_INT (size
);
240 rtx nval
= gen_rtx_REG (SImode
, 1);
241 emit_insn (gen_movsi (nval
, val
));
246 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
248 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
254 /* Work out the registers which need to be saved,
255 both as a mask and a count. */
258 calc_live_regs (int * count
)
261 int live_regs_mask
= 0;
265 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
267 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
270 live_regs_mask
|= (1 << reg
);
274 return live_regs_mask
;
277 /* Print the operand address in x to the stream. */
280 mcore_print_operand_address (FILE * stream
, rtx x
)
282 switch (GET_CODE (x
))
285 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
290 rtx base
= XEXP (x
, 0);
291 rtx index
= XEXP (x
, 1);
293 if (GET_CODE (base
) != REG
)
295 /* Ensure that BASE is a register (one of them must be). */
301 switch (GET_CODE (index
))
304 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
305 reg_names
[REGNO(base
)], INTVAL (index
));
318 output_addr_const (stream
, x
);
323 /* Print operand x (an rtx) in assembler syntax to file stream
324 according to modifier code.
326 'R' print the next register or memory location along, ie the lsw in
328 'O' print a constant without the #
329 'M' print a constant as its negative
330 'P' print log2 of a power of two
331 'Q' print log2 of an inverse of a power of two
332 'U' print register for ldm/stm instruction
333 'X' print byte number for xtrbN instruction. */
336 mcore_print_operand (FILE * stream
, rtx x
, int code
)
342 fprintf (asm_out_file
, "32");
344 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
347 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
)));
350 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
353 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
356 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
359 /* Next location along in memory or register. */
360 switch (GET_CODE (x
))
363 fputs (reg_names
[REGNO (x
) + 1], (stream
));
366 mcore_print_operand_address
367 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
374 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
375 reg_names
[REGNO (x
) + 3]);
378 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
381 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
385 switch (GET_CODE (x
))
388 fputs (reg_names
[REGNO (x
)], (stream
));
391 output_address (XEXP (x
, 0));
394 output_addr_const (stream
, x
);
401 /* What does a constant cost ? */
404 mcore_const_costs (rtx exp
, enum rtx_code code
)
406 int val
= INTVAL (exp
);
408 /* Easy constants. */
409 if ( CONST_OK_FOR_I (val
)
410 || CONST_OK_FOR_M (val
)
411 || CONST_OK_FOR_N (val
)
412 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
415 && ( CONST_OK_FOR_M (~val
)
416 || CONST_OK_FOR_N (~val
)))
418 else if (code
== PLUS
419 && ( CONST_OK_FOR_I (-val
)
420 || CONST_OK_FOR_M (-val
)
421 || CONST_OK_FOR_N (-val
)))
427 /* What does an and instruction cost - we do this b/c immediates may
428 have been relaxed. We want to ensure that cse will cse relaxed immeds
429 out. Otherwise we'll get bad code (multiple reloads of the same const). */
432 mcore_and_cost (rtx x
)
436 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
439 val
= INTVAL (XEXP (x
, 1));
441 /* Do it directly. */
442 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
444 /* Takes one instruction to load. */
445 else if (const_ok_for_mcore (val
))
447 /* Takes two instructions to load. */
448 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
451 /* Takes a lrw to load. */
455 /* What does an or cost - see and_cost(). */
458 mcore_ior_cost (rtx x
)
462 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
465 val
= INTVAL (XEXP (x
, 1));
467 /* Do it directly with bclri. */
468 if (CONST_OK_FOR_M (val
))
470 /* Takes one instruction to load. */
471 else if (const_ok_for_mcore (val
))
473 /* Takes two instructions to load. */
474 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
477 /* Takes a lrw to load. */
482 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int * total
)
487 *total
= mcore_const_costs (x
, outer_code
);
499 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
503 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
512 *total
= COSTS_N_INSNS (100);
520 /* Check to see if a comparison against a constant can be made more efficient
521 by incrementing/decrementing the constant to get one that is more efficient
525 mcore_modify_comparison (enum rtx_code code
)
527 rtx op1
= arch_compare_op1
;
529 if (GET_CODE (op1
) == CONST_INT
)
531 int val
= INTVAL (op1
);
536 if (CONST_OK_FOR_J (val
+ 1))
538 arch_compare_op1
= GEN_INT (val
+ 1);
551 /* Prepare the operands for a comparison. */
554 mcore_gen_compare_reg (enum rtx_code code
)
556 rtx op0
= arch_compare_op0
;
557 rtx op1
= arch_compare_op1
;
558 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
560 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
561 op1
= force_reg (SImode
, op1
);
563 /* cmpnei: 0-31 (K immediate)
564 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
567 case EQ
: /* Use inverted condition, cmpne. */
571 case NE
: /* Use normal condition, cmpne. */
572 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
573 op1
= force_reg (SImode
, op1
);
576 case LE
: /* Use inverted condition, reversed cmplt. */
580 case GT
: /* Use normal condition, reversed cmplt. */
581 if (GET_CODE (op1
) == CONST_INT
)
582 op1
= force_reg (SImode
, op1
);
585 case GE
: /* Use inverted condition, cmplt. */
589 case LT
: /* Use normal condition, cmplt. */
590 if (GET_CODE (op1
) == CONST_INT
&&
591 /* covered by btsti x,31. */
593 ! CONST_OK_FOR_J (INTVAL (op1
)))
594 op1
= force_reg (SImode
, op1
);
597 case GTU
: /* Use inverted condition, cmple. */
598 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) == 0)
600 /* Unsigned > 0 is the same as != 0, but we need
601 to invert the condition, so we want to set
602 code = EQ. This cannot be done however, as the
603 mcore does not support such a test. Instead we
604 cope with this case in the "bgtu" pattern itself
605 so we should never reach this point. */
613 case LEU
: /* Use normal condition, reversed cmphs. */
614 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
615 op1
= force_reg (SImode
, op1
);
618 case LTU
: /* Use inverted condition, cmphs. */
622 case GEU
: /* Use normal condition, cmphs. */
623 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
624 op1
= force_reg (SImode
, op1
);
631 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
637 mcore_symbolic_address_p (rtx x
)
639 switch (GET_CODE (x
))
646 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
647 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
648 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
655 mcore_call_address_operand (rtx x
, enum machine_mode mode
)
657 return register_operand (x
, mode
) || CONSTANT_P (x
);
660 /* Functions to output assembly code for a function call. */
663 mcore_output_call (rtx operands
[], int index
)
665 static char buffer
[20];
666 rtx addr
= operands
[index
];
672 if (mcore_current_function_name
== 0)
675 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
679 sprintf (buffer
, "jsr\t%%%d", index
);
685 if (mcore_current_function_name
== 0)
688 if (GET_CODE (addr
) != SYMBOL_REF
)
691 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, XSTR (addr
, 0), 0);
694 sprintf (buffer
, "jbsr\t%%%d", index
);
700 /* Can we load a constant with a single instruction ? */
703 const_ok_for_mcore (int value
)
705 if (value
>= 0 && value
<= 127)
708 /* Try exact power of two. */
709 if ((value
& (value
- 1)) == 0)
712 /* Try exact power of two - 1. */
713 if ((value
& (value
+ 1)) == 0)
719 /* Can we load a constant inline with up to 2 instructions ? */
722 mcore_const_ok_for_inline (long value
)
726 return try_constant_tricks (value
, & x
, & y
) > 0;
729 /* Are we loading the constant using a not ? */
732 mcore_const_trick_uses_not (long value
)
736 return try_constant_tricks (value
, & x
, & y
) == 2;
739 /* Try tricks to load a constant inline and return the trick number if
740 success (0 is non-inlinable).
743 1: single instruction (do the usual thing)
744 2: single insn followed by a 'not'
745 3: single insn followed by a subi
746 4: single insn followed by an addi
747 5: single insn followed by rsubi
748 6: single insn followed by bseti
749 7: single insn followed by bclri
750 8: single insn followed by rotli
751 9: single insn followed by lsli
752 10: single insn followed by ixh
753 11: single insn followed by ixw. */
756 try_constant_tricks (long value
, int * x
, int * y
)
759 unsigned bit
, shf
, rot
;
761 if (const_ok_for_mcore (value
))
762 return 1; /* Do the usual thing. */
766 if (const_ok_for_mcore (~value
))
772 for (i
= 1; i
<= 32; i
++)
774 if (const_ok_for_mcore (value
- i
))
782 if (const_ok_for_mcore (value
+ i
))
793 for (i
= 0; i
<= 31; i
++)
795 if (const_ok_for_mcore (i
- value
))
803 if (const_ok_for_mcore (value
& ~bit
))
811 if (const_ok_for_mcore (value
| bit
))
825 for (i
= 1; i
< 31; i
++)
829 /* MCore has rotate left. */
833 rot
|= c
; /* Simulate rotate. */
835 if (const_ok_for_mcore (rot
))
844 shf
= 0; /* Can't use logical shift, low order bit is one. */
848 if (shf
!= 0 && const_ok_for_mcore (shf
))
857 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
864 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
875 /* Check whether reg is dead at first. This is done by searching ahead
876 for either the next use (i.e., reg is live), a death note, or a set of
877 reg. Don't just use dead_or_set_p() since reload does not always mark
878 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
879 can ignore subregs by extracting the actual register. BRC */
882 mcore_is_dead (rtx first
, rtx reg
)
886 /* For mcore, subregs can't live independently of their parent regs. */
887 if (GET_CODE (reg
) == SUBREG
)
888 reg
= SUBREG_REG (reg
);
890 /* Dies immediately. */
891 if (dead_or_set_p (first
, reg
))
894 /* Look for conclusive evidence of live/death, otherwise we have
895 to assume that it is live. */
896 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
898 if (GET_CODE (insn
) == JUMP_INSN
)
899 return 0; /* We lose track, assume it is alive. */
901 else if (GET_CODE(insn
) == CALL_INSN
)
903 /* Call's might use it for target or register parms. */
904 if (reg_referenced_p (reg
, PATTERN (insn
))
905 || find_reg_fusage (insn
, USE
, reg
))
907 else if (dead_or_set_p (insn
, reg
))
910 else if (GET_CODE (insn
) == INSN
)
912 if (reg_referenced_p (reg
, PATTERN (insn
)))
914 else if (dead_or_set_p (insn
, reg
))
919 /* No conclusive evidence either way, we can not take the chance
920 that control flow hid the use from us -- "I'm not dead yet". */
924 /* Count the number of ones in mask. */
927 mcore_num_ones (int mask
)
929 /* A trick to count set bits recently posted on comp.compilers. */
930 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
931 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
932 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
933 mask
= ((mask
>> 8) + mask
);
935 return (mask
+ (mask
>> 16)) & 0xff;
938 /* Count the number of zeros in mask. */
941 mcore_num_zeros (int mask
)
943 return 32 - mcore_num_ones (mask
);
946 /* Determine byte being masked. */
949 mcore_byte_offset (unsigned int mask
)
951 if (mask
== 0x00ffffffL
)
953 else if (mask
== 0xff00ffffL
)
955 else if (mask
== 0xffff00ffL
)
957 else if (mask
== 0xffffff00L
)
963 /* Determine halfword being masked. */
966 mcore_halfword_offset (unsigned int mask
)
968 if (mask
== 0x0000ffffL
)
970 else if (mask
== 0xffff0000L
)
976 /* Output a series of bseti's corresponding to mask. */
979 mcore_output_bseti (rtx dst
, int mask
)
984 out_operands
[0] = dst
;
986 for (bit
= 0; bit
< 32; bit
++)
988 if ((mask
& 0x1) == 0x1)
990 out_operands
[1] = GEN_INT (bit
);
992 output_asm_insn ("bseti\t%0,%1", out_operands
);
1000 /* Output a series of bclri's corresponding to mask. */
1003 mcore_output_bclri (rtx dst
, int mask
)
1005 rtx out_operands
[2];
1008 out_operands
[0] = dst
;
1010 for (bit
= 0; bit
< 32; bit
++)
1012 if ((mask
& 0x1) == 0x0)
1014 out_operands
[1] = GEN_INT (bit
);
1016 output_asm_insn ("bclri\t%0,%1", out_operands
);
1025 /* Output a conditional move of two constants that are +/- 1 within each
1026 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1027 really worth the effort. */
1030 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1034 rtx out_operands
[4];
1036 out_operands
[0] = operands
[0];
1038 /* Check to see which constant is loadable. */
1039 if (const_ok_for_mcore (INTVAL (operands
[1])))
1041 out_operands
[1] = operands
[1];
1042 out_operands
[2] = operands
[2];
1044 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1046 out_operands
[1] = operands
[2];
1047 out_operands
[2] = operands
[1];
1049 /* Complement test since constants are swapped. */
1050 cmp_t
= (cmp_t
== 0);
1052 load_value
= INTVAL (out_operands
[1]);
1053 adjust_value
= INTVAL (out_operands
[2]);
1055 /* First output the test if folded into the pattern. */
1058 output_asm_insn (test
, operands
);
1060 /* Load the constant - for now, only support constants that can be
1061 generated with a single instruction. maybe add general inlinable
1062 constants later (this will increase the # of patterns since the
1063 instruction sequence has a different length attribute). */
1064 if (load_value
>= 0 && load_value
<= 127)
1065 output_asm_insn ("movi\t%0,%1", out_operands
);
1066 else if ((load_value
& (load_value
- 1)) == 0)
1067 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1068 else if ((load_value
& (load_value
+ 1)) == 0)
1069 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1071 /* Output the constant adjustment. */
1072 if (load_value
> adjust_value
)
1075 output_asm_insn ("decf\t%0", out_operands
);
1077 output_asm_insn ("dect\t%0", out_operands
);
1082 output_asm_insn ("incf\t%0", out_operands
);
1084 output_asm_insn ("inct\t%0", out_operands
);
1090 /* Outputs the peephole for moving a constant that gets not'ed followed
1091 by an and (i.e. combine the not and the and into andn). BRC */
1094 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1097 rtx out_operands
[3];
1098 const char * load_op
;
1101 if (try_constant_tricks (INTVAL (operands
[1]), &x
, &y
) != 2)
1104 out_operands
[0] = operands
[0];
1105 out_operands
[1] = GEN_INT(x
);
1106 out_operands
[2] = operands
[2];
1108 if (x
>= 0 && x
<= 127)
1109 load_op
= "movi\t%0,%1";
1111 /* Try exact power of two. */
1112 else if ((x
& (x
- 1)) == 0)
1113 load_op
= "bgeni\t%0,%P1";
1115 /* Try exact power of two - 1. */
1116 else if ((x
& (x
+ 1)) == 0)
1117 load_op
= "bmaski\t%0,%N1";
1120 load_op
= "BADMOVI\t%0,%1";
1122 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1123 output_asm_insn (buf
, out_operands
);
1128 /* Output an inline constant. */
1131 output_inline_const (enum machine_mode mode
, rtx operands
[])
1135 rtx out_operands
[3];
1138 const char *dst_fmt
;
1141 value
= INTVAL (operands
[1]);
1143 if ((trick_no
= try_constant_tricks (value
, &x
, &y
)) == 0)
1145 /* lrw's are handled separately: Large inlinable constants
1146 never get turned into lrw's. Our caller uses try_constant_tricks
1147 to back off to an lrw rather than calling this routine. */
1154 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1155 out_operands
[0] = operands
[0];
1156 out_operands
[1] = GEN_INT (x
);
1159 out_operands
[2] = GEN_INT (y
);
1161 /* Select dst format based on mode. */
1162 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1167 if (x
>= 0 && x
<= 127)
1168 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1170 /* Try exact power of two. */
1171 else if ((x
& (x
- 1)) == 0)
1172 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1174 /* Try exact power of two - 1. */
1175 else if ((x
& (x
+ 1)) == 0)
1176 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1179 sprintf (load_op
, "BADMOVI\t%s,%%1", dst_fmt
);
1184 strcpy (buf
, load_op
);
1187 sprintf (buf
, "%s\n\tnot\t%s\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1190 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1193 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1196 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1197 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1200 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1203 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1206 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1209 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op
, dst_fmt
, value
, value
);
1212 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1215 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1221 output_asm_insn (buf
, out_operands
);
1226 /* Output a move of a word or less value. */
1229 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1230 enum machine_mode mode ATTRIBUTE_UNUSED
)
1232 rtx dst
= operands
[0];
1233 rtx src
= operands
[1];
1235 if (GET_CODE (dst
) == REG
)
1237 if (GET_CODE (src
) == REG
)
1239 if (REGNO (src
) == CC_REG
) /* r-c */
1242 return "mov\t%0,%1"; /* r-r*/
1244 else if (GET_CODE (src
) == MEM
)
1246 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1247 return "lrw\t%0,[%1]"; /* a-R */
1249 switch (GET_MODE (src
)) /* r-m */
1252 return "ldw\t%0,%1";
1254 return "ld.h\t%0,%1";
1256 return "ld.b\t%0,%1";
1261 else if (GET_CODE (src
) == CONST_INT
)
1265 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1266 return "movi\t%0,%1";
1267 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1268 return "bgeni\t%0,%P1\t// %1 %x1";
1269 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1270 return "bmaski\t%0,%N1\t// %1 %x1";
1271 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1272 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1274 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1277 return "lrw\t%0, %1"; /* Into the literal pool. */
1279 else if (GET_CODE (dst
) == MEM
) /* m-r */
1280 switch (GET_MODE (dst
))
1283 return "stw\t%1,%0";
1285 return "st.h\t%1,%0";
1287 return "st.b\t%1,%0";
1295 /* Return a sequence of instructions to perform DI or DF move.
1296 Since the MCORE cannot move a DI or DF in one instruction, we have
1297 to take care when we see overlapping source and dest registers. */
1300 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1302 rtx dst
= operands
[0];
1303 rtx src
= operands
[1];
1305 if (GET_CODE (dst
) == REG
)
1307 if (GET_CODE (src
) == REG
)
1309 int dstreg
= REGNO (dst
);
1310 int srcreg
= REGNO (src
);
1312 /* Ensure the second source not overwritten. */
1313 if (srcreg
+ 1 == dstreg
)
1314 return "mov %R0,%R1\n\tmov %0,%1";
1316 return "mov %0,%1\n\tmov %R0,%R1";
1318 else if (GET_CODE (src
) == MEM
)
1320 rtx memexp
= memexp
= XEXP (src
, 0);
1321 int dstreg
= REGNO (dst
);
1324 if (GET_CODE (memexp
) == LABEL_REF
)
1325 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1326 else if (GET_CODE (memexp
) == REG
)
1327 basereg
= REGNO (memexp
);
1328 else if (GET_CODE (memexp
) == PLUS
)
1330 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1331 basereg
= REGNO (XEXP (memexp
, 0));
1332 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1333 basereg
= REGNO (XEXP (memexp
, 1));
1340 /* ??? length attribute is wrong here. */
1341 if (dstreg
== basereg
)
1343 /* Just load them in reverse order. */
1344 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1346 /* XXX: alternative: move basereg to basereg+1
1347 and then fall through. */
1350 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1352 else if (GET_CODE (src
) == CONST_INT
)
1354 if (TARGET_LITTLE_END
)
1356 if (CONST_OK_FOR_I (INTVAL (src
)))
1357 output_asm_insn ("movi %0,%1", operands
);
1358 else if (CONST_OK_FOR_M (INTVAL (src
)))
1359 output_asm_insn ("bgeni %0,%P1", operands
);
1360 else if (INTVAL (src
) == -1)
1361 output_asm_insn ("bmaski %0,32", operands
);
1362 else if (CONST_OK_FOR_N (INTVAL (src
)))
1363 output_asm_insn ("bmaski %0,%N1", operands
);
1367 if (INTVAL (src
) < 0)
1368 return "bmaski %R0,32";
1370 return "movi %R0,0";
1374 if (CONST_OK_FOR_I (INTVAL (src
)))
1375 output_asm_insn ("movi %R0,%1", operands
);
1376 else if (CONST_OK_FOR_M (INTVAL (src
)))
1377 output_asm_insn ("bgeni %R0,%P1", operands
);
1378 else if (INTVAL (src
) == -1)
1379 output_asm_insn ("bmaski %R0,32", operands
);
1380 else if (CONST_OK_FOR_N (INTVAL (src
)))
1381 output_asm_insn ("bmaski %R0,%N1", operands
);
1385 if (INTVAL (src
) < 0)
1386 return "bmaski %0,32";
1394 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1395 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1400 /* Predicates used by the templates. */
1402 /* Nonzero if OP can be source of a simple move operation. */
1405 mcore_general_movsrc_operand (rtx op
, enum machine_mode mode
)
1407 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
1408 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1411 return general_operand (op
, mode
);
1414 /* Nonzero if OP can be destination of a simple move operation. */
1417 mcore_general_movdst_operand (rtx op
, enum machine_mode mode
)
1419 if (GET_CODE (op
) == REG
&& REGNO (op
) == CC_REG
)
1422 return general_operand (op
, mode
);
1425 /* Nonzero if OP is a normal arithmetic register. */
1428 mcore_arith_reg_operand (rtx op
, enum machine_mode mode
)
1430 if (! register_operand (op
, mode
))
1433 if (GET_CODE (op
) == SUBREG
)
1434 op
= SUBREG_REG (op
);
1436 if (GET_CODE (op
) == REG
)
1437 return REGNO (op
) != CC_REG
;
1442 /* Nonzero if OP should be recognized during reload for an ixh/ixw
1443 operand. See the ixh/ixw patterns. */
1446 mcore_reload_operand (rtx op
, enum machine_mode mode
)
1448 if (mcore_arith_reg_operand (op
, mode
))
1451 if (! reload_in_progress
)
1454 return GET_CODE (op
) == MEM
;
1457 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1460 mcore_arith_J_operand (rtx op
, enum machine_mode mode
)
1462 if (register_operand (op
, mode
))
1465 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
1471 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1474 mcore_arith_K_operand (rtx op
, enum machine_mode mode
)
1476 if (register_operand (op
, mode
))
1479 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
1485 /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
1488 mcore_arith_K_operand_not_0 (rtx op
, enum machine_mode mode
)
1490 if (register_operand (op
, mode
))
1493 if ( GET_CODE (op
) == CONST_INT
1494 && CONST_OK_FOR_K (INTVAL (op
))
1495 && INTVAL (op
) != 0)
1502 mcore_arith_K_S_operand (rtx op
, enum machine_mode mode
)
1504 if (register_operand (op
, mode
))
1507 if (GET_CODE (op
) == CONST_INT
)
1509 if (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_M (~INTVAL (op
)))
1517 mcore_arith_S_operand (rtx op
)
1519 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1526 mcore_arith_M_operand (rtx op
, enum machine_mode mode
)
1528 if (register_operand (op
, mode
))
1531 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
1537 /* Nonzero if OP is a valid source operand for loading. */
1540 mcore_arith_imm_operand (rtx op
, enum machine_mode mode
)
1542 if (register_operand (op
, mode
))
1545 if (GET_CODE (op
) == CONST_INT
&& const_ok_for_mcore (INTVAL (op
)))
1552 mcore_arith_any_imm_operand (rtx op
, enum machine_mode mode
)
1554 if (register_operand (op
, mode
))
1557 if (GET_CODE (op
) == CONST_INT
)
1563 /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
1566 mcore_arith_O_operand (rtx op
, enum machine_mode mode
)
1568 if (register_operand (op
, mode
))
1571 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
)))
1577 /* Nonzero if OP is a valid source operand for a btsti. */
1580 mcore_literal_K_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1582 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
1588 /* Nonzero if OP is a valid source operand for an add/sub insn. */
1591 mcore_addsub_operand (rtx op
, enum machine_mode mode
)
1593 if (register_operand (op
, mode
))
1596 if (GET_CODE (op
) == CONST_INT
)
1600 /* The following is removed because it precludes large constants from being
1601 returned as valid source operands for and add/sub insn. While large
1602 constants may not directly be used in an add/sub, they may if first loaded
1603 into a register. Thus, this predicate should indicate that they are valid,
1604 and the constraint in mcore.md should control whether an additional load to
1605 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
1607 if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
1615 /* Nonzero if OP is a valid source operand for a compare operation. */
1618 mcore_compare_operand (rtx op
, enum machine_mode mode
)
1620 if (register_operand (op
, mode
))
1623 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
1629 /* Expand insert bit field. BRC */
1632 mcore_expand_insv (rtx operands
[])
1634 int width
= INTVAL (operands
[1]);
1635 int posn
= INTVAL (operands
[2]);
1637 rtx mreg
, sreg
, ereg
;
1639 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1640 for width==1 must be removed. Look around line 368. This is something
1641 we really want the md part to do. */
1642 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1644 /* Do directly with bseti or bclri. */
1645 /* RBE: 2/97 consider only low bit of constant. */
1646 if ((INTVAL(operands
[3])&1) == 0)
1648 mask
= ~(1 << posn
);
1649 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1650 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1655 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1656 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1662 /* Look at some bit-field placements that we aren't interested
1663 in handling ourselves, unless specifically directed to do so. */
1664 if (! TARGET_W_FIELD
)
1665 return 0; /* Generally, give up about now. */
1667 if (width
== 8 && posn
% 8 == 0)
1668 /* Byte sized and aligned; let caller break it up. */
1671 if (width
== 16 && posn
% 16 == 0)
1672 /* Short sized and aligned; let caller break it up. */
1675 /* The general case - we can do this a little bit better than what the
1676 machine independent part tries. This will get rid of all the subregs
1677 that mess up constant folding in combine when working with relaxed
1680 /* If setting the entire field, do it directly. */
1681 if (GET_CODE (operands
[3]) == CONST_INT
&&
1682 INTVAL (operands
[3]) == ((1 << width
) - 1))
1684 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1685 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1686 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1690 /* Generate the clear mask. */
1691 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1693 /* Clear the field, to overlay it later with the source. */
1694 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1695 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1697 /* If the source is constant 0, we've nothing to add back. */
1698 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1701 /* XXX: Should we worry about more games with constant values?
1702 We've covered the high profile: set/clear single-bit and many-bit
1703 fields. How often do we see "arbitrary bit pattern" constants? */
1704 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1706 /* Extract src as same width as dst (needed for signed values). We
1707 always have to do this since we widen everything to SImode.
1708 We don't have to mask if we're shifting this up against the
1709 MSB of the register (e.g., the shift will push out any hi-order
1711 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1713 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1714 emit_insn (gen_rtx_SET (SImode
, sreg
,
1715 gen_rtx_AND (SImode
, sreg
, ereg
)));
1718 /* Insert source value in dest. */
1720 emit_insn (gen_rtx_SET (SImode
, sreg
,
1721 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1723 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1724 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1729 /* Return 1 if OP is a load multiple operation. It is known to be a
1730 PARALLEL and the first section will be tested. */
1733 mcore_load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1735 int count
= XVECLEN (op
, 0);
1740 /* Perform a quick check so we don't blow up below. */
1742 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
1743 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
1744 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
1747 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
1748 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
1750 for (i
= 1; i
< count
; i
++)
1752 rtx elt
= XVECEXP (op
, 0, i
);
1754 if (GET_CODE (elt
) != SET
1755 || GET_CODE (SET_DEST (elt
)) != REG
1756 || GET_MODE (SET_DEST (elt
)) != SImode
1757 || REGNO (SET_DEST (elt
)) != (unsigned) (dest_regno
+ i
)
1758 || GET_CODE (SET_SRC (elt
)) != MEM
1759 || GET_MODE (SET_SRC (elt
)) != SImode
1760 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
1761 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
1762 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
1763 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
1770 /* Similar, but tests for store multiple. */
1773 mcore_store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1775 int count
= XVECLEN (op
, 0);
1780 /* Perform a quick check so we don't blow up below. */
1782 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
1783 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
1784 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
1787 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
1788 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
1790 for (i
= 1; i
< count
; i
++)
1792 rtx elt
= XVECEXP (op
, 0, i
);
1794 if (GET_CODE (elt
) != SET
1795 || GET_CODE (SET_SRC (elt
)) != REG
1796 || GET_MODE (SET_SRC (elt
)) != SImode
1797 || REGNO (SET_SRC (elt
)) != (unsigned) (src_regno
+ i
)
1798 || GET_CODE (SET_DEST (elt
)) != MEM
1799 || GET_MODE (SET_DEST (elt
)) != SImode
1800 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
1801 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
1802 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
1803 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
1810 /* ??? Block move stuff stolen from m88k. This code has not been
1811 verified for correctness. */
1813 /* Emit code to perform a block move. Choose the best method.
1815 OPERANDS[0] is the destination.
1816 OPERANDS[1] is the source.
1817 OPERANDS[2] is the size.
1818 OPERANDS[3] is the alignment safe to use. */
1820 /* Emit code to perform a block move with an offset sequence of ldw/st
1821 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1822 known constants. DEST and SRC are registers. OFFSET is the known
1823 starting point for the output pattern. */
1825 static const enum machine_mode mode_from_align
[] =
1827 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1828 VOIDmode
, VOIDmode
, VOIDmode
, DImode
1832 block_move_sequence (rtx dest
, rtx dst_mem
, rtx src
, rtx src_mem
,
1833 int size
, int align
, int offset
)
1836 enum machine_mode mode
[2];
1841 int offset_ld
= offset
;
1842 int offset_st
= offset
;
1844 active
[0] = active
[1] = FALSE
;
1846 /* Establish parameters for the first load and for the second load if
1847 it is known to be the same mode as the first. */
1848 amount
[0] = amount
[1] = align
;
1850 mode
[0] = mode_from_align
[align
];
1852 temp
[0] = gen_reg_rtx (mode
[0]);
1854 if (size
>= 2 * align
)
1857 temp
[1] = gen_reg_rtx (mode
[1]);
1869 /* Change modes as the sequence tails off. */
1870 if (size
< amount
[next
])
1872 amount
[next
] = (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1873 mode
[next
] = mode_from_align
[amount
[next
]];
1874 temp
[next
] = gen_reg_rtx (mode
[next
]);
1877 size
-= amount
[next
];
1878 srcp
= gen_rtx_MEM (
1880 MEM_IN_STRUCT_P (src_mem
) ? mode
[next
] : BLKmode
,
1884 gen_rtx_PLUS (Pmode
, src
, GEN_INT (offset_ld
)));
1886 RTX_UNCHANGING_P (srcp
) = RTX_UNCHANGING_P (src_mem
);
1887 MEM_VOLATILE_P (srcp
) = MEM_VOLATILE_P (src_mem
);
1888 MEM_IN_STRUCT_P (srcp
) = 1;
1889 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], srcp
));
1890 offset_ld
+= amount
[next
];
1891 active
[next
] = TRUE
;
1896 active
[phase
] = FALSE
;
1898 dstp
= gen_rtx_MEM (
1900 MEM_IN_STRUCT_P (dst_mem
) ? mode
[phase
] : BLKmode
,
1904 gen_rtx_PLUS (Pmode
, dest
, GEN_INT (offset_st
)));
1906 RTX_UNCHANGING_P (dstp
) = RTX_UNCHANGING_P (dst_mem
);
1907 MEM_VOLATILE_P (dstp
) = MEM_VOLATILE_P (dst_mem
);
1908 MEM_IN_STRUCT_P (dstp
) = 1;
1909 emit_insn (gen_rtx_SET (VOIDmode
, dstp
, temp
[phase
]));
1910 offset_st
+= amount
[phase
];
1913 while (active
[next
]);
1917 mcore_expand_block_move (rtx dst_mem
, rtx src_mem
, rtx
* operands
)
1919 int align
= INTVAL (operands
[3]);
1922 if (GET_CODE (operands
[2]) == CONST_INT
)
1924 bytes
= INTVAL (operands
[2]);
1931 /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before
1932 we give up and go to memcpy. */
1933 if ((align
== 4 && (bytes
<= 4*4
1934 || ((bytes
& 01) == 0 && bytes
<= 8*4)
1935 || ((bytes
& 03) == 0 && bytes
<= 16*4)))
1936 || (align
== 2 && bytes
<= 4*2)
1937 || (align
== 1 && bytes
<= 4*1))
1939 block_move_sequence (operands
[0], dst_mem
, operands
[1], src_mem
,
1945 /* If we get here, just use the library routine. */
1946 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0, VOIDmode
, 3,
1947 operands
[0], Pmode
, operands
[1], Pmode
, operands
[2],
1952 /* Code to generate prologue and epilogue sequences. */
1953 static int number_of_regs_before_varargs
;
1955 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1956 for a varargs function. */
1957 static int current_function_anonymous_args
;
1959 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1960 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1961 #define ADDI_REACH (32) /* Maximum addi operand. */
1964 layout_mcore_frame (struct mcore_frame
* infp
)
1973 unsigned int growths
;
1976 /* Might have to spill bytes to re-assemble a big argument that
1977 was passed partially in registers and partially on the stack. */
1978 nbytes
= current_function_pretend_args_size
;
1980 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1981 if (current_function_anonymous_args
)
1982 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1984 infp
->arg_size
= nbytes
;
1986 /* How much space to save non-volatile registers we stomp. */
1987 infp
->reg_mask
= calc_live_regs (& n
);
1988 infp
->reg_size
= n
* 4;
1990 /* And the rest of it... locals and space for overflowed outbounds. */
1991 infp
->local_size
= get_frame_size ();
1992 infp
->outbound_size
= current_function_outgoing_args_size
;
1994 /* Make sure we have a whole number of words for the locals. */
1995 if (infp
->local_size
% STACK_BYTES
)
1996 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1998 /* Only thing we know we have to pad is the outbound space, since
1999 we've aligned our locals assuming that base of locals is aligned. */
2000 infp
->pad_local
= 0;
2002 infp
->pad_outbound
= 0;
2003 if (infp
->outbound_size
% STACK_BYTES
)
2004 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
2006 /* Now we see how we want to stage the prologue so that it does
2007 the most appropriate stack growth and register saves to either:
2009 (2) reduce instruction space, or
2010 (3) reduce stack space. */
2011 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
2012 infp
->growth
[i
] = 0;
2014 regarg
= infp
->reg_size
+ infp
->arg_size
;
2015 localregarg
= infp
->local_size
+ regarg
;
2016 localreg
= infp
->local_size
+ infp
->reg_size
;
2017 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
2020 /* XXX: Consider one where we consider localregarg + outbound too! */
2022 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
2023 use stw's with offsets and buy the frame in one shot. */
2024 if (localregarg
<= ADDI_REACH
2025 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
2027 /* Make sure we'll be aligned. */
2028 if (localregarg
% STACK_BYTES
)
2029 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
2031 step
= localregarg
+ infp
->pad_reg
;
2032 infp
->reg_offset
= infp
->local_size
;
2034 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
2037 infp
->reg_offset
+= outbounds
;
2041 infp
->arg_offset
= step
- 4;
2042 infp
->growth
[growths
++] = step
;
2043 infp
->reg_growth
= growths
;
2044 infp
->local_growth
= growths
;
2046 /* If we haven't already folded it in. */
2048 infp
->growth
[growths
++] = outbounds
;
2053 /* Frame can't be done with a single subi, but can be done with 2
2054 insns. If the 'stm' is getting <= 2 registers, we use stw's and
2055 shift some of the stack purchase into the first subi, so both are
2056 single instructions. */
2057 if (localregarg
<= STORE_REACH
2058 && (infp
->local_size
> ADDI_REACH
)
2059 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
2063 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
2064 if (localregarg
% STACK_BYTES
)
2065 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
2067 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
2068 step
= ADDI_REACH
; /* As much up front as we can. */
2072 /* XXX: Consider whether step will still be aligned; we believe so. */
2073 infp
->arg_offset
= step
- 4;
2074 infp
->growth
[growths
++] = step
;
2075 infp
->reg_growth
= growths
;
2076 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
2079 /* Can we fold in any space required for outbounds? */
2080 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
2086 /* Get the rest of the locals in place. */
2088 infp
->growth
[growths
++] = step
;
2089 infp
->local_growth
= growths
;
2094 /* Finish off if we need to do so. */
2096 infp
->growth
[growths
++] = outbounds
;
2101 /* Registers + args is nicely aligned, so we'll buy that in one shot.
2102 Then we buy the rest of the frame in 1 or 2 steps depending on
2103 whether we need a frame pointer. */
2104 if ((regarg
% STACK_BYTES
) == 0)
2106 infp
->growth
[growths
++] = regarg
;
2107 infp
->reg_growth
= growths
;
2108 infp
->arg_offset
= regarg
- 4;
2109 infp
->reg_offset
= 0;
2111 if (infp
->local_size
% STACK_BYTES
)
2112 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
2114 step
= infp
->local_size
+ infp
->pad_local
;
2116 if (!frame_pointer_needed
)
2122 infp
->growth
[growths
++] = step
;
2123 infp
->local_growth
= growths
;
2125 /* If there's any left to be done. */
2127 infp
->growth
[growths
++] = outbounds
;
2132 /* XXX: optimizations that we'll want to play with....
2133 -- regarg is not aligned, but it's a small number of registers;
2134 use some of localsize so that regarg is aligned and then
2135 save the registers. */
2137 /* Simple encoding; plods down the stack buying the pieces as it goes.
2138 -- does not optimize space consumption.
2139 -- does not attempt to optimize instruction counts.
2140 -- but it is safe for all alignments. */
2141 if (regarg
% STACK_BYTES
!= 0)
2142 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
2144 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
2145 infp
->reg_growth
= growths
;
2146 infp
->arg_offset
= infp
->growth
[0] - 4;
2147 infp
->reg_offset
= 0;
2149 if (frame_pointer_needed
)
2151 if (infp
->local_size
% STACK_BYTES
!= 0)
2152 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
2154 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
2155 infp
->local_growth
= growths
;
2157 infp
->growth
[growths
++] = outbounds
;
2161 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
2162 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
2164 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
2165 infp
->local_growth
= growths
;
2168 /* Anything else that we've forgotten?, plus a few consistency checks. */
2170 assert (infp
->reg_offset
>= 0);
2171 assert (growths
<= MAX_STACK_GROWS
);
2173 for (i
= 0; i
< growths
; i
++)
2175 if (infp
->growth
[i
] % STACK_BYTES
)
2177 fprintf (stderr
,"stack growth of %d is not %d aligned\n",
2178 infp
->growth
[i
], STACK_BYTES
);
2184 /* Define the offset between two registers, one to be eliminated, and
2185 the other its replacement, at the start of a routine. */
2188 mcore_initial_elimination_offset (int from
, int to
)
2192 struct mcore_frame fi
;
2194 layout_mcore_frame (& fi
);
2197 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
2199 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
2201 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
2204 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
2205 return above_frame
+ below_frame
;
2207 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
2215 /* Keep track of some information about varargs for the prolog. */
2218 mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*args_so_far
,
2219 enum machine_mode mode
, tree type
,
2220 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
2221 int second_time ATTRIBUTE_UNUSED
)
2223 current_function_anonymous_args
= 1;
2225 /* We need to know how many argument registers are used before
2226 the varargs start, so that we can push the remaining argument
2227 registers during the prologue. */
2228 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
2230 /* There is a bug somewhere in the arg handling code.
2231 Until I can find it this workaround always pushes the
2232 last named argument onto the stack. */
2233 number_of_regs_before_varargs
= *args_so_far
;
2235 /* The last named argument may be split between argument registers
2236 and the stack. Allow for this here. */
2237 if (number_of_regs_before_varargs
> NPARM_REGS
)
2238 number_of_regs_before_varargs
= NPARM_REGS
;
2242 mcore_expand_prolog (void)
2244 struct mcore_frame fi
;
2245 int space_allocated
= 0;
2248 /* Find out what we're doing. */
2249 layout_mcore_frame (&fi
);
2251 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
2252 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
2256 /* Emit a symbol for this routine's frame size. */
2259 x
= DECL_RTL (current_function_decl
);
2261 if (GET_CODE (x
) != MEM
)
2266 if (GET_CODE (x
) != SYMBOL_REF
)
2269 if (mcore_current_function_name
)
2270 free (mcore_current_function_name
);
2272 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
2274 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
2276 if (current_function_calls_alloca
)
2277 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
2280 We're looking at how the 8byte alignment affects stack layout
2281 and where we had to pad things. This emits information we can
2282 extract which tells us about frame sizes and the like. */
2283 fprintf (asm_out_file
,
2284 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2285 mcore_current_function_name
,
2286 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
2287 fi
.local_size
, fi
.outbound_size
,
2288 frame_pointer_needed
);
2291 if (mcore_naked_function_p ())
2294 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2295 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2297 /* If we have a parameter passed partially in regs and partially in memory,
2298 the registers will have been stored to memory already in function.c. So
2299 we only need to do something here for varargs functions. */
2300 if (fi
.arg_size
!= 0 && current_function_pretend_args_size
== 0)
2303 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2304 int remaining
= fi
.arg_size
;
2306 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2308 emit_insn (gen_movsi
2309 (gen_rtx_MEM (SImode
,
2310 plus_constant (stack_pointer_rtx
, offset
)),
2311 gen_rtx_REG (SImode
, rn
)));
2315 /* Do we need another stack adjustment before we do the register saves? */
2316 if (growth
< fi
.reg_growth
)
2317 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2319 if (fi
.reg_size
!= 0)
2322 int offs
= fi
.reg_offset
;
2324 for (i
= 15; i
>= 0; i
--)
2326 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2330 while (fi
.reg_mask
& (1 << first_reg
))
2334 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2335 gen_rtx_REG (SImode
, first_reg
),
2336 GEN_INT (16 - first_reg
)));
2338 i
-= (15 - first_reg
);
2339 offs
+= (16 - first_reg
) * 4;
2341 else if (fi
.reg_mask
& (1 << i
))
2343 emit_insn (gen_movsi
2344 (gen_rtx_MEM (SImode
,
2345 plus_constant (stack_pointer_rtx
, offs
)),
2346 gen_rtx_REG (SImode
, i
)));
2352 /* Figure the locals + outbounds. */
2353 if (frame_pointer_needed
)
2355 /* If we haven't already purchased to 'fp'. */
2356 if (growth
< fi
.local_growth
)
2357 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2359 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2361 /* ... and then go any remaining distance for outbounds, etc. */
2362 if (fi
.growth
[growth
])
2363 output_stack_adjust (-1, fi
.growth
[growth
++]);
2367 if (growth
< fi
.local_growth
)
2368 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2369 if (fi
.growth
[growth
])
2370 output_stack_adjust (-1, fi
.growth
[growth
++]);
2375 mcore_expand_epilog (void)
2377 struct mcore_frame fi
;
2380 int growth
= MAX_STACK_GROWS
- 1 ;
2383 /* Find out what we're doing. */
2384 layout_mcore_frame(&fi
);
2386 if (mcore_naked_function_p ())
2389 /* If we had a frame pointer, restore the sp from that. */
2390 if (frame_pointer_needed
)
2392 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2393 growth
= fi
.local_growth
- 1;
2397 /* XXX: while loop should accumulate and do a single sell. */
2398 while (growth
>= fi
.local_growth
)
2400 if (fi
.growth
[growth
] != 0)
2401 output_stack_adjust (1, fi
.growth
[growth
]);
2406 /* Make sure we've shrunk stack back to the point where the registers
2407 were laid down. This is typically 0/1 iterations. Then pull the
2408 register save information back off the stack. */
2409 while (growth
>= fi
.reg_growth
)
2410 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2412 offs
= fi
.reg_offset
;
2414 for (i
= 15; i
>= 0; i
--)
2416 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2420 /* Find the starting register. */
2423 while (fi
.reg_mask
& (1 << first_reg
))
2428 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2429 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2430 GEN_INT (16 - first_reg
)));
2432 i
-= (15 - first_reg
);
2433 offs
+= (16 - first_reg
) * 4;
2435 else if (fi
.reg_mask
& (1 << i
))
2437 emit_insn (gen_movsi
2438 (gen_rtx_REG (SImode
, i
),
2439 gen_rtx_MEM (SImode
,
2440 plus_constant (stack_pointer_rtx
, offs
))));
2445 /* Give back anything else. */
2446 /* XXX: Should accumulate total and then give it back. */
2448 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2451 /* This code is borrowed from the SH port. */
2453 /* The MCORE cannot load a large constant into a register, constants have to
2454 come from a pc relative load. The reference of a pc relative load
2455 instruction must be less than 1k infront of the instruction. This
2456 means that we often have to dump a constant inside a function, and
2457 generate code to branch around it.
2459 It is important to minimize this, since the branches will slow things
2460 down and make things bigger.
2462 Worst case code looks like:
2478 We fix this by performing a scan before scheduling, which notices which
2479 instructions need to have their operands fetched from the constant table
2480 and builds the table.
2484 scan, find an instruction which needs a pcrel move. Look forward, find the
2485 last barrier which is within MAX_COUNT bytes of the requirement.
2486 If there isn't one, make one. Process all the instructions between
2487 the find and the barrier.
2489 In the above example, we can tell that L3 is within 1k of L1, so
2490 the first move can be shrunk from the 2 insn+constant sequence into
2491 just 1 insn, and the constant moved to L3 to make:
2501 Then the second move becomes the target for the shortening process. */
2505 rtx value
; /* Value in table. */
2506 rtx label
; /* Label of value. */
2509 /* The maximum number of constants that can fit into one pool, since
2510 the pc relative range is 0...1020 bytes and constants are at least 4
2511 bytes long. We subtract 4 from the range to allow for the case where
2512 we need to add a branch/align before the constant pool. */
2514 #define MAX_COUNT 1016
2515 #define MAX_POOL_SIZE (MAX_COUNT/4)
2516 static pool_node pool_vector
[MAX_POOL_SIZE
];
2517 static int pool_size
;
2519 /* Dump out any constants accumulated in the final pass. These
2520 will only be labels. */
2523 mcore_output_jump_label_table (void)
2529 fprintf (asm_out_file
, "\t.align 2\n");
2531 for (i
= 0; i
< pool_size
; i
++)
2533 pool_node
* p
= pool_vector
+ i
;
2535 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2537 output_asm_insn (".long %0", &p
->value
);
2546 /* Check whether insn is a candidate for a conditional. */
2549 is_cond_candidate (rtx insn
)
2551 /* The only things we conditionalize are those that can be directly
2552 changed into a conditional. Only bother with SImode items. If
2553 we wanted to be a little more aggressive, we could also do other
2554 modes such as DImode with reg-reg move or load 0. */
2555 if (GET_CODE (insn
) == INSN
)
2557 rtx pat
= PATTERN (insn
);
2560 if (GET_CODE (pat
) != SET
)
2563 dst
= XEXP (pat
, 0);
2565 if ((GET_CODE (dst
) != REG
&&
2566 GET_CODE (dst
) != SUBREG
) ||
2567 GET_MODE (dst
) != SImode
)
2570 src
= XEXP (pat
, 1);
2572 if ((GET_CODE (src
) == REG
||
2573 (GET_CODE (src
) == SUBREG
&&
2574 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2575 GET_MODE (src
) == SImode
)
2576 return COND_MOV_INSN
;
2577 else if (GET_CODE (src
) == CONST_INT
&&
2579 return COND_CLR_INSN
;
2580 else if (GET_CODE (src
) == PLUS
&&
2581 (GET_CODE (XEXP (src
, 0)) == REG
||
2582 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2583 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2584 GET_MODE (XEXP (src
, 0)) == SImode
&&
2585 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2586 INTVAL (XEXP (src
, 1)) == 1)
2587 return COND_INC_INSN
;
2588 else if (((GET_CODE (src
) == MINUS
&&
2589 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2590 INTVAL( XEXP (src
, 1)) == 1) ||
2591 (GET_CODE (src
) == PLUS
&&
2592 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2593 INTVAL (XEXP (src
, 1)) == -1)) &&
2594 (GET_CODE (XEXP (src
, 0)) == REG
||
2595 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2596 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2597 GET_MODE (XEXP (src
, 0)) == SImode
)
2598 return COND_DEC_INSN
;
2600 /* Some insns that we don't bother with:
2601 (set (rx:DI) (ry:DI))
2602 (set (rx:DI) (const_int 0))
2606 else if (GET_CODE (insn
) == JUMP_INSN
&&
2607 GET_CODE (PATTERN (insn
)) == SET
&&
2608 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2609 return COND_BRANCH_INSN
;
2614 /* Emit a conditional version of insn and replace the old insn with the
2615 new one. Return the new insn if emitted. */
2618 emit_new_cond_insn (rtx insn
, int cond
)
2624 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2627 pat
= PATTERN (insn
);
2629 if (GET_CODE (insn
) == INSN
)
2631 dst
= SET_DEST (pat
);
2632 src
= SET_SRC (pat
);
2636 dst
= JUMP_LABEL (insn
);
2645 c_insn
= gen_movt0 (dst
, src
, dst
);
2647 c_insn
= gen_movt0 (dst
, dst
, src
);
2652 c_insn
= gen_incscc (dst
, dst
);
2654 c_insn
= gen_incscc_false (dst
, dst
);
2659 c_insn
= gen_decscc (dst
, dst
);
2661 c_insn
= gen_decscc_false (dst
, dst
);
2664 case COND_BRANCH_INSN
:
2666 c_insn
= gen_branch_true (dst
);
2668 c_insn
= gen_branch_false (dst
);
2675 /* Only copy the notes if they exist. */
2676 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2678 /* We really don't need to bother with the notes and links at this
2679 point, but go ahead and save the notes. This will help is_dead()
2680 when applying peepholes (links don't matter since they are not
2681 used any more beyond this point for the mcore). */
2682 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2685 if (num
== COND_BRANCH_INSN
)
2687 /* For jumps, we need to be a little bit careful and emit the new jump
2688 before the old one and to update the use count for the target label.
2689 This way, the barrier following the old (uncond) jump will get
2690 deleted, but the label won't. */
2691 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2693 ++ LABEL_NUSES (dst
);
2695 JUMP_LABEL (c_insn
) = dst
;
2698 c_insn
= emit_insn_after (c_insn
, insn
);
2705 /* Attempt to change a basic block into a series of conditional insns. This
2706 works by taking the branch at the end of the 1st block and scanning for the
2707 end of the 2nd block. If all instructions in the 2nd block have cond.
2708 versions and the label at the start of block 3 is the same as the target
2709 from the branch at block 1, then conditionalize all insn in block 2 using
2710 the inverse condition of the branch at block 1. (Note I'm bending the
2711 definition of basic block here.)
2715 bt L2 <-- end of block 1 (delete)
2718 br L3 <-- end of block 2
2720 L2: ... <-- start of block 3 (NUSES==1)
2731 we can delete the L2 label if NUSES==1 and re-apply the optimization
2732 starting at the last instruction of block 2. This may allow an entire
2733 if-then-else statement to be conditionalized. BRC */
2735 conditionalize_block (rtx first
)
2739 rtx end_blk_1_br
= 0;
2740 rtx end_blk_2_insn
= 0;
2741 rtx start_blk_3_lab
= 0;
2747 /* Check that the first insn is a candidate conditional jump. This is
2748 the one that we'll eliminate. If not, advance to the next insn to
2750 if (GET_CODE (first
) != JUMP_INSN
||
2751 GET_CODE (PATTERN (first
)) != SET
||
2752 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2753 return NEXT_INSN (first
);
2755 /* Extract some information we need. */
2756 end_blk_1_br
= first
;
2757 br_pat
= PATTERN (end_blk_1_br
);
2759 /* Complement the condition since we use the reverse cond. for the insns. */
2760 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2762 /* Determine what kind of branch we have. */
2763 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2765 /* A normal branch, so extract label out of first arm. */
2766 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2770 /* An inverse branch, so extract the label out of the 2nd arm
2771 and complement the condition. */
2773 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2776 /* Scan forward for the start of block 2: it must start with a
2777 label and that label must be the same as the branch target
2778 label from block 1. We don't care about whether block 2 actually
2779 ends with a branch or a label (an uncond. branch is
2780 conditionalizable). */
2781 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2785 code
= GET_CODE (insn
);
2787 /* Look for the label at the start of block 3. */
2788 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2791 /* Skip barriers, notes, and conditionalizable insns. If the
2792 insn is not conditionalizable or makes this optimization fail,
2793 just return the next insn so we can start over from that point. */
2794 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2795 return NEXT_INSN (insn
);
2797 /* Remember the last real insn before the label (ie end of block 2). */
2798 if (code
== JUMP_INSN
|| code
== INSN
)
2801 end_blk_2_insn
= insn
;
2808 /* It is possible for this optimization to slow performance if the blocks
2809 are long. This really depends upon whether the branch is likely taken
2810 or not. If the branch is taken, we slow performance in many cases. But,
2811 if the branch is not taken, we always help performance (for a single
2812 block, but for a double block (i.e. when the optimization is re-applied)
2813 this is not true since the 'right thing' depends on the overall length of
2814 the collapsed block). As a compromise, don't apply this optimization on
2815 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2816 the best threshold depends on the latencies of the instructions (i.e.,
2817 the branch penalty). */
2818 if (optimize
> 1 && blk_size
> 2)
2821 /* At this point, we've found the start of block 3 and we know that
2822 it is the destination of the branch from block 1. Also, all
2823 instructions in the block 2 are conditionalizable. So, apply the
2824 conditionalization and delete the branch. */
2825 start_blk_3_lab
= insn
;
2827 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2828 insn
= NEXT_INSN (insn
))
2832 if (INSN_DELETED_P (insn
))
2835 /* Try to form a conditional variant of the instruction and emit it. */
2836 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2838 if (end_blk_2_insn
== insn
)
2839 end_blk_2_insn
= newinsn
;
2845 /* Note whether we will delete the label starting blk 3 when the jump
2846 gets deleted. If so, we want to re-apply this optimization at the
2847 last real instruction right before the label. */
2848 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2850 start_blk_3_lab
= 0;
2853 /* ??? we probably should redistribute the death notes for this insn, esp.
2854 the death of cc, but it doesn't really matter this late in the game.
2855 The peepholes all use is_dead() which will find the correct death
2856 regardless of whether there is a note. */
2857 delete_insn (end_blk_1_br
);
2859 if (! start_blk_3_lab
)
2860 return end_blk_2_insn
;
2862 /* Return the insn right after the label at the start of block 3. */
2863 return NEXT_INSN (start_blk_3_lab
);
2866 /* Apply the conditionalization of blocks optimization. This is the
2867 outer loop that traverses through the insns scanning for a branch
2868 that signifies an opportunity to apply the optimization. Note that
2869 this optimization is applied late. If we could apply it earlier,
2870 say before cse 2, it may expose more optimization opportunities.
2871 but, the pay back probably isn't really worth the effort (we'd have
2872 to update all reg/flow/notes/links/etc to make it work - and stick it
2873 in before cse 2). */
2876 conditionalize_optimization (void)
2880 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2884 static int saved_warn_return_type
= -1;
2885 static int saved_warn_return_type_count
= 0;
2887 /* This is to handle loads from the constant pool. */
2892 /* Reset this variable. */
2893 current_function_anonymous_args
= 0;
2895 /* Restore the warn_return_type if it has been altered. */
2896 if (saved_warn_return_type
!= -1)
2898 /* Only restore the value if we have reached another function.
2899 The test of warn_return_type occurs in final_function () in
2900 c-decl.c a long time after the code for the function is generated,
2901 so we need a counter to tell us when we have finished parsing that
2902 function and can restore the flag. */
2903 if (--saved_warn_return_type_count
== 0)
2905 warn_return_type
= saved_warn_return_type
;
2906 saved_warn_return_type
= -1;
2913 /* Conditionalize blocks where we can. */
2914 conditionalize_optimization ();
2916 /* Literal pool generation is now pushed off until the assembler. */
2920 /* Return true if X is something that can be moved directly into r15. */
2923 mcore_r15_operand_p (rtx x
)
2925 switch (GET_CODE (x
))
2928 return mcore_const_ok_for_inline (INTVAL (x
));
2940 /* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't
2941 directly move X into it, use r1-r14 as a temporary. */
2944 mcore_secondary_reload_class (enum reg_class
class,
2945 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2947 if (TEST_HARD_REG_BIT (reg_class_contents
[class], 15)
2948 && !mcore_r15_operand_p (x
))
2953 /* Return the reg_class to use when reloading the rtx X into the class
2954 CLASS. If X is too complex to move directly into r15, prefer to
2955 use LRW_REGS instead. */
2958 mcore_reload_class (rtx x
, enum reg_class
class)
2960 if (reg_class_subset_p (LRW_REGS
, class) && !mcore_r15_operand_p (x
))
2966 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2967 register. Note that the current version doesn't worry about whether
2968 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2969 in r2 matches an SImode in r2. Might think in the future about whether
2970 we want to be able to say something about modes. */
2973 mcore_is_same_reg (rtx x
, rtx y
)
2975 /* Strip any and all of the subreg wrappers. */
2976 while (GET_CODE (x
) == SUBREG
)
2979 while (GET_CODE (y
) == SUBREG
)
2982 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2989 mcore_override_options (void)
2991 if (mcore_stack_increment_string
)
2993 mcore_stack_increment
= atoi (mcore_stack_increment_string
);
2995 if (mcore_stack_increment
< 0
2996 || (mcore_stack_increment
== 0
2997 && (mcore_stack_increment_string
[0] != '0'
2998 || mcore_stack_increment_string
[1] != 0)))
2999 error ("invalid option `-mstack-increment=%s'",
3000 mcore_stack_increment_string
);
3003 /* Only the m340 supports little endian code. */
3004 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
3005 target_flags
|= M340_BIT
;
3008 /* Compute the number of word sized registers needed to
3009 hold a function argument of mode MODE and type TYPE. */
3012 mcore_num_arg_regs (enum machine_mode mode
, tree type
)
3016 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
3019 if (type
&& mode
== BLKmode
)
3020 size
= int_size_in_bytes (type
);
3022 size
= GET_MODE_SIZE (mode
);
3024 return ROUND_ADVANCE (size
);
3028 handle_structs_in_regs (enum machine_mode mode
, tree type
, int reg
)
3032 /* The MCore ABI defines that a structure whoes size is not a whole multiple
3033 of bytes is passed packed into registers (or spilled onto the stack if
3034 not enough registers are available) with the last few bytes of the
3035 structure being packed, left-justified, into the last register/stack slot.
3036 GCC handles this correctly if the last word is in a stack slot, but we
3037 have to generate a special, PARALLEL RTX if the last word is in an
3038 argument register. */
3040 && TYPE_MODE (type
) == BLKmode
3041 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
3042 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
3043 && (size
% UNITS_PER_WORD
!= 0)
3044 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
3046 rtx arg_regs
[NPARM_REGS
];
3051 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
3054 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
3055 GEN_INT (nregs
* UNITS_PER_WORD
));
3059 /* We assume here that NPARM_REGS == 6. The assert checks this. */
3060 assert (ARRAY_SIZE (arg_regs
) == 6);
3061 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
3062 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
3064 result
= gen_rtx_PARALLEL (mode
, rtvec
);
3068 return gen_rtx_REG (mode
, reg
);
3072 mcore_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3074 enum machine_mode mode
;
3077 mode
= TYPE_MODE (valtype
);
3079 PROMOTE_MODE (mode
, unsigned_p
, NULL
);
3081 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
3084 /* Define where to put the arguments to a function.
3085 Value is zero to push the argument on the stack,
3086 or a hard register in which to store the argument.
3088 MODE is the argument's machine mode.
3089 TYPE is the data type of the argument (as a tree).
3090 This is null for libcalls where that information may
3092 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3093 the preceding args and about the function being called.
3094 NAMED is nonzero if this argument is a named parameter
3095 (otherwise it is an extra parameter matching an ellipsis).
3097 On MCore the first args are normally in registers
3098 and the rest are pushed. Any arg that starts within the first
3099 NPARM_REGS words is at least partially passed in a register unless
3100 its data type forbids. */
3103 mcore_function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
,
3104 tree type
, int named
)
3111 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
3114 arg_reg
= ROUND_REG (cum
, mode
);
3116 if (arg_reg
< NPARM_REGS
)
3117 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
3122 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
3123 Returns the number of argument registers required to hold *part* of
3124 a parameter of machine mode MODE and type TYPE (which may be NULL if
3125 the type is not known). If the argument fits entirely in the argument
3126 registers, or entirely on the stack, then 0 is returned. CUM is the
3127 number of argument registers already used by earlier parameters to
3131 mcore_function_arg_partial_nregs (CUMULATIVE_ARGS cum
, enum machine_mode mode
,
3132 tree type
, int named
)
3134 int reg
= ROUND_REG (cum
, mode
);
3139 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
3142 /* REG is not the *hardware* register number of the register that holds
3143 the argument, it is the *argument* register number. So for example,
3144 the first argument to a function goes in argument register 0, which
3145 translates (for the MCore) into hardware register 2. The second
3146 argument goes into argument register 1, which translates into hardware
3147 register 3, and so on. NPARM_REGS is the number of argument registers
3148 supported by the target, not the maximum hardware register number of
3150 if (reg
>= NPARM_REGS
)
3153 /* If the argument fits entirely in registers, return 0. */
3154 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
3157 /* The argument overflows the number of available argument registers.
3158 Compute how many argument registers have not yet been assigned to
3159 hold an argument. */
3160 reg
= NPARM_REGS
- reg
;
3162 /* Return partially in registers and partially on the stack. */
3166 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
3169 mcore_dllexport_name_p (const char * symbol
)
3171 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
3174 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
3177 mcore_dllimport_name_p (const char * symbol
)
3179 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
3182 /* Mark a DECL as being dllexport'd. */
3185 mcore_mark_dllexport (tree decl
)
3187 const char * oldname
;
3192 rtlname
= XEXP (DECL_RTL (decl
), 0);
3194 if (GET_CODE (rtlname
) == SYMBOL_REF
)
3195 oldname
= XSTR (rtlname
, 0);
3196 else if ( GET_CODE (rtlname
) == MEM
3197 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
3198 oldname
= XSTR (XEXP (rtlname
, 0), 0);
3202 if (mcore_dllexport_name_p (oldname
))
3203 return; /* Already done. */
3205 newname
= alloca (strlen (oldname
) + 4);
3206 sprintf (newname
, "@e.%s", oldname
);
3208 /* We pass newname through get_identifier to ensure it has a unique
3209 address. RTL processing can sometimes peek inside the symbol ref
3210 and compare the string's addresses to see if two symbols are
3212 /* ??? At least I think that's why we do this. */
3213 idp
= get_identifier (newname
);
3215 XEXP (DECL_RTL (decl
), 0) =
3216 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3219 /* Mark a DECL as being dllimport'd. */
3222 mcore_mark_dllimport (tree decl
)
3224 const char * oldname
;
3230 rtlname
= XEXP (DECL_RTL (decl
), 0);
3232 if (GET_CODE (rtlname
) == SYMBOL_REF
)
3233 oldname
= XSTR (rtlname
, 0);
3234 else if ( GET_CODE (rtlname
) == MEM
3235 && GET_CODE (XEXP (rtlname
, 0)) == SYMBOL_REF
)
3236 oldname
= XSTR (XEXP (rtlname
, 0), 0);
3240 if (mcore_dllexport_name_p (oldname
))
3241 abort (); /* This shouldn't happen. */
3242 else if (mcore_dllimport_name_p (oldname
))
3243 return; /* Already done. */
3245 /* ??? One can well ask why we're making these checks here,
3246 and that would be a good question. */
3248 /* Imported variables can't be initialized. */
3249 if (TREE_CODE (decl
) == VAR_DECL
3250 && !DECL_VIRTUAL_P (decl
)
3251 && DECL_INITIAL (decl
))
3253 error ("%Jinitialized variable '%D' is marked dllimport", decl
, decl
);
3257 /* `extern' needn't be specified with dllimport.
3258 Specify `extern' now and hope for the best. Sigh. */
3259 if (TREE_CODE (decl
) == VAR_DECL
3260 /* ??? Is this test for vtables needed? */
3261 && !DECL_VIRTUAL_P (decl
))
3263 DECL_EXTERNAL (decl
) = 1;
3264 TREE_PUBLIC (decl
) = 1;
3267 newname
= alloca (strlen (oldname
) + 11);
3268 sprintf (newname
, "@i.__imp_%s", oldname
);
3270 /* We pass newname through get_identifier to ensure it has a unique
3271 address. RTL processing can sometimes peek inside the symbol ref
3272 and compare the string's addresses to see if two symbols are
3274 /* ??? At least I think that's why we do this. */
3275 idp
= get_identifier (newname
);
3277 newrtl
= gen_rtx_MEM (Pmode
,
3278 gen_rtx_SYMBOL_REF (Pmode
,
3279 IDENTIFIER_POINTER (idp
)));
3280 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3284 mcore_dllexport_p (tree decl
)
3286 if ( TREE_CODE (decl
) != VAR_DECL
3287 && TREE_CODE (decl
) != FUNCTION_DECL
)
3290 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
3294 mcore_dllimport_p (tree decl
)
3296 if ( TREE_CODE (decl
) != VAR_DECL
3297 && TREE_CODE (decl
) != FUNCTION_DECL
)
3300 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
3303 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3304 install some info in the .drective (PE) or .exports (ELF) sections. */
3307 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
3309 /* Mark the decl so we can tell from the rtl whether the object is
3310 dllexport'd or dllimport'd. */
3311 if (mcore_dllexport_p (decl
))
3312 mcore_mark_dllexport (decl
);
3313 else if (mcore_dllimport_p (decl
))
3314 mcore_mark_dllimport (decl
);
3316 /* It might be that DECL has already been marked as dllimport, but
3317 a subsequent definition nullified that. The attribute is gone
3318 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3319 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3320 || TREE_CODE (decl
) == VAR_DECL
)
3321 && DECL_RTL (decl
) != NULL_RTX
3322 && GET_CODE (DECL_RTL (decl
)) == MEM
3323 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3324 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3325 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3327 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3328 tree idp
= get_identifier (oldname
+ 9);
3329 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3331 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3333 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3334 ??? We leave these alone for now. */
3338 /* Undo the effects of the above. */
3341 mcore_strip_name_encoding (const char * str
)
3343 return str
+ (str
[0] == '@' ? 3 : 0);
3346 /* MCore specific attribute support.
3347 dllexport - for exporting a function/variable that will live in a dll
3348 dllimport - for importing a function/variable from a dll
3349 naked - do not create a function prologue/epilogue. */
3351 const struct attribute_spec mcore_attribute_table
[] =
3353 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3354 { "dllexport", 0, 0, true, false, false, NULL
},
3355 { "dllimport", 0, 0, true, false, false, NULL
},
3356 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
},
3357 { NULL
, 0, 0, false, false, false, NULL
}
3360 /* Handle a "naked" attribute; arguments as in
3361 struct attribute_spec.handler. */
3364 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3365 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3367 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3369 /* PR14310 - don't complain about lack of return statement
3370 in naked functions. The solution here is a gross hack
3371 but this is the only way to solve the problem without
3372 adding a new feature to GCC. I did try submitting a patch
3373 that would add such a new feature, but it was (rightfully)
3374 rejected on the grounds that it was creeping featurism,
3375 so hence this code. */
3376 if (warn_return_type
)
3378 saved_warn_return_type
= warn_return_type
;
3379 warn_return_type
= 0;
3380 saved_warn_return_type_count
= 2;
3382 else if (saved_warn_return_type_count
)
3383 saved_warn_return_type_count
= 2;
3387 warning ("`%s' attribute only applies to functions",
3388 IDENTIFIER_POINTER (name
));
3389 *no_add_attrs
= true;
3395 /* ??? It looks like this is PE specific? Oh well, this is what the
3396 old code did as well. */
3399 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3404 const char * prefix
;
3406 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3408 /* Strip off any encoding in name. */
3409 name
= (* targetm
.strip_name_encoding
) (name
);
3411 /* The object is put in, for example, section .text$foo.
3412 The linker will then ultimately place them in .text
3413 (everything from the $ on is stripped). */
3414 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3416 /* For compatibility with EPOC, we ignore the fact that the
3417 section might have relocs against it. */
3418 else if (decl_readonly_section (decl
, 0))
3423 len
= strlen (name
) + strlen (prefix
);
3424 string
= alloca (len
+ 1);
3426 sprintf (string
, "%s%s", prefix
, name
);
3428 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3432 mcore_naked_function_p (void)
3434 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3437 #ifdef OBJECT_FORMAT_ELF
3439 mcore_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
)
3441 fprintf (asm_out_file
, "\t.section %s\n", name
);
3443 #endif /* OBJECT_FORMAT_ELF */
3445 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3448 mcore_external_libcall (rtx fun
)
3450 fprintf (asm_out_file
, "\t.import\t");
3451 assemble_name (asm_out_file
, XSTR (fun
, 0));
3452 fprintf (asm_out_file
, "\n");
3455 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3458 mcore_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
3460 HOST_WIDE_INT size
= int_size_in_bytes (type
);
3461 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);