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* target.h (struct gcc_target): Add calls.pass_by_reference.
[official-gcc.git] / gcc / config / m32r / m32r.c
blobc46bff52ae490dcf20e0da2dd2a0f26dd2f15083
1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "ggc.h"
41 #include "tm_p.h"
42 #include "target.h"
43 #include "target-def.h"
44
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
47 rtx m32r_compare_op0, m32r_compare_op1;
48
49 /* Array of valid operand punctuation characters. */
50 char m32r_punct_chars[256];
51
52 /* Selected code model. */
53 const char * m32r_model_string = M32R_MODEL_DEFAULT;
54 enum m32r_model m32r_model;
55
56 /* Selected SDA support. */
57 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
58 enum m32r_sdata m32r_sdata;
59
60 /* Machine-specific symbol_ref flags. */
61 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
62 #define SYMBOL_REF_MODEL(X) \
63 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
64
65 /* For string literals, etc. */
66 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
67
68 /* Cache-flush support. Cache-flush is used at trampoline.
69 Default cache-flush is "trap 12".
70 default cache-flush function is "_flush_cache" (CACHE_FLUSH_FUNC)
71 default cache-flush trap-interrupt number is "12". (CACHE_FLUSH_TRAP)
72 You can change how to generate code of cache-flush with following options.
73 -flush-func=FLUSH-FUNC-NAME
74 -no-flush-func
75 -fluch-trap=TRAP-NUMBER
76 -no-flush-trap. */
77 const char *m32r_cache_flush_func = CACHE_FLUSH_FUNC;
78 const char *m32r_cache_flush_trap_string = CACHE_FLUSH_TRAP;
79 int m32r_cache_flush_trap = 12;
80
81 /* Forward declaration. */
82 static void init_reg_tables (void);
83 static void block_move_call (rtx, rtx, rtx);
84 static int m32r_is_insn (rtx);
85 const struct attribute_spec m32r_attribute_table[];
86 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
87 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
88 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
89
90 static void m32r_file_start (void);
91
92 static int m32r_adjust_priority (rtx, int);
93 static int m32r_issue_rate (void);
94
95 static void m32r_encode_section_info (tree, rtx, int);
96 static bool m32r_in_small_data_p (tree);
97 static bool m32r_return_in_memory (tree, tree);
98 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
99 tree, int *, int);
100 static void init_idents (void);
101 static bool m32r_rtx_costs (rtx, int, int, int *);
102 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
103 tree, bool);
104 \f
105 /* Initialize the GCC target structure. */
106 #undef TARGET_ATTRIBUTE_TABLE
107 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
108
109 #undef TARGET_ASM_ALIGNED_HI_OP
110 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
111 #undef TARGET_ASM_ALIGNED_SI_OP
112 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
113
114 #undef TARGET_ASM_FUNCTION_PROLOGUE
115 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
116 #undef TARGET_ASM_FUNCTION_EPILOGUE
117 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
118
119 #undef TARGET_ASM_FILE_START
120 #define TARGET_ASM_FILE_START m32r_file_start
121
122 #undef TARGET_SCHED_ADJUST_PRIORITY
123 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
124 #undef TARGET_SCHED_ISSUE_RATE
125 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
126 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
127 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
128
129 #undef TARGET_ENCODE_SECTION_INFO
130 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
131 #undef TARGET_IN_SMALL_DATA_P
132 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
133
134 #undef TARGET_RTX_COSTS
135 #define TARGET_RTX_COSTS m32r_rtx_costs
136 #undef TARGET_ADDRESS_COST
137 #define TARGET_ADDRESS_COST hook_int_rtx_0
138
139 #undef TARGET_PROMOTE_PROTOTYPES
140 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
141 #undef TARGET_RETURN_IN_MEMORY
142 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
143 #undef TARGET_SETUP_INCOMING_VARARGS
144 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
145 #undef TARGET_MUST_PASS_IN_STACK
146 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
147 #undef TARGET_PASS_BY_REFERENCE
148 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
149
150 struct gcc_target targetm = TARGET_INITIALIZER;
151 \f
152 /* Called by OVERRIDE_OPTIONS to initialize various things. */
153
154 void
155 m32r_init (void)
156 {
157 init_reg_tables ();
158
159 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
160 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
161 m32r_punct_chars['#'] = 1;
162 m32r_punct_chars['@'] = 1; /* ??? no longer used */
163
164 /* Provide default value if not specified. */
165 if (!g_switch_set)
166 g_switch_value = SDATA_DEFAULT_SIZE;
167
168 if (strcmp (m32r_model_string, "small") == 0)
169 m32r_model = M32R_MODEL_SMALL;
170 else if (strcmp (m32r_model_string, "medium") == 0)
171 m32r_model = M32R_MODEL_MEDIUM;
172 else if (strcmp (m32r_model_string, "large") == 0)
173 m32r_model = M32R_MODEL_LARGE;
174 else
175 error ("bad value (%s) for -mmodel switch", m32r_model_string);
176
177 if (strcmp (m32r_sdata_string, "none") == 0)
178 m32r_sdata = M32R_SDATA_NONE;
179 else if (strcmp (m32r_sdata_string, "sdata") == 0)
180 m32r_sdata = M32R_SDATA_SDATA;
181 else if (strcmp (m32r_sdata_string, "use") == 0)
182 m32r_sdata = M32R_SDATA_USE;
183 else
184 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
185
186 if (m32r_cache_flush_trap_string)
187 {
188 /* Change trap-number (12) for cache-flush to the others (0 - 15). */
189 m32r_cache_flush_trap = atoi (m32r_cache_flush_trap_string);
190 if (m32r_cache_flush_trap < 0 || m32r_cache_flush_trap > 15)
191 error ("bad value (%s) for -flush-trap=n (0=<n<=15)",
192 m32r_cache_flush_trap_string);
193 }
194 }
195
196 /* Vectors to keep interesting information about registers where it can easily
197 be got. We use to use the actual mode value as the bit number, but there
198 is (or may be) more than 32 modes now. Instead we use two tables: one
199 indexed by hard register number, and one indexed by mode. */
200
201 /* The purpose of m32r_mode_class is to shrink the range of modes so that
202 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
203 mapped into one m32r_mode_class mode. */
204
205 enum m32r_mode_class
206 {
207 C_MODE,
208 S_MODE, D_MODE, T_MODE, O_MODE,
209 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
210 };
211
212 /* Modes for condition codes. */
213 #define C_MODES (1 << (int) C_MODE)
214
215 /* Modes for single-word and smaller quantities. */
216 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
217
218 /* Modes for double-word and smaller quantities. */
219 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
220
221 /* Modes for quad-word and smaller quantities. */
222 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
223
224 /* Modes for accumulators. */
225 #define A_MODES (1 << (int) A_MODE)
226
227 /* Value is 1 if register/mode pair is acceptable on arc. */
228
229 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
230 {
231 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
232 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
233 S_MODES, C_MODES, A_MODES, A_MODES
234 };
235
236 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
237
238 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
239
240 static void
241 init_reg_tables (void)
242 {
243 int i;
244
245 for (i = 0; i < NUM_MACHINE_MODES; i++)
246 {
247 switch (GET_MODE_CLASS (i))
248 {
249 case MODE_INT:
250 case MODE_PARTIAL_INT:
251 case MODE_COMPLEX_INT:
252 if (GET_MODE_SIZE (i) <= 4)
253 m32r_mode_class[i] = 1 << (int) S_MODE;
254 else if (GET_MODE_SIZE (i) == 8)
255 m32r_mode_class[i] = 1 << (int) D_MODE;
256 else if (GET_MODE_SIZE (i) == 16)
257 m32r_mode_class[i] = 1 << (int) T_MODE;
258 else if (GET_MODE_SIZE (i) == 32)
259 m32r_mode_class[i] = 1 << (int) O_MODE;
260 else
261 m32r_mode_class[i] = 0;
262 break;
263 case MODE_FLOAT:
264 case MODE_COMPLEX_FLOAT:
265 if (GET_MODE_SIZE (i) <= 4)
266 m32r_mode_class[i] = 1 << (int) SF_MODE;
267 else if (GET_MODE_SIZE (i) == 8)
268 m32r_mode_class[i] = 1 << (int) DF_MODE;
269 else if (GET_MODE_SIZE (i) == 16)
270 m32r_mode_class[i] = 1 << (int) TF_MODE;
271 else if (GET_MODE_SIZE (i) == 32)
272 m32r_mode_class[i] = 1 << (int) OF_MODE;
273 else
274 m32r_mode_class[i] = 0;
275 break;
276 case MODE_CC:
277 m32r_mode_class[i] = 1 << (int) C_MODE;
278 break;
279 default:
280 m32r_mode_class[i] = 0;
281 break;
282 }
283 }
284
285 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
286 {
287 if (GPR_P (i))
288 m32r_regno_reg_class[i] = GENERAL_REGS;
289 else if (i == ARG_POINTER_REGNUM)
290 m32r_regno_reg_class[i] = GENERAL_REGS;
291 else
292 m32r_regno_reg_class[i] = NO_REGS;
293 }
294 }
295 \f
296 /* M32R specific attribute support.
297
298 interrupt - for interrupt functions
299
300 model - select code model used to access object
301
302 small: addresses use 24 bits, use bl to make calls
303 medium: addresses use 32 bits, use bl to make calls
304 large: addresses use 32 bits, use seth/add3/jl to make calls
305
306 Grep for MODEL in m32r.h for more info. */
307
308 static tree small_ident1;
309 static tree small_ident2;
310 static tree medium_ident1;
311 static tree medium_ident2;
312 static tree large_ident1;
313 static tree large_ident2;
314
315 static void
316 init_idents (void)
317 {
318 if (small_ident1 == 0)
319 {
320 small_ident1 = get_identifier ("small");
321 small_ident2 = get_identifier ("__small__");
322 medium_ident1 = get_identifier ("medium");
323 medium_ident2 = get_identifier ("__medium__");
324 large_ident1 = get_identifier ("large");
325 large_ident2 = get_identifier ("__large__");
326 }
327 }
328
329 const struct attribute_spec m32r_attribute_table[] =
330 {
331 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
332 { "interrupt", 0, 0, true, false, false, NULL },
333 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
334 { NULL, 0, 0, false, false, false, NULL }
335 };
336
337
338 /* Handle an "model" attribute; arguments as in
339 struct attribute_spec.handler. */
340 static tree
341 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
342 tree args, int flags ATTRIBUTE_UNUSED,
343 bool *no_add_attrs)
344 {
345 tree arg;
346
347 init_idents ();
348 arg = TREE_VALUE (args);
349
350 if (arg != small_ident1
351 && arg != small_ident2
352 && arg != medium_ident1
353 && arg != medium_ident2
354 && arg != large_ident1
355 && arg != large_ident2)
356 {
357 warning ("invalid argument of `%s' attribute",
358 IDENTIFIER_POINTER (name));
359 *no_add_attrs = true;
360 }
361
362 return NULL_TREE;
363 }
364 \f
365 /* Encode section information of DECL, which is either a VAR_DECL,
366 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
367
368 For the M32R we want to record:
369
370 - whether the object lives in .sdata/.sbss.
371 - what code model should be used to access the object
372 */
373
374 static void
375 m32r_encode_section_info (tree decl, rtx rtl, int first)
376 {
377 int extra_flags = 0;
378 tree model_attr;
379 enum m32r_model model;
380
381 default_encode_section_info (decl, rtl, first);
382
383 if (!DECL_P (decl))
384 return;
385
386 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
387 if (model_attr)
388 {
389 tree id;
390
391 init_idents ();
392
393 id = TREE_VALUE (TREE_VALUE (model_attr));
394
395 if (id == small_ident1 || id == small_ident2)
396 model = M32R_MODEL_SMALL;
397 else if (id == medium_ident1 || id == medium_ident2)
398 model = M32R_MODEL_MEDIUM;
399 else if (id == large_ident1 || id == large_ident2)
400 model = M32R_MODEL_LARGE;
401 else
402 abort (); /* shouldn't happen */
403 }
404 else
405 {
406 if (TARGET_MODEL_SMALL)
407 model = M32R_MODEL_SMALL;
408 else if (TARGET_MODEL_MEDIUM)
409 model = M32R_MODEL_MEDIUM;
410 else if (TARGET_MODEL_LARGE)
411 model = M32R_MODEL_LARGE;
412 else
413 abort (); /* shouldn't happen */
414 }
415 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
416
417 if (extra_flags)
418 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
419 }
420
421 /* Only mark the object as being small data area addressable if
422 it hasn't been explicitly marked with a code model.
423
424 The user can explicitly put an object in the small data area with the
425 section attribute. If the object is in sdata/sbss and marked with a
426 code model do both [put the object in .sdata and mark it as being
427 addressed with a specific code model - don't mark it as being addressed
428 with an SDA reloc though]. This is ok and might be useful at times. If
429 the object doesn't fit the linker will give an error. */
430
431 static bool
432 m32r_in_small_data_p (tree decl)
433 {
434 tree section;
435
436 if (TREE_CODE (decl) != VAR_DECL)
437 return false;
438
439 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
440 return false;
441
442 section = DECL_SECTION_NAME (decl);
443 if (section)
444 {
445 char *name = (char *) TREE_STRING_POINTER (section);
446 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
447 return true;
448 }
449 else
450 {
451 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
452 {
453 int size = int_size_in_bytes (TREE_TYPE (decl));
454
455 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
456 return true;
457 }
458 }
459
460 return false;
461 }
462
463 /* Do anything needed before RTL is emitted for each function. */
464
465 void
466 m32r_init_expanders (void)
467 {
468 /* ??? At one point there was code here. The function is left in
469 to make it easy to experiment. */
470 }
471 \f
472 /* Acceptable arguments to the call insn. */
473
474 int
475 call_address_operand (rtx op, enum machine_mode mode)
476 {
477 return symbolic_operand (op, mode);
478
479 /* Constants and values in registers are not OK, because
480 the m32r BL instruction can only support PC relative branching. */
481 }
482
483 int
484 call_operand (rtx op, enum machine_mode mode)
485 {
486 if (GET_CODE (op) != MEM)
487 return 0;
488 op = XEXP (op, 0);
489 return call_address_operand (op, mode);
490 }
491
492 /* Returns 1 if OP is a symbol reference. */
493
494 int
495 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
496 {
497 switch (GET_CODE (op))
498 {
499 case SYMBOL_REF:
500 case LABEL_REF:
501 case CONST :
502 return 1;
503
504 default:
505 return 0;
506 }
507 }
508
509 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
510
511 int
512 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
513 {
514 if (! TARGET_SDATA_USE)
515 return 0;
516
517 if (GET_CODE (op) == SYMBOL_REF)
518 return SYMBOL_REF_SMALL_P (op);
519
520 if (GET_CODE (op) == CONST
521 && GET_CODE (XEXP (op, 0)) == PLUS
522 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
523 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
524 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
525 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
526
527 return 0;
528 }
529
530 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
531
532 int
533 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
534 {
535 rtx sym;
536
537 if (flag_pic)
538 return 0;
539
540 if (GET_CODE (op) == LABEL_REF)
541 return TARGET_ADDR24;
542
543 if (GET_CODE (op) == SYMBOL_REF)
544 sym = op;
545 else if (GET_CODE (op) == CONST
546 && GET_CODE (XEXP (op, 0)) == PLUS
547 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
548 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
549 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
550 sym = XEXP (XEXP (op, 0), 0);
551 else
552 return 0;
553
554 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
555 return 1;
556
557 if (TARGET_ADDR24
558 && (CONSTANT_POOL_ADDRESS_P (sym)
559 || LIT_NAME_P (XSTR (sym, 0))))
560 return 1;
561
562 return 0;
563 }
564
565 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
566
567 int
568 addr32_operand (rtx op, enum machine_mode mode)
569 {
570 rtx sym;
571
572 if (GET_CODE (op) == LABEL_REF)
573 return TARGET_ADDR32;
574
575 if (GET_CODE (op) == SYMBOL_REF)
576 sym = op;
577 else if (GET_CODE (op) == CONST
578 && GET_CODE (XEXP (op, 0)) == PLUS
579 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
580 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
581 && ! flag_pic)
582 sym = XEXP (XEXP (op, 0), 0);
583 else
584 return 0;
585
586 return (! addr24_operand (sym, mode)
587 && ! small_data_operand (sym, mode));
588 }
589
590 /* Return 1 if OP is a function that can be called with the `bl' insn. */
591
592 int
593 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
594 {
595 if (flag_pic)
596 return 1;
597
598 if (GET_CODE (op) == SYMBOL_REF)
599 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
600
601 return TARGET_CALL26;
602 }
603
604 /* Returns 1 if OP is an acceptable operand for seth/add3. */
605
606 int
607 seth_add3_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
608 {
609 if (flag_pic)
610 return 0;
611
612 if (GET_CODE (op) == SYMBOL_REF
613 || GET_CODE (op) == LABEL_REF)
614 return 1;
615
616 if (GET_CODE (op) == CONST
617 && GET_CODE (XEXP (op, 0)) == PLUS
618 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
619 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
620 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
621 return 1;
622
623 return 0;
624 }
625
626 /* Return true if OP is a signed 8 bit immediate value. */
627
628 int
629 int8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
630 {
631 if (GET_CODE (op) != CONST_INT)
632 return 0;
633 return INT8_P (INTVAL (op));
634 }
635
636 /* Return true if OP is a signed 16 bit immediate value
637 useful in comparisons. */
638
639 int
640 cmp_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
641 {
642 if (GET_CODE (op) != CONST_INT)
643 return 0;
644 return CMP_INT16_P (INTVAL (op));
645 }
646
647 /* Return true if OP is an unsigned 16 bit immediate value. */
648
649 int
650 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
651 {
652 if (GET_CODE (op) != CONST_INT)
653 return 0;
654 return UINT16_P (INTVAL (op));
655 }
656
657 /* Return true if OP is a register or signed 16 bit value. */
658
659 int
660 reg_or_int16_operand (rtx op, enum machine_mode mode)
661 {
662 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
663 return register_operand (op, mode);
664 if (GET_CODE (op) != CONST_INT)
665 return 0;
666 return INT16_P (INTVAL (op));
667 }
668
669 /* Return true if OP is a register or an unsigned 16 bit value. */
670
671 int
672 reg_or_uint16_operand (rtx op, enum machine_mode mode)
673 {
674 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
675 return register_operand (op, mode);
676 if (GET_CODE (op) != CONST_INT)
677 return 0;
678 return UINT16_P (INTVAL (op));
679 }
680
681 /* Return true if OP is a register or an integer value that can be
682 used is SEQ/SNE. We can use either XOR of the value or ADD of
683 the negative of the value for the constant. Don't allow 0,
684 because that is special cased. */
685
686 int
687 reg_or_eq_int16_operand (rtx op, enum machine_mode mode)
688 {
689 HOST_WIDE_INT value;
690
691 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
692 return register_operand (op, mode);
693
694 if (GET_CODE (op) != CONST_INT)
695 return 0;
696
697 value = INTVAL (op);
698 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
699 }
700
701 /* Return true if OP is a register or signed 16 bit value for compares. */
702
703 int
704 reg_or_cmp_int16_operand (rtx op, enum machine_mode mode)
705 {
706 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
707 return register_operand (op, mode);
708 if (GET_CODE (op) != CONST_INT)
709 return 0;
710 return CMP_INT16_P (INTVAL (op));
711 }
712
713 /* Return true if OP is a register or the constant 0. */
714
715 int
716 reg_or_zero_operand (rtx op, enum machine_mode mode)
717 {
718 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
719 return register_operand (op, mode);
720
721 if (GET_CODE (op) != CONST_INT)
722 return 0;
723
724 return INTVAL (op) == 0;
725 }
726
727 /* Return true if OP is a const_int requiring two instructions to load. */
728
729 int
730 two_insn_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
731 {
732 if (GET_CODE (op) != CONST_INT)
733 return 0;
734 if (INT16_P (INTVAL (op))
735 || UINT24_P (INTVAL (op))
736 || UPPER16_P (INTVAL (op)))
737 return 0;
738 return 1;
739 }
740
741 /* Return true if OP is an acceptable argument for a single word
742 move source. */
743
744 int
745 move_src_operand (rtx op, enum machine_mode mode)
746 {
747 switch (GET_CODE (op))
748 {
749 case LABEL_REF :
750 case SYMBOL_REF :
751 case CONST :
752 return addr24_operand (op, mode);
753 case CONST_INT :
754 /* ??? We allow more cse opportunities if we only allow constants
755 loadable with one insn, and split the rest into two. The instances
756 where this would help should be rare and the current way is
757 simpler. */
758 if (HOST_BITS_PER_WIDE_INT > 32)
759 {
760 HOST_WIDE_INT rest = INTVAL (op) >> 31;
761 return (rest == 0 || rest == -1);
762 }
763 else
764 return 1;
765 case CONST_DOUBLE :
766 if (mode == SFmode)
767 return 1;
768 else if (mode == SImode)
769 {
770 /* Large unsigned constants are represented as const_double's. */
771 unsigned HOST_WIDE_INT low, high;
772
773 low = CONST_DOUBLE_LOW (op);
774 high = CONST_DOUBLE_HIGH (op);
775 return high == 0 && low <= (unsigned) 0xffffffff;
776 }
777 else
778 return 0;
779 case REG :
780 return register_operand (op, mode);
781 case SUBREG :
782 /* (subreg (mem ...) ...) can occur here if the inner part was once a
783 pseudo-reg and is now a stack slot. */
784 if (GET_CODE (SUBREG_REG (op)) == MEM)
785 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
786 else
787 return register_operand (op, mode);
788 case MEM :
789 if (GET_CODE (XEXP (op, 0)) == PRE_INC
790 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
791 return 0; /* loads can't do pre-{inc,dec} */
792 return address_operand (XEXP (op, 0), mode);
793 default :
794 return 0;
795 }
796 }
797
798 /* Return true if OP is an acceptable argument for a double word
799 move source. */
800
801 int
802 move_double_src_operand (rtx op, enum machine_mode mode)
803 {
804 switch (GET_CODE (op))
805 {
806 case CONST_INT :
807 case CONST_DOUBLE :
808 return 1;
809 case REG :
810 return register_operand (op, mode);
811 case SUBREG :
812 /* (subreg (mem ...) ...) can occur here if the inner part was once a
813 pseudo-reg and is now a stack slot. */
814 if (GET_CODE (SUBREG_REG (op)) == MEM)
815 return move_double_src_operand (SUBREG_REG (op), mode);
816 else
817 return register_operand (op, mode);
818 case MEM :
819 /* Disallow auto inc/dec for now. */
820 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
821 || GET_CODE (XEXP (op, 0)) == PRE_INC)
822 return 0;
823 return address_operand (XEXP (op, 0), mode);
824 default :
825 return 0;
826 }
827 }
828
829 /* Return true if OP is an acceptable argument for a move destination. */
830
831 int
832 move_dest_operand (rtx op, enum machine_mode mode)
833 {
834 switch (GET_CODE (op))
835 {
836 case REG :
837 return register_operand (op, mode);
838 case SUBREG :
839 /* (subreg (mem ...) ...) can occur here if the inner part was once a
840 pseudo-reg and is now a stack slot. */
841 if (GET_CODE (SUBREG_REG (op)) == MEM)
842 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
843 else
844 return register_operand (op, mode);
845 case MEM :
846 if (GET_CODE (XEXP (op, 0)) == POST_INC)
847 return 0; /* stores can't do post inc */
848 return address_operand (XEXP (op, 0), mode);
849 default :
850 return 0;
851 }
852 }
853
854 /* Return 1 if OP is a DImode const we want to handle inline.
855 This must match the code in the movdi pattern.
856 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
857
858 int
859 easy_di_const (rtx op)
860 {
861 rtx high_rtx, low_rtx;
862 HOST_WIDE_INT high, low;
863
864 split_double (op, &high_rtx, &low_rtx);
865 high = INTVAL (high_rtx);
866 low = INTVAL (low_rtx);
867 /* Pick constants loadable with 2 16 bit `ldi' insns. */
868 if (high >= -128 && high <= 127
869 && low >= -128 && low <= 127)
870 return 1;
871 return 0;
872 }
873
874 /* Return 1 if OP is a DFmode const we want to handle inline.
875 This must match the code in the movdf pattern.
876 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
877
878 int
879 easy_df_const (rtx op)
880 {
881 REAL_VALUE_TYPE r;
882 long l[2];
883
884 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
885 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
886 if (l[0] == 0 && l[1] == 0)
887 return 1;
888 if ((l[0] & 0xffff) == 0 && l[1] == 0)
889 return 1;
890 return 0;
891 }
892
893 /* Return 1 if OP is an EQ or NE comparison operator. */
894
895 int
896 eqne_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
897 {
898 enum rtx_code code = GET_CODE (op);
899
900 return (code == EQ || code == NE);
901 }
902
903 /* Return 1 if OP is a signed comparison operator. */
904
905 int
906 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
907 {
908 enum rtx_code code = GET_CODE (op);
909
910 return (COMPARISON_P (op)
911 && (code == EQ || code == NE
912 || code == LT || code == LE || code == GT || code == GE));
913 }
914
915 /* Return 1 if OP is (mem (reg ...)).
916 This is used in insn length calcs. */
917
918 int
919 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
920 {
921 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
922 }
923
924 /* Return true if OP is an acceptable input argument for a zero/sign extend
925 operation. */
926
927 int
928 extend_operand (rtx op, enum machine_mode mode)
929 {
930 rtx addr;
931
932 switch (GET_CODE (op))
933 {
934 case REG :
935 case SUBREG :
936 return register_operand (op, mode);
937
938 case MEM :
939 addr = XEXP (op, 0);
940 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
941 return 0; /* loads can't do pre inc/pre dec */
942
943 return address_operand (addr, mode);
944
945 default :
946 return 0;
947 }
948 }
949
950 /* Return nonzero if the operand is an insn that is a small insn.
951 Allow const_int 0 as well, which is a placeholder for NOP slots. */
952
953 int
954 small_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
955 {
956 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
957 return 1;
958
959 if (! INSN_P (op))
960 return 0;
961
962 return get_attr_length (op) == 2;
963 }
964
965 /* Return nonzero if the operand is an insn that is a large insn. */
966
967 int
968 large_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
969 {
970 if (! INSN_P (op))
971 return 0;
972
973 return get_attr_length (op) != 2;
974 }
975
976 /* Return nonzero if TYPE must be passed by indirect reference. */
977
978 static bool
979 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
980 enum machine_mode mode, tree type,
981 bool named ATTRIBUTE_UNUSED)
982 {
983 int size;
984
985 if (type)
986 size = int_size_in_bytes (type);
987 else
988 size = GET_MODE_SIZE (mode);
989
990 return (size < 0 || size > 8);
991 }
992 \f
993 /* Comparisons. */
994
995 /* X and Y are two things to compare using CODE. Emit the compare insn and
996 return the rtx for compare [arg0 of the if_then_else].
997 If need_compare is true then the comparison insn must be generated, rather
998 than being subsumed into the following branch instruction. */
999
1000 rtx
1001 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
1002 {
1003 enum rtx_code compare_code;
1004 enum rtx_code branch_code;
1005 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1006 int must_swap = 0;
1007
1008 switch (code)
1009 {
1010 case EQ: compare_code = EQ; branch_code = NE; break;
1011 case NE: compare_code = EQ; branch_code = EQ; break;
1012 case LT: compare_code = LT; branch_code = NE; break;
1013 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1014 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1015 case GE: compare_code = LT; branch_code = EQ; break;
1016 case LTU: compare_code = LTU; branch_code = NE; break;
1017 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1018 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1019 case GEU: compare_code = LTU; branch_code = EQ; break;
1020
1021 default:
1022 abort ();
1023 }
1024
1025 if (need_compare)
1026 {
1027 switch (compare_code)
1028 {
1029 case EQ:
1030 if (GET_CODE (y) == CONST_INT
1031 && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
1032 && y != const0_rtx)
1033 {
1034 rtx tmp = gen_reg_rtx (SImode);
1035
1036 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1037 x = tmp;
1038 y = const0_rtx;
1039 }
1040 else if (CONSTANT_P (y)) /* Reg equal to const. */
1041 {
1042 rtx tmp = force_reg (GET_MODE (x), y);
1043 y = tmp;
1044 }
1045
1046 if (register_operand (y, SImode) /* Reg equal to reg. */
1047 || y == const0_rtx) /* Reg equal to zero. */
1048 {
1049 emit_insn (gen_cmp_eqsi_insn (x, y));
1050
1051 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1052 }
1053 break;
1054
1055 case LT:
1056 if (register_operand (y, SImode)
1057 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1058 {
1059 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
1060
1061 switch (code)
1062 {
1063 case LT:
1064 emit_insn (gen_cmp_ltsi_insn (x, y));
1065 code = EQ;
1066 break;
1067 case LE:
1068 if (y == const0_rtx)
1069 tmp = const1_rtx;
1070 else
1071 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1072 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1073 code = EQ;
1074 break;
1075 case GT:
1076 if (GET_CODE (y) == CONST_INT)
1077 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1078 else
1079 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1080 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1081 code = NE;
1082 break;
1083 case GE:
1084 emit_insn (gen_cmp_ltsi_insn (x, y));
1085 code = NE;
1086 break;
1087 default:
1088 abort ();
1089 }
1090
1091 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1092 }
1093 break;
1094
1095 case LTU:
1096 if (register_operand (y, SImode)
1097 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1098 {
1099 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
1100
1101 switch (code)
1102 {
1103 case LTU:
1104 emit_insn (gen_cmp_ltusi_insn (x, y));
1105 code = EQ;
1106 break;
1107 case LEU:
1108 if (y == const0_rtx)
1109 tmp = const1_rtx;
1110 else
1111 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1112 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1113 code = EQ;
1114 break;
1115 case GTU:
1116 if (GET_CODE (y) == CONST_INT)
1117 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1118 else
1119 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1120 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1121 code = NE;
1122 break;
1123 case GEU:
1124 emit_insn (gen_cmp_ltusi_insn (x, y));
1125 code = NE;
1126 break;
1127 default:
1128 abort();
1129 }
1130
1131 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1132 }
1133 break;
1134
1135 default:
1136 abort();
1137 }
1138 }
1139 else
1140 {
1141 /* Reg/reg equal comparison. */
1142 if (compare_code == EQ
1143 && register_operand (y, SImode))
1144 return gen_rtx_fmt_ee (code, CCmode, x, y);
1145
1146 /* Reg/zero signed comparison. */
1147 if ((compare_code == EQ || compare_code == LT)
1148 && y == const0_rtx)
1149 return gen_rtx_fmt_ee (code, CCmode, x, y);
1150
1151 /* Reg/smallconst equal comparison. */
1152 if (compare_code == EQ
1153 && GET_CODE (y) == CONST_INT
1154 && CMP_INT16_P (INTVAL (y)))
1155 {
1156 rtx tmp = gen_reg_rtx (SImode);
1157
1158 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1159 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
1160 }
1161
1162 /* Reg/const equal comparison. */
1163 if (compare_code == EQ
1164 && CONSTANT_P (y))
1165 {
1166 rtx tmp = force_reg (GET_MODE (x), y);
1167
1168 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
1169 }
1170 }
1171
1172 if (CONSTANT_P (y))
1173 {
1174 if (must_swap)
1175 y = force_reg (GET_MODE (x), y);
1176 else
1177 {
1178 int ok_const =
1179 (code == LTU || code == LEU || code == GTU || code == GEU)
1180 ? uint16_operand (y, GET_MODE (y))
1181 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1182
1183 if (! ok_const)
1184 y = force_reg (GET_MODE (x), y);
1185 }
1186 }
1187
1188 switch (compare_code)
1189 {
1190 case EQ :
1191 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1192 break;
1193 case LT :
1194 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1195 break;
1196 case LTU :
1197 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1198 break;
1199
1200 default:
1201 abort ();
1202 }
1203
1204 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1205 }
1206 \f
1207 /* Split a 2 word move (DI or DF) into component parts. */
1208
1209 rtx
1210 gen_split_move_double (rtx operands[])
1211 {
1212 enum machine_mode mode = GET_MODE (operands[0]);
1213 rtx dest = operands[0];
1214 rtx src = operands[1];
1215 rtx val;
1216
1217 /* We might have (SUBREG (MEM)) here, so just get rid of the
1218 subregs to make this code simpler. It is safe to call
1219 alter_subreg any time after reload. */
1220 if (GET_CODE (dest) == SUBREG)
1221 alter_subreg (&dest);
1222 if (GET_CODE (src) == SUBREG)
1223 alter_subreg (&src);
1224
1225 start_sequence ();
1226 if (GET_CODE (dest) == REG)
1227 {
1228 int dregno = REGNO (dest);
1229
1230 /* Reg = reg. */
1231 if (GET_CODE (src) == REG)
1232 {
1233 int sregno = REGNO (src);
1234
1235 int reverse = (dregno == sregno + 1);
1236
1237 /* We normally copy the low-numbered register first. However, if
1238 the first register operand 0 is the same as the second register of
1239 operand 1, we must copy in the opposite order. */
1240 emit_insn (gen_rtx_SET (VOIDmode,
1241 operand_subword (dest, reverse, TRUE, mode),
1242 operand_subword (src, reverse, TRUE, mode)));
1243
1244 emit_insn (gen_rtx_SET (VOIDmode,
1245 operand_subword (dest, !reverse, TRUE, mode),
1246 operand_subword (src, !reverse, TRUE, mode)));
1247 }
1248
1249 /* Reg = constant. */
1250 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1251 {
1252 rtx words[2];
1253 split_double (src, &words[0], &words[1]);
1254 emit_insn (gen_rtx_SET (VOIDmode,
1255 operand_subword (dest, 0, TRUE, mode),
1256 words[0]));
1257
1258 emit_insn (gen_rtx_SET (VOIDmode,
1259 operand_subword (dest, 1, TRUE, mode),
1260 words[1]));
1261 }
1262
1263 /* Reg = mem. */
1264 else if (GET_CODE (src) == MEM)
1265 {
1266 /* If the high-address word is used in the address, we must load it
1267 last. Otherwise, load it first. */
1268 int reverse
1269 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1270
1271 /* We used to optimize loads from single registers as
1272
1273 ld r1,r3+; ld r2,r3
1274
1275 if r3 were not used subsequently. However, the REG_NOTES aren't
1276 propagated correctly by the reload phase, and it can cause bad
1277 code to be generated. We could still try:
1278
1279 ld r1,r3+; ld r2,r3; addi r3,-4
1280
1281 which saves 2 bytes and doesn't force longword alignment. */
1282 emit_insn (gen_rtx_SET (VOIDmode,
1283 operand_subword (dest, reverse, TRUE, mode),
1284 adjust_address (src, SImode,
1285 reverse * UNITS_PER_WORD)));
1286
1287 emit_insn (gen_rtx_SET (VOIDmode,
1288 operand_subword (dest, !reverse, TRUE, mode),
1289 adjust_address (src, SImode,
1290 !reverse * UNITS_PER_WORD)));
1291 }
1292 else
1293 abort ();
1294 }
1295
1296 /* Mem = reg. */
1297 /* We used to optimize loads from single registers as
1298
1299 st r1,r3; st r2,+r3
1300
1301 if r3 were not used subsequently. However, the REG_NOTES aren't
1302 propagated correctly by the reload phase, and it can cause bad
1303 code to be generated. We could still try:
1304
1305 st r1,r3; st r2,+r3; addi r3,-4
1306
1307 which saves 2 bytes and doesn't force longword alignment. */
1308 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1309 {
1310 emit_insn (gen_rtx_SET (VOIDmode,
1311 adjust_address (dest, SImode, 0),
1312 operand_subword (src, 0, TRUE, mode)));
1313
1314 emit_insn (gen_rtx_SET (VOIDmode,
1315 adjust_address (dest, SImode, UNITS_PER_WORD),
1316 operand_subword (src, 1, TRUE, mode)));
1317 }
1318
1319 else
1320 abort ();
1321
1322 val = get_insns ();
1323 end_sequence ();
1324 return val;
1325 }
1326
1327 \f
1328 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1329
1330 int
1331 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1332 tree type, int named ATTRIBUTE_UNUSED)
1333 {
1334 int ret;
1335 unsigned int size =
1336 (((mode == BLKmode && type)
1337 ? (unsigned int) int_size_in_bytes (type)
1338 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1339 / UNITS_PER_WORD;
1340
1341 if (*cum >= M32R_MAX_PARM_REGS)
1342 ret = 0;
1343 else if (*cum + size > M32R_MAX_PARM_REGS)
1344 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1345 else
1346 ret = 0;
1347
1348 return ret;
1349 }
1350
1351 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1352
1353 static bool
1354 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1355 {
1356 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1357 }
1358
1359 /* Do any needed setup for a variadic function. For the M32R, we must
1360 create a register parameter block, and then copy any anonymous arguments
1361 in registers to memory.
1362
1363 CUM has not been updated for the last named argument which has type TYPE
1364 and mode MODE, and we rely on this fact. */
1365
1366 static void
1367 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1368 tree type, int *pretend_size, int no_rtl)
1369 {
1370 int first_anon_arg;
1371
1372 if (no_rtl)
1373 return;
1374
1375 /* All BLKmode values are passed by reference. */
1376 if (mode == BLKmode)
1377 abort ();
1378
1379 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1380 + ROUND_ADVANCE_ARG (mode, type));
1381
1382 if (first_anon_arg < M32R_MAX_PARM_REGS)
1383 {
1384 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1385 int first_reg_offset = first_anon_arg;
1386 /* Size in words to "pretend" allocate. */
1387 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1388 rtx regblock;
1389
1390 regblock = gen_rtx_MEM (BLKmode,
1391 plus_constant (arg_pointer_rtx,
1392 FIRST_PARM_OFFSET (0)));
1393 set_mem_alias_set (regblock, get_varargs_alias_set ());
1394 move_block_from_reg (first_reg_offset, regblock, size);
1395
1396 *pretend_size = (size * UNITS_PER_WORD);
1397 }
1398 }
1399
1400 \f
1401 /* Return true if INSN is real instruction bearing insn. */
1402
1403 static int
1404 m32r_is_insn (rtx insn)
1405 {
1406 return (INSN_P (insn)
1407 && GET_CODE (PATTERN (insn)) != USE
1408 && GET_CODE (PATTERN (insn)) != CLOBBER
1409 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1410 }
1411
1412 /* Increase the priority of long instructions so that the
1413 short instructions are scheduled ahead of the long ones. */
1414
1415 static int
1416 m32r_adjust_priority (rtx insn, int priority)
1417 {
1418 if (m32r_is_insn (insn)
1419 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1420 priority <<= 3;
1421
1422 return priority;
1423 }
1424
1425 \f
1426 /* Indicate how many instructions can be issued at the same time.
1427 This is sort of a lie. The m32r can issue only 1 long insn at
1428 once, but it can issue 2 short insns. The default therefore is
1429 set at 2, but this can be overridden by the command line option
1430 -missue-rate=1. */
1431
1432 static int
1433 m32r_issue_rate (void)
1434 {
1435 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1436 }
1437 \f
1438 /* Cost functions. */
1439
1440 static bool
1441 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1442 {
1443 switch (code)
1444 {
1445 /* Small integers are as cheap as registers. 4 byte values can be
1446 fetched as immediate constants - let's give that the cost of an
1447 extra insn. */
1448 case CONST_INT:
1449 if (INT16_P (INTVAL (x)))
1450 {
1451 *total = 0;
1452 return true;
1453 }
1454 /* FALLTHRU */
1455
1456 case CONST:
1457 case LABEL_REF:
1458 case SYMBOL_REF:
1459 *total = COSTS_N_INSNS (1);
1460 return true;
1461
1462 case CONST_DOUBLE:
1463 {
1464 rtx high, low;
1465
1466 split_double (x, &high, &low);
1467 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1468 + !INT16_P (INTVAL (low)));
1469 return true;
1470 }
1471
1472 case MULT:
1473 *total = COSTS_N_INSNS (3);
1474 return true;
1475
1476 case DIV:
1477 case UDIV:
1478 case MOD:
1479 case UMOD:
1480 *total = COSTS_N_INSNS (10);
1481 return true;
1482
1483 default:
1484 return false;
1485 }
1486 }
1487 \f
1488 /* Type of function DECL.
1489
1490 The result is cached. To reset the cache at the end of a function,
1491 call with DECL = NULL_TREE. */
1492
1493 enum m32r_function_type
1494 m32r_compute_function_type (tree decl)
1495 {
1496 /* Cached value. */
1497 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1498 /* Last function we were called for. */
1499 static tree last_fn = NULL_TREE;
1500
1501 /* Resetting the cached value? */
1502 if (decl == NULL_TREE)
1503 {
1504 fn_type = M32R_FUNCTION_UNKNOWN;
1505 last_fn = NULL_TREE;
1506 return fn_type;
1507 }
1508
1509 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1510 return fn_type;
1511
1512 /* Compute function type. */
1513 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1514 ? M32R_FUNCTION_INTERRUPT
1515 : M32R_FUNCTION_NORMAL);
1516
1517 last_fn = decl;
1518 return fn_type;
1519 }
1520 \f/* Function prologue/epilogue handlers. */
1521
1522 /* M32R stack frames look like:
1523
1524 Before call After call
1525 +-----------------------+ +-----------------------+
1526 | | | |
1527 high | local variables, | | local variables, |
1528 mem | reg save area, etc. | | reg save area, etc. |
1529 | | | |
1530 +-----------------------+ +-----------------------+
1531 | | | |
1532 | arguments on stack. | | arguments on stack. |
1533 | | | |
1534 SP+0->+-----------------------+ +-----------------------+
1535 | reg parm save area, |
1536 | only created for |
1537 | variable argument |
1538 | functions |
1539 +-----------------------+
1540 | previous frame ptr |
1541 +-----------------------+
1542 | |
1543 | register save area |
1544 | |
1545 +-----------------------+
1546 | return address |
1547 +-----------------------+
1548 | |
1549 | local variables |
1550 | |
1551 +-----------------------+
1552 | |
1553 | alloca allocations |
1554 | |
1555 +-----------------------+
1556 | |
1557 low | arguments on stack |
1558 memory | |
1559 SP+0->+-----------------------+
1560
1561 Notes:
1562 1) The "reg parm save area" does not exist for non variable argument fns.
1563 2) The "reg parm save area" can be eliminated completely if we saved regs
1564 containing anonymous args separately but that complicates things too
1565 much (so it's not done).
1566 3) The return address is saved after the register save area so as to have as
1567 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1568
1569 /* Structure to be filled in by m32r_compute_frame_size with register
1570 save masks, and offsets for the current function. */
1571 struct m32r_frame_info
1572 {
1573 unsigned int total_size; /* # bytes that the entire frame takes up. */
1574 unsigned int extra_size; /* # bytes of extra stuff. */
1575 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1576 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1577 unsigned int reg_size; /* # bytes needed to store regs. */
1578 unsigned int var_size; /* # bytes that variables take up. */
1579 unsigned int gmask; /* Mask of saved gp registers. */
1580 unsigned int save_fp; /* Nonzero if fp must be saved. */
1581 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1582 int initialized; /* Nonzero if frame size already calculated. */
1583 };
1584
1585 /* Current frame information calculated by m32r_compute_frame_size. */
1586 static struct m32r_frame_info current_frame_info;
1587
1588 /* Zero structure to initialize current_frame_info. */
1589 static struct m32r_frame_info zero_frame_info;
1590
1591 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1592 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1593
1594 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1595 The return address and frame pointer are treated separately.
1596 Don't consider them here. */
1597 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1598 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1599 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1600
1601 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1602 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1603
1604 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1605 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1606
1607 /* Return the bytes needed to compute the frame pointer from the current
1608 stack pointer.
1609
1610 SIZE is the size needed for local variables. */
1611
1612 unsigned int
1613 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1614 {
1615 int regno;
1616 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1617 unsigned int reg_size, frame_size;
1618 unsigned int gmask;
1619 enum m32r_function_type fn_type;
1620 int interrupt_p;
1621 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1622
1623 var_size = M32R_STACK_ALIGN (size);
1624 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1625 pretend_size = current_function_pretend_args_size;
1626 extra_size = FIRST_PARM_OFFSET (0);
1627 total_size = extra_size + pretend_size + args_size + var_size;
1628 reg_size = 0;
1629 gmask = 0;
1630
1631 /* See if this is an interrupt handler. Call used registers must be saved
1632 for them too. */
1633 fn_type = m32r_compute_function_type (current_function_decl);
1634 interrupt_p = M32R_INTERRUPT_P (fn_type);
1635
1636 /* Calculate space needed for registers. */
1637 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1638 {
1639 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1640 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1641 {
1642 reg_size += UNITS_PER_WORD;
1643 gmask |= 1 << regno;
1644 }
1645 }
1646
1647 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1648 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1649
1650 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1651 * UNITS_PER_WORD);
1652 total_size += reg_size;
1653
1654 /* ??? Not sure this is necessary, and I don't think the epilogue
1655 handler will do the right thing if this changes total_size. */
1656 total_size = M32R_STACK_ALIGN (total_size);
1657
1658 frame_size = total_size - (pretend_size + reg_size);
1659
1660 /* Save computed information. */
1661 current_frame_info.total_size = total_size;
1662 current_frame_info.extra_size = extra_size;
1663 current_frame_info.pretend_size = pretend_size;
1664 current_frame_info.var_size = var_size;
1665 current_frame_info.args_size = args_size;
1666 current_frame_info.reg_size = reg_size;
1667 current_frame_info.gmask = gmask;
1668 current_frame_info.initialized = reload_completed;
1669
1670 /* Ok, we're done. */
1671 return total_size;
1672 }
1673 \f
1674 /* The table we use to reference PIC data. */
1675 static rtx global_offset_table;
1676
1677 static void
1678 m32r_reload_lr (rtx sp, int size)
1679 {
1680 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1681
1682 if (size == 0)
1683 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1684 else if (size <= 32768)
1685 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1686 gen_rtx_PLUS (Pmode, sp,
1687 GEN_INT (size)))));
1688 else
1689 {
1690 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1691
1692 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1693 emit_insn (gen_addsi3 (tmp, tmp, sp));
1694 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1695 }
1696
1697 emit_insn (gen_rtx_USE (VOIDmode, lr));
1698 }
1699
1700 void
1701 m32r_load_pic_register (void)
1702 {
1703 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1704 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1705 GEN_INT (TARGET_MODEL_SMALL)));
1706
1707 /* Need to emit this whether or not we obey regdecls,
1708 since setjmp/longjmp can cause life info to screw up. */
1709 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1710 }
1711
1712 /* Expand the m32r prologue as a series of insns. */
1713
1714 void
1715 m32r_expand_prologue (void)
1716 {
1717 int regno;
1718 int frame_size;
1719 unsigned int gmask;
1720 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1721
1722 if (! current_frame_info.initialized)
1723 m32r_compute_frame_size (get_frame_size ());
1724
1725 gmask = current_frame_info.gmask;
1726
1727 /* These cases shouldn't happen. Catch them now. */
1728 if (current_frame_info.total_size == 0 && gmask)
1729 abort ();
1730
1731 /* Allocate space for register arguments if this is a variadic function. */
1732 if (current_frame_info.pretend_size != 0)
1733 {
1734 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1735 the wrong result on a 64-bit host. */
1736 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1737 emit_insn (gen_addsi3 (stack_pointer_rtx,
1738 stack_pointer_rtx,
1739 GEN_INT (-pretend_size)));
1740 }
1741
1742 /* Save any registers we need to and set up fp. */
1743 if (current_frame_info.save_fp)
1744 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1745
1746 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1747
1748 /* Save any needed call-saved regs (and call-used if this is an
1749 interrupt handler). */
1750 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1751 {
1752 if ((gmask & (1 << regno)) != 0)
1753 emit_insn (gen_movsi_push (stack_pointer_rtx,
1754 gen_rtx_REG (Pmode, regno)));
1755 }
1756
1757 if (current_frame_info.save_lr)
1758 emit_insn (gen_movsi_push (stack_pointer_rtx,
1759 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1760
1761 /* Allocate the stack frame. */
1762 frame_size = (current_frame_info.total_size
1763 - (current_frame_info.pretend_size
1764 + current_frame_info.reg_size));
1765
1766 if (frame_size == 0)
1767 ; /* Nothing to do. */
1768 else if (frame_size <= 32768)
1769 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1770 GEN_INT (-frame_size)));
1771 else
1772 {
1773 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1774
1775 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1776 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1777 }
1778
1779 if (frame_pointer_needed)
1780 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1781
1782 if (current_function_profile)
1783 /* Push lr for mcount (form_pc, x). */
1784 emit_insn (gen_movsi_push (stack_pointer_rtx,
1785 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1786
1787 if (pic_reg_used)
1788 {
1789 m32r_load_pic_register ();
1790 m32r_reload_lr (stack_pointer_rtx,
1791 (current_function_profile ? 0 : frame_size));
1792 }
1793
1794 if (current_function_profile && !pic_reg_used)
1795 emit_insn (gen_blockage ());
1796 }
1797
1798 \f
1799 /* Set up the stack and frame pointer (if desired) for the function.
1800 Note, if this is changed, you need to mirror the changes in
1801 m32r_compute_frame_size which calculates the prolog size. */
1802
1803 static void
1804 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1805 {
1806 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1807
1808 /* If this is an interrupt handler, mark it as such. */
1809 if (M32R_INTERRUPT_P (fn_type))
1810 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1811
1812 if (! current_frame_info.initialized)
1813 m32r_compute_frame_size (size);
1814
1815 /* This is only for the human reader. */
1816 fprintf (file,
1817 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1818 ASM_COMMENT_START,
1819 current_frame_info.var_size,
1820 current_frame_info.reg_size / 4,
1821 current_frame_info.args_size,
1822 current_frame_info.extra_size);
1823 }
1824 \f
1825 /* Do any necessary cleanup after a function to restore stack, frame,
1826 and regs. */
1827
1828 static void
1829 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1830 {
1831 int regno;
1832 int noepilogue = FALSE;
1833 int total_size;
1834 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1835
1836 /* This is only for the human reader. */
1837 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1838
1839 if (!current_frame_info.initialized)
1840 abort ();
1841 total_size = current_frame_info.total_size;
1842
1843 if (total_size == 0)
1844 {
1845 rtx insn = get_last_insn ();
1846
1847 /* If the last insn was a BARRIER, we don't have to write any code
1848 because a jump (aka return) was put there. */
1849 if (GET_CODE (insn) == NOTE)
1850 insn = prev_nonnote_insn (insn);
1851 if (insn && GET_CODE (insn) == BARRIER)
1852 noepilogue = TRUE;
1853 }
1854
1855 if (!noepilogue)
1856 {
1857 unsigned int var_size = current_frame_info.var_size;
1858 unsigned int args_size = current_frame_info.args_size;
1859 unsigned int gmask = current_frame_info.gmask;
1860 int can_trust_sp_p = !current_function_calls_alloca;
1861 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1862 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1863
1864 /* The first thing to do is point the sp at the bottom of the register
1865 save area. */
1866 if (can_trust_sp_p)
1867 {
1868 unsigned int reg_offset = var_size + args_size;
1869 if (reg_offset == 0)
1870 ; /* Nothing to do. */
1871 else if (reg_offset < 128)
1872 fprintf (file, "\taddi %s,%s%d\n",
1873 sp_str, IMMEDIATE_PREFIX, reg_offset);
1874 else if (reg_offset < 32768)
1875 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1876 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1877 else
1878 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1879 reg_names[PROLOGUE_TMP_REGNUM],
1880 IMMEDIATE_PREFIX, reg_offset,
1881 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1882 }
1883 else if (frame_pointer_needed)
1884 {
1885 unsigned int reg_offset = var_size + args_size;
1886
1887 if (reg_offset == 0)
1888 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1889 else if (reg_offset < 32768)
1890 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1891 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1892 else
1893 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1894 reg_names[PROLOGUE_TMP_REGNUM],
1895 IMMEDIATE_PREFIX, reg_offset,
1896 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1897 }
1898 else
1899 abort ();
1900
1901 if (current_frame_info.save_lr)
1902 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1903
1904 /* Restore any saved registers, in reverse order of course. */
1905 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1906 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1907 {
1908 if ((gmask & (1L << regno)) != 0)
1909 fprintf (file, "\tpop %s\n", reg_names[regno]);
1910 }
1911
1912 if (current_frame_info.save_fp)
1913 fprintf (file, "\tpop %s\n", fp_str);
1914
1915 /* Remove varargs area if present. */
1916 if (current_frame_info.pretend_size != 0)
1917 fprintf (file, "\taddi %s,%s%d\n",
1918 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1919
1920 /* Emit the return instruction. */
1921 if (M32R_INTERRUPT_P (fn_type))
1922 fprintf (file, "\trte\n");
1923 else
1924 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1925 }
1926
1927 /* Reset state info for each function. */
1928 current_frame_info = zero_frame_info;
1929 m32r_compute_function_type (NULL_TREE);
1930 }
1931 \f
1932 /* Return nonzero if this function is known to have a null or 1 instruction
1933 epilogue. */
1934
1935 int
1936 direct_return (void)
1937 {
1938 if (!reload_completed)
1939 return FALSE;
1940
1941 if (! current_frame_info.initialized)
1942 m32r_compute_frame_size (get_frame_size ());
1943
1944 return current_frame_info.total_size == 0;
1945 }
1946
1947 \f
1948 /* PIC. */
1949
1950 int
1951 m32r_legitimate_pic_operand_p (rtx x)
1952 {
1953 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1954 return 0;
1955
1956 if (GET_CODE (x) == CONST
1957 && GET_CODE (XEXP (x, 0)) == PLUS
1958 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1959 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1960 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1961 return 0;
1962
1963 return 1;
1964 }
1965
1966 rtx
1967 m32r_legitimize_pic_address (rtx orig, rtx reg)
1968 {
1969 #ifdef DEBUG_PIC
1970 printf("m32r_legitimize_pic_address()\n");
1971 #endif
1972
1973 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1974 {
1975 rtx pic_ref, address;
1976 rtx insn;
1977 int subregs = 0;
1978
1979 if (reg == 0)
1980 {
1981 if (reload_in_progress || reload_completed)
1982 abort ();
1983 else
1984 reg = gen_reg_rtx (Pmode);
1985
1986 subregs = 1;
1987 }
1988
1989 if (subregs)
1990 address = gen_reg_rtx (Pmode);
1991 else
1992 address = reg;
1993
1994 emit_insn (gen_pic_load_addr (address, orig));
1995
1996 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1997 pic_ref = gen_rtx_MEM (Pmode, address);
1998
1999 RTX_UNCHANGING_P (pic_ref) = 1;
2000 insn = emit_move_insn (reg, pic_ref);
2001 current_function_uses_pic_offset_table = 1;
2002 #if 0
2003 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2004 by loop. */
2005 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2006 REG_NOTES (insn));
2007 #endif
2008 return reg;
2009 }
2010 else if (GET_CODE (orig) == CONST)
2011 {
2012 rtx base, offset;
2013
2014 if (GET_CODE (XEXP (orig, 0)) == PLUS
2015 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
2016 return orig;
2017
2018 if (reg == 0)
2019 {
2020 if (reload_in_progress || reload_completed)
2021 abort ();
2022 else
2023 reg = gen_reg_rtx (Pmode);
2024 }
2025
2026 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2027 {
2028 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
2029 if (base == reg)
2030 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
2031 else
2032 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
2033 }
2034 else
2035 return orig;
2036
2037 if (GET_CODE (offset) == CONST_INT)
2038 {
2039 if (INT16_P (INTVAL (offset)))
2040 return plus_constant (base, INTVAL (offset));
2041 else if (! reload_in_progress && ! reload_completed)
2042 offset = force_reg (Pmode, offset);
2043 else
2044 /* If we reach here, then something is seriously wrong. */
2045 abort ();
2046 }
2047
2048 return gen_rtx_PLUS (Pmode, base, offset);
2049 }
2050
2051 return orig;
2052 }
2053
2054 /* Emit special PIC prologues and epilogues. */
2055
2056 void
2057 m32r_finalize_pic (void)
2058 {
2059 current_function_uses_pic_offset_table |= current_function_profile;
2060 }
2061 \f
2062 /* Nested function support. */
2063
2064 /* Emit RTL insns to initialize the variable parts of a trampoline.
2065 FNADDR is an RTX for the address of the function's pure code.
2066 CXT is an RTX for the static chain value for the function. */
2067
2068 void
2069 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2070 rtx fnaddr ATTRIBUTE_UNUSED,
2071 rtx cxt ATTRIBUTE_UNUSED)
2072 {
2073 }
2074 \f
2075 static void
2076 m32r_file_start (void)
2077 {
2078 default_file_start ();
2079
2080 if (flag_verbose_asm)
2081 fprintf (asm_out_file,
2082 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
2083 ASM_COMMENT_START, g_switch_value);
2084
2085 if (TARGET_LITTLE_ENDIAN)
2086 fprintf (asm_out_file, "\t.little\n");
2087 }
2088 \f
2089 /* Print operand X (an rtx) in assembler syntax to file FILE.
2090 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2091 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2092
2093 void
2094 m32r_print_operand (FILE * file, rtx x, int code)
2095 {
2096 rtx addr;
2097
2098 switch (code)
2099 {
2100 /* The 's' and 'p' codes are used by output_block_move() to
2101 indicate post-increment 's'tores and 'p're-increment loads. */
2102 case 's':
2103 if (GET_CODE (x) == REG)
2104 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2105 else
2106 output_operand_lossage ("invalid operand to %%s code");
2107 return;
2108
2109 case 'p':
2110 if (GET_CODE (x) == REG)
2111 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2112 else
2113 output_operand_lossage ("invalid operand to %%p code");
2114 return;
2115
2116 case 'R' :
2117 /* Write second word of DImode or DFmode reference,
2118 register or memory. */
2119 if (GET_CODE (x) == REG)
2120 fputs (reg_names[REGNO (x)+1], file);
2121 else if (GET_CODE (x) == MEM)
2122 {
2123 fprintf (file, "@(");
2124 /* Handle possible auto-increment. Since it is pre-increment and
2125 we have already done it, we can just use an offset of four. */
2126 /* ??? This is taken from rs6000.c I think. I don't think it is
2127 currently necessary, but keep it around. */
2128 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2129 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2130 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2131 else
2132 output_address (plus_constant (XEXP (x, 0), 4));
2133 fputc (')', file);
2134 }
2135 else
2136 output_operand_lossage ("invalid operand to %%R code");
2137 return;
2138
2139 case 'H' : /* High word. */
2140 case 'L' : /* Low word. */
2141 if (GET_CODE (x) == REG)
2142 {
2143 /* L = least significant word, H = most significant word. */
2144 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2145 fputs (reg_names[REGNO (x)], file);
2146 else
2147 fputs (reg_names[REGNO (x)+1], file);
2148 }
2149 else if (GET_CODE (x) == CONST_INT
2150 || GET_CODE (x) == CONST_DOUBLE)
2151 {
2152 rtx first, second;
2153
2154 split_double (x, &first, &second);
2155 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2156 code == 'L' ? INTVAL (first) : INTVAL (second));
2157 }
2158 else
2159 output_operand_lossage ("invalid operand to %%H/%%L code");
2160 return;
2161
2162 case 'A' :
2163 {
2164 char str[30];
2165
2166 if (GET_CODE (x) != CONST_DOUBLE
2167 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2168 fatal_insn ("bad insn for 'A'", x);
2169
2170 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2171 fprintf (file, "%s", str);
2172 return;
2173 }
2174
2175 case 'B' : /* Bottom half. */
2176 case 'T' : /* Top half. */
2177 /* Output the argument to a `seth' insn (sets the Top half-word).
2178 For constants output arguments to a seth/or3 pair to set Top and
2179 Bottom halves. For symbols output arguments to a seth/add3 pair to
2180 set Top and Bottom halves. The difference exists because for
2181 constants seth/or3 is more readable but for symbols we need to use
2182 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2183 switch (GET_CODE (x))
2184 {
2185 case CONST_INT :
2186 case CONST_DOUBLE :
2187 {
2188 rtx first, second;
2189
2190 split_double (x, &first, &second);
2191 x = WORDS_BIG_ENDIAN ? second : first;
2192 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2193 (code == 'B'
2194 ? INTVAL (x) & 0xffff
2195 : (INTVAL (x) >> 16) & 0xffff));
2196 }
2197 return;
2198 case CONST :
2199 case SYMBOL_REF :
2200 if (code == 'B'
2201 && small_data_operand (x, VOIDmode))
2202 {
2203 fputs ("sda(", file);
2204 output_addr_const (file, x);
2205 fputc (')', file);
2206 return;
2207 }
2208 /* fall through */
2209 case LABEL_REF :
2210 fputs (code == 'T' ? "shigh(" : "low(", file);
2211 output_addr_const (file, x);
2212 fputc (')', file);
2213 return;
2214 default :
2215 output_operand_lossage ("invalid operand to %%T/%%B code");
2216 return;
2217 }
2218 break;
2219
2220 case 'U' :
2221 /* ??? wip */
2222 /* Output a load/store with update indicator if appropriate. */
2223 if (GET_CODE (x) == MEM)
2224 {
2225 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2226 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2227 fputs (".a", file);
2228 }
2229 else
2230 output_operand_lossage ("invalid operand to %%U code");
2231 return;
2232
2233 case 'N' :
2234 /* Print a constant value negated. */
2235 if (GET_CODE (x) == CONST_INT)
2236 output_addr_const (file, GEN_INT (- INTVAL (x)));
2237 else
2238 output_operand_lossage ("invalid operand to %%N code");
2239 return;
2240
2241 case 'X' :
2242 /* Print a const_int in hex. Used in comments. */
2243 if (GET_CODE (x) == CONST_INT)
2244 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2245 return;
2246
2247 case '#' :
2248 fputs (IMMEDIATE_PREFIX, file);
2249 return;
2250
2251 case 0 :
2252 /* Do nothing special. */
2253 break;
2254
2255 default :
2256 /* Unknown flag. */
2257 output_operand_lossage ("invalid operand output code");
2258 }
2259
2260 switch (GET_CODE (x))
2261 {
2262 case REG :
2263 fputs (reg_names[REGNO (x)], file);
2264 break;
2265
2266 case MEM :
2267 addr = XEXP (x, 0);
2268 if (GET_CODE (addr) == PRE_INC)
2269 {
2270 if (GET_CODE (XEXP (addr, 0)) != REG)
2271 fatal_insn ("pre-increment address is not a register", x);
2272
2273 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2274 }
2275 else if (GET_CODE (addr) == PRE_DEC)
2276 {
2277 if (GET_CODE (XEXP (addr, 0)) != REG)
2278 fatal_insn ("pre-decrement address is not a register", x);
2279
2280 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2281 }
2282 else if (GET_CODE (addr) == POST_INC)
2283 {
2284 if (GET_CODE (XEXP (addr, 0)) != REG)
2285 fatal_insn ("post-increment address is not a register", x);
2286
2287 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2288 }
2289 else
2290 {
2291 fputs ("@(", file);
2292 output_address (XEXP (x, 0));
2293 fputc (')', file);
2294 }
2295 break;
2296
2297 case CONST_DOUBLE :
2298 /* We handle SFmode constants here as output_addr_const doesn't. */
2299 if (GET_MODE (x) == SFmode)
2300 {
2301 REAL_VALUE_TYPE d;
2302 long l;
2303
2304 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2305 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2306 fprintf (file, "0x%08lx", l);
2307 break;
2308 }
2309
2310 /* Fall through. Let output_addr_const deal with it. */
2311
2312 default :
2313 output_addr_const (file, x);
2314 break;
2315 }
2316 }
2317
2318 /* Print a memory address as an operand to reference that memory location. */
2319
2320 void
2321 m32r_print_operand_address (FILE * file, rtx addr)
2322 {
2323 rtx base;
2324 rtx index = 0;
2325 int offset = 0;
2326
2327 switch (GET_CODE (addr))
2328 {
2329 case REG :
2330 fputs (reg_names[REGNO (addr)], file);
2331 break;
2332
2333 case PLUS :
2334 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2335 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2336 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2337 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2338 else
2339 base = XEXP (addr, 0), index = XEXP (addr, 1);
2340 if (GET_CODE (base) == REG)
2341 {
2342 /* Print the offset first (if present) to conform to the manual. */
2343 if (index == 0)
2344 {
2345 if (offset != 0)
2346 fprintf (file, "%d,", offset);
2347 fputs (reg_names[REGNO (base)], file);
2348 }
2349 /* The chip doesn't support this, but left in for generality. */
2350 else if (GET_CODE (index) == REG)
2351 fprintf (file, "%s,%s",
2352 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2353 /* Not sure this can happen, but leave in for now. */
2354 else if (GET_CODE (index) == SYMBOL_REF)
2355 {
2356 output_addr_const (file, index);
2357 fputc (',', file);
2358 fputs (reg_names[REGNO (base)], file);
2359 }
2360 else
2361 fatal_insn ("bad address", addr);
2362 }
2363 else if (GET_CODE (base) == LO_SUM)
2364 {
2365 if (index != 0
2366 || GET_CODE (XEXP (base, 0)) != REG)
2367 abort ();
2368 if (small_data_operand (XEXP (base, 1), VOIDmode))
2369 fputs ("sda(", file);
2370 else
2371 fputs ("low(", file);
2372 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2373 fputs ("),", file);
2374 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2375 }
2376 else
2377 fatal_insn ("bad address", addr);
2378 break;
2379
2380 case LO_SUM :
2381 if (GET_CODE (XEXP (addr, 0)) != REG)
2382 fatal_insn ("lo_sum not of register", addr);
2383 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2384 fputs ("sda(", file);
2385 else
2386 fputs ("low(", file);
2387 output_addr_const (file, XEXP (addr, 1));
2388 fputs ("),", file);
2389 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2390 break;
2391
2392 case PRE_INC : /* Assume SImode. */
2393 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2394 break;
2395
2396 case PRE_DEC : /* Assume SImode. */
2397 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2398 break;
2399
2400 case POST_INC : /* Assume SImode. */
2401 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2402 break;
2403
2404 default :
2405 output_addr_const (file, addr);
2406 break;
2407 }
2408 }
2409
2410 /* Return true if the operands are the constants 0 and 1. */
2411
2412 int
2413 zero_and_one (rtx operand1, rtx operand2)
2414 {
2415 return
2416 GET_CODE (operand1) == CONST_INT
2417 && GET_CODE (operand2) == CONST_INT
2418 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2419 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2420 }
2421
2422 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2423
2424 int
2425 conditional_move_operand (rtx operand, enum machine_mode mode)
2426 {
2427 /* Only defined for simple integers so far... */
2428 if (mode != SImode && mode != HImode && mode != QImode)
2429 return FALSE;
2430
2431 /* At the moment we can handle moving registers and loading constants. */
2432 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2433
2434 switch (GET_CODE (operand))
2435 {
2436 case REG:
2437 return 1;
2438
2439 case CONST_INT:
2440 return INT8_P (INTVAL (operand));
2441
2442 default:
2443 #if 0
2444 fprintf (stderr, "Test for cond move op of type: %s\n",
2445 GET_RTX_NAME (GET_CODE (operand)));
2446 #endif
2447 return 0;
2448 }
2449 }
2450
2451 /* Return true if the code is a test of the carry bit. */
2452
2453 int
2454 carry_compare_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2455 {
2456 rtx x;
2457
2458 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2459 return FALSE;
2460
2461 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2462 return FALSE;
2463
2464 x = XEXP (op, 0);
2465 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2466 return FALSE;
2467
2468 x = XEXP (op, 1);
2469 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2470 return FALSE;
2471
2472 return TRUE;
2473 }
2474
2475 /* Generate the correct assembler code to handle the conditional loading of a
2476 value into a register. It is known that the operands satisfy the
2477 conditional_move_operand() function above. The destination is operand[0].
2478 The condition is operand [1]. The 'true' value is operand [2] and the
2479 'false' value is operand [3]. */
2480
2481 char *
2482 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2483 {
2484 static char buffer [100];
2485 const char * dest = reg_names [REGNO (operands [0])];
2486
2487 buffer [0] = 0;
2488
2489 /* Destination must be a register. */
2490 if (GET_CODE (operands [0]) != REG)
2491 abort();
2492 if (! conditional_move_operand (operands [2], SImode))
2493 abort();
2494 if (! conditional_move_operand (operands [3], SImode))
2495 abort();
2496
2497 /* Check to see if the test is reversed. */
2498 if (GET_CODE (operands [1]) == NE)
2499 {
2500 rtx tmp = operands [2];
2501 operands [2] = operands [3];
2502 operands [3] = tmp;
2503 }
2504
2505 sprintf (buffer, "mvfc %s, cbr", dest);
2506
2507 /* If the true value was '0' then we need to invert the results of the move. */
2508 if (INTVAL (operands [2]) == 0)
2509 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2510 dest, dest);
2511
2512 return buffer;
2513 }
2514
2515 /* Returns true if the registers contained in the two
2516 rtl expressions are different. */
2517
2518 int
2519 m32r_not_same_reg (rtx a, rtx b)
2520 {
2521 int reg_a = -1;
2522 int reg_b = -2;
2523
2524 while (GET_CODE (a) == SUBREG)
2525 a = SUBREG_REG (a);
2526
2527 if (GET_CODE (a) == REG)
2528 reg_a = REGNO (a);
2529
2530 while (GET_CODE (b) == SUBREG)
2531 b = SUBREG_REG (b);
2532
2533 if (GET_CODE (b) == REG)
2534 reg_b = REGNO (b);
2535
2536 return reg_a != reg_b;
2537 }
2538
2539 \f
2540 rtx
2541 m32r_function_symbol (const char *name)
2542 {
2543 int extra_flags = 0;
2544 enum m32r_model model;
2545 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2546
2547 if (TARGET_MODEL_SMALL)
2548 model = M32R_MODEL_SMALL;
2549 else if (TARGET_MODEL_MEDIUM)
2550 model = M32R_MODEL_MEDIUM;
2551 else if (TARGET_MODEL_LARGE)
2552 model = M32R_MODEL_LARGE;
2553 else
2554 abort (); /* Shouldn't happen. */
2555 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2556
2557 if (extra_flags)
2558 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2559
2560 return sym;
2561 }
2562
2563 /* Use a library function to move some bytes. */
2564
2565 static void
2566 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2567 {
2568 /* We want to pass the size as Pmode, which will normally be SImode
2569 but will be DImode if we are using 64 bit longs and pointers. */
2570 if (GET_MODE (bytes_rtx) != VOIDmode
2571 && GET_MODE (bytes_rtx) != Pmode)
2572 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2573
2574 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2575 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2576 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2577 TYPE_UNSIGNED (sizetype)),
2578 TYPE_MODE (sizetype));
2579 }
2580
2581 /* The maximum number of bytes to copy using pairs of load/store instructions.
2582 If a block is larger than this then a loop will be generated to copy
2583 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
2584 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2585 string copy in it. */
2586 #define MAX_MOVE_BYTES 32
2587
2588 /* Expand string/block move operations.
2589
2590 operands[0] is the pointer to the destination.
2591 operands[1] is the pointer to the source.
2592 operands[2] is the number of bytes to move.
2593 operands[3] is the alignment. */
2594
2595 void
2596 m32r_expand_block_move (rtx operands[])
2597 {
2598 rtx orig_dst = operands[0];
2599 rtx orig_src = operands[1];
2600 rtx bytes_rtx = operands[2];
2601 rtx align_rtx = operands[3];
2602 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2603 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2604 int align = INTVAL (align_rtx);
2605 int leftover;
2606 rtx src_reg;
2607 rtx dst_reg;
2608
2609 if (constp && bytes <= 0)
2610 return;
2611
2612 /* Move the address into scratch registers. */
2613 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2614 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2615
2616 if (align > UNITS_PER_WORD)
2617 align = UNITS_PER_WORD;
2618
2619 /* If we prefer size over speed, always use a function call.
2620 If we do not know the size, use a function call.
2621 If the blocks are not word aligned, use a function call. */
2622 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2623 {
2624 block_move_call (dst_reg, src_reg, bytes_rtx);
2625 return;
2626 }
2627
2628 leftover = bytes % MAX_MOVE_BYTES;
2629 bytes -= leftover;
2630
2631 /* If necessary, generate a loop to handle the bulk of the copy. */
2632 if (bytes)
2633 {
2634 rtx label = NULL_RTX;
2635 rtx final_src = NULL_RTX;
2636 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2637 rtx rounded_total = GEN_INT (bytes);
2638 rtx new_dst_reg = gen_reg_rtx (SImode);
2639 rtx new_src_reg = gen_reg_rtx (SImode);
2640
2641 /* If we are going to have to perform this loop more than
2642 once, then generate a label and compute the address the
2643 source register will contain upon completion of the final
2644 iteration. */
2645 if (bytes > MAX_MOVE_BYTES)
2646 {
2647 final_src = gen_reg_rtx (Pmode);
2648
2649 if (INT16_P(bytes))
2650 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2651 else
2652 {
2653 emit_insn (gen_movsi (final_src, rounded_total));
2654 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2655 }
2656
2657 label = gen_label_rtx ();
2658 emit_label (label);
2659 }
2660
2661 /* It is known that output_block_move() will update src_reg to point
2662 to the word after the end of the source block, and dst_reg to point
2663 to the last word of the destination block, provided that the block
2664 is MAX_MOVE_BYTES long. */
2665 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2666 new_dst_reg, new_src_reg));
2667 emit_move_insn (dst_reg, new_dst_reg);
2668 emit_move_insn (src_reg, new_src_reg);
2669 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2670
2671 if (bytes > MAX_MOVE_BYTES)
2672 {
2673 emit_insn (gen_cmpsi (src_reg, final_src));
2674 emit_jump_insn (gen_bne (label));
2675 }
2676 }
2677
2678 if (leftover)
2679 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2680 gen_reg_rtx (SImode),
2681 gen_reg_rtx (SImode)));
2682 }
2683
2684 \f
2685 /* Emit load/stores for a small constant word aligned block_move.
2686
2687 operands[0] is the memory address of the destination.
2688 operands[1] is the memory address of the source.
2689 operands[2] is the number of bytes to move.
2690 operands[3] is a temp register.
2691 operands[4] is a temp register. */
2692
2693 void
2694 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2695 {
2696 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2697 int first_time;
2698 int got_extra = 0;
2699
2700 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2701 abort ();
2702
2703 /* We do not have a post-increment store available, so the first set of
2704 stores are done without any increment, then the remaining ones can use
2705 the pre-increment addressing mode.
2706
2707 Note: expand_block_move() also relies upon this behavior when building
2708 loops to copy large blocks. */
2709 first_time = 1;
2710
2711 while (bytes > 0)
2712 {
2713 if (bytes >= 8)
2714 {
2715 if (first_time)
2716 {
2717 output_asm_insn ("ld\t%5, %p1", operands);
2718 output_asm_insn ("ld\t%6, %p1", operands);
2719 output_asm_insn ("st\t%5, @%0", operands);
2720 output_asm_insn ("st\t%6, %s0", operands);
2721 }
2722 else
2723 {
2724 output_asm_insn ("ld\t%5, %p1", operands);
2725 output_asm_insn ("ld\t%6, %p1", operands);
2726 output_asm_insn ("st\t%5, %s0", operands);
2727 output_asm_insn ("st\t%6, %s0", operands);
2728 }
2729
2730 bytes -= 8;
2731 }
2732 else if (bytes >= 4)
2733 {
2734 if (bytes > 4)
2735 got_extra = 1;
2736
2737 output_asm_insn ("ld\t%5, %p1", operands);
2738
2739 if (got_extra)
2740 output_asm_insn ("ld\t%6, %p1", operands);
2741
2742 if (first_time)
2743 output_asm_insn ("st\t%5, @%0", operands);
2744 else
2745 output_asm_insn ("st\t%5, %s0", operands);
2746
2747 bytes -= 4;
2748 }
2749 else
2750 {
2751 /* Get the entire next word, even though we do not want all of it.
2752 The saves us from doing several smaller loads, and we assume that
2753 we cannot cause a page fault when at least part of the word is in
2754 valid memory [since we don't get called if things aren't properly
2755 aligned]. */
2756 int dst_offset = first_time ? 0 : 4;
2757 /* The amount of increment we have to make to the
2758 destination pointer. */
2759 int dst_inc_amount = dst_offset + bytes - 4;
2760 /* The same for the source pointer. */
2761 int src_inc_amount = bytes;
2762 int last_shift;
2763 rtx my_operands[3];
2764
2765 /* If got_extra is true then we have already loaded
2766 the next word as part of loading and storing the previous word. */
2767 if (! got_extra)
2768 output_asm_insn ("ld\t%6, @%1", operands);
2769
2770 if (bytes >= 2)
2771 {
2772 bytes -= 2;
2773
2774 output_asm_insn ("sra3\t%5, %6, #16", operands);
2775 my_operands[0] = operands[5];
2776 my_operands[1] = GEN_INT (dst_offset);
2777 my_operands[2] = operands[0];
2778 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2779
2780 /* If there is a byte left to store then increment the
2781 destination address and shift the contents of the source
2782 register down by 8 bits. We could not do the address
2783 increment in the store half word instruction, because it does
2784 not have an auto increment mode. */
2785 if (bytes > 0) /* assert (bytes == 1) */
2786 {
2787 dst_offset += 2;
2788 last_shift = 8;
2789 }
2790 }
2791 else
2792 last_shift = 24;
2793
2794 if (bytes > 0)
2795 {
2796 my_operands[0] = operands[6];
2797 my_operands[1] = GEN_INT (last_shift);
2798 output_asm_insn ("srai\t%0, #%1", my_operands);
2799 my_operands[0] = operands[6];
2800 my_operands[1] = GEN_INT (dst_offset);
2801 my_operands[2] = operands[0];
2802 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2803 }
2804
2805 /* Update the destination pointer if needed. We have to do
2806 this so that the patterns matches what we output in this
2807 function. */
2808 if (dst_inc_amount
2809 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2810 {
2811 my_operands[0] = operands[0];
2812 my_operands[1] = GEN_INT (dst_inc_amount);
2813 output_asm_insn ("addi\t%0, #%1", my_operands);
2814 }
2815
2816 /* Update the source pointer if needed. We have to do this
2817 so that the patterns matches what we output in this
2818 function. */
2819 if (src_inc_amount
2820 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2821 {
2822 my_operands[0] = operands[1];
2823 my_operands[1] = GEN_INT (src_inc_amount);
2824 output_asm_insn ("addi\t%0, #%1", my_operands);
2825 }
2826
2827 bytes = 0;
2828 }
2829
2830 first_time = 0;
2831 }
2832 }
2833
2834 /* Return true if op is an integer constant, less than or equal to
2835 MAX_MOVE_BYTES. */
2836
2837 int
2838 m32r_block_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2839 {
2840 if (GET_CODE (op) != CONST_INT
2841 || INTVAL (op) > MAX_MOVE_BYTES
2842 || INTVAL (op) <= 0)
2843 return 0;
2844
2845 return 1;
2846 }
2847
2848 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2849
2850 int
2851 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2852 unsigned int new_reg)
2853 {
2854 /* Interrupt routines can't clobber any register that isn't already used. */
2855 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2856 && !regs_ever_live[new_reg])
2857 return 0;
2858
2859 /* We currently emit epilogues as text, not rtl, so the liveness
2860 of the return address register isn't visible. */
2861 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2862 return 0;
2863
2864 return 1;
2865 }
2866
2867 rtx
2868 m32r_return_addr (int count)
2869 {
2870 if (count != 0)
2871 return const0_rtx;
2872
2873 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2874 }
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