gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 /* Driver configuration.  */
  23
  24 #undef  SWITCH_TAKES_ARG
  25 #define SWITCH_TAKES_ARG(CHAR)                                          \
  26   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
  27
  28 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
  29 #undef  LIB_SPEC
  30 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  31
  32 #undef STARTFILE_SPEC
  33 #undef ENDFILE_SPEC
  34
  35 \f
  36 /* Run-time target specifications.  */
  37
  38 #define TARGET_CPU_CPP_BUILTINS()               \
  39   do                                            \
  40     {                                           \
  41       builtin_define ("__iq2000__");            \
  42       builtin_assert ("cpu=iq2000");            \
  43       builtin_assert ("machine=iq2000");        \
  44     }                                           \
  45   while (0)
  46
  47 extern int      target_flags;
  48
  49 #define MASK_GPOPT         0x00000008   /* Optimize for global pointer.  */
  50 #define MASK_EMBEDDED_DATA 0x00008000   /* Reduce RAM usage, not fast code.  */
  51 #define MASK_UNINIT_CONST_IN_RODATA \
  52                            0x00800000   /* Store uninitialized
  53                                            consts in rodata.  */
  54
  55 /* Macros used in the machine description to test the flags.  */
  56
  57 #define TARGET_STATS            0
  58
  59 /* For embedded systems, optimize for reduced RAM space instead of for
  60    fastest code.  */
  61 #define TARGET_EMBEDDED_DATA    (target_flags & MASK_EMBEDDED_DATA)
  62
  63 #define TARGET_DEBUG_MODE       (target_flags & 0)
  64 #define TARGET_DEBUG_A_MODE     (target_flags & 0)
  65 #define TARGET_DEBUG_B_MODE     (target_flags & 0)
  66 #define TARGET_DEBUG_C_MODE     (target_flags & 0)
  67 #define TARGET_DEBUG_D_MODE     (target_flags & 0)
  68
  69 #define TARGET_SWITCHES                                                 \
  70 {                                                                       \
  71   {"no-crt0",          0,                                               \
  72      N_("No default crt0.o") },                                         \
  73   {"gpopt",               MASK_GPOPT,                                   \
  74      N_("Use GP relative sdata/sbss sections")},                        \
  75   {"no-gpopt",           -MASK_GPOPT,                                   \
  76      N_("Don't use GP relative sdata/sbss sections")},                  \
  77   {"embedded-data",       MASK_EMBEDDED_DATA,                           \
  78      N_("Use ROM instead of RAM")},                                     \
  79   {"no-embedded-data",   -MASK_EMBEDDED_DATA,                           \
  80      N_("Don't use ROM instead of RAM")},                               \
  81   {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,               \
  82      N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
  83   {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,           \
  84      N_("Don't put uninitialized constants in ROM")},                   \
  85   {"",                    (TARGET_DEFAULT                               \
  86                            | TARGET_CPU_DEFAULT),                       \
  87      NULL},                                                             \
  88 }
  89
  90 /* Default target_flags if no switches are specified.  */
  91
  92 #define TARGET_DEFAULT 0
  93
  94 #ifndef TARGET_CPU_DEFAULT
  95 #define TARGET_CPU_DEFAULT 0
  96 #endif
  97
  98 #ifndef IQ2000_ISA_DEFAULT
  99 #define IQ2000_ISA_DEFAULT 1
 100 #endif
 101
 102 #define TARGET_OPTIONS                                                  \
 103 {                                                                       \
 104   SUBTARGET_TARGET_OPTIONS                                              \
 105   { "cpu=",     & iq2000_cpu_string,                                    \
 106       N_("Specify CPU for scheduling purposes")},                       \
 107   { "arch=",    & iq2000_arch_string,                                   \
 108       N_("Specify CPU for code generation purposes")},                  \
 109 }
 110
 111 /* This is meant to be redefined in the host dependent files.  */
 112 #define SUBTARGET_TARGET_OPTIONS
 113
 114 #define IQ2000_VERSION "[1.0]"
 115
 116 #ifndef MACHINE_TYPE
 117 #define MACHINE_TYPE "IQ2000"
 118 #endif
 119
 120 #ifndef TARGET_VERSION_INTERNAL
 121 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
 122   fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
 123 #endif
 124
 125 #ifndef TARGET_VERSION
 126 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
 127 #endif
 128
 129 #define OVERRIDE_OPTIONS override_options ()
 130
 131 #define CAN_DEBUG_WITHOUT_FP
 132 \f
 133 /* Storage Layout.  */
 134
 135 #define BITS_BIG_ENDIAN                 0
 136 #define BYTES_BIG_ENDIAN                1
 137 #define WORDS_BIG_ENDIAN                1
 138 #define LIBGCC2_WORDS_BIG_ENDIAN        1
 139 #define BITS_PER_WORD                   32
 140 #define MAX_BITS_PER_WORD               64
 141 #define UNITS_PER_WORD                  4
 142 #define MIN_UNITS_PER_WORD              4
 143 #define POINTER_SIZE                    32
 144
 145 /* Define this macro if it is advisable to hold scalars in registers
 146    in a wider mode than that declared by the program.  In such cases,
 147    the value is constrained to be within the bounds of the declared
 148    type, but kept valid in the wider mode.  The signedness of the
 149    extension may differ from that of the type.
 150
 151    We promote any value smaller than SImode up to SImode.  */
 152
 153 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 154   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 155       && GET_MODE_SIZE (MODE) < 4)              \
 156     (MODE) = SImode;
 157
 158 #define PARM_BOUNDARY 32
 159
 160 #define STACK_BOUNDARY 64
 161
 162 #define FUNCTION_BOUNDARY 32
 163
 164 #define BIGGEST_ALIGNMENT 64
 165
 166 #undef  DATA_ALIGNMENT
 167 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 168   ((((ALIGN) < BITS_PER_WORD)                                           \
 169     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 170         || TREE_CODE (TYPE) == UNION_TYPE                               \
 171         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 172
 173 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 174   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 175    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 176
 177 #define EMPTY_FIELD_BOUNDARY 32
 178
 179 #define STRUCTURE_SIZE_BOUNDARY 8
 180
 181 #define STRICT_ALIGNMENT 1
 182
 183 #define PCC_BITFIELD_TYPE_MATTERS 1
 184
 185 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
 186
 187 \f
 188 /* Layout of Source Language Data Types.  */
 189
 190 #define INT_TYPE_SIZE           32
 191 #define SHORT_TYPE_SIZE         16
 192 #define LONG_TYPE_SIZE          32
 193 #define LONG_LONG_TYPE_SIZE     64
 194 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 195 #define FLOAT_TYPE_SIZE         32
 196 #define DOUBLE_TYPE_SIZE        64
 197 #define LONG_DOUBLE_TYPE_SIZE   64
 198 #define DEFAULT_SIGNED_CHAR     1
 199
 200 \f
 201 /* Register Basics.  */
 202
 203 /* On the IQ2000, we have 32 integer registers.  */
 204 #define FIRST_PSEUDO_REGISTER 33
 205
 206 #define FIXED_REGISTERS                                                 \
 207 {                                                                       \
 208   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 209   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 210 }
 211
 212 #define CALL_USED_REGISTERS                                             \
 213 {                                                                       \
 214   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 215   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 216 }
 217
 218 \f
 219 /* Order of allocation of registers.  */
 220
 221 #define REG_ALLOC_ORDER                                                 \
 222 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 223   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 224 }
 225
 226 \f
 227 /* How Values Fit in Registers.  */
 228
 229 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 230   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 231
 232 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 233  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 234   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 235   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 236
 237 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 238   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 239     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 240    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 241        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 242
 243 #define AVOID_CCMODE_COPIES
 244
 245 \f
 246 /* Register Classes.  */
 247
 248 enum reg_class
 249 {
 250   NO_REGS,                      /* No registers in set.  */
 251   GR_REGS,                      /* Integer registers.  */
 252   ALL_REGS,                     /* All registers.  */
 253   LIM_REG_CLASSES               /* Max value + 1.  */
 254 };
 255
 256 #define GENERAL_REGS GR_REGS
 257
 258 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 259
 260 #define REG_CLASS_NAMES                                         \
 261 {                                                               \
 262   "NO_REGS",                                                    \
 263   "GR_REGS",                                                    \
 264   "ALL_REGS"                                                    \
 265 }
 266
 267 #define REG_CLASS_CONTENTS                                      \
 268 {                                                               \
 269   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 270   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 271   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 272 }
 273
 274 #define REGNO_REG_CLASS(REGNO) \
 275 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 276
 277 #define BASE_REG_CLASS  (GR_REGS)
 278
 279 #define INDEX_REG_CLASS NO_REGS
 280
 281 #define REG_CLASS_FROM_LETTER(C) \
 282   ((C) == 'd' ? GR_REGS :        \
 283    (C) == 'b' ? ALL_REGS :       \
 284    (C) == 'y' ? GR_REGS :        \
 285    NO_REGS)
 286
 287 #define REGNO_OK_FOR_INDEX_P(regno)     0
 288
 289 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 290   ((CLASS) != ALL_REGS                                          \
 291    ? (CLASS)                                                    \
 292    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 293        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 294       ? (GR_REGS)                                               \
 295       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 296           || GET_MODE (X) == VOIDmode)                          \
 297          ? (GR_REGS)                                            \
 298          : (CLASS))))
 299
 300 #define SMALL_REGISTER_CLASSES 0
 301
 302 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 303   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 304
 305 /* For IQ2000:
 306
 307    `I'  is used for the range of constants an arithmetic insn can
 308         actually contain (16 bits signed integers).
 309
 310    `J'  is used for the range which is just zero (ie, $r0).
 311
 312    `K'  is used for the range of constants a logical insn can actually
 313         contain (16 bit zero-extended integers).
 314
 315    `L'  is used for the range of constants that be loaded with lui
 316         (ie, the bottom 16 bits are zero).
 317
 318    `M'  is used for the range of constants that take two words to load
 319         (ie, not matched by `I', `K', and `L').
 320
 321    `N'  is used for constants 0xffffnnnn or 0xnnnnffff
 322
 323    `O'  is a 5 bit zero-extended integer.  */
 324
 325 #define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
 326   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
 327    : (C) == 'J' ? ((VALUE) == 0)                                        \
 328    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
 329    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                          \
 330                    && (((VALUE) & ~2147483647) == 0                     \
 331                        || ((VALUE) & ~2147483647) == ~2147483647))      \
 332    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                       \
 333                    && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
 334                    && (((VALUE) & 0x0000ffff) != 0                      \
 335                        || (((VALUE) & ~2147483647) != 0                 \
 336                            && ((VALUE) & ~2147483647) != ~2147483647))) \
 337    : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
 338                    || (((VALUE) & 0xffff0000) == 0xffff0000))           \
 339    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
 340    : 0)
 341
 342 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
 343   ((C) == 'G'                                                           \
 344    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
 345
 346 /* `R' is for memory references which take 1 word for the instruction.  */
 347
 348 #define EXTRA_CONSTRAINT(OP,CODE)                                       \
 349   (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
 350    : FALSE)
 351
 352 \f
 353 /* Basic Stack Layout.  */
 354
 355 #define STACK_GROWS_DOWNWARD
 356
 357 /* #define FRAME_GROWS_DOWNWARD */
 358
 359 #define STARTING_FRAME_OFFSET                                           \
 360   (current_function_outgoing_args_size)
 361
 362 /* Use the default value zero.  */
 363 /* #define STACK_POINTER_OFFSET 0 */
 364
 365 #define FIRST_PARM_OFFSET(FNDECL) 0
 366
 367 /* The return address for the current frame is in r31 if this is a leaf
 368    function.  Otherwise, it is on the stack.  It is at a variable offset
 369    from sp/fp/ap, so we define a fake hard register rap which is a
 370    pointer to the return address on the stack.  This always gets eliminated
 371    during reload to be either the frame pointer or the stack pointer plus
 372    an offset.  */
 373
 374 #define RETURN_ADDR_RTX(count, frame)                                   \
 375   (((count) == 0)                                                       \
 376    ? (leaf_function_p ()                                                \
 377       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 378       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 379                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 380     : (rtx) 0)
 381
 382 /* Before the prologue, RA lives in r31.  */
 383 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 384
 385 \f
 386 /* Register That Address the Stack Frame.  */
 387
 388 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 389 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 390 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 391 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 392 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 393 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 394
 395 \f
 396 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 397
 398 #define FRAME_POINTER_REQUIRED 0
 399
 400 #define ELIMINABLE_REGS                                                 \
 401 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 402  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 403  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 404  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 405  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 406  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 407  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 408
 409
 410 /* We can always eliminate to the frame pointer.  We can eliminate to the
 411    stack pointer unless a frame pointer is needed.  */
 412
 413 #define CAN_ELIMINATE(FROM, TO)                                         \
 414   (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()    \
 415    || (TO == GP_REG_FIRST + 31 && leaf_function_p)))                    \
 416   || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM                           \
 417    && ((TO) == HARD_FRAME_POINTER_REGNUM                                \
 418    || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
 419
 420 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 421         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 422 \f
 423 /* Passing Function Arguments on the Stack.  */
 424
 425 /* #define PUSH_ROUNDING(BYTES) 0 */
 426
 427 #define ACCUMULATE_OUTGOING_ARGS 1
 428
 429 #define REG_PARM_STACK_SPACE(FNDECL) 0
 430
 431 #define OUTGOING_REG_PARM_STACK_SPACE
 432
 433 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 434
 435 \f
 436 /* Function Arguments in Registers.  */
 437
 438 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 439   function_arg (& CUM, MODE, TYPE, NAMED)
 440
 441 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
 442   function_arg_partial_nregs (& CUM, MODE, TYPE, NAMED)
 443
 444 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) (NAMED)
 445
 446 #define MAX_ARGS_IN_REGISTERS 8
 447
 448 typedef struct iq2000_args
 449 {
 450   int gp_reg_found;             /* Whether a gp register was found yet.  */
 451   unsigned int arg_number;      /* Argument number.  */
 452   unsigned int arg_words;       /* # total words the arguments take.  */
 453   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 454   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 455   int fp_code;                  /* Mode of FP arguments.  */
 456   unsigned int num_adjusts;     /* Number of adjustments made.  */
 457                                 /* Adjustments made to args pass in regs.  */
 458   struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
 459 } CUMULATIVE_ARGS;
 460
 461 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 462    for a call to a function whose data type is FNTYPE.
 463    For a library call, FNTYPE is 0.  */
 464 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 465   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 466
 467 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
 468   function_arg_advance (& CUM, MODE, TYPE, NAMED)
 469
 470 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 471   (! BYTES_BIG_ENDIAN                                                   \
 472    ? upward                                                             \
 473    : (((MODE) == BLKmode                                                \
 474        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 475           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 476        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 477           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 478       ? downward : upward))
 479
 480 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE)                               \
 481   (((TYPE) != 0)                                                        \
 482         ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)                          \
 483                 ? PARM_BOUNDARY                                         \
 484                 : TYPE_ALIGN(TYPE))                                     \
 485         : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)                  \
 486                 ? PARM_BOUNDARY                                         \
 487                 : GET_MODE_ALIGNMENT(MODE)))
 488
 489 #define FUNCTION_ARG_REGNO_P(N)                                         \
 490   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 491
 492 \f
 493 /* How Scalar Function Values are Returned.  */
 494
 495 #define FUNCTION_VALUE(VALTYPE, FUNC)   iq2000_function_value (VALTYPE, FUNC)
 496
 497 #define LIBCALL_VALUE(MODE)                             \
 498   gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT      \
 499                  || GET_MODE_SIZE (MODE) >= 4)          \
 500                 ? (MODE)                                \
 501                 : SImode),                              \
 502                GP_RETURN)
 503
 504 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 505
 506 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
 507
 508 \f
 509 /* How Large Values are Returned.  */
 510
 511 #define DEFAULT_PCC_STRUCT_RETURN 0
 512 \f
 513 /* Function Entry and Exit.  */
 514
 515 #define EXIT_IGNORE_STACK 1
 516
 517 \f
 518 /* Generating Code for Profiling.  */
 519
 520 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 521 {                                                                       \
 522   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 523   fprintf (FILE, "\t.set\tnoat\n");                                     \
 524   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 525            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 526   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 527   fprintf (FILE,                                                        \
 528            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 529            "subu",                                                      \
 530            reg_names[STACK_POINTER_REGNUM],                             \
 531            reg_names[STACK_POINTER_REGNUM],                             \
 532            Pmode == DImode ? 16 : 8);                                   \
 533   fprintf (FILE, "\t.set\treorder\n");                                  \
 534   fprintf (FILE, "\t.set\tat\n");                                       \
 535 }
 536
 537 \f
 538 /* Implementing the Varargs Macros.  */
 539
 540 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
 541   iq2000_va_start (valist, nextarg)
 542
 543 \f
 544 /* Trampolines for Nested Functions.  */
 545
 546 /* A C statement to output, on the stream FILE, assembler code for a
 547    block of data that contains the constant parts of a trampoline.
 548    This code should not include a label--the label is taken care of
 549    automatically.  */
 550
 551 #define TRAMPOLINE_TEMPLATE(STREAM)                                      \
 552 {                                                                        \
 553   fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");         \
 554   fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");         \
 555   fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");                   \
 556   if (Pmode == DImode)                                                  \
 557     {                                                                   \
 558       fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n"); \
 559       fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n"); \
 560     }                                                                   \
 561   else                                                                  \
 562     {                                                                   \
 563       fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n"); \
 564       fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n"); \
 565     }                                                                   \
 566   fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
 567   fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");             \
 568   fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");         \
 569   fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
 570   fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
 571 }
 572
 573 #define TRAMPOLINE_SIZE (40)
 574
 575 #define TRAMPOLINE_ALIGNMENT 32
 576
 577 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)                            \
 578 {                                                                           \
 579   rtx addr = ADDR;                                                          \
 580     emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
 581     emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
 582 }
 583
 584 \f
 585 /* Addressing Modes.  */
 586
 587 #define CONSTANT_ADDRESS_P(X)                                           \
 588   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 589     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 590     || (GET_CODE (X) == CONST)))
 591
 592 #define MAX_REGS_PER_ADDRESS 1
 593
 594 #ifdef REG_OK_STRICT
 595 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
 596   {                                                     \
 597     if (iq2000_legitimate_address_p (MODE, X, 1))       \
 598       goto ADDR;                                        \
 599   }
 600 #else
 601 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
 602   {                                                     \
 603     if (iq2000_legitimate_address_p (MODE, X, 0))       \
 604       goto ADDR;                                        \
 605   }
 606 #endif
 607
 608 #define REG_OK_FOR_INDEX_P(X) 0
 609
 610
 611 /* For the IQ2000, transform:
 612
 613         memory(X + <large int>)
 614    into:
 615         Y = <large int> & ~0x7fff;
 616         Z = X + Y
 617         memory (Z + (<large int> & 0x7fff));
 618 */
 619
 620 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                             \
 621 {                                                                       \
 622   rtx xinsn = (X);                                                      \
 623                                                                         \
 624   if (TARGET_DEBUG_B_MODE)                                              \
 625     {                                                                   \
 626       GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");                  \
 627       GO_DEBUG_RTX (xinsn);                                             \
 628     }                                                                   \
 629                                                                         \
 630   if (iq2000_check_split (X, MODE))             \
 631     {                                                                   \
 632       X = gen_rtx_LO_SUM (Pmode,                                        \
 633                           copy_to_mode_reg (Pmode,                      \
 634                                             gen_rtx_HIGH (Pmode, X)),   \
 635                           X);                                           \
 636       goto WIN;                                                         \
 637     }                                                                   \
 638                                                                         \
 639   if (GET_CODE (xinsn) == PLUS)                                         \
 640     {                                                                   \
 641       rtx xplus0 = XEXP (xinsn, 0);                                     \
 642       rtx xplus1 = XEXP (xinsn, 1);                                     \
 643       enum rtx_code code0 = GET_CODE (xplus0);                          \
 644       enum rtx_code code1 = GET_CODE (xplus1);                          \
 645                                                                         \
 646       if (code0 != REG && code1 == REG)                                 \
 647         {                                                               \
 648           xplus0 = XEXP (xinsn, 1);                                     \
 649           xplus1 = XEXP (xinsn, 0);                                     \
 650           code0 = GET_CODE (xplus0);                                    \
 651           code1 = GET_CODE (xplus1);                                    \
 652         }                                                               \
 653                                                                         \
 654       if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)         \
 655           && code1 == CONST_INT && !SMALL_INT (xplus1))                 \
 656         {                                                               \
 657           rtx int_reg = gen_reg_rtx (Pmode);                            \
 658           rtx ptr_reg = gen_reg_rtx (Pmode);                            \
 659                                                                         \
 660           emit_move_insn (int_reg,                                      \
 661                           GEN_INT (INTVAL (xplus1) & ~ 0x7fff));        \
 662                                                                         \
 663           emit_insn (gen_rtx_SET (VOIDmode,                             \
 664                                   ptr_reg,                              \
 665                                   gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
 666                                                                         \
 667           X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);        \
 668           goto WIN;                                                     \
 669         }                                                               \
 670     }                                                                   \
 671                                                                         \
 672   if (TARGET_DEBUG_B_MODE)                                              \
 673     GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");                  \
 674 }
 675
 676 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
 677
 678 #define LEGITIMATE_CONSTANT_P(X) (1)
 679
 680 \f
 681 /* Describing Relative Costs of Operations.  */
 682
 683 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 684
 685 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 686   (TO_P ? 2 : 16)
 687
 688 #define BRANCH_COST 2
 689
 690 #define SLOW_BYTE_ACCESS 1
 691
 692 #define NO_FUNCTION_CSE 1
 693
 694 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 695   if (REG_NOTE_KIND (LINK) != 0)                                        \
 696     (COST) = 0; /* Anti or output dependence.  */
 697
 698 \f
 699 /* Dividing the output into sections.  */
 700
 701 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 702
 703 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 704
 705 \f
 706 /* The Overall Framework of an Assembler File.  */
 707
 708 #define ASM_COMMENT_START " #"
 709
 710 #define ASM_APP_ON "#APP\n"
 711
 712 #define ASM_APP_OFF "#NO_APP\n"
 713
 714 \f
 715 /* Output and Generation of Labels.  */
 716
 717 #undef ASM_GENERATE_INTERNAL_LABEL
 718 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 719   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 720
 721 #define GLOBAL_ASM_OP "\t.globl\t"
 722
 723 \f
 724 /* Output of Assembler Instructions.  */
 725
 726 #define REGISTER_NAMES                                                  \
 727 {                                                                       \
 728  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 729  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 730  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 731  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 732 };
 733
 734 #define ADDITIONAL_REGISTER_NAMES                                       \
 735 {                                                                       \
 736   { "%0",        0 + GP_REG_FIRST },                                    \
 737   { "%1",        1 + GP_REG_FIRST },                                    \
 738   { "%2",        2 + GP_REG_FIRST },                                    \
 739   { "%3",        3 + GP_REG_FIRST },                                    \
 740   { "%4",        4 + GP_REG_FIRST },                                    \
 741   { "%5",        5 + GP_REG_FIRST },                                    \
 742   { "%6",        6 + GP_REG_FIRST },                                    \
 743   { "%7",        7 + GP_REG_FIRST },                                    \
 744   { "%8",        8 + GP_REG_FIRST },                                    \
 745   { "%9",        9 + GP_REG_FIRST },                                    \
 746   { "%10",      10 + GP_REG_FIRST },                                    \
 747   { "%11",      11 + GP_REG_FIRST },                                    \
 748   { "%12",      12 + GP_REG_FIRST },                                    \
 749   { "%13",      13 + GP_REG_FIRST },                                    \
 750   { "%14",      14 + GP_REG_FIRST },                                    \
 751   { "%15",      15 + GP_REG_FIRST },                                    \
 752   { "%16",      16 + GP_REG_FIRST },                                    \
 753   { "%17",      17 + GP_REG_FIRST },                                    \
 754   { "%18",      18 + GP_REG_FIRST },                                    \
 755   { "%19",      19 + GP_REG_FIRST },                                    \
 756   { "%20",      20 + GP_REG_FIRST },                                    \
 757   { "%21",      21 + GP_REG_FIRST },                                    \
 758   { "%22",      22 + GP_REG_FIRST },                                    \
 759   { "%23",      23 + GP_REG_FIRST },                                    \
 760   { "%24",      24 + GP_REG_FIRST },                                    \
 761   { "%25",      25 + GP_REG_FIRST },                                    \
 762   { "%26",      26 + GP_REG_FIRST },                                    \
 763   { "%27",      27 + GP_REG_FIRST },                                    \
 764   { "%28",      28 + GP_REG_FIRST },                                    \
 765   { "%29",      29 + GP_REG_FIRST },                                    \
 766   { "%30",      27 + GP_REG_FIRST },                                    \
 767   { "%31",      31 + GP_REG_FIRST },                                    \
 768   { "%rap",     32 + GP_REG_FIRST },                                    \
 769 }
 770
 771 /* Check if the current insn needs a nop in front of it
 772    because of load delays, and also update the delay slot statistics.  */
 773
 774 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 775   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 776
 777 /* See iq2000.c for the IQ2000 specific codes.  */
 778 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
 779
 780 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
 781
 782 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
 783
 784 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 785 do                                                                      \
 786   {                                                                     \
 787     fputs ("\n", STREAM);                                               \
 788   }                                                                     \
 789 while (0)
 790
 791 #define LOCAL_LABEL_PREFIX      "$"
 792
 793 #define USER_LABEL_PREFIX       ""
 794
 795 \f
 796 /* Output of dispatch tables.  */
 797
 798 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 799   do                                                                    \
 800     {                                                                   \
 801       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 802                Pmode == DImode ? ".dword" : ".word",                    \
 803                LOCAL_LABEL_PREFIX, VALUE);                              \
 804     }                                                                   \
 805   while (0)
 806
 807 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 808   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 809            Pmode == DImode ? ".dword" : ".word",                        \
 810            LOCAL_LABEL_PREFIX,                                          \
 811            VALUE)
 812
 813 \f
 814 /* Assembler Commands for Alignment.  */
 815
 816 #undef ASM_OUTPUT_SKIP
 817 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 818   fprintf (STREAM, "\t.space\t%u\n", (SIZE))
 819
 820 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 821   if ((LOG) != 0)                                                       \
 822     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 823
 824 \f
 825 /* Macros Affecting all Debug Formats.  */
 826
 827 #define DEBUGGER_AUTO_OFFSET(X)  \
 828   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 829
 830 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 831   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 832
 833 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 834
 835 #define DWARF2_DEBUGGING_INFO 1
 836
 837 \f
 838 /* Miscellaneous Parameters.  */
 839
 840 #define PREDICATE_CODES                                                 \
 841   {"uns_arith_operand",         { REG, CONST_INT, SUBREG }},            \
 842   {"arith_operand",             { REG, CONST_INT, SUBREG }},            \
 843   {"small_int",                 { CONST_INT }},                         \
 844   {"large_int",                 { CONST_INT }},                         \
 845   {"reg_or_0_operand",          { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
 846   {"simple_memory_operand",     { MEM, SUBREG }},                       \
 847   {"equality_op",               { EQ, NE }},                            \
 848   {"cmp_op",                    { EQ, NE, GT, GE, GTU, GEU, LT, LE,     \
 849                                   LTU, LEU }},                          \
 850   {"pc_or_label_operand",       { PC, LABEL_REF }},                     \
 851   {"call_insn_operand",         { CONST_INT, CONST, SYMBOL_REF, REG}},  \
 852   {"move_operand",              { CONST_INT, CONST_DOUBLE, CONST,       \
 853                                   SYMBOL_REF, LABEL_REF, SUBREG,        \
 854                                   REG, MEM}},                           \
 855   {"power_of_2_operand",        { CONST_INT }},
 856
 857 #define CASE_VECTOR_MODE SImode
 858
 859 #define WORD_REGISTER_OPERATIONS
 860
 861 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 862
 863 #define MOVE_MAX 4
 864
 865 #define MAX_MOVE_MAX 8
 866
 867 #define SHIFT_COUNT_TRUNCATED 1
 868
 869 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 870
 871 #define STORE_FLAG_VALUE 1
 872
 873 #define Pmode SImode
 874
 875 #define FUNCTION_MODE SImode
 876
 877 /* Standard GCC variables that we reference.  */
 878
 879 extern char     call_used_regs[];
 880
 881 /* IQ2000 external variables defined in iq2000.c.  */
 882
 883 /* Comparison type.  */
 884 enum cmp_type
 885 {
 886   CMP_SI,                               /* Compare four byte integers.  */
 887   CMP_DI,                               /* Compare eight byte integers.  */
 888   CMP_SF,                               /* Compare single precision floats.  */
 889   CMP_DF,                               /* Compare double precision floats.  */
 890   CMP_MAX                               /* Max comparison type.  */
 891 };
 892
 893 /* Types of delay slot.  */
 894 enum delay_type
 895 {
 896   DELAY_NONE,                           /* No delay slot.  */
 897   DELAY_LOAD,                           /* Load from memory delay.  */
 898   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 899 };
 900
 901 /* Which processor to schedule for.  */
 902
 903 enum processor_type
 904 {
 905   PROCESSOR_DEFAULT,
 906   PROCESSOR_IQ2000,
 907   PROCESSOR_IQ10
 908 };
 909
 910 /* Recast the cpu class to be the cpu attribute.  */
 911 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 912
 913 /* Functions to change what output section we are using.  */
 914 extern void             rdata_section (void);
 915 extern void             sdata_section (void);
 916 extern void             sbss_section  (void);
 917
 918 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 919 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 920
 921 \f
 922 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 923
 924 /* Macros to decide whether certain features are available or not,
 925    depending on the instruction set architecture level.  */
 926
 927 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 928
 929 /* ISA has branch likely instructions.  */
 930 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 931
 932 \f
 933 #undef ASM_SPEC
 934 #define ASM_SPEC "%{march=iq2000: -m2000} %{march=iq10: -m10} %{!march=*: -m2000}"
 935
 936 \f
 937 /* The mapping from gcc register number to DWARF 2 CFA column number.
 938    This mapping does not allow for tracking register 0, since
 939    register 0 is fixed.  */
 940 #define DWARF_FRAME_REGNUM(REG)                         \
 941   (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
 942
 943 /* The DWARF 2 CFA column which tracks the return address.  */
 944 #define DWARF_FRAME_RETURN_COLUMN ( GP_REG_FIRST + 26)
 945
 946 /* Describe how we implement __builtin_eh_return.  */
 947 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 948
 949 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 950    location used to store the amount to adjust the stack.  This is
 951    usually a register that is available from end of the function's body
 952    to the end of the epilogue. Thus, this cannot be a register used as a
 953    temporary by the epilogue.
 954
 955    This must be an integer register.  */
 956 #define EH_RETURN_STACKADJ_REGNO        3
 957 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 958
 959 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 960    location used to store the address the processor should jump to
 961    catch exception.  This is usually a registers that is available from
 962    end of the function's body to the end of the epilogue. Thus, this
 963    cannot be a register used as a temporary by the epilogue.
 964
 965    This must be an address register.  */
 966 #define EH_RETURN_HANDLER_REGNO         26
 967 #define EH_RETURN_HANDLER_RTX           \
 968         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 969
 970 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 971 #define DWARF_CIE_DATA_ALIGNMENT 4
 972
 973 /* For IQ2000, width of a floating point register.  */
 974 #define UNITS_PER_FPREG 4
 975
 976 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 977
 978 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 979
 980 /* Internal macros to classify a register number as to whether it's a
 981    general purpose register, a floating point register, a
 982    multiply/divide register, or a status register.  */
 983
 984 #define GP_REG_FIRST 0
 985 #define GP_REG_LAST  31
 986 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 987
 988 #define RAP_REG_NUM   32
 989 #define AT_REGNUM       (GP_REG_FIRST + 1)
 990
 991 #define GP_REG_P(REGNO) \
 992   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 993
 994 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 995    is larger than 32K bytes.  These registers must come from the
 996    scratch register set, and not used for passing and returning
 997    arguments and any other information used in the calling sequence.  */
 998
 999 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
1000 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
1001
1002 /* This macro is used later on in the file.  */
1003 #define GR_REG_CLASS_P(CLASS)                                           \
1004   ((CLASS) == GR_REGS)
1005
1006 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1007 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1008
1009 /* Certain machines have the property that some registers cannot be
1010    copied to some other registers without using memory.  Define this
1011    macro on those machines to be a C expression that is nonzero if
1012    objects of mode MODE in registers of CLASS1 can only be copied to
1013    registers of class CLASS2 by storing a register of CLASS1 into
1014    memory and loading that memory location into a register of CLASS2.
1015
1016    Do not define this macro if its value would always be zero.  */
1017
1018 /* Return the maximum number of consecutive registers
1019    needed to represent mode MODE in a register of class CLASS.  */
1020
1021 #define CLASS_UNITS(mode, size)                                         \
1022   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1023
1024 /* If defined, gives a class of registers that cannot be used as the
1025    operand of a SUBREG that changes the mode of the object illegally.  */
1026
1027 #define CLASS_CANNOT_CHANGE_MODE 0
1028
1029 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
1030
1031 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1032   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1033
1034 /* Make sure 4 words are always allocated on the stack.  */
1035
1036 #ifndef STACK_ARGS_ADJUST
1037 #define STACK_ARGS_ADJUST(SIZE)                                         \
1038   {                                                                     \
1039     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
1040       SIZE.constant = 4 * UNITS_PER_WORD;                               \
1041   }
1042 #endif
1043
1044 \f
1045 /* Symbolic macros for the registers used to return integer and floating
1046    point values.  */
1047
1048 #define GP_RETURN (GP_REG_FIRST + 2)
1049
1050 /* Symbolic macros for the first/last argument registers.  */
1051
1052 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1053 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
1054
1055 #define MAX_ARGS_IN_REGISTERS   8
1056
1057 \f
1058 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
1059
1060 #define MUST_SAVE_REGISTER(regno) \
1061  ((regs_ever_live[regno] && !call_used_regs[regno])                     \
1062   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
1063   || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
1064
1065 /* ALIGN FRAMES on double word boundaries */
1066 #ifndef IQ2000_STACK_ALIGN
1067 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
1068 #endif
1069
1070 \f
1071 /* These assume that REGNO is a hard or pseudo reg number.
1072    They give nonzero only if REGNO is a hard reg of the suitable class
1073    or a pseudo reg currently allocated to a suitable hard reg.
1074    These definitions are NOT overridden anywhere.  */
1075
1076 #define BASE_REG_P(regno, mode)                                 \
1077   (GP_REG_P (regno))
1078
1079 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
1080   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
1081              (mode))
1082
1083 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
1084   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
1085
1086 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
1087   GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1088
1089 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1090    and check its validity for a certain class.
1091    We have two alternate definitions for each of them.
1092    The usual definition accepts all pseudo regs; the other rejects them all.
1093    The symbol REG_OK_STRICT causes the latter definition to be used.
1094
1095    Most source files want to accept pseudo regs in the hope that
1096    they will get allocated to the class that the insn wants them to be in.
1097    Some source files that are used after register allocation
1098    need to be strict.  */
1099
1100 #ifndef REG_OK_STRICT
1101 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1102   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1103 #else
1104 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1105   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1106 #endif
1107
1108 #if 1
1109 #define GO_PRINTF(x)    fprintf (stderr, (x))
1110 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
1111 #define GO_DEBUG_RTX(x) debug_rtx (x)
1112
1113 #else
1114 #define GO_PRINTF(x)
1115 #define GO_PRINTF2(x,y)
1116 #define GO_DEBUG_RTX(x)
1117 #endif
1118
1119 /* If defined, modifies the length assigned to instruction INSN as a
1120    function of the context in which it is used.  LENGTH is an lvalue
1121    that contains the initially computed length of the insn and should
1122    be updated with the correct length of the insn.  */
1123 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1124   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1125
1126 \f
1127 /* A list of predicates that do special things with modes, and so
1128    should not elicit warnings for VOIDmode match_operand.  */
1129
1130 #define SPECIAL_MODE_PREDICATES \
1131   "pc_or_label_operand",
1132
1133 \f
1134
1135
1136 /* How to tell the debugger about changes of source files.  */
1137
1138 #ifndef SET_FILE_NUMBER
1139 #define SET_FILE_NUMBER() ++ num_source_filenames
1140 #endif
1141
1142 /* This is how to output a note the debugger telling it the line number
1143    to which the following sequence of instructions corresponds.  */
1144
1145 #ifndef LABEL_AFTER_LOC
1146 #define LABEL_AFTER_LOC(STREAM)
1147 #endif
1148
1149 \f
1150 /* Default to -G 8 */
1151 #ifndef IQ2000_DEFAULT_GVALUE
1152 #define IQ2000_DEFAULT_GVALUE 8
1153 #endif
1154
1155 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
1156
1157 \f
1158 /* See iq2000_expand_prologue's use of loadgp for when this should be
1159    true.  */
1160
1161 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE 0
1162 \f
1163 /* List of all IQ2000 punctuation characters used by print_operand.  */
1164 extern char iq2000_print_operand_punct[256];
1165
1166 /* The target cpu for optimization and scheduling.  */
1167 extern enum processor_type iq2000_tune;
1168
1169 /* Which instruction set architecture to use.  */
1170 extern int iq2000_isa;
1171
1172 /* Cached operands, and operator to compare for use in set/branch/trap
1173    on condition codes.  */
1174 extern rtx branch_cmp[2];
1175
1176 /* What type of branch to use.  */
1177 extern enum cmp_type branch_type;
1178
1179 /* Strings to hold which cpu and instruction set architecture to use.  */
1180 extern const char * iq2000_cpu_string;    /* For -mcpu=<xxx>.  */
1181 extern const char * iq2000_arch_string;   /* For -march=<xxx>.  */
1182
1183
1184
1185 enum iq2000_builtins
1186 {
1187   IQ2000_BUILTIN_ADO16,
1188   IQ2000_BUILTIN_CFC0,
1189   IQ2000_BUILTIN_CFC1,
1190   IQ2000_BUILTIN_CFC2,
1191   IQ2000_BUILTIN_CFC3,
1192   IQ2000_BUILTIN_CHKHDR,
1193   IQ2000_BUILTIN_CTC0,
1194   IQ2000_BUILTIN_CTC1,
1195   IQ2000_BUILTIN_CTC2,
1196   IQ2000_BUILTIN_CTC3,
1197   IQ2000_BUILTIN_LU,
1198   IQ2000_BUILTIN_LUC32L,
1199   IQ2000_BUILTIN_LUC64,
1200   IQ2000_BUILTIN_LUC64L,
1201   IQ2000_BUILTIN_LUK,
1202   IQ2000_BUILTIN_LULCK,
1203   IQ2000_BUILTIN_LUM32,
1204   IQ2000_BUILTIN_LUM32L,
1205   IQ2000_BUILTIN_LUM64,
1206   IQ2000_BUILTIN_LUM64L,
1207   IQ2000_BUILTIN_LUR,
1208   IQ2000_BUILTIN_LURL,
1209   IQ2000_BUILTIN_MFC0,
1210   IQ2000_BUILTIN_MFC1,
1211   IQ2000_BUILTIN_MFC2,
1212   IQ2000_BUILTIN_MFC3,
1213   IQ2000_BUILTIN_MRGB,
1214   IQ2000_BUILTIN_MTC0,
1215   IQ2000_BUILTIN_MTC1,
1216   IQ2000_BUILTIN_MTC2,
1217   IQ2000_BUILTIN_MTC3,
1218   IQ2000_BUILTIN_PKRL,
1219   IQ2000_BUILTIN_RAM,
1220   IQ2000_BUILTIN_RB,
1221   IQ2000_BUILTIN_RX,
1222   IQ2000_BUILTIN_SRRD,
1223   IQ2000_BUILTIN_SRRDL,
1224   IQ2000_BUILTIN_SRULC,
1225   IQ2000_BUILTIN_SRULCK,
1226   IQ2000_BUILTIN_SRWR,
1227   IQ2000_BUILTIN_SRWRU,
1228   IQ2000_BUILTIN_TRAPQF,
1229   IQ2000_BUILTIN_TRAPQFL,
1230   IQ2000_BUILTIN_TRAPQN,
1231   IQ2000_BUILTIN_TRAPQNE,
1232   IQ2000_BUILTIN_TRAPRE,
1233   IQ2000_BUILTIN_TRAPREL,
1234   IQ2000_BUILTIN_WB,
1235   IQ2000_BUILTIN_WBR,
1236   IQ2000_BUILTIN_WBU,
1237   IQ2000_BUILTIN_WX,
1238   IQ2000_BUILTIN_SYSCALL
1239 };