| blob | 8ed7b78d72cd8586fb7a29b9045bbd3d5ee8a4e5 |
1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
53 #include <splay-tree.h>
57 /* Specify which cpu to schedule for. */
61 {
63 };
65 /* Specify how accurate floating-point traps need to be. */
69 /* Specify the floating-point rounding mode. */
73 /* Specify which things cause traps. */
77 /* Specify bit size of immediate TLS offsets. */
81 /* Strings decoded into the above options. */
91 /* Save information from a "cmpxx" operation until the branch or scc is
92 emitted. */
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
101 /* The number of cycles of latency we should assume on memory reads. */
105 /* Whether the function needs the GP. */
109 /* The alias set for prologue/epilogue register save/restore. */
113 /* The assembler name of the current function. */
117 /* The next explicit relocation sequence number. */
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
131 {
141 };
144 {
155 },
166 },
177 },
178 };
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
183 one of them. */
186 {
196 };
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
201 #else
202 #define NUM_ARGS current_function_args_info
203 #endif
205 #define REG_PV 27
206 #define REG_RA 26
208 /* Declarations of static functions. */
212 #if TARGET_ABI_OPEN_VMS
214 #endif
220 \f
221 /* Parse target option strings. */
223 void
225 {
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
249 };
251 /* Unicos/Mk doesn't have shared libraries. */
253 {
257 }
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
263 else
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
276 {
279 else
280 {
283 }
284 }
287 {
290 else
291 {
294 }
295 }
298 {
305 else
307 }
310 {
319 else
321 alpha_fprm_string);
322 }
325 {
334 else
336 }
339 {
346 else
348 }
350 alpha_cpu
355 {
358 {
364 }
367 }
370 {
373 {
376 }
379 }
381 /* Do some sanity checks on the above options. */
384 {
387 }
391 {
394 }
397 {
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
402 }
405 {
407 {
410 }
412 {
415 }
419 }
421 {
430 ;
434 {
436 {
440 };
444 {
448 }
449 else
451 }
453 {
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
457 }
458 else
459 {
462 }
465 }
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
481 {
486 }
490 /* Acquire a unique set number for our register saves and restores. */
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
498 /* Tell the compiler when we're using VAX floating point. */
500 {
504 }
505 }
506 \f
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
509 int
511 {
520 }
522 /* Returns 1 if OP is either the constant zero or a register. If a
523 register, it must be in the proper mode unless MODE is VOIDmode. */
525 int
527 {
529 }
531 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
532 any register. */
534 int
536 {
540 }
543 /* Return 1 if OP is an 8-bit constant or any register. */
545 int
547 {
551 }
553 /* Return 1 if OP is a constant or any register. */
555 int
557 {
559 }
561 /* Return 1 if OP is an 8-bit constant. */
563 int
565 {
568 }
570 /* Return 1 if the operand is a valid second operand to an add insn. */
572 int
574 {
576 /* Constraints I, J, O and P are covered by K. */
581 }
583 /* Return 1 if the operand is a valid second operand to a sign-extending
584 add insn. */
586 int
588 {
594 }
596 /* Return 1 if OP is the constant 4 or 8. */
598 int
600 {
603 }
605 /* Return 1 if OP is a valid first operand to an AND insn. */
607 int
609 {
620 }
622 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
624 int
626 {
632 }
634 /* Return 1 if OP is a constant that is the width, in bits, of an integral
635 mode smaller than DImode. */
637 int
639 {
643 }
645 /* Return 1 if OP is a constant that is the width of an integral machine mode
646 smaller than an integer. */
648 int
650 {
652 {
663 }
665 {
668 }
671 }
673 /* Return 1 if OP is a multiple of 8 less than 64. */
675 int
677 {
681 }
683 /* Return 1 if OP is the zero constant for MODE. */
685 int
687 {
689 }
691 /* Return 1 if OP is a hard floating-point register. */
693 int
695 {
702 }
704 /* Return 1 if OP is a hard general register. */
706 int
708 {
715 }
717 /* Return 1 if OP is a register or a constant integer. */
720 int
722 {
725 }
727 /* Return 1 if OP is something that can be reloaded into a register;
728 if it is a MEM, it need not be valid. */
730 int
732 {
737 {
754 }
757 }
759 /* Likewise, but don't accept constants. */
761 int
763 {
771 }
773 /* Return 1 if OP is a valid operand for the source of a move insn. */
775 int
777 {
785 {
790 {
791 /* We don't split symbolic operands into something unintelligable
792 until after reload, but we do not wish non-small, non-global
793 symbolic operands to be reconstructed from their high/lo_sum
794 form. */
799 }
801 /* This handles both the Windows/NT and OSF cases. */
814 /* ... fall through ... */
828 }
831 }
833 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
834 file, and in the same section as the current function. */
836 int
838 {
842 /* Easy test for recursion. */
846 /* Functions that are not local can be overridden, and thus may
847 not share the same gp. */
851 /* If -msmall-data is in effect, assume that there is only one GP
852 for the module, and so any local symbol has this property. We
853 need explicit relocations to be able to enforce this for symbols
854 not defined in this unit of translation, however. */
858 /* Functions that are not external are defined in this UoT,
859 and thus must share the same gp. */
861 }
863 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
865 int
867 {
870 /* Must share the same GP. */
874 /* If profiling is implemented via linker tricks, we can't jump
875 to the nogp alternate entry point. Note that current_function_profile
876 would not be correct, since that doesn't indicate if the target
877 function uses profiling. */
878 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
879 but is approximately correct for the OSF ABIs. Don't know
880 what to do for VMS, NT, or UMK. */
884 /* Must be a function. In some cases folks create thunks in static
885 data structures and then make calls to them. If we allow the
886 direct call, we'll get an error from the linker about !samegp reloc
887 against a symbol without a .prologue directive. */
891 /* Must be "near" so that the branch is assumed to reach. With
892 -msmall-text, this is assumed true of all local symbols. Since
893 we've already checked samegp, locality is already assured. */
897 /* Otherwise, a decl is "near" if it is defined in the same section. */
912 }
914 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
915 a (non-tls) variable known to be defined in this file. */
917 int
919 {
935 }
937 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
938 known to be defined in this file in the small data area. */
940 int
942 {
957 /* ??? There's no encode_section_info equivalent for the rtl
958 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
965 }
967 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
968 not known (or known not) to be defined in this file. */
970 int
972 {
985 }
987 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
989 int
991 {
996 {
998 {
999 /* Disallow virtual registers to cope with pathological test cases
1000 such as compile/930117-1.c in which the virtual reg decomposes
1001 to the frame pointer. Which is a hard reg that is not $27. */
1003 }
1004 else
1006 }
1013 }
1015 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1016 possibly with an offset. */
1018 int
1020 {
1031 }
1033 /* Return true if OP is valid for a particular TLS relocation. */
1035 static int
1037 {
1053 {
1056 }
1057 else
1058 {
1061 }
1064 {
1073 }
1074 }
1076 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1078 int
1080 {
1082 }
1084 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1086 int
1088 {
1090 }
1092 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1094 int
1096 {
1098 }
1100 /* Return true if OP is valid for 16-bit TP relative relocations. */
1102 int
1104 {
1106 }
1108 /* Return true if OP is valid for 32-bit TP relative relocations. */
1110 int
1112 {
1114 }
1116 /* Return true if OP is valid for 64-bit TP relative relocations. */
1118 int
1120 {
1122 }
1124 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1125 comparisons are valid in which insn. */
1127 int
1129 {
1137 }
1139 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1140 Here we know which comparisons are valid in which insn. */
1142 int
1144 {
1152 }
1154 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1156 int
1158 {
1168 }
1170 /* Return 1 if OP is a signed comparison operation. */
1172 int
1174 {
1183 }
1185 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1186 Here we know which comparisons are valid in which insn. */
1188 int
1190 {
1197 }
1199 /* Return 1 if this is a divide or modulus operator. */
1201 int
1203 {
1207 }
1209 /* Return 1 if this is a float->int conversion operator. */
1211 int
1213 {
1217 }
1219 /* Return 1 if this memory address is a known aligned register plus
1220 a constant. It must be a valid address. This means that we can do
1221 this as an aligned reference plus some offset.
1223 Take into account what reload will do. */
1225 int
1227 {
1228 rtx base;
1231 {
1237 {
1241 }
1242 }
1250 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1251 sorts of constructs. Dig for the real base register. */
1256 else
1257 {
1261 }
1264 }
1266 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1268 int
1270 {
1271 rtx base;
1274 {
1280 {
1284 }
1285 }
1293 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1294 sorts of constructs. Dig for the real base register. */
1299 else
1300 {
1304 }
1307 }
1309 /* Return 1 if OP is either a register or an unaligned memory location. */
1311 int
1313 {
1315 }
1317 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1319 int
1321 {
1329 }
1331 /* Returns 1 if OP is not an eliminable register.
1333 This exists to cure a pathological abort in the s8addq (et al) patterns,
1335 long foo () { long t; bar(); return (long) &t * 26107; }
1337 which run afoul of a hack in reload to cure a (presumably) similar
1338 problem with lea-type instructions on other targets. But there is
1339 one of us and many of them, so work around the problem by selectively
1340 preventing combine from making the optimization. */
1342 int
1344 {
1352 }
1354 /* Return 1 is OP is a memory location that is not a reference (using
1355 an AND) to an unaligned location. Take into account what reload
1356 will do. */
1358 int
1360 {
1362 {
1368 {
1371 /* This may not have been assigned an equivalent address if it will
1372 be eliminated. In that case, it doesn't matter what we do. */
1375 }
1376 }
1379 }
1381 /* Accept a register, but not a subreg of any kind. This allows us to
1382 avoid pathological cases in reload wrt data movement common in
1383 int->fp conversion. */
1385 int
1387 {
1391 }
1393 /* Recognize an addition operation that includes a constant. Used to
1394 convince reload to canonize (plus (plus reg c1) c2) during register
1395 elimination. */
1397 int
1399 {
1408 }
1410 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1411 the range defined for C in [I-P]. */
1413 bool
1415 {
1417 {
1419 /* An unsigned 8 bit constant. */
1422 /* The constant zero. */
1425 /* A signed 16 bit constant. */
1428 /* A shifted signed 16 bit constant appropriate for LDAH. */
1432 /* A constant that can be AND'ed with using a ZAP insn. */
1435 /* A complemented unsigned 8 bit constant. */
1438 /* A negated unsigned 8 bit constant. */
1441 /* The constant 1, 2 or 3. */
1446 }
1447 }
1449 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1450 matches for C in [GH]. */
1452 bool
1454 {
1456 {
1458 /* The floating point zero constant. */
1463 /* A valid operand of a ZAP insn. */
1470 }
1471 }
1473 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1474 matches for C. */
1476 bool
1478 {
1480 {
1497 }
1498 }
1500 /* Return 1 if this function can directly return via $26. */
1502 int
1504 {
1506 && reload_completed
1511 }
1513 /* Return the ADDR_VEC associated with a tablejump insn. */
1515 rtx
1517 {
1518 rtx tmp;
1530 }
1532 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1534 rtx
1536 {
1540 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1541 there for edge frequency counts from profile data. */
1544 {
1550 {
1556 count++;
1560 }
1561 }
1564 }
1566 /* Return the TLS model to use for SYMBOL. */
1568 static enum tls_model
1570 {
1577 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1582 }
1583 \f
1584 /* Return true if the function DECL will share the same GP as any
1585 function in the current unit of translation. */
1587 static bool
1589 {
1590 /* Functions that are not local can be overridden, and thus may
1591 not share the same gp. */
1595 /* If -msmall-data is in effect, assume that there is only one GP
1596 for the module, and so any local symbol has this property. We
1597 need explicit relocations to be able to enforce this for symbols
1598 not defined in this unit of translation, however. */
1602 /* Functions that are not external are defined in this UoT. */
1603 /* ??? Irritatingly, static functions not yet emitted are still
1604 marked "external". Apply this to non-static functions only. */
1606 }
1608 /* Return true if EXP should be placed in the small data section. */
1610 static bool
1612 {
1613 /* We want to merge strings, so we never consider them small data. */
1617 /* Functions are never in the small data area. Duh. */
1622 {
1627 }
1628 else
1629 {
1632 /* If this is an incomplete type with size 0, then we can't put it
1633 in sdata because it might be too big when completed. */
1636 }
1639 }
1641 #if TARGET_ABI_OPEN_VMS
1642 static bool
1644 {
1651 }
1653 #define LINKAGE_SYMBOL_REF_P(X) \
1654 ((GET_CODE (X) == SYMBOL_REF \
1655 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1656 || (GET_CODE (X) == CONST \
1657 && GET_CODE (XEXP (X, 0)) == PLUS \
1658 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1659 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1660 #endif
1662 /* legitimate_address_p recognizes an RTL expression that is a valid
1663 memory address for an instruction. The MODE argument is the
1664 machine mode for the MEM expression that wants to use this address.
1666 For Alpha, we have either a constant address or the sum of a
1667 register and a constant address, or just a register. For DImode,
1668 any of those forms can be surrounded with an AND that clear the
1669 low-order three bits; this is an "unaligned" access. */
1671 bool
1673 {
1674 /* If this is an ldq_u type address, discard the outer AND. */
1681 /* Discard non-paradoxical subregs. */
1687 /* Unadorned general registers are valid. */
1689 && (strict
1694 /* Constant addresses (i.e. +/- 32k) are valid. */
1698 #if TARGET_ABI_OPEN_VMS
1701 #endif
1703 /* Register plus a small constant offset is valid. */
1705 {
1709 /* Discard non-paradoxical subregs. */
1716 {
1726 }
1727 }
1729 /* If we're managing explicit relocations, LO_SUM is valid, as
1730 are small data symbols. */
1732 {
1737 {
1741 /* Discard non-paradoxical subregs. */
1747 /* Must have a valid base register. */
1749 && (strict
1754 /* The symbol must be local. */
1759 }
1760 }
1763 }
1765 /* Build the SYMBOL_REF for __tls_get_addr. */
1769 static rtx
1771 {
1775 }
1777 /* Try machine-dependent ways of modifying an illegitimate address
1778 to be legitimate. If we find one, return the new, valid address. */
1780 rtx
1783 {
1784 HOST_WIDE_INT addend;
1786 /* If the address is (plus reg const_int) and the CONST_INT is not a
1787 valid offset, compute the high part of the constant and add it to
1788 the register. Then our address is (plus temp low-part-const). */
1793 {
1797 }
1799 /* If the address is (const (plus FOO const_int)), find the low-order
1800 part of the CONST_INT. Then load FOO plus any high-order part of the
1801 CONST_INT into a register. Our address is (plus reg low-part-const).
1802 This is done to reduce the number of GOT entries. */
1807 {
1811 }
1813 /* If we have a (plus reg const), emit the load as in (2), then add
1814 the two registers, and finally generate (plus reg low-part-const) as
1815 our address. */
1822 {
1828 }
1830 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1832 {
1836 {
1877 UNSPEC_TLSLDM_CALL);
1884 {
1889 }
1891 {
1896 }
1918 {
1923 }
1925 }
1928 {
1931 else
1932 {
1938 }
1939 }
1940 }
1944 split_addend:
1945 {
1963 }
1964 }
1966 /* We do not allow indirect calls to be optimized into sibling calls, nor
1967 can we allow a call to a function with a different GP to be optimized
1968 into a sibcall. */
1970 static bool
1972 {
1973 /* Can't do indirect tail calls, since we don't know if the target
1974 uses the same GP. */
1978 /* Otherwise, we can make a tail call if the target function shares
1979 the same GP. */
1981 }
1983 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1984 small symbolic operand until after reload. At which point we need
1985 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1986 so that sched2 has the proper dependency information. */
1988 static int
1990 {
1993 /* Don't re-split. */
1998 }
2000 int
2002 {
2004 }
2006 static int
2008 {
2011 /* Don't re-split. */
2016 {
2020 }
2023 }
2025 rtx
2027 {
2031 }
2033 /* Indicate that INSN cannot be duplicated. This is true for any insn
2034 that we've marked with gpdisp relocs, since those have to stay in
2035 1-1 correspondence with one another.
2037 Technically we could copy them if we could set up a mapping from one
2038 sequence number to another, across the set of insns to be duplicated.
2039 This seems overly complicated and error-prone since interblock motion
2040 from sched-ebb could move one of the pair of insns to a different block.
2042 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2043 then they'll be in a different block from their ldgp. Which could lead
2044 the bb reorder code to think that it would be ok to copy just the block
2045 containing the call and branch to the block containing the ldgp. */
2047 static bool
2049 {
2054 else
2056 }
2059 /* Try a machine-dependent way of reloading an illegitimate address
2060 operand. If we find one, push the reload and return the new rtx. */
2062 rtx
2067 {
2068 /* We must recognize output that we have already generated ourselves. */
2074 {
2079 }
2081 /* We wish to handle large displacements off a base register by
2082 splitting the addend across an ldah and the mem insn. This
2083 cuts number of extra insns needed from 3 to 1. */
2089 {
2092 HOST_WIDE_INT high
2095 /* Check for 32-bit overflow. */
2099 /* Reload the high part into a base reg; leave the low part
2100 in the mem directly. */
2110 }
2113 }
2114 \f
2115 /* Compute a (partial) cost for rtx X. Return true if the complete
2116 cost has been computed, and false if subexpressions should be
2117 scanned. In either case, *TOTAL contains the cost result. */
2119 static bool
2121 {
2128 else
2132 {
2134 /* If this is an 8-bit constant, return zero since it can be used
2135 nearly anywhere with no cost. If it is a valid operand for an
2136 ADD or AND, likewise return 0 if we know it will be used in that
2137 context. Otherwise, return 2 since it might be used there later.
2138 All other constants take at least two insns. */
2140 {
2143 }
2144 /* FALLTHRU */
2154 else
2166 /* Estimate of cost for call_pal rduniq. */
2167 /* ??? How many insns do we emit here? More than one... */
2169 else
2170 /* Otherwise we do a load from the GOT. */
2180 {
2184 }
2192 else
2199 {
2202 }
2203 /* FALLTHRU */
2213 else
2225 else
2235 {
2238 }
2239 /* FALLTHRU */
2243 {
2246 }
2247 /* FALLTHRU */
2260 }
2261 }
2262 \f
2263 /* REF is an alignable memory location. Place an aligned SImode
2264 reference into *PALIGNED_MEM and the number of bits to shift into
2265 *PBITNUM. SCRATCH is a free register for use in reloading out
2266 of range stack slots. */
2268 void
2270 {
2271 rtx base;
2279 {
2284 }
2285 else
2286 {
2288 }
2293 *paligned_mem
2299 else
2301 }
2303 /* Similar, but just get the address. Handle the two reload cases.
2304 Add EXTRA_OFFSET to the address we return. */
2306 rtx
2308 {
2309 rtx base;
2317 {
2322 }
2323 else
2324 {
2326 }
2332 }
2334 /* On the Alpha, all (non-symbolic) constants except zero go into
2335 a floating-point register via memory. Note that we cannot
2336 return anything that is not a subset of CLASS, and that some
2337 symbolic constants cannot be dropped to memory. */
2339 enum reg_class
2341 {
2342 /* Zero is present in any register class. */
2346 /* These sorts of constants we can easily drop to memory. */
2348 {
2354 }
2356 /* All other kinds of constants should not (and in the case of HIGH
2357 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2358 secondary reload. */
2363 }
2365 /* Loading and storing HImode or QImode values to and from memory
2366 usually requires a scratch register. The exceptions are loading
2367 QImode and HImode from an aligned address to a general register
2368 unless byte instructions are permitted.
2370 We also cannot load an unaligned address or a paradoxical SUBREG
2371 into an FP register.
2373 We also cannot do integral arithmetic into FP regs, as might result
2374 from register elimination into a DImode fp register. */
2376 enum reg_class
2379 {
2381 {
2388 {
2391 }
2392 }
2395 {
2407 }
2410 }
2411 \f
2412 /* Subfunction of the following function. Update the flags of any MEM
2413 found in part of X. */
2415 static void
2417 {
2421 {
2428 unchanging_p);
2433 unchanging_p);
2438 unchanging_p);
2440 unchanging_p);
2447 /* Sadly, we cannot use alias sets because the extra aliasing
2448 produced by the AND interferes. Given that two-byte quantities
2449 are the only thing we would be able to differentiate anyway,
2450 there does not seem to be any point in convoluting the early
2451 out of the alias check. */
2456 }
2457 }
2459 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2460 generated to perform a memory operation, look for any MEMs in either
2461 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2462 volatile flags from REF into each of the MEMs found. If REF is not
2463 a MEM, don't do anything. */
2465 void
2467 {
2477 /* This is only called from alpha.md, after having had something
2478 generated from one of the insn patterns. So if everything is
2479 zero, the pattern is already up-to-date. */
2484 }
2485 \f
2486 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2488 static rtx
2491 {
2494 /* Use a pseudo if highly optimizing and still generating RTL. */
2495 rtx subtarget
2499 /* If this is a sign-extended 32-bit constant, we can do this in at most
2500 three insns, so do it if we have enough insns left. We always have
2501 a sign-extended 32-bit constant when compiling on a narrow machine. */
2505 {
2511 /* If HIGH will be interpreted as negative but the constant is
2512 positive, we must adjust it to do two ldha insns. */
2515 {
2519 }
2522 {
2523 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2524 but that meant that we can't handle INT_MIN on 32-bit machines
2525 (like NT/Alpha), because we recurse indefinitely through
2526 emit_move_insn to gen_movdi. So instead, since we know exactly
2527 what we want, create it explicitly. */
2533 }
2535 {
2537 {
2540 }
2541 else
2545 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2546 This means that if we go through expand_binop, we'll try to
2547 generate extensions, etc, which will require new pseudos, which
2548 will fail during some split phases. The SImode add patterns
2549 still exist, but are not named. So build the insns by hand. */
2552 {
2559 }
2567 }
2568 }
2570 /* If we couldn't do it that way, try some other methods. But if we have
2571 no instructions left, don't bother. Likewise, if this is SImode and
2572 we can't make pseudos, we can't do anything since the expand_binop
2573 and expand_unop calls will widen and try to make pseudos. */
2578 /* Next, see if we can load a related constant and then shift and possibly
2579 negate it to get the constant we want. Try this once each increasing
2580 numbers of insns. */
2583 {
2584 /* First, see if minus some low bits, we've an easy load of
2585 high bits. */
2593 /* Next try complementing. */
2597 /* Next try to form a constant and do a left shift. We can do this
2598 if some low-order bits are zero; the exact_log2 call below tells
2599 us that information. The bits we are shifting out could be any
2600 value, but here we'll just try the 0- and sign-extended forms of
2601 the constant. To try to increase the chance of having the same
2602 constant in more than one insn, start at the highest number of
2603 bits to shift, but try all possibilities in case a ZAPNOT will
2604 be useful. */
2617 /* Now try high-order zero bits. Here we try the shifted-in bits as
2618 all zero and all ones. Be careful to avoid shifting outside the
2619 mode and to avoid shifting outside the host wide int size. */
2620 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2621 confuse the recursive call and set all of the high 32 bits. */
2631 i)))
2636 /* Now try high-order 1 bits. We get that with a sign-extension.
2637 But one bit isn't enough here. Be careful to avoid shifting outside
2638 the mode and to avoid shifting outside the host wide int size. */
2648 i)))
2652 }
2654 #if HOST_BITS_PER_WIDE_INT == 64
2655 /* Finally, see if can load a value into the target that is the same as the
2656 constant except that all bytes that are 0 are changed to be 0xff. If we
2657 can, then we can do a ZAPNOT to obtain the desired constant. */
2664 /* We are only called for SImode and DImode. If this is SImode, ensure that
2665 we are sign extended to a full word. */
2674 #endif
2677 }
2679 /* Try to output insns to set TARGET equal to the constant C if it can be
2680 done in less than N insns. Do all computations in MODE. Returns the place
2681 where the output has been placed if it can be done and the insns have been
2682 emitted. If it would take more than N insns, zero is returned and no
2683 insns and emitted. */
2685 rtx
2688 {
2693 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2694 can't load this constant in one insn, do this in DImode. */
2698 {
2701 }
2703 /* Try 1 insn, then 2, then up to N. */
2705 {
2708 {
2714 }
2715 }
2717 /* Allow for the case where we changed the mode of TARGET. */
2722 }
2724 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2725 fall back to a straight forward decomposition. We do this to avoid
2726 exponential run times encountered when looking for longer sequences
2727 with alpha_emit_set_const. */
2729 rtx
2731 {
2734 /* Decompose the entire word */
2735 #if HOST_BITS_PER_WIDE_INT >= 64
2747 #else
2759 #endif
2761 /* Construct the high word */
2763 {
2767 }
2768 else
2771 /* Shift it into place */
2774 /* Add in the low bits. */
2781 }
2783 /* Expand a move instruction; return true if all work is done.
2784 We don't handle non-bwx subword loads here. */
2786 bool
2788 {
2789 /* If the output is not a register, the input must be. */
2794 /* Allow legitimize_address to perform some simplifications. */
2796 {
2797 rtx tmp;
2799 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2800 compiled at the end of compilation. In the meantime, someone can
2801 re-encode-section-info on some symbol changing it e.g. from global
2802 to local-not-small. If this happens, we'd have emitted a plain
2803 load rather than a high+losum load and not recognize the insn.
2805 So if rtl inlining is in effect, we delay the global/not-global
2806 decision until rest_of_compilation by wrapping it in an
2807 UNSPEC_SYMBOL. */
2809 && rtx_equal_function_value_matters
2811 {
2814 }
2818 {
2823 }
2824 }
2826 /* Early out for non-constants and valid constants. */
2830 /* Split large integers. */
2833 {
2838 {
2841 }
2843 {
2846 }
2847 else
2848 {
2851 }
2860 {
2865 }
2866 }
2868 /* Otherwise we've nothing left but to drop the thing to memory. */
2871 {
2875 }
2876 else
2879 }
2881 /* Expand a non-bwx QImode or HImode move instruction;
2882 return true if all work is done. */
2884 bool
2886 {
2887 /* If the output is not a register, the input must be. */
2891 /* Handle four memory cases, unaligned and aligned for either the input
2892 or the output. The only case where we can be called during reload is
2893 for aligned loads; all other cases require temporaries. */
2903 {
2905 {
2907 {
2909 ? gen_reload_inqi_help
2913 }
2914 else
2915 {
2918 rtx subtarget;
2926 else
2930 ? gen_aligned_loadqi
2936 }
2937 }
2938 else
2939 {
2940 /* Don't pass these as parameters since that makes the generated
2941 code depend on parameter evaluation order which will cause
2942 bootstrap failures. */
2953 else
2957 ? gen_unaligned_loadqi
2966 }
2968 }
2978 {
2980 {
2989 }
2990 else
2991 {
2996 ? gen_unaligned_storeqi
3003 }
3005 }
3008 }
3010 /* Generate an unsigned DImode to FP conversion. This is the same code
3011 optabs would emit if we didn't have TFmode patterns.
3013 For SFmode, this is the only construction I've found that can pass
3014 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3015 intermediates will work, because you'll get intermediate rounding
3016 that ruins the end result. Some of this could be fixed by turning
3017 on round-to-positive-infinity, but that requires diddling the fpsr,
3018 which kills performance. I tried turning this around and converting
3019 to a negative number, so that I could turn on /m, but either I did
3020 it wrong or there's something else cause I wound up with the exact
3021 same single-bit error. There is a branch-less form of this same code:
3023 srl $16,1,$1
3024 and $16,1,$2
3025 cmplt $16,0,$3
3026 or $1,$2,$2
3027 cmovge $16,$16,$2
3028 itoft $3,$f10
3029 itoft $2,$f11
3030 cvtqs $f11,$f11
3031 adds $f11,$f11,$f0
3032 fcmoveq $f10,$f11,$f0
3034 I'm not using it because it's the same number of instructions as
3035 this branch-full form, and it has more serialized long latency
3036 instructions on the critical path.
3038 For DFmode, we can avoid rounding errors by breaking up the word
3039 into two pieces, converting them separately, and adding them back:
3041 LC0: .long 0,0x5f800000
3043 itoft $16,$f11
3044 lda $2,LC0
3045 cmplt $16,0,$1
3046 cpyse $f11,$f31,$f10
3047 cpyse $f31,$f11,$f11
3048 s4addq $1,$2,$1
3049 lds $f12,0($1)
3050 cvtqt $f10,$f10
3051 cvtqt $f11,$f11
3052 addt $f12,$f10,$f0
3053 addt $f0,$f11,$f0
3055 This doesn't seem to be a clear-cut win over the optabs form.
3056 It probably all depends on the distribution of numbers being
3057 converted -- in the optabs form, all but high-bit-set has a
3058 much lower minimum execution time. */
3060 void
3062 {
3090 }
3092 /* Generate the comparison for a conditional branch. */
3094 rtx
3096 {
3100 rtx tem;
3103 {
3107 /* X_floating library comparison functions return
3108 -1 unordered
3109 0 false
3110 1 true
3111 Convert the compare against the raw return value. */
3114 {
3131 }
3136 }
3138 /* The general case: fold the comparison code to the types of compares
3139 that we have, choosing the branch as necessary. */
3141 {
3144 /* We have these compares: */
3150 /* These must be reversed. */
3155 /* For FP, we swap them, for INT, we reverse them. */
3157 {
3161 }
3162 else
3163 {
3166 }
3171 }
3174 {
3177 {
3178 /* When we are not as concerned about non-finite values, and we
3179 are comparing against zero, we can branch directly. */
3183 {
3184 /* Undo the swap we probably did just above. */
3188 }
3189 }
3190 else
3191 {
3192 /* ??? We mark the branch mode to be CCmode to prevent the
3193 compare and branch from being combined, since the compare
3194 insn follows IEEE rules that the branch does not. */
3196 }
3197 }
3198 else
3199 {
3202 /* The following optimizations are only for signed compares. */
3204 {
3205 /* Whee. Compare and branch against 0 directly. */
3209 /* If the constants doesn't fit into an immediate, but can
3210 be generated by lda/ldah, we adjust the argument and
3211 compare against zero, so we can use beq/bne directly. */
3212 /* ??? Don't do this when comparing against symbols, otherwise
3213 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3214 be declared false out of hand (at least for non-weak). */
3219 {
3225 {
3228 }
3229 }
3230 }
3236 }
3238 /* Emit an initial compare instruction, if necessary. */
3241 {
3244 }
3246 /* Zero the operands. */
3249 /* Return the branch comparison. */
3251 }
3253 /* Certain simplifications can be done to make invalid setcc operations
3254 valid. Return the final comparison, or NULL if we can't work. */
3256 rtx
3258 {
3262 rtx tmp;
3264 /* Zero the operands. */
3268 {
3272 /* X_floating library comparison functions return
3273 -1 unordered
3274 0 false
3275 1 true
3276 Convert the compare against the raw return value. */
3280 else
3291 else
3293 }
3298 /* The general case: fold the comparison code to the types of compares
3299 that we have, choosing the branch as necessary. */
3303 {
3306 /* We have these compares. */
3314 /* FALLTHRU */
3322 /* These normally need swapping, but for integer zero we have
3323 special patterns that recognize swapped operands. */
3334 }
3337 {
3342 }
3344 /* Emit an initial compare instruction, if necessary. */
3346 {
3355 }
3357 /* Return the setcc comparison. */
3359 }
3362 /* Rewrite a comparison against zero CMP of the form
3363 (CODE (cc0) (const_int 0)) so it can be written validly in
3364 a conditional move (if_then_else CMP ...).
3365 If both of the operands that set cc0 are nonzero we must emit
3366 an insn to perform the compare (it can't be done within
3367 the conditional move). */
3369 rtx
3371 {
3377 enum machine_mode cmp_mode
3382 rtx tem;
3384 /* Zero the operands. */
3388 {
3394 /* If we have fp<->int register move instructions, do a cmov by
3395 performing the comparison in fp registers, and move the
3396 zero/nonzero value to integer registers, where we can then
3397 use a normal cmov, or vice-versa. */
3400 {
3402 /* We have these compares. */
3407 /* This must be reversed. */
3412 /* These normally need swapping, but for integer zero we have
3413 special patterns that recognize swapped operands. */
3416 else
3417 {
3421 }
3426 }
3438 }
3440 /* We may be able to use a conditional move directly.
3441 This avoids emitting spurious compares. */
3447 /* We can't put the comparison inside the conditional move;
3448 emit a compare instruction and put that inside the
3449 conditional move. Make sure we emit only comparisons we have;
3450 swap or reverse as necessary. */
3456 {
3458 /* We have these compares: */
3462 /* This must be reversed. */
3468 /* These must be swapped. */
3470 {
3473 }
3478 }
3481 {
3486 }
3488 /* ??? We mark the branch mode to be CCmode to prevent the compare
3489 and cmov from being combined, since the compare insn follows IEEE
3490 rules that the cmov does not. */
3497 }
3499 /* Simplify a conditional move of two constants into a setcc with
3500 arithmetic. This is done with a splitter since combine would
3501 just undo the work if done during code generation. It also catches
3502 cases we wouldn't have before cse. */
3504 int
3507 {
3519 {
3523 }
3527 {
3531 else
3533 }
3534 /* Below, we must be careful to use copy_rtx on target and subtarget
3535 in intermediate insns, as they may be a subreg rtx, which may not
3536 be shared. */
3539 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3540 viable over a longer latency cmove. On EV5, the E0 slot is a
3541 scarce resource, and on EV4 shift has the same latency as a cmove. */
3543 {
3550 }
3552 {
3557 }
3559 {
3560 rtx add_op;
3567 else
3568 {
3571 {
3576 }
3577 else
3579 }
3580 }
3581 else
3585 }
3586 \f
3587 /* Look up the function X_floating library function name for the
3588 given operation. */
3591 {
3595 rtx libcall;
3596 };
3599 {
3615 };
3618 {
3621 };
3623 static rtx
3625 {
3630 /* How irritating. Nothing to key off for the main table. */
3632 {
3635 }
3639 {
3642 {
3646 }
3648 }
3651 }
3653 /* Most X_floating operations take the rounding mode as an argument.
3654 Compute that here. */
3656 static int
3659 {
3663 {
3679 /* XXX For reference, round to +inf is mode = 3. */
3680 }
3686 }
3688 /* Emit an X_floating library function call.
3690 Note that these functions do not follow normal calling conventions:
3691 TFmode arguments are passed in two integer registers (as opposed to
3692 indirect); TFmode return values appear in R16+R17.
3694 FUNC is the function to call.
3695 TARGET is where the output belongs.
3696 OPERANDS are the inputs.
3697 NOPERANDS is the count of inputs.
3698 EQUIV is the expression equivalent for the function.
3699 */
3701 static void
3704 {
3711 {
3713 {
3727 /* FALLTHRU */
3735 }
3739 }
3742 {
3754 }
3766 }
3768 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3770 void
3772 {
3773 rtx func;
3786 }
3788 /* Emit an X_floating library function call for a comparison. */
3790 static rtx
3792 {
3793 rtx func;
3802 /* ??? Strange mode for equiv because what's actually returned
3803 is -1,0,1, not a proper boolean value. */
3808 }
3810 /* Emit an X_floating library function call for a conversion. */
3812 void
3814 {
3817 rtx func;
3828 {
3841 }
3847 }
3849 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3850 OP[0] into OP[0,1]. Naturally, output operand ordering is
3851 little-endian. */
3853 void
3855 {
3857 {
3860 }
3862 {
3865 }
3868 else
3872 {
3875 }
3877 {
3880 }
3881 else
3883 }
3885 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3886 op2 is a register containing the sign bit, operation is the
3887 logical operation to be performed. */
3889 void
3891 {
3893 rtx scratch;
3898 /* Detect three flavors of operand overlap. */
3903 {
3906 else
3908 }
3913 /* ??? If the destination overlaps both source tf and high_bit, then
3914 assume source tf is dead in its entirety and use the other half
3915 for a scratch register. Otherwise "scratch" is just the proper
3916 destination register. */
3922 {
3926 }
3927 }
3928 \f
3929 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3930 unaligned data:
3932 unsigned: signed:
3933 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3934 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3935 lda r3,X(r11) lda r3,X+2(r11)
3936 extwl r1,r3,r1 extql r1,r3,r1
3937 extwh r2,r3,r2 extqh r2,r3,r2
3938 or r1.r2.r1 or r1,r2,r1
3939 sra r1,48,r1
3941 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3942 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3943 lda r3,X(r11) lda r3,X(r11)
3944 extll r1,r3,r1 extll r1,r3,r1
3945 extlh r2,r3,r2 extlh r2,r3,r2
3946 or r1.r2.r1 addl r1,r2,r1
3948 quad: ldq_u r1,X(r11)
3949 ldq_u r2,X+7(r11)
3950 lda r3,X(r11)
3951 extql r1,r3,r1
3952 extqh r2,r3,r2
3953 or r1.r2.r1
3954 */
3956 void
3959 {
3973 /* AND addresses cannot be in any alias set, since they may implicitly
3974 alias surrounding code. Ideally we'd have some alias set that
3975 covered all types except those with alignment 8 or higher. */
3992 {
4001 }
4003 {
4009 /* We must use tgt here for the target. Alpha-vms port fails if we use
4010 addr for the target, because addr is marked as a pointer and combine
4011 knows that pointers are always sign-extended 32 bit values. */
4015 }
4016 else
4017 {
4019 {
4022 {
4040 }
4042 }
4043 else
4044 {
4048 {
4066 }
4067 }
4072 }
4076 }
4078 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4080 void
4083 {
4095 /* AND addresses cannot be in any alias set, since they may implicitly
4096 alias surrounding code. Ideally we'd have some alias set that
4097 covered all types except those with alignment 8 or higher. */
4114 {
4118 {
4120 {
4130 }
4133 }
4136 {
4141 {
4145 }
4149 }
4152 }
4153 else
4154 {
4158 {
4163 {
4173 }
4174 }
4179 {
4184 {
4188 }
4192 }
4193 }
4196 {
4199 }
4202 {
4205 }
4206 else
4207 {
4208 /* Must store high before low for degenerate case of aligned. */
4211 }
4212 }
4214 /* The block move code tries to maximize speed by separating loads and
4215 stores at the expense of register pressure: we load all of the data
4216 before we store it back out. There are two secondary effects worth
4217 mentioning, that this speeds copying to/from aligned and unaligned
4218 buffers, and that it makes the code significantly easier to write. */
4220 #define MAX_MOVE_WORDS 8
4222 /* Load an integral number of consecutive unaligned quadwords. */
4224 static void
4227 {
4232 HOST_WIDE_INT i;
4238 /* Generate all the tmp registers we need. */
4240 {
4243 }
4249 /* Load up all of the source data. */
4251 {
4255 im8));
4258 }
4263 im8));
4267 /* Extract the half-word fragments. Unfortunately DEC decided to make
4268 extxh with offset zero a noop instead of zeroing the register, so
4269 we must take care of that edge condition ourselves with cmov. */
4277 {
4279 {
4282 }
4283 else
4284 {
4287 }
4291 const0_rtx),
4293 }
4295 /* Merge the half-words into whole words. */
4297 {
4300 }
4301 }
4303 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4304 may be NULL to store zeros. */
4306 static void
4309 {
4315 HOST_WIDE_INT i;
4321 /* Generate all the tmp registers we need. */
4334 im8));
4341 /* Load up the destination end bits. */
4345 /* Shift the input data into place. */
4350 {
4352 {
4354 {
4357 }
4358 else
4359 {
4362 }
4363 }
4365 {
4368 OPTAB_WIDEN);
4369 }
4370 }
4372 /* Split and merge the ends with the destination data. */
4374 {
4377 }
4378 else
4379 {
4382 }
4385 {
4390 }
4392 /* Store it all. */
4395 else
4398 {
4403 im8));
4406 }
4409 else
4411 }
4414 /* Expand string/block move operations.
4416 operands[0] is the pointer to the destination.
4417 operands[1] is the pointer to the source.
4418 operands[2] is the number of bytes to move.
4419 operands[3] is the alignment. */
4421 int
4423 {
4433 rtx tmp;
4441 /* Look for additional alignment information from recorded register info. */
4449 {
4454 {
4461 }
4462 }
4470 {
4475 {
4482 }
4483 }
4487 {
4500 }
4503 {
4516 }
4519 {
4531 }
4534 {
4539 }
4542 {
4544 {
4551 }
4553 {
4558 }
4559 }
4562 {
4567 }
4572 /* Now save it back out again. */
4576 /* Write out the data in whatever chunks reading the source allowed. */
4578 {
4580 {
4584 i++;
4585 }
4586 }
4589 {
4590 /* If the source has remaining DImode regs, write them out in
4591 two pieces. */
4593 {
4602 i++;
4603 }
4606 {
4610 i++;
4611 }
4612 }
4615 {
4616 /* Write out a remaining block of words using unaligned methods. */
4624 else
4630 }
4632 /* Due to the above, this won't be aligned. */
4633 /* ??? If we have more than one of these, consider constructing full
4634 words in registers and using alpha_expand_unaligned_store_words. */
4636 {
4639 i++;
4640 }
4644 {
4646 i++;
4648 }
4649 else
4651 {
4653 i++;
4655 }
4658 {
4660 i++;
4662 }
4668 }
4670 int
4672 {
4680 rtx tmp;
4688 /* Look for stricter alignment. */
4695 {
4700 {
4707 }
4708 }
4710 /* Handle an unaligned prefix first. */
4713 {
4714 #if HOST_BITS_PER_WIDE_INT >= 64
4715 /* Given that alignofs is bounded by align, the only time BWX could
4716 generate three stores is for a 7 byte fill. Prefer two individual
4717 stores over a load/mask/store sequence. */
4721 {
4725 HOST_WIDE_INT mask;
4732 {
4736 }
4737 else
4738 {
4741 }
4748 }
4749 #endif
4752 {
4757 }
4759 {
4764 }
4766 {
4771 }
4773 /* If we've not used the extra lead alignment information by now,
4774 we won't be able to. Downgrade align to match what's left over. */
4776 {
4779 }
4780 }
4782 /* Handle a block of contiguous long-words. */
4785 {
4790 const0_rtx);
4794 }
4796 /* If the block is large and appropriately aligned, emit a single
4797 store followed by a sequence of stq_u insns. */
4800 {
4801 rtx orig_dsta;
4813 {
4814 rtx mem
4821 }
4823 /* Depending on the alignment, the first stq_u may have overlapped
4824 with the initial stl, which means that the last stq_u didn't
4825 write as much as it would appear. Leave those questionable bytes
4826 unaccounted for. */
4829 }
4831 /* Handle a smaller block of aligned words. */
4835 {
4840 const0_rtx);
4844 }
4846 /* An unaligned block uses stq_u stores for as many as possible. */
4849 {
4856 }
4858 /* Next clean up any trailing pieces. */
4860 #if HOST_BITS_PER_WIDE_INT >= 64
4861 /* Count the number of bits in BYTES for which aligned stores could
4862 be emitted. */
4868 /* If we have appropriate alignment (and it wouldn't take too many
4869 instructions otherwise), mask out the bytes we need. */
4871 {
4873 {
4875 HOST_WIDE_INT mask;
4887 }
4889 {
4891 HOST_WIDE_INT mask;
4903 }
4904 }
4905 #endif
4908 {
4912 }
4915 {
4917 {
4920 const0_rtx);
4924 }
4926 {
4930 }
4931 }
4934 {
4938 }
4941 }
4943 /* Returns a mask so that zap(x, value) == x & mask. */
4945 rtx
4947 {
4948 rtx result;
4952 {
4956 {
4960 }
4963 }
4965 {
4969 {
4973 }
4976 {
4980 }
4983 }
4984 else
4988 }
4990 void
4994 {
4999 else
5004 else
5008 }
5009 \f
5010 /* Adjust the cost of a scheduling dependency. Return the new cost of
5011 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5013 static int
5015 {
5018 /* If the dependence is an anti-dependence, there is no cost. For an
5019 output dependence, there is sometimes a cost, but it doesn't seem
5020 worth handling those few cases. */
5024 /* If we can't recognize the insns, we can't really do anything. */
5031 /* Bring in the user-defined memory latency. */
5037 /* Everything else handled in DFA bypasses now. */
5040 }
5042 /* The number of instructions that can be issued per cycle. */
5044 static int
5046 {
5048 }
5050 /* How many alternative schedules to try. This should be as wide as the
5051 scheduling freedom in the DFA, but no wider. Making this value too
5052 large results extra work for the scheduler.
5054 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5055 alternative schedules. For EV5, we can choose between E0/E1 and
5056 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5058 static int
5060 {
5062 }
5063 \f
5064 /* Machine-specific function data. */
5067 {
5068 /* For unicosmk. */
5069 /* List of call information words for calls from this function. */
5074 /* List of deferred case vectors. */
5077 /* For OSF. */
5080 /* For TARGET_LD_BUGGY_LDGP. */
5082 };
5084 /* How to allocate a 'struct machine_function'. */
5088 {
5091 }
5093 /* Functions to save and restore alpha_return_addr_rtx. */
5095 /* Start the ball rolling with RETURN_ADDR_RTX. */
5097 rtx
5099 {
5104 }
5106 /* Return or create a memory slot containing the gp value for the current
5107 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5109 rtx
5111 {
5115 {
5127 }
5130 }
5132 static int
5134 {
5135 rtx top;
5145 }
5147 \f
5148 /* Return the trap mode suffix applicable to the current
5149 instruction, or NULL. */
5153 {
5157 {
5173 {
5181 }
5186 {
5195 }
5200 {
5209 }
5211 }
5213 }
5215 /* Return the rounding mode suffix applicable to the current
5216 instruction, or NULL. */
5220 {
5224 {
5229 {
5238 }
5243 }
5245 }
5247 /* Locate some local-dynamic symbol still in use by this function
5248 so that we can print its name in some movdi_er_tlsldm pattern. */
5250 static int
5252 {
5257 {
5260 }
5263 }
5267 {
5268 rtx insn;
5279 }
5281 /* Print an operand. Recognize special options, documented below. */
5283 void
5285 {
5289 {
5291 /* Print the assembler name of the current function. */
5300 {
5308 }
5311 /* Generates single precision instruction suffix. */
5316 /* Generates double precision instruction suffix. */
5321 /* Generates a nop after a noreturn call at the very end of the
5322 function. */
5342 else
5347 {
5351 {
5354 }
5356 {
5359 }
5362 else
5363 {
5366 }
5370 }
5374 /* If this operand is the constant zero, write it as "$31". */
5379 else
5384 /* Similar, but for floating-point. */
5389 else
5394 /* Write the 1's complement of a constant. */
5402 /* Write 1 << C, for a constant C. */
5410 /* Write the high-order 16 bits of a constant, sign-extended. */
5418 /* Write the low-order 16 bits of a constant, sign-extended. */
5427 /* Write mask for ZAP insn. */
5429 {
5431 HOST_WIDE_INT value;
5446 }
5449 {
5457 }
5458 else
5463 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5477 /* Similar, except do it from the mask. */
5479 {
5483 {
5486 }
5488 {
5491 }
5493 {
5496 }
5498 {
5501 }
5502 }
5507 {
5510 }
5515 /* Write the constant value divided by 8 for little-endian mode or
5516 (56 - value) / 8 for big-endian mode. */
5526 WORDS_BIG_ENDIAN
5532 /* Same, except compute (64 - c) / 8 */
5543 {
5544 /* On Unicos/Mk systems: use a DEX expression if the symbol
5545 clashes with a register name. */
5549 else
5551 }
5555 /* Write out comparison name. */
5556 {
5575 else
5577 }
5581 /* Write the divide or modulus operator. */
5583 {
5599 }
5603 /* Write "_u" for unaligned access. */
5614 {
5616 {
5624 }
5625 }
5626 else
5632 }
5633 }
5635 void
5637 {
5646 {
5649 }
5652 {
5657 {
5660 {
5672 }
5675 }
5676 else
5677 {
5681 }
5692 else
5698 }
5708 #if TARGET_ABI_OPEN_VMS
5710 {
5713 }
5717 {
5722 }
5723 #endif
5725 else
5729 }
5730 \f
5731 /* Emit RTL insns to initialize the variable parts of a trampoline at
5732 TRAMP. FNADDR is an RTX for the address of the function's pure
5733 code. CXT is an RTX for the static chain value for the function.
5735 The three offset parameters are for the individual template's
5736 layout. A JMPOFS < 0 indicates that the trampoline does not
5737 contain instructions at all.
5739 We assume here that a function will be called many more times than
5740 its address is taken (e.g., it might be passed to qsort), so we
5741 take the trouble to initialize the "hint" field in the JMP insn.
5742 Note that the hint field is PC (new) + 4 * bits 13:0. */
5744 void
5747 {
5749 /* VMS really uses DImode pointers in memory at this point. */
5752 #ifdef POINTERS_EXTEND_UNSIGNED
5755 #endif
5757 /* Store function address and CXT. */
5763 /* This has been disabled since the hint only has a 32k range, and in
5764 no existing OS is the stack within 32k of the text segment. */
5766 {
5767 /* Compute hint value. */
5770 OPTAB_WIDEN);
5776 /* Merge in the hint. */
5781 OPTAB_WIDEN);
5783 }
5785 #ifdef TRANSFER_FROM_TRAMPOLINE
5788 #endif
5792 }
5793 \f
5794 /* Determine where to put an argument to a function.
5795 Value is zero to push the argument on the stack,
5796 or a hard register in which to store the argument.
5798 MODE is the argument's machine mode.
5799 TYPE is the data type of the argument (as a tree).
5800 This is null for libcalls where that information may
5801 not be available.
5802 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5803 the preceding args and about the function being called.
5804 NAMED is nonzero if this argument is a named parameter
5805 (otherwise it is an extra parameter matching an ellipsis).
5807 On Alpha the first 6 words of args are normally in registers
5808 and the rest are pushed. */
5810 rtx
5813 {
5817 /* Don't get confused and pass small structures in FP registers. */
5820 else
5821 {
5822 #ifdef ENABLE_CHECKING
5823 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5824 values here. */
5827 #endif
5829 /* Set up defaults for FP operands passed in FP registers, and
5830 integral operands passed in integer registers. */
5833 else
5835 }
5837 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5838 the three platforms, so we can't avoid conditional compilation. */
5839 #if TARGET_ABI_OPEN_VMS
5840 {
5848 }
5849 #elif TARGET_ABI_UNICOSMK
5850 {
5853 /* If this is the last argument, generate the call info word (CIW). */
5854 /* ??? We don't include the caller's line number in the CIW because
5855 I don't know how to determine it if debug infos are turned off. */
5857 {
5859 HOST_WIDE_INT lo;
5860 HOST_WIDE_INT hi;
5861 rtx ciw;
5871 else
5874 #if HOST_BITS_PER_WIDE_INT == 32
5876 #else
5880 #endif
5884 UNSPEC_UMK_LOAD_CIW);
5885 }
5894 {
5900 /* The argument fits in two registers. Note that we still need to
5901 reserve a register for empty structures. */
5906 else
5907 {
5911 }
5912 }
5913 }
5914 #elif TARGET_ABI_OSF
5915 {
5920 /* VOID is passed as a special flag for "last argument". */
5925 }
5926 #else
5927 #error Unhandled ABI
5928 #endif
5931 }
5933 /* Return true if TYPE must be returned in memory, instead of in registers. */
5935 static bool
5937 {
5942 {
5945 /* All aggregates are returned in memory. */
5948 }
5952 {
5954 /* Pass all float vectors in memory, like an aggregate. */
5958 /* We judge complex floats on the size of their element,
5959 not the size of the whole type. */
5970 /* ??? We get called on all sorts of random stuff from
5971 aggregate_value_p. We can't abort, but it's not clear
5972 what's safe to return. Pretend it's a struct I guess. */
5974 }
5976 /* Otherwise types must fit in one register. */
5978 }
5980 /* Return true if TYPE should be passed by invisible reference. */
5982 static bool
5985 tree type ATTRIBUTE_UNUSED,
5987 {
5989 }
5991 /* Define how to find the value returned by a function. VALTYPE is the
5992 data type of the value (as a tree). If the precise function being
5993 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5994 MODE is set instead of VALTYPE for libcalls.
5996 On Alpha the value is found in $0 for integer functions and
5997 $f0 for floating-point functions. */
5999 rtx
6002 {
6006 #ifdef ENABLE_CHECKING
6009 #endif
6016 {
6018 /* Do the same thing as PROMOTE_MODE. */
6020 /* FALLTHRU */
6032 {
6035 return gen_rtx_PARALLEL
6039 const0_rtx),
6042 }
6046 }
6049 }
6051 /* TCmode complex values are passed by invisible reference. We
6052 should not split these values. */
6054 static bool
6056 {
6058 }
6060 static tree
6062 {
6073 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6075 /* Dummy field to prevent alignment warnings. */
6082 integer_type_node);
6087 ptr_type_node);
6095 }
6097 /* Perform any needed actions needed for a function that is receiving a
6098 variable number of arguments. */
6100 static void
6103 tree type ATTRIBUTE_UNUSED,
6105 {
6106 #if TARGET_ABI_UNICOSMK
6107 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6108 arguments on the stack. Unfortunately, it doesn't always store the first
6109 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6110 with stdargs as we always have at least one named argument there. */
6113 {
6115 {
6118 }
6120 }
6121 #elif TARGET_ABI_OPEN_VMS
6122 /* For VMS, we allocate space for all 6 arg registers plus a count.
6124 However, if NO registers need to be saved, don't allocate any space.
6125 This is not only because we won't need the space, but because AP
6126 includes the current_pretend_args_size and we don't want to mess up
6127 any ap-relative addresses already made. */
6129 {
6131 {
6134 }
6136 }
6137 #else
6138 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6139 only push those that are remaining. However, if NO registers need to
6140 be saved, don't allocate any space. This is not only because we won't
6141 need the space, but because AP includes the current_pretend_args_size
6142 and we don't want to mess up any ap-relative addresses already made.
6144 If we are not to use the floating-point registers, save the integer
6145 registers where we would put the floating-point registers. This is
6146 not the most efficient way to implement varargs with just one register
6147 class, but it isn't worth doing anything more efficient in this rare
6148 case. */
6155 {
6157 rtx tmp;
6171 }
6173 #endif
6174 }
6176 void
6178 {
6179 HOST_WIDE_INT offset;
6188 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6189 up by 48, storing fp arg registers in the first 48 bytes, and the
6190 integer arg registers in the next 48 bytes. This is only done,
6191 however, if any integer registers need to be stored.
6193 If no integer registers need be stored, then we must subtract 48
6194 in order to account for the integer arg registers which are counted
6195 in argsize above, but which are not actually stored on the stack.
6196 Must further be careful here about structures straddling the last
6197 integer argument register; that futzes with pretend_args_size,
6198 which changes the meaning of AP. */
6202 else
6206 {
6214 }
6215 else
6216 {
6235 }
6236 }
6238 static tree
6240 {
6244 /* If the type could not be passed in registers, skip the block
6245 reserved for the registers. */
6247 {
6252 }
6259 {
6263 }
6265 {
6271 /* Copy the value into a new temporary, lest the formal temporary
6272 be reused out from under us. */
6279 }
6281 {
6290 }
6292 /* Build the final address and force that value into a temporary. */
6301 /* Update the offset field. */
6305 else
6306 {
6310 }
6317 }
6319 static tree
6321 {
6334 /* Pull the fields of the structure out into temporaries. Since we never
6335 modify the base field, we can use a formal temporary. Sign-extend the
6336 offset field so that it's the proper width for pointer arithmetic. */
6342 /* Find the value. Note that this will be a stable indirection, or
6343 a composite of stable indirections in the case of complex. */
6346 /* Stuff the offset temporary back into its field. */
6352 }
6353 \f
6354 /* Builtins. */
6356 enum alpha_builtin
6357 {
6358 ALPHA_BUILTIN_CMPBGE,
6359 ALPHA_BUILTIN_EXTBL,
6360 ALPHA_BUILTIN_EXTWL,
6361 ALPHA_BUILTIN_EXTLL,
6362 ALPHA_BUILTIN_EXTQL,
6363 ALPHA_BUILTIN_EXTWH,
6364 ALPHA_BUILTIN_EXTLH,
6365 ALPHA_BUILTIN_EXTQH,
6366 ALPHA_BUILTIN_INSBL,
6367 ALPHA_BUILTIN_INSWL,
6368 ALPHA_BUILTIN_INSLL,
6369 ALPHA_BUILTIN_INSQL,
6370 ALPHA_BUILTIN_INSWH,
6371 ALPHA_BUILTIN_INSLH,
6372 ALPHA_BUILTIN_INSQH,
6373 ALPHA_BUILTIN_MSKBL,
6374 ALPHA_BUILTIN_MSKWL,
6375 ALPHA_BUILTIN_MSKLL,
6376 ALPHA_BUILTIN_MSKQL,
6377 ALPHA_BUILTIN_MSKWH,
6378 ALPHA_BUILTIN_MSKLH,
6379 ALPHA_BUILTIN_MSKQH,
6380 ALPHA_BUILTIN_UMULH,
6381 ALPHA_BUILTIN_ZAP,
6382 ALPHA_BUILTIN_ZAPNOT,
6383 ALPHA_BUILTIN_AMASK,
6384 ALPHA_BUILTIN_IMPLVER,
6385 ALPHA_BUILTIN_RPCC,
6386 ALPHA_BUILTIN_THREAD_POINTER,
6387 ALPHA_BUILTIN_SET_THREAD_POINTER,
6389 /* TARGET_MAX */
6390 ALPHA_BUILTIN_MINUB8,
6391 ALPHA_BUILTIN_MINSB8,
6392 ALPHA_BUILTIN_MINUW4,
6393 ALPHA_BUILTIN_MINSW4,
6394 ALPHA_BUILTIN_MAXUB8,
6395 ALPHA_BUILTIN_MAXSB8,
6396 ALPHA_BUILTIN_MAXUW4,
6397 ALPHA_BUILTIN_MAXSW4,
6398 ALPHA_BUILTIN_PERR,
6399 ALPHA_BUILTIN_PKLB,
6400 ALPHA_BUILTIN_PKWB,
6401 ALPHA_BUILTIN_UNPKBL,
6402 ALPHA_BUILTIN_UNPKBW,
6404 /* TARGET_CIX */
6405 ALPHA_BUILTIN_CTTZ,
6406 ALPHA_BUILTIN_CTLZ,
6407 ALPHA_BUILTIN_CTPOP,
6409 ALPHA_BUILTIN_max
6410 };
6413 CODE_FOR_builtin_cmpbge,
6414 CODE_FOR_builtin_extbl,
6415 CODE_FOR_builtin_extwl,
6416 CODE_FOR_builtin_extll,
6417 CODE_FOR_builtin_extql,
6418 CODE_FOR_builtin_extwh,
6419 CODE_FOR_builtin_extlh,
6420 CODE_FOR_builtin_extqh,
6421 CODE_FOR_builtin_insbl,
6422 CODE_FOR_builtin_inswl,
6423 CODE_FOR_builtin_insll,
6424 CODE_FOR_builtin_insql,
6425 CODE_FOR_builtin_inswh,
6426 CODE_FOR_builtin_inslh,
6427 CODE_FOR_builtin_insqh,
6428 CODE_FOR_builtin_mskbl,
6429 CODE_FOR_builtin_mskwl,
6430 CODE_FOR_builtin_mskll,
6431 CODE_FOR_builtin_mskql,
6432 CODE_FOR_builtin_mskwh,
6433 CODE_FOR_builtin_msklh,
6434 CODE_FOR_builtin_mskqh,
6435 CODE_FOR_umuldi3_highpart,
6436 CODE_FOR_builtin_zap,
6437 CODE_FOR_builtin_zapnot,
6438 CODE_FOR_builtin_amask,
6439 CODE_FOR_builtin_implver,
6440 CODE_FOR_builtin_rpcc,
6441 CODE_FOR_load_tp,
6442 CODE_FOR_set_tp,
6444 /* TARGET_MAX */
6445 CODE_FOR_builtin_minub8,
6446 CODE_FOR_builtin_minsb8,
6447 CODE_FOR_builtin_minuw4,
6448 CODE_FOR_builtin_minsw4,
6449 CODE_FOR_builtin_maxub8,
6450 CODE_FOR_builtin_maxsb8,
6451 CODE_FOR_builtin_maxuw4,
6452 CODE_FOR_builtin_maxsw4,
6453 CODE_FOR_builtin_perr,
6454 CODE_FOR_builtin_pklb,
6455 CODE_FOR_builtin_pkwb,
6456 CODE_FOR_builtin_unpkbl,
6457 CODE_FOR_builtin_unpkbw,
6459 /* TARGET_CIX */
6460 CODE_FOR_builtin_cttz,
6461 CODE_FOR_builtin_ctlz,
6462 CODE_FOR_builtin_ctpop
6463 };
6465 struct alpha_builtin_def
6466 {
6470 };
6475 };
6486 };
6523 };
6525 static void
6527 {
6529 tree ftype;
6550 long_integer_type_node,
6568 }
6570 /* Expand an expression EXP that calls a built-in function,
6571 with result going to TARGET if that's convenient
6572 (and in mode MODE if that's convenient).
6573 SUBTARGET may be used as the target for computing one of EXP's operands.
6574 IGNORE is nonzero if the value is to be ignored. */
6576 static rtx
6578 rtx subtarget ATTRIBUTE_UNUSED,
6581 {
6582 #define MAX_ARGS 2
6601 arglist;
6603 {
6618 }
6621 {
6627 }
6630 {
6637 else
6645 }
6652 else
6654 }
6655 \f
6656 /* This page contains routines that are used to determine what the function
6657 prologue and epilogue code will do and write them out. */
6659 /* Compute the size of the save area in the stack. */
6661 /* These variables are used for communication between the following functions.
6662 They indicate various things about the current function being compiled
6663 that are used to tell what kind of prologue, epilogue and procedure
6664 descriptor to generate. */
6666 /* Nonzero if we need a stack procedure. */
6670 /* Register number (either FP or SP) that is used to unwind the frame. */
6673 /* Register number used to save FP. We need not have one for RA since
6674 we don't modify it for register procedures. This is only defined
6675 for register frame procedures. */
6678 /* Register number used to reference objects off our PV. */
6681 /* Compute register masks for saved registers. */
6683 static void
6685 {
6690 /* When outputting a thunk, we don't have valid register life info,
6691 but assemble_start_function wants to output .frame and .mask
6692 directives. */
6694 {
6698 }
6703 /* One for every register we have to save. */
6708 {
6711 else
6713 }
6715 /* We need to restore these for the handler. */
6717 {
6719 {
6724 }
6726 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6727 avoid hackery in unwind-dw2.c, we need to actively store a
6728 zero in the prologue of _Unwind_RaiseException et al. */
6730 }
6732 /* If any register spilled, then spill the return address also. */
6733 /* ??? This is required by the Digital stack unwind specification
6734 and isn't needed if we're doing Dwarf2 unwinding. */
6740 }
6742 int
6744 {
6752 {
6755 }
6756 else
6757 {
6761 sa_size++;
6762 }
6765 {
6766 /* We might not need to generate a frame if we don't make any calls
6767 (including calls to __T3E_MISMATCH if this is a vararg function),
6768 don't have any local variables which require stack slots, don't
6769 use alloca and have not determined that we need a frame for other
6770 reasons. */
6772 alpha_procedure_type
6774 || current_function_outgoing_args_size
6779 /* Always reserve space for saving callee-saved registers if we
6780 need a frame as required by the calling convention. */
6783 }
6785 {
6786 /* Start by assuming we can use a register procedure if we don't
6787 make any calls (REG_RA not used) or need to save any
6788 registers and a stack procedure if we do. */
6793 else
6796 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6797 made the final decision on stack procedure vs register procedure. */
6801 /* Decide whether to refer to objects off our PV via FP or PV.
6802 If we need FP for something else or if we receive a nonlocal
6803 goto (which expects PV to contain the value), we must use PV.
6804 Otherwise, start by assuming we can use FP. */
6806 vms_base_regno
6807 = (frame_pointer_needed
6808 || current_function_has_nonlocal_label
6813 /* If we want to copy PV into FP, we need to find some register
6814 in which to save FP. */
6827 /* Stack unwinding should be done via FP unless we use it for PV. */
6831 /* If this is a stack procedure, allow space for saving FP and RA. */
6834 }
6835 else
6836 {
6837 /* Our size must be even (multiple of 16 bytes). */
6839 sa_size++;
6840 }
6843 }
6845 /* Define the offset between two registers, one to be eliminated,
6846 and the other its replacement, at the start of a routine. */
6848 HOST_WIDE_INT
6851 {
6852 HOST_WIDE_INT ret;
6858 ;
6863 else
6867 }
6869 int
6871 {
6874 }
6876 int
6878 {
6881 }
6883 #if TARGET_ABI_OPEN_VMS
6886 {
6887 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6892 };
6894 #endif
6896 static int
6898 {
6900 }
6902 int
6904 {
6906 }
6908 static int
6910 {
6911 rtx insn;
6913 /* The GP being variable is an OSF abi thing. */
6917 /* We need the gp to load the address of __mcount. */
6921 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6925 /* The nonlocal receiver pattern assumes that the gp is valid for
6926 the nested function. Reasonable because it's almost always set
6927 correctly already. For the cases where that's wrong, make sure
6928 the nested function loads its gp on entry. */
6932 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6933 Even if we are a static function, we still need to do this in case
6934 our address is taken and passed to something like qsort. */
6948 }
6950 \f
6951 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6952 sequences. */
6954 static rtx
6956 {
6958 rtx insn;
6966 {
6969 {
6972 }
6974 }
6975 else
6976 {
6979 }
6981 }
6983 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6985 /* Write function prologue. */
6987 /* On vms we have two kinds of functions:
6989 - stack frame (PROC_STACK)
6990 these are 'normal' functions with local vars and which are
6991 calling other functions
6992 - register frame (PROC_REGISTER)
6993 keeps all data in registers, needs no stack
6995 We must pass this to the assembler so it can generate the
6996 proper pdsc (procedure descriptor)
6997 This is done with the '.pdesc' command.
6999 On not-vms, we don't really differentiate between the two, as we can
7000 simply allocate stack without saving registers. */
7002 void
7004 {
7005 /* Registers to save. */
7008 /* Stack space needed for pushing registers clobbered by us. */
7009 HOST_WIDE_INT sa_size;
7010 /* Complete stack size needed. */
7011 HOST_WIDE_INT frame_size;
7012 /* Offset from base reg to register save area. */
7013 HOST_WIDE_INT reg_offset;
7023 + frame_size
7026 /* We have to allocate space for the DSIB if we generate a frame. */
7031 else
7033 + sa_size
7039 else
7044 /* Emit an insn to reload GP, if needed. */
7046 {
7050 }
7052 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7053 the call to mcount ourselves, rather than having the linker do it
7054 magically in response to -pg. Since _mcount has special linkage,
7055 don't represent the call as a call. */
7062 /* Adjust the stack by the frame size. If the frame size is > 4096
7063 bytes, we need to be sure we probe somewhere in the first and last
7064 4096 bytes (we can probably get away without the latter test) and
7065 every 8192 bytes in between. If the frame size is > 32768, we
7066 do this in a loop. Otherwise, we generate the explicit probe
7067 instructions.
7069 Note that we are only allowed to adjust sp once in the prologue. */
7072 {
7074 {
7077 do
7083 /* We only have to do this probe if we aren't saving registers. */
7086 }
7093 }
7094 else
7095 {
7096 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7097 number of 8192 byte blocks to probe. We then probe each block
7098 in the loop and then set SP to the proper location. If the
7099 amount remaining is > 4096, we have to do one more probe if we
7100 are not saving any registers. */
7106 rtx seq;
7112 /* Because of the difficulty in emitting a new basic block this
7113 late in the compilation, generate the loop as a single insn. */
7117 {
7121 }
7124 {
7125 /* For NT stack unwind (done by 'reverse execution'), it's
7126 not OK to take the result of a loop, even though the value
7127 is already in ptr, so we reload it via a single operation
7128 and subtract it to sp.
7130 Yes, that's correct -- we have to reload the whole constant
7131 into a temporary via ldah+lda then subtract from sp. */
7140 ptr));
7141 }
7142 else
7143 {
7146 }
7148 /* This alternative is special, because the DWARF code cannot
7149 possibly intuit through the loop above. So we invent this
7150 note it looks at instead. */
7160 }
7163 {
7164 /* Cope with very large offsets to the register save area. */
7167 {
7169 HOST_WIDE_INT bias;
7173 else
7179 }
7181 /* Save regs in stack order. Beginning with VMS PV. */
7183 {
7187 }
7189 /* Save register RA next. */
7191 {
7197 }
7199 /* Now save any other registers required to be saved. */
7202 {
7207 }
7209 /* Store a zero if requested for unwinding. */
7211 {
7225 }
7229 {
7234 }
7235 }
7237 {
7238 /* The standard frame on the T3E includes space for saving registers.
7239 We just have to use it. We don't have to save the return address and
7240 the old frame pointer here - they are saved in the DSIB. */
7245 {
7247 reg_offset));
7251 }
7254 {
7256 reg_offset));
7260 }
7261 }
7264 {
7266 /* Register frame procedures save the fp.
7267 ?? Ought to have a dwarf2 save for this. */
7269 hard_frame_pointer_rtx);
7279 /* If we have to allocate space for outgoing args, do it now. */
7281 {
7282 rtx seq
7284 plus_constant
7286 - (ALPHA_ROUND
7289 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7290 if ! frame_pointer_needed. Setting the bit will change the CFA
7291 computation rule to use sp again, which would be wrong if we had
7292 frame_pointer_needed, as this means sp might move unpredictably
7293 later on.
7295 Also, note that
7296 frame_pointer_needed
7297 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7298 and
7299 current_function_outgoing_args_size != 0
7300 => alpha_procedure_type != PT_NULL,
7302 so when we are not setting the bit here, we are guaranteed to
7303 have emitted an FRP frame pointer update just before. */
7305 }
7306 }
7308 {
7309 /* If we need a frame pointer, set it from the stack pointer. */
7311 {
7314 else
7315 /* This must always be the last instruction in the
7316 prologue, thus we emit a special move + clobber. */
7319 }
7320 }
7322 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7323 the prologue, for exception handling reasons, we cannot do this for
7324 any insn that might fault. We could prevent this for mems with a
7325 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7326 have to prevent all such scheduling with a blockage.
7328 Linux, on the other hand, never bothered to implement OSF/1's
7329 exception handling, and so doesn't care about such things. Anyone
7330 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7334 }
7336 /* Output the textual info surrounding the prologue. */
7338 void
7340 tree decl ATTRIBUTE_UNUSED)
7341 {
7344 /* Stack space needed for pushing registers clobbered by us. */
7345 HOST_WIDE_INT sa_size;
7346 /* Complete stack size needed. */
7348 /* Offset from base reg to register save area. */
7349 HOST_WIDE_INT reg_offset;
7353 /* Don't emit an extern directive for functions defined in the same file. */
7355 {
7356 tree name_tree;
7359 }
7368 + frame_size
7375 else
7377 + sa_size
7383 else
7388 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7389 We have to do that before the .ent directive as we cannot switch
7390 files within procedures with native ecoff because line numbers are
7391 linked to procedure descriptors.
7392 Outputting the lineno helps debugging of one line functions as they
7393 would otherwise get no line number at all. Please note that we would
7394 like to put out last_linenum from final.c, but it is not accessible. */
7397 {
7398 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7401 #endif
7402 #ifdef ASM_OUTPUT_SOURCE_LINE
7406 #endif
7407 }
7409 /* Issue function start and label. */
7412 {
7417 /* If the function needs GP, we'll write the "..ng" label there.
7418 Otherwise, do it here. */
7420 && ! alpha_function_needs_gp
7422 {
7426 }
7427 }
7433 /* For public functions, the label must be globalized by appending an
7434 additional colon. */
7446 {
7447 /* Set flags in procedure descriptor to request IEEE-conformant
7448 math-library routines. The value we set it to is PDSC_EXC_IEEE
7449 (/usr/include/pdsc.h). */
7451 }
7453 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7457 /* Describe our frame. If the frame size is larger than an integer,
7458 print it as zero to avoid an assembler error. We won't be
7459 properly describing such a frame, but that's the best we can do. */
7461 ;
7465 vms_unwind_regno,
7467 reg_offset);
7470 (frame_pointer_needed
7473 current_function_pretend_args_size);
7475 /* Describe which registers were spilled. */
7477 ;
7479 {
7481 /* ??? Does VMS care if mask contains ra? The old code didn't
7482 set it, so I don't here. */
7488 }
7490 {
7492 {
7499 }
7504 }
7506 #if TARGET_ABI_OPEN_VMS
7507 /* Ifdef'ed cause link_section are only available then. */
7516 #endif
7517 }
7519 /* Emit the .prologue note at the scheduled end of the prologue. */
7521 static void
7523 {
7525 ;
7533 }
7535 /* Write function epilogue. */
7537 /* ??? At some point we will want to support full unwind, and so will
7538 need to mark the epilogue as well. At the moment, we just confuse
7539 dwarf2out. */
7540 #undef FRP
7541 #define FRP(exp) exp
7543 void
7545 {
7546 /* Registers to save. */
7549 /* Stack space needed for pushing registers clobbered by us. */
7550 HOST_WIDE_INT sa_size;
7551 /* Complete stack size needed. */
7552 HOST_WIDE_INT frame_size;
7553 /* Offset from base reg to register save area. */
7554 HOST_WIDE_INT reg_offset;
7558 rtx eh_ofs;
7567 + frame_size
7574 else
7576 + sa_size
7581 {
7584 else
7586 }
7587 else
7592 fp_is_frame_pointer
7600 else
7604 {
7605 /* If we have a frame pointer, restore SP from it. */
7611 /* Cope with very large offsets to the register save area. */
7613 {
7615 HOST_WIDE_INT bias;
7619 else
7626 }
7628 /* Restore registers in order, excepting a true frame pointer. */
7640 {
7643 else
7644 {
7648 }
7650 }
7657 {
7662 }
7663 }
7665 {
7666 /* Restore callee-saved general-purpose registers. */
7672 {
7674 reg_offset));
7678 }
7682 {
7684 reg_offset));
7688 }
7690 /* Restore the return address from the DSIB. */
7695 }
7698 {
7702 {
7706 }
7708 /* If the stack size is large, begin computation into a temporary
7709 register so as not to interfere with a potential fp restore,
7710 which must be consecutive with an SP restore. */
7715 {
7719 }
7721 {
7727 else
7728 {
7731 }
7733 }
7734 else
7735 {
7739 {
7740 /* We can't drop new things to memory this late, afaik,
7741 so build it up by pieces. */
7746 }
7747 }
7749 /* From now on, things must be in order. So emit blockages. */
7751 /* Restore the frame pointer. */
7753 {
7759 }
7761 {
7766 }
7768 {
7772 }
7774 /* Restore the stack pointer. */
7778 else
7781 }
7782 else
7783 {
7785 {
7789 }
7791 {
7792 /* Decrement the frame pointer if the function does not have a
7793 frame. */
7798 }
7799 }
7800 }
7801 \f
7802 /* Output the rest of the textual info surrounding the epilogue. */
7804 void
7806 {
7807 #if TARGET_ABI_OPEN_VMS
7809 #endif
7811 /* End the function. */
7813 {
7817 }
7820 /* Output jump tables and the static subroutine information block. */
7822 {
7825 }
7826 }
7828 #if TARGET_ABI_OSF
7829 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7831 In order to avoid the hordes of differences between generated code
7832 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7833 lots of code loading up large constants, generate rtl and emit it
7834 instead of going straight to text.
7836 Not sure why this idea hasn't been explored before... */
7838 static void
7841 tree function)
7842 {
7848 /* We always require a valid GP. */
7852 /* Find the "this" pointer. If the function returns a structure,
7853 the structure return pointer is in $16. */
7856 else
7859 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7860 entire constant for the add. */
7864 {
7869 }
7870 else
7871 {
7875 }
7877 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7879 {
7888 {
7891 }
7892 else
7893 {
7898 }
7901 else
7906 }
7908 /* Generate a tail call to the target function. */
7910 {
7913 }
7919 /* Run just enough of rest_of_compilation to get the insns emitted.
7920 There's not really enough bulk here to make other passes such as
7921 instruction scheduling worth while. Note that use_thunk calls
7922 assemble_start_function and assemble_end_function. */
7929 }
7931 \f
7932 /* Debugging support. */
7936 /* Count the number of sdb related labels are generated (to find block
7937 start and end boundaries). */
7941 /* Next label # for each statement. */
7945 /* Count the number of .file directives, so that .loc is up to date. */
7949 /* Name of the file containing the current function. */
7953 /* Offsets to alpha virtual arg/local debugging pointers. */
7957 \f
7958 /* Emit a new filename to a stream. */
7960 void
7962 {
7967 {
7976 }
7979 {
7984 }
7988 {
7991 else
7992 {
7996 }
8000 }
8001 }
8003 /* Emit a linenumber to a stream. */
8005 void
8007 {
8009 {
8010 /* mips-tfile doesn't understand .stabd directives. */
8014 }
8015 else
8017 }
8018 \f
8019 /* Structure to show the current status of registers and memory. */
8021 struct shadow_summary
8022 {
8028 };
8030 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8031 to the summary structure. SET is nonzero if the insn is setting the
8032 object, otherwise zero. */
8034 static void
8036 {
8044 {
8045 /* ??? Note that this case would be incorrect if the Alpha had a
8046 ZERO_EXTRACT in SET_DEST. */
8075 {
8083 {
8086 else
8088 }
8089 else
8090 {
8093 else
8095 }
8096 }
8102 else
8105 /* Find the regs used in memory address computation: */
8114 /* Handle common unary and binary ops for efficiency. */
8136 {
8151 }
8152 }
8153 }
8155 /* Ensure a sufficient number of `trapb' insns are in the code when
8156 the user requests code with a trap precision of functions or
8157 instructions.
8159 In naive mode, when the user requests a trap-precision of
8160 "instruction", a trapb is needed after every instruction that may
8161 generate a trap. This ensures that the code is resumption safe but
8162 it is also slow.
8164 When optimizations are turned on, we delay issuing a trapb as long
8165 as possible. In this context, a trap shadow is the sequence of
8166 instructions that starts with a (potentially) trap generating
8167 instruction and extends to the next trapb or call_pal instruction
8168 (but GCC never generates call_pal by itself). We can delay (and
8169 therefore sometimes omit) a trapb subject to the following
8170 conditions:
8172 (a) On entry to the trap shadow, if any Alpha register or memory
8173 location contains a value that is used as an operand value by some
8174 instruction in the trap shadow (live on entry), then no instruction
8175 in the trap shadow may modify the register or memory location.
8177 (b) Within the trap shadow, the computation of the base register
8178 for a memory load or store instruction may not involve using the
8179 result of an instruction that might generate an UNPREDICTABLE
8180 result.
8182 (c) Within the trap shadow, no register may be used more than once
8183 as a destination register. (This is to make life easier for the
8184 trap-handler.)
8186 (d) The trap shadow may not include any branch instructions. */
8188 static void
8190 {
8203 {
8205 {
8207 {
8209 exception_nesting++;
8215 exception_nesting--;
8224 }
8225 }
8227 {
8229 {
8233 }
8235 {
8237 {
8246 {
8248 /* Annoyingly, get_attr_trap will abort on these. */
8257 {
8258 /* (c) would be violated */
8260 }
8262 /* Combine shadow with summary of current insn: */
8273 {
8274 /* (a) would be violated (also takes care of (b)) */
8281 }
8291 }
8292 }
8293 else
8294 {
8295 close_shadow:
8304 }
8305 }
8306 }
8313 {
8317 }
8318 }
8319 }
8320 \f
8321 /* Alpha can only issue instruction groups simultaneously if they are
8322 suitably aligned. This is very processor-specific. */
8329 };
8340 };
8342 static enum alphaev4_pipe
8344 {
8351 {
8381 }
8382 }
8384 static enum alphaev5_pipe
8386 {
8393 {
8430 }
8431 }
8433 /* IN_USE is a mask of the slots currently filled within the insn group.
8434 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8435 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8437 LEN is, of course, the length of the group in bytes. */
8439 static rtx
8441 {
8452 {
8457 {
8459 /* Force complex instructions to start new groups. */
8463 /* If this is a completely unrecognized insn, its an asm.
8464 We don't know how long it is, so record length as -1 to
8465 signal a needed realignment. */
8468 else
8474 {
8478 }
8479 else
8485 {
8489 }
8501 }
8504 /* Haifa doesn't do well scheduling branches. */
8508 next:
8514 /* Let Haifa tell us where it thinks insn group boundaries are. */
8520 }
8522 next_and_done:
8525 done:
8529 }
8531 /* IN_USE is a mask of the slots currently filled within the insn group.
8532 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8533 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8535 LEN is, of course, the length of the group in bytes. */
8537 static rtx
8539 {
8550 {
8555 {
8557 /* Force complex instructions to start new groups. */
8561 /* If this is a completely unrecognized insn, its an asm.
8562 We don't know how long it is, so record length as -1 to
8563 signal a needed realignment. */
8566 else
8570 /* ??? Most of the places below, we would like to abort, as
8571 it would indicate an error either in Haifa, or in the
8572 scheduling description. Unfortunately, Haifa never
8573 schedules the last instruction of the BB, so we don't
8574 have an accurate TI bit to go off. */
8577 {
8581 }
8582 else
8588 {
8592 }
8604 {
8608 }
8609 else
8630 }
8633 /* Haifa doesn't do well scheduling branches. */
8634 /* ??? If this is predicted not-taken, slotting continues, except
8635 that no more IBR, FBR, or JSR insns may be slotted. */
8639 next:
8645 /* Let Haifa tell us where it thinks insn group boundaries are. */
8651 }
8653 next_and_done:
8656 done:
8660 }
8662 static rtx
8664 {
8666 rtx nop;
8669 {
8672 }
8674 {
8677 }
8679 {
8682 }
8683 else
8688 }
8690 static rtx
8692 {
8694 rtx nop;
8697 {
8700 }
8702 {
8705 }
8707 {
8710 }
8711 else
8716 }
8718 /* The instruction group alignment main loop. */
8720 static void
8724 {
8725 /* ALIGN is the known alignment for the insn group. */
8727 /* OFS is the offset of the current insn in the insn group. */
8732 /* Let shorten branches care for assigning alignments to code labels. */
8739 else
8748 {
8751 /* When we see a label, resync alignment etc. */
8753 {
8757 {
8760 }
8766 }
8768 /* Handle complex instructions special. */
8770 {
8771 /* Asms will have length < 0. This is a signal that we have
8772 lost alignment knowledge. Assume, however, that the asm
8773 will not mis-align instructions. */
8775 {
8779 }
8780 }
8782 /* If the known alignment is smaller than the recognized insn group,
8783 realign the output. */
8785 {
8793 /* Can't realign between a call and its gp reload. */
8796 {
8800 }
8801 }
8803 /* If the group won't fit in the same INT16 as the previous,
8804 we need to add padding to keep the group together. Rather
8805 than simply leaving the insn filling to the assembler, we
8806 can make use of the knowledge of what sorts of instructions
8807 were issued in the previous group to make sure that all of
8808 the added nops are really free. */
8810 {
8812 rtx where;
8814 /* Insert nops before labels, branches, and calls to truly merge
8815 the execution of the nops with the previous instruction group. */
8818 {
8820 {
8824 }
8827 }
8828 else
8831 do
8835 }
8840 }
8841 }
8842 \f
8843 /* Machine dependent reorg pass. */
8845 static void
8847 {
8851 /* Due to the number of extra trapb insns, don't bother fixing up
8852 alignment when trap precision is instruction. Moreover, we can
8853 only do our job when sched2 is run. */
8857 {
8862 }
8863 }
8864 \f
8865 #if !TARGET_ABI_UNICOSMK
8867 #ifdef HAVE_STAMP_H
8868 #include <stamp.h>
8869 #endif
8871 static void
8873 {
8874 #ifdef OBJECT_FORMAT_ELF
8875 /* If emitting dwarf2 debug information, we cannot generate a .file
8876 directive to start the file, as it will conflict with dwarf2out
8877 file numbers. So it's only useful when emitting mdebug output. */
8879 #endif
8882 #ifdef MS_STAMP
8884 #endif
8896 : (TARGET_CPU_EV5
8899 }
8900 #endif
8902 #ifdef OBJECT_FORMAT_ELF
8904 /* Switch to the section to which we should output X. The only thing
8905 special we do here is to honor small data. */
8907 static void
8910 {
8912 /* ??? Consider using mergeable sdata sections. */
8914 else
8916 }
8919 \f
8920 /* Structure to collect function names for final output in link section. */
8921 /* Note that items marked with GTY can't be ifdef'ed out. */
8927 {
8929 rtx linkage;
8932 };
8935 {
8938 links;
8939 };
8942 splay_tree alpha_links_tree;
8944 splay_tree alpha_funcs_tree;
8948 #if TARGET_ABI_OPEN_VMS
8950 /* Return the VMS argument type corresponding to MODE. */
8952 enum avms_arg_type
8954 {
8956 {
8963 }
8964 }
8966 /* Return an rtx for an integer representing the VMS Argument Information
8967 register value. */
8969 rtx
8971 {
8979 }
8980 \f
8981 /* Make (or fake) .linkage entry for function call.
8983 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8985 Return an SYMBOL_REF rtx for the linkage. */
8987 rtx
8989 {
8990 splay_tree_node node;
8994 name++;
8997 {
9002 splay_tree_compare_pointers);
9012 }
9015 {
9016 /* Is this name already defined? */
9020 {
9023 {
9024 /* Defined here but external assumed. */
9027 }
9028 else
9029 {
9030 /* Used here but unused assumed. */
9033 }
9035 }
9036 }
9037 else
9043 /* Assume external if no definition. */
9046 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9049 /* Construct a SYMBOL_REF for us to call. */
9050 {
9058 }
9064 }
9066 rtx
9068 {
9069 splay_tree_node cfunnode;
9081 {
9082 splay_tree_node lnode;
9084 /* Is this name already defined? */
9089 }
9090 else
9094 {
9103 name++;
9112 {
9115 }
9127 }
9131 else
9136 else
9138 }
9140 static int
9142 {
9149 {
9151 {
9152 /* Local and used */
9154 }
9155 else
9156 {
9157 /* External and used, request code address. */
9159 }
9160 }
9161 else
9162 {
9164 {
9165 /* Local and used, build linkage pair. */
9168 }
9169 else
9170 {
9171 /* External and used, request linkage pair. */
9173 }
9174 }
9177 }
9179 static void
9181 {
9182 splay_tree_node node;
9201 {
9203 /* splay_tree_delete (func->links); */
9204 }
9205 }
9207 /* Given a decl, a section name, and whether the decl initializer
9208 has relocs, choose attributes for the section. */
9210 #define SECTION_VMS_OVERLAY SECTION_FORGET
9211 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9212 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9214 static unsigned int
9216 {
9230 }
9232 /* Switch to an arbitrary section NAME with attributes as specified
9233 by FLAGS. ALIGN specifies any known alignment requirements for
9234 the section; 0 if the default should be used. */
9236 static void
9238 {
9252 }
9254 /* Record an element in the table of global constructors. SYMBOL is
9255 a SYMBOL_REF of the function to be called; PRIORITY is a number
9256 between 0 and MAX_INIT_PRIORITY.
9258 Differs from default_ctors_section_asm_out_constructor in that the
9259 width of the .ctors entry is always 64 bits, rather than the 32 bits
9260 used by a normal pointer. */
9262 static void
9264 {
9268 }
9270 static void
9272 {
9276 }
9277 #else
9279 rtx
9282 {
9284 }
9286 rtx
9288 tree cfundecl ATTRIBUTE_UNUSED,
9291 {
9293 }
9296 \f
9297 #if TARGET_ABI_UNICOSMK
9299 /* This evaluates to true if we do not know how to pass TYPE solely in
9300 registers. This is the case for all arguments that do not fit in two
9301 registers. */
9303 static bool
9305 {
9315 }
9317 /* Define the offset between two registers, one to be eliminated, and the
9318 other its replacement, at the start of a routine. */
9320 int
9322 {
9340 else
9342 }
9344 /* Output the module name for .ident and .end directives. We have to strip
9345 directories and add make sure that the module name starts with a letter
9346 or '$'. */
9348 static void
9350 {
9356 /* CAM only accepts module names that start with a letter or '$'. We
9357 prefix the module name with a '$' if necessary. */
9364 }
9366 /* Output the definition of a common variable. */
9368 void
9370 {
9371 tree name_tree;
9380 /* Mark the symbol as defined in this module. */
9383 }
9385 #define SECTION_PUBLIC SECTION_MACH_DEP
9386 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9389 static unsigned int
9392 {
9399 {
9406 }
9407 else
9414 }
9416 /* Generate a section name for decl and associate it with the
9417 declaration. */
9419 static void
9421 {
9433 {
9436 /* It is essential that we prefix the section name here because
9437 otherwise the section names generated for constructors and
9438 destructors confuse collect2. */
9443 }
9446 else
9447 {
9453 }
9454 }
9456 /* Switch to an arbitrary section NAME with attributes as specified
9457 by FLAGS. ALIGN specifies any known alignment requirements for
9458 the section; 0 if the default should be used. */
9460 static void
9462 {
9465 /* Close the previous section. */
9469 /* Find out what kind of section we are opening. */
9478 else
9484 else
9486 }
9488 static void
9490 {
9494 }
9496 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9497 in code sections because .align fill unused space with zeroes. */
9499 void
9501 {
9504 else
9506 }
9508 /* Add a case vector to the current function's list of deferred case
9509 vectors. Case vectors have to be put into a separate section because CAM
9510 does not allow data definitions in code sections. */
9512 void
9514 {
9520 }
9522 /* Output a case vector. */
9524 static void
9526 {
9535 {
9536 ASM_OUTPUT_ADDR_VEC_ELT
9538 }
9539 }
9541 /* Output current function's deferred case vectors. */
9543 static void
9545 {
9547 rtx t;
9555 }
9557 /* Generate the name of the SSIB section for the current function. */
9560 #define SSIB_PREFIX_LEN 7
9564 {
9565 /* This is ok since CAM won't be able to deal with names longer than that
9566 anyway. */
9570 rtx x;
9591 }
9593 /* Set up the dynamic subprogram information block (DSIB) and update the
9594 frame pointer register ($15) for subroutines which have a frame. If the
9595 subroutine doesn't have a frame, simply increment $15. */
9597 static void
9599 {
9601 {
9603 rtx mem;
9605 /* Allocate 64 bytes for the DSIB. */
9611 /* Save the return address. */
9618 /* Save the old frame pointer. */
9627 /* Store the SSIB pointer. */
9637 /* Save the CIW index. */
9645 /* Set the new frame pointer. */
9650 }
9651 else
9652 {
9653 /* Increment the frame pointer register to indicate that we do not
9654 have a frame. */
9658 }
9659 }
9661 /* Output the static subroutine information block for the current
9662 function. */
9664 static void
9666 {
9669 rtx x;
9670 rtx ciw;
9677 /* Some required stuff and the function name length. */
9682 /* Saved registers
9683 ??? We don't do that yet. */
9687 /* Function address. */
9696 /* Function name.
9697 ??? We do it the same way Cray CC does it but this could be
9698 simplified. */
9704 else
9707 /* All call information words used in the function. */
9710 {
9712 #if HOST_BITS_PER_WIDE_INT == 32
9715 #else
9717 #endif
9718 }
9719 }
9721 /* Add a call information word (CIW) to the list of the current function's
9722 CIWs and return its index.
9724 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9726 rtx
9728 {
9729 rtx node;
9735 else
9743 }
9749 {
9752 count++);
9754 }
9758 {
9761 count++);
9763 }
9765 /* The Cray assembler doesn't accept extern declarations for symbols which
9766 are defined in the same file. We have to keep track of all global
9767 symbols which are referenced and/or defined in a source file and output
9768 extern declarations for those which are referenced but not defined at
9769 the end of file. */
9771 /* List of identifiers for which an extern declaration might have to be
9772 emitted. */
9773 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9775 struct unicosmk_extern_list
9776 {
9779 };
9783 /* Output extern declarations which are required for every asm file. */
9785 static void
9787 {
9798 }
9800 /* Output extern declarations for global symbols which are have been
9801 referenced but not defined. */
9803 static void
9805 {
9809 tree name_tree;
9813 {
9814 /* We have to strip the encoding and possibly remove user_label_prefix
9815 from the identifier in order to handle -fleading-underscore and
9816 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9824 {
9829 }
9830 }
9831 }
9833 /* Record an extern. */
9835 void
9837 {
9845 }
9847 /* The Cray assembler generates incorrect code if identifiers which
9848 conflict with register names are used as instruction operands. We have
9849 to replace such identifiers with DEX expressions. */
9851 /* Structure to collect identifiers which have been replaced by DEX
9852 expressions. */
9853 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9858 };
9860 /* List of identifiers which have been replaced by DEX expressions. The DEX
9861 number is determined by the position in the list. */
9865 /* The number of elements in the DEX list. */
9869 /* Check if NAME must be replaced by a DEX expression. */
9871 static int
9873 {
9884 {
9894 }
9895 }
9897 /* Return the DEX number if X must be replaced by a DEX expression and 0
9898 otherwise. */
9900 static int
9902 {
9916 {
9920 }
9929 }
9931 /* Output the DEX definitions for this file. */
9933 static void
9935 {
9946 {
9951 }
9954 }
9956 /* Output text that to appear at the beginning of an assembler file. */
9958 static void
9960 {
9967 /* The Unicos/Mk assembler uses different register names. Instead of trying
9968 to support them, we simply use micro definitions. */
9970 /* CAM has different register names: rN for the integer register N and fN
9971 for the floating-point register N. Instead of trying to use these in
9972 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9973 register. */
9983 /* The .align directive fill unused space with zeroes which does not work
9984 in code sections. We define the macro 'gcc@code@align' which uses nops
9985 instead. Note that it assumes that code sections always have the
9986 biggest possible alignment since . refers to the current offset from
9987 the beginning of the section. */
9999 /* Output extern declarations which should always be visible. */
10002 /* Open a dummy section. We always need to be inside a section for the
10003 section-switching code to work correctly.
10004 ??? This should be a module id or something like that. I still have to
10005 figure out what the rules for those are. */
10007 }
10009 /* Output text to appear at the end of an assembler file. This includes all
10010 pending extern declarations and DEX expressions. */
10012 static void
10014 {
10017 /* Output all pending externs. */
10021 /* Output dex definitions used for functions whose names conflict with
10022 register names. */
10029 }
10031 #else
10033 static void
10035 {}
10037 static void
10039 {}
10041 static void
10044 {}
10046 rtx
10048 {
10050 }
10052 static int
10054 {
10056 }
10060 static void
10062 {
10064 {
10065 /* Prevent gcc from generating calls to __divsi3. */
10069 /* Use the functions provided by the system library
10070 for DImode integer division. */
10073 }
10075 {
10076 /* Use the VMS runtime library functions for division and
10077 remainder. */
10086 }
10087 }
10089 \f
10090 /* Initialize the GCC target structure. */
10091 #if TARGET_ABI_OPEN_VMS
10092 # undef TARGET_ATTRIBUTE_TABLE
10093 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10094 # undef TARGET_SECTION_TYPE_FLAGS
10095 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10096 #endif
10098 #undef TARGET_IN_SMALL_DATA_P
10099 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10101 #if TARGET_ABI_UNICOSMK
10102 # undef TARGET_INSERT_ATTRIBUTES
10103 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10104 # undef TARGET_SECTION_TYPE_FLAGS
10105 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10106 # undef TARGET_ASM_UNIQUE_SECTION
10107 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10108 # undef TARGET_ASM_GLOBALIZE_LABEL
10109 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10110 # undef TARGET_MUST_PASS_IN_STACK
10111 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10112 #endif
10114 #undef TARGET_ASM_ALIGNED_HI_OP
10116 #undef TARGET_ASM_ALIGNED_DI_OP
10119 /* Default unaligned ops are provided for ELF systems. To get unaligned
10120 data for non-ELF systems, we have to turn off auto alignment. */
10121 #ifndef OBJECT_FORMAT_ELF
10122 #undef TARGET_ASM_UNALIGNED_HI_OP
10124 #undef TARGET_ASM_UNALIGNED_SI_OP
10126 #undef TARGET_ASM_UNALIGNED_DI_OP
10128 #endif
10130 #ifdef OBJECT_FORMAT_ELF
10131 #undef TARGET_ASM_SELECT_RTX_SECTION
10132 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10133 #endif
10135 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10136 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10138 #undef TARGET_INIT_LIBFUNCS
10139 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10141 #if TARGET_ABI_UNICOSMK
10142 #undef TARGET_ASM_FILE_START
10143 #define TARGET_ASM_FILE_START unicosmk_file_start
10144 #undef TARGET_ASM_FILE_END
10145 #define TARGET_ASM_FILE_END unicosmk_file_end
10146 #else
10147 #undef TARGET_ASM_FILE_START
10148 #define TARGET_ASM_FILE_START alpha_file_start
10149 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10150 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10151 #endif
10153 #undef TARGET_SCHED_ADJUST_COST
10154 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10155 #undef TARGET_SCHED_ISSUE_RATE
10156 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10157 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10158 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
10159 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10160 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10161 alpha_multipass_dfa_lookahead
10163 #undef TARGET_HAVE_TLS
10164 #define TARGET_HAVE_TLS HAVE_AS_TLS
10166 #undef TARGET_INIT_BUILTINS
10167 #define TARGET_INIT_BUILTINS alpha_init_builtins
10168 #undef TARGET_EXPAND_BUILTIN
10169 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10171 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10172 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10173 #undef TARGET_CANNOT_COPY_INSN_P
10174 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10176 #if TARGET_ABI_OSF
10177 #undef TARGET_ASM_OUTPUT_MI_THUNK
10178 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10179 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10180 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10181 #endif
10183 #undef TARGET_RTX_COSTS
10184 #define TARGET_RTX_COSTS alpha_rtx_costs
10185 #undef TARGET_ADDRESS_COST
10186 #define TARGET_ADDRESS_COST hook_int_rtx_0
10188 #undef TARGET_MACHINE_DEPENDENT_REORG
10189 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10191 #undef TARGET_PROMOTE_FUNCTION_ARGS
10192 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10193 #undef TARGET_PROMOTE_FUNCTION_RETURN
10194 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10195 #undef TARGET_PROMOTE_PROTOTYPES
10196 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10197 #undef TARGET_RETURN_IN_MEMORY
10198 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10199 #undef TARGET_PASS_BY_REFERENCE
10200 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10201 #undef TARGET_SETUP_INCOMING_VARARGS
10202 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10203 #undef TARGET_STRICT_ARGUMENT_NAMING
10204 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10205 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10206 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10207 #undef TARGET_SPLIT_COMPLEX_ARG
10208 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10209 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10210 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10212 #undef TARGET_BUILD_BUILTIN_VA_LIST
10213 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10217 \f