| blob | 3609dac47151a42d4bfdd21ba94150418e0d2490 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
55 #ifndef CHECK_STACK_LIMIT
56 #define CHECK_STACK_LIMIT (-1)
57 #endif
59 /* Return index of given mode in mult and division cost tables. */
60 #define MODE_INDEX(mode) \
61 ((mode) == QImode ? 0 \
62 : (mode) == HImode ? 1 \
63 : (mode) == SImode ? 2 \
64 : (mode) == DImode ? 3 \
65 : 4)
67 /* Processor costs (relative to an add) */
68 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
69 #define COSTS_N_BYTES(N) ((N) * 2)
71 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
73 static const
96 in QImode, HImode and SImode.
97 Relative to reg-reg move (2). */
101 in SFmode, DFmode and XFmode */
103 in SFmode, DFmode and XFmode */
106 in SImode and DImode */
108 in SImode and DImode */
111 in SImode, DImode and TImode */
113 in SImode, DImode and TImode */
128 };
130 /* Processor costs (relative to an add) */
131 static const
154 in QImode, HImode and SImode.
155 Relative to reg-reg move (2). */
159 in SFmode, DFmode and XFmode */
161 in SFmode, DFmode and XFmode */
164 in SImode and DImode */
166 in SImode and DImode */
169 in SImode, DImode and TImode */
171 in SImode, DImode and TImode */
183 DUMMY_STRINGOP_ALGS},
185 DUMMY_STRINGOP_ALGS},
186 };
188 static const
211 in QImode, HImode and SImode.
212 Relative to reg-reg move (2). */
216 in SFmode, DFmode and XFmode */
218 in SFmode, DFmode and XFmode */
221 in SImode and DImode */
223 in SImode and DImode */
226 in SImode, DImode and TImode */
228 in SImode, DImode and TImode */
240 DUMMY_STRINGOP_ALGS},
242 DUMMY_STRINGOP_ALGS}
243 };
245 static const
268 in QImode, HImode and SImode.
269 Relative to reg-reg move (2). */
273 in SFmode, DFmode and XFmode */
275 in SFmode, DFmode and XFmode */
278 in SImode and DImode */
280 in SImode and DImode */
283 in SImode, DImode and TImode */
285 in SImode, DImode and TImode */
297 DUMMY_STRINGOP_ALGS},
299 DUMMY_STRINGOP_ALGS}
300 };
302 static const
325 in QImode, HImode and SImode.
326 Relative to reg-reg move (2). */
330 in SFmode, DFmode and XFmode */
332 in SFmode, DFmode and XFmode */
335 in SImode and DImode */
337 in SImode and DImode */
340 in SImode, DImode and TImode */
342 in SImode, DImode and TImode */
353 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
354 the alignment). For small blocks inline loop is still a noticeable win, for bigger
355 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
356 more expensive startup time in CPU, but after 4K the difference is down in the noise.
357 */
360 DUMMY_STRINGOP_ALGS},
363 DUMMY_STRINGOP_ALGS}
364 };
366 static const
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
394 in SFmode, DFmode and XFmode */
396 in SFmode, DFmode and XFmode */
400 in SImode and DImode */
402 in SImode and DImode */
405 in SImode, DImode and TImode */
407 in SImode, DImode and TImode */
419 DUMMY_STRINGOP_ALGS},
421 DUMMY_STRINGOP_ALGS}
422 };
424 static const
447 in QImode, HImode and SImode.
448 Relative to reg-reg move (2). */
452 in SFmode, DFmode and XFmode */
454 in SFmode, DFmode and XFmode */
457 in SImode and DImode */
459 in SImode and DImode */
462 in SImode, DImode and TImode */
464 in SImode, DImode and TImode */
476 DUMMY_STRINGOP_ALGS},
478 DUMMY_STRINGOP_ALGS}
479 };
481 static const
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
509 in SFmode, DFmode and XFmode */
511 in SFmode, DFmode and XFmode */
514 in SImode and DImode */
516 in SImode and DImode */
519 in SImode, DImode and TImode */
521 in SImode, DImode and TImode */
532 /* For some reason, Athlon deals better with REP prefix (relative to loops)
533 compared to K8. Alignment becomes important after 8 bytes for memcpy and
534 128 bytes for memset. */
536 DUMMY_STRINGOP_ALGS},
538 DUMMY_STRINGOP_ALGS}
539 };
541 static const
564 in QImode, HImode and SImode.
565 Relative to reg-reg move (2). */
569 in SFmode, DFmode and XFmode */
571 in SFmode, DFmode and XFmode */
574 in SImode and DImode */
576 in SImode and DImode */
579 in SImode, DImode and TImode */
581 in SImode, DImode and TImode */
584 /* New AMD processors never drop prefetches; if they cannot be performed
585 immediately, they are queued. We set number of simultaneous prefetches
586 to a large constant to reflect this (it probably is not a good idea not
587 to limit number of prefetches at all, as their execution also takes some
588 time). */
597 /* K8 has optimized REP instruction for medium sized blocks, but for very small
598 blocks it is better to use loop. For large blocks, libcall can do
599 nontemporary accesses and beat inline considerably. */
605 };
629 in QImode, HImode and SImode.
630 Relative to reg-reg move (2). */
634 in SFmode, DFmode and XFmode */
636 in SFmode, DFmode and XFmode */
639 in SImode and DImode */
641 in SImode and DImode */
644 in SImode, DImode and TImode */
646 in SImode, DImode and TImode */
648 /* On K8
649 MOVD reg64, xmmreg Double FSTORE 4
650 MOVD reg32, xmmreg Double FSTORE 4
651 On AMDFAM10
652 MOVD reg64, xmmreg Double FADD 3
653 1/1 1/1
654 MOVD reg32, xmmreg Double FADD 3
655 1/1 1/1 */
657 /* New AMD processors never drop prefetches; if they cannot be performed
658 immediately, they are queued. We set number of simultaneous prefetches
659 to a large constant to reflect this (it probably is not a good idea not
660 to limit number of prefetches at all, as their execution also takes some
661 time). */
671 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
672 very small blocks it is better to use loop. For large blocks, libcall can
673 do nontemporary accesses and beat inline considerably. */
679 };
681 static const
704 in QImode, HImode and SImode.
705 Relative to reg-reg move (2). */
709 in SFmode, DFmode and XFmode */
711 in SFmode, DFmode and XFmode */
714 in SImode and DImode */
716 in SImode and DImode */
719 in SImode, DImode and TImode */
721 in SImode, DImode and TImode */
733 DUMMY_STRINGOP_ALGS},
736 DUMMY_STRINGOP_ALGS},
737 };
739 static const
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
767 in SFmode, DFmode and XFmode */
769 in SFmode, DFmode and XFmode */
772 in SImode and DImode */
774 in SImode and DImode */
777 in SImode, DImode and TImode */
779 in SImode, DImode and TImode */
797 };
799 static const
822 in QImode, HImode and SImode.
823 Relative to reg-reg move (2). */
827 in SFmode, DFmode and XFmode */
831 in SImode and DImode */
833 in SImode and DImode */
836 in SImode, DImode and TImode */
838 in SImode, DImode and TImode */
856 };
858 /* Generic64 should produce code tuned for Nocona and K8. */
859 static const
862 /* On all chips taken into consideration lea is 2 cycles and more. With
863 this cost however our current implementation of synth_mult results in
864 use of unnecessary temporary registers causing regression on several
865 SPECfp benchmarks. */
886 in QImode, HImode and SImode.
887 Relative to reg-reg move (2). */
891 in SFmode, DFmode and XFmode */
893 in SFmode, DFmode and XFmode */
896 in SImode and DImode */
898 in SImode and DImode */
901 in SImode, DImode and TImode */
903 in SImode, DImode and TImode */
907 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
908 is increased to perhaps more appropriate value of 5. */
920 };
922 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
923 static const
946 in QImode, HImode and SImode.
947 Relative to reg-reg move (2). */
951 in SFmode, DFmode and XFmode */
953 in SFmode, DFmode and XFmode */
956 in SImode and DImode */
958 in SImode and DImode */
961 in SImode, DImode and TImode */
963 in SImode, DImode and TImode */
975 DUMMY_STRINGOP_ALGS},
977 DUMMY_STRINGOP_ALGS},
978 };
982 /* Processor feature/optimization bitmasks. */
983 #define m_386 (1<<PROCESSOR_I386)
984 #define m_486 (1<<PROCESSOR_I486)
985 #define m_PENT (1<<PROCESSOR_PENTIUM)
986 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
987 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
988 #define m_NOCONA (1<<PROCESSOR_NOCONA)
989 #define m_CORE2 (1<<PROCESSOR_CORE2)
991 #define m_GEODE (1<<PROCESSOR_GEODE)
992 #define m_K6 (1<<PROCESSOR_K6)
993 #define m_K6_GEODE (m_K6 | m_GEODE)
994 #define m_K8 (1<<PROCESSOR_K8)
995 #define m_ATHLON (1<<PROCESSOR_ATHLON)
996 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
997 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
998 #define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
1000 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1001 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1003 /* Generic instruction choice should be common subset of supported CPUs
1004 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1005 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1007 /* Feature tests against the various tunings. */
1009 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1010 negatively, so enabling for Generic64 seems like good code size
1011 tradeoff. We can't enable it for 32bit generic because it does not
1012 work well with PPro base chips. */
1015 /* X86_TUNE_PUSH_MEMORY */
1019 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1022 /* X86_TUNE_USE_BIT_TEST */
1023 m_386,
1025 /* X86_TUNE_UNROLL_STRLEN */
1028 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1031 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1032 on simulation result. But after P4 was made, no performance benefit
1033 was observed with branch hints. It also increases the code size.
1034 As a result, icc never generates branch hints. */
1037 /* X86_TUNE_DOUBLE_WITH_ADD */
1040 /* X86_TUNE_USE_SAHF */
1044 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1045 partial dependencies. */
1049 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1050 register stalls on Generic32 compilation setting as well. However
1051 in current implementation the partial register stalls are not eliminated
1052 very well - they can be introduced via subregs synthesized by combine
1053 and can happen in caller/callee saving sequences. Because this option
1054 pays back little on PPro based chips and is in conflict with partial reg
1055 dependencies used by Athlon/P4 based chips, it is better to leave it off
1056 for generic32 for now. */
1057 m_PPRO,
1059 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1062 /* X86_TUNE_USE_HIMODE_FIOP */
1065 /* X86_TUNE_USE_SIMODE_FIOP */
1068 /* X86_TUNE_USE_MOV0 */
1069 m_K6,
1071 /* X86_TUNE_USE_CLTD */
1074 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1075 m_PENT4,
1077 /* X86_TUNE_SPLIT_LONG_MOVES */
1078 m_PPRO,
1080 /* X86_TUNE_READ_MODIFY_WRITE */
1083 /* X86_TUNE_READ_MODIFY */
1086 /* X86_TUNE_PROMOTE_QIMODE */
1090 /* X86_TUNE_FAST_PREFIX */
1093 /* X86_TUNE_SINGLE_STRINGOP */
1096 /* X86_TUNE_QIMODE_MATH */
1099 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1100 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1101 might be considered for Generic32 if our scheme for avoiding partial
1102 stalls was more effective. */
1105 /* X86_TUNE_PROMOTE_QI_REGS */
1108 /* X86_TUNE_PROMOTE_HI_REGS */
1109 m_PPRO,
1111 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1114 /* X86_TUNE_ADD_ESP_8 */
1118 /* X86_TUNE_SUB_ESP_4 */
1121 /* X86_TUNE_SUB_ESP_8 */
1125 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1126 for DFmode copies */
1130 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1133 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1134 conflict here in between PPro/Pentium4 based chips that thread 128bit
1135 SSE registers as single units versus K8 based chips that divide SSE
1136 registers to two 64bit halves. This knob promotes all store destinations
1137 to be 128bit to allow register renaming on 128bit SSE units, but usually
1138 results in one extra microop on 64bit SSE units. Experimental results
1139 shows that disabling this option on P4 brings over 20% SPECfp regression,
1140 while enabling it on K8 brings roughly 2.4% regression that can be partly
1141 masked by careful scheduling of moves. */
1144 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1145 m_AMDFAM10,
1147 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1148 are resolved on SSE register parts instead of whole registers, so we may
1149 maintain just lower part of scalar values in proper format leaving the
1150 upper part undefined. */
1151 m_ATHLON_K8,
1153 /* X86_TUNE_SSE_TYPELESS_STORES */
1154 m_ATHLON_K8_AMDFAM10,
1156 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1159 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1162 /* X86_TUNE_PROLOGUE_USING_MOVE */
1165 /* X86_TUNE_EPILOGUE_USING_MOVE */
1168 /* X86_TUNE_SHIFT1 */
1171 /* X86_TUNE_USE_FFREEP */
1172 m_ATHLON_K8_AMDFAM10,
1174 /* X86_TUNE_INTER_UNIT_MOVES */
1177 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1178 than 4 branch instructions in the 16 byte window. */
1181 /* X86_TUNE_SCHEDULE */
1184 /* X86_TUNE_USE_BT */
1185 m_ATHLON_K8_AMDFAM10,
1187 /* X86_TUNE_USE_INCDEC */
1190 /* X86_TUNE_PAD_RETURNS */
1193 /* X86_TUNE_EXT_80387_CONSTANTS */
1196 /* X86_TUNE_SHORTEN_X87_SSE */
1199 /* X86_TUNE_AVOID_VECTOR_DECODE */
1202 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1203 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1206 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1207 vector path on AMD machines. */
1210 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1211 machines. */
1214 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1215 than a MOV. */
1216 m_PENT,
1218 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1219 but one byte longer. */
1220 m_PENT,
1222 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1223 operand that cannot be represented using a modRM byte. The XOR
1224 replacement is long decoded, so this split helps here as well. */
1225 m_K6,
1226 };
1228 /* Feature tests against the various architecture variations. */
1230 /* X86_ARCH_CMOVE */
1233 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1236 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1239 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1242 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1244 };
1246 static const unsigned int x86_accumulate_outgoing_args
1249 static const unsigned int x86_arch_always_fancy_math_387
1255 /* In case the average insn count for single function invocation is
1256 lower than this constant, emit fast (but longer) prologue and
1257 epilogue code. */
1258 #define FAST_PROLOGUE_INSN_COUNT 20
1260 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1265 /* Array of the smallest class containing reg number REGNO, indexed by
1266 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1269 {
1270 /* ax, dx, cx, bx */
1272 /* si, di, bp, sp */
1274 /* FP registers */
1277 /* arg pointer */
1278 NON_Q_REGS,
1279 /* flags, fpsr, fpcr, frame */
1289 };
1291 /* The "default" register map used in 32bit mode. */
1294 {
1302 };
1305 {
1308 };
1311 {
1314 };
1317 {
1319 };
1321 /* The "default" register map used in 64bit mode. */
1323 {
1331 };
1333 /* Define the register numbers to be used in Dwarf debugging information.
1334 The SVR4 reference port C compiler uses the following register numbers
1335 in its Dwarf output code:
1336 0 for %eax (gcc regno = 0)
1337 1 for %ecx (gcc regno = 2)
1338 2 for %edx (gcc regno = 1)
1339 3 for %ebx (gcc regno = 3)
1340 4 for %esp (gcc regno = 7)
1341 5 for %ebp (gcc regno = 6)
1342 6 for %esi (gcc regno = 4)
1343 7 for %edi (gcc regno = 5)
1344 The following three DWARF register numbers are never generated by
1345 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1346 believes these numbers have these meanings.
1347 8 for %eip (no gcc equivalent)
1348 9 for %eflags (gcc regno = 17)
1349 10 for %trapno (no gcc equivalent)
1350 It is not at all clear how we should number the FP stack registers
1351 for the x86 architecture. If the version of SDB on x86/svr4 were
1352 a bit less brain dead with respect to floating-point then we would
1353 have a precedent to follow with respect to DWARF register numbers
1354 for x86 FP registers, but the SDB on x86/svr4 is so completely
1355 broken with respect to FP registers that it is hardly worth thinking
1356 of it as something to strive for compatibility with.
1357 The version of x86/svr4 SDB I have at the moment does (partially)
1358 seem to believe that DWARF register number 11 is associated with
1359 the x86 register %st(0), but that's about all. Higher DWARF
1360 register numbers don't seem to be associated with anything in
1361 particular, and even for DWARF regno 11, SDB only seems to under-
1362 stand that it should say that a variable lives in %st(0) (when
1363 asked via an `=' command) if we said it was in DWARF regno 11,
1364 but SDB still prints garbage when asked for the value of the
1365 variable in question (via a `/' command).
1366 (Also note that the labels SDB prints for various FP stack regs
1367 when doing an `x' command are all wrong.)
1368 Note that these problems generally don't affect the native SVR4
1369 C compiler because it doesn't allow the use of -O with -g and
1370 because when it is *not* optimizing, it allocates a memory
1371 location for each floating-point variable, and the memory
1372 location is what gets described in the DWARF AT_location
1373 attribute for the variable in question.
1374 Regardless of the severe mental illness of the x86/svr4 SDB, we
1375 do something sensible here and we use the following DWARF
1376 register numbers. Note that these are all stack-top-relative
1377 numbers.
1378 11 for %st(0) (gcc regno = 8)
1379 12 for %st(1) (gcc regno = 9)
1380 13 for %st(2) (gcc regno = 10)
1381 14 for %st(3) (gcc regno = 11)
1382 15 for %st(4) (gcc regno = 12)
1383 16 for %st(5) (gcc regno = 13)
1384 17 for %st(6) (gcc regno = 14)
1385 18 for %st(7) (gcc regno = 15)
1386 */
1388 {
1396 };
1398 /* Test and compare insns in i386.md store the information needed to
1399 generate branch and scc insns here. */
1405 /* Size of the register save area. */
1406 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1408 /* Define the structure for the machine field in struct function. */
1411 {
1414 rtx rtl;
1416 };
1418 /* Structure describing stack frame layout.
1419 Stack grows downward:
1421 [arguments]
1422 <- ARG_POINTER
1423 saved pc
1425 saved frame pointer if frame_pointer_needed
1426 <- HARD_FRAME_POINTER
1427 [saved regs]
1429 [padding1] \
1430 )
1431 [va_arg registers] (
1432 > to_allocate <- FRAME_POINTER
1433 [frame] (
1434 )
1435 [padding2] /
1436 */
1437 struct ix86_frame
1438 {
1442 HOST_WIDE_INT frame;
1447 HOST_WIDE_INT to_allocate;
1448 /* The offsets relative to ARG_POINTER. */
1449 HOST_WIDE_INT frame_pointer_offset;
1450 HOST_WIDE_INT hard_frame_pointer_offset;
1451 HOST_WIDE_INT stack_pointer_offset;
1453 /* When save_regs_using_mov is set, emit prologue using
1454 move instead of push instructions. */
1456 };
1458 /* Code model option. */
1460 /* Asm dialect. */
1462 /* TLS dialects. */
1465 /* Which unit we are generating floating point math for. */
1468 /* Which cpu are we scheduling for. */
1471 /* Which instruction set architecture to use. */
1474 /* true if sse prefetch instruction is not NOOP. */
1477 /* ix86_regparm_string as a number */
1480 /* -mstackrealign option */
1484 /* Preferred alignment for stack boundary in bits. */
1487 /* Values 1-5: see jump.c */
1490 /* Variables which are this size or smaller are put in the data/bss
1491 or ldata/lbss sections. */
1495 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1499 /* Register class used for passing given 64bit part of the argument.
1500 These represent classes as documented by the PS ABI, with the exception
1501 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1502 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1504 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1505 whenever possible (upper half does contain padding). */
1506 enum x86_64_reg_class
1507 {
1508 X86_64_NO_CLASS,
1509 X86_64_INTEGER_CLASS,
1510 X86_64_INTEGERSI_CLASS,
1511 X86_64_SSE_CLASS,
1512 X86_64_SSESF_CLASS,
1513 X86_64_SSEDF_CLASS,
1514 X86_64_SSEUP_CLASS,
1515 X86_64_X87_CLASS,
1516 X86_64_X87UP_CLASS,
1517 X86_64_COMPLEX_X87_CLASS,
1518 X86_64_MEMORY_CLASS
1519 };
1521 {
1524 };
1526 #define MAX_CLASSES 4
1528 /* Table of constants used by fldpi, fldln2, etc.... */
1532 \f
1540 \f
1541 /* The svr4 ABI for the i386 says that records and unions are returned
1542 in memory. */
1543 #ifndef DEFAULT_PCC_STRUCT_RETURN
1544 #define DEFAULT_PCC_STRUCT_RETURN 1
1545 #endif
1547 /* Implement TARGET_HANDLE_OPTION. */
1549 static bool
1551 {
1553 {
1556 {
1559 }
1564 {
1567 }
1572 {
1577 }
1582 {
1585 }
1590 {
1593 }
1598 {
1601 }
1606 {
1609 }
1614 {
1617 }
1622 }
1623 }
1625 /* Sometimes certain combinations of command options do not make
1626 sense on a particular target machine. You can define a macro
1627 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1628 defined, is executed once just after all the command options have
1629 been parsed.
1631 Don't use this macro to turn on various extra optimizations for
1632 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1634 void
1636 {
1641 /* Comes from final.c -- no real reason to change it. */
1642 #define MAX_CODE_ALIGN 16
1644 static struct ptt
1645 {
1654 }
1656 {
1671 };
1674 static struct pta
1675 {
1678 const enum pta_flags
1679 {
1696 }
1698 {
1774 };
1778 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1779 SUBTARGET_OVERRIDE_OPTIONS;
1780 #endif
1782 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1783 SUBSUBTARGET_OVERRIDE_OPTIONS;
1784 #endif
1786 /* -fPIC is the default for x86_64. */
1790 /* Set the default values for switches whose default depends on TARGET_64BIT
1791 in case they weren't overwritten by command line options. */
1793 {
1794 /* Mach-O doesn't support omitting the frame pointer for now. */
1801 }
1802 else
1803 {
1810 }
1812 /* Need to check -mtune=generic first. */
1814 {
1817 /* As special support for cross compilers we read -mtune=native
1818 as -mtune=generic. With native compilers we won't see the
1819 -mtune=native, as it was changed by the driver. */
1821 {
1824 else
1826 }
1829 }
1830 else
1831 {
1835 {
1838 }
1840 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1841 need to use a sensible tune option. */
1845 {
1848 else
1850 }
1851 }
1853 {
1868 else
1870 }
1883 {
1896 else
1898 }
1899 else
1900 {
1901 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
1902 use of rip-relative addressing. This eliminates fixups that
1903 would otherwise be needed if this object is to be placed in a
1904 DLL, and is essentially just as efficient as direct addressing. */
1909 else
1911 }
1913 {
1919 else
1921 }
1931 {
1933 /* Default cpu tuning to the architecture. */
1978 }
1989 {
1992 {
1994 {
2001 }
2002 else
2005 }
2006 /* Intel CPUs have always interpreted SSE prefetch instructions as
2007 NOPs; so, we can enable SSE prefetch instructions even when
2008 -mtune (rather than -march) points us to a processor that has them.
2009 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2010 higher processors. */
2014 }
2024 else
2029 /* Arrange to set up i386_stack_locals for all functions. */
2032 /* Validate -mregparm= value. */
2034 {
2040 else
2042 }
2046 /* If the user has provided any of the -malign-* options,
2047 warn and use that value only if -falign-* is not set.
2048 Remove this code in GCC 3.2 or later. */
2050 {
2053 {
2057 else
2059 }
2060 }
2063 {
2066 {
2070 else
2072 }
2073 }
2076 {
2079 {
2083 else
2085 }
2086 }
2088 /* Default align_* from the processor table. */
2090 {
2093 }
2095 {
2098 }
2100 {
2102 }
2104 /* Validate -mbranch-cost= value, or provide default. */
2107 {
2111 else
2113 }
2115 {
2119 else
2121 }
2124 {
2131 else
2133 ix86_tls_dialect_string);
2134 }
2137 {
2141 }
2143 /* Keep nonleaf frame pointers. */
2149 /* If we're doing fast math, we don't care about comparison order
2150 wrt NaNs. This lets us use a shorter comparison sequence. */
2154 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2155 since the insns won't need emulation. */
2159 /* Likewise, if the target doesn't have a 387, or we've specified
2160 software floating point, don't use 387 inline intrinsics. */
2164 /* Turn on SSSE3 builtins for -msse4.1. */
2168 /* Turn on SSE3 builtins for -mssse3. */
2172 /* Turn on SSE3 builtins for -msse4a. */
2176 /* Turn on SSE2 builtins for -msse3. */
2180 /* Turn on SSE builtins for -msse2. */
2184 /* Turn on MMX builtins for -msse. */
2186 {
2189 }
2191 /* Turn on MMX builtins for 3Dnow. */
2195 /* Turn on POPCNT builtins for -mabm. */
2200 {
2204 /* Enable by default the SSE and MMX builtins. Do allow the user to
2205 explicitly disable any of these. In particular, disabling SSE and
2206 MMX for kernel code is extremely useful. */
2207 target_flags
2210 }
2211 else
2212 {
2213 /* i386 ABI does not specify red zone. It still makes sense to use it
2214 when programmer takes care to stack from being destroyed. */
2217 }
2219 /* Validate -mpreferred-stack-boundary= value, or provide default.
2220 The default of 128 bits is for Pentium III's SSE __m128. We can't
2221 change it because of optimize_size. Otherwise, we can't mix object
2222 files compiled with -Os and -On. */
2225 {
2230 else
2232 }
2234 /* Accept -msseregparm only if at least SSE support is enabled. */
2241 {
2245 {
2247 {
2250 }
2251 else
2253 }
2256 {
2258 {
2261 }
2263 {
2266 }
2267 else
2269 }
2270 else
2272 }
2274 /* If the i387 is disabled, then do not return values in it. */
2283 /* ??? Unwind info is not correct around the CFG unless either a frame
2284 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2285 unwind info generation to be aware of the CFG and propagating states
2286 around edges. */
2289 && flag_omit_frame_pointer
2291 {
2296 }
2298 /* For sane SSE instruction set generation we need fcomi instruction.
2299 It is safe to enable all CMOVE instructions. */
2303 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2304 {
2310 }
2312 /* When scheduling description is not available, disable scheduler pass
2313 so it won't slow down the compilation and make x87 code slower. */
2322 }
2323 \f
2324 /* Return true if this goes in large data/bss. */
2326 static bool
2328 {
2332 /* Functions are never large data. */
2337 {
2343 }
2344 else
2345 {
2348 /* If this is an incomplete type with size 0, then we can't put it
2349 in data because it might be too big when completed. */
2352 }
2355 }
2357 /* Switch to the appropriate section for output of DECL.
2358 DECL is either a `VAR_DECL' node or a constant of some sort.
2359 RELOC indicates whether forming the initial value of DECL requires
2360 link-time relocations. */
2363 ATTRIBUTE_UNUSED;
2368 {
2371 {
2375 {
2409 /* We don't split these for medium model. Place them into
2410 default sections and hope for best. */
2412 }
2414 {
2415 /* We might get called with string constants, but get_named_section
2416 doesn't like them as they are not DECLs. Also, we need to set
2417 flags in that case. */
2421 }
2422 }
2424 }
2426 /* Build up a unique section name, expressed as a
2427 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2428 RELOC indicates whether the initial value of EXP requires
2429 link-time relocations. */
2431 static void ATTRIBUTE_UNUSED
2433 {
2436 {
2438 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2442 {
2466 /* We don't split these for medium model. Place them into
2467 default sections and hope for best. */
2469 }
2471 {
2487 }
2488 }
2490 }
2492 #ifdef COMMON_ASM_OP
2493 /* This says how to output assembler code to declare an
2494 uninitialized external linkage data object.
2496 For medium model x86-64 we need to use .largecomm opcode for
2497 large objects. */
2498 void
2502 {
2506 else
2511 }
2512 #endif
2514 /* Utility function for targets to use in implementing
2515 ASM_OUTPUT_ALIGNED_BSS. */
2517 void
2521 {
2525 else
2528 #ifdef ASM_DECLARE_OBJECT_NAME
2531 #else
2532 /* Standard thing is just output label for the object. */
2536 }
2537 \f
2538 void
2540 {
2541 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2542 make the problem with not enough registers even worse. */
2543 #ifdef INSN_SCHEDULING
2546 #endif
2549 /* The Darwin libraries never set errno, so we might as well
2550 avoid calling them when that's the only reason we would. */
2553 /* The default values of these switches depend on the TARGET_64BIT
2554 that is not known at this moment. Mark these values with 2 and
2555 let user the to override these. In case there is no command line option
2556 specifying them, we will set the defaults in override_options. */
2561 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2562 SUBTARGET_OPTIMIZATION_OPTIONS;
2563 #endif
2564 }
2565 \f
2566 /* Decide whether we can make a sibling call to a function. DECL is the
2567 declaration of the function being targeted by the call and EXP is the
2568 CALL_EXPR representing the call. */
2570 static bool
2572 {
2573 tree func;
2576 /* If we are generating position-independent code, we cannot sibcall
2577 optimize any indirect call, or a direct call to a global function,
2578 as the PLT requires %ebx be live. */
2584 else
2585 {
2589 }
2591 /* Check that the return value locations are the same. Like
2592 if we are returning floats on the 80387 register stack, we cannot
2593 make a sibcall from a function that doesn't return a float to a
2594 function that does or, conversely, from a function that does return
2595 a float to a function that doesn't; the necessary stack adjustment
2596 would not be executed. This is also the place we notice
2597 differences in the return value ABI. Note that it is ok for one
2598 of the functions to have void return type as long as the return
2599 value of the other is passed in a register. */
2604 {
2607 }
2609 ;
2613 /* If this call is indirect, we'll need to be able to use a call-clobbered
2614 register for the address of the target function. Make sure that all
2615 such registers are not used for passing parameters. */
2617 {
2618 tree type;
2620 /* We're looking at the CALL_EXPR, we need the type of the function. */
2626 {
2627 /* ??? Need to count the actual number of registers to be used,
2628 not the possible number of registers. Fix later. */
2630 }
2631 }
2633 /* Dllimport'd functions are also called indirectly. */
2639 /* If we forced aligned the stack, then sibcalling would unalign the
2640 stack, which may break the called function. */
2644 /* Otherwise okay. That also includes certain types of indirect calls. */
2646 }
2648 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2649 calling convention attributes;
2650 arguments as in struct attribute_spec.handler. */
2652 static tree
2654 tree args,
2657 {
2662 {
2667 }
2669 /* Can combine regparm with all attributes but fastcall. */
2671 {
2672 tree cst;
2675 {
2677 }
2681 {
2686 }
2688 {
2692 }
2698 {
2701 }
2704 }
2707 {
2708 /* Do not warn when emulating the MS ABI. */
2714 }
2716 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2718 {
2720 {
2722 }
2724 {
2726 }
2728 {
2730 }
2731 }
2733 /* Can combine stdcall with fastcall (redundant), regparm and
2734 sseregparm. */
2736 {
2738 {
2740 }
2742 {
2744 }
2745 }
2747 /* Can combine cdecl with regparm and sseregparm. */
2749 {
2751 {
2753 }
2755 {
2757 }
2758 }
2760 /* Can combine sseregparm with all attributes. */
2763 }
2765 /* Return 0 if the attributes for two types are incompatible, 1 if they
2766 are compatible, and 2 if they are nearly compatible (which causes a
2767 warning to be generated). */
2769 static int
2771 {
2772 /* Check for mismatch of non-default calling convention. */
2778 /* Check for mismatched fastcall/regparm types. */
2785 /* Check for mismatched sseregparm types. */
2790 /* Check for mismatched return types (cdecl vs stdcall). */
2796 }
2797 \f
2798 /* Return the regparm value for a function with the indicated TYPE and DECL.
2799 DECL may be NULL when calling function indirectly
2800 or considering a libcall. */
2802 static int
2804 {
2805 tree attr;
2818 /* Use register calling convention for local functions when possible. */
2821 {
2824 {
2828 /* Make sure no regparm register is taken by a
2829 global register variable. */
2834 /* We can't use regparm(3) for nested functions as these use
2835 static chain pointer in third argument. */
2841 /* If the function realigns its stackpointer, the prologue will
2842 clobber %ecx. If we've already generated code for the callee,
2843 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
2844 scanning the attributes for the self-realigning property. */
2852 /* Each global register variable increases register preassure,
2853 so the more global reg vars there are, the smaller regparm
2854 optimization use, unless requested by the user explicitly. */
2857 globals++;
2858 local_regparm
2863 }
2864 }
2867 }
2869 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
2870 DFmode (2) arguments in SSE registers for a function with the
2871 indicated TYPE and DECL. DECL may be NULL when calling function
2872 indirectly or considering a libcall. Otherwise return 0. */
2874 static int
2876 {
2879 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2880 by the sseregparm attribute. */
2883 {
2885 {
2889 else
2893 }
2896 }
2898 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
2899 (and DFmode for SSE2) arguments in SSE registers. */
2901 {
2905 }
2908 }
2910 /* Return true if EAX is live at the start of the function. Used by
2911 ix86_expand_prologue to determine if we need special help before
2912 calling allocate_stack_worker. */
2914 static bool
2916 {
2917 /* Cheat. Don't bother working forward from ix86_function_regparm
2918 to the function type to whether an actual argument is located in
2919 eax. Instead just look at cfg info, which is still close enough
2920 to correct at this point. This gives false positives for broken
2921 functions that might use uninitialized data that happens to be
2922 allocated in eax, but who cares? */
2924 }
2926 /* Return true if TYPE has a variable argument list. */
2928 static bool
2930 {
2940 }
2942 /* Value is the number of bytes of arguments automatically
2943 popped when returning from a subroutine call.
2944 FUNDECL is the declaration node of the function (as a tree),
2945 FUNTYPE is the data type of the function (as a tree),
2946 or for a library call it is an identifier node for the subroutine name.
2947 SIZE is the number of bytes of arguments passed on the stack.
2949 On the 80386, the RTD insn may be used to pop them if the number
2950 of args is fixed, but if the number is variable then the caller
2951 must pop them all. RTD can't be used for library calls now
2952 because the library is compiled with the Unix compiler.
2953 Use of RTD is a selectable option, since it is incompatible with
2954 standard Unix calling sequences. If the option is not selected,
2955 the caller must always pop the args.
2957 The attribute stdcall is equivalent to RTD on a per module basis. */
2959 int
2961 {
2964 /* None of the 64-bit ABIs pop arguments. */
2970 /* Cdecl functions override -mrtd, and never pop the stack. */
2972 {
2973 /* Stdcall and fastcall functions will pop the stack if not
2974 variable args. */
2981 }
2983 /* Lose any fake structure return argument if it is passed on the stack. */
2986 {
2990 }
2993 }
2994 \f
2995 /* Argument support functions. */
2997 /* Return true when register may be used to pass function parameters. */
2998 bool
3000 {
3005 {
3009 else
3015 }
3018 {
3021 }
3022 else
3023 {
3027 }
3029 /* RAX is used as hidden argument to va_arg functions. */
3035 else
3041 }
3043 /* Return if we do not know how to pass TYPE solely in registers. */
3045 static bool
3047 {
3051 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3052 The layout_type routine is crafty and tries to trick us into passing
3053 currently unsupported vector types on the stack by using TImode. */
3056 }
3058 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3059 for a call to a function whose data type is FNTYPE.
3060 For a library call, FNTYPE is 0. */
3062 void
3066 tree fndecl)
3067 {
3070 /* Set up the number of registers to use for passing arguments. */
3084 {
3085 /* If there are variable arguments, then we won't pass anything
3086 in registers in 32-bit mode. */
3088 {
3095 }
3097 /* Use ecx and edx registers if function has fastcall attribute,
3098 else look for regparm information. */
3100 {
3102 {
3105 }
3106 else
3108 }
3110 /* Set up the number of SSE registers used for passing SFmode
3111 and DFmode arguments. Warn for mismatching ABI. */
3113 }
3114 }
3116 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3117 But in the case of vector types, it is some vector mode.
3119 When we have only some of our vector isa extensions enabled, then there
3120 are some modes for which vector_mode_supported_p is false. For these
3121 modes, the generic vector support in gcc will choose some non-vector mode
3122 in order to implement the type. By computing the natural mode, we'll
3123 select the proper ABI location for the operand and not depend on whatever
3124 the middle-end decides to do with these vector types. */
3126 static enum machine_mode
3128 {
3132 {
3135 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3137 {
3142 else
3145 /* Get the mode which has this inner mode and number of units. */
3152 }
3153 }
3156 }
3158 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3159 this may not agree with the mode that the type system has chosen for the
3160 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3161 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3163 static rtx
3166 {
3167 rtx tmp;
3171 else
3172 {
3176 }
3179 }
3181 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3182 of this code is to classify each 8bytes of incoming argument by the register
3183 class and assign registers accordingly. */
3185 /* Return the union class of CLASS1 and CLASS2.
3186 See the x86-64 PS ABI for details. */
3188 static enum x86_64_reg_class
3190 {
3191 /* Rule #1: If both classes are equal, this is the resulting class. */
3195 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3196 the other class. */
3202 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3206 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3214 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3215 MEMORY is used. */
3224 /* Rule #6: Otherwise class SSE is used. */
3226 }
3228 /* Classify the argument of type TYPE and mode MODE.
3229 CLASSES will be filled by the register class used to pass each word
3230 of the operand. The number of words is returned. In case the parameter
3231 should be passed in memory, 0 is returned. As a special case for zero
3232 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3234 BIT_OFFSET is used internally for handling records and specifies offset
3235 of the offset in bits modulo 256 to avoid overflow cases.
3237 See the x86-64 PS ABI for details.
3238 */
3240 static int
3243 {
3244 HOST_WIDE_INT bytes =
3248 /* Variable sized entities are always passed/returned in memory. */
3257 {
3259 tree field;
3262 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3269 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3270 signalize memory class, so handle it as special case. */
3272 {
3275 }
3277 /* Classify each field of record and merge classes. */
3279 {
3281 /* And now merge the fields of structure. */
3283 {
3285 {
3291 /* Bitfields are always classified as integer. Handle them
3292 early, since later code would consider them to be
3293 misaligned integers. */
3295 {
3303 }
3304 else
3305 {
3313 {
3318 }
3319 }
3320 }
3321 }
3325 /* Arrays are handled as small records. */
3326 {
3333 /* The partial classes are now full classes. */
3343 }
3346 /* Unions are similar to RECORD_TYPE but offset is always 0.
3347 */
3349 {
3351 {
3359 bit_offset);
3364 }
3365 }
3370 }
3372 /* Final merger cleanup. */
3374 {
3375 /* If one class is MEMORY, everything should be passed in
3376 memory. */
3380 /* The X86_64_SSEUP_CLASS should be always preceded by
3381 X86_64_SSE_CLASS. */
3386 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3390 }
3392 }
3394 /* Compute alignment needed. We align all types to natural boundaries with
3395 exception of XFmode that is aligned to 64bits. */
3397 {
3406 /* Misaligned fields are always returned in memory. */
3409 }
3411 /* for V1xx modes, just use the base mode */
3416 /* Classification of atomic types. */
3418 {
3436 else
3448 else
3473 /* This modes is larger than 16 bytes. */
3503 else
3507 }
3508 }
3510 /* Examine the argument and return set number of register required in each
3511 class. Return 0 iff parameter should be passed in memory. */
3512 static int
3515 {
3525 {
3547 }
3549 }
3551 /* Construct container for the argument used by GCC interface. See
3552 FUNCTION_ARG for the detailed description. */
3554 static rtx
3558 {
3559 /* The following variables hold the static issued_error state. */
3573 rtx ret;
3584 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3585 some less clueful developer tries to use floating-point anyway. */
3587 {
3589 {
3591 {
3594 }
3595 }
3597 {
3600 }
3602 }
3604 /* Likewise, error if the ABI requires us to return values in the
3605 x87 registers and the user specified -mno-80387. */
3611 {
3613 {
3616 }
3618 }
3620 /* First construct simple cases. Avoid SCmode, since we want to use
3621 single register to pass this type. */
3624 {
3636 /* Zero sized array, struct or class. */
3640 }
3654 /* Otherwise figure out the entries of the PARALLEL. */
3656 {
3658 {
3663 /* Merge TImodes on aligned occasions here too. */
3668 else
3670 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3676 intreg++;
3683 sse_regno++;
3690 sse_regno++;
3695 else
3702 i++;
3703 sse_regno++;
3707 }
3708 }
3710 /* Empty aligned struct, union or class. */
3718 }
3720 /* Update the data in CUM to advance over an argument of mode MODE
3721 and data type TYPE. (TYPE is null for libcalls where that information
3722 may not be available.) */
3724 static void
3727 {
3729 {
3736 /* FALLTHRU */
3747 {
3750 }
3759 /* FALLTHRU */
3769 {
3774 {
3777 }
3778 }
3786 {
3791 {
3794 }
3795 }
3797 }
3798 }
3800 static void
3803 {
3809 {
3814 }
3815 else
3817 }
3819 static void
3821 HOST_WIDE_INT words)
3822 {
3823 /* Otherwise, this should be passed indirect. */
3828 {
3831 }
3832 }
3834 void
3837 {
3842 else
3853 else
3855 }
3857 /* Define where to put the arguments to a function.
3858 Value is zero to push the argument on the stack,
3859 or a hard register in which to store the argument.
3861 MODE is the argument's machine mode.
3862 TYPE is the data type of the argument (as a tree).
3863 This is null for libcalls where that information may
3864 not be available.
3865 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3866 the preceding args and about the function being called.
3867 NAMED is nonzero if this argument is a named parameter
3868 (otherwise it is an extra parameter matching an ellipsis). */
3870 static rtx
3874 {
3877 /* Avoid the AL settings for the Unix64 ABI. */
3882 {
3889 /* FALLTHRU */
3895 {
3898 /* Fastcall allocates the first two DWORD (SImode) or
3899 smaller arguments to ECX and EDX. */
3901 {
3905 /* ECX not EAX is the first allocated register. */
3908 }
3910 }
3919 /* FALLTHRU */
3928 {
3930 {
3934 }
3938 }
3946 {
3948 {
3952 }
3956 }
3958 }
3961 }
3963 static rtx
3966 {
3967 /* Handle a hidden AL argument containing number of registers
3968 for varargs x86-64 functions. */
3972 ? SSE_REGPARM_MAX
3980 }
3982 static rtx
3985 {
3988 /* Avoid the AL settings for the Unix64 ABI. */
3992 /* If we've run out of registers, it goes on the stack. */
3998 /* Only floating point modes are passed in anything but integer regs. */
4000 {
4003 else
4004 {
4007 /* Unnamed floating parameters are passed in both the
4008 SSE and integer registers. */
4014 }
4015 }
4018 }
4020 rtx
4023 {
4029 else
4033 /* To simplify the code below, represent vector types with a vector mode
4034 even if MMX/SSE are not active. */
4042 else
4044 }
4046 /* A C expression that indicates when an argument must be passed by
4047 reference. If nonzero for an argument, a copy of that argument is
4048 made in memory and a pointer to the argument is passed instead of
4049 the argument itself. The pointer is passed in whatever way is
4050 appropriate for passing a pointer to that type. */
4052 static bool
4056 {
4058 {
4060 {
4061 /* Arrays are passed by reference. */
4066 {
4067 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4068 are passed by reference. */
4071 }
4072 }
4074 /* __m128 is passed by reference. */
4075 /* ??? How to handle complex? For now treat them as structs,
4076 and pass them by reference if they're too large. */
4079 }
4084 }
4086 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4087 ABI. Only called if TARGET_SSE. */
4088 static bool
4090 {
4099 {
4100 /* Walk the aggregates recursively. */
4102 {
4106 {
4107 tree field;
4109 /* Walk all the structure fields. */
4111 {
4115 }
4117 }
4120 /* Just for use if some languages passes arrays by value. */
4127 }
4128 }
4130 }
4132 /* Gives the alignment boundary, in bits, of an argument with the
4133 specified mode and type. */
4135 int
4137 {
4141 else
4146 {
4147 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4148 make an exception for SSE modes since these require 128bit
4149 alignment.
4151 The handling here differs from field_alignment. ICC aligns MMX
4152 arguments to 4 byte boundaries, while structure fields are aligned
4153 to 8 byte boundaries. */
4157 {
4160 }
4161 else
4162 {
4165 }
4166 }
4170 }
4172 /* Return true if N is a possible register number of function value. */
4174 bool
4176 {
4178 {
4194 }
4197 }
4199 /* Define how to find the value returned by a function.
4200 VALTYPE is the data type of the value (as a tree).
4201 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4202 otherwise, FUNC is 0. */
4204 static rtx
4207 {
4210 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4211 we normally prevent this case when mmx is not available. However
4212 some ABIs may require the result to be returned like DImode. */
4216 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4217 we prevent this case when sse is not available. However some ABIs
4218 may require the result to be returned like integer TImode. */
4223 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4226 else
4227 /* Most things go in %eax. */
4230 /* Override FP return register with %xmm0 for local functions when
4231 SSE math is enabled or for functions with sseregparm attribute. */
4233 {
4238 }
4241 }
4243 static rtx
4245 tree valtype)
4246 {
4247 rtx ret;
4249 /* Handle libcalls, which don't provide a type node. */
4251 {
4253 {
4270 }
4271 }
4277 /* For zero sized structures, construct_container returns NULL, but we
4278 need to keep rest of compiler happy by returning meaningful value. */
4283 }
4285 static rtx
4287 {
4291 {
4296 }
4299 }
4301 static rtx
4304 {
4316 else
4318 }
4320 static rtx
4323 {
4329 }
4331 rtx
4333 {
4335 }
4337 /* Return true iff type is returned in memory. */
4339 static int
4341 {
4342 HOST_WIDE_INT size;
4353 {
4354 /* User-created vectors small enough to fit in EAX. */
4358 /* MMX/3dNow values are returned in MM0,
4359 except when it doesn't exits. */
4363 /* SSE values are returned in XMM0, except when it doesn't exist. */
4366 }
4377 }
4379 static int
4381 {
4384 }
4386 static int
4388 {
4391 /* __m128 and friends are returned in xmm0. */
4395 /* Otherwise, the size must be exactly in [1248]. */
4397 }
4399 int
4401 {
4408 else
4410 }
4412 /* Return false iff TYPE is returned in memory. This version is used
4413 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4414 but differs notably in that when MMX is available, 8-byte vectors
4415 are returned in memory, rather than in MMX registers. */
4417 int
4419 {
4432 {
4433 /* Return in memory only if MMX registers *are* available. This
4434 seems backwards, but it is consistent with the existing
4435 Solaris x86 ABI. */
4440 }
4447 }
4449 /* When returning SSE vector types, we have a choice of either
4450 (1) being abi incompatible with a -march switch, or
4451 (2) generating an error.
4452 Given no good solution, I think the safest thing is one warning.
4453 The user won't be able to use -Werror, but....
4455 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4456 called in response to actually generating a caller or callee that
4457 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4458 via aggregate_value_p for general type probing from tree-ssa. */
4460 static rtx
4462 {
4466 {
4467 /* Look at the return type of the function, not the function type. */
4471 {
4474 {
4478 }
4479 }
4482 {
4484 {
4488 }
4489 }
4490 }
4493 }
4495 \f
4496 /* Create the va_list data type. */
4498 static tree
4500 {
4503 /* For i386 we use plain pointer to argument area. */
4511 unsigned_type_node);
4513 unsigned_type_node);
4515 ptr_type_node);
4517 ptr_type_node);
4536 /* The correct type is an array type of one element. */
4538 }
4540 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4542 static void
4544 {
4546 rtx label;
4547 rtx label_ref;
4548 rtx tmp_reg;
4549 rtx nsse_reg;
4556 /* Indicate to allocate space on the stack for varargs save area. */
4564 i < ix86_regparm
4566 i++)
4567 {
4574 }
4577 {
4578 /* Now emit code to save SSE registers. The AX parameter contains number
4579 of SSE parameter registers used to call this function. We use
4580 sse_prologue_save insn template that produces computed jump across
4581 SSE saves. We need some preparation work to get this working. */
4586 /* Compute address to jump to :
4587 label - 5*eax + nnamed_sse_arguments*5 */
4595 emit_move_insn
4599 label_ref,
4601 else
4605 /* Compute address of memory block we save into. We always use pointer
4606 pointing 127 bytes after first byte to store - this is needed to keep
4607 instruction size limited by 4 bytes. */
4617 /* And finally do the dirty job! */
4620 }
4621 }
4623 static void
4625 {
4630 {
4641 }
4642 }
4644 static void
4648 {
4649 CUMULATIVE_ARGS next_cum;
4650 tree fntype;
4653 /* This argument doesn't appear to be used anymore. Which is good,
4654 because the old code here didn't suppress rtl generation. */
4665 /* For varargs, we do not want to skip the dummy va_dcl argument.
4666 For stdargs, we do want to skip the last named argument. */
4673 else
4675 }
4677 /* Implement va_start. */
4679 void
4681 {
4685 tree type;
4687 /* Only 64bit target needs something special. */
4689 {
4692 }
4705 /* Count number of gp and fp argument registers used. */
4711 {
4717 }
4720 {
4726 }
4728 /* Find the overflow area. */
4739 {
4740 /* Find the register save area.
4741 Prologue of the function save it right above stack frame. */
4747 }
4748 }
4750 /* Implement va_arg. */
4752 static tree
4754 {
4761 rtx container;
4763 tree ptrtype;
4766 /* Only 64bit target needs something special. */
4791 /* Pull the value out of the saved registers. */
4797 {
4811 /* In case we are passing structure, verify that it is consecutive block
4812 on the register save area. If not we need to do moves. */
4814 {
4815 /* Verify that all registers are strictly consecutive */
4817 {
4821 {
4826 }
4827 }
4828 else
4829 {
4833 {
4838 }
4839 }
4840 }
4842 {
4845 }
4846 else
4847 {
4852 }
4854 /* First ensure that we fit completely in registers. */
4856 {
4863 }
4865 {
4873 }
4875 /* Compute index to start of area used for integer regs. */
4877 {
4878 /* int_addr = gpr + sav; */
4883 }
4885 {
4886 /* sse_addr = fpr + sav; */
4891 }
4893 {
4897 /* addr = &temp; */
4903 {
4914 {
4917 }
4918 else
4919 {
4922 }
4935 }
4936 }
4939 {
4944 }
4946 {
4951 }
4958 }
4960 /* ... otherwise out of the overflow area. */
4962 /* Care for on-stack alignment if needed. */
4966 else
4967 {
4973 }
4985 {
4988 }
4996 }
4997 \f
4998 /* Return nonzero if OPNUM's MEM should be matched
4999 in movabs* patterns. */
5001 int
5003 {
5015 }
5016 \f
5017 /* Initialize the table of extra 80387 mathematical constants. */
5019 static void
5021 {
5023 {
5029 };
5033 {
5035 /* Ensure each constant is rounded to XFmode precision. */
5038 }
5041 }
5043 /* Return true if the constant is something that can be loaded with
5044 a special instruction. */
5046 int
5048 {
5051 REAL_VALUE_TYPE r;
5063 /* For XFmode constants, try to find a special 80387 instruction when
5064 optimizing for size or on those CPUs that benefit from them. */
5067 {
5076 }
5078 /* Load of the constant -0.0 or -1.0 will be split as
5079 fldz;fchs or fld1;fchs sequence. */
5086 }
5088 /* Return the opcode of the special instruction to be used to load
5089 the constant X. */
5093 {
5095 {
5115 }
5116 }
5118 /* Return the CONST_DOUBLE representing the 80387 constant that is
5119 loaded by the specified special instruction. The argument IDX
5120 matches the return value from standard_80387_constant_p. */
5122 rtx
5124 {
5131 {
5142 }
5145 XFmode);
5146 }
5148 /* Return 1 if mode is a valid mode for sse. */
5149 static int
5151 {
5153 {
5164 }
5165 }
5167 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5168 */
5169 int
5171 {
5181 }
5183 /* Return the opcode of the special instruction to be used to load
5184 the constant X. */
5188 {
5190 {
5196 else
5200 }
5202 }
5204 /* Returns 1 if OP contains a symbol reference */
5206 int
5208 {
5217 {
5219 {
5225 }
5229 }
5232 }
5234 /* Return 1 if it is appropriate to emit `ret' instructions in the
5235 body of a function. Do this only if the epilogue is simple, needing a
5236 couple of insns. Prior to reloading, we can't tell how many registers
5237 must be saved, so return 0 then. Return 0 if there is no frame
5238 marker to de-allocate. */
5240 int
5242 {
5248 /* Don't allow more than 32 pop, since that's all we can do
5249 with one instruction. */
5256 }
5257 \f
5258 /* Value should be nonzero if functions must have frame pointers.
5259 Zero means the frame pointer need not be set up (and parms may
5260 be accessed via the stack pointer) in functions that seem suitable. */
5262 int
5264 {
5265 /* If we accessed previous frames, then the generated code expects
5266 to be able to access the saved ebp value in our frame. */
5270 /* Several x86 os'es need a frame pointer for other reasons,
5271 usually pertaining to setjmp. */
5275 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5276 the frame pointer by default. Turn it back on now if we've not
5277 got a leaf function. */
5279 && (!current_function_is_leaf
5287 }
5289 /* Record that the current function accesses previous call frames. */
5291 void
5293 {
5295 }
5296 \f
5297 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5298 # define USE_HIDDEN_LINKONCE 1
5299 #else
5300 # define USE_HIDDEN_LINKONCE 0
5301 #endif
5305 /* Fills in the label name that should be used for a pc thunk for
5306 the given register. */
5308 static void
5310 {
5315 else
5317 }
5320 /* This function generates code for -fpic that loads %ebx with
5321 the return address of the caller and then returns. */
5323 void
5325 {
5330 {
5338 #if TARGET_MACHO
5340 {
5348 }
5349 else
5350 #endif
5352 {
5353 tree decl;
5356 error_mark_node);
5369 }
5370 else
5371 {
5374 }
5380 }
5384 }
5386 /* Emit code for the SET_GOT patterns. */
5390 {
5396 {
5397 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5402 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5403 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5404 an unadorned address. */
5409 }
5414 {
5419 else
5422 #if TARGET_MACHO
5423 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5424 is what will be referenced by the Mach-O PIC subsystem. */
5427 #endif
5434 }
5435 else
5436 {
5444 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5445 is what will be referenced by the Mach-O PIC subsystem. */
5446 #if TARGET_MACHO
5449 else
5452 #endif
5453 }
5460 else
5464 }
5466 /* Generate an "push" pattern for input ARG. */
5468 static rtx
5470 {
5474 stack_pointer_rtx)),
5475 arg);
5476 }
5478 /* Return >= 0 if there is an unused call-clobbered register available
5479 for the entire function. */
5481 static unsigned int
5483 {
5486 {
5491 }
5494 }
5496 /* Return 1 if we need to save REGNO. */
5497 static int
5499 {
5503 || current_function_profile
5504 || current_function_calls_eh_return
5506 {
5510 }
5513 {
5516 {
5522 }
5523 }
5533 }
5535 /* Return number of registers to be saved on the stack. */
5537 static int
5539 {
5545 nregs++;
5547 }
5549 /* Return the offset between two registers, one to be eliminated, and the other
5550 its replacement, at the start of a routine. */
5552 HOST_WIDE_INT
5554 {
5563 else
5564 {
5572 }
5573 }
5575 /* Fill structure ix86_frame about frame of currently computed function. */
5577 static void
5579 {
5580 HOST_WIDE_INT total_size;
5582 HOST_WIDE_INT offset;
5592 /* During reload iteration the amount of registers saved can change.
5593 Recompute the value as needed. Do not recompute when amount of registers
5594 didn't change as reload does multiple calls to the function and does not
5595 expect the decision to change within single iteration. */
5598 {
5602 /* The fast prologue uses move instead of push to save registers. This
5603 is significantly longer, but also executes faster as modern hardware
5604 can execute the moves in parallel, but can't do that for push/pop.
5606 Be careful about choosing what prologue to emit: When function takes
5607 many instructions to execute we may use slow version as well as in
5608 case function is known to be outside hot spot (this is known with
5609 feedback only). Weight the size of function by number of registers
5610 to save as it is cheap to use one or two push instructions but very
5611 slow to use many of them. */
5615 || (flag_branch_probabilities
5618 else
5621 }
5625 else
5629 /* Skip return address and saved base pointer. */
5634 /* Do some sanity checking of stack_alignment_needed and
5635 preferred_alignment, since i386 port is the only using those features
5636 that may break easily. */
5647 /* Register save area */
5650 /* Va-arg area */
5652 {
5655 }
5656 else
5659 /* Align start of frame for local function. */
5665 /* Frame pointer points here. */
5670 /* Add outgoing arguments area. Can be skipped if we eliminated
5671 all the function calls as dead code.
5672 Skipping is however impossible when function calls alloca. Alloca
5673 expander assumes that last current_function_outgoing_args_size
5674 of stack frame are unused. */
5678 {
5681 }
5682 else
5685 /* Align stack boundary. Only needed if we're calling another function
5686 or using alloca. */
5691 else
5696 /* We've reached end of stack frame. */
5699 /* Size prologue needs to allocate. */
5709 && current_function_is_leaf
5711 {
5717 }
5718 else
5722 #if 0
5738 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
5739 #endif
5740 }
5742 /* Emit code to save registers in the prologue. */
5744 static void
5746 {
5748 rtx insn;
5752 {
5755 }
5756 }
5758 /* Emit code to save registers using MOV insns. First register
5759 is restored from POINTER + OFFSET. */
5760 static void
5762 {
5764 rtx insn;
5768 {
5774 }
5775 }
5777 /* Expand prologue or epilogue stack adjustment.
5778 The pattern exist to put a dependency on all ebp-based memory accesses.
5779 STYLE should be negative if instructions should be marked as frame related,
5780 zero if %r11 register is live and cannot be freely used and positive
5781 otherwise. */
5783 static void
5785 {
5786 rtx insn;
5792 else
5793 {
5794 rtx r11;
5795 /* r11 is used by indirect sibcall return as well, set before the
5796 epilogue and used after the epilogue. ATM indirect sibcall
5797 shouldn't be used together with huge frame sizes in one
5798 function because of the frame_size check in sibcall.c. */
5805 offset));
5806 }
5809 }
5811 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5813 static rtx
5815 {
5823 || ix86_force_align_arg_pointer
5825 {
5826 /* Nested functions can't realign the stack due to a register
5827 conflict. */
5830 {
5835 ix86_force_align_arg_pointer_string);
5837 }
5840 }
5841 else
5843 }
5845 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5846 This is called from dwarf2out.c to emit call frame instructions
5847 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5848 static void
5850 {
5855 {
5866 }
5867 }
5869 /* Expand the prologue into a bunch of separate insns. */
5871 void
5873 {
5874 rtx insn;
5877 HOST_WIDE_INT allocate;
5882 {
5885 /* Grab the argument pointer. */
5891 /* The unwind info consists of two parts: install the fafp as the cfa,
5892 and record the fafp as the "save register" of the stack pointer.
5893 The later is there in order that the unwinder can see where it
5894 should restore the stack pointer across the and insn. */
5899 UNSPEC_REG_SAVE);
5906 /* Align the stack. */
5910 /* And here we cheat like madmen with the unwind info. We force the
5911 cfa register back to sp+4, which is exactly what it was at the
5912 start of the function. Re-pushing the return address results in
5913 the return at the same spot relative to the cfa, and thus is
5914 correct wrt the unwind info. */
5925 }
5927 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5928 slower on all targets. Also sdb doesn't like it. */
5931 {
5937 }
5943 else
5946 /* When using red zone we may start register saving before allocating
5947 the stack frame saving one cycle of the prologue. */
5954 ;
5958 else
5959 {
5960 /* Only valid for Win32. */
5963 rtx t;
5969 else
5973 {
5976 }
5982 else
5992 {
5995 allocate
5998 else
6001 }
6002 }
6005 {
6008 else
6011 }
6017 {
6024 }
6027 {
6029 {
6031 {
6044 }
6045 else
6047 }
6048 else
6051 /* Even with accurate pre-reload life analysis, we can wind up
6052 deleting all references to the pic register after reload.
6053 Consider if cross-jumping unifies two sides of a branch
6054 controlled by a comparison vs the only read from a global.
6055 In which case, allow the set_got to be deleted, though we're
6056 too late to do anything about the ebx save in the prologue. */
6058 }
6060 /* Prevent function calls from be scheduled before the call to mcount.
6061 In the pic_reg_used case, make sure that the got load isn't deleted. */
6064 }
6066 /* Emit code to restore saved registers using MOV insns. First register
6067 is restored from POINTER + OFFSET. */
6068 static void
6071 {
6077 {
6078 /* Ensure that adjust_address won't be forced to produce pointer
6079 out of range allowed by x86-64 instruction set. */
6081 {
6082 rtx r11;
6089 }
6093 }
6094 }
6096 /* Restore function stack, frame, and registers. */
6098 void
6100 {
6104 HOST_WIDE_INT offset;
6108 /* Calculate start of saved registers relative to ebp. Special care
6109 must be taken for the normal return case of a function using
6110 eh_return: the eax and edx registers are marked as saved, but not
6111 restored along this path. */
6117 /* If we're only restoring one register and sp is not valid then
6118 using a move instruction to restore the register since it's
6119 less work than reloading sp and popping the register.
6121 The default code result in stack adjustment using add/lea instruction,
6122 while this code results in LEAVE instruction (or discrete equivalent),
6123 so it is profitable in some other cases as well. Especially when there
6124 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6125 and there is exactly one register to pop. This heuristic may need some
6126 tuning in future. */
6128 || (TARGET_EPILOGUE_USING_MOVE
6136 {
6137 /* Restore registers. We can use ebp or esp to address the memory
6138 locations. If both are available, default to ebp, since offsets
6139 are known to be small. Only exception is esp pointing directly to the
6140 end of block of saved registers, where we may simplify addressing
6141 mode. */
6146 else
6150 /* eh_return epilogues need %ecx added to the stack pointer. */
6152 {
6156 {
6166 }
6167 else
6168 {
6173 }
6174 }
6179 style);
6180 /* If not an i386, mov & pop is faster than "leave". */
6184 else
6185 {
6187 hard_frame_pointer_rtx,
6191 else
6193 }
6194 }
6195 else
6196 {
6197 /* First step is to deallocate the stack frame so that we can
6198 pop the registers. */
6200 {
6203 hard_frame_pointer_rtx,
6205 }
6212 {
6215 else
6217 }
6219 {
6220 /* Leave results in shorter dependency chains on CPUs that are
6221 able to grok it fast. */
6226 else
6228 }
6229 }
6232 {
6236 }
6238 /* Sibcall epilogues don't want a return instruction. */
6243 {
6246 /* i386 can only pop 64K bytes. If asked to pop more, pop
6247 return address, do explicit add, and jump indirectly to the
6248 caller. */
6251 {
6254 /* There is no "pascal" calling convention in any 64bit ABI. */
6260 }
6261 else
6263 }
6264 else
6266 }
6268 /* Reset from the function's potential modifications. */
6270 static void
6272 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6273 {
6276 #if TARGET_MACHO
6277 /* Mach-O doesn't support labels at the end of objects, so if
6278 it looks like we might want one, insert a NOP. */
6279 {
6290 }
6291 #endif
6293 }
6294 \f
6295 /* Extract the parts of an RTL expression that is a valid memory address
6296 for an instruction. Return 0 if the structure of the address is
6297 grossly off. Return -1 if the address contains ASHIFT, so it is not
6298 strictly valid, but still used for computing length of lea instruction. */
6300 int
6302 {
6313 {
6318 do
6319 {
6324 }
6331 {
6334 {
6344 && TARGET_TLS_DIRECT_SEG_REFS
6347 else
6357 else
6372 }
6373 }
6374 }
6376 {
6379 }
6381 {
6382 rtx tmp;
6384 /* We're called for lea too, which implements ashift on occasion. */
6394 }
6395 else
6398 /* Extract the integral value of scale. */
6400 {
6404 }
6409 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6414 {
6415 rtx tmp;
6418 }
6420 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6426 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6427 Avoid this by transforming to [%esi+0]. */
6434 /* Special case: encode reg+reg instead of reg*2. */
6438 /* Special case: scaling cannot be encoded without base or displacement. */
6449 }
6450 \f
6451 /* Return cost of the memory address x.
6452 For i386, it is better to use a complex address than let gcc copy
6453 the address into a reg and make a new pseudo. But not if the address
6454 requires to two regs - that would mean more pseudos with longer
6455 lifetimes. */
6456 static int
6458 {
6470 /* More complex memory references are better. */
6472 cost--;
6474 cost--;
6476 /* Attempt to minimize number of registers in the address. */
6482 cost++;
6489 cost++;
6491 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6492 since it's predecode logic can't detect the length of instructions
6493 and it degenerates to vector decoded. Increase cost of such
6494 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6495 to split such addresses or even refuse such addresses at all.
6497 Following addressing modes are affected:
6498 [base+scale*index]
6499 [scale*index+disp]
6500 [base+index]
6502 The first and last case may be avoidable by explicitly coding the zero in
6503 memory address, but I don't have AMD-K6 machine handy to check this
6504 theory. */
6513 }
6514 \f
6515 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6516 this is used for to form addresses to local data when -fPIC is in
6517 use. */
6519 static bool
6521 {
6523 {
6527 {
6531 }
6532 }
6535 }
6537 /* Determine if a given RTX is a valid constant. We already know this
6538 satisfies CONSTANT_P. */
6540 bool
6542 {
6544 {
6549 {
6553 }
6558 /* Only some unspecs are valid as "constants". */
6561 {
6577 }
6579 /* We must have drilled down to a symbol. */
6584 /* FALLTHRU */
6587 /* TLS symbols are never valid. */
6591 /* DLLIMPORT symbols are never valid. */
6611 }
6613 /* Otherwise we handle everything else in the move patterns. */
6615 }
6617 /* Determine if it's legal to put X into the constant pool. This
6618 is not possible for the address of thread-local symbols, which
6619 is checked above. */
6621 static bool
6623 {
6624 /* We can always put integral constants and vectors in memory. */
6626 {
6634 }
6636 }
6638 /* Determine if a given RTX is a valid constant address. */
6640 bool
6642 {
6644 }
6646 /* Nonzero if the constant value X is a legitimate general operand
6647 when generating PIC code. It is given that flag_pic is on and
6648 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6650 bool
6652 {
6653 rtx inner;
6656 {
6663 /* Only some unspecs are valid as "constants". */
6666 {
6677 }
6678 /* FALLTHRU */
6686 }
6687 }
6689 /* Determine if a given CONST RTX is a valid memory displacement
6690 in PIC mode. */
6692 int
6694 {
6697 /* In 64bit mode we can allow direct addresses of symbols and labels
6698 when they are not dynamic symbols. */
6700 {
6704 {
6721 /* FALLTHRU */
6724 /* TLS references should always be enclosed in UNSPEC. */
6734 }
6735 }
6741 {
6742 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6743 of GOT tables. We should not need these anyway. */
6754 }
6758 {
6763 }
6772 {
6776 /* We need to check for both symbols and labels because VxWorks loads
6777 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
6778 details. */
6782 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6783 While ABI specify also 32bit relocation but we don't produce it in
6784 small PIC model at all. */
6806 }
6809 }
6811 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6812 memory address for an instruction. The MODE argument is the machine mode
6813 for the MEM expression that wants to use this address.
6815 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6816 convert common non-canonical forms to canonical form so that they will
6817 be recognized. */
6819 int
6822 {
6825 HOST_WIDE_INT scale;
6830 {
6833 }
6840 /* Validate base register.
6842 Don't allow SUBREG's that span more than a word here. It can lead to spill
6843 failures when the base is one word out of a two word structure, which is
6844 represented internally as a DImode int. */
6847 {
6848 rtx reg;
6858 else
6859 {
6862 }
6865 {
6868 }
6872 {
6875 }
6876 }
6878 /* Validate index register.
6880 Don't allow SUBREG's that span more than a word here -- same as above. */
6883 {
6884 rtx reg;
6894 else
6895 {
6898 }
6901 {
6904 }
6908 {
6911 }
6912 }
6914 /* Validate scale factor. */
6916 {
6919 {
6922 }
6925 {
6928 }
6929 }
6931 /* Validate displacement. */
6933 {
6939 {
6940 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6941 used. While ABI specify also 32bit relocations, we don't produce
6942 them at all and use IP relative instead. */
6965 }
6968 && (flag_pic
6969 || (TARGET_MACHO
6970 #if TARGET_MACHO
6971 && MACHOPIC_INDIRECT
6973 #endif
6974 )))
6975 {
6977 is_legitimate_pic:
6979 {
6980 /* foo@dtpoff(%rX) is ok. */
6987 {
6990 }
6991 }
6993 {
6996 }
6998 /* This code used to verify that a symbolic pic displacement
6999 includes the pic_offset_table_rtx register.
7001 While this is good idea, unfortunately these constructs may
7002 be created by "adds using lea" optimization for incorrect
7003 code like:
7005 int a;
7006 int foo(int i)
7007 {
7008 return *(&a+i);
7009 }
7011 This code is nonsensical, but results in addressing
7012 GOT table with pic_offset_table_rtx base. We can't
7013 just refuse it easily, since it gets matched by
7014 "addsi3" pattern, that later gets split to lea in the
7015 case output register differs from input. While this
7016 can be handled by separate addsi pattern for this case
7017 that never results in lea, this seems to be easier and
7018 correct fix for crash to disable this test. */
7019 }
7026 {
7029 }
7032 {
7035 }
7036 }
7038 /* Everything looks valid. */
7041 report_error:
7043 }
7044 \f
7045 /* Return a unique alias set for the GOT. */
7047 static HOST_WIDE_INT
7049 {
7054 }
7056 /* Return a legitimate reference for ORIG (an address) using the
7057 register REG. If REG is 0, a new pseudo is generated.
7059 There are two types of references that must be handled:
7061 1. Global data references must load the address from the GOT, via
7062 the PIC reg. An insn is emitted to do this load, and the reg is
7063 returned.
7065 2. Static data references, constant pool addresses, and code labels
7066 compute the address as an offset from the GOT, whose base is in
7067 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7068 differentiate them from global data objects. The returned
7069 address is the PIC reg + an unspec constant.
7071 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7072 reg also appears in the address. */
7074 static rtx
7076 {
7079 rtx base;
7081 #if TARGET_MACHO
7083 {
7086 /* Use the generic Mach-O PIC machinery. */
7088 }
7089 #endif
7096 {
7097 rtx tmpreg;
7098 /* This symbol may be referenced via a displacement from the PIC
7099 base address (@GOTOFF). */
7106 {
7108 UNSPEC_GOTOFF);
7110 }
7111 else
7116 else
7121 {
7125 }
7127 }
7129 {
7130 /* This symbol may be referenced via a displacement from the PIC
7131 base address (@GOTOFF). */
7138 {
7140 UNSPEC_GOTOFF);
7142 }
7143 else
7149 {
7152 }
7153 }
7155 /* We can't use @GOTOFF for text labels on VxWorks;
7156 see gotoff_operand. */
7158 {
7159 /* Given that we've already handled dllimport variables separately
7160 in legitimize_address, and all other variables should satisfy
7161 legitimate_pic_address_disp_p, we should never arrive here. */
7165 {
7173 /* Use directly gen_movsi, otherwise the address is loaded
7174 into register for CSE. We don't want to CSE this addresses,
7175 instead we CSE addresses from the GOT table, so skip this. */
7178 }
7179 else
7180 {
7181 /* This symbol must be referenced via a load from the
7182 Global Offset Table (@GOT). */
7198 }
7199 }
7200 else
7201 {
7204 {
7206 {
7209 }
7210 else
7212 }
7214 {
7217 /* We must match stuff we generate before. Assume the only
7218 unspecs that can get here are ours. Not that we could do
7219 anything with them anyway.... */
7225 }
7227 {
7230 /* Check first to see if this is a constant offset from a @GOTOFF
7231 symbol reference. */
7234 {
7236 {
7240 UNSPEC_GOTOFF);
7246 {
7249 }
7250 }
7251 else
7252 {
7255 {
7259 }
7260 }
7261 }
7262 else
7263 {
7270 else
7271 {
7273 {
7276 }
7278 }
7279 }
7280 }
7281 }
7283 }
7284 \f
7285 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7287 static rtx
7289 {
7301 }
7303 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7304 false if we expect this to be used for a memory address and true if
7305 we expect to load the address into a register. */
7307 static rtx
7309 {
7314 {
7320 {
7330 }
7333 else
7337 {
7341 }
7349 {
7361 }
7364 else
7368 {
7373 }
7381 {
7385 }
7391 {
7394 }
7396 {
7401 }
7403 {
7407 }
7408 else
7409 {
7412 }
7422 {
7426 }
7427 else
7428 {
7432 }
7442 {
7445 }
7446 else
7447 {
7451 }
7456 }
7459 }
7461 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7462 to symbol DECL. */
7465 htab_t dllimport_map;
7467 static tree
7469 {
7476 tree to;
7477 rtx rtl;
7501 {
7502 name++;
7504 }
7505 else
7525 }
7527 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7528 true if we require the result be a register. */
7530 static rtx
7532 {
7533 tree imp_decl;
7534 rtx x;
7543 }
7545 /* Try machine-dependent ways of modifying an illegitimate address
7546 to be legitimate. If we find one, return the new, valid address.
7547 This macro is used in only one place: `memory_address' in explow.c.
7549 OLDX is the address as it was before break_out_memory_refs was called.
7550 In some cases it is useful to look at this to decide what needs to be done.
7552 MODE and WIN are passed so that this macro can use
7553 GO_IF_LEGITIMATE_ADDRESS.
7555 It is always safe for this macro to do nothing. It exists to recognize
7556 opportunities to optimize the output.
7558 For the 80386, we handle X+REG by loading X into a register R and
7559 using R+REG. R will go in a general reg and indexing will be used.
7560 However, if REG is a broken-out memory address or multiplication,
7561 nothing needs to be done because REG can certainly go in a general reg.
7563 When -fpic is used, special handling is needed for symbolic references.
7564 See comments by legitimize_pic_address in i386.c for details. */
7566 rtx
7568 {
7579 {
7582 }
7588 {
7595 {
7598 }
7599 }
7601 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7605 {
7610 }
7613 {
7614 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7619 {
7625 }
7630 {
7636 }
7638 /* Put multiply first if it isn't already. */
7640 {
7645 }
7647 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7648 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7649 created by virtual register instantiation, register elimination, and
7650 similar optimizations. */
7652 {
7658 }
7660 /* Canonicalize
7661 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7662 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7667 {
7668 rtx constant;
7672 {
7675 }
7677 {
7680 }
7681 else
7685 {
7691 }
7692 }
7698 {
7701 }
7704 {
7707 }
7715 {
7718 }
7724 {
7732 }
7735 {
7743 }
7744 }
7747 }
7748 \f
7749 /* Print an integer constant expression in assembler syntax. Addition
7750 and subtraction are the only arithmetic that may appear in these
7751 expressions. FILE is the stdio stream to write to, X is the rtx, and
7752 CODE is the operand print code from the output string. */
7754 static void
7756 {
7760 {
7769 else
7770 {
7773 /* Mark the decl as referenced so that cgraph will
7774 output the function. */
7778 #if TARGET_MACHO
7782 #endif
7784 }
7792 /* FALLTHRU */
7803 /* This used to output parentheses around the expression,
7804 but that does not work on the 386 (either ATT or BSD assembler). */
7810 {
7811 /* We can use %d if the number is <32 bits and positive. */
7816 else
7818 }
7819 else
7820 /* We can't handle floating point constants;
7821 PRINT_OPERAND must handle them. */
7826 /* Some assemblers need integer constants to appear first. */
7828 {
7832 }
7833 else
7834 {
7839 }
7856 {
7870 /* FIXME: This might be @TPOFF in Sun ld too. */
7879 else
7888 else
7897 }
7902 }
7903 }
7905 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7906 We need to emit DTP-relative relocations. */
7908 static void ATTRIBUTE_UNUSED
7910 {
7915 {
7923 }
7924 }
7926 /* In the name of slightly smaller debug output, and to cater to
7927 general assembler lossage, recognize PIC+GOTOFF and turn it back
7928 into a direct symbol reference.
7930 On Darwin, this is necessary to avoid a crash, because Darwin
7931 has a different PIC label for each routine but the DWARF debugging
7932 information is not associated with any particular routine, so it's
7933 necessary to remove references to the PIC label from RTL stored by
7934 the DWARF output code. */
7936 static rtx
7938 {
7940 /* reg_addend is NULL or a multiple of some register. */
7942 /* const_addend is NULL or a const_int. */
7944 /* This is the result, or NULL. */
7951 {
7958 }
7966 /* %ebx + GOT/GOTOFF */
7967 ;
7969 {
7970 /* %ebx + %reg * scale + GOT/GOTOFF */
7978 else
7984 }
7985 else
7991 {
7994 }
8013 }
8015 /* If X is a machine specific address (i.e. a symbol or label being
8016 referenced as a displacement from the GOT implemented using an
8017 UNSPEC), then return the base term. Otherwise return X. */
8019 rtx
8021 {
8022 rtx term;
8025 {
8044 }
8053 }
8054 \f
8055 static void
8058 {
8062 {
8068 }
8073 {
8085 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8086 Those same assemblers have the same but opposite lossage on cmov. */
8092 {
8105 }
8113 {
8126 }
8129 /* ??? As above. */
8149 }
8151 }
8153 /* Print the name of register X to FILE based on its machine mode and number.
8154 If CODE is 'w', pretend the mode is HImode.
8155 If CODE is 'b', pretend the mode is QImode.
8156 If CODE is 'k', pretend the mode is SImode.
8157 If CODE is 'q', pretend the mode is DImode.
8158 If CODE is 'h', pretend the reg is the 'high' byte register.
8159 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8161 void
8163 {
8185 else
8188 /* Irritatingly, AMD extended registers use different naming convention
8189 from the normal registers. */
8191 {
8194 {
8213 }
8215 }
8217 {
8220 {
8223 }
8224 /* FALLTHRU */
8230 /* FALLTHRU */
8233 normal:
8248 }
8249 }
8251 /* Locate some local-dynamic symbol still in use by this function
8252 so that we can print its name in some tls_local_dynamic_base
8253 pattern. */
8255 static int
8257 {
8262 {
8265 }
8268 }
8272 {
8273 rtx insn;
8284 }
8286 /* Meaning of CODE:
8287 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8288 C -- print opcode suffix for set/cmov insn.
8289 c -- like C, but print reversed condition
8290 F,f -- likewise, but for floating-point.
8291 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8292 otherwise nothing
8293 R -- print the prefix for register names.
8294 z -- print the opcode suffix for the size of the current operand.
8295 * -- print a star (in certain assembler syntax)
8296 A -- print an absolute memory reference.
8297 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8298 s -- print a shift double count, followed by the assemblers argument
8299 delimiter.
8300 b -- print the QImode name of the register for the indicated operand.
8301 %b0 would print %al if operands[0] is reg 0.
8302 w -- likewise, print the HImode name of the register.
8303 k -- likewise, print the SImode name of the register.
8304 q -- likewise, print the DImode name of the register.
8305 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8306 y -- print "st(0)" instead of "st" as a register.
8307 D -- print condition for SSE cmp instruction.
8308 P -- if PIC, print an @PLT suffix.
8309 X -- don't print any sort of PIC '@' suffix for a symbol.
8310 & -- print some in-use local-dynamic symbol name.
8311 H -- print a memory address offset by 8; used for sse high-parts
8312 */
8314 void
8316 {
8318 {
8320 {
8332 {
8338 /* Intel syntax. For absolute addresses, registers should not
8339 be surrounded by braces. */
8341 {
8346 }
8351 }
8388 /* 387 opcodes don't get size suffixes if the operands are
8389 registers. */
8393 /* Likewise if using Intel opcodes. */
8397 /* This is the size of op from size of operand. */
8399 {
8406 {
8407 #ifdef HAVE_GAS_FILDS_FISTS
8409 #endif
8411 }
8412 else
8418 {
8421 }
8422 else
8433 {
8434 #ifdef GAS_MNEMONICS
8436 #else
8439 #endif
8440 }
8441 else
8447 }
8461 {
8464 }
8468 /* Little bit of braindamage here. The SSE compare instructions
8469 does use completely different names for the comparisons that the
8470 fp conditional moves. */
8472 {
8505 }
8508 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8510 {
8512 {
8519 }
8521 }
8522 #endif
8528 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8531 #endif
8535 /* Like above, but reverse condition */
8537 /* Check to see if argument to %c is really a constant
8538 and not a condition code which needs to be reversed. */
8540 {
8541 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8543 }
8547 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8550 #endif
8555 /* It doesn't actually matter what mode we use here, as we're
8556 only going to use this for printing. */
8561 {
8562 rtx x;
8569 {
8574 {
8578 /* Emit hints only in the case default branch prediction
8579 heuristics would fail. */
8581 {
8582 /* We use 3e (DS) prefix for taken branches and
8583 2e (CS) prefix for not taken branches. */
8586 else
8588 }
8589 }
8590 }
8592 }
8595 }
8596 }
8602 {
8603 /* No `byte ptr' prefix for call instructions. */
8605 {
8608 {
8617 }
8619 /* Check for explicit size override (codes 'b', 'w' and 'k') */
8629 }
8632 /* Avoid (%rip) for call operands. */
8638 else
8640 }
8643 {
8644 REAL_VALUE_TYPE r;
8653 }
8655 /* These float cases don't actually occur as immediate operands. */
8657 {
8662 }
8666 {
8671 }
8673 else
8674 {
8675 /* We have patterns that allow zero sets of memory, for instance.
8676 In 64-bit mode, we should probably support all 8-byte vectors,
8677 since we can in fact encode that into an immediate. */
8679 {
8682 }
8685 {
8687 {
8690 }
8693 {
8696 else
8698 }
8699 }
8704 else
8706 }
8707 }
8708 \f
8709 /* Print a memory operand whose address is ADDR. */
8711 void
8713 {
8727 {
8738 }
8741 {
8742 /* Displacement only requires special attention. */
8745 {
8747 {
8751 }
8753 }
8756 else
8759 /* Use one byte shorter RIP relative addressing for 64bit mode. */
8761 {
8770 }
8771 }
8772 else
8773 {
8775 {
8777 {
8782 else
8784 }
8790 {
8795 }
8797 }
8798 else
8799 {
8803 {
8804 /* Pull out the offset of a symbol; print any symbol itself. */
8808 {
8812 }
8820 else
8822 }
8826 {
8829 {
8833 }
8834 }
8837 else
8841 {
8846 }
8848 }
8849 }
8850 }
8852 bool
8854 {
8855 rtx op;
8862 {
8865 /* FIXME: This might be @TPOFF in Sun ld. */
8876 else
8887 else
8897 }
8900 }
8901 \f
8902 /* Split one or more DImode RTL references into pairs of SImode
8903 references. The RTL can be REG, offsettable MEM, integer constant, or
8904 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8905 split and "num" is its length. lo_half and hi_half are output arrays
8906 that parallel "operands". */
8908 void
8910 {
8912 {
8915 /* simplify_subreg refuse to split volatile memory addresses,
8916 but we still have to handle it. */
8918 {
8921 }
8922 else
8923 {
8930 }
8931 }
8932 }
8933 /* Split one or more TImode RTL references into pairs of DImode
8934 references. The RTL can be REG, offsettable MEM, integer constant, or
8935 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8936 split and "num" is its length. lo_half and hi_half are output arrays
8937 that parallel "operands". */
8939 void
8941 {
8943 {
8946 /* simplify_subreg refuse to split volatile memory addresses, but we
8947 still have to handle it. */
8949 {
8952 }
8953 else
8954 {
8957 }
8958 }
8959 }
8960 \f
8961 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8962 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8963 is the expression of the binary operation. The output may either be
8964 emitted here, or returned to the caller, like all output_* functions.
8966 There is no guarantee that the operands are the same mode, as they
8967 might be within FLOAT or FLOAT_EXTEND expressions. */
8969 #ifndef SYSV386_COMPAT
8970 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8971 wants to fix the assemblers because that causes incompatibility
8972 with gcc. No-one wants to fix gcc because that causes
8973 incompatibility with assemblers... You can use the option of
8974 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8975 #define SYSV386_COMPAT 1
8976 #endif
8980 {
8986 #ifdef ENABLE_CHECKING
8987 /* Even if we do not want to check the inputs, this documents input
8988 constraints. Which helps in understanding the following code. */
8998 else
9000 #endif
9003 {
9008 else
9017 else
9026 else
9035 else
9042 }
9045 {
9049 else
9052 }
9056 {
9060 {
9064 }
9066 /* know operands[0] == operands[1]. */
9069 {
9072 }
9075 {
9077 /* How is it that we are storing to a dead operand[2]?
9078 Well, presumably operands[1] is dead too. We can't
9079 store the result to st(0) as st(0) gets popped on this
9080 instruction. Instead store to operands[2] (which I
9081 think has to be st(1)). st(1) will be popped later.
9082 gcc <= 2.8.1 didn't have this check and generated
9083 assembly code that the Unixware assembler rejected. */
9085 else
9088 }
9092 else
9099 {
9102 }
9105 {
9108 }
9111 {
9112 #if SYSV386_COMPAT
9113 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9114 derived assemblers, confusingly reverse the direction of
9115 the operation for fsub{r} and fdiv{r} when the
9116 destination register is not st(0). The Intel assembler
9117 doesn't have this brain damage. Read !SYSV386_COMPAT to
9118 figure out what the hardware really does. */
9121 else
9123 #else
9125 /* As above for fmul/fadd, we can't store to st(0). */
9127 else
9129 #endif
9131 }
9134 {
9135 #if SYSV386_COMPAT
9138 else
9140 #else
9143 else
9145 #endif
9147 }
9150 {
9153 else
9156 }
9158 {
9159 #if SYSV386_COMPAT
9161 #else
9163 #endif
9164 }
9165 else
9166 {
9167 #if SYSV386_COMPAT
9169 #else
9171 #endif
9172 }
9177 }
9181 }
9183 /* Return needed mode for entity in optimize_mode_switching pass. */
9185 int
9187 {
9190 /* The mode UNINITIALIZED is used to store control word after a
9191 function call or ASM pattern. The mode ANY specify that function
9192 has no requirements on the control word and make no changes in the
9193 bits we are interested in. */
9207 {
9230 }
9233 }
9235 /* Output code to initialize control word copies used by trunc?f?i and
9236 rounding patterns. CURRENT_MODE is set to current control word,
9237 while NEW_MODE is set to new control word. */
9239 void
9241 {
9243 rtx new_mode;
9253 {
9255 {
9257 /* round toward zero (truncate) */
9263 /* round down toward -oo */
9270 /* round up toward +oo */
9277 /* mask precision exception for nearbyint() */
9284 }
9285 }
9286 else
9287 {
9289 {
9291 /* round toward zero (truncate) */
9297 /* round down toward -oo */
9303 /* round up toward +oo */
9309 /* mask precision exception for nearbyint() */
9316 }
9317 }
9323 }
9325 /* Output code for INSN to convert a float to a signed int. OPERANDS
9326 are the insn operands. The output may be [HSD]Imode and the input
9327 operand may be [SDX]Fmode. */
9331 {
9336 /* Jump through a hoop or two for DImode, since the hardware has no
9337 non-popping instruction. We used to do this a different way, but
9338 that was somewhat fragile and broke with post-reload splitters. */
9348 else
9349 {
9354 else
9358 }
9361 }
9363 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9364 have the values zero or one, indicates the ffreep insn's operand
9365 from the OPERANDS array. */
9369 {
9371 #if HAVE_AS_IX86_FFREEP
9373 #else
9374 {
9382 }
9383 #endif
9386 }
9389 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9390 should be used. UNORDERED_P is true when fucom should be used. */
9394 {
9400 {
9403 }
9404 else
9405 {
9408 }
9411 {
9415 else
9417 else
9420 else
9422 }
9429 {
9431 {
9434 }
9435 else
9437 }
9440 && stack_top_dies
9443 {
9444 /* If both the top of the 387 stack dies, and the other operand
9445 is also a stack register that dies, then this must be a
9446 `fcompp' float compare */
9449 {
9450 /* There is no double popping fcomi variant. Fortunately,
9451 eflags is immune from the fstp's cc clobbering. */
9454 else
9457 }
9458 else
9459 {
9462 else
9464 }
9465 }
9466 else
9467 {
9468 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9471 {
9479 NULL,
9480 NULL,
9487 NULL,
9488 NULL,
9489 NULL,
9490 NULL
9491 };
9506 }
9507 }
9509 void
9511 {
9514 #ifdef ASM_QUAD
9517 #else
9519 #endif
9522 }
9524 void
9526 {
9529 #ifdef ASM_QUAD
9532 #else
9534 #endif
9535 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
9541 #if TARGET_MACHO
9543 {
9547 }
9548 #endif
9549 else
9552 }
9553 \f
9554 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9555 for the target. */
9557 void
9559 {
9560 rtx tmp;
9562 /* We play register width games, which are only valid after reload. */
9565 /* Avoid HImode and its attendant prefix byte. */
9570 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
9572 {
9575 }
9578 }
9580 /* X is an unchanging MEM. If it is a constant pool reference, return
9581 the constant pool rtx, else NULL. */
9583 rtx
9585 {
9592 }
9594 void
9596 {
9605 {
9608 {
9613 }
9617 }
9621 {
9634 {
9640 }
9641 }
9644 {
9646 {
9647 #if TARGET_MACHO
9649 {
9650 rtx temp = ((reload_in_progress
9657 }
9662 #endif
9663 }
9664 else
9665 {
9669 {
9674 }
9675 }
9676 }
9677 else
9678 {
9689 /* Force large constants in 64bit compilation into register
9690 to get them CSEed. */
9699 {
9700 /* If we are loading a floating point constant to a register,
9701 force the value to memory now, since we'll get better code
9702 out the back end. */
9705 ;
9707 {
9710 {
9715 }
9716 }
9717 }
9718 }
9721 }
9723 void
9725 {
9728 /* Force constants other than zero into memory. We do not know how
9729 the instructions used to build constants modify the upper 64 bits
9730 of the register, once we have that information we may be able
9731 to handle some of them more efficiently. */
9738 /* Make operand1 a register if it isn't already. */
9742 {
9745 }
9748 }
9750 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
9751 straight to ix86_expand_vector_move. */
9752 /* Code generation for scalar reg-reg moves of single and double precision data:
9753 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
9754 movaps reg, reg
9755 else
9756 movss reg, reg
9757 if (x86_sse_partial_reg_dependency == true)
9758 movapd reg, reg
9759 else
9760 movsd reg, reg
9762 Code generation for scalar loads of double precision data:
9763 if (x86_sse_split_regs == true)
9764 movlpd mem, reg (gas syntax)
9765 else
9766 movsd mem, reg
9768 Code generation for unaligned packed loads of single precision data
9769 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
9770 if (x86_sse_unaligned_move_optimal)
9771 movups mem, reg
9773 if (x86_sse_partial_reg_dependency == true)
9774 {
9775 xorps reg, reg
9776 movlps mem, reg
9777 movhps mem+8, reg
9778 }
9779 else
9780 {
9781 movlps mem, reg
9782 movhps mem+8, reg
9783 }
9785 Code generation for unaligned packed loads of double precision data
9786 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
9787 if (x86_sse_unaligned_move_optimal)
9788 movupd mem, reg
9790 if (x86_sse_split_regs == true)
9791 {
9792 movlpd mem, reg
9793 movhpd mem+8, reg
9794 }
9795 else
9796 {
9797 movsd mem, reg
9798 movhpd mem+8, reg
9799 }
9800 */
9802 void
9804 {
9811 {
9812 /* If we're optimizing for size, movups is the smallest. */
9814 {
9819 }
9821 /* ??? If we have typed data, then it would appear that using
9822 movdqu is the only way to get unaligned data loaded with
9823 integer type. */
9825 {
9830 }
9833 {
9834 rtx zero;
9837 {
9842 }
9844 /* When SSE registers are split into halves, we can avoid
9845 writing to the top half twice. */
9847 {
9850 }
9851 else
9852 {
9853 /* ??? Not sure about the best option for the Intel chips.
9854 The following would seem to satisfy; the register is
9855 entirely cleared, breaking the dependency chain. We
9856 then store to the upper half, with a dependency depth
9857 of one. A rumor has it that Intel recommends two movsd
9858 followed by an unpacklpd, but this is unconfirmed. And
9859 given that the dependency depth of the unpacklpd would
9860 still be one, I'm not sure why this would be better. */
9862 }
9868 }
9869 else
9870 {
9872 {
9877 }
9881 else
9890 }
9891 }
9893 {
9894 /* If we're optimizing for size, movups is the smallest. */
9896 {
9901 }
9903 /* ??? Similar to above, only less clear because of quote
9904 typeless stores unquote. */
9907 {
9912 }
9915 {
9920 }
9921 else
9922 {
9929 }
9930 }
9931 else
9933 }
9935 /* Expand a push in MODE. This is some mode for which we do not support
9936 proper push instructions, at least from the registers that we expect
9937 the value to live in. */
9939 void
9941 {
9942 rtx tmp;
9952 }
9954 /* Helper function of ix86_fixup_binary_operands to canonicalize
9955 operand order. Returns true if the operands should be swapped. */
9957 static bool
9959 rtx operands[])
9960 {
9965 /* If the operation is not commutative, we can't do anything. */
9969 /* Highest priority is that src1 should match dst. */
9975 /* Next highest priority is that immediate constants come second. */
9981 /* Lowest priority is that memory references should come second. */
9988 }
9991 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
9992 destination to use for the operation. If different from the true
9993 destination in operands[0], a copy operation will be required. */
9995 rtx
9997 rtx operands[])
9998 {
10003 /* Canonicalize operand order. */
10005 {
10009 }
10011 /* Both source operands cannot be in memory. */
10013 {
10014 /* Optimization: Only read from memory once. */
10016 {
10019 }
10020 else
10022 }
10024 /* If the destination is memory, and we do not have matching source
10025 operands, do things in registers. */
10029 /* Source 1 cannot be a constant. */
10033 /* Source 1 cannot be a non-matching memory. */
10040 }
10042 /* Similarly, but assume that the destination has already been
10043 set up properly. */
10045 void
10048 {
10051 }
10053 /* Attempt to expand a binary operator. Make the expansion closer to the
10054 actual machine, then just general_operand, which will allow 3 separate
10055 memory references (one output, two input) in a single insn. */
10057 void
10059 rtx operands[])
10060 {
10067 /* Emit the instruction. */
10071 {
10072 /* Reload doesn't know about the flags register, and doesn't know that
10073 it doesn't want to clobber it. We can only do this with PLUS. */
10076 }
10077 else
10078 {
10081 }
10083 /* Fix up the destination if needed. */
10086 }
10088 /* Return TRUE or FALSE depending on whether the binary operator meets the
10089 appropriate constraints. */
10091 int
10094 {
10099 /* Both source operands cannot be in memory. */
10103 /* Canonicalize operand order for commutative operators. */
10105 {
10109 }
10111 /* If the destination is memory, we must have a matching source operand. */
10115 /* Source 1 cannot be a constant. */
10119 /* Source 1 cannot be a non-matching memory. */
10124 }
10126 /* Attempt to expand a unary operator. Make the expansion closer to the
10127 actual machine, then just general_operand, which will allow 2 separate
10128 memory references (one output, one input) in a single insn. */
10130 void
10132 rtx operands[])
10133 {
10140 /* If the destination is memory, and we do not have matching source
10141 operands, do things in registers. */
10144 {
10147 else
10149 }
10151 /* When source operand is memory, destination must match. */
10155 /* Emit the instruction. */
10159 {
10160 /* Reload doesn't know about the flags register, and doesn't know that
10161 it doesn't want to clobber it. */
10164 }
10165 else
10166 {
10169 }
10171 /* Fix up the destination if needed. */
10174 }
10176 /* Return TRUE or FALSE depending on whether the unary operator meets the
10177 appropriate constraints. */
10179 int
10183 {
10184 /* If one of operands is memory, source and destination must match. */
10190 }
10192 /* Post-reload splitter for converting an SF or DFmode value in an
10193 SSE register into an unsigned SImode. */
10195 void
10197 {
10208 /* Load up the value into the low element. We must ensure that the other
10209 elements are valid floats -- zero is the easiest such value. */
10211 {
10214 else
10216 }
10217 else
10218 {
10223 else
10225 }
10245 else
10250 }
10252 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10253 Expects the 64-bit DImode to be supplied in a pair of integral
10254 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10255 -mfpmath=sse, !optimize_size only. */
10257 void
10259 {
10263 rtx x;
10269 {
10272 }
10273 else
10274 {
10278 }
10286 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10289 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10290 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10291 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10292 (0x1.0p84 + double(fp_value_hi_xmm)).
10293 Note these exponents differ by 32. */
10297 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10298 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10307 /* Add the upper and lower DFmode values together. */
10310 else
10311 {
10315 }
10318 }
10320 /* Convert an unsigned SImode value into a DFmode. Only currently used
10321 for SSE, but applicable anywhere. */
10323 void
10325 {
10326 REAL_VALUE_TYPE TWO31r;
10341 }
10343 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10344 32-bit mode; otherwise we have a direct convert instruction. */
10346 void
10348 {
10349 REAL_VALUE_TYPE TWO32r;
10367 }
10369 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10370 For x86_32, -mfpmath=sse, !optimize_size only. */
10371 void
10373 {
10374 REAL_VALUE_TYPE ONE16r;
10393 }
10395 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10396 then replicate the value for all elements of the vector
10397 register. */
10399 rtx
10401 {
10402 rtvec v;
10404 {
10408 else
10416 else
10422 }
10423 }
10425 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
10426 Create a mask for the sign bit in MODE for an SSE register. If VECT is
10427 true, then replicate the mask for all elements of the vector register.
10428 If INVERT is true, then create a mask excluding the sign bit. */
10430 rtx
10432 {
10436 rtx v;
10437 rtx mask;
10439 /* Find the sign bit, sign extended to 2*HWI. */
10444 else
10450 /* Force this value into the low part of a fp vector constant. */
10457 }
10459 /* Generate code for floating point ABS or NEG. */
10461 void
10463 rtx operands[])
10464 {
10472 {
10475 }
10479 /* NEG and ABS performed with SSE use bitwise mask operations.
10480 Create the appropriate mask now. */
10483 else
10489 /* If the destination is memory, and we don't have matching source
10490 operands or we're using the x87, do things in registers. */
10493 {
10496 else
10498 }
10503 {
10507 }
10508 else
10509 {
10513 {
10518 }
10519 else
10521 }
10525 }
10527 /* Expand a copysign operation. Special case operand 0 being a constant. */
10529 void
10531 {
10543 {
10544 rtvec v;
10551 else
10552 {
10556 else
10559 }
10565 else
10567 }
10568 else
10569 {
10575 else
10577 }
10578 }
10580 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
10581 be a constant, and so has already been expanded into a vector constant. */
10583 void
10585 {
10602 {
10605 }
10606 }
10608 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
10609 so we have to do two masks. */
10611 void
10613 {
10628 {
10629 /* Shouldn't happen often (it's useless, obviously), but when it does
10630 we'd generate incorrect code if we continue below. */
10633 }
10636 {
10647 }
10648 else
10649 {
10651 {
10653 }
10655 {
10659 }
10663 {
10666 }
10668 {
10673 }
10675 }
10679 }
10681 /* Return TRUE or FALSE depending on whether the first SET in INSN
10682 has source and destination with matching CC modes, and that the
10683 CC mode is at least as constrained as REQ_MODE. */
10685 int
10687 {
10688 rtx set;
10699 {
10709 /* FALLTHRU */
10713 /* FALLTHRU */
10717 /* FALLTHRU */
10723 }
10726 }
10728 /* Generate insn patterns to do an integer compare of OPERANDS. */
10730 static rtx
10732 {
10739 /* This is very simple, but making the interface the same as in the
10740 FP case makes the rest of the code easier. */
10744 /* Return the test that should be put into the flags user, i.e.
10745 the bcc, scc, or cmov instruction. */
10747 }
10749 /* Figure out whether to use ordered or unordered fp comparisons.
10750 Return the appropriate mode to use. */
10752 enum machine_mode
10754 {
10755 /* ??? In order to make all comparisons reversible, we do all comparisons
10756 non-trapping when compiling for IEEE. Once gcc is able to distinguish
10757 all forms trapping and nontrapping comparisons, we can make inequality
10758 comparisons trapping again, since it results in better code when using
10759 FCOM based compares. */
10761 }
10763 enum machine_mode
10765 {
10769 {
10772 }
10775 {
10776 /* Only zero flag is needed. */
10780 /* Codes needing carry flag. */
10786 /* Codes possibly doable only with sign flag when
10787 comparing against zero. */
10792 else
10793 /* For other cases Carry flag is not required. */
10795 /* Codes doable only with sign flag when comparing
10796 against zero, but we miss jump instruction for it
10797 so we need to use relational tests against overflow
10798 that thus needs to be zero. */
10803 else
10805 /* strcmp pattern do (use flags) and combine may ask us for proper
10806 mode. */
10811 }
10812 }
10814 /* Return the fixed registers used for condition codes. */
10816 static bool
10818 {
10822 }
10824 /* If two condition code modes are compatible, return a condition code
10825 mode which is compatible with both. Otherwise, return
10826 VOIDmode. */
10828 static enum machine_mode
10830 {
10842 {
10852 {
10862 }
10866 /* These are only compatible with themselves, which we already
10867 checked above. */
10869 }
10870 }
10872 /* Split comparison code CODE into comparisons we can do using branch
10873 instructions. BYPASS_CODE is comparison code for branch that will
10874 branch around FIRST_CODE and SECOND_CODE. If some of branches
10875 is not required, set value to UNKNOWN.
10876 We never require more than two branches. */
10878 void
10882 {
10887 /* The fcomi comparison sets flags as follows:
10889 cmp ZF PF CF
10890 > 0 0 0
10891 < 0 0 1
10892 = 1 0 0
10893 un 1 1 1 */
10896 {
10932 }
10934 {
10937 }
10938 }
10940 /* Return cost of comparison done fcom + arithmetics operations on AX.
10941 All following functions do use number of instructions as a cost metrics.
10942 In future this should be tweaked to compute bytes for optimize_size and
10943 take into account performance of various instructions on various CPUs. */
10944 static int
10946 {
10949 /* The cost of code output by ix86_expand_fp_compare. */
10951 {
10974 }
10975 }
10977 /* Return cost of comparison done using fcomi operation.
10978 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10979 static int
10981 {
10983 /* Return arbitrarily high cost when instruction is not supported - this
10984 prevents gcc from using it. */
10989 }
10991 /* Return cost of comparison done using sahf operation.
10992 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10993 static int
10995 {
10997 /* Return arbitrarily high cost when instruction is not preferred - this
10998 avoids gcc from using it. */
11003 }
11005 /* Compute cost of the comparison done using any method.
11006 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11007 static int
11009 {
11022 }
11024 /* Return true if we should use an FCOMI instruction for this
11025 fp comparison. */
11027 int
11029 {
11036 }
11038 /* Swap, force into registers, or otherwise massage the two operands
11039 to a fp comparison. The operands are updated in place; the new
11040 comparison code is returned. */
11042 static enum rtx_code
11044 {
11050 /* All of the unordered compare instructions only work on registers.
11051 The same is true of the fcomi compare instructions. The XFmode
11052 compare instructions require registers except when comparing
11053 against zero or when converting operand 1 from fixed point to
11054 floating point. */
11063 {
11066 }
11067 else
11068 {
11069 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11070 things around if they appear profitable, otherwise force op0
11071 into a register. */
11077 {
11078 rtx tmp;
11081 }
11087 {
11092 {
11095 }
11096 else
11098 }
11099 }
11101 /* Try to rearrange the comparison to make it cheaper. */
11105 {
11106 rtx tmp;
11111 }
11116 }
11118 /* Convert comparison codes we use to represent FP comparison to integer
11119 code that will result in proper branch. Return UNKNOWN if no such code
11120 is available. */
11122 enum rtx_code
11124 {
11126 {
11149 }
11150 }
11152 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11154 static rtx
11157 {
11173 /* Do fcomi/sahf based test when profitable. */
11178 {
11180 {
11183 tmp);
11185 }
11186 else
11187 {
11194 }
11196 /* The FP codes work out to act like unsigned. */
11202 const0_rtx);
11206 const0_rtx);
11207 }
11208 else
11209 {
11210 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11217 /* In the unordered case, we have to check C2 for NaN's, which
11218 doesn't happen to work out to anything nice combination-wise.
11219 So do some bit twiddling on the value we've got in AH to come
11220 up with an appropriate set of condition codes. */
11224 {
11228 {
11231 }
11232 else
11233 {
11239 }
11244 {
11249 }
11250 else
11251 {
11254 }
11259 {
11262 }
11263 else
11264 {
11269 }
11274 {
11280 }
11281 else
11282 {
11285 }
11290 {
11295 }
11296 else
11297 {
11301 }
11306 {
11311 }
11312 else
11313 {
11316 }
11330 }
11331 }
11333 /* Return the test that should be put into the flags user, i.e.
11334 the bcc, scc, or cmov instruction. */
11337 const0_rtx);
11338 }
11340 rtx
11342 {
11353 {
11356 }
11358 {
11362 }
11363 else
11367 }
11369 /* Return true if the CODE will result in nontrivial jump sequence. */
11370 bool
11372 {
11378 }
11380 void
11382 {
11383 rtx tmp;
11385 /* If we have emitted a compare insn, go straight to simple.
11386 ix86_expand_compare won't emit anything if ix86_compare_emitted
11387 is non NULL. */
11392 {
11396 simple:
11400 pc_rtx);
11407 {
11408 rtvec vec;
11417 /* Check whether we will use the natural sequence with one jump. If
11418 so, we can expand jump early. Otherwise delay expansion by
11419 creating compound insn to not confuse optimizers. */
11422 {
11426 }
11427 else
11428 {
11433 pc_rtx);
11448 }
11450 }
11456 /* Expand DImode branch into multiple compare+branch. */
11457 {
11463 {
11468 }
11470 {
11474 }
11475 else
11476 {
11480 }
11482 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
11483 avoid two branches. This costs one extra insn, so disable when
11484 optimizing for size. */
11487 && (!optimize_size
11489 {
11509 }
11511 /* Otherwise, if we are doing less-than or greater-or-equal-than,
11512 op1 is a constant and the low word is zero, then we can just
11513 examine the high word. */
11517 {
11525 }
11527 /* Otherwise, we need two or three jumps. */
11536 {
11550 }
11552 /*
11553 * a < b =>
11554 * if (hi(a) < hi(b)) goto true;
11555 * if (hi(a) > hi(b)) goto false;
11556 * if (lo(a) < lo(b)) goto true;
11557 * false:
11558 */
11575 }
11579 }
11580 }
11582 /* Split branch based on floating point condition. */
11583 void
11586 {
11589 rtx condition;
11591 rtx i;
11594 {
11599 }
11604 /* Remove pushed operand from stack. */
11609 {
11610 /* Distribute the probabilities across the jumps.
11611 Assume the BYPASS and SECOND to be always test
11612 for UNORDERED. */
11615 /* Value of 1 is low enough to make no need for probability
11616 to be updated. Later we may run some experiments and see
11617 if unordered values are more frequent in practice. */
11622 }
11624 {
11629 bypass,
11631 label),
11632 pc_rtx)));
11638 }
11649 {
11653 target2)));
11659 }
11662 }
11664 int
11666 {
11683 {
11688 {
11693 }
11699 else
11701 }
11703 /* Attach a REG_EQUAL note describing the comparison result. */
11705 {
11710 }
11713 }
11715 /* Expand comparison setting or clearing carry flag. Return true when
11716 successful and set pop for the operation. */
11717 static bool
11719 {
11723 /* Do not handle DImode compares that go through special path.
11724 Also we can't deal with FP compares yet. This is possible to add. */
11729 {
11735 /* Shortcut: following common codes never translate
11736 into carry flag compares. */
11741 /* These comparisons require zero flag; swap operands so they won't. */
11744 {
11749 }
11751 /* Try to expand the comparison and verify that we end up with carry flag
11752 based comparison. This is fails to be true only when we decide to expand
11753 comparison using arithmetic that is not too common scenario. */
11765 else
11772 }
11776 {
11781 /* Convert a==0 into (unsigned)a<1. */
11790 /* Convert a>b into b<a or a>=b-1. */
11794 {
11796 /* Bail out on overflow. We still can swap operands but that
11797 would force loading of the constant into register. */
11802 }
11803 else
11804 {
11809 }
11812 /* Convert a>=0 into (unsigned)a<0x80000000. */
11830 }
11831 /* Swapping operands may cause constant to appear as first operand. */
11833 {
11837 }
11843 }
11845 int
11847 {
11865 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
11866 HImode insns, we'd be swallowed in word prefix ops. */
11872 {
11876 HOST_WIDE_INT diff;
11879 /* Sign bit compares are better done using shifts than we do by using
11880 sbb. */
11884 {
11885 /* Detect overlap between destination and compare sources. */
11889 {
11896 {
11899 }
11901 /* To simplify rest of code, restrict to the GEU case. */
11903 {
11909 }
11910 else
11911 {
11914 reverse_condition_maybe_unordered
11916 else
11918 }
11927 else
11929 }
11930 else
11931 {
11934 else
11935 {
11940 }
11943 }
11946 {
11947 /*
11948 * cmpl op0,op1
11949 * sbbl dest,dest
11950 * [addl dest, ct]
11951 *
11952 * Size 5 - 8.
11953 */
11958 }
11960 {
11961 /*
11962 * cmpl op0,op1
11963 * sbbl dest,dest
11964 * orl $ct, dest
11965 *
11966 * Size 8.
11967 */
11971 }
11973 {
11974 /*
11975 * cmpl op0,op1
11976 * sbbl dest,dest
11977 * notl dest
11978 * [addl dest, cf]
11979 *
11980 * Size 8 - 11.
11981 */
11987 }
11988 else
11989 {
11990 /*
11991 * cmpl op0,op1
11992 * sbbl dest,dest
11993 * [notl dest]
11994 * andl cf - ct, dest
11995 * [addl dest, ct]
11996 *
11997 * Size 8 - 11.
11998 */
12001 {
12005 }
12015 }
12021 }
12024 {
12027 HOST_WIDE_INT tmp;
12032 {
12035 /* We may be reversing unordered compare to normal compare, that
12036 is not valid in general (we may convert non-trapping condition
12037 to trapping one), however on i386 we currently emit all
12038 comparisons unordered. */
12041 }
12042 else
12043 {
12046 }
12047 }
12052 {
12057 {
12062 }
12063 }
12065 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12069 {
12070 /* If lea code below could be used, only optimize
12071 if it results in a 2 insn sequence. */
12077 {
12078 /*
12079 * notl op1 (if necessary)
12080 * sarl $31, op1
12081 * orl cf, op1
12082 */
12084 {
12088 }
12100 }
12101 }
12109 {
12110 /*
12111 * xorl dest,dest
12112 * cmpl op1,op2
12113 * setcc dest
12114 * lea cf(dest*(ct-cf)),dest
12115 *
12116 * Size 14.
12117 *
12118 * This also catches the degenerate setcc-only case.
12119 */
12121 rtx tmp;
12128 /* On x86_64 the lea instruction operates on Pmode, so we need
12129 to get arithmetics done in proper mode to match. */
12132 else
12133 {
12134 rtx out1;
12137 nops++;
12139 {
12141 nops++;
12142 }
12143 }
12145 {
12147 nops++;
12148 }
12150 {
12153 else
12155 }
12160 }
12162 /*
12163 * General case: Jumpful:
12164 * xorl dest,dest cmpl op1, op2
12165 * cmpl op1, op2 movl ct, dest
12166 * setcc dest jcc 1f
12167 * decl dest movl cf, dest
12168 * andl (cf-ct),dest 1:
12169 * addl ct,dest
12170 *
12171 * Size 20. Size 14.
12172 *
12173 * This is reasonably steep, but branch mispredict costs are
12174 * high on modern cpus, so consider failing only if optimizing
12175 * for space.
12176 */
12180 {
12182 {
12189 {
12192 /* We may be reversing unordered compare to normal compare,
12193 that is not valid in general (we may convert non-trapping
12194 condition to trapping one), however on i386 we currently
12195 emit all comparisons unordered. */
12197 }
12198 else
12199 {
12203 }
12204 }
12207 {
12208 /* notl op1 (if needed)
12209 sarl $31, op1
12210 andl (cf-ct), op1
12211 addl ct, op1
12213 For x < 0 (resp. x <= -1) there will be no notl,
12214 so if possible swap the constants to get rid of the
12215 complement.
12216 True/false will be -1/0 while code below (store flag
12217 followed by decrement) is 0/-1, so the constants need
12218 to be exchanged once more. */
12221 {
12224 }
12225 else
12226 {
12230 }
12234 }
12235 else
12236 {
12242 }
12254 }
12255 }
12258 {
12259 /* Try a few things more with specific constants and a variable. */
12261 optab op;
12267 /* If one of the two operands is an interesting constant, load a
12268 constant with the above and mask it in with a logical operation. */
12271 {
12277 else
12279 }
12281 {
12287 else
12289 }
12290 else
12297 /* Recurse to get the constant loaded. */
12301 /* Mask in the interesting variable. */
12303 OPTAB_WIDEN);
12308 }
12310 /*
12311 * For comparison with above,
12312 *
12313 * movl cf,dest
12314 * movl ct,tmp
12315 * cmpl op1,op2
12316 * cmovcc tmp,dest
12317 *
12318 * Size 15.
12319 */
12327 {
12331 }
12333 {
12337 }
12356 bypass_test,
12362 second_test,
12367 }
12369 /* Swap, force into registers, or otherwise massage the two operands
12370 to an sse comparison with a mask result. Thus we differ a bit from
12371 ix86_prepare_fp_compare_args which expects to produce a flags result.
12373 The DEST operand exists to help determine whether to commute commutative
12374 operators. The POP0/POP1 operands are updated in place. The new
12375 comparison code is returned, or UNKNOWN if not implementable. */
12377 static enum rtx_code
12380 {
12381 rtx tmp;
12384 {
12387 /* We have no LTGT as an operator. We could implement it with
12388 NE & ORDERED, but this requires an extra temporary. It's
12389 not clear that it's worth it. */
12396 /* These are supported directly. */
12403 /* For commutative operators, try to canonicalize the destination
12404 operand to be first in the comparison - this helps reload to
12405 avoid extra moves. */
12408 /* FALLTHRU */
12414 /* These are not supported directly. Swap the comparison operands
12415 to transform into something that is supported. */
12424 }
12427 }
12429 /* Detect conditional moves that exactly match min/max operational
12430 semantics. Note that this is IEEE safe, as long as we don't
12431 interchange the operands.
12433 Returns FALSE if this conditional move doesn't match a MIN/MAX,
12434 and TRUE if the operation is successful and instructions are emitted. */
12436 static bool
12439 {
12442 rtx tmp;
12445 ;
12447 {
12451 }
12452 else
12459 else
12464 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
12465 but MODE may be a vector mode and thus not appropriate. */
12467 {
12469 rtvec v;
12474 }
12475 else
12476 {
12479 }
12483 }
12485 /* Expand an sse vector comparison. Return the register with the result. */
12487 static rtx
12490 {
12492 rtx x;
12507 }
12509 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
12510 operations. This is used for both scalar and vector conditional moves. */
12512 static void
12514 {
12519 {
12523 }
12525 {
12530 }
12531 else
12532 {
12539 else
12551 }
12552 }
12554 /* Expand a floating-point conditional move. Return true if successful. */
12556 int
12558 {
12564 {
12567 /* Since we've no cmove for sse registers, don't force bad register
12568 allocation just to gain access to it. Deny movcc when the
12569 comparison mode doesn't match the move mode. */
12591 }
12593 /* The floating point conditional move instructions don't directly
12594 support conditions resulting from a signed integer comparison. */
12598 /* The floating point conditional move instructions don't directly
12599 support signed integer comparisons. */
12602 {
12610 }
12612 {
12616 }
12618 {
12622 }
12637 }
12639 /* Expand a floating-point vector conditional move; a vcond operation
12640 rather than a movcc operation. */
12642 bool
12644 {
12646 rtx cmp;
12661 }
12663 /* Expand a signed integral vector conditional move. */
12665 bool
12667 {
12676 /* Canonicalize the comparison to EQ, GT, GTU. */
12678 {
12695 /* FALLTHRU */
12705 }
12707 /* Unsigned parallel compare is not supported by the hardware. Play some
12708 tricks to turn this into a signed comparison against 0. */
12710 {
12714 {
12716 {
12719 /* Perform a parallel modulo subtraction. */
12723 /* Extract the original sign bit of op0. */
12731 /* XOR it back into the result of the subtraction. This results
12732 in the sign bit set iff we saw unsigned underflow. */
12737 }
12742 /* Perform a parallel unsigned saturating subtraction. */
12753 }
12757 }
12765 }
12767 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
12768 true if we should do zero extension, else sign extension. HIGH_P is
12769 true if we want the N/2 high elements, else the low elements. */
12771 void
12773 {
12779 {
12783 else
12789 else
12795 else
12800 }
12806 else
12811 }
12813 /* Expand conditional increment or decrement using adb/sbb instructions.
12814 The default case using setcc followed by the conditional move can be
12815 done by generic code. */
12816 int
12818 {
12820 rtx compare_op;
12835 {
12838 }
12841 {
12845 reverse_condition_maybe_unordered
12847 else
12849 }
12852 /* Construct either adc or sbb insn. */
12854 {
12856 {
12871 }
12872 }
12873 else
12874 {
12876 {
12891 }
12892 }
12894 }
12897 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
12898 works for floating pointer parameters and nonoffsetable memories.
12899 For pushes, it returns just stack offsets; the values will be saved
12900 in the right order. Maximally three parts are generated. */
12902 static int
12904 {
12909 else
12915 /* Optimize constant pool reference to immediates. This is used by fp
12916 moves, that force all constants to memory to allow combining. */
12918 {
12922 }
12925 {
12926 /* The only non-offsetable memories we handle are pushes. */
12935 }
12938 {
12940 /* Caution: if we looked through a constant pool memory above,
12941 the operand may actually have a different mode now. That's
12942 ok, since we want to pun this all the way back to an integer. */
12946 }
12949 {
12952 else
12953 {
12955 {
12961 }
12963 {
12969 }
12971 {
12972 REAL_VALUE_TYPE r;
12977 {
12987 }
12990 }
12991 else
12993 }
12994 }
12995 else
12996 {
13000 {
13003 {
13007 }
13009 {
13013 }
13015 {
13016 REAL_VALUE_TYPE r;
13022 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13025 = gen_int_mode
13028 DImode);
13029 else
13036 = gen_int_mode
13039 DImode);
13040 else
13042 }
13043 else
13045 }
13046 }
13049 }
13051 /* Emit insns to perform a move or push of DI, DF, and XF values.
13052 Return false when normal moves are needed; true when all required
13053 insns have been emitted. Operands 2-4 contain the input values
13054 int the correct order; operands 5-7 contain the output values. */
13056 void
13058 {
13065 /* The DFmode expanders may ask us to move double.
13066 For 64bit target this is single move. By hiding the fact
13067 here we simplify i386.md splitters. */
13069 {
13070 /* Optimize constant pool reference to immediates. This is used by
13071 fp moves, that force all constants to memory to allow combining. */
13078 {
13081 }
13082 else
13087 }
13089 /* The only non-offsettable memory we handle is push. */
13092 else
13099 /* When emitting push, take care for source operands on the stack. */
13102 {
13108 }
13110 /* We need to do copy in the right order in case an address register
13111 of the source overlaps the destination. */
13113 {
13115 collisions++;
13117 collisions++;
13120 collisions++;
13122 /* Collision in the middle part can be handled by reordering. */
13125 {
13126 rtx tmp;
13129 }
13131 /* If there are more collisions, we can't handle it by reordering.
13132 Do an lea to the last part and use only one colliding move. */
13134 {
13135 rtx base;
13141 /* Handle the case when the last part isn't valid for lea.
13142 Happens in 64-bit mode storing the 12-byte XFmode. */
13153 }
13154 }
13157 {
13159 {
13161 {
13165 }
13166 }
13167 else
13168 {
13169 /* In 64bit mode we don't have 32bit push available. In case this is
13170 register, it is OK - we will just use larger counterpart. We also
13171 retype memory - these comes from attempt to avoid REX prefix on
13172 moving of second half of TFmode value. */
13174 {
13176 {
13187 }
13191 }
13192 }
13196 }
13198 /* Choose correct order to not overwrite the source before it is copied. */
13206 {
13208 {
13215 }
13216 else
13217 {
13222 }
13223 }
13224 else
13225 {
13227 {
13234 }
13235 else
13236 {
13241 }
13242 }
13244 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
13246 {
13250 {
13259 }
13268 }
13276 }
13278 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
13279 left shift by a constant, either using a single shift or
13280 a sequence of add instructions. */
13282 static void
13284 {
13286 {
13288 ? gen_addsi3
13290 }
13293 {
13296 {
13298 ? gen_addsi3
13300 }
13301 }
13302 else
13304 ? gen_ashlsi3
13306 }
13308 void
13310 {
13316 {
13321 {
13327 }
13328 else
13329 {
13333 ? gen_x86_shld_1
13336 }
13338 }
13343 {
13344 /* Assuming we've chosen a QImode capable registers, then 1 << N
13345 can be done with two 32/64-bit shifts, no branches, no cmoves. */
13347 {
13363 }
13365 /* Otherwise, we can get the same results by manually performing
13366 a bit extract operation on bit 5/6, and then performing the two
13367 shifts. The two methods of getting 0/1 into low/high are exactly
13368 the same size. Avoiding the shift in the bit extract case helps
13369 pentium4 a bit; no one else seems to care much either way. */
13370 else
13371 {
13372 rtx x;
13376 else
13381 ? gen_lshrsi3
13384 ? gen_andsi3
13388 ? gen_xorsi3
13390 }
13393 ? gen_ashlsi3
13396 ? gen_ashlsi3
13399 }
13402 {
13403 /* For -1 << N, we can avoid the shld instruction, because we
13404 know that we're shifting 0...31/63 ones into a -1. */
13408 else
13410 }
13411 else
13412 {
13418 ? gen_x86_shld_1
13420 }
13425 {
13428 ? gen_x86_shift_adj_1
13430 }
13431 else
13433 }
13435 void
13437 {
13443 {
13448 {
13451 ? gen_ashrsi3
13456 }
13458 {
13462 ? gen_ashrsi3
13467 ? gen_ashrsi3
13470 }
13471 else
13472 {
13476 ? gen_x86_shrd_1
13479 ? gen_ashrsi3
13481 }
13482 }
13483 else
13484 {
13491 ? gen_x86_shrd_1
13494 ? gen_ashrsi3
13498 {
13501 ? gen_ashrsi3
13505 ? gen_x86_shift_adj_1
13507 scratch));
13508 }
13509 else
13511 }
13512 }
13514 void
13516 {
13522 {
13527 {
13533 ? gen_lshrsi3
13536 }
13537 else
13538 {
13542 ? gen_x86_shrd_1
13545 ? gen_lshrsi3
13547 }
13548 }
13549 else
13550 {
13557 ? gen_x86_shrd_1
13560 ? gen_lshrsi3
13563 /* Heh. By reversing the arguments, we can reuse this pattern. */
13565 {
13568 ? gen_x86_shift_adj_1
13570 scratch));
13571 }
13572 else
13574 }
13575 }
13577 /* Predict just emitted jump instruction to be taken with probability PROB. */
13578 static void
13580 {
13587 }
13589 /* Helper function for the string operations below. Dest VARIABLE whether
13590 it is aligned to VALUE bytes. If true, jump to the label. */
13591 static rtx
13593 {
13598 else
13604 else
13607 }
13609 /* Adjust COUNTER by the VALUE. */
13610 static void
13612 {
13615 else
13617 }
13619 /* Zero extend possibly SImode EXP to Pmode register. */
13620 rtx
13622 {
13623 rtx r;
13631 }
13633 /* Divide COUNTREG by SCALE. */
13634 static rtx
13636 {
13637 rtx sc;
13638 rtx piece_size_mask;
13651 }
13653 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
13654 DImode for constant loop counts. */
13656 static enum machine_mode
13658 {
13666 }
13668 /* When SRCPTR is non-NULL, output simple loop to move memory
13669 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
13670 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
13671 equivalent loop to set memory by VALUE (supposed to be in MODE).
13673 The size is rounded down to whole number of chunk size moved at once.
13674 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
13677 static void
13682 {
13687 rtx size;
13688 rtx x_addr;
13689 rtx y_addr;
13698 /* Those two should combine. */
13700 {
13704 }
13714 {
13718 /* When unrolling for chips that reorder memory reads and writes,
13719 we can save registers by using single temporary.
13720 Also using 4 temporaries is overkill in 32bit mode. */
13722 {
13724 {
13726 {
13727 destmem =
13729 srcmem =
13731 }
13733 }
13734 }
13735 else
13736 {
13740 {
13743 {
13744 srcmem =
13746 }
13748 }
13750 {
13752 {
13753 destmem =
13755 }
13757 }
13758 }
13759 }
13760 else
13762 {
13764 destmem =
13767 }
13777 {
13783 else
13785 }
13786 else
13794 {
13799 }
13801 }
13803 /* Output "rep; mov" instruction.
13804 Arguments have same meaning as for previous function */
13805 static void
13808 rtx count,
13810 {
13811 rtx destexp;
13812 rtx srcexp;
13813 rtx countreg;
13815 /* If the size is known, it is shorter to use rep movs. */
13826 {
13833 }
13834 else
13835 {
13838 }
13841 }
13843 /* Output "rep; stos" instruction.
13844 Arguments have same meaning as for previous function */
13845 static void
13847 rtx count,
13849 {
13850 rtx destexp;
13851 rtx countreg;
13858 {
13862 }
13863 else
13866 }
13868 static void
13871 {
13875 }
13877 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
13878 static void
13881 {
13884 {
13889 {
13891 {
13894 }
13895 else
13898 }
13900 {
13903 else
13904 {
13907 }
13909 }
13911 {
13914 }
13916 {
13919 }
13921 {
13924 }
13926 }
13928 {
13934 }
13936 /* When there are stringops, we can cheaply increase dest and src pointers.
13937 Otherwise we save code size by maintaining offset (zero is readily
13938 available from preceding rep operation) and using x86 addressing modes.
13939 */
13941 {
13943 {
13950 }
13952 {
13959 }
13961 {
13968 }
13969 }
13970 else
13971 {
13973 rtx tmp;
13976 {
13987 }
13989 {
14002 }
14004 {
14013 }
14014 }
14015 }
14017 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14018 static void
14021 {
14022 count =
14028 }
14030 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14031 static void
14033 {
14034 rtx dest;
14037 {
14042 {
14044 {
14049 }
14050 else
14053 }
14055 {
14057 {
14060 }
14061 else
14062 {
14067 }
14069 }
14071 {
14075 }
14077 {
14081 }
14083 {
14087 }
14089 }
14091 {
14094 }
14096 {
14099 {
14103 }
14104 else
14105 {
14111 }
14114 }
14116 {
14119 {
14122 }
14123 else
14124 {
14128 }
14131 }
14133 {
14139 }
14141 {
14147 }
14149 {
14155 }
14156 }
14158 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
14159 DESIRED_ALIGNMENT. */
14160 static void
14164 {
14166 {
14174 }
14176 {
14184 }
14186 {
14194 }
14196 }
14198 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
14199 DESIRED_ALIGNMENT. */
14200 static void
14203 {
14205 {
14212 }
14214 {
14221 }
14223 {
14230 }
14232 }
14234 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
14235 static enum stringop_alg
14238 {
14244 else
14248 /* rep; movq or rep; movl is the smallest variant. */
14250 {
14253 else
14255 }
14256 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
14257 */
14261 {
14265 {
14268 {
14271 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
14272 last non-libcall inline algorithm. */
14274 {
14275 /* When the current size is best to be copied by a libcall,
14276 but we are still forced to inline, run the heuristic bellow
14277 that will pick code for medium sized blocks. */
14281 }
14282 else
14284 }
14285 }
14287 }
14288 /* When asked to inline the call anyway, try to pick meaningful choice.
14289 We look for maximal size of block that is faster to copy by hand and
14290 take blocks of at most of that size guessing that average size will
14291 be roughly half of the block.
14293 If this turns out to be bad, we might simply specify the preferred
14294 choice in ix86_costs. */
14297 {
14313 }
14315 }
14317 /* Decide on alignment. We know that the operand is already aligned to ALIGN
14318 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
14319 static int
14323 {
14326 {
14337 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14338 copying whole cacheline at once. */
14341 else
14345 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14346 copying whole cacheline at once. */
14349 else
14357 }
14366 }
14368 /* Return the smallest power of 2 greater than VAL. */
14369 static int
14371 {
14376 }
14378 /* Expand string move (memcpy) operation. Use i386 string operations when
14379 profitable. expand_clrmem contains similar code. The code depends upon
14380 architecture, block size and alignment, but always has the same
14381 overall structure:
14383 1) Prologue guard: Conditional that jumps up to epilogues for small
14384 blocks that can be handled by epilogue alone. This is faster but
14385 also needed for correctness, since prologue assume the block is larger
14386 than the desired alignment.
14388 Optional dynamic check for size and libcall for large
14389 blocks is emitted here too, with -minline-stringops-dynamically.
14391 2) Prologue: copy first few bytes in order to get destination aligned
14392 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
14393 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
14394 We emit either a jump tree on power of two sized blocks, or a byte loop.
14396 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
14397 with specified algorithm.
14399 4) Epilogue: code copying tail of the block that is too small to be
14400 handled by main body (or up to size guarded by prologue guard). */
14402 int
14405 {
14406 rtx destreg;
14407 rtx srcreg;
14409 rtx tmp;
14421 /* i386 can do misaligned access on reasonably increased cost. */
14430 /* Step 0: Decide on preferred algorithm, desired alignment and
14431 size of chunks to be copied by main loop. */
14447 {
14467 }
14471 /* Step 1: Prologue guard. */
14473 /* Alignment code needs count to be in register. */
14475 {
14480 }
14483 /* Ensure that alignment prologue won't copy past end of block. */
14485 {
14487 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14488 Make sure it is power of 2. */
14496 ;
14499 else
14501 }
14502 /* Emit code to decide on runtime whether library call or inline should be
14503 used. */
14505 {
14514 }
14516 /* Step 2: Alignment prologue. */
14519 {
14520 /* Except for the first move in epilogue, we no longer know
14521 constant offset in aliasing info. It don't seems to worth
14522 the pain to maintain it for the first move, so throw away
14523 the info early. */
14527 desired_align);
14528 }
14530 {
14534 }
14536 /* Step 3: Main loop. */
14539 {
14552 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
14553 registers for 4 temporaries anyway. */
14556 expected_size);
14560 DImode);
14564 SImode);
14568 QImode);
14570 }
14571 /* Adjust properly the offset of src and dest memory for aliasing. */
14573 {
14578 }
14579 else
14580 {
14583 }
14585 /* Step 4: Epilogue to copy the remaining bytes. */
14588 {
14589 /* When the main loop is done, COUNT_EXP might hold original count,
14590 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14591 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14592 bytes. Compensate if needed. */
14595 {
14596 tmp =
14599 OPTAB_DIRECT);
14602 }
14605 }
14609 epilogue_size_needed);
14613 }
14615 /* Helper function for memcpy. For QImode value 0xXY produce
14616 0xXYXYXYXY of wide specified by MODE. This is essentially
14617 a * 0x10101010, but we can do slightly better than
14618 synth_mult by unwinding the sequence by hand on CPUs with
14619 slow multiply. */
14620 static rtx
14622 {
14624 rtx tmp;
14631 {
14639 }
14648 nops--;
14653 {
14657 OPTAB_DIRECT);
14658 }
14659 else
14660 {
14666 else
14668 else
14669 {
14672 reg =
14674 }
14684 }
14685 }
14687 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
14688 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
14689 alignment from ALIGN to DESIRED_ALIGN. */
14690 static rtx
14692 {
14693 rtx promoted_val;
14702 else
14706 }
14708 /* Expand string clear operation (bzero). Use i386 string operations when
14709 profitable. See expand_movmem comment for explanation of individual
14710 steps performed. */
14711 int
14714 {
14715 rtx destreg;
14717 rtx tmp;
14731 /* i386 can do misaligned access on reasonably increased cost. */
14740 /* Step 0: Decide on preferred algorithm, desired alignment and
14741 size of chunks to be copied by main loop. */
14756 {
14776 }
14779 /* Step 1: Prologue guard. */
14781 /* Alignment code needs count to be in register. */
14783 {
14788 }
14789 /* Do the cheap promotion to allow better CSE across the
14790 main loop and epilogue (ie one load of the big constant in the
14791 front of all code. */
14795 /* Ensure that alignment prologue won't copy past end of block. */
14797 {
14799 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14800 Make sure it is power of 2. */
14803 /* To improve performance of small blocks, we jump around the VAL
14804 promoting mode. This mean that if the promoted VAL is not constant,
14805 we might not use it in the epilogue and have to use byte
14806 loop variant. */
14814 ;
14817 else
14819 }
14821 {
14830 }
14832 /* Step 2: Alignment prologue. */
14834 /* Do the expensive promotion once we branched off the small blocks. */
14841 {
14842 /* Except for the first move in epilogue, we no longer know
14843 constant offset in aliasing info. It don't seems to worth
14844 the pain to maintain it for the first move, so throw away
14845 the info early. */
14848 desired_align);
14849 }
14851 {
14855 }
14857 /* Step 3: Main loop. */
14860 {
14878 DImode);
14882 SImode);
14886 QImode);
14888 }
14889 /* Adjust properly the offset of src and dest memory for aliasing. */
14893 else
14896 /* Step 4: Epilogue to copy the remaining bytes. */
14899 {
14900 /* When the main loop is done, COUNT_EXP might hold original count,
14901 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14902 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14903 bytes. Compensate if needed. */
14906 {
14907 tmp =
14910 OPTAB_DIRECT);
14914 }
14917 }
14919 {
14922 size_needed);
14923 else
14925 size_needed);
14926 }
14930 }
14932 /* Expand the appropriate insns for doing strlen if not just doing
14933 repnz; scasb
14935 out = result, initialized with the start address
14936 align_rtx = alignment of the address.
14937 scratch = scratch register, initialized with the startaddress when
14938 not aligned, otherwise undefined
14940 This is just the body. It needs the initializations mentioned above and
14941 some address computing at the end. These things are done in i386.md. */
14943 static void
14945 {
14947 rtx tmp;
14952 rtx mem;
14955 rtx cmp;
14961 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
14963 /* Is there a known alignment and is it less than 4? */
14965 {
14968 /* Is there a known alignment and is it not 2? */
14970 {
14974 /* Leave just the 3 lower bits. */
14984 }
14985 else
14986 {
14987 /* Since the alignment is 2, we have to check 2 or 0 bytes;
14988 check if is aligned to 4 - byte. */
14995 }
14999 /* Now compare the bytes. */
15001 /* Compare the first n unaligned byte on a byte per byte basis. */
15005 /* Increment the address. */
15008 else
15011 /* Not needed with an alignment of 2 */
15013 {
15017 end_0_label);
15021 else
15025 }
15028 end_0_label);
15032 else
15034 }
15036 /* Generate loop to check 4 bytes at a time. It is not a good idea to
15037 align this loop. It gives only huge programs, but does not help to
15038 speed up. */
15045 else
15048 /* This formula yields a nonzero result iff one of the bytes is zero.
15049 This saves three branches inside loop and many cycles. */
15057 align_4_label);
15060 {
15066 /* If zero is not in the first two bytes, move two bytes forward. */
15072 reg,
15073 tmpreg)));
15074 /* Emit lea manually to avoid clobbering of flags. */
15082 reg2,
15083 out)));
15085 }
15086 else
15087 {
15089 /* Is zero in the first two bytes? */
15096 pc_rtx);
15100 /* Not in the first two. Move two bytes forward. */
15104 else
15109 }
15111 /* Avoid branch in fixing the byte. */
15117 else
15121 }
15123 /* Expand strlen. */
15125 int
15127 {
15130 /* The generic case of strlen expander is long. Avoid it's
15131 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
15134 && !TARGET_INLINE_ALL_STRINGOPS
15135 && !optimize_size
15144 {
15145 /* Well it seems that some optimizer does not combine a call like
15146 foo(strlen(bar), strlen(bar));
15147 when the move and the subtraction is done here. It does calculate
15148 the length just once when these instructions are done inside of
15149 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
15150 often used and I use one fewer register for the lifetime of
15151 output_strlen_unroll() this is better. */
15157 /* strlensi_unroll_1 returns the address of the zero at the end of
15158 the string, like memchr(), so compute the length by subtracting
15159 the start address. */
15162 else
15164 }
15165 else
15166 {
15167 rtx unspec;
15177 /* If .md starts supporting :P, this can be done in .md. */
15182 {
15185 }
15186 else
15187 {
15190 }
15191 }
15193 }
15195 /* For given symbol (function) construct code to compute address of it's PLT
15196 entry in large x86-64 PIC model. */
15197 rtx
15199 {
15209 }
15211 void
15213 rtx callarg2 ATTRIBUTE_UNUSED,
15215 {
15223 {
15224 #if TARGET_MACHO
15227 #endif
15228 }
15229 else
15230 {
15231 /* Static functions and indirect calls don't need the pic register. */
15236 }
15239 {
15243 }
15251 {
15254 }
15257 {
15258 rtx addr;
15263 }
15269 {
15273 }
15278 }
15280 \f
15281 /* Clear stack slot assignments remembered from previous functions.
15282 This is called from INIT_EXPANDERS once before RTL is emitted for each
15283 function. */
15287 {
15295 }
15297 /* Return a MEM corresponding to a stack slot with mode MODE.
15298 Allocate a new slot if necessary.
15300 The RTL for a function can have several slots available: N is
15301 which slot to use. */
15303 rtx
15305 {
15323 }
15325 /* Construct the SYMBOL_REF for the tls_get_addr function. */
15328 rtx
15330 {
15333 {
15335 (TARGET_ANY_GNU_TLS
15339 }
15342 }
15344 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
15347 rtx
15349 {
15352 {
15357 }
15360 }
15361 \f
15362 /* Calculate the length of the memory address in the instruction
15363 encoding. Does not include the one-byte modrm, opcode, or prefix. */
15365 int
15367 {
15392 /* Rule of thumb:
15393 - esp as the base always wants an index,
15394 - ebp as the base always wants a displacement. */
15396 /* Register Indirect. */
15398 {
15399 /* esp (for its index) and ebp (for its displacement) need
15400 the two-byte modrm form. */
15406 }
15408 /* Direct Addressing. */
15412 else
15413 {
15414 /* Find the length of the displacement constant. */
15416 {
15419 else
15421 }
15422 /* ebp always wants a displacement. */
15426 /* An index requires the two-byte modrm form.... */
15428 /* ...like esp, which always wants an index. */
15433 }
15436 }
15438 /* Compute default value for "length_immediate" attribute. When SHORTFORM
15439 is set, expect that insn have 8bit immediate alternative. */
15440 int
15442 {
15448 {
15452 else
15453 {
15455 {
15465 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
15471 }
15472 }
15473 }
15475 }
15476 /* Compute default value for "length_address" attribute. */
15477 int
15479 {
15483 {
15492 }
15497 {
15500 }
15502 }
15503 \f
15504 /* Return the maximum number of instructions a cpu can issue. */
15506 static int
15508 {
15510 {
15530 }
15531 }
15533 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
15534 by DEP_INSN and nothing set by DEP_INSN. */
15536 static int
15538 {
15541 /* Simplify the test for uninteresting insns. */
15549 {
15552 }
15557 {
15560 }
15561 else
15567 /* This test is true if the dependent insn reads the flags but
15568 not any other potentially set register. */
15576 }
15578 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
15579 address with operands set by DEP_INSN. */
15581 static int
15583 {
15584 rtx addr;
15588 {
15597 }
15598 else
15599 {
15604 {
15607 }
15609 found:;
15610 }
15613 }
15615 static int
15617 {
15623 /* Anti and output dependencies have zero cost on all CPUs. */
15629 /* If we can't recognize the insns, we can't really do anything. */
15637 {
15639 /* Address Generation Interlock adds a cycle of latency. */
15643 /* ??? Compares pair with jump/setcc. */
15647 /* Floating point stores require value to be ready one cycle earlier. */
15657 /* INT->FP conversion is expensive. */
15661 /* There is one cycle extra latency between an FP op and a store. */
15669 /* Show ability of reorder buffer to hide latency of load by executing
15670 in parallel with previous instruction in case
15671 previous instruction is not needed to compute the address. */
15674 {
15675 /* Claim moves to take one cycle, as core can issue one load
15676 at time and the next load can start cycle later. */
15681 cost--;
15682 }
15688 /* The esp dependency is resolved before the instruction is really
15689 finished. */
15694 /* INT->FP conversion is expensive. */
15698 /* Show ability of reorder buffer to hide latency of load by executing
15699 in parallel with previous instruction in case
15700 previous instruction is not needed to compute the address. */
15703 {
15704 /* Claim moves to take one cycle, as core can issue one load
15705 at time and the next load can start cycle later. */
15711 else
15713 }
15723 /* Show ability of reorder buffer to hide latency of load by executing
15724 in parallel with previous instruction in case
15725 previous instruction is not needed to compute the address. */
15728 {
15732 /* Because of the difference between the length of integer and
15733 floating unit pipeline preparation stages, the memory operands
15734 for floating point are cheaper.
15736 ??? For Athlon it the difference is most probably 2. */
15739 else
15744 else
15746 }
15750 }
15753 }
15755 /* How many alternative schedules to try. This should be as wide as the
15756 scheduling freedom in the DFA, but no wider. Making this value too
15757 large results extra work for the scheduler. */
15759 static int
15761 {
15769 else
15771 }
15773 \f
15774 /* Compute the alignment given to a constant that is being placed in memory.
15775 EXP is the constant and ALIGN is the alignment that the object would
15776 ordinarily have.
15777 The value of this function is used instead of that alignment to align
15778 the object. */
15780 int
15782 {
15784 {
15789 }
15795 }
15797 /* Compute the alignment for a static variable.
15798 TYPE is the data type, and ALIGN is the alignment that
15799 the object would ordinarily have. The value of this function is used
15800 instead of that alignment to align the object. */
15802 int
15804 {
15815 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15816 to 16byte boundary. */
15818 {
15825 }
15828 {
15833 }
15835 {
15841 }
15846 {
15851 }
15854 {
15859 }
15862 }
15864 /* Compute the alignment for a local variable.
15865 TYPE is the data type, and ALIGN is the alignment that
15866 the object would ordinarily have. The value of this macro is used
15867 instead of that alignment to align the object. */
15869 int
15871 {
15872 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15873 to 16byte boundary. */
15875 {
15882 }
15884 {
15889 }
15891 {
15896 }
15901 {
15906 }
15909 {
15915 }
15917 }
15918 \f
15919 /* Emit RTL insns to initialize the variable parts of a trampoline.
15920 FNADDR is an RTX for the address of the function's pure code.
15921 CXT is an RTX for the static chain value for the function. */
15922 void
15924 {
15926 {
15927 /* Compute offset from the end of the jmp to the target function. */
15937 }
15938 else
15939 {
15941 /* Try to load address using shorter movl instead of movabs.
15942 We may want to support movq for kernel mode, but kernel does not use
15943 trampolines at the moment. */
15945 {
15952 }
15953 else
15954 {
15958 fnaddr);
15960 }
15961 /* Load static chain using movabs to r10. */
15965 cxt);
15967 /* Jump to the r11 */
15974 }
15976 #ifdef ENABLE_EXECUTE_STACK
15979 #endif
15980 }
15981 \f
15982 /* Codes for all the SSE/MMX builtins. */
15983 enum ix86_builtins
15984 {
15985 IX86_BUILTIN_ADDPS,
15986 IX86_BUILTIN_ADDSS,
15987 IX86_BUILTIN_DIVPS,
15988 IX86_BUILTIN_DIVSS,
15989 IX86_BUILTIN_MULPS,
15990 IX86_BUILTIN_MULSS,
15991 IX86_BUILTIN_SUBPS,
15992 IX86_BUILTIN_SUBSS,
15994 IX86_BUILTIN_CMPEQPS,
15995 IX86_BUILTIN_CMPLTPS,
15996 IX86_BUILTIN_CMPLEPS,
15997 IX86_BUILTIN_CMPGTPS,
15998 IX86_BUILTIN_CMPGEPS,
15999 IX86_BUILTIN_CMPNEQPS,
16000 IX86_BUILTIN_CMPNLTPS,
16001 IX86_BUILTIN_CMPNLEPS,
16002 IX86_BUILTIN_CMPNGTPS,
16003 IX86_BUILTIN_CMPNGEPS,
16004 IX86_BUILTIN_CMPORDPS,
16005 IX86_BUILTIN_CMPUNORDPS,
16006 IX86_BUILTIN_CMPEQSS,
16007 IX86_BUILTIN_CMPLTSS,
16008 IX86_BUILTIN_CMPLESS,
16009 IX86_BUILTIN_CMPNEQSS,
16010 IX86_BUILTIN_CMPNLTSS,
16011 IX86_BUILTIN_CMPNLESS,
16012 IX86_BUILTIN_CMPNGTSS,
16013 IX86_BUILTIN_CMPNGESS,
16014 IX86_BUILTIN_CMPORDSS,
16015 IX86_BUILTIN_CMPUNORDSS,
16017 IX86_BUILTIN_COMIEQSS,
16018 IX86_BUILTIN_COMILTSS,
16019 IX86_BUILTIN_COMILESS,
16020 IX86_BUILTIN_COMIGTSS,
16021 IX86_BUILTIN_COMIGESS,
16022 IX86_BUILTIN_COMINEQSS,
16023 IX86_BUILTIN_UCOMIEQSS,
16024 IX86_BUILTIN_UCOMILTSS,
16025 IX86_BUILTIN_UCOMILESS,
16026 IX86_BUILTIN_UCOMIGTSS,
16027 IX86_BUILTIN_UCOMIGESS,
16028 IX86_BUILTIN_UCOMINEQSS,
16030 IX86_BUILTIN_CVTPI2PS,
16031 IX86_BUILTIN_CVTPS2PI,
16032 IX86_BUILTIN_CVTSI2SS,
16033 IX86_BUILTIN_CVTSI642SS,
16034 IX86_BUILTIN_CVTSS2SI,
16035 IX86_BUILTIN_CVTSS2SI64,
16036 IX86_BUILTIN_CVTTPS2PI,
16037 IX86_BUILTIN_CVTTSS2SI,
16038 IX86_BUILTIN_CVTTSS2SI64,
16040 IX86_BUILTIN_MAXPS,
16041 IX86_BUILTIN_MAXSS,
16042 IX86_BUILTIN_MINPS,
16043 IX86_BUILTIN_MINSS,
16045 IX86_BUILTIN_LOADUPS,
16046 IX86_BUILTIN_STOREUPS,
16047 IX86_BUILTIN_MOVSS,
16049 IX86_BUILTIN_MOVHLPS,
16050 IX86_BUILTIN_MOVLHPS,
16051 IX86_BUILTIN_LOADHPS,
16052 IX86_BUILTIN_LOADLPS,
16053 IX86_BUILTIN_STOREHPS,
16054 IX86_BUILTIN_STORELPS,
16056 IX86_BUILTIN_MASKMOVQ,
16057 IX86_BUILTIN_MOVMSKPS,
16058 IX86_BUILTIN_PMOVMSKB,
16060 IX86_BUILTIN_MOVNTPS,
16061 IX86_BUILTIN_MOVNTQ,
16063 IX86_BUILTIN_LOADDQU,
16064 IX86_BUILTIN_STOREDQU,
16066 IX86_BUILTIN_PACKSSWB,
16067 IX86_BUILTIN_PACKSSDW,
16068 IX86_BUILTIN_PACKUSWB,
16070 IX86_BUILTIN_PADDB,
16071 IX86_BUILTIN_PADDW,
16072 IX86_BUILTIN_PADDD,
16073 IX86_BUILTIN_PADDQ,
16074 IX86_BUILTIN_PADDSB,
16075 IX86_BUILTIN_PADDSW,
16076 IX86_BUILTIN_PADDUSB,
16077 IX86_BUILTIN_PADDUSW,
16078 IX86_BUILTIN_PSUBB,
16079 IX86_BUILTIN_PSUBW,
16080 IX86_BUILTIN_PSUBD,
16081 IX86_BUILTIN_PSUBQ,
16082 IX86_BUILTIN_PSUBSB,
16083 IX86_BUILTIN_PSUBSW,
16084 IX86_BUILTIN_PSUBUSB,
16085 IX86_BUILTIN_PSUBUSW,
16087 IX86_BUILTIN_PAND,
16088 IX86_BUILTIN_PANDN,
16089 IX86_BUILTIN_POR,
16090 IX86_BUILTIN_PXOR,
16092 IX86_BUILTIN_PAVGB,
16093 IX86_BUILTIN_PAVGW,
16095 IX86_BUILTIN_PCMPEQB,
16096 IX86_BUILTIN_PCMPEQW,
16097 IX86_BUILTIN_PCMPEQD,
16098 IX86_BUILTIN_PCMPGTB,
16099 IX86_BUILTIN_PCMPGTW,
16100 IX86_BUILTIN_PCMPGTD,
16102 IX86_BUILTIN_PMADDWD,
16104 IX86_BUILTIN_PMAXSW,
16105 IX86_BUILTIN_PMAXUB,
16106 IX86_BUILTIN_PMINSW,
16107 IX86_BUILTIN_PMINUB,
16109 IX86_BUILTIN_PMULHUW,
16110 IX86_BUILTIN_PMULHW,
16111 IX86_BUILTIN_PMULLW,
16113 IX86_BUILTIN_PSADBW,
16114 IX86_BUILTIN_PSHUFW,
16116 IX86_BUILTIN_PSLLW,
16117 IX86_BUILTIN_PSLLD,
16118 IX86_BUILTIN_PSLLQ,
16119 IX86_BUILTIN_PSRAW,
16120 IX86_BUILTIN_PSRAD,
16121 IX86_BUILTIN_PSRLW,
16122 IX86_BUILTIN_PSRLD,
16123 IX86_BUILTIN_PSRLQ,
16124 IX86_BUILTIN_PSLLWI,
16125 IX86_BUILTIN_PSLLDI,
16126 IX86_BUILTIN_PSLLQI,
16127 IX86_BUILTIN_PSRAWI,
16128 IX86_BUILTIN_PSRADI,
16129 IX86_BUILTIN_PSRLWI,
16130 IX86_BUILTIN_PSRLDI,
16131 IX86_BUILTIN_PSRLQI,
16133 IX86_BUILTIN_PUNPCKHBW,
16134 IX86_BUILTIN_PUNPCKHWD,
16135 IX86_BUILTIN_PUNPCKHDQ,
16136 IX86_BUILTIN_PUNPCKLBW,
16137 IX86_BUILTIN_PUNPCKLWD,
16138 IX86_BUILTIN_PUNPCKLDQ,
16140 IX86_BUILTIN_SHUFPS,
16142 IX86_BUILTIN_RCPPS,
16143 IX86_BUILTIN_RCPSS,
16144 IX86_BUILTIN_RSQRTPS,
16145 IX86_BUILTIN_RSQRTSS,
16146 IX86_BUILTIN_SQRTPS,
16147 IX86_BUILTIN_SQRTSS,
16149 IX86_BUILTIN_UNPCKHPS,
16150 IX86_BUILTIN_UNPCKLPS,
16152 IX86_BUILTIN_ANDPS,
16153 IX86_BUILTIN_ANDNPS,
16154 IX86_BUILTIN_ORPS,
16155 IX86_BUILTIN_XORPS,
16157 IX86_BUILTIN_EMMS,
16158 IX86_BUILTIN_LDMXCSR,
16159 IX86_BUILTIN_STMXCSR,
16160 IX86_BUILTIN_SFENCE,
16162 /* 3DNow! Original */
16163 IX86_BUILTIN_FEMMS,
16164 IX86_BUILTIN_PAVGUSB,
16165 IX86_BUILTIN_PF2ID,
16166 IX86_BUILTIN_PFACC,
16167 IX86_BUILTIN_PFADD,
16168 IX86_BUILTIN_PFCMPEQ,
16169 IX86_BUILTIN_PFCMPGE,
16170 IX86_BUILTIN_PFCMPGT,
16171 IX86_BUILTIN_PFMAX,
16172 IX86_BUILTIN_PFMIN,
16173 IX86_BUILTIN_PFMUL,
16174 IX86_BUILTIN_PFRCP,
16175 IX86_BUILTIN_PFRCPIT1,
16176 IX86_BUILTIN_PFRCPIT2,
16177 IX86_BUILTIN_PFRSQIT1,
16178 IX86_BUILTIN_PFRSQRT,
16179 IX86_BUILTIN_PFSUB,
16180 IX86_BUILTIN_PFSUBR,
16181 IX86_BUILTIN_PI2FD,
16182 IX86_BUILTIN_PMULHRW,
16184 /* 3DNow! Athlon Extensions */
16185 IX86_BUILTIN_PF2IW,
16186 IX86_BUILTIN_PFNACC,
16187 IX86_BUILTIN_PFPNACC,
16188 IX86_BUILTIN_PI2FW,
16189 IX86_BUILTIN_PSWAPDSI,
16190 IX86_BUILTIN_PSWAPDSF,
16192 /* SSE2 */
16193 IX86_BUILTIN_ADDPD,
16194 IX86_BUILTIN_ADDSD,
16195 IX86_BUILTIN_DIVPD,
16196 IX86_BUILTIN_DIVSD,
16197 IX86_BUILTIN_MULPD,
16198 IX86_BUILTIN_MULSD,
16199 IX86_BUILTIN_SUBPD,
16200 IX86_BUILTIN_SUBSD,
16202 IX86_BUILTIN_CMPEQPD,
16203 IX86_BUILTIN_CMPLTPD,
16204 IX86_BUILTIN_CMPLEPD,
16205 IX86_BUILTIN_CMPGTPD,
16206 IX86_BUILTIN_CMPGEPD,
16207 IX86_BUILTIN_CMPNEQPD,
16208 IX86_BUILTIN_CMPNLTPD,
16209 IX86_BUILTIN_CMPNLEPD,
16210 IX86_BUILTIN_CMPNGTPD,
16211 IX86_BUILTIN_CMPNGEPD,
16212 IX86_BUILTIN_CMPORDPD,
16213 IX86_BUILTIN_CMPUNORDPD,
16214 IX86_BUILTIN_CMPEQSD,
16215 IX86_BUILTIN_CMPLTSD,
16216 IX86_BUILTIN_CMPLESD,
16217 IX86_BUILTIN_CMPNEQSD,
16218 IX86_BUILTIN_CMPNLTSD,
16219 IX86_BUILTIN_CMPNLESD,
16220 IX86_BUILTIN_CMPORDSD,
16221 IX86_BUILTIN_CMPUNORDSD,
16223 IX86_BUILTIN_COMIEQSD,
16224 IX86_BUILTIN_COMILTSD,
16225 IX86_BUILTIN_COMILESD,
16226 IX86_BUILTIN_COMIGTSD,
16227 IX86_BUILTIN_COMIGESD,
16228 IX86_BUILTIN_COMINEQSD,
16229 IX86_BUILTIN_UCOMIEQSD,
16230 IX86_BUILTIN_UCOMILTSD,
16231 IX86_BUILTIN_UCOMILESD,
16232 IX86_BUILTIN_UCOMIGTSD,
16233 IX86_BUILTIN_UCOMIGESD,
16234 IX86_BUILTIN_UCOMINEQSD,
16236 IX86_BUILTIN_MAXPD,
16237 IX86_BUILTIN_MAXSD,
16238 IX86_BUILTIN_MINPD,
16239 IX86_BUILTIN_MINSD,
16241 IX86_BUILTIN_ANDPD,
16242 IX86_BUILTIN_ANDNPD,
16243 IX86_BUILTIN_ORPD,
16244 IX86_BUILTIN_XORPD,
16246 IX86_BUILTIN_SQRTPD,
16247 IX86_BUILTIN_SQRTSD,
16249 IX86_BUILTIN_UNPCKHPD,
16250 IX86_BUILTIN_UNPCKLPD,
16252 IX86_BUILTIN_SHUFPD,
16254 IX86_BUILTIN_LOADUPD,
16255 IX86_BUILTIN_STOREUPD,
16256 IX86_BUILTIN_MOVSD,
16258 IX86_BUILTIN_LOADHPD,
16259 IX86_BUILTIN_LOADLPD,
16261 IX86_BUILTIN_CVTDQ2PD,
16262 IX86_BUILTIN_CVTDQ2PS,
16264 IX86_BUILTIN_CVTPD2DQ,
16265 IX86_BUILTIN_CVTPD2PI,
16266 IX86_BUILTIN_CVTPD2PS,
16267 IX86_BUILTIN_CVTTPD2DQ,
16268 IX86_BUILTIN_CVTTPD2PI,
16270 IX86_BUILTIN_CVTPI2PD,
16271 IX86_BUILTIN_CVTSI2SD,
16272 IX86_BUILTIN_CVTSI642SD,
16274 IX86_BUILTIN_CVTSD2SI,
16275 IX86_BUILTIN_CVTSD2SI64,
16276 IX86_BUILTIN_CVTSD2SS,
16277 IX86_BUILTIN_CVTSS2SD,
16278 IX86_BUILTIN_CVTTSD2SI,
16279 IX86_BUILTIN_CVTTSD2SI64,
16281 IX86_BUILTIN_CVTPS2DQ,
16282 IX86_BUILTIN_CVTPS2PD,
16283 IX86_BUILTIN_CVTTPS2DQ,
16285 IX86_BUILTIN_MOVNTI,
16286 IX86_BUILTIN_MOVNTPD,
16287 IX86_BUILTIN_MOVNTDQ,
16289 /* SSE2 MMX */
16290 IX86_BUILTIN_MASKMOVDQU,
16291 IX86_BUILTIN_MOVMSKPD,
16292 IX86_BUILTIN_PMOVMSKB128,
16294 IX86_BUILTIN_PACKSSWB128,
16295 IX86_BUILTIN_PACKSSDW128,
16296 IX86_BUILTIN_PACKUSWB128,
16298 IX86_BUILTIN_PADDB128,
16299 IX86_BUILTIN_PADDW128,
16300 IX86_BUILTIN_PADDD128,
16301 IX86_BUILTIN_PADDQ128,
16302 IX86_BUILTIN_PADDSB128,
16303 IX86_BUILTIN_PADDSW128,
16304 IX86_BUILTIN_PADDUSB128,
16305 IX86_BUILTIN_PADDUSW128,
16306 IX86_BUILTIN_PSUBB128,
16307 IX86_BUILTIN_PSUBW128,
16308 IX86_BUILTIN_PSUBD128,
16309 IX86_BUILTIN_PSUBQ128,
16310 IX86_BUILTIN_PSUBSB128,
16311 IX86_BUILTIN_PSUBSW128,
16312 IX86_BUILTIN_PSUBUSB128,
16313 IX86_BUILTIN_PSUBUSW128,
16315 IX86_BUILTIN_PAND128,
16316 IX86_BUILTIN_PANDN128,
16317 IX86_BUILTIN_POR128,
16318 IX86_BUILTIN_PXOR128,
16320 IX86_BUILTIN_PAVGB128,
16321 IX86_BUILTIN_PAVGW128,
16323 IX86_BUILTIN_PCMPEQB128,
16324 IX86_BUILTIN_PCMPEQW128,
16325 IX86_BUILTIN_PCMPEQD128,
16326 IX86_BUILTIN_PCMPGTB128,
16327 IX86_BUILTIN_PCMPGTW128,
16328 IX86_BUILTIN_PCMPGTD128,
16330 IX86_BUILTIN_PMADDWD128,
16332 IX86_BUILTIN_PMAXSW128,
16333 IX86_BUILTIN_PMAXUB128,
16334 IX86_BUILTIN_PMINSW128,
16335 IX86_BUILTIN_PMINUB128,
16337 IX86_BUILTIN_PMULUDQ,
16338 IX86_BUILTIN_PMULUDQ128,
16339 IX86_BUILTIN_PMULHUW128,
16340 IX86_BUILTIN_PMULHW128,
16341 IX86_BUILTIN_PMULLW128,
16343 IX86_BUILTIN_PSADBW128,
16344 IX86_BUILTIN_PSHUFHW,
16345 IX86_BUILTIN_PSHUFLW,
16346 IX86_BUILTIN_PSHUFD,
16348 IX86_BUILTIN_PSLLDQI128,
16349 IX86_BUILTIN_PSLLWI128,
16350 IX86_BUILTIN_PSLLDI128,
16351 IX86_BUILTIN_PSLLQI128,
16352 IX86_BUILTIN_PSRAWI128,
16353 IX86_BUILTIN_PSRADI128,
16354 IX86_BUILTIN_PSRLDQI128,
16355 IX86_BUILTIN_PSRLWI128,
16356 IX86_BUILTIN_PSRLDI128,
16357 IX86_BUILTIN_PSRLQI128,
16359 IX86_BUILTIN_PSLLDQ128,
16360 IX86_BUILTIN_PSLLW128,
16361 IX86_BUILTIN_PSLLD128,
16362 IX86_BUILTIN_PSLLQ128,
16363 IX86_BUILTIN_PSRAW128,
16364 IX86_BUILTIN_PSRAD128,
16365 IX86_BUILTIN_PSRLW128,
16366 IX86_BUILTIN_PSRLD128,
16367 IX86_BUILTIN_PSRLQ128,
16369 IX86_BUILTIN_PUNPCKHBW128,
16370 IX86_BUILTIN_PUNPCKHWD128,
16371 IX86_BUILTIN_PUNPCKHDQ128,
16372 IX86_BUILTIN_PUNPCKHQDQ128,
16373 IX86_BUILTIN_PUNPCKLBW128,
16374 IX86_BUILTIN_PUNPCKLWD128,
16375 IX86_BUILTIN_PUNPCKLDQ128,
16376 IX86_BUILTIN_PUNPCKLQDQ128,
16378 IX86_BUILTIN_CLFLUSH,
16379 IX86_BUILTIN_MFENCE,
16380 IX86_BUILTIN_LFENCE,
16382 /* Prescott New Instructions. */
16383 IX86_BUILTIN_ADDSUBPS,
16384 IX86_BUILTIN_HADDPS,
16385 IX86_BUILTIN_HSUBPS,
16386 IX86_BUILTIN_MOVSHDUP,
16387 IX86_BUILTIN_MOVSLDUP,
16388 IX86_BUILTIN_ADDSUBPD,
16389 IX86_BUILTIN_HADDPD,
16390 IX86_BUILTIN_HSUBPD,
16391 IX86_BUILTIN_LDDQU,
16393 IX86_BUILTIN_MONITOR,
16394 IX86_BUILTIN_MWAIT,
16396 /* SSSE3. */
16397 IX86_BUILTIN_PHADDW,
16398 IX86_BUILTIN_PHADDD,
16399 IX86_BUILTIN_PHADDSW,
16400 IX86_BUILTIN_PHSUBW,
16401 IX86_BUILTIN_PHSUBD,
16402 IX86_BUILTIN_PHSUBSW,
16403 IX86_BUILTIN_PMADDUBSW,
16404 IX86_BUILTIN_PMULHRSW,
16405 IX86_BUILTIN_PSHUFB,
16406 IX86_BUILTIN_PSIGNB,
16407 IX86_BUILTIN_PSIGNW,
16408 IX86_BUILTIN_PSIGND,
16409 IX86_BUILTIN_PALIGNR,
16410 IX86_BUILTIN_PABSB,
16411 IX86_BUILTIN_PABSW,
16412 IX86_BUILTIN_PABSD,
16414 IX86_BUILTIN_PHADDW128,
16415 IX86_BUILTIN_PHADDD128,
16416 IX86_BUILTIN_PHADDSW128,
16417 IX86_BUILTIN_PHSUBW128,
16418 IX86_BUILTIN_PHSUBD128,
16419 IX86_BUILTIN_PHSUBSW128,
16420 IX86_BUILTIN_PMADDUBSW128,
16421 IX86_BUILTIN_PMULHRSW128,
16422 IX86_BUILTIN_PSHUFB128,
16423 IX86_BUILTIN_PSIGNB128,
16424 IX86_BUILTIN_PSIGNW128,
16425 IX86_BUILTIN_PSIGND128,
16426 IX86_BUILTIN_PALIGNR128,
16427 IX86_BUILTIN_PABSB128,
16428 IX86_BUILTIN_PABSW128,
16429 IX86_BUILTIN_PABSD128,
16431 /* AMDFAM10 - SSE4A New Instructions. */
16432 IX86_BUILTIN_MOVNTSD,
16433 IX86_BUILTIN_MOVNTSS,
16434 IX86_BUILTIN_EXTRQI,
16435 IX86_BUILTIN_EXTRQ,
16436 IX86_BUILTIN_INSERTQI,
16437 IX86_BUILTIN_INSERTQ,
16439 /* SSE4.1. */
16440 IX86_BUILTIN_BLENDPD,
16441 IX86_BUILTIN_BLENDPS,
16442 IX86_BUILTIN_BLENDVPD,
16443 IX86_BUILTIN_BLENDVPS,
16444 IX86_BUILTIN_PBLENDVB128,
16445 IX86_BUILTIN_PBLENDW128,
16447 IX86_BUILTIN_DPPD,
16448 IX86_BUILTIN_DPPS,
16450 IX86_BUILTIN_INSERTPS128,
16452 IX86_BUILTIN_MOVNTDQA,
16453 IX86_BUILTIN_MPSADBW128,
16454 IX86_BUILTIN_PACKUSDW128,
16455 IX86_BUILTIN_PCMPEQQ,
16456 IX86_BUILTIN_PHMINPOSUW128,
16458 IX86_BUILTIN_PMAXSB128,
16459 IX86_BUILTIN_PMAXSD128,
16460 IX86_BUILTIN_PMAXUD128,
16461 IX86_BUILTIN_PMAXUW128,
16463 IX86_BUILTIN_PMINSB128,
16464 IX86_BUILTIN_PMINSD128,
16465 IX86_BUILTIN_PMINUD128,
16466 IX86_BUILTIN_PMINUW128,
16468 IX86_BUILTIN_PMOVSXBW128,
16469 IX86_BUILTIN_PMOVSXBD128,
16470 IX86_BUILTIN_PMOVSXBQ128,
16471 IX86_BUILTIN_PMOVSXWD128,
16472 IX86_BUILTIN_PMOVSXWQ128,
16473 IX86_BUILTIN_PMOVSXDQ128,
16475 IX86_BUILTIN_PMOVZXBW128,
16476 IX86_BUILTIN_PMOVZXBD128,
16477 IX86_BUILTIN_PMOVZXBQ128,
16478 IX86_BUILTIN_PMOVZXWD128,
16479 IX86_BUILTIN_PMOVZXWQ128,
16480 IX86_BUILTIN_PMOVZXDQ128,
16482 IX86_BUILTIN_PMULDQ128,
16483 IX86_BUILTIN_PMULLD128,
16485 IX86_BUILTIN_ROUNDPD,
16486 IX86_BUILTIN_ROUNDPS,
16487 IX86_BUILTIN_ROUNDSD,
16488 IX86_BUILTIN_ROUNDSS,
16490 IX86_BUILTIN_PTESTZ,
16491 IX86_BUILTIN_PTESTC,
16492 IX86_BUILTIN_PTESTNZC,
16494 IX86_BUILTIN_VEC_INIT_V2SI,
16495 IX86_BUILTIN_VEC_INIT_V4HI,
16496 IX86_BUILTIN_VEC_INIT_V8QI,
16497 IX86_BUILTIN_VEC_EXT_V2DF,
16498 IX86_BUILTIN_VEC_EXT_V2DI,
16499 IX86_BUILTIN_VEC_EXT_V4SF,
16500 IX86_BUILTIN_VEC_EXT_V4SI,
16501 IX86_BUILTIN_VEC_EXT_V8HI,
16502 IX86_BUILTIN_VEC_EXT_V2SI,
16503 IX86_BUILTIN_VEC_EXT_V4HI,
16504 IX86_BUILTIN_VEC_EXT_V16QI,
16505 IX86_BUILTIN_VEC_SET_V2DI,
16506 IX86_BUILTIN_VEC_SET_V4SF,
16507 IX86_BUILTIN_VEC_SET_V4SI,
16508 IX86_BUILTIN_VEC_SET_V8HI,
16509 IX86_BUILTIN_VEC_SET_V4HI,
16510 IX86_BUILTIN_VEC_SET_V16QI,
16512 IX86_BUILTIN_MAX
16513 };
16515 /* Table for the ix86 builtin decls. */
16518 /* Add a ix86 target builtin function with CODE, NAME and TYPE. Do so,
16519 * if the target_flags include one of MASK. Stores the function decl
16520 * in the ix86_builtins array.
16521 * Returns the function decl or NULL_TREE, if the builtin was not added. */
16525 {
16530 {
16534 }
16537 }
16539 /* Like def_builtin, but also marks the function decl "const". */
16544 {
16549 }
16551 /* Bits for builtin_description.flag. */
16553 /* Set when we don't support the comparison natively, and should
16554 swap_comparison in order to support it. */
16555 #define BUILTIN_DESC_SWAP_OPERANDS 1
16557 struct builtin_description
16558 {
16565 };
16568 {
16580 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
16586 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
16587 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
16588 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
16589 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
16590 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
16591 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
16592 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
16593 };
16596 {
16597 /* SSE4.1 */
16598 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
16599 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
16600 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
16601 };
16603 /* SSE builtins with 3 arguments and the last argument must be a 8 bit
16604 constant or xmm0. */
16606 {
16607 /* SSE4.1 */
16608 { MASK_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, 0, 0 },
16609 { MASK_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, 0, 0 },
16610 { MASK_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, 0, 0 },
16611 { MASK_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, 0, 0 },
16614 { MASK_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, 0, 0 },
16615 { MASK_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, 0, 0 },
16616 { MASK_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, 0, 0 },
16617 { MASK_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, 0, 0 },
16620 };
16623 {
16624 /* SSE */
16634 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
16635 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
16636 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
16638 BUILTIN_DESC_SWAP_OPERANDS },
16640 BUILTIN_DESC_SWAP_OPERANDS },
16641 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
16642 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
16643 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
16644 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
16645 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
16646 BUILTIN_DESC_SWAP_OPERANDS },
16647 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
16648 BUILTIN_DESC_SWAP_OPERANDS },
16649 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
16650 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
16651 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
16652 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
16653 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
16654 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
16655 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
16656 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
16657 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
16658 BUILTIN_DESC_SWAP_OPERANDS },
16659 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
16660 BUILTIN_DESC_SWAP_OPERANDS },
16661 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
16679 /* MMX */
16699 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
16700 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
16707 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
16708 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
16717 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
16718 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
16719 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
16720 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
16722 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
16723 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
16724 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
16725 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
16726 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
16727 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
16729 /* Special. */
16760 /* SSE2 */
16770 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
16771 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
16772 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
16774 BUILTIN_DESC_SWAP_OPERANDS },
16776 BUILTIN_DESC_SWAP_OPERANDS },
16777 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
16778 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
16779 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
16780 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
16781 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
16782 BUILTIN_DESC_SWAP_OPERANDS },
16783 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
16784 BUILTIN_DESC_SWAP_OPERANDS },
16785 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
16786 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
16787 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
16788 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
16789 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
16790 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
16791 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
16792 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
16793 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
16806 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
16807 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
16809 /* SSE2 MMX */
16819 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
16820 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
16821 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
16822 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
16823 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
16824 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
16825 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
16826 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
16829 { MASK_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
16832 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
16836 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
16837 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
16839 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
16840 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
16841 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
16842 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
16843 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
16844 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
16851 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
16852 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
16853 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
16854 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
16855 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
16856 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
16857 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
16858 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
16860 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
16861 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
16862 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
16864 { MASK_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
16888 /* SSE3 MMX */
16889 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
16890 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
16896 /* SSSE3 */
16897 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
16898 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
16899 { MASK_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
16900 { MASK_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
16901 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
16902 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
16903 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
16904 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
16905 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
16906 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
16907 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
16908 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
16909 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
16910 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
16911 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
16912 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
16913 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
16914 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
16915 { MASK_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
16916 { MASK_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
16917 { MASK_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
16918 { MASK_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
16919 { MASK_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
16920 { MASK_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, 0, 0 },
16922 /* SSE4.1 */
16923 { MASK_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, 0, 0 },
16924 { MASK_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, 0, 0 },
16925 { MASK_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, 0, 0 },
16926 { MASK_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, 0, 0 },
16927 { MASK_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, 0, 0 },
16928 { MASK_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, 0, 0 },
16929 { MASK_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, 0, 0 },
16930 { MASK_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, 0, 0 },
16931 { MASK_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, 0, 0 },
16932 { MASK_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, 0, 0 },
16935 };
16938 {
16978 /* SSE3 */
16979 { MASK_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, 0, 0 },
16980 { MASK_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, 0, 0 },
16982 /* SSSE3 */
16990 /* SSE4.1 */
17003 { MASK_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, 0, 0 },
17005 /* Fake 1 arg builtins with a constant smaller than 8 bits as the
17006 2nd arg. */
17009 };
17011 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
17012 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
17013 builtins. */
17014 static void
17016 {
17023 tree V2DI_type_node
17042 /* Comparisons. */
17043 tree int_ftype_v4sf_v4sf
17046 tree v4si_ftype_v4sf_v4sf
17049 /* MMX/SSE/integer conversions. */
17050 tree int_ftype_v4sf
17053 tree int64_ftype_v4sf
17056 tree int_ftype_v8qi
17058 tree v4sf_ftype_v4sf_int
17061 tree v4sf_ftype_v4sf_int64
17064 NULL_TREE);
17065 tree v4sf_ftype_v4sf_v2si
17069 /* Miscellaneous. */
17070 tree v8qi_ftype_v4hi_v4hi
17073 tree v4hi_ftype_v2si_v2si
17076 tree v4sf_ftype_v4sf_v4sf_int
17080 tree v2si_ftype_v4hi_v4hi
17083 tree v4hi_ftype_v4hi_int
17086 tree v4hi_ftype_v4hi_di
17089 NULL_TREE);
17090 tree v2si_ftype_v2si_di
17093 NULL_TREE);
17094 tree void_ftype_void
17096 tree void_ftype_unsigned
17098 tree void_ftype_unsigned_unsigned
17101 tree void_ftype_pcvoid_unsigned_unsigned
17104 NULL_TREE);
17105 tree unsigned_ftype_void
17107 tree v2si_ftype_v4sf
17109 /* Loads/stores. */
17110 tree void_ftype_v8qi_v8qi_pchar
17114 tree v4sf_ftype_pcfloat
17116 /* @@@ the type is bogus */
17117 tree v4sf_ftype_v4sf_pv2si
17120 tree void_ftype_pv2si_v4sf
17123 tree void_ftype_pfloat_v4sf
17126 tree void_ftype_pdi_di
17129 NULL_TREE);
17130 tree void_ftype_pv2di_v2di
17133 /* Normal vector unops. */
17134 tree v4sf_ftype_v4sf
17136 tree v16qi_ftype_v16qi
17138 tree v8hi_ftype_v8hi
17140 tree v4si_ftype_v4si
17142 tree v8qi_ftype_v8qi
17144 tree v4hi_ftype_v4hi
17147 /* Normal vector binops. */
17148 tree v4sf_ftype_v4sf_v4sf
17151 tree v8qi_ftype_v8qi_v8qi
17154 tree v4hi_ftype_v4hi_v4hi
17157 tree v2si_ftype_v2si_v2si
17160 tree di_ftype_di_di
17162 long_long_unsigned_type_node,
17165 tree di_ftype_di_di_int
17167 long_long_unsigned_type_node,
17168 long_long_unsigned_type_node,
17171 tree v2si_ftype_v2sf
17173 tree v2sf_ftype_v2si
17175 tree v2si_ftype_v2si
17177 tree v2sf_ftype_v2sf
17179 tree v2sf_ftype_v2sf_v2sf
17182 tree v2si_ftype_v2sf_v2sf
17189 tree int_ftype_v2df_v2df
17193 tree void_ftype_pcvoid
17195 tree v4sf_ftype_v4si
17197 tree v4si_ftype_v4sf
17199 tree v2df_ftype_v4si
17201 tree v4si_ftype_v2df
17203 tree v2si_ftype_v2df
17205 tree v4sf_ftype_v2df
17207 tree v2df_ftype_v2si
17209 tree v2df_ftype_v4sf
17211 tree int_ftype_v2df
17213 tree int64_ftype_v2df
17216 tree v2df_ftype_v2df_int
17219 tree v2df_ftype_v2df_int64
17222 NULL_TREE);
17223 tree v4sf_ftype_v4sf_v2df
17226 tree v2df_ftype_v2df_v4sf
17229 tree v2df_ftype_v2df_v2df_int
17232 integer_type_node,
17233 NULL_TREE);
17234 tree v2df_ftype_v2df_pcdouble
17237 tree void_ftype_pdouble_v2df
17240 tree void_ftype_pint_int
17243 tree void_ftype_v16qi_v16qi_pchar
17247 tree v2df_ftype_pcdouble
17249 tree v2df_ftype_v2df_v2df
17252 tree v16qi_ftype_v16qi_v16qi
17255 tree v8hi_ftype_v8hi_v8hi
17258 tree v4si_ftype_v4si_v4si
17261 tree v2di_ftype_v2di_v2di
17264 tree v2di_ftype_v2df_v2df
17267 tree v2df_ftype_v2df
17269 tree v2di_ftype_v2di_int
17272 tree v2di_ftype_v2di_v2di_int
17275 tree v4si_ftype_v4si_int
17278 tree v8hi_ftype_v8hi_int
17281 tree v4si_ftype_v8hi_v8hi
17284 tree di_ftype_v8qi_v8qi
17287 tree di_ftype_v2si_v2si
17290 tree v2di_ftype_v16qi_v16qi
17293 tree v2di_ftype_v4si_v4si
17296 tree int_ftype_v16qi
17298 tree v16qi_ftype_pcchar
17300 tree void_ftype_pchar_v16qi
17304 tree v2di_ftype_v2di_unsigned_unsigned
17307 NULL_TREE);
17308 tree v2di_ftype_v2di_v2di_unsigned_unsigned
17311 NULL_TREE);
17312 tree v2di_ftype_v2di_v16qi
17314 NULL_TREE);
17315 tree v2df_ftype_v2df_v2df_v2df
17319 tree v4sf_ftype_v4sf_v4sf_v4sf
17323 tree v8hi_ftype_v16qi
17325 NULL_TREE);
17326 tree v4si_ftype_v16qi
17328 NULL_TREE);
17329 tree v2di_ftype_v16qi
17331 NULL_TREE);
17332 tree v4si_ftype_v8hi
17334 NULL_TREE);
17335 tree v2di_ftype_v8hi
17337 NULL_TREE);
17338 tree v2di_ftype_v4si
17340 NULL_TREE);
17341 tree v2di_ftype_pv2di
17343 NULL_TREE);
17344 tree v16qi_ftype_v16qi_v16qi_int
17347 NULL_TREE);
17348 tree v16qi_ftype_v16qi_v16qi_v16qi
17351 NULL_TREE);
17352 tree v8hi_ftype_v8hi_v8hi_int
17355 NULL_TREE);
17356 tree v4si_ftype_v4si_v4si_int
17359 NULL_TREE);
17360 tree int_ftype_v2di_v2di
17363 NULL_TREE);
17365 tree float80_type;
17366 tree float128_type;
17367 tree ftype;
17369 /* The __float80 type. */
17373 else
17374 {
17375 /* The __float80 type. */
17380 }
17383 {
17388 }
17390 /* Add all SSE builtins that are more or less simple operations on
17391 three operands. */
17395 {
17396 /* Use one of the operands; the target can have a different mode for
17397 mask-generating compares. */
17399 tree type;
17406 {
17427 }
17429 /* Override for variable blends. */
17431 {
17443 }
17446 }
17448 /* Add all builtins that are more or less simple operations on two
17449 operands. */
17451 {
17452 /* Use one of the operands; the target can have a different mode for
17453 mask-generating compares. */
17455 tree type;
17462 {
17496 }
17498 /* Override for comparisons. */
17508 }
17510 /* Add all builtins that are more or less simple operations on 1 operand. */
17512 {
17514 tree type;
17521 {
17549 }
17552 }
17554 /* Add the remaining MMX insns with somewhat more complicated types. */
17567 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
17570 /* comi/ucomi insns. */
17574 else
17577 /* ptest insns. */
17581 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
17582 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
17583 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
17587 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
17588 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
17589 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
17590 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
17591 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
17592 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
17593 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
17594 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
17595 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
17597 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
17600 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
17602 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
17603 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
17604 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
17605 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
17608 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
17609 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
17610 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
17612 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
17614 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
17623 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
17625 /* Original 3DNow! */
17627 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
17631 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
17632 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
17633 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
17638 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
17639 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
17641 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
17645 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
17647 /* 3DNow! extension as used in the Athlon CPU. */
17649 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
17650 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
17652 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
17653 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
17655 /* SSE2 */
17656 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
17659 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
17661 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
17662 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
17665 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
17667 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
17668 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
17673 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
17678 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
17680 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
17681 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
17683 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
17684 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
17685 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
17686 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
17687 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
17689 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
17691 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
17692 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
17693 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
17694 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
17696 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
17697 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
17698 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
17700 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
17701 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
17702 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
17703 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
17710 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
17713 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
17715 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
17716 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
17717 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
17718 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
17719 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
17720 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
17721 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
17723 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
17724 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
17725 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
17726 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
17727 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
17728 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
17729 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
17731 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
17732 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
17733 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
17734 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
17736 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
17738 /* Prescott New Instructions. */
17740 void_ftype_pcvoid_unsigned_unsigned,
17741 IX86_BUILTIN_MONITOR);
17743 void_ftype_unsigned_unsigned,
17744 IX86_BUILTIN_MWAIT);
17748 /* SSSE3. */
17752 IX86_BUILTIN_PALIGNR);
17754 /* SSE4.1. */
17792 /* AMDFAM10 SSE4A New built-ins */
17806 /* Access to the vec_init patterns. */
17813 short_integer_type_node,
17814 short_integer_type_node,
17827 /* Access to the vec_extract patterns. */
17835 NULL_TREE);
17869 /* Access to the vec_set patterns. */
17871 intDI_type_node,
17877 float_type_node,
17883 intSI_type_node,
17889 intHI_type_node,
17895 intHI_type_node,
17901 intQI_type_node,
17905 }
17907 static void
17909 {
17912 }
17914 /* Errors in the source file can cause expand_expr to return const0_rtx
17915 where we expect a vector. To avoid crashing, use one of the vector
17916 clear instructions. */
17917 static rtx
17919 {
17923 }
17925 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
17926 4 operands. The third argument must be a constant smaller than 8
17927 bits or xmm0. */
17929 static rtx
17931 rtx target)
17932 {
17933 rtx pat;
17944 rtx xmm0;
17953 {
17957 /* The third argument of variable blends must be xmm0. */
17965 {
17967 {
17975 }
17977 }
17979 }
17991 }
17993 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
17995 static rtx
17997 {
18018 {
18022 }
18024 /* The insn must want input operands in the same modes as the
18025 result. */
18034 /* ??? Using ix86_fixup_binary_operands is problematic when
18035 we've got mismatched modes. Fake it. */
18042 {
18046 }
18048 {
18052 }
18059 }
18061 /* Subroutine of ix86_expand_builtin to take care of stores. */
18063 static rtx
18065 {
18066 rtx pat;
18084 }
18086 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
18088 static rtx
18091 {
18092 rtx pat;
18104 else
18105 {
18112 }
18115 {
18118 {
18124 {
18127 }
18129 }
18134 }
18140 }
18142 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
18143 sqrtss, rsqrtss, rcpss. */
18145 static rtx
18147 {
18148 rtx pat;
18175 }
18177 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
18179 static rtx
18181 rtx target)
18182 {
18183 rtx pat;
18188 rtx op2;
18199 /* Swap operands if we have a comparison that isn't available in
18200 hardware. */
18202 {
18207 }
18227 }
18229 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
18231 static rtx
18233 rtx target)
18234 {
18235 rtx pat;
18249 /* Swap operands if we have a comparison that isn't available in
18250 hardware. */
18252 {
18256 }
18277 const0_rtx)));
18280 }
18282 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
18284 static rtx
18286 rtx target)
18287 {
18288 rtx pat;
18321 const0_rtx)));
18324 }
18326 /* Return the integer constant in ARG. Constrain it to be in the range
18327 of the subparts of VEC_TYPE; issue an error if not. */
18329 static int
18331 {
18336 {
18339 }
18342 }
18344 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18345 ix86_expand_vector_init. We DO have language-level syntax for this, in
18346 the form of (type){ init-list }. Except that since we can't place emms
18347 instructions from inside the compiler, we can't allow the use of MMX
18348 registers unless the user explicitly asks for it. So we do *not* define
18349 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
18350 we have builtins invoked by mmintrin.h that gives us license to emit
18351 these sorts of instructions. */
18353 static rtx
18355 {
18365 {
18368 }
18375 }
18377 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18378 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
18379 had a language-level syntax for referencing vector elements. */
18381 static rtx
18383 {
18387 rtx op0;
18407 }
18409 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18410 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
18411 a language-level syntax for referencing vector elements. */
18413 static rtx
18415 {
18439 /* OP0 is the source of these builtin functions and shouldn't be
18440 modified. Create a copy, use it and return it as target. */
18446 }
18448 /* Expand an expression EXP that calls a built-in function,
18449 with result going to TARGET if that's convenient
18450 (and in mode MODE if that's convenient).
18451 SUBTARGET may be used as the target for computing one of EXP's operands.
18452 IGNORE is nonzero if the value is to be ignored. */
18454 static rtx
18458 {
18469 {
18481 ? CODE_FOR_mmx_maskmovq
18483 /* Note the arg order is different from the operand order. */
18590 ? CODE_FOR_sse_shufps
18609 {
18610 /* @@@ better error message */
18613 }
18643 {
18644 /* @@@ better error message */
18647 }
18682 do_pshifti:
18689 {
18692 }
18732 do_pshift:
18768 {
18771 }
18773 {
18776 }
18915 else
18938 {
18941 }
18942 else
18943 {
18946 }
18959 {
18962 }
18964 {
18967 }
18969 {
18972 }
18994 ? CODE_FOR_sse4a_extrq
19032 {
19035 }
19037 {
19040 }
19074 {
19077 }
19079 {
19082 }
19118 }
19125 target);
19129 {
19130 /* Compares are treated specially. */
19138 }
19153 }
19155 /* Returns a function decl for a vectorized version of the builtin function
19156 with builtin function code FN and the result vector type TYPE, or NULL_TREE
19157 if it is not available. */
19159 static tree
19161 tree type_in)
19162 {
19176 {
19196 ;
19197 }
19200 }
19202 /* Returns a decl of a function that implements conversion of the
19203 input vector of type TYPE, or NULL_TREE if it is not available. */
19205 static tree
19207 {
19212 {
19215 {
19220 }
19224 {
19229 }
19233 }
19234 }
19236 /* Store OPERAND to the memory after reload is completed. This means
19237 that we can't easily use assign_stack_local. */
19238 rtx
19240 {
19241 rtx result;
19245 {
19248 stack_pointer_rtx,
19251 }
19253 {
19255 {
19259 /* FALLTHRU */
19265 stack_pointer_rtx)),
19266 operand));
19270 }
19272 }
19273 else
19274 {
19276 {
19278 {
19285 stack_pointer_rtx)),
19291 stack_pointer_rtx)),
19293 }
19296 /* Store HImodes as SImodes. */
19298 /* FALLTHRU */
19304 stack_pointer_rtx)),
19305 operand));
19309 }
19311 }
19313 }
19315 /* Free operand from the memory. */
19316 void
19318 {
19320 {
19325 else
19327 /* Use LEA to deallocate stack space. In peephole2 it will be converted
19328 to pop or add instruction if registers are available. */
19332 }
19333 }
19335 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
19336 QImode must go into class Q_REGS.
19337 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
19338 movdf to do mem-to-mem moves through integer regs. */
19339 enum reg_class
19341 {
19344 /* We're only allowed to return a subclass of CLASS. Many of the
19345 following checks fail for NO_REGS, so eliminate that early. */
19349 /* All classes can load zeros. */
19353 /* Force constants into memory if we are loading a (nonzero) constant into
19354 an MMX or SSE register. This is because there are no MMX/SSE instructions
19355 to load from a constant. */
19360 /* Prefer SSE regs only, if we can use them for math. */
19364 /* Floating-point constants need more complex checks. */
19366 {
19367 /* General regs can load everything. */
19371 /* Floats can load 0 and 1 plus some others. Note that we eliminated
19372 zero above. We only want to wind up preferring 80387 registers if
19373 we plan on doing computation with them. */
19376 {
19377 /* Limit class to non-sse. */
19386 }
19389 }
19391 /* Generally when we see PLUS here, it's the function invariant
19392 (plus soft-fp const_int). Which can only be computed into general
19393 regs. */
19397 /* QImode constants are easy to load, but non-constant QImode data
19398 must go into Q_REGS. */
19400 {
19406 }
19409 }
19411 /* Discourage putting floating-point values in SSE registers unless
19412 SSE math is being used, and likewise for the 387 registers. */
19413 enum reg_class
19415 {
19418 /* Restrict the output reload class to the register bank that we are doing
19419 math on. If we would like not to return a subset of CLASS, reject this
19420 alternative: if reload cannot do this, it will still use its choice. */
19426 {
19431 else
19433 }
19436 }
19438 /* If we are copying between general and FP registers, we need a memory
19439 location. The same is true for SSE and MMX registers.
19441 The macro can't work reliably when one of the CLASSES is class containing
19442 registers from multiple units (SSE, MMX, integer). We avoid this by never
19443 combining those units in single alternative in the machine description.
19444 Ensure that this constraint holds to avoid unexpected surprises.
19446 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
19447 enforce these sanity checks. */
19449 int
19452 {
19459 {
19462 }
19467 /* ??? This is a lie. We do have moves between mmx/general, and for
19468 mmx/sse2. But by saying we need secondary memory we discourage the
19469 register allocator from using the mmx registers unless needed. */
19474 {
19475 /* SSE1 doesn't have any direct moves from other classes. */
19479 /* If the target says that inter-unit moves are more expensive
19480 than moving through memory, then don't generate them. */
19484 /* Between SSE and general, we have moves no larger than word size. */
19487 }
19490 }
19492 /* Return true if the registers in CLASS cannot represent the change from
19493 modes FROM to TO. */
19495 bool
19498 {
19502 /* x87 registers can't do subreg at all, as all values are reformatted
19503 to extended precision. */
19508 {
19509 /* Vector registers do not support QI or HImode loads. If we don't
19510 disallow a change to these modes, reload will assume it's ok to
19511 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
19512 the vec_dupv4hi pattern. */
19516 /* Vector registers do not support subreg with nonzero offsets, which
19517 are otherwise valid for integer registers. Since we can't see
19518 whether we have a nonzero offset from here, prohibit all
19519 nonparadoxical subregs changing size. */
19522 }
19525 }
19527 /* Return the cost of moving data from a register in class CLASS1 to
19528 one in class CLASS2.
19530 It is not required that the cost always equal 2 when FROM is the same as TO;
19531 on some machines it is expensive to move between registers if they are not
19532 general registers. */
19534 int
19537 {
19538 /* In case we require secondary memory, compute cost of the store followed
19539 by load. In order to avoid bad register allocation choices, we need
19540 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
19543 {
19551 /* In case of copying from general_purpose_register we may emit multiple
19552 stores followed by single load causing memory size mismatch stall.
19553 Count this as arbitrarily high cost of 20. */
19557 /* In the case of FP/MMX moves, the registers actually overlap, and we
19558 have to switch modes in order to treat them differently. */
19564 }
19566 /* Moves between SSE/MMX and integer unit are expensive. */
19577 }
19579 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
19581 bool
19583 {
19584 /* Flags and only flags can only hold CCmode values. */
19594 {
19595 /* We implement the move patterns for all vector modes into and
19596 out of SSE registers, even when no operation instructions
19597 are available. */
19602 }
19604 {
19605 /* We implement the move patterns for 3DNOW modes even in MMX mode,
19606 so if the register is available at all, then we can move data of
19607 the given mode into or out of it. */
19610 }
19613 {
19614 /* Take care for QImode values - they can be in non-QI regs,
19615 but then they do cause partial register stalls. */
19621 }
19622 /* We handle both integer and floats in the general purpose registers. */
19627 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
19628 on to use that value in smaller contexts, this can easily force a
19629 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
19630 supporting DImode, allow it. */
19635 }
19637 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
19638 tieable integer mode. */
19640 static bool
19642 {
19644 {
19657 }
19658 }
19660 /* Return true if MODE1 is accessible in a register that can hold MODE2
19661 without copying. That is, all register classes that can hold MODE2
19662 can also hold MODE1. */
19664 bool
19666 {
19674 /* MODE2 being XFmode implies fp stack or general regs, which means we
19675 can tie any smaller floating point modes to it. Note that we do not
19676 tie this with TFmode. */
19680 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
19681 that we can tie it with SFmode. */
19685 /* If MODE2 is only appropriate for an SSE register, then tie with
19686 any other mode acceptable to SSE registers. */
19692 /* If MODE2 is appropriate for an MMX register, then tie
19693 with any other mode acceptable to MMX registers. */
19700 }
19702 /* Return the cost of moving data of mode M between a
19703 register and memory. A value of 2 is the default; this cost is
19704 relative to those in `REGISTER_MOVE_COST'.
19706 If moving between registers and memory is more expensive than
19707 between two registers, you should define this macro to express the
19708 relative cost.
19710 Model also increased moving costs of QImode registers in non
19711 Q_REGS classes.
19712 */
19713 int
19715 {
19717 {
19720 {
19732 }
19734 }
19736 {
19739 {
19751 }
19753 }
19755 {
19758 {
19767 }
19769 }
19771 {
19776 else
19783 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
19789 }
19790 }
19792 /* Compute a (partial) cost for rtx X. Return true if the complete
19793 cost has been computed, and false if subexpressions should be
19794 scanned. In either case, *TOTAL contains the cost result. */
19796 static bool
19798 {
19802 {
19812 && (!TARGET_64BIT
19817 else
19824 else
19826 {
19835 /* Start with (MEM (SYMBOL_REF)), since that's where
19836 it'll probably end up. Add a penalty for size. */
19841 }
19845 /* The zero extensions is often completely free on x86_64, so make
19846 it as cheap as possible. */
19852 else
19863 {
19866 {
19869 }
19872 {
19875 }
19876 }
19877 /* FALLTHRU */
19884 {
19886 {
19889 else
19891 }
19892 else
19893 {
19896 else
19898 }
19899 }
19900 else
19901 {
19904 else
19906 }
19911 {
19912 /* ??? SSE scalar cost should be used here. */
19915 }
19917 {
19920 }
19922 {
19923 /* ??? SSE vector cost should be used here. */
19926 }
19927 else
19928 {
19933 {
19936 nbits++;
19937 }
19938 else
19939 /* This is arbitrary. */
19942 /* Compute costs correctly for widening multiplication. */
19946 {
19953 {
19957 else
19959 }
19963 }
19970 }
19977 /* ??? SSE cost should be used here. */
19982 /* ??? SSE vector cost should be used here. */
19984 else
19991 {
19996 {
19999 {
20003 outer_code);
20006 }
20007 }
20010 {
20013 {
20018 }
20019 }
20021 {
20027 }
20028 }
20029 /* FALLTHRU */
20033 {
20034 /* ??? SSE cost should be used here. */
20037 }
20039 {
20042 }
20044 {
20045 /* ??? SSE vector cost should be used here. */
20048 }
20049 /* FALLTHRU */
20055 {
20062 }
20063 /* FALLTHRU */
20067 {
20068 /* ??? SSE cost should be used here. */
20071 }
20073 {
20076 }
20078 {
20079 /* ??? SSE vector cost should be used here. */
20082 }
20083 /* FALLTHRU */
20088 else
20097 {
20098 /* This kind of construct is implemented using test[bwl].
20099 Treat it as if we had an AND. */
20104 }
20114 /* ??? SSE cost should be used here. */
20119 /* ??? SSE vector cost should be used here. */
20125 /* ??? SSE cost should be used here. */
20130 /* ??? SSE vector cost should be used here. */
20141 }
20142 }
20144 #if TARGET_MACHO
20148 /* Given a symbol name and its associated stub, write out the
20149 definition of the stub. */
20151 void
20153 {
20158 /* For 64-bit we shouldn't get here. */
20161 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20176 else
20183 {
20187 }
20188 else
20194 {
20197 }
20198 else
20207 }
20209 void
20211 {
20214 }
20217 /* Order the registers for register allocator. */
20219 void
20221 {
20225 /* First allocate the local general purpose registers. */
20230 /* Global general purpose registers. */
20235 /* x87 registers come first in case we are doing FP math
20236 using them. */
20241 /* SSE registers. */
20247 /* x87 registers. */
20255 /* Initialize the rest of array as we do not allocate some registers
20256 at all. */
20259 }
20261 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20262 struct attribute_spec.handler. */
20263 static tree
20265 tree args ATTRIBUTE_UNUSED,
20267 {
20270 {
20273 }
20274 else
20279 {
20283 }
20289 {
20293 }
20296 }
20298 static bool
20300 {
20304 }
20306 /* Returns an expression indicating where the this parameter is
20307 located on entry to the FUNCTION. */
20309 static rtx
20311 {
20316 {
20321 else
20324 }
20328 {
20333 }
20336 }
20338 /* Determine whether x86_output_mi_thunk can succeed. */
20340 static bool
20342 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
20344 {
20345 /* 64-bit can handle anything. */
20349 /* For 32-bit, everything's fine if we have one free register. */
20353 /* Need a free register for vcall_offset. */
20357 /* Need a free register for GOT references. */
20361 /* Otherwise ok. */
20363 }
20365 /* Output the assembler code for a thunk function. THUNK_DECL is the
20366 declaration for the thunk function itself, FUNCTION is the decl for
20367 the target function. DELTA is an immediate constant offset to be
20368 added to THIS. If VCALL_OFFSET is nonzero, the word at
20369 *(*this + vcall_offset) should be added to THIS. */
20371 static void
20375 {
20380 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
20381 pull it in now and let DELTA benefit. */
20385 {
20386 /* Put the this parameter into %eax. */
20390 }
20391 else
20394 /* Adjust the this parameter by a fixed constant. */
20396 {
20400 {
20402 {
20408 }
20410 }
20411 else
20413 }
20415 /* Adjust the this parameter by a value stored in the vtable. */
20417 {
20420 else
20421 {
20427 }
20433 else
20436 /* Adjust the this parameter. */
20439 {
20445 }
20449 else
20451 }
20453 /* If necessary, drop THIS back to its stack slot. */
20455 {
20459 }
20463 {
20466 /* All thunks should be in the same object as their target,
20467 and thus binds_local_p should be true. */
20470 else
20471 {
20477 }
20478 }
20479 else
20480 {
20483 else
20484 #if TARGET_MACHO
20486 {
20488 tmp = (gen_rtx_SYMBOL_REF
20494 }
20495 else
20497 {
20504 }
20505 }
20506 }
20508 static void
20510 {
20512 #if TARGET_MACHO
20514 #endif
20521 }
20523 int
20525 {
20538 }
20540 /* Output assembler code to FILE to increment profiler label # LABELNO
20541 for profiling a function entry. */
20542 void
20544 {
20546 {
20547 #ifndef NO_PROFILE_COUNTERS
20549 #endif
20553 else
20555 }
20557 {
20558 #ifndef NO_PROFILE_COUNTERS
20561 #endif
20563 }
20564 else
20565 {
20566 #ifndef NO_PROFILE_COUNTERS
20568 PROFILE_COUNT_REGISTER);
20569 #endif
20571 }
20572 }
20574 /* We don't have exact information about the insn sizes, but we may assume
20575 quite safely that we are informed about all 1 byte insns and memory
20576 address sizes. This is enough to eliminate unnecessary padding in
20577 99% of cases. */
20579 static int
20581 {
20587 /* Discard alignments we've emit and jump instructions. */
20596 /* Important case - calls are always 5 bytes.
20597 It is common to have many calls in the row. */
20605 /* For normal instructions we may rely on the sizes of addresses
20606 and the presence of symbol to require 4 bytes of encoding.
20607 This is not the case for jumps where references are PC relative. */
20609 {
20613 }
20616 else
20618 }
20620 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
20621 window. */
20623 static void
20625 {
20630 /* Look for all minimal intervals of instructions containing 4 jumps.
20631 The intervals are bounded by START and INSN. NBYTES is the total
20632 size of instructions in the interval including INSN and not including
20633 START. When the NBYTES is smaller than 16 bytes, it is possible
20634 that the end of START and INSN ends up in the same 16byte page.
20636 The smallest offset in the page INSN can start is the case where START
20637 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
20638 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
20639 */
20641 {
20651 njumps++;
20652 else
20656 {
20663 else
20666 }
20673 {
20680 }
20681 }
20682 }
20684 /* AMD Athlon works faster
20685 when RET is not destination of conditional jump or directly preceded
20686 by other jump instruction. We avoid the penalty by inserting NOP just
20687 before the RET instructions in such cases. */
20688 static void
20690 {
20691 edge e;
20692 edge_iterator ei;
20695 {
20698 rtx prev;
20708 {
20709 edge e;
20710 edge_iterator ei;
20716 }
20718 {
20724 /* Empty functions get branch mispredict even when the jump destination
20725 is not visible to us. */
20728 }
20730 {
20733 }
20734 }
20735 }
20737 /* Implement machine specific optimizations. We implement padding of returns
20738 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
20739 static void
20741 {
20746 }
20748 /* Return nonzero when QImode register that must be represented via REX prefix
20749 is used. */
20750 bool
20752 {
20760 }
20762 /* Return nonzero when P points to register encoded via REX prefix.
20763 Called via for_each_rtx. */
20764 static int
20766 {
20772 }
20774 /* Return true when INSN mentions register that must be encoded using REX
20775 prefix. */
20776 bool
20778 {
20780 }
20782 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
20783 optabs would emit if we didn't have TFmode patterns. */
20785 void
20787 {
20821 }
20822 \f
20823 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20824 with all elements equal to VAR. Return true if successful. */
20826 static bool
20829 {
20831 rtx x;
20834 {
20839 /* FALLTHRU */
20854 {
20860 }
20861 else
20862 {
20867 }
20878 {
20880 /* Extend HImode to SImode using a paradoxical SUBREG. */
20883 /* Insert the SImode value as low element of V4SImode vector. */
20888 const1_rtx);
20890 /* Cast the V4SImode vector back to a V8HImode vector. */
20893 /* Duplicate the low short through the whole low SImode word. */
20895 /* Cast the V8HImode vector back to a V4SImode vector. */
20898 /* Replicate the low element of the V4SImode vector. */
20900 /* Cast the V2SImode back to V8HImode, and store in target. */
20903 }
20910 {
20912 /* Extend QImode to SImode using a paradoxical SUBREG. */
20915 /* Insert the SImode value as low element of V4SImode vector. */
20920 const1_rtx);
20922 /* Cast the V4SImode vector back to a V16QImode vector. */
20925 /* Duplicate the low byte through the whole low SImode word. */
20928 /* Cast the V16QImode vector back to a V4SImode vector. */
20931 /* Replicate the low element of the V4SImode vector. */
20933 /* Cast the V2SImode back to V16QImode, and store in target. */
20936 }
20941 widen:
20942 /* Replicate the value once into the next wider mode and recurse. */
20957 }
20958 }
20960 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20961 whose ONE_VAR element is VAR, and other elements are zero. Return true
20962 if successful. */
20964 static bool
20967 {
20969 rtx new_target;
20973 {
20978 /* FALLTHRU */
20993 else
21000 {
21001 /* We need to shuffle the value to the correct position, so
21002 create a new pseudo to store the intermediate result. */
21004 /* With SSE2, we can use the integer shuffle insns. */
21006 {
21015 }
21017 /* Otherwise convert the intermediate result to V4SFmode and
21018 use the SSE1 shuffle instructions. */
21020 {
21023 }
21024 else
21037 }
21052 widen:
21056 /* Zero extend the variable element to SImode and recurse. */
21069 }
21070 }
21072 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21073 consisting of the values in VALS. It is known that all elements
21074 except ONE_VAR are constants. Return true if successful. */
21076 static bool
21079 {
21089 {
21094 /* For the two element vectors, it's just as easy to use
21095 the general case. */
21110 widen:
21111 /* There's no way to set one QImode entry easily. Combine
21112 the variable value with its adjacent constant value, and
21113 promote to an HImode set. */
21116 {
21121 }
21122 else
21123 {
21126 }
21140 }
21145 }
21147 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
21148 all values variable, and none identical. */
21150 static void
21153 {
21159 {
21164 /* FALLTHRU */
21168 /* For the two element vectors, we always implement VEC_CONCAT. */
21180 half:
21181 {
21182 rtvec v;
21184 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
21185 Recurse to load the two halves. */
21196 }
21207 }
21210 {
21218 }
21219 else
21220 {
21232 {
21236 {
21242 else
21243 {
21248 }
21249 }
21252 }
21257 {
21263 }
21265 {
21270 }
21271 else
21273 }
21274 }
21276 /* Initialize vector TARGET via VALS. Suppress the use of MMX
21277 instructions unless MMX_OK is true. */
21279 void
21281 {
21288 rtx x;
21291 {
21299 }
21301 /* Constants are best loaded from the constant pool. */
21303 {
21306 }
21308 /* If all values are identical, broadcast the value. */
21314 /* Values where only one field is non-constant are best loaded from
21315 the pool and overwritten via move later. */
21317 {
21321 one_var))
21326 }
21329 }
21331 void
21333 {
21337 rtx tmp;
21340 {
21344 {
21349 else
21353 }
21362 {
21365 /* For the two element vectors, we implement a VEC_CONCAT with
21366 the extraction of the other element. */
21373 else
21378 }
21387 {
21393 /* tmp = target = A B C D */
21395 /* target = A A B B */
21397 /* target = X A B B */
21399 /* target = A X C D */
21406 /* tmp = target = A B C D */
21408 /* tmp = X B C D */
21410 /* target = A B X D */
21417 /* tmp = target = A B C D */
21419 /* tmp = X B C D */
21421 /* target = A B X D */
21429 }
21437 /* Element 0 handled by vec_merge below. */
21439 {
21442 }
21445 {
21446 /* With SSE2, use integer shuffles to swap element 0 and ELT,
21447 store into element 0, then shuffle them back. */
21464 }
21465 else
21466 {
21467 /* For SSE1, we have to reuse the V4SF code. */
21470 }
21487 }
21490 {
21494 }
21495 else
21496 {
21505 }
21506 }
21508 void
21510 {
21514 rtx tmp;
21517 {
21522 /* FALLTHRU */
21535 {
21555 }
21567 {
21569 {
21589 }
21593 }
21594 else
21595 {
21596 /* For SSE1, we have to reuse the V4SF code. */
21600 }
21615 /* ??? Could extract the appropriate HImode element and shift. */
21618 }
21621 {
21625 /* Let the rtl optimizers know about the zero extension performed. */
21627 {
21630 }
21633 }
21634 else
21635 {
21642 }
21643 }
21645 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
21646 pattern to reduce; DEST is the destination; IN is the input vector. */
21648 void
21650 {
21664 }
21665 \f
21666 /* Target hook for scalar_mode_supported_p. */
21667 static bool
21669 {
21674 else
21676 }
21678 /* Implements target hook vector_mode_supported_p. */
21679 static bool
21681 {
21691 }
21693 /* Worker function for TARGET_MD_ASM_CLOBBERS.
21695 We do this in the new i386 backend to maintain source compatibility
21696 with the old cc0-based compiler. */
21698 static tree
21700 tree inputs ATTRIBUTE_UNUSED,
21701 tree clobbers)
21702 {
21704 clobbers);
21706 clobbers);
21708 }
21710 /* Implements target vector targetm.asm.encode_section_info. This
21711 is not used by netware. */
21713 static void ATTRIBUTE_UNUSED
21715 {
21722 }
21724 /* Worker function for REVERSE_CONDITION. */
21726 enum rtx_code
21728 {
21732 }
21734 /* Output code to perform an x87 FP register move, from OPERANDS[1]
21735 to OPERANDS[0]. */
21739 {
21741 {
21744 {
21748 }
21752 }
21754 {
21758 else
21759 {
21760 /* There is no non-popping store to memory for XFmode.
21761 So if we need one, follow the store with a load. */
21764 else
21766 }
21767 }
21768 else
21770 }
21772 /* Output code to perform a conditional jump to LABEL, if C2 flag in
21773 FP status register is set. */
21775 void
21777 {
21779 rtx temp;
21784 {
21789 }
21790 else
21791 {
21796 }
21800 pc_rtx);
21805 }
21807 /* Output code to perform a log1p XFmode calculation. */
21810 {
21821 XFmode)));
21835 }
21837 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
21839 static void ATTRIBUTE_UNUSED
21841 tree decl)
21842 {
21843 /* With Binutils 2.15, the "@unwind" marker must be specified on
21844 every occurrence of the ".eh_frame" section, not just the first
21845 one. */
21848 {
21852 }
21854 }
21856 /* Return the mangling of TYPE if it is an extended fundamental type. */
21860 {
21862 {
21864 /* __float128 is "g". */
21867 /* "long double" or __float80 is "e". */
21871 }
21872 }
21874 /* For 32-bit code we can save PIC register setup by using
21875 __stack_chk_fail_local hidden function instead of calling
21876 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
21877 register, so it is better to call __stack_chk_fail directly. */
21879 static tree
21881 {
21882 return TARGET_64BIT
21885 }
21887 /* Select a format to encode pointers in exception handling data. CODE
21888 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
21889 true if the symbol may be affected by dynamic relocations.
21891 ??? All x86 object file formats are capable of representing this.
21892 After all, the relocation needed is the same as for the call insn.
21893 Whether or not a particular assembler allows us to enter such, I
21894 guess we'll have to see. */
21895 int
21897 {
21899 {
21906 }
21911 }
21912 \f
21913 /* Expand copysign from SIGN to the positive value ABS_VALUE
21914 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
21915 the sign-bit. */
21916 static void
21918 {
21922 {
21925 {
21926 /* We need to generate a scalar mode mask in this case. */
21931 }
21932 }
21933 else
21939 }
21941 /* Expand fabs (OP0) and return a new rtx that holds the result. The
21942 mask for masking out the sign-bit is stored in *SMASK, if that is
21943 non-null. */
21944 static rtx
21946 {
21953 {
21954 /* We need to generate a scalar mode mask in this case. */
21959 }
21967 }
21969 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
21970 swapping the operands if SWAP_OPERANDS is true. The expanded
21971 code is a forward jump to a newly created label in case the
21972 comparison is true. The generated label rtx is returned. */
21973 static rtx
21976 {
21980 {
21984 }
21997 }
21999 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
22000 using comparison code CODE. Operands are swapped for the comparison if
22001 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
22002 static rtx
22005 {
22010 {
22014 }
22019 else
22024 }
22026 /* Generate and return a rtx of mode MODE for 2**n where n is the number
22027 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
22028 static rtx
22030 {
22031 REAL_VALUE_TYPE TWO52r;
22032 rtx TWO52;
22039 }
22041 /* Expand SSE sequence for computing lround from OP1 storing
22042 into OP0. */
22043 void
22045 {
22046 /* C code for the stuff we're doing below:
22047 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
22048 return (long)tmp;
22049 */
22053 rtx adj;
22055 /* load nextafter (0.5, 0.0) */
22060 /* adj = copysign (0.5, op1) */
22064 /* adj = op1 + adj */
22067 /* op0 = (imode)adj */
22069 }
22071 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
22072 into OPERAND0. */
22073 void
22075 {
22076 /* C code for the stuff we're doing below (for do_floor):
22077 xi = (long)op1;
22078 xi -= (double)xi > op1 ? 1 : 0;
22079 return xi;
22080 */
22085 /* reg = (long)op1 */
22089 /* freg = (double)reg */
22093 /* ireg = (freg > op1) ? ireg - 1 : ireg */
22104 }
22106 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
22107 result in OPERAND0. */
22108 void
22110 {
22111 /* C code for the stuff we're doing below:
22112 xa = fabs (operand1);
22113 if (!isless (xa, 2**52))
22114 return operand1;
22115 xa = xa + 2**52 - 2**52;
22116 return copysign (xa, operand1);
22117 */
22124 /* xa = abs (operand1) */
22127 /* if (!isless (xa, TWO52)) goto label; */
22140 }
22142 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
22143 into OPERAND0. */
22144 void
22146 {
22147 /* C code for the stuff we expand below.
22148 double xa = fabs (x), x2;
22149 if (!isless (xa, TWO52))
22150 return x;
22151 xa = xa + TWO52 - TWO52;
22152 x2 = copysign (xa, x);
22153 Compensate. Floor:
22154 if (x2 > x)
22155 x2 -= 1;
22156 Compensate. Ceil:
22157 if (x2 < x)
22158 x2 -= -1;
22159 return x2;
22160 */
22166 /* Temporary for holding the result, initialized to the input
22167 operand to ease control flow. */
22171 /* xa = abs (operand1) */
22174 /* if (!isless (xa, TWO52)) goto label; */
22177 /* xa = xa + TWO52 - TWO52; */
22181 /* xa = copysign (xa, operand1) */
22184 /* generate 1.0 or -1.0 */
22189 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
22193 /* We always need to subtract here to preserve signed zero. */
22202 }
22204 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
22205 into OPERAND0. */
22206 void
22208 {
22209 /* C code for the stuff we expand below.
22210 double xa = fabs (x), x2;
22211 if (!isless (xa, TWO52))
22212 return x;
22213 x2 = (double)(long)x;
22214 Compensate. Floor:
22215 if (x2 > x)
22216 x2 -= 1;
22217 Compensate. Ceil:
22218 if (x2 < x)
22219 x2 += 1;
22220 if (HONOR_SIGNED_ZEROS (mode))
22221 return copysign (x2, x);
22222 return x2;
22223 */
22229 /* Temporary for holding the result, initialized to the input
22230 operand to ease control flow. */
22234 /* xa = abs (operand1) */
22237 /* if (!isless (xa, TWO52)) goto label; */
22240 /* xa = (double)(long)x */
22245 /* generate 1.0 */
22248 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
22263 }
22265 /* Expand SSE sequence for computing round from OPERAND1 storing
22266 into OPERAND0. Sequence that works without relying on DImode truncation
22267 via cvttsd2siq that is only available on 64bit targets. */
22268 void
22270 {
22271 /* C code for the stuff we expand below.
22272 double xa = fabs (x), xa2, x2;
22273 if (!isless (xa, TWO52))
22274 return x;
22275 Using the absolute value and copying back sign makes
22276 -0.0 -> -0.0 correct.
22277 xa2 = xa + TWO52 - TWO52;
22278 Compensate.
22279 dxa = xa2 - xa;
22280 if (dxa <= -0.5)
22281 xa2 += 1;
22282 else if (dxa > 0.5)
22283 xa2 -= 1;
22284 x2 = copysign (xa2, x);
22285 return x2;
22286 */
22292 /* Temporary for holding the result, initialized to the input
22293 operand to ease control flow. */
22297 /* xa = abs (operand1) */
22300 /* if (!isless (xa, TWO52)) goto label; */
22303 /* xa2 = xa + TWO52 - TWO52; */
22307 /* dxa = xa2 - xa; */
22310 /* generate 0.5, 1.0 and -0.5 */
22316 /* Compensate. */
22318 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
22323 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
22329 /* res = copysign (xa2, operand1) */
22336 }
22338 /* Expand SSE sequence for computing trunc from OPERAND1 storing
22339 into OPERAND0. */
22340 void
22342 {
22343 /* C code for SSE variant we expand below.
22344 double xa = fabs (x), x2;
22345 if (!isless (xa, TWO52))
22346 return x;
22347 x2 = (double)(long)x;
22348 if (HONOR_SIGNED_ZEROS (mode))
22349 return copysign (x2, x);
22350 return x2;
22351 */
22357 /* Temporary for holding the result, initialized to the input
22358 operand to ease control flow. */
22362 /* xa = abs (operand1) */
22365 /* if (!isless (xa, TWO52)) goto label; */
22368 /* x = (double)(long)x */
22380 }
22382 /* Expand SSE sequence for computing trunc from OPERAND1 storing
22383 into OPERAND0. */
22384 void
22386 {
22390 /* C code for SSE variant we expand below.
22391 double xa = fabs (x), x2;
22392 if (!isless (xa, TWO52))
22393 return x;
22394 xa2 = xa + TWO52 - TWO52;
22395 Compensate:
22396 if (xa2 > xa)
22397 xa2 -= 1.0;
22398 x2 = copysign (xa2, x);
22399 return x2;
22400 */
22404 /* Temporary for holding the result, initialized to the input
22405 operand to ease control flow. */
22409 /* xa = abs (operand1) */
22412 /* if (!isless (xa, TWO52)) goto label; */
22415 /* res = xa + TWO52 - TWO52; */
22420 /* generate 1.0 */
22423 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
22431 /* res = copysign (res, operand1) */
22438 }
22440 /* Expand SSE sequence for computing round from OPERAND1 storing
22441 into OPERAND0. */
22442 void
22444 {
22445 /* C code for the stuff we're doing below:
22446 double xa = fabs (x);
22447 if (!isless (xa, TWO52))
22448 return x;
22449 xa = (double)(long)(xa + nextafter (0.5, 0.0));
22450 return copysign (xa, x);
22451 */
22457 /* Temporary for holding the result, initialized to the input
22458 operand to ease control flow. */
22466 /* load nextafter (0.5, 0.0) */
22471 /* xa = xa + 0.5 */
22475 /* xa = (double)(int64_t)xa */
22480 /* res = copysign (xa, operand1) */
22487 }
22489 \f
22490 /* Table of valid machine attributes. */
22492 {
22493 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
22494 /* Stdcall attribute says callee is responsible for popping arguments
22495 if they are not variable. */
22497 /* Fastcall attribute says callee is responsible for popping arguments
22498 if they are not variable. */
22500 /* Cdecl attribute says the callee is a normal C declaration */
22502 /* Regparm attribute specifies how many integer arguments are to be
22503 passed in registers. */
22505 /* Sseregparm attribute says we are using x86_64 calling conventions
22506 for FP arguments. */
22508 /* force_align_arg_pointer says this function realigns the stack at entry. */
22511 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22515 #endif
22518 #ifdef SUBTARGET_ATTRIBUTE_TABLE
22519 SUBTARGET_ATTRIBUTE_TABLE,
22520 #endif
22522 };
22524 /* Initialize the GCC target structure. */
22525 #undef TARGET_ATTRIBUTE_TABLE
22526 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
22527 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22528 # undef TARGET_MERGE_DECL_ATTRIBUTES
22529 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
22530 #endif
22532 #undef TARGET_COMP_TYPE_ATTRIBUTES
22533 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
22535 #undef TARGET_INIT_BUILTINS
22536 #define TARGET_INIT_BUILTINS ix86_init_builtins
22537 #undef TARGET_EXPAND_BUILTIN
22538 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
22540 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22541 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION ix86_builtin_vectorized_function
22542 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
22543 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_builtin_conversion
22545 #undef TARGET_ASM_FUNCTION_EPILOGUE
22546 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
22548 #undef TARGET_ENCODE_SECTION_INFO
22549 #ifndef SUBTARGET_ENCODE_SECTION_INFO
22550 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
22551 #else
22552 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
22553 #endif
22555 #undef TARGET_ASM_OPEN_PAREN
22557 #undef TARGET_ASM_CLOSE_PAREN
22560 #undef TARGET_ASM_ALIGNED_HI_OP
22561 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
22562 #undef TARGET_ASM_ALIGNED_SI_OP
22563 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
22564 #ifdef ASM_QUAD
22565 #undef TARGET_ASM_ALIGNED_DI_OP
22566 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
22567 #endif
22569 #undef TARGET_ASM_UNALIGNED_HI_OP
22570 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
22571 #undef TARGET_ASM_UNALIGNED_SI_OP
22572 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
22573 #undef TARGET_ASM_UNALIGNED_DI_OP
22574 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
22576 #undef TARGET_SCHED_ADJUST_COST
22577 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
22578 #undef TARGET_SCHED_ISSUE_RATE
22579 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
22580 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22581 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22582 ia32_multipass_dfa_lookahead
22584 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22585 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
22587 #ifdef HAVE_AS_TLS
22588 #undef TARGET_HAVE_TLS
22589 #define TARGET_HAVE_TLS true
22590 #endif
22591 #undef TARGET_CANNOT_FORCE_CONST_MEM
22592 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
22593 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22594 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
22596 #undef TARGET_DELEGITIMIZE_ADDRESS
22597 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
22599 #undef TARGET_MS_BITFIELD_LAYOUT_P
22600 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
22602 #if TARGET_MACHO
22603 #undef TARGET_BINDS_LOCAL_P
22604 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
22605 #endif
22606 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22607 #undef TARGET_BINDS_LOCAL_P
22608 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
22609 #endif
22611 #undef TARGET_ASM_OUTPUT_MI_THUNK
22612 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
22613 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22614 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
22616 #undef TARGET_ASM_FILE_START
22617 #define TARGET_ASM_FILE_START x86_file_start
22619 #undef TARGET_DEFAULT_TARGET_FLAGS
22620 #define TARGET_DEFAULT_TARGET_FLAGS \
22621 (TARGET_DEFAULT \
22622 | TARGET_64BIT_DEFAULT \
22623 | TARGET_SUBTARGET_DEFAULT \
22624 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
22626 #undef TARGET_HANDLE_OPTION
22627 #define TARGET_HANDLE_OPTION ix86_handle_option
22629 #undef TARGET_RTX_COSTS
22630 #define TARGET_RTX_COSTS ix86_rtx_costs
22631 #undef TARGET_ADDRESS_COST
22632 #define TARGET_ADDRESS_COST ix86_address_cost
22634 #undef TARGET_FIXED_CONDITION_CODE_REGS
22635 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
22636 #undef TARGET_CC_MODES_COMPATIBLE
22637 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
22639 #undef TARGET_MACHINE_DEPENDENT_REORG
22640 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
22642 #undef TARGET_BUILD_BUILTIN_VA_LIST
22643 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
22645 #undef TARGET_MD_ASM_CLOBBERS
22646 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
22648 #undef TARGET_PROMOTE_PROTOTYPES
22649 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
22650 #undef TARGET_STRUCT_VALUE_RTX
22651 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
22652 #undef TARGET_SETUP_INCOMING_VARARGS
22653 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
22654 #undef TARGET_MUST_PASS_IN_STACK
22655 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
22656 #undef TARGET_PASS_BY_REFERENCE
22657 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
22658 #undef TARGET_INTERNAL_ARG_POINTER
22659 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
22660 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
22661 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
22662 #undef TARGET_STRICT_ARGUMENT_NAMING
22663 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
22665 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22666 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
22668 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22669 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
22671 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22672 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
22674 #ifdef HAVE_AS_TLS
22675 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22676 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
22677 #endif
22679 #ifdef SUBTARGET_INSERT_ATTRIBUTES
22680 #undef TARGET_INSERT_ATTRIBUTES
22681 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
22682 #endif
22684 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
22685 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
22687 #undef TARGET_STACK_PROTECT_FAIL
22688 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
22690 #undef TARGET_FUNCTION_VALUE
22691 #define TARGET_FUNCTION_VALUE ix86_function_value
22694 \f