1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
92 ;; We have a special constraint for pattern matching.
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
123 ; TLS relocation specifiers
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
139 ; Stack Smashing Protector
145 ;; UNSPEC_VOLATILE usage
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
177 ; Sibling call register.
179 ; Literal pool base register.
181 ; Return address register.
183 ; Condition code register.
185 ; Thread local storage pointer register.
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimpdf,fsimpsf,
203 floaddf,floadsf,fstoredf,fstoresf,
204 fmuldf,fmulsf,fdivdf,fdivsf,
205 ftoi,itof,fsqrtdf,fsqrtsf,
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (cond [(eq_attr "op_type" "E") (const_string "reg")
217 (eq_attr "op_type" "RR") (const_string "reg")
218 (eq_attr "op_type" "RX") (const_string "agen")
219 (eq_attr "op_type" "RI") (const_string "reg")
220 (eq_attr "op_type" "RRE") (const_string "reg")
221 (eq_attr "op_type" "RS") (const_string "agen")
222 (eq_attr "op_type" "RSI") (const_string "agen")
223 (eq_attr "op_type" "S") (const_string "agen")
224 (eq_attr "op_type" "SI") (const_string "agen")
225 (eq_attr "op_type" "SS") (const_string "agen")
226 (eq_attr "op_type" "SSE") (const_string "agen")
227 (eq_attr "op_type" "RXE") (const_string "agen")
228 (eq_attr "op_type" "RSE") (const_string "agen")
229 (eq_attr "op_type" "RIL") (const_string "agen")
230 (eq_attr "op_type" "RXY") (const_string "agen")
231 (eq_attr "op_type" "RSY") (const_string "agen")
232 (eq_attr "op_type" "SIY") (const_string "agen")]
233 (const_string "agen")))
237 (define_attr "length" ""
238 (cond [(eq_attr "op_type" "E") (const_int 2)
239 (eq_attr "op_type" "RR") (const_int 2)
240 (eq_attr "op_type" "RX") (const_int 4)
241 (eq_attr "op_type" "RI") (const_int 4)
242 (eq_attr "op_type" "RRE") (const_int 4)
243 (eq_attr "op_type" "RS") (const_int 4)
244 (eq_attr "op_type" "RSI") (const_int 4)
245 (eq_attr "op_type" "S") (const_int 4)
246 (eq_attr "op_type" "SI") (const_int 4)
247 (eq_attr "op_type" "SS") (const_int 6)
248 (eq_attr "op_type" "SSE") (const_int 6)
249 (eq_attr "op_type" "RXE") (const_int 6)
250 (eq_attr "op_type" "RSE") (const_int 6)
251 (eq_attr "op_type" "RIL") (const_int 6)
252 (eq_attr "op_type" "RXY") (const_int 6)
253 (eq_attr "op_type" "RSY") (const_int 6)
254 (eq_attr "op_type" "SIY") (const_int 6)]
258 ;; Processor type. This attribute must exactly match the processor_type
259 ;; enumeration in s390.h. The current machine description does not
260 ;; distinguish between g5 and g6, but there are differences between the two
261 ;; CPUs could in theory be modeled.
263 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
264 (const (symbol_ref "s390_tune")))
266 ;; Pipeline description for z900. For lack of anything better,
267 ;; this description is also used for the g5 and g6.
270 ;; Pipeline description for z990.
274 (include "predicates.md")
281 ;; This mode macro allows DF and SF patterns to be generated from the
283 (define_mode_macro FPR [DF SF])
285 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
286 ;; from the same template.
287 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
289 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
290 ;; from the same template.
291 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
292 (define_mode_macro DSI [DI SI])
294 ;; This mode macro allows :P to be used for patterns that operate on
295 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
296 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
297 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
299 ;; This mode macro allows the QI and HI patterns to be defined from
300 ;; the same template.
301 (define_mode_macro HQI [HI QI])
303 ;; This mode macro allows the integer patterns to be defined from the
305 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
307 ;; This macro allows to unify all 'bCOND' expander patterns.
308 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
309 ordered uneq unlt ungt unle unge ltgt])
311 ;; This macro allows to unify all 'sCOND' patterns.
312 (define_code_macro SCOND [ltu gtu leu geu])
314 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
315 ;; the same template.
316 (define_code_macro SHIFT [ashift lshiftrt])
319 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
320 ;; and "ltebr" in SFmode.
321 (define_mode_attr de [(DF "d") (SF "e")])
323 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
324 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
325 (define_mode_attr dee [(DF "d") (SF "ee")])
327 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
328 ;; 'ashift' and "srdl" in 'lshiftrt'.
329 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
331 ;; In SHIFT templates, this attribute holds the correct standard name for the
332 ;; pattern itself and the corresponding function calls.
333 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
335 ;; This attribute handles differences in the instruction 'type' and will result
336 ;; in "RRE" for DImode and "RR" for SImode.
337 (define_mode_attr E [(DI "E") (SI "")])
339 ;; This attribute handles differences in the instruction 'type' and will result
340 ;; in "RSE" for TImode and "RS" for DImode.
341 (define_mode_attr TE [(TI "E") (DI "")])
343 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
344 ;; and "lcr" in SImode.
345 (define_mode_attr g [(DI "g") (SI "")])
347 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
348 ;; and "cds" in DImode.
349 (define_mode_attr tg [(TI "g") (DI "")])
351 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
352 ;; and "cfdbr" in SImode.
353 (define_mode_attr gf [(DI "g") (SI "f")])
355 ;; ICM mask required to load MODE value into the highest subreg
356 ;; of a SImode register.
357 (define_mode_attr icm_hi [(HI "12") (QI "8")])
359 ;; ICM mask required to load MODE value into the lowest subreg
360 ;; of a SImode register.
361 (define_mode_attr icm_lo [(HI "3") (QI "1")])
363 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
364 ;; HImode and "llgc" in QImode.
365 (define_mode_attr hc [(HI "h") (QI "c")])
367 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
369 (define_mode_attr DBL [(DI "TI") (SI "DI")])
371 ;; Maximum unsigned integer that fits in MODE.
372 (define_mode_attr max_uint [(HI "65535") (QI "255")])
376 ;;- Compare instructions.
379 (define_expand "cmp<mode>"
380 [(set (reg:CC CC_REGNUM)
381 (compare:CC (match_operand:GPR 0 "register_operand" "")
382 (match_operand:GPR 1 "general_operand" "")))]
385 s390_compare_op0 = operands[0];
386 s390_compare_op1 = operands[1];
390 (define_expand "cmp<mode>"
391 [(set (reg:CC CC_REGNUM)
392 (compare:CC (match_operand:FPR 0 "register_operand" "")
393 (match_operand:FPR 1 "general_operand" "")))]
396 s390_compare_op0 = operands[0];
397 s390_compare_op1 = operands[1];
402 ; Test-under-Mask instructions
404 (define_insn "*tmqi_mem"
405 [(set (reg CC_REGNUM)
406 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
407 (match_operand:QI 1 "immediate_operand" "n,n"))
408 (match_operand:QI 2 "immediate_operand" "n,n")))]
409 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
413 [(set_attr "op_type" "SI,SIY")])
415 (define_insn "*tmdi_reg"
416 [(set (reg CC_REGNUM)
417 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
418 (match_operand:DI 1 "immediate_operand"
419 "N0HD0,N1HD0,N2HD0,N3HD0"))
420 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
422 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
423 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
429 [(set_attr "op_type" "RI")])
431 (define_insn "*tmsi_reg"
432 [(set (reg CC_REGNUM)
433 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
434 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
435 (match_operand:SI 2 "immediate_operand" "n,n")))]
436 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
437 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
441 [(set_attr "op_type" "RI")])
443 (define_insn "*tm<mode>_full"
444 [(set (reg CC_REGNUM)
445 (compare (match_operand:HQI 0 "register_operand" "d")
446 (match_operand:HQI 1 "immediate_operand" "n")))]
447 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
449 [(set_attr "op_type" "RI")])
452 ; Load-and-Test instructions
454 (define_insn "*tstdi_sign"
455 [(set (reg CC_REGNUM)
456 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
457 (const_int 32)) (const_int 32))
458 (match_operand:DI 1 "const0_operand" "")))
459 (set (match_operand:DI 2 "register_operand" "=d")
460 (sign_extend:DI (match_dup 0)))]
461 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
463 [(set_attr "op_type" "RRE")])
465 (define_insn "*tstdi_extimm"
466 [(set (reg CC_REGNUM)
467 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
468 (match_operand:DI 1 "const0_operand" "")))
469 (set (match_operand:DI 2 "register_operand" "=d,d")
471 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
475 [(set_attr "op_type" "RRE,RXY")])
477 (define_insn "*tstdi_cconly_extimm"
478 [(set (reg CC_REGNUM)
479 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
480 (match_operand:DI 1 "const0_operand" "")))
481 (clobber (match_scratch:DI 2 "=X,d"))]
482 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
486 [(set_attr "op_type" "RRE,RXY")])
488 (define_insn "*tstdi"
489 [(set (reg CC_REGNUM)
490 (compare (match_operand:DI 0 "register_operand" "d")
491 (match_operand:DI 1 "const0_operand" "")))
492 (set (match_operand:DI 2 "register_operand" "=d")
494 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
496 [(set_attr "op_type" "RRE")])
498 (define_insn "*tstdi_cconly"
499 [(set (reg CC_REGNUM)
500 (compare (match_operand:DI 0 "register_operand" "d")
501 (match_operand:DI 1 "const0_operand" "")))]
502 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
504 [(set_attr "op_type" "RRE")])
506 (define_insn "*tstdi_cconly_31"
507 [(set (reg CC_REGNUM)
508 (compare (match_operand:DI 0 "register_operand" "d")
509 (match_operand:DI 1 "const0_operand" "")))]
510 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
512 [(set_attr "op_type" "RS")
513 (set_attr "atype" "reg")])
515 (define_insn "*tstsi_extimm"
516 [(set (reg CC_REGNUM)
517 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
518 (match_operand:SI 1 "const0_operand" "")))
519 (set (match_operand:SI 2 "register_operand" "=d,d")
521 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
525 [(set_attr "op_type" "RR,RXY")])
527 (define_insn "*tstsi_cconly_extimm"
528 [(set (reg CC_REGNUM)
529 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
530 (match_operand:SI 1 "const0_operand" "")))
531 (clobber (match_scratch:SI 2 "=X,d"))]
532 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
536 [(set_attr "op_type" "RR,RXY")])
538 (define_insn "*tstsi"
539 [(set (reg CC_REGNUM)
540 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
541 (match_operand:SI 1 "const0_operand" "")))
542 (set (match_operand:SI 2 "register_operand" "=d,d,d")
544 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
549 [(set_attr "op_type" "RR,RS,RSY")])
551 (define_insn "*tstsi_cconly"
552 [(set (reg CC_REGNUM)
553 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
554 (match_operand:SI 1 "const0_operand" "")))
555 (clobber (match_scratch:SI 2 "=X,d,d"))]
556 "s390_match_ccmode(insn, CCSmode)"
561 [(set_attr "op_type" "RR,RS,RSY")])
563 (define_insn "*tstsi_cconly2"
564 [(set (reg CC_REGNUM)
565 (compare (match_operand:SI 0 "register_operand" "d")
566 (match_operand:SI 1 "const0_operand" "")))]
567 "s390_match_ccmode(insn, CCSmode)"
569 [(set_attr "op_type" "RR")])
571 (define_insn "*tst<mode>CCT"
572 [(set (reg CC_REGNUM)
573 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
574 (match_operand:HQI 1 "const0_operand" "")))
575 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
577 "s390_match_ccmode(insn, CCTmode)"
580 icmy\t%2,<icm_lo>,%S0
582 [(set_attr "op_type" "RS,RSY,RI")])
584 (define_insn "*tsthiCCT_cconly"
585 [(set (reg CC_REGNUM)
586 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
587 (match_operand:HI 1 "const0_operand" "")))
588 (clobber (match_scratch:HI 2 "=d,d,X"))]
589 "s390_match_ccmode(insn, CCTmode)"
594 [(set_attr "op_type" "RS,RSY,RI")])
596 (define_insn "*tstqiCCT_cconly"
597 [(set (reg CC_REGNUM)
598 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
599 (match_operand:QI 1 "const0_operand" "")))]
600 "s390_match_ccmode(insn, CCTmode)"
605 [(set_attr "op_type" "SI,SIY,RI")])
607 (define_insn "*tst<mode>"
608 [(set (reg CC_REGNUM)
609 (compare (match_operand:HQI 0 "s_operand" "Q,S")
610 (match_operand:HQI 1 "const0_operand" "")))
611 (set (match_operand:HQI 2 "register_operand" "=d,d")
613 "s390_match_ccmode(insn, CCSmode)"
616 icmy\t%2,<icm_lo>,%S0"
617 [(set_attr "op_type" "RS,RSY")])
619 (define_insn "*tst<mode>_cconly"
620 [(set (reg CC_REGNUM)
621 (compare (match_operand:HQI 0 "s_operand" "Q,S")
622 (match_operand:HQI 1 "const0_operand" "")))
623 (clobber (match_scratch:HQI 2 "=d,d"))]
624 "s390_match_ccmode(insn, CCSmode)"
627 icmy\t%2,<icm_lo>,%S0"
628 [(set_attr "op_type" "RS,RSY")])
631 ; Compare (equality) instructions
633 (define_insn "*cmpdi_cct"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
636 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
637 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
644 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
646 (define_insn "*cmpsi_cct"
647 [(set (reg CC_REGNUM)
648 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
649 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
650 "s390_match_ccmode (insn, CCTmode)"
658 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
661 ; Compare (signed) instructions
663 (define_insn "*cmpdi_ccs_sign"
664 [(set (reg CC_REGNUM)
665 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
666 (match_operand:DI 0 "register_operand" "d,d")))]
667 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
671 [(set_attr "op_type" "RRE,RXY")])
673 (define_insn "*cmpdi_ccs"
674 [(set (reg CC_REGNUM)
675 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
676 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
677 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
683 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
685 (define_insn "*cmpsi_ccs_sign"
686 [(set (reg CC_REGNUM)
687 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
688 (match_operand:SI 0 "register_operand" "d,d")))]
689 "s390_match_ccmode(insn, CCSRmode)"
693 [(set_attr "op_type" "RX,RXY")])
695 (define_insn "*cmpsi_ccs"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
698 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
699 "s390_match_ccmode(insn, CCSmode)"
706 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
709 ; Compare (unsigned) instructions
711 (define_insn "*cmpdi_ccu_zero"
712 [(set (reg CC_REGNUM)
713 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
714 (match_operand:DI 0 "register_operand" "d,d")))]
715 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
719 [(set_attr "op_type" "RRE,RXY")])
721 (define_insn "*cmpdi_ccu"
722 [(set (reg CC_REGNUM)
723 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
724 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
725 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
732 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
734 (define_insn "*cmpsi_ccu"
735 [(set (reg CC_REGNUM)
736 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
737 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
738 "s390_match_ccmode (insn, CCUmode)"
746 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
748 (define_insn "*cmphi_ccu"
749 [(set (reg CC_REGNUM)
750 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
751 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
752 "s390_match_ccmode (insn, CCUmode)
753 && !register_operand (operands[1], HImode)"
759 [(set_attr "op_type" "RS,RSY,SS,SS")])
761 (define_insn "*cmpqi_ccu"
762 [(set (reg CC_REGNUM)
763 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
764 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
765 "s390_match_ccmode (insn, CCUmode)
766 && !register_operand (operands[1], QImode)"
774 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
777 ; Block compare (CLC) instruction patterns.
780 [(set (reg CC_REGNUM)
781 (compare (match_operand:BLK 0 "memory_operand" "Q")
782 (match_operand:BLK 1 "memory_operand" "Q")))
783 (use (match_operand 2 "const_int_operand" "n"))]
784 "s390_match_ccmode (insn, CCUmode)
785 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
786 "clc\t%O0(%2,%R0),%S1"
787 [(set_attr "op_type" "SS")])
790 [(set (reg CC_REGNUM)
791 (compare (match_operand 0 "memory_operand" "")
792 (match_operand 1 "memory_operand" "")))]
794 && s390_match_ccmode (insn, CCUmode)
795 && GET_MODE (operands[0]) == GET_MODE (operands[1])
796 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
798 [(set (match_dup 0) (match_dup 1))
799 (use (match_dup 2))])]
801 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
802 operands[0] = adjust_address (operands[0], BLKmode, 0);
803 operands[1] = adjust_address (operands[1], BLKmode, 0);
805 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
806 operands[0], operands[1]);
807 operands[0] = SET_DEST (PATTERN (curr_insn));
811 ; (DF|SF) instructions
813 (define_insn "*cmp<mode>_ccs_0"
814 [(set (reg CC_REGNUM)
815 (compare (match_operand:FPR 0 "register_operand" "f")
816 (match_operand:FPR 1 "const0_operand" "")))]
817 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
819 [(set_attr "op_type" "RRE")
820 (set_attr "type" "fsimp<mode>")])
822 (define_insn "*cmp<mode>_ccs_0_ibm"
823 [(set (reg CC_REGNUM)
824 (compare (match_operand:FPR 0 "register_operand" "f")
825 (match_operand:FPR 1 "const0_operand" "")))]
826 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
828 [(set_attr "op_type" "RR")
829 (set_attr "type" "fsimp<mode>")])
831 (define_insn "*cmp<mode>_ccs"
832 [(set (reg CC_REGNUM)
833 (compare (match_operand:FPR 0 "register_operand" "f,f")
834 (match_operand:FPR 1 "general_operand" "f,R")))]
835 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
839 [(set_attr "op_type" "RRE,RXE")
840 (set_attr "type" "fsimp<mode>")])
842 (define_insn "*cmp<mode>_ccs_ibm"
843 [(set (reg CC_REGNUM)
844 (compare (match_operand:FPR 0 "register_operand" "f,f")
845 (match_operand:FPR 1 "general_operand" "f,R")))]
846 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
850 [(set_attr "op_type" "RR,RX")
851 (set_attr "type" "fsimp<mode>")])
855 ;;- Move instructions.
859 ; movti instruction pattern(s).
863 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
864 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
872 [(set_attr "op_type" "RSY,RSY,*,*,SS")
873 (set_attr "type" "lm,stm,*,*,*")])
876 [(set (match_operand:TI 0 "nonimmediate_operand" "")
877 (match_operand:TI 1 "general_operand" ""))]
878 "TARGET_64BIT && reload_completed
879 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
880 [(set (match_dup 2) (match_dup 4))
881 (set (match_dup 3) (match_dup 5))]
883 operands[2] = operand_subword (operands[0], 0, 0, TImode);
884 operands[3] = operand_subword (operands[0], 1, 0, TImode);
885 operands[4] = operand_subword (operands[1], 0, 0, TImode);
886 operands[5] = operand_subword (operands[1], 1, 0, TImode);
890 [(set (match_operand:TI 0 "nonimmediate_operand" "")
891 (match_operand:TI 1 "general_operand" ""))]
892 "TARGET_64BIT && reload_completed
893 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
894 [(set (match_dup 2) (match_dup 4))
895 (set (match_dup 3) (match_dup 5))]
897 operands[2] = operand_subword (operands[0], 1, 0, TImode);
898 operands[3] = operand_subword (operands[0], 0, 0, TImode);
899 operands[4] = operand_subword (operands[1], 1, 0, TImode);
900 operands[5] = operand_subword (operands[1], 0, 0, TImode);
904 [(set (match_operand:TI 0 "register_operand" "")
905 (match_operand:TI 1 "memory_operand" ""))]
906 "TARGET_64BIT && reload_completed
907 && !s_operand (operands[1], VOIDmode)"
908 [(set (match_dup 0) (match_dup 1))]
910 rtx addr = operand_subword (operands[0], 1, 0, TImode);
911 s390_load_address (addr, XEXP (operands[1], 0));
912 operands[1] = replace_equiv_address (operands[1], addr);
915 (define_expand "reload_outti"
916 [(parallel [(match_operand:TI 0 "" "")
917 (match_operand:TI 1 "register_operand" "d")
918 (match_operand:DI 2 "register_operand" "=&a")])]
921 gcc_assert (MEM_P (operands[0]));
922 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
923 operands[0] = replace_equiv_address (operands[0], operands[2]);
924 emit_move_insn (operands[0], operands[1]);
929 ; movdi instruction pattern(s).
932 (define_expand "movdi"
933 [(set (match_operand:DI 0 "general_operand" "")
934 (match_operand:DI 1 "general_operand" ""))]
937 /* Handle symbolic constants. */
938 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
939 emit_symbolic_move (operands);
942 (define_insn "*movdi_larl"
943 [(set (match_operand:DI 0 "register_operand" "=d")
944 (match_operand:DI 1 "larl_operand" "X"))]
946 && !FP_REG_P (operands[0])"
948 [(set_attr "op_type" "RIL")
949 (set_attr "type" "larl")])
951 (define_insn "*movdi_64extimm"
952 [(set (match_operand:DI 0 "nonimmediate_operand"
953 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
954 (match_operand:DI 1 "general_operand"
955 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
956 "TARGET_64BIT && TARGET_EXTIMM"
980 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
981 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
982 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
983 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
985 (define_insn "*movdi_64"
986 [(set (match_operand:DI 0 "nonimmediate_operand"
987 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
988 (match_operand:DI 1 "general_operand"
989 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
990 "TARGET_64BIT && !TARGET_EXTIMM"
1011 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1012 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1013 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1014 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1017 [(set (match_operand:DI 0 "register_operand" "")
1018 (match_operand:DI 1 "register_operand" ""))]
1019 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1020 [(set (match_dup 2) (match_dup 3))
1021 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1022 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1023 "operands[2] = gen_lowpart (SImode, operands[0]);
1024 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1027 [(set (match_operand:DI 0 "register_operand" "")
1028 (match_operand:DI 1 "register_operand" ""))]
1029 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1030 && dead_or_set_p (insn, operands[1])"
1031 [(set (match_dup 3) (match_dup 2))
1032 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1033 (set (match_dup 4) (match_dup 2))]
1034 "operands[2] = gen_lowpart (SImode, operands[1]);
1035 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1038 [(set (match_operand:DI 0 "register_operand" "")
1039 (match_operand:DI 1 "register_operand" ""))]
1040 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1041 && !dead_or_set_p (insn, operands[1])"
1042 [(set (match_dup 3) (match_dup 2))
1043 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1044 (set (match_dup 4) (match_dup 2))
1045 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1046 "operands[2] = gen_lowpart (SImode, operands[1]);
1047 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1049 (define_insn "*movdi_31"
1050 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1051 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1066 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1067 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1070 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1071 (match_operand:DI 1 "general_operand" ""))]
1072 "!TARGET_64BIT && reload_completed
1073 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1074 [(set (match_dup 2) (match_dup 4))
1075 (set (match_dup 3) (match_dup 5))]
1077 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1078 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1079 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1080 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1084 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1085 (match_operand:DI 1 "general_operand" ""))]
1086 "!TARGET_64BIT && reload_completed
1087 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1088 [(set (match_dup 2) (match_dup 4))
1089 (set (match_dup 3) (match_dup 5))]
1091 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1092 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1093 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1094 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1098 [(set (match_operand:DI 0 "register_operand" "")
1099 (match_operand:DI 1 "memory_operand" ""))]
1100 "!TARGET_64BIT && reload_completed
1101 && !FP_REG_P (operands[0])
1102 && !s_operand (operands[1], VOIDmode)"
1103 [(set (match_dup 0) (match_dup 1))]
1105 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1106 s390_load_address (addr, XEXP (operands[1], 0));
1107 operands[1] = replace_equiv_address (operands[1], addr);
1110 (define_expand "reload_outdi"
1111 [(parallel [(match_operand:DI 0 "" "")
1112 (match_operand:DI 1 "register_operand" "d")
1113 (match_operand:SI 2 "register_operand" "=&a")])]
1116 gcc_assert (MEM_P (operands[0]));
1117 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1118 operands[0] = replace_equiv_address (operands[0], operands[2]);
1119 emit_move_insn (operands[0], operands[1]);
1124 [(set (match_operand:DI 0 "register_operand" "")
1125 (mem:DI (match_operand 1 "address_operand" "")))]
1127 && !FP_REG_P (operands[0])
1128 && GET_CODE (operands[1]) == SYMBOL_REF
1129 && CONSTANT_POOL_ADDRESS_P (operands[1])
1130 && get_pool_mode (operands[1]) == DImode
1131 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1132 [(set (match_dup 0) (match_dup 2))]
1133 "operands[2] = get_pool_constant (operands[1]);")
1135 (define_insn "*la_64"
1136 [(set (match_operand:DI 0 "register_operand" "=d,d")
1137 (match_operand:QI 1 "address_operand" "U,W"))]
1142 [(set_attr "op_type" "RX,RXY")
1143 (set_attr "type" "la")])
1147 [(set (match_operand:DI 0 "register_operand" "")
1148 (match_operand:QI 1 "address_operand" ""))
1149 (clobber (reg:CC CC_REGNUM))])]
1151 && preferred_la_operand_p (operands[1], const0_rtx)"
1152 [(set (match_dup 0) (match_dup 1))]
1156 [(set (match_operand:DI 0 "register_operand" "")
1157 (match_operand:DI 1 "register_operand" ""))
1160 (plus:DI (match_dup 0)
1161 (match_operand:DI 2 "nonmemory_operand" "")))
1162 (clobber (reg:CC CC_REGNUM))])]
1164 && !reg_overlap_mentioned_p (operands[0], operands[2])
1165 && preferred_la_operand_p (operands[1], operands[2])"
1166 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1169 (define_expand "reload_indi"
1170 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1171 (match_operand:DI 1 "s390_plus_operand" "")
1172 (match_operand:DI 2 "register_operand" "=&a")])]
1175 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1180 ; movsi instruction pattern(s).
1183 (define_expand "movsi"
1184 [(set (match_operand:SI 0 "general_operand" "")
1185 (match_operand:SI 1 "general_operand" ""))]
1188 /* Handle symbolic constants. */
1189 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1190 emit_symbolic_move (operands);
1193 (define_insn "*movsi_larl"
1194 [(set (match_operand:SI 0 "register_operand" "=d")
1195 (match_operand:SI 1 "larl_operand" "X"))]
1196 "!TARGET_64BIT && TARGET_CPU_ZARCH
1197 && !FP_REG_P (operands[0])"
1199 [(set_attr "op_type" "RIL")
1200 (set_attr "type" "larl")])
1202 (define_insn "*movsi_zarch"
1203 [(set (match_operand:SI 0 "nonimmediate_operand"
1204 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1205 (match_operand:SI 1 "general_operand"
1206 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1229 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1230 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1231 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1232 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1234 (define_insn "*movsi_esa"
1235 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1236 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1251 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1252 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1255 [(set (match_operand:SI 0 "register_operand" "")
1256 (mem:SI (match_operand 1 "address_operand" "")))]
1257 "!FP_REG_P (operands[0])
1258 && GET_CODE (operands[1]) == SYMBOL_REF
1259 && CONSTANT_POOL_ADDRESS_P (operands[1])
1260 && get_pool_mode (operands[1]) == SImode
1261 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1262 [(set (match_dup 0) (match_dup 2))]
1263 "operands[2] = get_pool_constant (operands[1]);")
1265 (define_insn "*la_31"
1266 [(set (match_operand:SI 0 "register_operand" "=d,d")
1267 (match_operand:QI 1 "address_operand" "U,W"))]
1268 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1272 [(set_attr "op_type" "RX,RXY")
1273 (set_attr "type" "la")])
1277 [(set (match_operand:SI 0 "register_operand" "")
1278 (match_operand:QI 1 "address_operand" ""))
1279 (clobber (reg:CC CC_REGNUM))])]
1281 && preferred_la_operand_p (operands[1], const0_rtx)"
1282 [(set (match_dup 0) (match_dup 1))]
1286 [(set (match_operand:SI 0 "register_operand" "")
1287 (match_operand:SI 1 "register_operand" ""))
1290 (plus:SI (match_dup 0)
1291 (match_operand:SI 2 "nonmemory_operand" "")))
1292 (clobber (reg:CC CC_REGNUM))])]
1294 && !reg_overlap_mentioned_p (operands[0], operands[2])
1295 && preferred_la_operand_p (operands[1], operands[2])"
1296 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1299 (define_insn "*la_31_and"
1300 [(set (match_operand:SI 0 "register_operand" "=d,d")
1301 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1302 (const_int 2147483647)))]
1307 [(set_attr "op_type" "RX,RXY")
1308 (set_attr "type" "la")])
1310 (define_insn_and_split "*la_31_and_cc"
1311 [(set (match_operand:SI 0 "register_operand" "=d")
1312 (and:SI (match_operand:QI 1 "address_operand" "p")
1313 (const_int 2147483647)))
1314 (clobber (reg:CC CC_REGNUM))]
1317 "&& reload_completed"
1319 (and:SI (match_dup 1) (const_int 2147483647)))]
1321 [(set_attr "op_type" "RX")
1322 (set_attr "type" "la")])
1324 (define_insn "force_la_31"
1325 [(set (match_operand:SI 0 "register_operand" "=d,d")
1326 (match_operand:QI 1 "address_operand" "U,W"))
1327 (use (const_int 0))]
1332 [(set_attr "op_type" "RX")
1333 (set_attr "type" "la")])
1335 (define_expand "reload_insi"
1336 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1337 (match_operand:SI 1 "s390_plus_operand" "")
1338 (match_operand:SI 2 "register_operand" "=&a")])]
1341 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1346 ; movhi instruction pattern(s).
1349 (define_expand "movhi"
1350 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1351 (match_operand:HI 1 "general_operand" ""))]
1354 /* Make it explicit that loading a register from memory
1355 always sign-extends (at least) to SImode. */
1356 if (optimize && !no_new_pseudos
1357 && register_operand (operands[0], VOIDmode)
1358 && GET_CODE (operands[1]) == MEM)
1360 rtx tmp = gen_reg_rtx (SImode);
1361 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1362 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1363 operands[1] = gen_lowpart (HImode, tmp);
1367 (define_insn "*movhi"
1368 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1369 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1379 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1380 (set_attr "type" "lr,*,*,*,store,store,*")])
1383 [(set (match_operand:HI 0 "register_operand" "")
1384 (mem:HI (match_operand 1 "address_operand" "")))]
1385 "GET_CODE (operands[1]) == SYMBOL_REF
1386 && CONSTANT_POOL_ADDRESS_P (operands[1])
1387 && get_pool_mode (operands[1]) == HImode
1388 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1389 [(set (match_dup 0) (match_dup 2))]
1390 "operands[2] = get_pool_constant (operands[1]);")
1393 ; movqi instruction pattern(s).
1396 (define_expand "movqi"
1397 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1398 (match_operand:QI 1 "general_operand" ""))]
1401 /* On z/Architecture, zero-extending from memory to register
1402 is just as fast as a QImode load. */
1403 if (TARGET_ZARCH && optimize && !no_new_pseudos
1404 && register_operand (operands[0], VOIDmode)
1405 && GET_CODE (operands[1]) == MEM)
1407 rtx tmp = gen_reg_rtx (word_mode);
1408 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1409 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1410 operands[1] = gen_lowpart (QImode, tmp);
1414 (define_insn "*movqi"
1415 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1416 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1428 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1429 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1432 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1433 (mem:QI (match_operand 1 "address_operand" "")))]
1434 "GET_CODE (operands[1]) == SYMBOL_REF
1435 && CONSTANT_POOL_ADDRESS_P (operands[1])
1436 && get_pool_mode (operands[1]) == QImode
1437 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1438 [(set (match_dup 0) (match_dup 2))]
1439 "operands[2] = get_pool_constant (operands[1]);")
1442 ; movstrictqi instruction pattern(s).
1445 (define_insn "*movstrictqi"
1446 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1447 (match_operand:QI 1 "memory_operand" "R,T"))]
1452 [(set_attr "op_type" "RX,RXY")])
1455 ; movstricthi instruction pattern(s).
1458 (define_insn "*movstricthi"
1459 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1460 (match_operand:HI 1 "memory_operand" "Q,S"))
1461 (clobber (reg:CC CC_REGNUM))]
1466 [(set_attr "op_type" "RS,RSY")])
1469 ; movstrictsi instruction pattern(s).
1472 (define_insn "movstrictsi"
1473 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1474 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1481 [(set_attr "op_type" "RR,RX,RXY,RRE")
1482 (set_attr "type" "lr,load,load,*")])
1485 ; movdf instruction pattern(s).
1488 (define_expand "movdf"
1489 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1490 (match_operand:DF 1 "general_operand" ""))]
1494 (define_insn "*movdf_64"
1495 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1496 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1509 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1510 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1512 (define_insn "*movdf_31"
1513 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1514 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1530 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1531 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1532 lm,lm,stm,stm,*,*,*")])
1535 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1536 (match_operand:DF 1 "general_operand" ""))]
1537 "!TARGET_64BIT && reload_completed
1538 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1539 [(set (match_dup 2) (match_dup 4))
1540 (set (match_dup 3) (match_dup 5))]
1542 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1543 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1544 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1545 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1549 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1550 (match_operand:DF 1 "general_operand" ""))]
1551 "!TARGET_64BIT && reload_completed
1552 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1553 [(set (match_dup 2) (match_dup 4))
1554 (set (match_dup 3) (match_dup 5))]
1556 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1557 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1558 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1559 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1563 [(set (match_operand:DF 0 "register_operand" "")
1564 (match_operand:DF 1 "memory_operand" ""))]
1565 "!TARGET_64BIT && reload_completed
1566 && !FP_REG_P (operands[0])
1567 && !s_operand (operands[1], VOIDmode)"
1568 [(set (match_dup 0) (match_dup 1))]
1570 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1571 s390_load_address (addr, XEXP (operands[1], 0));
1572 operands[1] = replace_equiv_address (operands[1], addr);
1575 (define_expand "reload_outdf"
1576 [(parallel [(match_operand:DF 0 "" "")
1577 (match_operand:DF 1 "register_operand" "d")
1578 (match_operand:SI 2 "register_operand" "=&a")])]
1581 gcc_assert (MEM_P (operands[0]));
1582 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1583 operands[0] = replace_equiv_address (operands[0], operands[2]);
1584 emit_move_insn (operands[0], operands[1]);
1589 ; movsf instruction pattern(s).
1592 (define_insn "movsf"
1593 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1594 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1609 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1610 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1611 lr,load,load,store,store,*")])
1614 ; movcc instruction pattern
1617 (define_insn "movcc"
1618 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1619 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1629 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1630 (set_attr "type" "lr,*,*,store,store,load,load")])
1633 ; Block move (MVC) patterns.
1637 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1638 (match_operand:BLK 1 "memory_operand" "Q"))
1639 (use (match_operand 2 "const_int_operand" "n"))]
1640 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1641 "mvc\t%O0(%2,%R0),%S1"
1642 [(set_attr "op_type" "SS")])
1645 [(set (match_operand 0 "memory_operand" "")
1646 (match_operand 1 "memory_operand" ""))]
1648 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1649 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1651 [(set (match_dup 0) (match_dup 1))
1652 (use (match_dup 2))])]
1654 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1655 operands[0] = adjust_address (operands[0], BLKmode, 0);
1656 operands[1] = adjust_address (operands[1], BLKmode, 0);
1661 [(set (match_operand:BLK 0 "memory_operand" "")
1662 (match_operand:BLK 1 "memory_operand" ""))
1663 (use (match_operand 2 "const_int_operand" ""))])
1665 [(set (match_operand:BLK 3 "memory_operand" "")
1666 (match_operand:BLK 4 "memory_operand" ""))
1667 (use (match_operand 5 "const_int_operand" ""))])]
1668 "s390_offset_p (operands[0], operands[3], operands[2])
1669 && s390_offset_p (operands[1], operands[4], operands[2])
1670 && !s390_overlap_p (operands[0], operands[1],
1671 INTVAL (operands[2]) + INTVAL (operands[5]))
1672 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1674 [(set (match_dup 6) (match_dup 7))
1675 (use (match_dup 8))])]
1676 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1677 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1678 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1682 ; load_multiple pattern(s).
1684 ; ??? Due to reload problems with replacing registers inside match_parallel
1685 ; we currently support load_multiple/store_multiple only after reload.
1688 (define_expand "load_multiple"
1689 [(match_par_dup 3 [(set (match_operand 0 "" "")
1690 (match_operand 1 "" ""))
1691 (use (match_operand 2 "" ""))])]
1694 enum machine_mode mode;
1700 /* Support only loading a constant number of fixed-point registers from
1701 memory and only bother with this if more than two */
1702 if (GET_CODE (operands[2]) != CONST_INT
1703 || INTVAL (operands[2]) < 2
1704 || INTVAL (operands[2]) > 16
1705 || GET_CODE (operands[1]) != MEM
1706 || GET_CODE (operands[0]) != REG
1707 || REGNO (operands[0]) >= 16)
1710 count = INTVAL (operands[2]);
1711 regno = REGNO (operands[0]);
1712 mode = GET_MODE (operands[0]);
1713 if (mode != SImode && mode != word_mode)
1716 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1719 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1721 from = XEXP (operands[1], 0);
1724 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1725 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1726 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1728 from = XEXP (XEXP (operands[1], 0), 0);
1729 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1736 from = force_reg (Pmode, XEXP (operands[1], 0));
1740 for (i = 0; i < count; i++)
1741 XVECEXP (operands[3], 0, i)
1742 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1743 change_address (operands[1], mode,
1744 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1747 (define_insn "*load_multiple_di"
1748 [(match_parallel 0 "load_multiple_operation"
1749 [(set (match_operand:DI 1 "register_operand" "=r")
1750 (match_operand:DI 2 "s_operand" "QS"))])]
1751 "reload_completed && word_mode == DImode"
1753 int words = XVECLEN (operands[0], 0);
1754 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1755 return "lmg\t%1,%0,%S2";
1757 [(set_attr "op_type" "RSY")
1758 (set_attr "type" "lm")])
1760 (define_insn "*load_multiple_si"
1761 [(match_parallel 0 "load_multiple_operation"
1762 [(set (match_operand:SI 1 "register_operand" "=r,r")
1763 (match_operand:SI 2 "s_operand" "Q,S"))])]
1766 int words = XVECLEN (operands[0], 0);
1767 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1768 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1770 [(set_attr "op_type" "RS,RSY")
1771 (set_attr "type" "lm")])
1774 ; store multiple pattern(s).
1777 (define_expand "store_multiple"
1778 [(match_par_dup 3 [(set (match_operand 0 "" "")
1779 (match_operand 1 "" ""))
1780 (use (match_operand 2 "" ""))])]
1783 enum machine_mode mode;
1789 /* Support only storing a constant number of fixed-point registers to
1790 memory and only bother with this if more than two. */
1791 if (GET_CODE (operands[2]) != CONST_INT
1792 || INTVAL (operands[2]) < 2
1793 || INTVAL (operands[2]) > 16
1794 || GET_CODE (operands[0]) != MEM
1795 || GET_CODE (operands[1]) != REG
1796 || REGNO (operands[1]) >= 16)
1799 count = INTVAL (operands[2]);
1800 regno = REGNO (operands[1]);
1801 mode = GET_MODE (operands[1]);
1802 if (mode != SImode && mode != word_mode)
1805 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1809 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1811 to = XEXP (operands[0], 0);
1814 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1815 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1816 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1818 to = XEXP (XEXP (operands[0], 0), 0);
1819 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1826 to = force_reg (Pmode, XEXP (operands[0], 0));
1830 for (i = 0; i < count; i++)
1831 XVECEXP (operands[3], 0, i)
1832 = gen_rtx_SET (VOIDmode,
1833 change_address (operands[0], mode,
1834 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1835 gen_rtx_REG (mode, regno + i));
1838 (define_insn "*store_multiple_di"
1839 [(match_parallel 0 "store_multiple_operation"
1840 [(set (match_operand:DI 1 "s_operand" "=QS")
1841 (match_operand:DI 2 "register_operand" "r"))])]
1842 "reload_completed && word_mode == DImode"
1844 int words = XVECLEN (operands[0], 0);
1845 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1846 return "stmg\t%2,%0,%S1";
1848 [(set_attr "op_type" "RSY")
1849 (set_attr "type" "stm")])
1852 (define_insn "*store_multiple_si"
1853 [(match_parallel 0 "store_multiple_operation"
1854 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1855 (match_operand:SI 2 "register_operand" "r,r"))])]
1858 int words = XVECLEN (operands[0], 0);
1859 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1860 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1862 [(set_attr "op_type" "RS,RSY")
1863 (set_attr "type" "stm")])
1866 ;; String instructions.
1869 (define_insn "*execute"
1870 [(match_parallel 0 ""
1871 [(unspec [(match_operand 1 "register_operand" "a")
1872 (match_operand:BLK 2 "memory_operand" "R")
1873 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1874 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1875 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1877 [(set_attr "op_type" "RX")
1878 (set_attr "type" "cs")])
1882 ; strlenM instruction pattern(s).
1885 (define_expand "strlen<mode>"
1886 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1889 (unspec:P [(const_int 0)
1890 (match_operand:BLK 1 "memory_operand" "")
1892 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1893 (clobber (scratch:P))
1894 (clobber (reg:CC CC_REGNUM))])
1896 [(set (match_operand:P 0 "register_operand" "")
1897 (minus:P (match_dup 4) (match_dup 5)))
1898 (clobber (reg:CC CC_REGNUM))])]
1901 operands[4] = gen_reg_rtx (Pmode);
1902 operands[5] = gen_reg_rtx (Pmode);
1903 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1904 operands[1] = replace_equiv_address (operands[1], operands[5]);
1907 (define_insn "*strlen<mode>"
1908 [(set (match_operand:P 0 "register_operand" "=a")
1909 (unspec:P [(match_operand:P 2 "general_operand" "0")
1910 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1912 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1913 (clobber (match_scratch:P 1 "=a"))
1914 (clobber (reg:CC CC_REGNUM))]
1916 "srst\t%0,%1\;jo\t.-4"
1917 [(set_attr "length" "8")
1918 (set_attr "type" "vs")])
1921 ; cmpstrM instruction pattern(s).
1924 (define_expand "cmpstrsi"
1925 [(set (reg:SI 0) (const_int 0))
1927 [(clobber (match_operand 3 "" ""))
1928 (clobber (match_dup 4))
1929 (set (reg:CCU CC_REGNUM)
1930 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1931 (match_operand:BLK 2 "memory_operand" "")))
1934 [(set (match_operand:SI 0 "register_operand" "=d")
1935 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1936 (clobber (reg:CC CC_REGNUM))])]
1939 /* As the result of CMPINT is inverted compared to what we need,
1940 we have to swap the operands. */
1941 rtx op1 = operands[2];
1942 rtx op2 = operands[1];
1943 rtx addr1 = gen_reg_rtx (Pmode);
1944 rtx addr2 = gen_reg_rtx (Pmode);
1946 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1947 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1948 operands[1] = replace_equiv_address_nv (op1, addr1);
1949 operands[2] = replace_equiv_address_nv (op2, addr2);
1950 operands[3] = addr1;
1951 operands[4] = addr2;
1954 (define_insn "*cmpstr<mode>"
1955 [(clobber (match_operand:P 0 "register_operand" "=d"))
1956 (clobber (match_operand:P 1 "register_operand" "=d"))
1957 (set (reg:CCU CC_REGNUM)
1958 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1959 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1962 "clst\t%0,%1\;jo\t.-4"
1963 [(set_attr "length" "8")
1964 (set_attr "type" "vs")])
1967 ; movstr instruction pattern.
1970 (define_expand "movstr"
1971 [(set (reg:SI 0) (const_int 0))
1973 [(clobber (match_dup 3))
1974 (set (match_operand:BLK 1 "memory_operand" "")
1975 (match_operand:BLK 2 "memory_operand" ""))
1976 (set (match_operand 0 "register_operand" "")
1977 (unspec [(match_dup 1)
1979 (reg:SI 0)] UNSPEC_MVST))
1980 (clobber (reg:CC CC_REGNUM))])]
1983 rtx addr1 = gen_reg_rtx (Pmode);
1984 rtx addr2 = gen_reg_rtx (Pmode);
1986 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1987 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1988 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1989 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1990 operands[3] = addr2;
1993 (define_insn "*movstr"
1994 [(clobber (match_operand:P 2 "register_operand" "=d"))
1995 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1996 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1997 (set (match_operand:P 0 "register_operand" "=d")
1998 (unspec [(mem:BLK (match_dup 1))
1999 (mem:BLK (match_dup 3))
2000 (reg:SI 0)] UNSPEC_MVST))
2001 (clobber (reg:CC CC_REGNUM))]
2003 "mvst\t%1,%2\;jo\t.-4"
2004 [(set_attr "length" "8")
2005 (set_attr "type" "vs")])
2009 ; movmemM instruction pattern(s).
2012 (define_expand "movmem<mode>"
2013 [(set (match_operand:BLK 0 "memory_operand" "")
2014 (match_operand:BLK 1 "memory_operand" ""))
2015 (use (match_operand:GPR 2 "general_operand" ""))
2016 (match_operand 3 "" "")]
2018 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2020 ; Move a block that is up to 256 bytes in length.
2021 ; The block length is taken as (operands[2] % 256) + 1.
2023 (define_expand "movmem_short"
2025 [(set (match_operand:BLK 0 "memory_operand" "")
2026 (match_operand:BLK 1 "memory_operand" ""))
2027 (use (match_operand 2 "nonmemory_operand" ""))
2028 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2029 (clobber (match_dup 3))])]
2031 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2033 (define_insn "*movmem_short"
2034 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2035 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2036 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2037 (use (match_operand 3 "immediate_operand" "X,R,X"))
2038 (clobber (match_scratch 4 "=X,X,&a"))]
2039 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2040 && GET_MODE (operands[4]) == Pmode"
2042 [(set_attr "type" "cs")])
2045 [(set (match_operand:BLK 0 "memory_operand" "")
2046 (match_operand:BLK 1 "memory_operand" ""))
2047 (use (match_operand 2 "const_int_operand" ""))
2048 (use (match_operand 3 "immediate_operand" ""))
2049 (clobber (scratch))]
2052 [(set (match_dup 0) (match_dup 1))
2053 (use (match_dup 2))])]
2054 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2057 [(set (match_operand:BLK 0 "memory_operand" "")
2058 (match_operand:BLK 1 "memory_operand" ""))
2059 (use (match_operand 2 "register_operand" ""))
2060 (use (match_operand 3 "memory_operand" ""))
2061 (clobber (scratch))]
2064 [(unspec [(match_dup 2) (match_dup 3)
2065 (const_int 0)] UNSPEC_EXECUTE)
2066 (set (match_dup 0) (match_dup 1))
2067 (use (const_int 1))])]
2071 [(set (match_operand:BLK 0 "memory_operand" "")
2072 (match_operand:BLK 1 "memory_operand" ""))
2073 (use (match_operand 2 "register_operand" ""))
2074 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2075 (clobber (match_operand 3 "register_operand" ""))]
2076 "reload_completed && TARGET_CPU_ZARCH"
2077 [(set (match_dup 3) (label_ref (match_dup 4)))
2079 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2080 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2081 (set (match_dup 0) (match_dup 1))
2082 (use (const_int 1))])]
2083 "operands[4] = gen_label_rtx ();")
2085 ; Move a block of arbitrary length.
2087 (define_expand "movmem_long"
2089 [(clobber (match_dup 2))
2090 (clobber (match_dup 3))
2091 (set (match_operand:BLK 0 "memory_operand" "")
2092 (match_operand:BLK 1 "memory_operand" ""))
2093 (use (match_operand 2 "general_operand" ""))
2095 (clobber (reg:CC CC_REGNUM))])]
2098 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2099 rtx reg0 = gen_reg_rtx (dword_mode);
2100 rtx reg1 = gen_reg_rtx (dword_mode);
2101 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2102 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2103 rtx len0 = gen_lowpart (Pmode, reg0);
2104 rtx len1 = gen_lowpart (Pmode, reg1);
2106 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2107 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2108 emit_move_insn (len0, operands[2]);
2110 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2111 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2112 emit_move_insn (len1, operands[2]);
2114 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2115 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2120 (define_insn "*movmem_long"
2121 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2122 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2123 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2124 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2127 (clobber (reg:CC CC_REGNUM))]
2129 "mvcle\t%0,%1,0\;jo\t.-4"
2130 [(set_attr "length" "8")
2131 (set_attr "type" "vs")])
2134 ; setmemM instruction pattern(s).
2137 (define_expand "setmem<mode>"
2138 [(set (match_operand:BLK 0 "memory_operand" "")
2139 (match_operand:QI 2 "general_operand" ""))
2140 (use (match_operand:GPR 1 "general_operand" ""))
2141 (match_operand 3 "" "")]
2143 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2145 ; Clear a block that is up to 256 bytes in length.
2146 ; The block length is taken as (operands[1] % 256) + 1.
2148 (define_expand "clrmem_short"
2150 [(set (match_operand:BLK 0 "memory_operand" "")
2152 (use (match_operand 1 "nonmemory_operand" ""))
2153 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2154 (clobber (match_dup 2))
2155 (clobber (reg:CC CC_REGNUM))])]
2157 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2159 (define_insn "*clrmem_short"
2160 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2162 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2163 (use (match_operand 2 "immediate_operand" "X,R,X"))
2164 (clobber (match_scratch 3 "=X,X,&a"))
2165 (clobber (reg:CC CC_REGNUM))]
2166 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2167 && GET_MODE (operands[3]) == Pmode"
2169 [(set_attr "type" "cs")])
2172 [(set (match_operand:BLK 0 "memory_operand" "")
2174 (use (match_operand 1 "const_int_operand" ""))
2175 (use (match_operand 2 "immediate_operand" ""))
2177 (clobber (reg:CC CC_REGNUM))]
2180 [(set (match_dup 0) (const_int 0))
2182 (clobber (reg:CC CC_REGNUM))])]
2183 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2186 [(set (match_operand:BLK 0 "memory_operand" "")
2188 (use (match_operand 1 "register_operand" ""))
2189 (use (match_operand 2 "memory_operand" ""))
2191 (clobber (reg:CC CC_REGNUM))]
2194 [(unspec [(match_dup 1) (match_dup 2)
2195 (const_int 0)] UNSPEC_EXECUTE)
2196 (set (match_dup 0) (const_int 0))
2198 (clobber (reg:CC CC_REGNUM))])]
2202 [(set (match_operand:BLK 0 "memory_operand" "")
2204 (use (match_operand 1 "register_operand" ""))
2205 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2206 (clobber (match_operand 2 "register_operand" ""))
2207 (clobber (reg:CC CC_REGNUM))]
2208 "reload_completed && TARGET_CPU_ZARCH"
2209 [(set (match_dup 2) (label_ref (match_dup 3)))
2211 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2212 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2213 (set (match_dup 0) (const_int 0))
2215 (clobber (reg:CC CC_REGNUM))])]
2216 "operands[3] = gen_label_rtx ();")
2218 ; Initialize a block of arbitrary length with (operands[2] % 256).
2220 (define_expand "setmem_long"
2222 [(clobber (match_dup 1))
2223 (set (match_operand:BLK 0 "memory_operand" "")
2224 (match_operand 2 "setmem_operand" ""))
2225 (use (match_operand 1 "general_operand" ""))
2227 (clobber (reg:CC CC_REGNUM))])]
2230 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2231 rtx reg0 = gen_reg_rtx (dword_mode);
2232 rtx reg1 = gen_reg_rtx (dword_mode);
2233 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2234 rtx len0 = gen_lowpart (Pmode, reg0);
2236 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2237 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2238 emit_move_insn (len0, operands[1]);
2240 emit_move_insn (reg1, const0_rtx);
2242 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2247 (define_insn "*setmem_long"
2248 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2249 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2250 (match_operand 2 "setmem_operand" "Y"))
2252 (use (match_operand:<DBL> 1 "register_operand" "d"))
2253 (clobber (reg:CC CC_REGNUM))]
2255 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2256 [(set_attr "length" "8")
2257 (set_attr "type" "vs")])
2260 ; cmpmemM instruction pattern(s).
2263 (define_expand "cmpmemsi"
2264 [(set (match_operand:SI 0 "register_operand" "")
2265 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2266 (match_operand:BLK 2 "memory_operand" "") ) )
2267 (use (match_operand:SI 3 "general_operand" ""))
2268 (use (match_operand:SI 4 "" ""))]
2270 "s390_expand_cmpmem (operands[0], operands[1],
2271 operands[2], operands[3]); DONE;")
2273 ; Compare a block that is up to 256 bytes in length.
2274 ; The block length is taken as (operands[2] % 256) + 1.
2276 (define_expand "cmpmem_short"
2278 [(set (reg:CCU CC_REGNUM)
2279 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2280 (match_operand:BLK 1 "memory_operand" "")))
2281 (use (match_operand 2 "nonmemory_operand" ""))
2282 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2283 (clobber (match_dup 3))])]
2285 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2287 (define_insn "*cmpmem_short"
2288 [(set (reg:CCU CC_REGNUM)
2289 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2290 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2291 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2292 (use (match_operand 3 "immediate_operand" "X,R,X"))
2293 (clobber (match_scratch 4 "=X,X,&a"))]
2294 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2295 && GET_MODE (operands[4]) == Pmode"
2297 [(set_attr "type" "cs")])
2300 [(set (reg:CCU CC_REGNUM)
2301 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2302 (match_operand:BLK 1 "memory_operand" "")))
2303 (use (match_operand 2 "const_int_operand" ""))
2304 (use (match_operand 3 "immediate_operand" ""))
2305 (clobber (scratch))]
2308 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2309 (use (match_dup 2))])]
2310 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2313 [(set (reg:CCU CC_REGNUM)
2314 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2315 (match_operand:BLK 1 "memory_operand" "")))
2316 (use (match_operand 2 "register_operand" ""))
2317 (use (match_operand 3 "memory_operand" ""))
2318 (clobber (scratch))]
2321 [(unspec [(match_dup 2) (match_dup 3)
2322 (const_int 0)] UNSPEC_EXECUTE)
2323 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2324 (use (const_int 1))])]
2328 [(set (reg:CCU CC_REGNUM)
2329 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2330 (match_operand:BLK 1 "memory_operand" "")))
2331 (use (match_operand 2 "register_operand" ""))
2332 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2333 (clobber (match_operand 3 "register_operand" ""))]
2334 "reload_completed && TARGET_CPU_ZARCH"
2335 [(set (match_dup 3) (label_ref (match_dup 4)))
2337 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2338 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2339 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2340 (use (const_int 1))])]
2341 "operands[4] = gen_label_rtx ();")
2343 ; Compare a block of arbitrary length.
2345 (define_expand "cmpmem_long"
2347 [(clobber (match_dup 2))
2348 (clobber (match_dup 3))
2349 (set (reg:CCU CC_REGNUM)
2350 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2351 (match_operand:BLK 1 "memory_operand" "")))
2352 (use (match_operand 2 "general_operand" ""))
2353 (use (match_dup 3))])]
2356 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2357 rtx reg0 = gen_reg_rtx (dword_mode);
2358 rtx reg1 = gen_reg_rtx (dword_mode);
2359 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2360 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2361 rtx len0 = gen_lowpart (Pmode, reg0);
2362 rtx len1 = gen_lowpart (Pmode, reg1);
2364 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2365 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2366 emit_move_insn (len0, operands[2]);
2368 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2369 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2370 emit_move_insn (len1, operands[2]);
2372 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2373 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2378 (define_insn "*cmpmem_long"
2379 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2380 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2381 (set (reg:CCU CC_REGNUM)
2382 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2383 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2385 (use (match_dup 3))]
2387 "clcle\t%0,%1,0\;jo\t.-4"
2388 [(set_attr "length" "8")
2389 (set_attr "type" "vs")])
2391 ; Convert CCUmode condition code to integer.
2392 ; Result is zero if EQ, positive if LTU, negative if GTU.
2394 (define_insn_and_split "cmpint"
2395 [(set (match_operand:SI 0 "register_operand" "=d")
2396 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2398 (clobber (reg:CC CC_REGNUM))]
2402 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2404 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2405 (clobber (reg:CC CC_REGNUM))])])
2407 (define_insn_and_split "*cmpint_cc"
2408 [(set (reg CC_REGNUM)
2409 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2412 (set (match_operand:SI 0 "register_operand" "=d")
2413 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2414 "s390_match_ccmode (insn, CCSmode)"
2416 "&& reload_completed"
2417 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2419 [(set (match_dup 2) (match_dup 3))
2420 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2422 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2423 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2424 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2427 (define_insn_and_split "*cmpint_sign"
2428 [(set (match_operand:DI 0 "register_operand" "=d")
2429 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2431 (clobber (reg:CC CC_REGNUM))]
2434 "&& reload_completed"
2435 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2437 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2438 (clobber (reg:CC CC_REGNUM))])])
2440 (define_insn_and_split "*cmpint_sign_cc"
2441 [(set (reg CC_REGNUM)
2442 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2443 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2445 (const_int 32)) (const_int 32))
2447 (set (match_operand:DI 0 "register_operand" "=d")
2448 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2449 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2451 "&& reload_completed"
2452 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2454 [(set (match_dup 2) (match_dup 3))
2455 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2457 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2458 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2459 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2464 ;;- Conversion instructions.
2468 (define_insn "*sethigh<mode>si"
2469 [(set (match_operand:SI 0 "register_operand" "=d,d")
2470 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2471 (clobber (reg:CC CC_REGNUM))]
2474 icm\t%0,<icm_hi>,%S1
2475 icmy\t%0,<icm_hi>,%S1"
2476 [(set_attr "op_type" "RS,RSY")])
2478 (define_insn "*sethighqidi_64"
2479 [(set (match_operand:DI 0 "register_operand" "=d")
2480 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2481 (clobber (reg:CC CC_REGNUM))]
2484 [(set_attr "op_type" "RSY")])
2486 (define_insn "*sethighqidi_31"
2487 [(set (match_operand:DI 0 "register_operand" "=d,d")
2488 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2489 (clobber (reg:CC CC_REGNUM))]
2494 [(set_attr "op_type" "RS,RSY")])
2496 (define_insn_and_split "*extractqi"
2497 [(set (match_operand:SI 0 "register_operand" "=d")
2498 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2499 (match_operand 2 "const_int_operand" "n")
2501 (clobber (reg:CC CC_REGNUM))]
2503 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2505 "&& reload_completed"
2507 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2508 (clobber (reg:CC CC_REGNUM))])
2509 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2511 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2512 operands[1] = change_address (operands[1], QImode, 0);
2515 (define_insn_and_split "*extracthi"
2516 [(set (match_operand:SI 0 "register_operand" "=d")
2517 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2518 (match_operand 2 "const_int_operand" "n")
2520 (clobber (reg:CC CC_REGNUM))]
2522 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2524 "&& reload_completed"
2526 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2527 (clobber (reg:CC CC_REGNUM))])
2528 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2530 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2531 operands[1] = change_address (operands[1], HImode, 0);
2535 ; extendsidi2 instruction pattern(s).
2538 (define_expand "extendsidi2"
2539 [(set (match_operand:DI 0 "register_operand" "")
2540 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2545 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2546 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2547 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2548 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2553 (define_insn "*extendsidi2"
2554 [(set (match_operand:DI 0 "register_operand" "=d,d")
2555 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2560 [(set_attr "op_type" "RRE,RXY")])
2563 ; extend(hi|qi)di2 instruction pattern(s).
2566 (define_expand "extend<mode>di2"
2567 [(set (match_operand:DI 0 "register_operand" "")
2568 (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2573 rtx tmp = gen_reg_rtx (SImode);
2574 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2575 emit_insn (gen_extendsidi2 (operands[0], tmp));
2578 else if (!TARGET_EXTIMM)
2580 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2581 GET_MODE_BITSIZE (<MODE>mode));
2582 operands[1] = gen_lowpart (DImode, operands[1]);
2583 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2584 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2589 (define_insn "*extendhidi2_extimm"
2590 [(set (match_operand:DI 0 "register_operand" "=d,d")
2591 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2592 "TARGET_64BIT && TARGET_EXTIMM"
2596 [(set_attr "op_type" "RRE,RXY")])
2598 (define_insn "*extendhidi2"
2599 [(set (match_operand:DI 0 "register_operand" "=d")
2600 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2603 [(set_attr "op_type" "RXY")])
2605 (define_insn "*extendqidi2_extimm"
2606 [(set (match_operand:DI 0 "register_operand" "=d,d")
2607 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2608 "TARGET_64BIT && TARGET_EXTIMM"
2612 [(set_attr "op_type" "RRE,RXY")])
2614 (define_insn "*extendqidi2"
2615 [(set (match_operand:DI 0 "register_operand" "=d")
2616 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2617 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2619 [(set_attr "op_type" "RXY")])
2621 (define_insn_and_split "*extendqidi2_short_displ"
2622 [(set (match_operand:DI 0 "register_operand" "=d")
2623 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2624 (clobber (reg:CC CC_REGNUM))]
2625 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2627 "&& reload_completed"
2629 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2630 (clobber (reg:CC CC_REGNUM))])
2632 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2633 (clobber (reg:CC CC_REGNUM))])]
2637 ; extend(hi|qi)si2 instruction pattern(s).
2640 (define_expand "extend<mode>si2"
2641 [(set (match_operand:SI 0 "register_operand" "")
2642 (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2647 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2648 GET_MODE_BITSIZE(<MODE>mode));
2649 operands[1] = gen_lowpart (SImode, operands[1]);
2650 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2651 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2656 (define_insn "*extendhisi2_extimm"
2657 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2658 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2664 [(set_attr "op_type" "RRE,RX,RXY")])
2666 (define_insn "*extendhisi2"
2667 [(set (match_operand:SI 0 "register_operand" "=d,d")
2668 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2673 [(set_attr "op_type" "RX,RXY")])
2675 (define_insn "*extendqisi2_extimm"
2676 [(set (match_operand:SI 0 "register_operand" "=d,d")
2677 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2682 [(set_attr "op_type" "RRE,RXY")])
2684 (define_insn "*extendqisi2"
2685 [(set (match_operand:SI 0 "register_operand" "=d")
2686 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2687 "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2689 [(set_attr "op_type" "RXY")])
2691 (define_insn_and_split "*extendqisi2_short_displ"
2692 [(set (match_operand:SI 0 "register_operand" "=d")
2693 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2694 (clobber (reg:CC CC_REGNUM))]
2695 "!TARGET_LONG_DISPLACEMENT"
2697 "&& reload_completed"
2699 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2700 (clobber (reg:CC CC_REGNUM))])
2702 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2703 (clobber (reg:CC CC_REGNUM))])]
2707 ; extendqihi2 instruction pattern(s).
2712 ; zero_extendsidi2 instruction pattern(s).
2715 (define_expand "zero_extendsidi2"
2716 [(set (match_operand:DI 0 "register_operand" "")
2717 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2722 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2723 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2724 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2729 (define_insn "*zero_extendsidi2"
2730 [(set (match_operand:DI 0 "register_operand" "=d,d")
2731 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2736 [(set_attr "op_type" "RRE,RXY")])
2739 ; zero_extend(hi|qi)di2 instruction pattern(s).
2742 (define_expand "zero_extend<mode>di2"
2743 [(set (match_operand:DI 0 "register_operand" "")
2744 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2749 rtx tmp = gen_reg_rtx (SImode);
2750 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2751 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2754 else if (!TARGET_EXTIMM)
2756 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2757 GET_MODE_BITSIZE(<MODE>mode));
2758 operands[1] = gen_lowpart (DImode, operands[1]);
2759 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2760 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2765 (define_insn "*zero_extend<mode>di2_extimm"
2766 [(set (match_operand:DI 0 "register_operand" "=d,d")
2767 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2768 "TARGET_64BIT && TARGET_EXTIMM"
2772 [(set_attr "op_type" "RRE,RXY")])
2774 (define_insn "*zero_extend<mode>di2"
2775 [(set (match_operand:DI 0 "register_operand" "=d")
2776 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2777 "TARGET_64BIT && !TARGET_EXTIMM"
2779 [(set_attr "op_type" "RXY")])
2782 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2785 (define_insn "*llgt_sidi"
2786 [(set (match_operand:DI 0 "register_operand" "=d")
2787 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2788 (const_int 2147483647)))]
2791 [(set_attr "op_type" "RXE")])
2793 (define_insn_and_split "*llgt_sidi_split"
2794 [(set (match_operand:DI 0 "register_operand" "=d")
2795 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2796 (const_int 2147483647)))
2797 (clobber (reg:CC CC_REGNUM))]
2800 "&& reload_completed"
2802 (and:DI (subreg:DI (match_dup 1) 0)
2803 (const_int 2147483647)))]
2806 (define_insn "*llgt_sisi"
2807 [(set (match_operand:SI 0 "register_operand" "=d,d")
2808 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2809 (const_int 2147483647)))]
2814 [(set_attr "op_type" "RRE,RXE")])
2816 (define_insn "*llgt_didi"
2817 [(set (match_operand:DI 0 "register_operand" "=d,d")
2818 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2819 (const_int 2147483647)))]
2824 [(set_attr "op_type" "RRE,RXE")])
2827 [(set (match_operand:GPR 0 "register_operand" "")
2828 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2829 (const_int 2147483647)))
2830 (clobber (reg:CC CC_REGNUM))]
2831 "TARGET_ZARCH && reload_completed"
2833 (and:GPR (match_dup 1)
2834 (const_int 2147483647)))]
2838 ; zero_extend(hi|qi)si2 instruction pattern(s).
2841 (define_expand "zero_extend<mode>si2"
2842 [(set (match_operand:SI 0 "register_operand" "")
2843 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2848 operands[1] = gen_lowpart (SImode, operands[1]);
2849 emit_insn (gen_andsi3 (operands[0], operands[1],
2850 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2855 (define_insn "*zero_extend<mode>si2_extimm"
2856 [(set (match_operand:SI 0 "register_operand" "=d,d")
2857 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2862 [(set_attr "op_type" "RRE,RXY")])
2864 (define_insn "*zero_extend<mode>si2_64"
2865 [(set (match_operand:SI 0 "register_operand" "=d")
2866 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2867 "TARGET_ZARCH && !TARGET_EXTIMM"
2869 [(set_attr "op_type" "RXY")])
2871 (define_insn_and_split "*zero_extendhisi2_31"
2872 [(set (match_operand:SI 0 "register_operand" "=&d")
2873 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2874 (clobber (reg:CC CC_REGNUM))]
2877 "&& reload_completed"
2878 [(set (match_dup 0) (const_int 0))
2880 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2881 (clobber (reg:CC CC_REGNUM))])]
2882 "operands[2] = gen_lowpart (HImode, operands[0]);")
2884 (define_insn_and_split "*zero_extendqisi2_31"
2885 [(set (match_operand:SI 0 "register_operand" "=&d")
2886 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2889 "&& reload_completed"
2890 [(set (match_dup 0) (const_int 0))
2891 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2892 "operands[2] = gen_lowpart (QImode, operands[0]);")
2895 ; zero_extendqihi2 instruction pattern(s).
2898 (define_expand "zero_extendqihi2"
2899 [(set (match_operand:HI 0 "register_operand" "")
2900 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2901 "TARGET_ZARCH && !TARGET_EXTIMM"
2903 operands[1] = gen_lowpart (HImode, operands[1]);
2904 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2908 (define_insn "*zero_extendqihi2_64"
2909 [(set (match_operand:HI 0 "register_operand" "=d")
2910 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2911 "TARGET_ZARCH && !TARGET_EXTIMM"
2913 [(set_attr "op_type" "RXY")])
2915 (define_insn_and_split "*zero_extendqihi2_31"
2916 [(set (match_operand:HI 0 "register_operand" "=&d")
2917 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2920 "&& reload_completed"
2921 [(set (match_dup 0) (const_int 0))
2922 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2923 "operands[2] = gen_lowpart (QImode, operands[0]);")
2927 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2930 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2931 [(set (match_operand:GPR 0 "register_operand" "")
2932 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2933 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2935 rtx label1 = gen_label_rtx ();
2936 rtx label2 = gen_label_rtx ();
2937 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2938 REAL_VALUE_TYPE cmp, sub;
2940 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2941 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2942 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2944 emit_insn (gen_cmp<FPR:mode> (operands[1],
2945 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2946 emit_jump_insn (gen_blt (label1));
2947 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2948 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2949 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2953 emit_label (label1);
2954 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2955 operands[1], GEN_INT(5)));
2956 emit_label (label2);
2960 (define_expand "fix_trunc<FPR:mode>di2"
2961 [(set (match_operand:DI 0 "register_operand" "")
2962 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2963 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2965 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2966 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2971 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2972 [(set (match_operand:GPR 0 "register_operand" "=d")
2973 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2974 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2975 (clobber (reg:CC CC_REGNUM))]
2976 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2977 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2978 [(set_attr "op_type" "RRE")
2979 (set_attr "type" "ftoi")])
2982 ; fix_truncdfsi2 instruction pattern(s).
2985 (define_expand "fix_truncdfsi2"
2986 [(set (match_operand:SI 0 "register_operand" "")
2987 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2990 if (TARGET_IBM_FLOAT)
2992 /* This is the algorithm from POP chapter A.5.7.2. */
2994 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2995 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2996 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2998 operands[1] = force_reg (DFmode, operands[1]);
2999 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3000 two31r, two32, temp));
3004 operands[1] = force_reg (DFmode, operands[1]);
3005 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3011 (define_insn "fix_truncdfsi2_ibm"
3012 [(set (match_operand:SI 0 "register_operand" "=d")
3013 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3014 (use (match_operand:DI 2 "immediate_operand" "m"))
3015 (use (match_operand:DI 3 "immediate_operand" "m"))
3016 (use (match_operand:BLK 4 "memory_operand" "m"))
3017 (clobber (reg:CC CC_REGNUM))]
3018 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3020 output_asm_insn ("sd\t%1,%2", operands);
3021 output_asm_insn ("aw\t%1,%3", operands);
3022 output_asm_insn ("std\t%1,%4", operands);
3023 output_asm_insn ("xi\t%N4,128", operands);
3026 [(set_attr "length" "20")])
3029 ; fix_truncsfsi2 instruction pattern(s).
3032 (define_expand "fix_truncsfsi2"
3033 [(set (match_operand:SI 0 "register_operand" "")
3034 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3037 if (TARGET_IBM_FLOAT)
3039 /* Convert to DFmode and then use the POP algorithm. */
3040 rtx temp = gen_reg_rtx (DFmode);
3041 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3042 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3046 operands[1] = force_reg (SFmode, operands[1]);
3047 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3054 ; floatdi(df|sf)2 instruction pattern(s).
3057 (define_insn "floatdi<mode>2"
3058 [(set (match_operand:FPR 0 "register_operand" "=f")
3059 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3060 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3062 [(set_attr "op_type" "RRE")
3063 (set_attr "type" "itof" )])
3066 ; floatsidf2 instruction pattern(s).
3069 (define_expand "floatsidf2"
3070 [(set (match_operand:DF 0 "register_operand" "")
3071 (float:DF (match_operand:SI 1 "register_operand" "")))]
3074 if (TARGET_IBM_FLOAT)
3076 /* This is the algorithm from POP chapter A.5.7.1. */
3078 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3079 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3081 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3086 (define_insn "floatsidf2_ieee"
3087 [(set (match_operand:DF 0 "register_operand" "=f")
3088 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3089 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3091 [(set_attr "op_type" "RRE")
3092 (set_attr "type" "itof" )])
3094 (define_insn "floatsidf2_ibm"
3095 [(set (match_operand:DF 0 "register_operand" "=f")
3096 (float:DF (match_operand:SI 1 "register_operand" "d")))
3097 (use (match_operand:DI 2 "immediate_operand" "m"))
3098 (use (match_operand:BLK 3 "memory_operand" "m"))
3099 (clobber (reg:CC CC_REGNUM))]
3100 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3102 output_asm_insn ("st\t%1,%N3", operands);
3103 output_asm_insn ("xi\t%N3,128", operands);
3104 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3105 output_asm_insn ("ld\t%0,%3", operands);
3108 [(set_attr "length" "20")])
3111 ; floatsisf2 instruction pattern(s).
3114 (define_expand "floatsisf2"
3115 [(set (match_operand:SF 0 "register_operand" "")
3116 (float:SF (match_operand:SI 1 "register_operand" "")))]
3119 if (TARGET_IBM_FLOAT)
3121 /* Use the POP algorithm to convert to DFmode and then truncate. */
3122 rtx temp = gen_reg_rtx (DFmode);
3123 emit_insn (gen_floatsidf2 (temp, operands[1]));
3124 emit_insn (gen_truncdfsf2 (operands[0], temp));
3129 (define_insn "floatsisf2_ieee"
3130 [(set (match_operand:SF 0 "register_operand" "=f")
3131 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3132 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3134 [(set_attr "op_type" "RRE")
3135 (set_attr "type" "itof" )])
3138 ; truncdfsf2 instruction pattern(s).
3141 (define_expand "truncdfsf2"
3142 [(set (match_operand:SF 0 "register_operand" "")
3143 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3147 (define_insn "truncdfsf2_ieee"
3148 [(set (match_operand:SF 0 "register_operand" "=f")
3149 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3150 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3152 [(set_attr "op_type" "RRE")])
3154 (define_insn "truncdfsf2_ibm"
3155 [(set (match_operand:SF 0 "register_operand" "=f,f")
3156 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3157 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3161 [(set_attr "op_type" "RR,RX")
3162 (set_attr "type" "floadsf")])
3165 ; extendsfdf2 instruction pattern(s).
3168 (define_expand "extendsfdf2"
3169 [(set (match_operand:DF 0 "register_operand" "")
3170 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3173 if (TARGET_IBM_FLOAT)
3175 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3180 (define_insn "extendsfdf2_ieee"
3181 [(set (match_operand:DF 0 "register_operand" "=f,f")
3182 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3183 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3187 [(set_attr "op_type" "RRE,RXE")
3188 (set_attr "type" "floadsf")])
3190 (define_insn "extendsfdf2_ibm"
3191 [(set (match_operand:DF 0 "register_operand" "=f,f")
3192 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3193 (clobber (reg:CC CC_REGNUM))]
3194 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3196 sdr\t%0,%0\;ler\t%0,%1
3197 sdr\t%0,%0\;le\t%0,%1"
3198 [(set_attr "length" "4,6")
3199 (set_attr "type" "floadsf")])
3203 ;; ARITHMETIC OPERATIONS
3205 ; arithmetic operations set the ConditionCode,
3206 ; because of unpredictable Bits in Register for Halfword and Byte
3207 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3210 ;;- Add instructions.
3214 ; addti3 instruction pattern(s).
3217 (define_insn_and_split "addti3"
3218 [(set (match_operand:TI 0 "register_operand" "=&d")
3219 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3220 (match_operand:TI 2 "general_operand" "do") ) )
3221 (clobber (reg:CC CC_REGNUM))]
3224 "&& reload_completed"
3226 [(set (reg:CCL1 CC_REGNUM)
3227 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3229 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3231 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3232 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3233 (clobber (reg:CC CC_REGNUM))])]
3234 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3235 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3236 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3237 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3238 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3239 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3242 ; adddi3 instruction pattern(s).
3245 (define_insn "*adddi3_sign"
3246 [(set (match_operand:DI 0 "register_operand" "=d,d")
3247 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3248 (match_operand:DI 1 "register_operand" "0,0")))
3249 (clobber (reg:CC CC_REGNUM))]
3254 [(set_attr "op_type" "RRE,RXY")])
3256 (define_insn "*adddi3_zero_cc"
3257 [(set (reg CC_REGNUM)
3258 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3259 (match_operand:DI 1 "register_operand" "0,0"))
3261 (set (match_operand:DI 0 "register_operand" "=d,d")
3262 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3263 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3267 [(set_attr "op_type" "RRE,RXY")])
3269 (define_insn "*adddi3_zero_cconly"
3270 [(set (reg CC_REGNUM)
3271 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3272 (match_operand:DI 1 "register_operand" "0,0"))
3274 (clobber (match_scratch:DI 0 "=d,d"))]
3275 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3279 [(set_attr "op_type" "RRE,RXY")])
3281 (define_insn "*adddi3_zero"
3282 [(set (match_operand:DI 0 "register_operand" "=d,d")
3283 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3284 (match_operand:DI 1 "register_operand" "0,0")))
3285 (clobber (reg:CC CC_REGNUM))]
3290 [(set_attr "op_type" "RRE,RXY")])
3292 (define_insn "*adddi3_imm_cc"
3293 [(set (reg CC_REGNUM)
3294 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3295 (match_operand:DI 2 "const_int_operand" "K,Os"))
3297 (set (match_operand:DI 0 "register_operand" "=d,d")
3298 (plus:DI (match_dup 1) (match_dup 2)))]
3300 && s390_match_ccmode (insn, CCAmode)
3301 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3302 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3306 [(set_attr "op_type" "RI,RIL")])
3308 (define_insn "*adddi3_carry1_cc"
3309 [(set (reg CC_REGNUM)
3310 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3311 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3313 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3314 (plus:DI (match_dup 1) (match_dup 2)))]
3315 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3321 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3323 (define_insn "*adddi3_carry1_cconly"
3324 [(set (reg CC_REGNUM)
3325 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3326 (match_operand:DI 2 "general_operand" "d,m"))
3328 (clobber (match_scratch:DI 0 "=d,d"))]
3329 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3333 [(set_attr "op_type" "RRE,RXY")])
3335 (define_insn "*adddi3_carry2_cc"
3336 [(set (reg CC_REGNUM)
3337 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3338 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3340 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3341 (plus:DI (match_dup 1) (match_dup 2)))]
3342 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3348 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3350 (define_insn "*adddi3_carry2_cconly"
3351 [(set (reg CC_REGNUM)
3352 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3353 (match_operand:DI 2 "general_operand" "d,m"))
3355 (clobber (match_scratch:DI 0 "=d,d"))]
3356 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3360 [(set_attr "op_type" "RRE,RXY")])
3362 (define_insn "*adddi3_cc"
3363 [(set (reg CC_REGNUM)
3364 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3365 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3367 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3368 (plus:DI (match_dup 1) (match_dup 2)))]
3369 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3375 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3377 (define_insn "*adddi3_cconly"
3378 [(set (reg CC_REGNUM)
3379 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3380 (match_operand:DI 2 "general_operand" "d,m"))
3382 (clobber (match_scratch:DI 0 "=d,d"))]
3383 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3387 [(set_attr "op_type" "RRE,RXY")])
3389 (define_insn "*adddi3_cconly2"
3390 [(set (reg CC_REGNUM)
3391 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3392 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3393 (clobber (match_scratch:DI 0 "=d,d"))]
3394 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3398 [(set_attr "op_type" "RRE,RXY")])
3400 (define_insn "*adddi3_64"
3401 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3402 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3403 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3404 (clobber (reg:CC CC_REGNUM))]
3412 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3414 (define_insn_and_split "*adddi3_31z"
3415 [(set (match_operand:DI 0 "register_operand" "=&d")
3416 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3417 (match_operand:DI 2 "general_operand" "do") ) )
3418 (clobber (reg:CC CC_REGNUM))]
3419 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3421 "&& reload_completed"
3423 [(set (reg:CCL1 CC_REGNUM)
3424 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3426 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3428 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3429 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3430 (clobber (reg:CC CC_REGNUM))])]
3431 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3432 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3433 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3434 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3435 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3436 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3438 (define_insn_and_split "*adddi3_31"
3439 [(set (match_operand:DI 0 "register_operand" "=&d")
3440 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3441 (match_operand:DI 2 "general_operand" "do") ) )
3442 (clobber (reg:CC CC_REGNUM))]
3445 "&& reload_completed"
3447 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3448 (clobber (reg:CC CC_REGNUM))])
3450 [(set (reg:CCL1 CC_REGNUM)
3451 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3453 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3455 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3457 (label_ref (match_dup 9))))
3459 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3460 (clobber (reg:CC CC_REGNUM))])
3462 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3463 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3464 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3465 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3466 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3467 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3468 operands[9] = gen_label_rtx ();")
3470 (define_expand "adddi3"
3472 [(set (match_operand:DI 0 "register_operand" "")
3473 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3474 (match_operand:DI 2 "general_operand" "")))
3475 (clobber (reg:CC CC_REGNUM))])]
3480 ; addsi3 instruction pattern(s).
3483 (define_insn "*addsi3_imm_cc"
3484 [(set (reg CC_REGNUM)
3485 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3486 (match_operand:SI 2 "const_int_operand" "K,Os"))
3488 (set (match_operand:SI 0 "register_operand" "=d,d")
3489 (plus:SI (match_dup 1) (match_dup 2)))]
3490 "s390_match_ccmode (insn, CCAmode)
3491 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3492 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3493 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3497 [(set_attr "op_type" "RI,RIL")])
3499 (define_insn "*addsi3_carry1_cc"
3500 [(set (reg CC_REGNUM)
3501 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3502 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3504 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3505 (plus:SI (match_dup 1) (match_dup 2)))]
3506 "s390_match_ccmode (insn, CCL1mode)"
3512 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3514 (define_insn "*addsi3_carry1_cconly"
3515 [(set (reg CC_REGNUM)
3516 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3517 (match_operand:SI 2 "general_operand" "d,R,T"))
3519 (clobber (match_scratch:SI 0 "=d,d,d"))]
3520 "s390_match_ccmode (insn, CCL1mode)"
3525 [(set_attr "op_type" "RR,RX,RXY")])
3527 (define_insn "*addsi3_carry2_cc"
3528 [(set (reg CC_REGNUM)
3529 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3530 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3532 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3533 (plus:SI (match_dup 1) (match_dup 2)))]
3534 "s390_match_ccmode (insn, CCL1mode)"
3540 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3542 (define_insn "*addsi3_carry2_cconly"
3543 [(set (reg CC_REGNUM)
3544 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3545 (match_operand:SI 2 "general_operand" "d,R,T"))
3547 (clobber (match_scratch:SI 0 "=d,d,d"))]
3548 "s390_match_ccmode (insn, CCL1mode)"
3553 [(set_attr "op_type" "RR,RX,RXY")])
3555 (define_insn "*addsi3_cc"
3556 [(set (reg CC_REGNUM)
3557 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3558 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3560 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3561 (plus:SI (match_dup 1) (match_dup 2)))]
3562 "s390_match_ccmode (insn, CCLmode)"
3568 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3570 (define_insn "*addsi3_cconly"
3571 [(set (reg CC_REGNUM)
3572 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3573 (match_operand:SI 2 "general_operand" "d,R,T"))
3575 (clobber (match_scratch:SI 0 "=d,d,d"))]
3576 "s390_match_ccmode (insn, CCLmode)"
3581 [(set_attr "op_type" "RR,RX,RXY")])
3583 (define_insn "*addsi3_cconly2"
3584 [(set (reg CC_REGNUM)
3585 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3586 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3587 (clobber (match_scratch:SI 0 "=d,d,d"))]
3588 "s390_match_ccmode (insn, CCLmode)"
3593 [(set_attr "op_type" "RR,RX,RXY")])
3595 (define_insn "*addsi3_sign"
3596 [(set (match_operand:SI 0 "register_operand" "=d,d")
3597 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3598 (match_operand:SI 1 "register_operand" "0,0")))
3599 (clobber (reg:CC CC_REGNUM))]
3604 [(set_attr "op_type" "RX,RXY")])
3606 (define_insn "addsi3"
3607 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3608 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3609 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3610 (clobber (reg:CC CC_REGNUM))]
3618 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3621 ; add(df|sf)3 instruction pattern(s).
3624 (define_expand "add<mode>3"
3626 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3627 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3628 (match_operand:FPR 2 "general_operand" "f,R")))
3629 (clobber (reg:CC CC_REGNUM))])]
3633 (define_insn "*add<mode>3"
3634 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3635 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3636 (match_operand:FPR 2 "general_operand" "f,R")))
3637 (clobber (reg:CC CC_REGNUM))]
3638 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3642 [(set_attr "op_type" "RRE,RXE")
3643 (set_attr "type" "fsimp<mode>")])
3645 (define_insn "*add<mode>3_cc"
3646 [(set (reg CC_REGNUM)
3647 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3648 (match_operand:FPR 2 "general_operand" "f,R"))
3649 (match_operand:FPR 3 "const0_operand" "")))
3650 (set (match_operand:FPR 0 "register_operand" "=f,f")
3651 (plus:FPR (match_dup 1) (match_dup 2)))]
3652 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3656 [(set_attr "op_type" "RRE,RXE")
3657 (set_attr "type" "fsimp<mode>")])
3659 (define_insn "*add<mode>3_cconly"
3660 [(set (reg CC_REGNUM)
3661 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3662 (match_operand:FPR 2 "general_operand" "f,R"))
3663 (match_operand:FPR 3 "const0_operand" "")))
3664 (clobber (match_scratch:FPR 0 "=f,f"))]
3665 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3669 [(set_attr "op_type" "RRE,RXE")
3670 (set_attr "type" "fsimp<mode>")])
3672 (define_insn "*add<mode>3_ibm"
3673 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3674 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3675 (match_operand:FPR 2 "general_operand" "f,R")))
3676 (clobber (reg:CC CC_REGNUM))]
3677 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3681 [(set_attr "op_type" "RR,RX")
3682 (set_attr "type" "fsimp<mode>")])
3686 ;;- Subtract instructions.
3690 ; subti3 instruction pattern(s).
3693 (define_insn_and_split "subti3"
3694 [(set (match_operand:TI 0 "register_operand" "=&d")
3695 (minus:TI (match_operand:TI 1 "register_operand" "0")
3696 (match_operand:TI 2 "general_operand" "do") ) )
3697 (clobber (reg:CC CC_REGNUM))]
3700 "&& reload_completed"
3702 [(set (reg:CCL2 CC_REGNUM)
3703 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3705 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3707 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3708 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3709 (clobber (reg:CC CC_REGNUM))])]
3710 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3711 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3712 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3713 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3714 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3715 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3718 ; subdi3 instruction pattern(s).
3721 (define_insn "*subdi3_sign"
3722 [(set (match_operand:DI 0 "register_operand" "=d,d")
3723 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3724 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3725 (clobber (reg:CC CC_REGNUM))]
3730 [(set_attr "op_type" "RRE,RXY")])
3732 (define_insn "*subdi3_zero_cc"
3733 [(set (reg CC_REGNUM)
3734 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3735 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3737 (set (match_operand:DI 0 "register_operand" "=d,d")
3738 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3739 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3743 [(set_attr "op_type" "RRE,RXY")])
3745 (define_insn "*subdi3_zero_cconly"
3746 [(set (reg CC_REGNUM)
3747 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3748 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3750 (clobber (match_scratch:DI 0 "=d,d"))]
3751 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3755 [(set_attr "op_type" "RRE,RXY")])
3757 (define_insn "*subdi3_zero"
3758 [(set (match_operand:DI 0 "register_operand" "=d,d")
3759 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3760 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3761 (clobber (reg:CC CC_REGNUM))]
3766 [(set_attr "op_type" "RRE,RXY")])
3768 (define_insn "*subdi3_borrow_cc"
3769 [(set (reg CC_REGNUM)
3770 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3771 (match_operand:DI 2 "general_operand" "d,m"))
3773 (set (match_operand:DI 0 "register_operand" "=d,d")
3774 (minus:DI (match_dup 1) (match_dup 2)))]
3775 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3779 [(set_attr "op_type" "RRE,RXY")])
3781 (define_insn "*subdi3_borrow_cconly"
3782 [(set (reg CC_REGNUM)
3783 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3784 (match_operand:DI 2 "general_operand" "d,m"))
3786 (clobber (match_scratch:DI 0 "=d,d"))]
3787 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3791 [(set_attr "op_type" "RRE,RXY")])
3793 (define_insn "*subdi3_cc"
3794 [(set (reg CC_REGNUM)
3795 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3796 (match_operand:DI 2 "general_operand" "d,m"))
3798 (set (match_operand:DI 0 "register_operand" "=d,d")
3799 (minus:DI (match_dup 1) (match_dup 2)))]
3800 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3804 [(set_attr "op_type" "RRE,RXY")])
3806 (define_insn "*subdi3_cc2"
3807 [(set (reg CC_REGNUM)
3808 (compare (match_operand:DI 1 "register_operand" "0,0")
3809 (match_operand:DI 2 "general_operand" "d,m")))
3810 (set (match_operand:DI 0 "register_operand" "=d,d")
3811 (minus:DI (match_dup 1) (match_dup 2)))]
3812 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3816 [(set_attr "op_type" "RRE,RXY")])
3818 (define_insn "*subdi3_cconly"
3819 [(set (reg CC_REGNUM)
3820 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3821 (match_operand:DI 2 "general_operand" "d,m"))
3823 (clobber (match_scratch:DI 0 "=d,d"))]
3824 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3828 [(set_attr "op_type" "RRE,RXY")])
3830 (define_insn "*subdi3_cconly2"
3831 [(set (reg CC_REGNUM)
3832 (compare (match_operand:DI 1 "register_operand" "0,0")
3833 (match_operand:DI 2 "general_operand" "d,m")))
3834 (clobber (match_scratch:DI 0 "=d,d"))]
3835 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3839 [(set_attr "op_type" "RRE,RXY")])
3841 (define_insn "*subdi3_64"
3842 [(set (match_operand:DI 0 "register_operand" "=d,d")
3843 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3844 (match_operand:DI 2 "general_operand" "d,m") ) )
3845 (clobber (reg:CC CC_REGNUM))]
3850 [(set_attr "op_type" "RRE,RRE")])
3852 (define_insn_and_split "*subdi3_31z"
3853 [(set (match_operand:DI 0 "register_operand" "=&d")
3854 (minus:DI (match_operand:DI 1 "register_operand" "0")
3855 (match_operand:DI 2 "general_operand" "do") ) )
3856 (clobber (reg:CC CC_REGNUM))]
3857 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3859 "&& reload_completed"
3861 [(set (reg:CCL2 CC_REGNUM)
3862 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3864 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3866 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3867 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3868 (clobber (reg:CC CC_REGNUM))])]
3869 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3870 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3871 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3872 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3873 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3874 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3876 (define_insn_and_split "*subdi3_31"
3877 [(set (match_operand:DI 0 "register_operand" "=&d")
3878 (minus:DI (match_operand:DI 1 "register_operand" "0")
3879 (match_operand:DI 2 "general_operand" "do") ) )
3880 (clobber (reg:CC CC_REGNUM))]
3883 "&& reload_completed"
3885 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3886 (clobber (reg:CC CC_REGNUM))])
3888 [(set (reg:CCL2 CC_REGNUM)
3889 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3891 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3893 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3895 (label_ref (match_dup 9))))
3897 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3898 (clobber (reg:CC CC_REGNUM))])
3900 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3901 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3902 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3903 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3904 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3905 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3906 operands[9] = gen_label_rtx ();")
3908 (define_expand "subdi3"
3910 [(set (match_operand:DI 0 "register_operand" "")
3911 (minus:DI (match_operand:DI 1 "register_operand" "")
3912 (match_operand:DI 2 "general_operand" "")))
3913 (clobber (reg:CC CC_REGNUM))])]
3918 ; subsi3 instruction pattern(s).
3921 (define_insn "*subsi3_borrow_cc"
3922 [(set (reg CC_REGNUM)
3923 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3924 (match_operand:SI 2 "general_operand" "d,R,T"))
3926 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3927 (minus:SI (match_dup 1) (match_dup 2)))]
3928 "s390_match_ccmode (insn, CCL2mode)"
3933 [(set_attr "op_type" "RR,RX,RXY")])
3935 (define_insn "*subsi3_borrow_cconly"
3936 [(set (reg CC_REGNUM)
3937 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3938 (match_operand:SI 2 "general_operand" "d,R,T"))
3940 (clobber (match_scratch:SI 0 "=d,d,d"))]
3941 "s390_match_ccmode (insn, CCL2mode)"
3946 [(set_attr "op_type" "RR,RX,RXY")])
3948 (define_insn "*subsi3_cc"
3949 [(set (reg CC_REGNUM)
3950 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3951 (match_operand:SI 2 "general_operand" "d,R,T"))
3953 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3954 (minus:SI (match_dup 1) (match_dup 2)))]
3955 "s390_match_ccmode (insn, CCLmode)"
3960 [(set_attr "op_type" "RR,RX,RXY")])
3962 (define_insn "*subsi3_cc2"
3963 [(set (reg CC_REGNUM)
3964 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3965 (match_operand:SI 2 "general_operand" "d,R,T")))
3966 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3967 (minus:SI (match_dup 1) (match_dup 2)))]
3968 "s390_match_ccmode (insn, CCL3mode)"
3973 [(set_attr "op_type" "RR,RX,RXY")])
3975 (define_insn "*subsi3_cconly"
3976 [(set (reg CC_REGNUM)
3977 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3978 (match_operand:SI 2 "general_operand" "d,R,T"))
3980 (clobber (match_scratch:SI 0 "=d,d,d"))]
3981 "s390_match_ccmode (insn, CCLmode)"
3986 [(set_attr "op_type" "RR,RX,RXY")])
3988 (define_insn "*subsi3_cconly2"
3989 [(set (reg CC_REGNUM)
3990 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3991 (match_operand:SI 2 "general_operand" "d,R,T")))
3992 (clobber (match_scratch:SI 0 "=d,d,d"))]
3993 "s390_match_ccmode (insn, CCL3mode)"
3998 [(set_attr "op_type" "RR,RX,RXY")])
4000 (define_insn "*subsi3_sign"
4001 [(set (match_operand:SI 0 "register_operand" "=d,d")
4002 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4003 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4004 (clobber (reg:CC CC_REGNUM))]
4009 [(set_attr "op_type" "RX,RXY")])
4011 (define_insn "subsi3"
4012 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4013 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4014 (match_operand:SI 2 "general_operand" "d,R,T")))
4015 (clobber (reg:CC CC_REGNUM))]
4021 [(set_attr "op_type" "RR,RX,RXY")])
4025 ; sub(df|sf)3 instruction pattern(s).
4028 (define_expand "sub<mode>3"
4030 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4031 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4032 (match_operand:FPR 2 "general_operand" "f,R")))
4033 (clobber (reg:CC CC_REGNUM))])]
4037 (define_insn "*sub<mode>3"
4038 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4039 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4040 (match_operand:FPR 2 "general_operand" "f,R")))
4041 (clobber (reg:CC CC_REGNUM))]
4042 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4046 [(set_attr "op_type" "RRE,RXE")
4047 (set_attr "type" "fsimp<mode>")])
4049 (define_insn "*sub<mode>3_cc"
4050 [(set (reg CC_REGNUM)
4051 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4052 (match_operand:FPR 2 "general_operand" "f,R"))
4053 (match_operand:FPR 3 "const0_operand" "")))
4054 (set (match_operand:FPR 0 "register_operand" "=f,f")
4055 (minus:FPR (match_dup 1) (match_dup 2)))]
4056 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4060 [(set_attr "op_type" "RRE,RXE")
4061 (set_attr "type" "fsimp<mode>")])
4063 (define_insn "*sub<mode>3_cconly"
4064 [(set (reg CC_REGNUM)
4065 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4066 (match_operand:FPR 2 "general_operand" "f,R"))
4067 (match_operand:FPR 3 "const0_operand" "")))
4068 (clobber (match_scratch:FPR 0 "=f,f"))]
4069 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4073 [(set_attr "op_type" "RRE,RXE")
4074 (set_attr "type" "fsimp<mode>")])
4076 (define_insn "*sub<mode>3_ibm"
4077 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4078 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4079 (match_operand:FPR 2 "general_operand" "f,R")))
4080 (clobber (reg:CC CC_REGNUM))]
4081 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4085 [(set_attr "op_type" "RR,RX")
4086 (set_attr "type" "fsimp<mode>")])
4090 ;;- Conditional add/subtract instructions.
4094 ; add(di|si)cc instruction pattern(s).
4097 (define_insn "*add<mode>3_alc_cc"
4098 [(set (reg CC_REGNUM)
4100 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4101 (match_operand:GPR 2 "general_operand" "d,m"))
4102 (match_operand:GPR 3 "s390_alc_comparison" ""))
4104 (set (match_operand:GPR 0 "register_operand" "=d,d")
4105 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4106 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4110 [(set_attr "op_type" "RRE,RXY")])
4112 (define_insn "*add<mode>3_alc"
4113 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4114 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4115 (match_operand:GPR 2 "general_operand" "d,m"))
4116 (match_operand:GPR 3 "s390_alc_comparison" "")))
4117 (clobber (reg:CC CC_REGNUM))]
4122 [(set_attr "op_type" "RRE,RXY")])
4124 (define_insn "*sub<mode>3_slb_cc"
4125 [(set (reg CC_REGNUM)
4127 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4128 (match_operand:GPR 2 "general_operand" "d,m"))
4129 (match_operand:GPR 3 "s390_slb_comparison" ""))
4131 (set (match_operand:GPR 0 "register_operand" "=d,d")
4132 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4133 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4137 [(set_attr "op_type" "RRE,RXY")])
4139 (define_insn "*sub<mode>3_slb"
4140 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4141 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4142 (match_operand:GPR 2 "general_operand" "d,m"))
4143 (match_operand:GPR 3 "s390_slb_comparison" "")))
4144 (clobber (reg:CC CC_REGNUM))]
4149 [(set_attr "op_type" "RRE,RXY")])
4151 (define_expand "add<mode>cc"
4152 [(match_operand:GPR 0 "register_operand" "")
4153 (match_operand 1 "comparison_operator" "")
4154 (match_operand:GPR 2 "register_operand" "")
4155 (match_operand:GPR 3 "const_int_operand" "")]
4157 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4158 s390_compare_op0, s390_compare_op1,
4159 operands[0], operands[2],
4160 operands[3])) FAIL; DONE;")
4163 ; scond instruction pattern(s).
4166 (define_insn_and_split "*scond<mode>"
4167 [(set (match_operand:GPR 0 "register_operand" "=&d")
4168 (match_operand:GPR 1 "s390_alc_comparison" ""))
4169 (clobber (reg:CC CC_REGNUM))]
4172 "&& reload_completed"
4173 [(set (match_dup 0) (const_int 0))
4175 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4177 (clobber (reg:CC CC_REGNUM))])]
4180 (define_insn_and_split "*scond<mode>_neg"
4181 [(set (match_operand:GPR 0 "register_operand" "=&d")
4182 (match_operand:GPR 1 "s390_slb_comparison" ""))
4183 (clobber (reg:CC CC_REGNUM))]
4186 "&& reload_completed"
4187 [(set (match_dup 0) (const_int 0))
4189 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4191 (clobber (reg:CC CC_REGNUM))])
4193 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4194 (clobber (reg:CC CC_REGNUM))])]
4198 (define_expand "s<code>"
4199 [(set (match_operand:SI 0 "register_operand" "")
4200 (SCOND (match_dup 0)
4203 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4204 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4206 (define_expand "seq"
4208 [(set (match_operand:SI 0 "register_operand" "=d")
4210 (clobber (reg:CC CC_REGNUM))])
4212 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4213 (clobber (reg:CC CC_REGNUM))])]
4216 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4218 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4219 PUT_MODE (operands[1], SImode);
4222 (define_insn_and_split "*sne"
4223 [(set (match_operand:SI 0 "register_operand" "=d")
4224 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4226 (clobber (reg:CC CC_REGNUM))]
4231 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4232 (clobber (reg:CC CC_REGNUM))])])
4236 ;;- Multiply instructions.
4240 ; muldi3 instruction pattern(s).
4243 (define_insn "*muldi3_sign"
4244 [(set (match_operand:DI 0 "register_operand" "=d,d")
4245 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4246 (match_operand:DI 1 "register_operand" "0,0")))]
4251 [(set_attr "op_type" "RRE,RXY")
4252 (set_attr "type" "imuldi")])
4254 (define_insn "muldi3"
4255 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4256 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4257 (match_operand:DI 2 "general_operand" "d,K,m")))]
4263 [(set_attr "op_type" "RRE,RI,RXY")
4264 (set_attr "type" "imuldi")])
4267 ; mulsi3 instruction pattern(s).
4270 (define_insn "*mulsi3_sign"
4271 [(set (match_operand:SI 0 "register_operand" "=d")
4272 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4273 (match_operand:SI 1 "register_operand" "0")))]
4276 [(set_attr "op_type" "RX")
4277 (set_attr "type" "imulhi")])
4279 (define_insn "mulsi3"
4280 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4281 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4282 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4289 [(set_attr "op_type" "RRE,RI,RX,RXY")
4290 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4293 ; mulsidi3 instruction pattern(s).
4296 (define_insn "mulsidi3"
4297 [(set (match_operand:DI 0 "register_operand" "=d,d")
4298 (mult:DI (sign_extend:DI
4299 (match_operand:SI 1 "register_operand" "%0,0"))
4301 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4306 [(set_attr "op_type" "RR,RX")
4307 (set_attr "type" "imulsi")])
4310 ; umulsidi3 instruction pattern(s).
4313 (define_insn "umulsidi3"
4314 [(set (match_operand:DI 0 "register_operand" "=d,d")
4315 (mult:DI (zero_extend:DI
4316 (match_operand:SI 1 "register_operand" "%0,0"))
4318 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4319 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4323 [(set_attr "op_type" "RRE,RXY")
4324 (set_attr "type" "imulsi")])
4327 ; mul(df|sf)3 instruction pattern(s).
4330 (define_expand "mul<mode>3"
4331 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4332 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4333 (match_operand:FPR 2 "general_operand" "f,R")))]
4337 (define_insn "*mul<mode>3"
4338 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4339 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4340 (match_operand:FPR 2 "general_operand" "f,R")))]
4341 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4345 [(set_attr "op_type" "RRE,RXE")
4346 (set_attr "type" "fmul<mode>")])
4348 (define_insn "*mul<mode>3_ibm"
4349 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4350 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4351 (match_operand:FPR 2 "general_operand" "f,R")))]
4352 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4356 [(set_attr "op_type" "RR,RX")
4357 (set_attr "type" "fmul<mode>")])
4359 (define_insn "*fmadd<mode>"
4360 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4361 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4362 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4363 (match_operand:FPR 3 "register_operand" "0,0")))]
4364 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4368 [(set_attr "op_type" "RRE,RXE")
4369 (set_attr "type" "fmul<mode>")])
4371 (define_insn "*fmsub<mode>"
4372 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4373 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4374 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4375 (match_operand:FPR 3 "register_operand" "0,0")))]
4376 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4380 [(set_attr "op_type" "RRE,RXE")
4381 (set_attr "type" "fmul<mode>")])
4384 ;;- Divide and modulo instructions.
4388 ; divmoddi4 instruction pattern(s).
4391 (define_expand "divmoddi4"
4392 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4393 (div:DI (match_operand:DI 1 "register_operand" "")
4394 (match_operand:DI 2 "general_operand" "")))
4395 (set (match_operand:DI 3 "general_operand" "")
4396 (mod:DI (match_dup 1) (match_dup 2)))])
4397 (clobber (match_dup 4))]
4400 rtx insn, div_equal, mod_equal;
4402 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4403 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4405 operands[4] = gen_reg_rtx(TImode);
4406 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4408 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4410 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4412 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4414 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4419 (define_insn "divmodtidi3"
4420 [(set (match_operand:TI 0 "register_operand" "=d,d")
4424 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4425 (match_operand:DI 2 "general_operand" "d,m")))
4427 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4432 [(set_attr "op_type" "RRE,RXY")
4433 (set_attr "type" "idiv")])
4435 (define_insn "divmodtisi3"
4436 [(set (match_operand:TI 0 "register_operand" "=d,d")
4440 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4442 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4445 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4450 [(set_attr "op_type" "RRE,RXY")
4451 (set_attr "type" "idiv")])
4454 ; udivmoddi4 instruction pattern(s).
4457 (define_expand "udivmoddi4"
4458 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4459 (udiv:DI (match_operand:DI 1 "general_operand" "")
4460 (match_operand:DI 2 "nonimmediate_operand" "")))
4461 (set (match_operand:DI 3 "general_operand" "")
4462 (umod:DI (match_dup 1) (match_dup 2)))])
4463 (clobber (match_dup 4))]
4466 rtx insn, div_equal, mod_equal, equal;
4468 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4469 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4470 equal = gen_rtx_IOR (TImode,
4471 gen_rtx_ASHIFT (TImode,
4472 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4474 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4476 operands[4] = gen_reg_rtx(TImode);
4477 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4478 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4479 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4480 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4482 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4484 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4486 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4488 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4490 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4495 (define_insn "udivmodtidi3"
4496 [(set (match_operand:TI 0 "register_operand" "=d,d")
4501 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4503 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4507 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4512 [(set_attr "op_type" "RRE,RXY")
4513 (set_attr "type" "idiv")])
4516 ; divmodsi4 instruction pattern(s).
4519 (define_expand "divmodsi4"
4520 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4521 (div:SI (match_operand:SI 1 "general_operand" "")
4522 (match_operand:SI 2 "nonimmediate_operand" "")))
4523 (set (match_operand:SI 3 "general_operand" "")
4524 (mod:SI (match_dup 1) (match_dup 2)))])
4525 (clobber (match_dup 4))]
4528 rtx insn, div_equal, mod_equal, equal;
4530 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4531 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4532 equal = gen_rtx_IOR (DImode,
4533 gen_rtx_ASHIFT (DImode,
4534 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4536 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4538 operands[4] = gen_reg_rtx(DImode);
4539 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4540 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4542 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4544 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4546 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4548 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4550 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4555 (define_insn "divmoddisi3"
4556 [(set (match_operand:DI 0 "register_operand" "=d,d")
4561 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4563 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4567 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4572 [(set_attr "op_type" "RR,RX")
4573 (set_attr "type" "idiv")])
4576 ; udivsi3 and umodsi3 instruction pattern(s).
4579 (define_expand "udivmodsi4"
4580 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4581 (udiv:SI (match_operand:SI 1 "general_operand" "")
4582 (match_operand:SI 2 "nonimmediate_operand" "")))
4583 (set (match_operand:SI 3 "general_operand" "")
4584 (umod:SI (match_dup 1) (match_dup 2)))])
4585 (clobber (match_dup 4))]
4586 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4588 rtx insn, div_equal, mod_equal, equal;
4590 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4591 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4592 equal = gen_rtx_IOR (DImode,
4593 gen_rtx_ASHIFT (DImode,
4594 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4596 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4598 operands[4] = gen_reg_rtx(DImode);
4599 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4600 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4601 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4602 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4604 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4606 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4608 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4610 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4612 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4617 (define_insn "udivmoddisi3"
4618 [(set (match_operand:DI 0 "register_operand" "=d,d")
4623 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4625 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4629 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4630 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4634 [(set_attr "op_type" "RRE,RXY")
4635 (set_attr "type" "idiv")])
4637 (define_expand "udivsi3"
4638 [(set (match_operand:SI 0 "register_operand" "=d")
4639 (udiv:SI (match_operand:SI 1 "general_operand" "")
4640 (match_operand:SI 2 "general_operand" "")))
4641 (clobber (match_dup 3))]
4642 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4644 rtx insn, udiv_equal, umod_equal, equal;
4646 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4647 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4648 equal = gen_rtx_IOR (DImode,
4649 gen_rtx_ASHIFT (DImode,
4650 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4652 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4654 operands[3] = gen_reg_rtx (DImode);
4656 if (CONSTANT_P (operands[2]))
4658 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4660 rtx label1 = gen_label_rtx ();
4662 operands[1] = make_safe_from (operands[1], operands[0]);
4663 emit_move_insn (operands[0], const0_rtx);
4664 emit_insn (gen_cmpsi (operands[1], operands[2]));
4665 emit_jump_insn (gen_bltu (label1));
4666 emit_move_insn (operands[0], const1_rtx);
4667 emit_label (label1);
4671 operands[2] = force_reg (SImode, operands[2]);
4672 operands[2] = make_safe_from (operands[2], operands[0]);
4674 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4675 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4678 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4680 insn = emit_move_insn (operands[0],
4681 gen_lowpart (SImode, operands[3]));
4683 gen_rtx_EXPR_LIST (REG_EQUAL,
4684 udiv_equal, REG_NOTES (insn));
4689 rtx label1 = gen_label_rtx ();
4690 rtx label2 = gen_label_rtx ();
4691 rtx label3 = gen_label_rtx ();
4693 operands[1] = force_reg (SImode, operands[1]);
4694 operands[1] = make_safe_from (operands[1], operands[0]);
4695 operands[2] = force_reg (SImode, operands[2]);
4696 operands[2] = make_safe_from (operands[2], operands[0]);
4698 emit_move_insn (operands[0], const0_rtx);
4699 emit_insn (gen_cmpsi (operands[2], operands[1]));
4700 emit_jump_insn (gen_bgtu (label3));
4701 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4702 emit_jump_insn (gen_blt (label2));
4703 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4704 emit_jump_insn (gen_beq (label1));
4705 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4706 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4709 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4711 insn = emit_move_insn (operands[0],
4712 gen_lowpart (SImode, operands[3]));
4714 gen_rtx_EXPR_LIST (REG_EQUAL,
4715 udiv_equal, REG_NOTES (insn));
4717 emit_label (label1);
4718 emit_move_insn (operands[0], operands[1]);
4720 emit_label (label2);
4721 emit_move_insn (operands[0], const1_rtx);
4722 emit_label (label3);
4724 emit_move_insn (operands[0], operands[0]);
4728 (define_expand "umodsi3"
4729 [(set (match_operand:SI 0 "register_operand" "=d")
4730 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4731 (match_operand:SI 2 "nonimmediate_operand" "")))
4732 (clobber (match_dup 3))]
4733 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4735 rtx insn, udiv_equal, umod_equal, equal;
4737 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4738 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4739 equal = gen_rtx_IOR (DImode,
4740 gen_rtx_ASHIFT (DImode,
4741 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4743 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4745 operands[3] = gen_reg_rtx (DImode);
4747 if (CONSTANT_P (operands[2]))
4749 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4751 rtx label1 = gen_label_rtx ();
4753 operands[1] = make_safe_from (operands[1], operands[0]);
4754 emit_move_insn (operands[0], operands[1]);
4755 emit_insn (gen_cmpsi (operands[0], operands[2]));
4756 emit_jump_insn (gen_bltu (label1));
4757 emit_insn (gen_abssi2 (operands[0], operands[2]));
4758 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4759 emit_label (label1);
4763 operands[2] = force_reg (SImode, operands[2]);
4764 operands[2] = make_safe_from (operands[2], operands[0]);
4766 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4767 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4770 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4772 insn = emit_move_insn (operands[0],
4773 gen_highpart (SImode, operands[3]));
4775 gen_rtx_EXPR_LIST (REG_EQUAL,
4776 umod_equal, REG_NOTES (insn));
4781 rtx label1 = gen_label_rtx ();
4782 rtx label2 = gen_label_rtx ();
4783 rtx label3 = gen_label_rtx ();
4785 operands[1] = force_reg (SImode, operands[1]);
4786 operands[1] = make_safe_from (operands[1], operands[0]);
4787 operands[2] = force_reg (SImode, operands[2]);
4788 operands[2] = make_safe_from (operands[2], operands[0]);
4790 emit_move_insn(operands[0], operands[1]);
4791 emit_insn (gen_cmpsi (operands[2], operands[1]));
4792 emit_jump_insn (gen_bgtu (label3));
4793 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4794 emit_jump_insn (gen_blt (label2));
4795 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4796 emit_jump_insn (gen_beq (label1));
4797 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4798 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4801 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4803 insn = emit_move_insn (operands[0],
4804 gen_highpart (SImode, operands[3]));
4806 gen_rtx_EXPR_LIST (REG_EQUAL,
4807 umod_equal, REG_NOTES (insn));
4809 emit_label (label1);
4810 emit_move_insn (operands[0], const0_rtx);
4812 emit_label (label2);
4813 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4814 emit_label (label3);
4820 ; div(df|sf)3 instruction pattern(s).
4823 (define_expand "div<mode>3"
4824 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4825 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4826 (match_operand:FPR 2 "general_operand" "f,R")))]
4830 (define_insn "*div<mode>3"
4831 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4832 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4833 (match_operand:FPR 2 "general_operand" "f,R")))]
4834 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4838 [(set_attr "op_type" "RRE,RXE")
4839 (set_attr "type" "fdiv<mode>")])
4841 (define_insn "*div<mode>3_ibm"
4842 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4843 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4844 (match_operand:FPR 2 "general_operand" "f,R")))]
4845 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4849 [(set_attr "op_type" "RR,RX")
4850 (set_attr "type" "fdiv<mode>")])
4854 ;;- And instructions.
4857 (define_expand "and<mode>3"
4858 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4859 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4860 (match_operand:INT 2 "general_operand" "")))
4861 (clobber (reg:CC CC_REGNUM))]
4863 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4866 ; anddi3 instruction pattern(s).
4869 (define_insn "*anddi3_cc"
4870 [(set (reg CC_REGNUM)
4871 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4872 (match_operand:DI 2 "general_operand" "d,m"))
4874 (set (match_operand:DI 0 "register_operand" "=d,d")
4875 (and:DI (match_dup 1) (match_dup 2)))]
4876 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4880 [(set_attr "op_type" "RRE,RXY")])
4882 (define_insn "*anddi3_cconly"
4883 [(set (reg CC_REGNUM)
4884 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4885 (match_operand:DI 2 "general_operand" "d,m"))
4887 (clobber (match_scratch:DI 0 "=d,d"))]
4888 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4889 /* Do not steal TM patterns. */
4890 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4894 [(set_attr "op_type" "RRE,RXY")])
4896 (define_insn "*anddi3_extimm"
4897 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
4898 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4899 "%d,o,0,0,0,0,0,0,0,0,0,0")
4900 (match_operand:DI 2 "general_operand"
4901 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
4902 (clobber (reg:CC CC_REGNUM))]
4903 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4917 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
4919 (define_insn "*anddi3"
4920 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4921 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4922 "%d,o,0,0,0,0,0,0,0,0")
4923 (match_operand:DI 2 "general_operand"
4924 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4925 (clobber (reg:CC CC_REGNUM))]
4926 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4938 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4941 [(set (match_operand:DI 0 "s_operand" "")
4942 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4943 (clobber (reg:CC CC_REGNUM))]
4946 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4947 (clobber (reg:CC CC_REGNUM))])]
4948 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4952 ; andsi3 instruction pattern(s).
4955 (define_insn "*andsi3_cc"
4956 [(set (reg CC_REGNUM)
4957 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4958 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4960 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4961 (and:SI (match_dup 1) (match_dup 2)))]
4962 "s390_match_ccmode(insn, CCTmode)"
4968 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4970 (define_insn "*andsi3_cconly"
4971 [(set (reg CC_REGNUM)
4972 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4973 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4975 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
4976 "s390_match_ccmode(insn, CCTmode)
4977 /* Do not steal TM patterns. */
4978 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4984 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4986 (define_insn "*andsi3_zarch"
4987 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4988 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4989 "%d,o,0,0,0,0,0,0,0,0")
4990 (match_operand:SI 2 "general_operand"
4991 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
4992 (clobber (reg:CC CC_REGNUM))]
4993 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5005 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5007 (define_insn "*andsi3_esa"
5008 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5009 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5010 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5011 (clobber (reg:CC CC_REGNUM))]
5012 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5018 [(set_attr "op_type" "RR,RX,SI,SS")])
5021 [(set (match_operand:SI 0 "s_operand" "")
5022 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5023 (clobber (reg:CC CC_REGNUM))]
5026 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5027 (clobber (reg:CC CC_REGNUM))])]
5028 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5031 ; andhi3 instruction pattern(s).
5034 (define_insn "*andhi3_zarch"
5035 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5036 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5037 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5038 (clobber (reg:CC CC_REGNUM))]
5039 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5045 [(set_attr "op_type" "RR,RI,SI,SS")])
5047 (define_insn "*andhi3_esa"
5048 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5049 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5050 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5051 (clobber (reg:CC CC_REGNUM))]
5052 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5057 [(set_attr "op_type" "RR,SI,SS")])
5060 [(set (match_operand:HI 0 "s_operand" "")
5061 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5062 (clobber (reg:CC CC_REGNUM))]
5065 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5066 (clobber (reg:CC CC_REGNUM))])]
5067 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5070 ; andqi3 instruction pattern(s).
5073 (define_insn "*andqi3_zarch"
5074 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5075 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5076 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5077 (clobber (reg:CC CC_REGNUM))]
5078 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5085 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5087 (define_insn "*andqi3_esa"
5088 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5089 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5090 (match_operand:QI 2 "general_operand" "d,n,Q")))
5091 (clobber (reg:CC CC_REGNUM))]
5092 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5097 [(set_attr "op_type" "RR,SI,SS")])
5100 ; Block and (NC) patterns.
5104 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5105 (and:BLK (match_dup 0)
5106 (match_operand:BLK 1 "memory_operand" "Q")))
5107 (use (match_operand 2 "const_int_operand" "n"))
5108 (clobber (reg:CC CC_REGNUM))]
5109 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5110 "nc\t%O0(%2,%R0),%S1"
5111 [(set_attr "op_type" "SS")])
5114 [(set (match_operand 0 "memory_operand" "")
5116 (match_operand 1 "memory_operand" "")))
5117 (clobber (reg:CC CC_REGNUM))]
5119 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5120 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5122 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5124 (clobber (reg:CC CC_REGNUM))])]
5126 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5127 operands[0] = adjust_address (operands[0], BLKmode, 0);
5128 operands[1] = adjust_address (operands[1], BLKmode, 0);
5133 [(set (match_operand:BLK 0 "memory_operand" "")
5134 (and:BLK (match_dup 0)
5135 (match_operand:BLK 1 "memory_operand" "")))
5136 (use (match_operand 2 "const_int_operand" ""))
5137 (clobber (reg:CC CC_REGNUM))])
5139 [(set (match_operand:BLK 3 "memory_operand" "")
5140 (and:BLK (match_dup 3)
5141 (match_operand:BLK 4 "memory_operand" "")))
5142 (use (match_operand 5 "const_int_operand" ""))
5143 (clobber (reg:CC CC_REGNUM))])]
5144 "s390_offset_p (operands[0], operands[3], operands[2])
5145 && s390_offset_p (operands[1], operands[4], operands[2])
5146 && !s390_overlap_p (operands[0], operands[1],
5147 INTVAL (operands[2]) + INTVAL (operands[5]))
5148 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5150 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5152 (clobber (reg:CC CC_REGNUM))])]
5153 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5154 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5155 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5159 ;;- Bit set (inclusive or) instructions.
5162 (define_expand "ior<mode>3"
5163 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5164 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5165 (match_operand:INT 2 "general_operand" "")))
5166 (clobber (reg:CC CC_REGNUM))]
5168 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5171 ; iordi3 instruction pattern(s).
5174 (define_insn "*iordi3_cc"
5175 [(set (reg CC_REGNUM)
5176 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5177 (match_operand:DI 2 "general_operand" "d,m"))
5179 (set (match_operand:DI 0 "register_operand" "=d,d")
5180 (ior:DI (match_dup 1) (match_dup 2)))]
5181 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5185 [(set_attr "op_type" "RRE,RXY")])
5187 (define_insn "*iordi3_cconly"
5188 [(set (reg CC_REGNUM)
5189 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5190 (match_operand:DI 2 "general_operand" "d,m"))
5192 (clobber (match_scratch:DI 0 "=d,d"))]
5193 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5197 [(set_attr "op_type" "RRE,RXY")])
5199 (define_insn "*iordi3_extimm"
5200 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5201 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5202 (match_operand:DI 2 "general_operand"
5203 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5204 (clobber (reg:CC CC_REGNUM))]
5205 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5217 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5219 (define_insn "*iordi3"
5220 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5221 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5222 (match_operand:DI 2 "general_operand"
5223 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5224 (clobber (reg:CC CC_REGNUM))]
5225 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5235 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5238 [(set (match_operand:DI 0 "s_operand" "")
5239 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5240 (clobber (reg:CC CC_REGNUM))]
5243 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5244 (clobber (reg:CC CC_REGNUM))])]
5245 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5248 ; iorsi3 instruction pattern(s).
5251 (define_insn "*iorsi3_cc"
5252 [(set (reg CC_REGNUM)
5253 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5254 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5256 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5257 (ior:SI (match_dup 1) (match_dup 2)))]
5258 "s390_match_ccmode(insn, CCTmode)"
5264 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5266 (define_insn "*iorsi3_cconly"
5267 [(set (reg CC_REGNUM)
5268 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5269 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5271 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5272 "s390_match_ccmode(insn, CCTmode)"
5278 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5280 (define_insn "*iorsi3_zarch"
5281 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5282 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5283 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5284 (clobber (reg:CC CC_REGNUM))]
5285 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5295 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5297 (define_insn "*iorsi3_esa"
5298 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5299 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5300 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5301 (clobber (reg:CC CC_REGNUM))]
5302 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5308 [(set_attr "op_type" "RR,RX,SI,SS")])
5311 [(set (match_operand:SI 0 "s_operand" "")
5312 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5313 (clobber (reg:CC CC_REGNUM))]
5316 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5317 (clobber (reg:CC CC_REGNUM))])]
5318 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5321 ; iorhi3 instruction pattern(s).
5324 (define_insn "*iorhi3_zarch"
5325 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5326 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5327 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5328 (clobber (reg:CC CC_REGNUM))]
5329 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5335 [(set_attr "op_type" "RR,RI,SI,SS")])
5337 (define_insn "*iorhi3_esa"
5338 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5339 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5340 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5341 (clobber (reg:CC CC_REGNUM))]
5342 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5347 [(set_attr "op_type" "RR,SI,SS")])
5350 [(set (match_operand:HI 0 "s_operand" "")
5351 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5352 (clobber (reg:CC CC_REGNUM))]
5355 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5356 (clobber (reg:CC CC_REGNUM))])]
5357 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5360 ; iorqi3 instruction pattern(s).
5363 (define_insn "*iorqi3_zarch"
5364 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5365 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5366 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5367 (clobber (reg:CC CC_REGNUM))]
5368 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5375 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5377 (define_insn "*iorqi3_esa"
5378 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5379 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5380 (match_operand:QI 2 "general_operand" "d,n,Q")))
5381 (clobber (reg:CC CC_REGNUM))]
5382 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5387 [(set_attr "op_type" "RR,SI,SS")])
5390 ; Block inclusive or (OC) patterns.
5394 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5395 (ior:BLK (match_dup 0)
5396 (match_operand:BLK 1 "memory_operand" "Q")))
5397 (use (match_operand 2 "const_int_operand" "n"))
5398 (clobber (reg:CC CC_REGNUM))]
5399 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5400 "oc\t%O0(%2,%R0),%S1"
5401 [(set_attr "op_type" "SS")])
5404 [(set (match_operand 0 "memory_operand" "")
5406 (match_operand 1 "memory_operand" "")))
5407 (clobber (reg:CC CC_REGNUM))]
5409 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5410 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5412 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5414 (clobber (reg:CC CC_REGNUM))])]
5416 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5417 operands[0] = adjust_address (operands[0], BLKmode, 0);
5418 operands[1] = adjust_address (operands[1], BLKmode, 0);
5423 [(set (match_operand:BLK 0 "memory_operand" "")
5424 (ior:BLK (match_dup 0)
5425 (match_operand:BLK 1 "memory_operand" "")))
5426 (use (match_operand 2 "const_int_operand" ""))
5427 (clobber (reg:CC CC_REGNUM))])
5429 [(set (match_operand:BLK 3 "memory_operand" "")
5430 (ior:BLK (match_dup 3)
5431 (match_operand:BLK 4 "memory_operand" "")))
5432 (use (match_operand 5 "const_int_operand" ""))
5433 (clobber (reg:CC CC_REGNUM))])]
5434 "s390_offset_p (operands[0], operands[3], operands[2])
5435 && s390_offset_p (operands[1], operands[4], operands[2])
5436 && !s390_overlap_p (operands[0], operands[1],
5437 INTVAL (operands[2]) + INTVAL (operands[5]))
5438 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5440 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5442 (clobber (reg:CC CC_REGNUM))])]
5443 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5444 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5445 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5449 ;;- Xor instructions.
5452 (define_expand "xor<mode>3"
5453 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5454 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5455 (match_operand:INT 2 "general_operand" "")))
5456 (clobber (reg:CC CC_REGNUM))]
5458 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5461 ; xordi3 instruction pattern(s).
5464 (define_insn "*xordi3_cc"
5465 [(set (reg CC_REGNUM)
5466 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5467 (match_operand:DI 2 "general_operand" "d,m"))
5469 (set (match_operand:DI 0 "register_operand" "=d,d")
5470 (xor:DI (match_dup 1) (match_dup 2)))]
5471 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5475 [(set_attr "op_type" "RRE,RXY")])
5477 (define_insn "*xordi3_cconly"
5478 [(set (reg CC_REGNUM)
5479 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5480 (match_operand:DI 2 "general_operand" "d,m"))
5482 (clobber (match_scratch:DI 0 "=d,d"))]
5483 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5487 [(set_attr "op_type" "RRE,RXY")])
5489 (define_insn "*xordi3_extimm"
5490 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5491 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5492 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5493 (clobber (reg:CC CC_REGNUM))]
5494 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5502 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5504 (define_insn "*xordi3"
5505 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5506 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5507 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5508 (clobber (reg:CC CC_REGNUM))]
5509 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5515 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5518 [(set (match_operand:DI 0 "s_operand" "")
5519 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5520 (clobber (reg:CC CC_REGNUM))]
5523 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5524 (clobber (reg:CC CC_REGNUM))])]
5525 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5528 ; xorsi3 instruction pattern(s).
5531 (define_insn "*xorsi3_cc"
5532 [(set (reg CC_REGNUM)
5533 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5534 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5536 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5537 (xor:SI (match_dup 1) (match_dup 2)))]
5538 "s390_match_ccmode(insn, CCTmode)"
5544 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5546 (define_insn "*xorsi3_cconly"
5547 [(set (reg CC_REGNUM)
5548 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5549 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5551 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5552 "s390_match_ccmode(insn, CCTmode)"
5558 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5560 (define_insn "*xorsi3"
5561 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5562 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5563 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5564 (clobber (reg:CC CC_REGNUM))]
5565 "s390_logical_operator_ok_p (operands)"
5573 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5576 [(set (match_operand:SI 0 "s_operand" "")
5577 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5578 (clobber (reg:CC CC_REGNUM))]
5581 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5582 (clobber (reg:CC CC_REGNUM))])]
5583 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5586 ; xorhi3 instruction pattern(s).
5589 (define_insn "*xorhi3"
5590 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5591 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5592 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5593 (clobber (reg:CC CC_REGNUM))]
5594 "s390_logical_operator_ok_p (operands)"
5600 [(set_attr "op_type" "RIL,RR,SI,SS")])
5603 [(set (match_operand:HI 0 "s_operand" "")
5604 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5605 (clobber (reg:CC CC_REGNUM))]
5608 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5609 (clobber (reg:CC CC_REGNUM))])]
5610 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5613 ; xorqi3 instruction pattern(s).
5616 (define_insn "*xorqi3"
5617 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5618 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5619 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5620 (clobber (reg:CC CC_REGNUM))]
5621 "s390_logical_operator_ok_p (operands)"
5628 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5631 ; Block exclusive or (XC) patterns.
5635 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5636 (xor:BLK (match_dup 0)
5637 (match_operand:BLK 1 "memory_operand" "Q")))
5638 (use (match_operand 2 "const_int_operand" "n"))
5639 (clobber (reg:CC CC_REGNUM))]
5640 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5641 "xc\t%O0(%2,%R0),%S1"
5642 [(set_attr "op_type" "SS")])
5645 [(set (match_operand 0 "memory_operand" "")
5647 (match_operand 1 "memory_operand" "")))
5648 (clobber (reg:CC CC_REGNUM))]
5650 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5651 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5653 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5655 (clobber (reg:CC CC_REGNUM))])]
5657 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5658 operands[0] = adjust_address (operands[0], BLKmode, 0);
5659 operands[1] = adjust_address (operands[1], BLKmode, 0);
5664 [(set (match_operand:BLK 0 "memory_operand" "")
5665 (xor:BLK (match_dup 0)
5666 (match_operand:BLK 1 "memory_operand" "")))
5667 (use (match_operand 2 "const_int_operand" ""))
5668 (clobber (reg:CC CC_REGNUM))])
5670 [(set (match_operand:BLK 3 "memory_operand" "")
5671 (xor:BLK (match_dup 3)
5672 (match_operand:BLK 4 "memory_operand" "")))
5673 (use (match_operand 5 "const_int_operand" ""))
5674 (clobber (reg:CC CC_REGNUM))])]
5675 "s390_offset_p (operands[0], operands[3], operands[2])
5676 && s390_offset_p (operands[1], operands[4], operands[2])
5677 && !s390_overlap_p (operands[0], operands[1],
5678 INTVAL (operands[2]) + INTVAL (operands[5]))
5679 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5681 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5683 (clobber (reg:CC CC_REGNUM))])]
5684 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5685 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5686 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5689 ; Block xor (XC) patterns with src == dest.
5692 (define_insn "*xc_zero"
5693 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5695 (use (match_operand 1 "const_int_operand" "n"))
5696 (clobber (reg:CC CC_REGNUM))]
5697 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5698 "xc\t%O0(%1,%R0),%S0"
5699 [(set_attr "op_type" "SS")])
5703 [(set (match_operand:BLK 0 "memory_operand" "")
5705 (use (match_operand 1 "const_int_operand" ""))
5706 (clobber (reg:CC CC_REGNUM))])
5708 [(set (match_operand:BLK 2 "memory_operand" "")
5710 (use (match_operand 3 "const_int_operand" ""))
5711 (clobber (reg:CC CC_REGNUM))])]
5712 "s390_offset_p (operands[0], operands[2], operands[1])
5713 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5715 [(set (match_dup 4) (const_int 0))
5717 (clobber (reg:CC CC_REGNUM))])]
5718 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5719 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5723 ;;- Negate instructions.
5727 ; neg(di|si)2 instruction pattern(s).
5730 (define_expand "neg<mode>2"
5732 [(set (match_operand:DSI 0 "register_operand" "=d")
5733 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5734 (clobber (reg:CC CC_REGNUM))])]
5738 (define_insn "*negdi2_sign_cc"
5739 [(set (reg CC_REGNUM)
5740 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5741 (match_operand:SI 1 "register_operand" "d") 0)
5742 (const_int 32)) (const_int 32)))
5744 (set (match_operand:DI 0 "register_operand" "=d")
5745 (neg:DI (sign_extend:DI (match_dup 1))))]
5746 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5748 [(set_attr "op_type" "RRE")])
5750 (define_insn "*negdi2_sign"
5751 [(set (match_operand:DI 0 "register_operand" "=d")
5752 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5753 (clobber (reg:CC CC_REGNUM))]
5756 [(set_attr "op_type" "RRE")])
5758 (define_insn "*neg<mode>2_cc"
5759 [(set (reg CC_REGNUM)
5760 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5762 (set (match_operand:GPR 0 "register_operand" "=d")
5763 (neg:GPR (match_dup 1)))]
5764 "s390_match_ccmode (insn, CCAmode)"
5766 [(set_attr "op_type" "RR<E>")])
5768 (define_insn "*neg<mode>2_cconly"
5769 [(set (reg CC_REGNUM)
5770 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5772 (clobber (match_scratch:GPR 0 "=d"))]
5773 "s390_match_ccmode (insn, CCAmode)"
5775 [(set_attr "op_type" "RR<E>")])
5777 (define_insn "*neg<mode>2"
5778 [(set (match_operand:GPR 0 "register_operand" "=d")
5779 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5780 (clobber (reg:CC CC_REGNUM))]
5783 [(set_attr "op_type" "RR<E>")])
5785 (define_insn_and_split "*negdi2_31"
5786 [(set (match_operand:DI 0 "register_operand" "=d")
5787 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5788 (clobber (reg:CC CC_REGNUM))]
5791 "&& reload_completed"
5793 [(set (match_dup 2) (neg:SI (match_dup 3)))
5794 (clobber (reg:CC CC_REGNUM))])
5796 [(set (reg:CCAP CC_REGNUM)
5797 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5798 (set (match_dup 4) (neg:SI (match_dup 5)))])
5800 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5802 (label_ref (match_dup 6))))
5804 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5805 (clobber (reg:CC CC_REGNUM))])
5807 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5808 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5809 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5810 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5811 operands[6] = gen_label_rtx ();")
5814 ; neg(df|sf)2 instruction pattern(s).
5817 (define_expand "neg<mode>2"
5819 [(set (match_operand:FPR 0 "register_operand" "=f")
5820 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5821 (clobber (reg:CC CC_REGNUM))])]
5825 (define_insn "*neg<mode>2_cc"
5826 [(set (reg CC_REGNUM)
5827 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5828 (match_operand:FPR 2 "const0_operand" "")))
5829 (set (match_operand:FPR 0 "register_operand" "=f")
5830 (neg:FPR (match_dup 1)))]
5831 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5833 [(set_attr "op_type" "RRE")
5834 (set_attr "type" "fsimp<mode>")])
5836 (define_insn "*neg<mode>2_cconly"
5837 [(set (reg CC_REGNUM)
5838 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5839 (match_operand:FPR 2 "const0_operand" "")))
5840 (clobber (match_scratch:FPR 0 "=f"))]
5841 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5843 [(set_attr "op_type" "RRE")
5844 (set_attr "type" "fsimp<mode>")])
5846 (define_insn "*neg<mode>2"
5847 [(set (match_operand:FPR 0 "register_operand" "=f")
5848 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5849 (clobber (reg:CC CC_REGNUM))]
5850 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5852 [(set_attr "op_type" "RRE")
5853 (set_attr "type" "fsimp<mode>")])
5855 (define_insn "*neg<mode>2_ibm"
5856 [(set (match_operand:FPR 0 "register_operand" "=f")
5857 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5858 (clobber (reg:CC CC_REGNUM))]
5859 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5861 [(set_attr "op_type" "RR")
5862 (set_attr "type" "fsimp<mode>")])
5866 ;;- Absolute value instructions.
5870 ; abs(di|si)2 instruction pattern(s).
5873 (define_insn "*absdi2_sign_cc"
5874 [(set (reg CC_REGNUM)
5875 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5876 (match_operand:SI 1 "register_operand" "d") 0)
5877 (const_int 32)) (const_int 32)))
5879 (set (match_operand:DI 0 "register_operand" "=d")
5880 (abs:DI (sign_extend:DI (match_dup 1))))]
5881 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5883 [(set_attr "op_type" "RRE")])
5885 (define_insn "*absdi2_sign"
5886 [(set (match_operand:DI 0 "register_operand" "=d")
5887 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5888 (clobber (reg:CC CC_REGNUM))]
5891 [(set_attr "op_type" "RRE")])
5893 (define_insn "*abs<mode>2_cc"
5894 [(set (reg CC_REGNUM)
5895 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5897 (set (match_operand:GPR 0 "register_operand" "=d")
5898 (abs:GPR (match_dup 1)))]
5899 "s390_match_ccmode (insn, CCAmode)"
5901 [(set_attr "op_type" "RR<E>")])
5903 (define_insn "*abs<mode>2_cconly"
5904 [(set (reg CC_REGNUM)
5905 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5907 (clobber (match_scratch:GPR 0 "=d"))]
5908 "s390_match_ccmode (insn, CCAmode)"
5910 [(set_attr "op_type" "RR<E>")])
5912 (define_insn "abs<mode>2"
5913 [(set (match_operand:GPR 0 "register_operand" "=d")
5914 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5915 (clobber (reg:CC CC_REGNUM))]
5918 [(set_attr "op_type" "RR<E>")])
5921 ; abs(df|sf)2 instruction pattern(s).
5924 (define_expand "abs<mode>2"
5926 [(set (match_operand:FPR 0 "register_operand" "=f")
5927 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5928 (clobber (reg:CC CC_REGNUM))])]
5932 (define_insn "*abs<mode>2_cc"
5933 [(set (reg CC_REGNUM)
5934 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5935 (match_operand:FPR 2 "const0_operand" "")))
5936 (set (match_operand:FPR 0 "register_operand" "=f")
5937 (abs:FPR (match_dup 1)))]
5938 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5940 [(set_attr "op_type" "RRE")
5941 (set_attr "type" "fsimp<mode>")])
5943 (define_insn "*abs<mode>2_cconly"
5944 [(set (reg CC_REGNUM)
5945 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5946 (match_operand:FPR 2 "const0_operand" "")))
5947 (clobber (match_scratch:FPR 0 "=f"))]
5948 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5950 [(set_attr "op_type" "RRE")
5951 (set_attr "type" "fsimp<mode>")])
5953 (define_insn "*abs<mode>2"
5954 [(set (match_operand:FPR 0 "register_operand" "=f")
5955 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5956 (clobber (reg:CC CC_REGNUM))]
5957 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5959 [(set_attr "op_type" "RRE")
5960 (set_attr "type" "fsimp<mode>")])
5962 (define_insn "*abs<mode>2_ibm"
5963 [(set (match_operand:FPR 0 "register_operand" "=f")
5964 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5965 (clobber (reg:CC CC_REGNUM))]
5966 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5968 [(set_attr "op_type" "RR")
5969 (set_attr "type" "fsimp<mode>")])
5972 ;;- Negated absolute value instructions
5979 (define_insn "*negabsdi2_sign_cc"
5980 [(set (reg CC_REGNUM)
5981 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5982 (match_operand:SI 1 "register_operand" "d") 0)
5983 (const_int 32)) (const_int 32))))
5985 (set (match_operand:DI 0 "register_operand" "=d")
5986 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5987 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5989 [(set_attr "op_type" "RRE")])
5991 (define_insn "*negabsdi2_sign"
5992 [(set (match_operand:DI 0 "register_operand" "=d")
5993 (neg:DI (abs:DI (sign_extend:DI
5994 (match_operand:SI 1 "register_operand" "d")))))
5995 (clobber (reg:CC CC_REGNUM))]
5998 [(set_attr "op_type" "RRE")])
6000 (define_insn "*negabs<mode>2_cc"
6001 [(set (reg CC_REGNUM)
6002 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6004 (set (match_operand:GPR 0 "register_operand" "=d")
6005 (neg:GPR (abs:GPR (match_dup 1))))]
6006 "s390_match_ccmode (insn, CCAmode)"
6008 [(set_attr "op_type" "RR<E>")])
6010 (define_insn "*negabs<mode>2_cconly"
6011 [(set (reg CC_REGNUM)
6012 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6014 (clobber (match_scratch:GPR 0 "=d"))]
6015 "s390_match_ccmode (insn, CCAmode)"
6017 [(set_attr "op_type" "RR<E>")])
6019 (define_insn "*negabs<mode>2"
6020 [(set (match_operand:GPR 0 "register_operand" "=d")
6021 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6022 (clobber (reg:CC CC_REGNUM))]
6025 [(set_attr "op_type" "RR<E>")])
6031 (define_insn "*negabs<mode>2_cc"
6032 [(set (reg CC_REGNUM)
6033 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6034 (match_operand:FPR 2 "const0_operand" "")))
6035 (set (match_operand:FPR 0 "register_operand" "=f")
6036 (neg:FPR (abs:FPR (match_dup 1))))]
6037 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6039 [(set_attr "op_type" "RRE")
6040 (set_attr "type" "fsimp<mode>")])
6042 (define_insn "*negabs<mode>2_cconly"
6043 [(set (reg CC_REGNUM)
6044 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6045 (match_operand:FPR 2 "const0_operand" "")))
6046 (clobber (match_scratch:FPR 0 "=f"))]
6047 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6049 [(set_attr "op_type" "RRE")
6050 (set_attr "type" "fsimp<mode>")])
6052 (define_insn "*negabs<mode>2"
6053 [(set (match_operand:FPR 0 "register_operand" "=f")
6054 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6055 (clobber (reg:CC CC_REGNUM))]
6056 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6058 [(set_attr "op_type" "RRE")
6059 (set_attr "type" "fsimp<mode>")])
6062 ;;- Square root instructions.
6066 ; sqrt(df|sf)2 instruction pattern(s).
6069 (define_insn "sqrt<mode>2"
6070 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6071 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6072 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6076 [(set_attr "op_type" "RRE,RXE")
6077 (set_attr "type" "fsqrt<mode>")])
6081 ;;- One complement instructions.
6085 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6088 (define_expand "one_cmpl<mode>2"
6090 [(set (match_operand:INT 0 "register_operand" "")
6091 (xor:INT (match_operand:INT 1 "register_operand" "")
6093 (clobber (reg:CC CC_REGNUM))])]
6099 ;; Find leftmost bit instructions.
6102 (define_expand "clzdi2"
6103 [(set (match_operand:DI 0 "register_operand" "=d")
6104 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6105 "TARGET_EXTIMM && TARGET_64BIT"
6107 rtx insn, clz_equal;
6108 rtx wide_reg = gen_reg_rtx (TImode);
6109 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6111 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6113 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6115 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6117 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6122 (define_insn "clztidi2"
6123 [(set (match_operand:TI 0 "register_operand" "=d")
6127 (xor:DI (match_operand:DI 1 "register_operand" "d")
6128 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6129 (subreg:SI (clz:DI (match_dup 1)) 4))))
6132 (zero_extend:TI (clz:DI (match_dup 1)))))
6133 (clobber (reg:CC CC_REGNUM))]
6134 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6135 == (unsigned HOST_WIDE_INT) 1 << 63
6136 && TARGET_EXTIMM && TARGET_64BIT"
6138 [(set_attr "op_type" "RRE")])
6142 ;;- Rotate instructions.
6146 ; rotl(di|si)3 instruction pattern(s).
6149 (define_insn "rotl<mode>3"
6150 [(set (match_operand:GPR 0 "register_operand" "=d")
6151 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6152 (match_operand:SI 2 "shift_count_operand" "Y")))]
6155 [(set_attr "op_type" "RSE")
6156 (set_attr "atype" "reg")])
6160 ;;- Shift instructions.
6164 ; (ashl|lshr)di3 instruction pattern(s).
6167 (define_expand "<shift>di3"
6168 [(set (match_operand:DI 0 "register_operand" "")
6169 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6170 (match_operand:SI 2 "shift_count_operand" "")))]
6174 (define_insn "*<shift>di3_31"
6175 [(set (match_operand:DI 0 "register_operand" "=d")
6176 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6177 (match_operand:SI 2 "shift_count_operand" "Y")))]
6180 [(set_attr "op_type" "RS")
6181 (set_attr "atype" "reg")])
6183 (define_insn "*<shift>di3_64"
6184 [(set (match_operand:DI 0 "register_operand" "=d")
6185 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6186 (match_operand:SI 2 "shift_count_operand" "Y")))]
6188 "s<lr>lg\t%0,%1,%Y2"
6189 [(set_attr "op_type" "RSE")
6190 (set_attr "atype" "reg")])
6193 ; ashrdi3 instruction pattern(s).
6196 (define_expand "ashrdi3"
6198 [(set (match_operand:DI 0 "register_operand" "")
6199 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6200 (match_operand:SI 2 "shift_count_operand" "")))
6201 (clobber (reg:CC CC_REGNUM))])]
6205 (define_insn "*ashrdi3_cc_31"
6206 [(set (reg CC_REGNUM)
6207 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6208 (match_operand:SI 2 "shift_count_operand" "Y"))
6210 (set (match_operand:DI 0 "register_operand" "=d")
6211 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6212 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6214 [(set_attr "op_type" "RS")
6215 (set_attr "atype" "reg")])
6217 (define_insn "*ashrdi3_cconly_31"
6218 [(set (reg CC_REGNUM)
6219 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6220 (match_operand:SI 2 "shift_count_operand" "Y"))
6222 (clobber (match_scratch:DI 0 "=d"))]
6223 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6225 [(set_attr "op_type" "RS")
6226 (set_attr "atype" "reg")])
6228 (define_insn "*ashrdi3_31"
6229 [(set (match_operand:DI 0 "register_operand" "=d")
6230 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6231 (match_operand:SI 2 "shift_count_operand" "Y")))
6232 (clobber (reg:CC CC_REGNUM))]
6235 [(set_attr "op_type" "RS")
6236 (set_attr "atype" "reg")])
6238 (define_insn "*ashrdi3_cc_64"
6239 [(set (reg CC_REGNUM)
6240 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6241 (match_operand:SI 2 "shift_count_operand" "Y"))
6243 (set (match_operand:DI 0 "register_operand" "=d")
6244 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6245 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6247 [(set_attr "op_type" "RSE")
6248 (set_attr "atype" "reg")])
6250 (define_insn "*ashrdi3_cconly_64"
6251 [(set (reg CC_REGNUM)
6252 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6253 (match_operand:SI 2 "shift_count_operand" "Y"))
6255 (clobber (match_scratch:DI 0 "=d"))]
6256 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6258 [(set_attr "op_type" "RSE")
6259 (set_attr "atype" "reg")])
6261 (define_insn "*ashrdi3_64"
6262 [(set (match_operand:DI 0 "register_operand" "=d")
6263 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6264 (match_operand:SI 2 "shift_count_operand" "Y")))
6265 (clobber (reg:CC CC_REGNUM))]
6268 [(set_attr "op_type" "RSE")
6269 (set_attr "atype" "reg")])
6273 ; (ashl|lshr)si3 instruction pattern(s).
6276 (define_insn "<shift>si3"
6277 [(set (match_operand:SI 0 "register_operand" "=d")
6278 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6279 (match_operand:SI 2 "shift_count_operand" "Y")))]
6282 [(set_attr "op_type" "RS")
6283 (set_attr "atype" "reg")])
6286 ; ashrsi3 instruction pattern(s).
6289 (define_insn "*ashrsi3_cc"
6290 [(set (reg CC_REGNUM)
6291 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6292 (match_operand:SI 2 "shift_count_operand" "Y"))
6294 (set (match_operand:SI 0 "register_operand" "=d")
6295 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6296 "s390_match_ccmode(insn, CCSmode)"
6298 [(set_attr "op_type" "RS")
6299 (set_attr "atype" "reg")])
6302 (define_insn "*ashrsi3_cconly"
6303 [(set (reg CC_REGNUM)
6304 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6305 (match_operand:SI 2 "shift_count_operand" "Y"))
6307 (clobber (match_scratch:SI 0 "=d"))]
6308 "s390_match_ccmode(insn, CCSmode)"
6310 [(set_attr "op_type" "RS")
6311 (set_attr "atype" "reg")])
6313 (define_insn "ashrsi3"
6314 [(set (match_operand:SI 0 "register_operand" "=d")
6315 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6316 (match_operand:SI 2 "shift_count_operand" "Y")))
6317 (clobber (reg:CC CC_REGNUM))]
6320 [(set_attr "op_type" "RS")
6321 (set_attr "atype" "reg")])
6325 ;; Branch instruction patterns.
6328 (define_expand "b<code>"
6330 (if_then_else (COMPARE (match_operand 0 "" "")
6335 "s390_emit_jump (operands[0],
6336 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6340 ;;- Conditional jump instructions.
6343 (define_insn "*cjump_64"
6346 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6347 (label_ref (match_operand 0 "" ""))
6351 if (get_attr_length (insn) == 4)
6354 return "jg%C1\t%l0";
6356 [(set_attr "op_type" "RI")
6357 (set_attr "type" "branch")
6358 (set (attr "length")
6359 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6360 (const_int 4) (const_int 6)))])
6362 (define_insn "*cjump_31"
6365 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6366 (label_ref (match_operand 0 "" ""))
6370 gcc_assert (get_attr_length (insn) == 4);
6373 [(set_attr "op_type" "RI")
6374 (set_attr "type" "branch")
6375 (set (attr "length")
6376 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6377 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6378 (const_int 4) (const_int 6))
6379 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6380 (const_int 4) (const_int 8))))])
6382 (define_insn "*cjump_long"
6385 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6386 (match_operand 0 "address_operand" "U")
6390 if (get_attr_op_type (insn) == OP_TYPE_RR)
6395 [(set (attr "op_type")
6396 (if_then_else (match_operand 0 "register_operand" "")
6397 (const_string "RR") (const_string "RX")))
6398 (set_attr "type" "branch")
6399 (set_attr "atype" "agen")])
6403 ;;- Negated conditional jump instructions.
6406 (define_insn "*icjump_64"
6409 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6411 (label_ref (match_operand 0 "" ""))))]
6414 if (get_attr_length (insn) == 4)
6417 return "jg%D1\t%l0";
6419 [(set_attr "op_type" "RI")
6420 (set_attr "type" "branch")
6421 (set (attr "length")
6422 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6423 (const_int 4) (const_int 6)))])
6425 (define_insn "*icjump_31"
6428 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6430 (label_ref (match_operand 0 "" ""))))]
6433 gcc_assert (get_attr_length (insn) == 4);
6436 [(set_attr "op_type" "RI")
6437 (set_attr "type" "branch")
6438 (set (attr "length")
6439 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6440 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6441 (const_int 4) (const_int 6))
6442 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6443 (const_int 4) (const_int 8))))])
6445 (define_insn "*icjump_long"
6448 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6450 (match_operand 0 "address_operand" "U")))]
6453 if (get_attr_op_type (insn) == OP_TYPE_RR)
6458 [(set (attr "op_type")
6459 (if_then_else (match_operand 0 "register_operand" "")
6460 (const_string "RR") (const_string "RX")))
6461 (set_attr "type" "branch")
6462 (set_attr "atype" "agen")])
6465 ;;- Trap instructions.
6469 [(trap_if (const_int 1) (const_int 0))]
6472 [(set_attr "op_type" "RI")
6473 (set_attr "type" "branch")])
6475 (define_expand "conditional_trap"
6476 [(trap_if (match_operand 0 "comparison_operator" "")
6477 (match_operand 1 "general_operand" ""))]
6480 if (operands[1] != const0_rtx) FAIL;
6481 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6482 s390_compare_op0, s390_compare_op1);
6485 (define_insn "*trap"
6486 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6490 [(set_attr "op_type" "RI")
6491 (set_attr "type" "branch")])
6494 ;;- Loop instructions.
6496 ;; This is all complicated by the fact that since this is a jump insn
6497 ;; we must handle our own output reloads.
6499 (define_expand "doloop_end"
6500 [(use (match_operand 0 "" "")) ; loop pseudo
6501 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6502 (use (match_operand 2 "" "")) ; max iterations
6503 (use (match_operand 3 "" "")) ; loop level
6504 (use (match_operand 4 "" ""))] ; label
6507 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6508 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6509 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6510 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6511 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6512 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6519 (define_insn_and_split "doloop_si64"
6522 (ne (match_operand:SI 1 "register_operand" "d,d")
6524 (label_ref (match_operand 0 "" ""))
6526 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6527 (plus:SI (match_dup 1) (const_int -1)))
6528 (clobber (match_scratch:SI 3 "=X,&1"))
6529 (clobber (reg:CC CC_REGNUM))]
6532 if (which_alternative != 0)
6534 else if (get_attr_length (insn) == 4)
6535 return "brct\t%1,%l0";
6537 return "ahi\t%1,-1\;jgne\t%l0";
6539 "&& reload_completed
6540 && (! REG_P (operands[2])
6541 || ! rtx_equal_p (operands[1], operands[2]))"
6542 [(parallel [(set (reg:CCAN CC_REGNUM)
6543 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6545 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6546 (set (match_dup 2) (match_dup 3))
6547 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6548 (label_ref (match_dup 0))
6551 [(set_attr "op_type" "RI")
6552 (set_attr "type" "branch")
6553 (set (attr "length")
6554 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6555 (const_int 4) (const_int 10)))])
6557 (define_insn_and_split "doloop_si31"
6560 (ne (match_operand:SI 1 "register_operand" "d,d")
6562 (label_ref (match_operand 0 "" ""))
6564 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6565 (plus:SI (match_dup 1) (const_int -1)))
6566 (clobber (match_scratch:SI 3 "=X,&1"))
6567 (clobber (reg:CC CC_REGNUM))]
6570 if (which_alternative != 0)
6572 else if (get_attr_length (insn) == 4)
6573 return "brct\t%1,%l0";
6577 "&& reload_completed
6578 && (! REG_P (operands[2])
6579 || ! rtx_equal_p (operands[1], operands[2]))"
6580 [(parallel [(set (reg:CCAN CC_REGNUM)
6581 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6583 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6584 (set (match_dup 2) (match_dup 3))
6585 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6586 (label_ref (match_dup 0))
6589 [(set_attr "op_type" "RI")
6590 (set_attr "type" "branch")
6591 (set (attr "length")
6592 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6593 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6594 (const_int 4) (const_int 6))
6595 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6596 (const_int 4) (const_int 8))))])
6598 (define_insn "*doloop_si_long"
6601 (ne (match_operand:SI 1 "register_operand" "d,d")
6603 (match_operand 0 "address_operand" "U,U")
6605 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6606 (plus:SI (match_dup 1) (const_int -1)))
6607 (clobber (match_scratch:SI 3 "=X,&1"))
6608 (clobber (reg:CC CC_REGNUM))]
6611 if (get_attr_op_type (insn) == OP_TYPE_RR)
6612 return "bctr\t%1,%0";
6614 return "bct\t%1,%a0";
6616 [(set (attr "op_type")
6617 (if_then_else (match_operand 0 "register_operand" "")
6618 (const_string "RR") (const_string "RX")))
6619 (set_attr "type" "branch")
6620 (set_attr "atype" "agen")])
6622 (define_insn_and_split "doloop_di"
6625 (ne (match_operand:DI 1 "register_operand" "d,d")
6627 (label_ref (match_operand 0 "" ""))
6629 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6630 (plus:DI (match_dup 1) (const_int -1)))
6631 (clobber (match_scratch:DI 3 "=X,&1"))
6632 (clobber (reg:CC CC_REGNUM))]
6635 if (which_alternative != 0)
6637 else if (get_attr_length (insn) == 4)
6638 return "brctg\t%1,%l0";
6640 return "aghi\t%1,-1\;jgne\t%l0";
6642 "&& reload_completed
6643 && (! REG_P (operands[2])
6644 || ! rtx_equal_p (operands[1], operands[2]))"
6645 [(parallel [(set (reg:CCAN CC_REGNUM)
6646 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6648 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6649 (set (match_dup 2) (match_dup 3))
6650 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6651 (label_ref (match_dup 0))
6654 [(set_attr "op_type" "RI")
6655 (set_attr "type" "branch")
6656 (set (attr "length")
6657 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6658 (const_int 4) (const_int 10)))])
6661 ;;- Unconditional jump instructions.
6665 ; jump instruction pattern(s).
6668 (define_expand "jump"
6669 [(match_operand 0 "" "")]
6671 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6673 (define_insn "*jump64"
6674 [(set (pc) (label_ref (match_operand 0 "" "")))]
6677 if (get_attr_length (insn) == 4)
6682 [(set_attr "op_type" "RI")
6683 (set_attr "type" "branch")
6684 (set (attr "length")
6685 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6686 (const_int 4) (const_int 6)))])
6688 (define_insn "*jump31"
6689 [(set (pc) (label_ref (match_operand 0 "" "")))]
6692 gcc_assert (get_attr_length (insn) == 4);
6695 [(set_attr "op_type" "RI")
6696 (set_attr "type" "branch")
6697 (set (attr "length")
6698 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6699 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6700 (const_int 4) (const_int 6))
6701 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6702 (const_int 4) (const_int 8))))])
6705 ; indirect-jump instruction pattern(s).
6708 (define_insn "indirect_jump"
6709 [(set (pc) (match_operand 0 "address_operand" "U"))]
6712 if (get_attr_op_type (insn) == OP_TYPE_RR)
6717 [(set (attr "op_type")
6718 (if_then_else (match_operand 0 "register_operand" "")
6719 (const_string "RR") (const_string "RX")))
6720 (set_attr "type" "branch")
6721 (set_attr "atype" "agen")])
6724 ; casesi instruction pattern(s).
6727 (define_insn "casesi_jump"
6728 [(set (pc) (match_operand 0 "address_operand" "U"))
6729 (use (label_ref (match_operand 1 "" "")))]
6732 if (get_attr_op_type (insn) == OP_TYPE_RR)
6737 [(set (attr "op_type")
6738 (if_then_else (match_operand 0 "register_operand" "")
6739 (const_string "RR") (const_string "RX")))
6740 (set_attr "type" "branch")
6741 (set_attr "atype" "agen")])
6743 (define_expand "casesi"
6744 [(match_operand:SI 0 "general_operand" "")
6745 (match_operand:SI 1 "general_operand" "")
6746 (match_operand:SI 2 "general_operand" "")
6747 (label_ref (match_operand 3 "" ""))
6748 (label_ref (match_operand 4 "" ""))]
6751 rtx index = gen_reg_rtx (SImode);
6752 rtx base = gen_reg_rtx (Pmode);
6753 rtx target = gen_reg_rtx (Pmode);
6755 emit_move_insn (index, operands[0]);
6756 emit_insn (gen_subsi3 (index, index, operands[1]));
6757 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6760 if (Pmode != SImode)
6761 index = convert_to_mode (Pmode, index, 1);
6762 if (GET_CODE (index) != REG)
6763 index = copy_to_mode_reg (Pmode, index);
6766 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6768 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6770 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6772 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6773 emit_move_insn (target, index);
6776 target = gen_rtx_PLUS (Pmode, base, target);
6777 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6784 ;;- Jump to subroutine.
6789 ; untyped call instruction pattern(s).
6792 ;; Call subroutine returning any type.
6793 (define_expand "untyped_call"
6794 [(parallel [(call (match_operand 0 "" "")
6796 (match_operand 1 "" "")
6797 (match_operand 2 "" "")])]
6802 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6804 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6806 rtx set = XVECEXP (operands[2], 0, i);
6807 emit_move_insn (SET_DEST (set), SET_SRC (set));
6810 /* The optimizer does not know that the call sets the function value
6811 registers we stored in the result block. We avoid problems by
6812 claiming that all hard registers are used and clobbered at this
6814 emit_insn (gen_blockage ());
6819 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6820 ;; all of memory. This blocks insns from being moved across this point.
6822 (define_insn "blockage"
6823 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6826 [(set_attr "type" "none")
6827 (set_attr "length" "0")])
6833 (define_expand "sibcall"
6834 [(call (match_operand 0 "" "")
6835 (match_operand 1 "" ""))]
6838 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6842 (define_insn "*sibcall_br"
6843 [(call (mem:QI (reg SIBCALL_REGNUM))
6844 (match_operand 0 "const_int_operand" "n"))]
6845 "SIBLING_CALL_P (insn)
6846 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6848 [(set_attr "op_type" "RR")
6849 (set_attr "type" "branch")
6850 (set_attr "atype" "agen")])
6852 (define_insn "*sibcall_brc"
6853 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6854 (match_operand 1 "const_int_operand" "n"))]
6855 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6857 [(set_attr "op_type" "RI")
6858 (set_attr "type" "branch")])
6860 (define_insn "*sibcall_brcl"
6861 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6862 (match_operand 1 "const_int_operand" "n"))]
6863 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6865 [(set_attr "op_type" "RIL")
6866 (set_attr "type" "branch")])
6869 ; sibcall_value patterns
6872 (define_expand "sibcall_value"
6873 [(set (match_operand 0 "" "")
6874 (call (match_operand 1 "" "")
6875 (match_operand 2 "" "")))]
6878 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6882 (define_insn "*sibcall_value_br"
6883 [(set (match_operand 0 "" "")
6884 (call (mem:QI (reg SIBCALL_REGNUM))
6885 (match_operand 1 "const_int_operand" "n")))]
6886 "SIBLING_CALL_P (insn)
6887 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6889 [(set_attr "op_type" "RR")
6890 (set_attr "type" "branch")
6891 (set_attr "atype" "agen")])
6893 (define_insn "*sibcall_value_brc"
6894 [(set (match_operand 0 "" "")
6895 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6896 (match_operand 2 "const_int_operand" "n")))]
6897 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6899 [(set_attr "op_type" "RI")
6900 (set_attr "type" "branch")])
6902 (define_insn "*sibcall_value_brcl"
6903 [(set (match_operand 0 "" "")
6904 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6905 (match_operand 2 "const_int_operand" "n")))]
6906 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6908 [(set_attr "op_type" "RIL")
6909 (set_attr "type" "branch")])
6913 ; call instruction pattern(s).
6916 (define_expand "call"
6917 [(call (match_operand 0 "" "")
6918 (match_operand 1 "" ""))
6919 (use (match_operand 2 "" ""))]
6922 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6923 gen_rtx_REG (Pmode, RETURN_REGNUM));
6927 (define_insn "*bras"
6928 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6929 (match_operand 1 "const_int_operand" "n"))
6930 (clobber (match_operand 2 "register_operand" "=r"))]
6931 "!SIBLING_CALL_P (insn)
6932 && TARGET_SMALL_EXEC
6933 && GET_MODE (operands[2]) == Pmode"
6935 [(set_attr "op_type" "RI")
6936 (set_attr "type" "jsr")])
6938 (define_insn "*brasl"
6939 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6940 (match_operand 1 "const_int_operand" "n"))
6941 (clobber (match_operand 2 "register_operand" "=r"))]
6942 "!SIBLING_CALL_P (insn)
6944 && GET_MODE (operands[2]) == Pmode"
6946 [(set_attr "op_type" "RIL")
6947 (set_attr "type" "jsr")])
6949 (define_insn "*basr"
6950 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6951 (match_operand 1 "const_int_operand" "n"))
6952 (clobber (match_operand 2 "register_operand" "=r"))]
6953 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6955 if (get_attr_op_type (insn) == OP_TYPE_RR)
6956 return "basr\t%2,%0";
6958 return "bas\t%2,%a0";
6960 [(set (attr "op_type")
6961 (if_then_else (match_operand 0 "register_operand" "")
6962 (const_string "RR") (const_string "RX")))
6963 (set_attr "type" "jsr")
6964 (set_attr "atype" "agen")])
6967 ; call_value instruction pattern(s).
6970 (define_expand "call_value"
6971 [(set (match_operand 0 "" "")
6972 (call (match_operand 1 "" "")
6973 (match_operand 2 "" "")))
6974 (use (match_operand 3 "" ""))]
6977 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6978 gen_rtx_REG (Pmode, RETURN_REGNUM));
6982 (define_insn "*bras_r"
6983 [(set (match_operand 0 "" "")
6984 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6985 (match_operand:SI 2 "const_int_operand" "n")))
6986 (clobber (match_operand 3 "register_operand" "=r"))]
6987 "!SIBLING_CALL_P (insn)
6988 && TARGET_SMALL_EXEC
6989 && GET_MODE (operands[3]) == Pmode"
6991 [(set_attr "op_type" "RI")
6992 (set_attr "type" "jsr")])
6994 (define_insn "*brasl_r"
6995 [(set (match_operand 0 "" "")
6996 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6997 (match_operand 2 "const_int_operand" "n")))
6998 (clobber (match_operand 3 "register_operand" "=r"))]
6999 "!SIBLING_CALL_P (insn)
7001 && GET_MODE (operands[3]) == Pmode"
7003 [(set_attr "op_type" "RIL")
7004 (set_attr "type" "jsr")])
7006 (define_insn "*basr_r"
7007 [(set (match_operand 0 "" "")
7008 (call (mem:QI (match_operand 1 "address_operand" "U"))
7009 (match_operand 2 "const_int_operand" "n")))
7010 (clobber (match_operand 3 "register_operand" "=r"))]
7011 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7013 if (get_attr_op_type (insn) == OP_TYPE_RR)
7014 return "basr\t%3,%1";
7016 return "bas\t%3,%a1";
7018 [(set (attr "op_type")
7019 (if_then_else (match_operand 1 "register_operand" "")
7020 (const_string "RR") (const_string "RX")))
7021 (set_attr "type" "jsr")
7022 (set_attr "atype" "agen")])
7025 ;;- Thread-local storage support.
7028 (define_expand "get_tp_64"
7029 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7033 (define_expand "get_tp_31"
7034 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7038 (define_expand "set_tp_64"
7039 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7040 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7044 (define_expand "set_tp_31"
7045 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7046 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7050 (define_insn "*set_tp"
7051 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7054 [(set_attr "type" "none")
7055 (set_attr "length" "0")])
7057 (define_insn "*tls_load_64"
7058 [(set (match_operand:DI 0 "register_operand" "=d")
7059 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7060 (match_operand:DI 2 "" "")]
7064 [(set_attr "op_type" "RXE")])
7066 (define_insn "*tls_load_31"
7067 [(set (match_operand:SI 0 "register_operand" "=d,d")
7068 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7069 (match_operand:SI 2 "" "")]
7075 [(set_attr "op_type" "RX,RXY")])
7077 (define_insn "*bras_tls"
7078 [(set (match_operand 0 "" "")
7079 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7080 (match_operand 2 "const_int_operand" "n")))
7081 (clobber (match_operand 3 "register_operand" "=r"))
7082 (use (match_operand 4 "" ""))]
7083 "!SIBLING_CALL_P (insn)
7084 && TARGET_SMALL_EXEC
7085 && GET_MODE (operands[3]) == Pmode"
7087 [(set_attr "op_type" "RI")
7088 (set_attr "type" "jsr")])
7090 (define_insn "*brasl_tls"
7091 [(set (match_operand 0 "" "")
7092 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7093 (match_operand 2 "const_int_operand" "n")))
7094 (clobber (match_operand 3 "register_operand" "=r"))
7095 (use (match_operand 4 "" ""))]
7096 "!SIBLING_CALL_P (insn)
7098 && GET_MODE (operands[3]) == Pmode"
7100 [(set_attr "op_type" "RIL")
7101 (set_attr "type" "jsr")])
7103 (define_insn "*basr_tls"
7104 [(set (match_operand 0 "" "")
7105 (call (mem:QI (match_operand 1 "address_operand" "U"))
7106 (match_operand 2 "const_int_operand" "n")))
7107 (clobber (match_operand 3 "register_operand" "=r"))
7108 (use (match_operand 4 "" ""))]
7109 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7111 if (get_attr_op_type (insn) == OP_TYPE_RR)
7112 return "basr\t%3,%1%J4";
7114 return "bas\t%3,%a1%J4";
7116 [(set (attr "op_type")
7117 (if_then_else (match_operand 1 "register_operand" "")
7118 (const_string "RR") (const_string "RX")))
7119 (set_attr "type" "jsr")
7120 (set_attr "atype" "agen")])
7123 ;;- Atomic operations
7127 ; memory barrier pattern.
7130 (define_expand "memory_barrier"
7131 [(set (mem:BLK (match_dup 0))
7132 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7135 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7136 MEM_VOLATILE_P (operands[0]) = 1;
7139 (define_insn "*memory_barrier"
7140 [(set (match_operand:BLK 0 "" "")
7141 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7144 [(set_attr "op_type" "RR")])
7147 ; compare and swap patterns.
7150 (define_expand "sync_compare_and_swap<mode>"
7152 [(set (match_operand:TDSI 0 "register_operand" "")
7153 (match_operand:TDSI 1 "memory_operand" ""))
7155 (unspec_volatile:TDSI
7157 (match_operand:TDSI 2 "register_operand" "")
7158 (match_operand:TDSI 3 "register_operand" "")]
7160 (set (reg:CCZ1 CC_REGNUM)
7161 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7164 (define_expand "sync_compare_and_swap_cc<mode>"
7166 [(set (match_operand:TDSI 0 "register_operand" "")
7167 (match_operand:TDSI 1 "memory_operand" ""))
7169 (unspec_volatile:TDSI
7171 (match_operand:TDSI 2 "register_operand" "")
7172 (match_operand:TDSI 3 "register_operand" "")]
7175 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7178 /* Emulate compare. */
7179 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7180 s390_compare_op0 = operands[1];
7181 s390_compare_op1 = operands[2];
7182 s390_compare_emitted = operands[4];
7185 (define_insn "*sync_compare_and_swap<mode>"
7186 [(set (match_operand:DP 0 "register_operand" "=r")
7187 (match_operand:DP 1 "memory_operand" "+Q"))
7191 (match_operand:DP 2 "register_operand" "0")
7192 (match_operand:DP 3 "register_operand" "r")]
7194 (set (reg:CCZ1 CC_REGNUM)
7195 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7197 "cds<tg>\t%0,%3,%S1"
7198 [(set_attr "op_type" "RS<TE>")
7199 (set_attr "type" "sem")])
7201 (define_insn "*sync_compare_and_swap<mode>"
7202 [(set (match_operand:GPR 0 "register_operand" "=r")
7203 (match_operand:GPR 1 "memory_operand" "+Q"))
7205 (unspec_volatile:GPR
7207 (match_operand:GPR 2 "register_operand" "0")
7208 (match_operand:GPR 3 "register_operand" "r")]
7210 (set (reg:CCZ1 CC_REGNUM)
7211 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7214 [(set_attr "op_type" "RS<E>")
7215 (set_attr "type" "sem")])
7219 ;;- Miscellaneous instructions.
7223 ; allocate stack instruction pattern(s).
7226 (define_expand "allocate_stack"
7227 [(match_operand 0 "general_operand" "")
7228 (match_operand 1 "general_operand" "")]
7231 rtx temp = gen_reg_rtx (Pmode);
7233 emit_move_insn (temp, s390_back_chain_rtx ());
7234 anti_adjust_stack (operands[1]);
7235 emit_move_insn (s390_back_chain_rtx (), temp);
7237 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7243 ; setjmp instruction pattern.
7246 (define_expand "builtin_setjmp_receiver"
7247 [(match_operand 0 "" "")]
7250 emit_insn (s390_load_got ());
7251 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7255 ;; These patterns say how to save and restore the stack pointer. We need not
7256 ;; save the stack pointer at function level since we are careful to
7257 ;; preserve the backchain. At block level, we have to restore the backchain
7258 ;; when we restore the stack pointer.
7260 ;; For nonlocal gotos, we must save both the stack pointer and its
7261 ;; backchain and restore both. Note that in the nonlocal case, the
7262 ;; save area is a memory location.
7264 (define_expand "save_stack_function"
7265 [(match_operand 0 "general_operand" "")
7266 (match_operand 1 "general_operand" "")]
7270 (define_expand "restore_stack_function"
7271 [(match_operand 0 "general_operand" "")
7272 (match_operand 1 "general_operand" "")]
7276 (define_expand "restore_stack_block"
7277 [(match_operand 0 "register_operand" "")
7278 (match_operand 1 "register_operand" "")]
7281 rtx temp = gen_reg_rtx (Pmode);
7283 emit_move_insn (temp, s390_back_chain_rtx ());
7284 emit_move_insn (operands[0], operands[1]);
7285 emit_move_insn (s390_back_chain_rtx (), temp);
7290 (define_expand "save_stack_nonlocal"
7291 [(match_operand 0 "memory_operand" "")
7292 (match_operand 1 "register_operand" "")]
7295 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7296 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7298 /* Copy the backchain to the first word, sp to the second and the
7299 literal pool base to the third. */
7301 if (TARGET_BACKCHAIN)
7303 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7304 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7307 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7308 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7313 (define_expand "restore_stack_nonlocal"
7314 [(match_operand 0 "register_operand" "")
7315 (match_operand 1 "memory_operand" "")]
7318 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7319 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7320 rtx temp = NULL_RTX;
7322 /* Restore the backchain from the first word, sp from the second and the
7323 literal pool base from the third. */
7325 if (TARGET_BACKCHAIN)
7326 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7328 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7329 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7332 emit_move_insn (s390_back_chain_rtx (), temp);
7334 emit_insn (gen_rtx_USE (VOIDmode, base));
7338 (define_expand "exception_receiver"
7342 s390_set_has_landing_pad_p (true);
7347 ; nop instruction pattern(s).
7354 [(set_attr "op_type" "RR")])
7358 ; Special literal pool access instruction pattern(s).
7361 (define_insn "*pool_entry"
7362 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7363 UNSPECV_POOL_ENTRY)]
7366 enum machine_mode mode = GET_MODE (PATTERN (insn));
7367 unsigned int align = GET_MODE_BITSIZE (mode);
7368 s390_output_pool_entry (operands[0], mode, align);
7371 [(set (attr "length")
7372 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7374 (define_insn "pool_align"
7375 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7376 UNSPECV_POOL_ALIGN)]
7379 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7381 (define_insn "pool_section_start"
7382 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7385 [(set_attr "length" "0")])
7387 (define_insn "pool_section_end"
7388 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7391 [(set_attr "length" "0")])
7393 (define_insn "main_base_31_small"
7394 [(set (match_operand 0 "register_operand" "=a")
7395 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7396 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7398 [(set_attr "op_type" "RR")
7399 (set_attr "type" "la")])
7401 (define_insn "main_base_31_large"
7402 [(set (match_operand 0 "register_operand" "=a")
7403 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7404 (set (pc) (label_ref (match_operand 2 "" "")))]
7405 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7407 [(set_attr "op_type" "RI")])
7409 (define_insn "main_base_64"
7410 [(set (match_operand 0 "register_operand" "=a")
7411 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7412 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7414 [(set_attr "op_type" "RIL")
7415 (set_attr "type" "larl")])
7417 (define_insn "main_pool"
7418 [(set (match_operand 0 "register_operand" "=a")
7419 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7420 "GET_MODE (operands[0]) == Pmode"
7425 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7426 (const_string "larl") (const_string "la")))])
7428 (define_insn "reload_base_31"
7429 [(set (match_operand 0 "register_operand" "=a")
7430 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7431 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7432 "basr\t%0,0\;la\t%0,%1-.(%0)"
7433 [(set_attr "length" "6")
7434 (set_attr "type" "la")])
7436 (define_insn "reload_base_64"
7437 [(set (match_operand 0 "register_operand" "=a")
7438 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7439 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7441 [(set_attr "op_type" "RIL")
7442 (set_attr "type" "larl")])
7445 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7450 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7453 ;; Insns related to generating the function prologue and epilogue.
7457 (define_expand "prologue"
7458 [(use (const_int 0))]
7460 "s390_emit_prologue (); DONE;")
7462 (define_expand "epilogue"
7463 [(use (const_int 1))]
7465 "s390_emit_epilogue (false); DONE;")
7467 (define_expand "sibcall_epilogue"
7468 [(use (const_int 0))]
7470 "s390_emit_epilogue (true); DONE;")
7472 (define_insn "*return"
7474 (use (match_operand 0 "register_operand" "a"))]
7475 "GET_MODE (operands[0]) == Pmode"
7477 [(set_attr "op_type" "RR")
7478 (set_attr "type" "jsr")
7479 (set_attr "atype" "agen")])
7482 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7483 ;; pointer. This is used for compatibility.
7485 (define_expand "ptr_extend"
7486 [(set (match_operand:DI 0 "register_operand" "=r")
7487 (match_operand:SI 1 "register_operand" "r"))]
7490 emit_insn (gen_anddi3 (operands[0],
7491 gen_lowpart (DImode, operands[1]),
7492 GEN_INT (0x7fffffff)));
7496 ;; Instruction definition to expand eh_return macro to support
7497 ;; swapping in special linkage return addresses.
7499 (define_expand "eh_return"
7500 [(use (match_operand 0 "register_operand" ""))]
7503 s390_emit_tpf_eh_return (operands[0]);
7508 ; Stack Protector Patterns
7511 (define_expand "stack_protect_set"
7512 [(set (match_operand 0 "memory_operand" "")
7513 (match_operand 1 "memory_operand" ""))]
7516 #ifdef TARGET_THREAD_SSP_OFFSET
7518 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7519 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7522 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7524 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7529 (define_insn "stack_protect_set<mode>"
7530 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7531 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7533 "mvc\t%O0(%G0,%R0),%S1"
7534 [(set_attr "op_type" "SS")])
7536 (define_expand "stack_protect_test"
7537 [(set (reg:CC CC_REGNUM)
7538 (compare (match_operand 0 "memory_operand" "")
7539 (match_operand 1 "memory_operand" "")))
7540 (match_operand 2 "" "")]
7543 #ifdef TARGET_THREAD_SSP_OFFSET
7545 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7546 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7548 s390_compare_op0 = operands[0];
7549 s390_compare_op1 = operands[1];
7550 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7553 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7555 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7557 emit_jump_insn (gen_beq (operands[2]));
7562 (define_insn "stack_protect_test<mode>"
7563 [(set (reg:CCZ CC_REGNUM)
7564 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7565 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7567 "clc\t%O0(%G0,%R0),%S1"
7568 [(set_attr "op_type" "SS")])