gcc/testsuite/gcc.target/arm/pr51534.c

   1 /* Test the vector comparison intrinsics when comparing to immediate zero.
   2    */
   3
   4 /* { dg-do assemble } */
   5 /* { dg-require-effective-target arm_neon_ok } */
   6 /* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
   7 /* { dg-add-options arm_neon } */
   8
   9 #include <arm_neon.h>
  10
  11 #define GEN_TEST(T, D, C, R) \
  12   R test_##C##_##T (T a) { return C (a, D (0)); }
  13
  14 #define GEN_DOUBLE_TESTS(S, T, C) \
  15   GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
  16   GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T)
  17
  18 #define GEN_QUAD_TESTS(S, T, C) \
  19   GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
  20   GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T)
  21
  22 #define GEN_COND_TESTS(C) \
  23   GEN_DOUBLE_TESTS (8, int8x8_t, C) \
  24   GEN_DOUBLE_TESTS (16, int16x4_t, C) \
  25   GEN_DOUBLE_TESTS (32, int32x2_t, C) \
  26   GEN_QUAD_TESTS (8, int8x16_t, C) \
  27   GEN_QUAD_TESTS (16, int16x8_t, C) \
  28   GEN_QUAD_TESTS (32, int32x4_t, C)
  29
  30 GEN_COND_TESTS(vcgt)
  31 GEN_COND_TESTS(vcge)
  32 GEN_COND_TESTS(vclt)
  33 GEN_COND_TESTS(vcle)
  34 GEN_COND_TESTS(vceq)
  35
  36 /* Scan for expected outputs.  */
  37 /* { dg-final { scan-assembler "vcgt\.s8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  38 /* { dg-final { scan-assembler-times "vcgt\.u8\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  39 /* { dg-final { scan-assembler "vcgt\.s16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  40 /* { dg-final { scan-assembler-times "vcgt\.u16\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  41 /* { dg-final { scan-assembler "vcgt\.s32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  42 /* { dg-final { scan-assembler-times "vcgt\.u32\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  43 /* { dg-final { scan-assembler "vcgt\.s8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  44 /* { dg-final { scan-assembler-times "vcgt\.u8\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  45 /* { dg-final { scan-assembler "vcgt\.s16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  46 /* { dg-final { scan-assembler-times "vcgt\.u16\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  47 /* { dg-final { scan-assembler "vcgt\.s32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  48 /* { dg-final { scan-assembler-times "vcgt\.u32\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  49 /* { dg-final { scan-assembler "vcge\.s8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  50 /* { dg-final { scan-assembler-times "vcge\.u8\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  51 /* { dg-final { scan-assembler "vcge\.s16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  52 /* { dg-final { scan-assembler-times "vcge\.u16\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  53 /* { dg-final { scan-assembler "vcge\.s32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  54 /* { dg-final { scan-assembler-times "vcge\.u32\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
  55 /* { dg-final { scan-assembler "vcge\.s8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  56 /* { dg-final { scan-assembler-times "vcge\.u8\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  57 /* { dg-final { scan-assembler "vcge\.s16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  58 /* { dg-final { scan-assembler-times "vcge\.u16\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  59 /* { dg-final { scan-assembler "vcge\.s32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  60 /* { dg-final { scan-assembler-times "vcge\.u32\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
  61 /* { dg-final { scan-assembler "vclt\.s8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  62 /* { dg-final { scan-assembler "vclt\.s16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  63 /* { dg-final { scan-assembler "vclt\.s32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  64 /* { dg-final { scan-assembler "vclt\.s8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  65 /* { dg-final { scan-assembler "vclt\.s16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  66 /* { dg-final { scan-assembler "vclt\.s32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  67 /* { dg-final { scan-assembler "vcle\.s8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  68 /* { dg-final { scan-assembler "vcle\.s16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  69 /* { dg-final { scan-assembler "vcle\.s32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
  70 /* { dg-final { scan-assembler "vcle\.s8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  71 /* { dg-final { scan-assembler "vcle\.s16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  72 /* { dg-final { scan-assembler "vcle\.s32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
  73 /* { dg-final { scan-assembler-times "vceq\.i8\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
  74 /* { dg-final { scan-assembler-times "vceq\.i16\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
  75 /* { dg-final { scan-assembler-times "vceq\.i32\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
  76 /* { dg-final { scan-assembler-times "vceq\.i8\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
  77 /* { dg-final { scan-assembler-times "vceq\.i16\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
  78 /* { dg-final { scan-assembler-times "vceq\.i32\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
  79
  80 /* And ensure we don't have unexpected output too.  */
  81 /* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[         \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
  82
  83 /* Tidy up.  */