1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
33 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
35 #include "addresses.h"
38 /* Forward declarations */
39 static void set_of_1 (rtx
, const_rtx
, void *);
40 static bool covers_regno_p (const_rtx
, unsigned int);
41 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
42 static int computed_jump_p_1 (const_rtx
);
43 static void parms_set (rtx
, const_rtx
, void *);
45 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
46 const_rtx
, machine_mode
,
47 unsigned HOST_WIDE_INT
);
48 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
54 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
55 machine_mode
, unsigned int);
57 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
58 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
60 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
61 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
62 SIGN_EXTEND then while narrowing we also have to enforce the
63 representation and sign-extend the value to mode DESTINATION_REP.
65 If the value is already sign-extended to DESTINATION_REP mode we
66 can just switch to DESTINATION mode on it. For each pair of
67 integral modes SOURCE and DESTINATION, when truncating from SOURCE
68 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
69 contains the number of high-order bits in SOURCE that have to be
70 copies of the sign-bit so that we can do this mode-switch to
74 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
76 /* Store X into index I of ARRAY. ARRAY is known to have at least I
77 elements. Return the new base of ARRAY. */
80 typename
T::value_type
*
81 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
83 size_t i
, value_type x
)
85 if (base
== array
.stack
)
92 gcc_checking_assert (i
== LOCAL_ELEMS
);
93 /* A previous iteration might also have moved from the stack to the
94 heap, in which case the heap array will already be big enough. */
95 if (vec_safe_length (array
.heap
) <= i
)
96 vec_safe_grow (array
.heap
, i
+ 1);
97 base
= array
.heap
->address ();
98 memcpy (base
, array
.stack
, sizeof (array
.stack
));
99 base
[LOCAL_ELEMS
] = x
;
102 unsigned int length
= array
.heap
->length ();
105 gcc_checking_assert (base
== array
.heap
->address ());
111 gcc_checking_assert (i
== length
);
112 vec_safe_push (array
.heap
, x
);
113 return array
.heap
->address ();
117 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
118 number of elements added to the worklist. */
120 template <typename T
>
122 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
124 size_t end
, rtx_type x
)
126 enum rtx_code code
= GET_CODE (x
);
127 const char *format
= GET_RTX_FORMAT (code
);
128 size_t orig_end
= end
;
129 if (__builtin_expect (INSN_P (x
), false))
131 /* Put the pattern at the top of the queue, since that's what
132 we're likely to want most. It also allows for the SEQUENCE
134 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
135 if (format
[i
] == 'e')
137 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
138 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
141 base
= add_single_to_queue (array
, base
, end
++, subx
);
145 for (int i
= 0; format
[i
]; ++i
)
146 if (format
[i
] == 'e')
148 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
149 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
152 base
= add_single_to_queue (array
, base
, end
++, subx
);
154 else if (format
[i
] == 'E')
156 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
157 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
158 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
159 for (unsigned int j
= 0; j
< length
; j
++)
160 base
[end
++] = T::get_value (vec
[j
]);
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
= add_single_to_queue (array
, base
, end
++,
164 T::get_value (vec
[j
]));
165 if (code
== SEQUENCE
&& end
== length
)
166 /* If the subrtxes of the sequence fill the entire array then
167 we know that no other parts of a containing insn are queued.
168 The caller is therefore iterating over the sequence as a
169 PATTERN (...), so we also want the patterns of the
171 for (unsigned int j
= 0; j
< length
; j
++)
173 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
175 base
[j
] = T::get_value (PATTERN (x
));
178 return end
- orig_end
;
181 template <typename T
>
183 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
185 vec_free (array
.heap
);
188 template <typename T
>
189 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
191 template class generic_subrtx_iterator
<const_rtx_accessor
>;
192 template class generic_subrtx_iterator
<rtx_var_accessor
>;
193 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
195 /* Return 1 if the value of X is unstable
196 (would be different at a different point in the program).
197 The frame pointer, arg pointer, etc. are considered stable
198 (within one function) and so is anything marked `unchanging'. */
201 rtx_unstable_p (const_rtx x
)
203 const RTX_CODE code
= GET_CODE (x
);
210 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
219 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
220 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
221 /* The arg pointer varies if it is not a fixed register. */
222 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
224 /* ??? When call-clobbered, the value is stable modulo the restore
225 that must happen after a call. This currently screws up local-alloc
226 into believing that the restore is not needed. */
227 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
232 if (MEM_VOLATILE_P (x
))
241 fmt
= GET_RTX_FORMAT (code
);
242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
245 if (rtx_unstable_p (XEXP (x
, i
)))
248 else if (fmt
[i
] == 'E')
251 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
252 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
259 /* Return 1 if X has a value that can vary even between two
260 executions of the program. 0 means X can be compared reliably
261 against certain constants or near-constants.
262 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
263 zero, we are slightly more conservative.
264 The frame pointer and the arg pointer are considered constant. */
267 rtx_varies_p (const_rtx x
, bool for_alias
)
280 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
289 /* Note that we have to test for the actual rtx used for the frame
290 and arg pointers and not just the register number in case we have
291 eliminated the frame and/or arg pointer and are using it
293 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
294 /* The arg pointer varies if it is not a fixed register. */
295 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
297 if (x
== pic_offset_table_rtx
298 /* ??? When call-clobbered, the value is stable modulo the restore
299 that must happen after a call. This currently screws up
300 local-alloc into believing that the restore is not needed, so we
301 must return 0 only if we are called from alias analysis. */
302 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
307 /* The operand 0 of a LO_SUM is considered constant
308 (in fact it is related specifically to operand 1)
309 during alias analysis. */
310 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
311 || rtx_varies_p (XEXP (x
, 1), for_alias
);
314 if (MEM_VOLATILE_P (x
))
323 fmt
= GET_RTX_FORMAT (code
);
324 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
327 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
330 else if (fmt
[i
] == 'E')
333 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
334 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
341 /* Compute an approximation for the offset between the register
342 FROM and TO for the current function, as it was at the start
346 get_initial_register_offset (int from
, int to
)
348 #ifdef ELIMINABLE_REGS
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 HOST_WIDE_INT offset
;
458 if (reload_completed
)
460 INITIAL_FRAME_POINTER_OFFSET (offset
);
464 offset
= crtl
->outgoing_args_size
+ get_frame_size ();
465 #if !STACK_GROWS_DOWNWARD
470 if (to
== STACK_POINTER_REGNUM
)
472 else if (from
== STACK_POINTER_REGNUM
)
480 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
481 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
482 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
483 references on strict alignment machines. */
486 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
487 machine_mode mode
, bool unaligned_mems
)
489 enum rtx_code code
= GET_CODE (x
);
491 /* The offset must be a multiple of the mode size if we are considering
492 unaligned memory references on strict alignment machines. */
493 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
495 HOST_WIDE_INT actual_offset
= offset
;
497 #ifdef SPARC_STACK_BOUNDARY_HACK
498 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
499 the real alignment of %sp. However, when it does this, the
500 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
501 if (SPARC_STACK_BOUNDARY_HACK
502 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
503 actual_offset
-= STACK_POINTER_OFFSET
;
506 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
513 if (SYMBOL_REF_WEAK (x
))
515 if (!CONSTANT_POOL_ADDRESS_P (x
))
518 HOST_WIDE_INT decl_size
;
523 size
= GET_MODE_SIZE (mode
);
527 /* If the size of the access or of the symbol is unknown,
529 decl
= SYMBOL_REF_DECL (x
);
531 /* Else check that the access is in bounds. TODO: restructure
532 expr_size/tree_expr_size/int_expr_size and just use the latter. */
535 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
536 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
537 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
539 else if (TREE_CODE (decl
) == STRING_CST
)
540 decl_size
= TREE_STRING_LENGTH (decl
);
541 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
542 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
546 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
555 /* Stack references are assumed not to trap, but we need to deal with
556 nonsensical offsets. */
557 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
558 || x
== stack_pointer_rtx
559 /* The arg pointer varies if it is not a fixed register. */
560 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
563 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
565 HOST_WIDE_INT red_zone_size
= 0;
567 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
569 HOST_WIDE_INT low_bound
, high_bound
;
572 size
= GET_MODE_SIZE (mode
);
574 if (x
== frame_pointer_rtx
)
576 if (FRAME_GROWS_DOWNWARD
)
578 high_bound
= STARTING_FRAME_OFFSET
;
579 low_bound
= high_bound
- get_frame_size ();
583 low_bound
= STARTING_FRAME_OFFSET
;
584 high_bound
= low_bound
+ get_frame_size ();
587 else if (x
== hard_frame_pointer_rtx
)
589 HOST_WIDE_INT sp_offset
590 = get_initial_register_offset (STACK_POINTER_REGNUM
,
591 HARD_FRAME_POINTER_REGNUM
);
592 HOST_WIDE_INT ap_offset
593 = get_initial_register_offset (ARG_POINTER_REGNUM
,
594 HARD_FRAME_POINTER_REGNUM
);
596 #if STACK_GROWS_DOWNWARD
597 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
598 high_bound
= ap_offset
599 + FIRST_PARM_OFFSET (current_function_decl
)
600 #if !ARGS_GROW_DOWNWARD
605 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
606 low_bound
= ap_offset
607 + FIRST_PARM_OFFSET (current_function_decl
)
608 #if ARGS_GROW_DOWNWARD
614 else if (x
== stack_pointer_rtx
)
616 HOST_WIDE_INT ap_offset
617 = get_initial_register_offset (ARG_POINTER_REGNUM
,
618 STACK_POINTER_REGNUM
);
620 #if STACK_GROWS_DOWNWARD
621 low_bound
= - red_zone_size
- stack_boundary
;
622 high_bound
= ap_offset
623 + FIRST_PARM_OFFSET (current_function_decl
)
624 #if !ARGS_GROW_DOWNWARD
629 high_bound
= red_zone_size
+ stack_boundary
;
630 low_bound
= ap_offset
631 + FIRST_PARM_OFFSET (current_function_decl
)
632 #if ARGS_GROW_DOWNWARD
640 /* We assume that accesses are safe to at least the
642 Examples are varargs and __builtin_return_address. */
643 #if ARGS_GROW_DOWNWARD
644 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
646 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
647 - crtl
->args
.size
- stack_boundary
;
649 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
651 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
652 + crtl
->args
.size
+ stack_boundary
;
656 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
660 /* All of the virtual frame registers are stack references. */
661 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
662 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
668 mode
, unaligned_mems
);
671 /* An address is assumed not to trap if:
672 - it is the pic register plus a constant. */
673 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
676 /* - or it is an address that can't trap plus a constant integer. */
677 if (CONST_INT_P (XEXP (x
, 1))
678 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
679 size
, mode
, unaligned_mems
))
686 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
687 mode
, unaligned_mems
);
694 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
695 mode
, unaligned_mems
);
701 /* If it isn't one of the case above, it can cause a trap. */
705 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
708 rtx_addr_can_trap_p (const_rtx x
)
710 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
713 /* Return true if X is an address that is known to not be zero. */
716 nonzero_address_p (const_rtx x
)
718 const enum rtx_code code
= GET_CODE (x
);
723 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
729 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
730 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
731 || x
== stack_pointer_rtx
732 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
734 /* All of the virtual frame registers are stack references. */
735 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
736 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
741 return nonzero_address_p (XEXP (x
, 0));
744 /* Handle PIC references. */
745 if (XEXP (x
, 0) == pic_offset_table_rtx
746 && CONSTANT_P (XEXP (x
, 1)))
751 /* Similar to the above; allow positive offsets. Further, since
752 auto-inc is only allowed in memories, the register must be a
754 if (CONST_INT_P (XEXP (x
, 1))
755 && INTVAL (XEXP (x
, 1)) > 0)
757 return nonzero_address_p (XEXP (x
, 0));
760 /* Similarly. Further, the offset is always positive. */
767 return nonzero_address_p (XEXP (x
, 0));
770 return nonzero_address_p (XEXP (x
, 1));
776 /* If it isn't one of the case above, might be zero. */
780 /* Return 1 if X refers to a memory location whose address
781 cannot be compared reliably with constant addresses,
782 or if X refers to a BLKmode memory object.
783 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
784 zero, we are slightly more conservative. */
787 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
798 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
800 fmt
= GET_RTX_FORMAT (code
);
801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
804 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
807 else if (fmt
[i
] == 'E')
810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
811 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
817 /* Return the CALL in X if there is one. */
820 get_call_rtx_from (rtx x
)
824 if (GET_CODE (x
) == PARALLEL
)
825 x
= XVECEXP (x
, 0, 0);
826 if (GET_CODE (x
) == SET
)
828 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
833 /* Return the value of the integer term in X, if one is apparent;
835 Only obvious integer terms are detected.
836 This is used in cse.c with the `related_value' field. */
839 get_integer_term (const_rtx x
)
841 if (GET_CODE (x
) == CONST
)
844 if (GET_CODE (x
) == MINUS
845 && CONST_INT_P (XEXP (x
, 1)))
846 return - INTVAL (XEXP (x
, 1));
847 if (GET_CODE (x
) == PLUS
848 && CONST_INT_P (XEXP (x
, 1)))
849 return INTVAL (XEXP (x
, 1));
853 /* If X is a constant, return the value sans apparent integer term;
855 Only obvious integer terms are detected. */
858 get_related_value (const_rtx x
)
860 if (GET_CODE (x
) != CONST
)
863 if (GET_CODE (x
) == PLUS
864 && CONST_INT_P (XEXP (x
, 1)))
866 else if (GET_CODE (x
) == MINUS
867 && CONST_INT_P (XEXP (x
, 1)))
872 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
873 to somewhere in the same object or object_block as SYMBOL. */
876 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
880 if (GET_CODE (symbol
) != SYMBOL_REF
)
888 if (CONSTANT_POOL_ADDRESS_P (symbol
)
889 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
892 decl
= SYMBOL_REF_DECL (symbol
);
893 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
897 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
898 && SYMBOL_REF_BLOCK (symbol
)
899 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
900 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
901 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
907 /* Split X into a base and a constant offset, storing them in *BASE_OUT
908 and *OFFSET_OUT respectively. */
911 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
913 if (GET_CODE (x
) == CONST
)
916 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
918 *base_out
= XEXP (x
, 0);
919 *offset_out
= XEXP (x
, 1);
924 *offset_out
= const0_rtx
;
927 /* Return the number of places FIND appears within X. If COUNT_DEST is
928 zero, we do not count occurrences inside the destination of a SET. */
931 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
935 const char *format_ptr
;
954 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
956 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
960 if (MEM_P (find
) && rtx_equal_p (x
, find
))
965 if (SET_DEST (x
) == find
&& ! count_dest
)
966 return count_occurrences (SET_SRC (x
), find
, count_dest
);
973 format_ptr
= GET_RTX_FORMAT (code
);
976 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
978 switch (*format_ptr
++)
981 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
985 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
986 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
994 /* Return TRUE if OP is a register or subreg of a register that
995 holds an unsigned quantity. Otherwise, return FALSE. */
998 unsigned_reg_p (rtx op
)
1002 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1005 if (GET_CODE (op
) == SUBREG
1006 && SUBREG_PROMOTED_SIGN (op
))
1013 /* Nonzero if register REG appears somewhere within IN.
1014 Also works if REG is not a register; in this case it checks
1015 for a subexpression of IN that is Lisp "equal" to REG. */
1018 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1030 if (GET_CODE (in
) == LABEL_REF
)
1031 return reg
== LABEL_REF_LABEL (in
);
1033 code
= GET_CODE (in
);
1037 /* Compare registers by number. */
1039 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1041 /* These codes have no constituent expressions
1049 /* These are kept unique for a given value. */
1056 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1059 fmt
= GET_RTX_FORMAT (code
);
1061 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1066 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1067 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1070 else if (fmt
[i
] == 'e'
1071 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1077 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1078 no CODE_LABEL insn. */
1081 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1086 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1092 /* Nonzero if register REG is used in an insn between
1093 FROM_INSN and TO_INSN (exclusive of those two). */
1096 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1097 const rtx_insn
*to_insn
)
1101 if (from_insn
== to_insn
)
1104 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1105 if (NONDEBUG_INSN_P (insn
)
1106 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1107 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1112 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1113 is entirely replaced by a new value and the only use is as a SET_DEST,
1114 we do not consider it a reference. */
1117 reg_referenced_p (const_rtx x
, const_rtx body
)
1121 switch (GET_CODE (body
))
1124 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1127 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1128 of a REG that occupies all of the REG, the insn references X if
1129 it is mentioned in the destination. */
1130 if (GET_CODE (SET_DEST (body
)) != CC0
1131 && GET_CODE (SET_DEST (body
)) != PC
1132 && !REG_P (SET_DEST (body
))
1133 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1134 && REG_P (SUBREG_REG (SET_DEST (body
)))
1135 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1136 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1137 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1138 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1139 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1144 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1145 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1152 return reg_overlap_mentioned_p (x
, body
);
1155 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1158 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1161 case UNSPEC_VOLATILE
:
1162 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1163 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1168 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1169 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1174 if (MEM_P (XEXP (body
, 0)))
1175 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1180 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1182 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1189 /* Nonzero if register REG is set or clobbered in an insn between
1190 FROM_INSN and TO_INSN (exclusive of those two). */
1193 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1194 const rtx_insn
*to_insn
)
1196 const rtx_insn
*insn
;
1198 if (from_insn
== to_insn
)
1201 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1202 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1207 /* Return true if REG is set or clobbered inside INSN. */
1210 reg_set_p (const_rtx reg
, const_rtx insn
)
1212 /* After delay slot handling, call and branch insns might be in a
1213 sequence. Check all the elements there. */
1214 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1216 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1217 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1223 /* We can be passed an insn or part of one. If we are passed an insn,
1224 check if a side-effect of the insn clobbers REG. */
1226 && (FIND_REG_INC_NOTE (insn
, reg
)
1229 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1230 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1231 GET_MODE (reg
), REGNO (reg
)))
1233 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1236 return set_of (reg
, insn
) != NULL_RTX
;
1239 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1240 only if none of them are modified between START and END. Return 1 if
1241 X contains a MEM; this routine does use memory aliasing. */
1244 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1246 const enum rtx_code code
= GET_CODE (x
);
1267 if (modified_between_p (XEXP (x
, 0), start
, end
))
1269 if (MEM_READONLY_P (x
))
1271 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1272 if (memory_modified_in_insn_p (x
, insn
))
1278 return reg_set_between_p (x
, start
, end
);
1284 fmt
= GET_RTX_FORMAT (code
);
1285 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1287 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1290 else if (fmt
[i
] == 'E')
1291 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1292 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1299 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1300 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1301 does use memory aliasing. */
1304 modified_in_p (const_rtx x
, const_rtx insn
)
1306 const enum rtx_code code
= GET_CODE (x
);
1323 if (modified_in_p (XEXP (x
, 0), insn
))
1325 if (MEM_READONLY_P (x
))
1327 if (memory_modified_in_insn_p (x
, insn
))
1333 return reg_set_p (x
, insn
);
1339 fmt
= GET_RTX_FORMAT (code
);
1340 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1342 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1345 else if (fmt
[i
] == 'E')
1346 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1347 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1354 /* Helper function for set_of. */
1362 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1364 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1365 if (rtx_equal_p (x
, data
->pat
)
1366 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1370 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1371 (either directly or via STRICT_LOW_PART and similar modifiers). */
1373 set_of (const_rtx pat
, const_rtx insn
)
1375 struct set_of_data data
;
1376 data
.found
= NULL_RTX
;
1378 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1382 /* Add all hard register in X to *PSET. */
1384 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1386 subrtx_iterator::array_type array
;
1387 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1389 const_rtx x
= *iter
;
1390 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1391 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1395 /* This function, called through note_stores, collects sets and
1396 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1399 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1401 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1402 if (REG_P (x
) && HARD_REGISTER_P (x
))
1403 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1406 /* Examine INSN, and compute the set of hard registers written by it.
1407 Store it in *PSET. Should only be called after reload. */
1409 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1413 CLEAR_HARD_REG_SET (*pset
);
1414 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1418 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1420 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1421 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1423 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1424 if (REG_NOTE_KIND (link
) == REG_INC
)
1425 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1428 /* Like record_hard_reg_sets, but called through note_uses. */
1430 record_hard_reg_uses (rtx
*px
, void *data
)
1432 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1435 /* Given an INSN, return a SET expression if this insn has only a single SET.
1436 It may also have CLOBBERs, USEs, or SET whose output
1437 will not be used, which we ignore. */
1440 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1443 int set_verified
= 1;
1446 if (GET_CODE (pat
) == PARALLEL
)
1448 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1450 rtx sub
= XVECEXP (pat
, 0, i
);
1451 switch (GET_CODE (sub
))
1458 /* We can consider insns having multiple sets, where all
1459 but one are dead as single set insns. In common case
1460 only single set is present in the pattern so we want
1461 to avoid checking for REG_UNUSED notes unless necessary.
1463 When we reach set first time, we just expect this is
1464 the single set we are looking for and only when more
1465 sets are found in the insn, we check them. */
1468 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1469 && !side_effects_p (set
))
1475 set
= sub
, set_verified
= 0;
1476 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1477 || side_effects_p (sub
))
1489 /* Given an INSN, return nonzero if it has more than one SET, else return
1493 multiple_sets (const_rtx insn
)
1498 /* INSN must be an insn. */
1499 if (! INSN_P (insn
))
1502 /* Only a PARALLEL can have multiple SETs. */
1503 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1505 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1506 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1508 /* If we have already found a SET, then return now. */
1516 /* Either zero or one SET. */
1520 /* Return nonzero if the destination of SET equals the source
1521 and there are no side effects. */
1524 set_noop_p (const_rtx set
)
1526 rtx src
= SET_SRC (set
);
1527 rtx dst
= SET_DEST (set
);
1529 if (dst
== pc_rtx
&& src
== pc_rtx
)
1532 if (MEM_P (dst
) && MEM_P (src
))
1533 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1535 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1536 return rtx_equal_p (XEXP (dst
, 0), src
)
1537 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1538 && !side_effects_p (src
);
1540 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1541 dst
= XEXP (dst
, 0);
1543 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1545 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1547 src
= SUBREG_REG (src
);
1548 dst
= SUBREG_REG (dst
);
1551 /* It is a NOOP if destination overlaps with selected src vector
1553 if (GET_CODE (src
) == VEC_SELECT
1554 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1555 && HARD_REGISTER_P (XEXP (src
, 0))
1556 && HARD_REGISTER_P (dst
))
1559 rtx par
= XEXP (src
, 1);
1560 rtx src0
= XEXP (src
, 0);
1561 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1562 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1564 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1565 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1568 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1569 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1572 return (REG_P (src
) && REG_P (dst
)
1573 && REGNO (src
) == REGNO (dst
));
1576 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1580 noop_move_p (const rtx_insn
*insn
)
1582 rtx pat
= PATTERN (insn
);
1584 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1587 /* Insns carrying these notes are useful later on. */
1588 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1591 /* Check the code to be executed for COND_EXEC. */
1592 if (GET_CODE (pat
) == COND_EXEC
)
1593 pat
= COND_EXEC_CODE (pat
);
1595 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1598 if (GET_CODE (pat
) == PARALLEL
)
1601 /* If nothing but SETs of registers to themselves,
1602 this insn can also be deleted. */
1603 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1605 rtx tem
= XVECEXP (pat
, 0, i
);
1607 if (GET_CODE (tem
) == USE
1608 || GET_CODE (tem
) == CLOBBER
)
1611 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1621 /* Return nonzero if register in range [REGNO, ENDREGNO)
1622 appears either explicitly or implicitly in X
1623 other than being stored into.
1625 References contained within the substructure at LOC do not count.
1626 LOC may be zero, meaning don't ignore anything. */
1629 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1633 unsigned int x_regno
;
1638 /* The contents of a REG_NONNEG note is always zero, so we must come here
1639 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1643 code
= GET_CODE (x
);
1648 x_regno
= REGNO (x
);
1650 /* If we modifying the stack, frame, or argument pointer, it will
1651 clobber a virtual register. In fact, we could be more precise,
1652 but it isn't worth it. */
1653 if ((x_regno
== STACK_POINTER_REGNUM
1654 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1655 && x_regno
== ARG_POINTER_REGNUM
)
1656 || x_regno
== FRAME_POINTER_REGNUM
)
1657 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1660 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1663 /* If this is a SUBREG of a hard reg, we can see exactly which
1664 registers are being modified. Otherwise, handle normally. */
1665 if (REG_P (SUBREG_REG (x
))
1666 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1668 unsigned int inner_regno
= subreg_regno (x
);
1669 unsigned int inner_endregno
1670 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1671 ? subreg_nregs (x
) : 1);
1673 return endregno
> inner_regno
&& regno
< inner_endregno
;
1679 if (&SET_DEST (x
) != loc
1680 /* Note setting a SUBREG counts as referring to the REG it is in for
1681 a pseudo but not for hard registers since we can
1682 treat each word individually. */
1683 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1684 && loc
!= &SUBREG_REG (SET_DEST (x
))
1685 && REG_P (SUBREG_REG (SET_DEST (x
)))
1686 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1687 && refers_to_regno_p (regno
, endregno
,
1688 SUBREG_REG (SET_DEST (x
)), loc
))
1689 || (!REG_P (SET_DEST (x
))
1690 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1693 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1702 /* X does not match, so try its subexpressions. */
1704 fmt
= GET_RTX_FORMAT (code
);
1705 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1707 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1715 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1718 else if (fmt
[i
] == 'E')
1721 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1722 if (loc
!= &XVECEXP (x
, i
, j
)
1723 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1730 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1731 we check if any register number in X conflicts with the relevant register
1732 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1733 contains a MEM (we don't bother checking for memory addresses that can't
1734 conflict because we expect this to be a rare case. */
1737 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1739 unsigned int regno
, endregno
;
1741 /* If either argument is a constant, then modifying X can not
1742 affect IN. Here we look at IN, we can profitably combine
1743 CONSTANT_P (x) with the switch statement below. */
1744 if (CONSTANT_P (in
))
1748 switch (GET_CODE (x
))
1750 case STRICT_LOW_PART
:
1753 /* Overly conservative. */
1758 regno
= REGNO (SUBREG_REG (x
));
1759 if (regno
< FIRST_PSEUDO_REGISTER
)
1760 regno
= subreg_regno (x
);
1761 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1762 ? subreg_nregs (x
) : 1);
1767 endregno
= END_REGNO (x
);
1769 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1779 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1780 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1783 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1786 else if (fmt
[i
] == 'E')
1789 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1790 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1800 return reg_mentioned_p (x
, in
);
1806 /* If any register in here refers to it we return true. */
1807 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1808 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1809 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1815 gcc_assert (CONSTANT_P (x
));
1820 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1821 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1822 ignored by note_stores, but passed to FUN.
1824 FUN receives three arguments:
1825 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1826 2. the SET or CLOBBER rtx that does the store,
1827 3. the pointer DATA provided to note_stores.
1829 If the item being stored in or clobbered is a SUBREG of a hard register,
1830 the SUBREG will be passed. */
1833 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1837 if (GET_CODE (x
) == COND_EXEC
)
1838 x
= COND_EXEC_CODE (x
);
1840 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1842 rtx dest
= SET_DEST (x
);
1844 while ((GET_CODE (dest
) == SUBREG
1845 && (!REG_P (SUBREG_REG (dest
))
1846 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1847 || GET_CODE (dest
) == ZERO_EXTRACT
1848 || GET_CODE (dest
) == STRICT_LOW_PART
)
1849 dest
= XEXP (dest
, 0);
1851 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1852 each of whose first operand is a register. */
1853 if (GET_CODE (dest
) == PARALLEL
)
1855 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1856 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1857 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1860 (*fun
) (dest
, x
, data
);
1863 else if (GET_CODE (x
) == PARALLEL
)
1864 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1865 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1868 /* Like notes_stores, but call FUN for each expression that is being
1869 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1870 FUN for each expression, not any interior subexpressions. FUN receives a
1871 pointer to the expression and the DATA passed to this function.
1873 Note that this is not quite the same test as that done in reg_referenced_p
1874 since that considers something as being referenced if it is being
1875 partially set, while we do not. */
1878 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1883 switch (GET_CODE (body
))
1886 (*fun
) (&COND_EXEC_TEST (body
), data
);
1887 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1891 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1892 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1896 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1897 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1901 (*fun
) (&XEXP (body
, 0), data
);
1905 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1906 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1910 (*fun
) (&TRAP_CONDITION (body
), data
);
1914 (*fun
) (&XEXP (body
, 0), data
);
1918 case UNSPEC_VOLATILE
:
1919 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1920 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1924 if (MEM_P (XEXP (body
, 0)))
1925 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1930 rtx dest
= SET_DEST (body
);
1932 /* For sets we replace everything in source plus registers in memory
1933 expression in store and operands of a ZERO_EXTRACT. */
1934 (*fun
) (&SET_SRC (body
), data
);
1936 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1938 (*fun
) (&XEXP (dest
, 1), data
);
1939 (*fun
) (&XEXP (dest
, 2), data
);
1942 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1943 dest
= XEXP (dest
, 0);
1946 (*fun
) (&XEXP (dest
, 0), data
);
1951 /* All the other possibilities never store. */
1952 (*fun
) (pbody
, data
);
1957 /* Return nonzero if X's old contents don't survive after INSN.
1958 This will be true if X is (cc0) or if X is a register and
1959 X dies in INSN or because INSN entirely sets X.
1961 "Entirely set" means set directly and not through a SUBREG, or
1962 ZERO_EXTRACT, so no trace of the old contents remains.
1963 Likewise, REG_INC does not count.
1965 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1966 but for this use that makes no difference, since regs don't overlap
1967 during their lifetimes. Therefore, this function may be used
1968 at any time after deaths have been computed.
1970 If REG is a hard reg that occupies multiple machine registers, this
1971 function will only return 1 if each of those registers will be replaced
1975 dead_or_set_p (const_rtx insn
, const_rtx x
)
1977 unsigned int regno
, end_regno
;
1980 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1981 if (GET_CODE (x
) == CC0
)
1984 gcc_assert (REG_P (x
));
1987 end_regno
= END_REGNO (x
);
1988 for (i
= regno
; i
< end_regno
; i
++)
1989 if (! dead_or_set_regno_p (insn
, i
))
1995 /* Return TRUE iff DEST is a register or subreg of a register and
1996 doesn't change the number of words of the inner register, and any
1997 part of the register is TEST_REGNO. */
2000 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2002 unsigned int regno
, endregno
;
2004 if (GET_CODE (dest
) == SUBREG
2005 && (((GET_MODE_SIZE (GET_MODE (dest
))
2006 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
2007 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
2008 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
2009 dest
= SUBREG_REG (dest
);
2014 regno
= REGNO (dest
);
2015 endregno
= END_REGNO (dest
);
2016 return (test_regno
>= regno
&& test_regno
< endregno
);
2019 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2020 any member matches the covers_regno_no_parallel_p criteria. */
2023 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2025 if (GET_CODE (dest
) == PARALLEL
)
2027 /* Some targets place small structures in registers for return
2028 values of functions, and those registers are wrapped in
2029 PARALLELs that we may see as the destination of a SET. */
2032 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2034 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2035 if (inner
!= NULL_RTX
2036 && covers_regno_no_parallel_p (inner
, test_regno
))
2043 return covers_regno_no_parallel_p (dest
, test_regno
);
2046 /* Utility function for dead_or_set_p to check an individual register. */
2049 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2053 /* See if there is a death note for something that includes TEST_REGNO. */
2054 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2058 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2061 pattern
= PATTERN (insn
);
2063 /* If a COND_EXEC is not executed, the value survives. */
2064 if (GET_CODE (pattern
) == COND_EXEC
)
2067 if (GET_CODE (pattern
) == SET
)
2068 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2069 else if (GET_CODE (pattern
) == PARALLEL
)
2073 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2075 rtx body
= XVECEXP (pattern
, 0, i
);
2077 if (GET_CODE (body
) == COND_EXEC
)
2078 body
= COND_EXEC_CODE (body
);
2080 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2081 && covers_regno_p (SET_DEST (body
), test_regno
))
2089 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2090 If DATUM is nonzero, look for one whose datum is DATUM. */
2093 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2097 gcc_checking_assert (insn
);
2099 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2100 if (! INSN_P (insn
))
2104 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2105 if (REG_NOTE_KIND (link
) == kind
)
2110 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2111 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2116 /* Return the reg-note of kind KIND in insn INSN which applies to register
2117 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2118 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2119 it might be the case that the note overlaps REGNO. */
2122 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2126 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2127 if (! INSN_P (insn
))
2130 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2131 if (REG_NOTE_KIND (link
) == kind
2132 /* Verify that it is a register, so that scratch and MEM won't cause a
2134 && REG_P (XEXP (link
, 0))
2135 && REGNO (XEXP (link
, 0)) <= regno
2136 && END_REGNO (XEXP (link
, 0)) > regno
)
2141 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2145 find_reg_equal_equiv_note (const_rtx insn
)
2152 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2153 if (REG_NOTE_KIND (link
) == REG_EQUAL
2154 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2156 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2157 insns that have multiple sets. Checking single_set to
2158 make sure of this is not the proper check, as explained
2159 in the comment in set_unique_reg_note.
2161 This should be changed into an assert. */
2162 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2169 /* Check whether INSN is a single_set whose source is known to be
2170 equivalent to a constant. Return that constant if so, otherwise
2174 find_constant_src (const rtx_insn
*insn
)
2178 set
= single_set (insn
);
2181 x
= avoid_constant_pool_reference (SET_SRC (set
));
2186 note
= find_reg_equal_equiv_note (insn
);
2187 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2188 return XEXP (note
, 0);
2193 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2194 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2197 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2199 /* If it's not a CALL_INSN, it can't possibly have a
2200 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2210 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2212 link
= XEXP (link
, 1))
2213 if (GET_CODE (XEXP (link
, 0)) == code
2214 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2219 unsigned int regno
= REGNO (datum
);
2221 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2222 to pseudo registers, so don't bother checking. */
2224 if (regno
< FIRST_PSEUDO_REGISTER
)
2226 unsigned int end_regno
= END_REGNO (datum
);
2229 for (i
= regno
; i
< end_regno
; i
++)
2230 if (find_regno_fusage (insn
, code
, i
))
2238 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2239 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2242 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2246 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2247 to pseudo registers, so don't bother checking. */
2249 if (regno
>= FIRST_PSEUDO_REGISTER
2253 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2257 if (GET_CODE (op
= XEXP (link
, 0)) == code
2258 && REG_P (reg
= XEXP (op
, 0))
2259 && REGNO (reg
) <= regno
2260 && END_REGNO (reg
) > regno
)
2268 /* Return true if KIND is an integer REG_NOTE. */
2271 int_reg_note_p (enum reg_note kind
)
2273 return kind
== REG_BR_PROB
;
2276 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2277 stored as the pointer to the next register note. */
2280 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2284 gcc_checking_assert (!int_reg_note_p (kind
));
2289 case REG_LABEL_TARGET
:
2290 case REG_LABEL_OPERAND
:
2292 /* These types of register notes use an INSN_LIST rather than an
2293 EXPR_LIST, so that copying is done right and dumps look
2295 note
= alloc_INSN_LIST (datum
, list
);
2296 PUT_REG_NOTE_KIND (note
, kind
);
2300 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2307 /* Add register note with kind KIND and datum DATUM to INSN. */
2310 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2312 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2315 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2318 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2320 gcc_checking_assert (int_reg_note_p (kind
));
2321 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2322 datum
, REG_NOTES (insn
));
2325 /* Add a register note like NOTE to INSN. */
2328 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2330 if (GET_CODE (note
) == INT_LIST
)
2331 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2333 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2336 /* Remove register note NOTE from the REG_NOTES of INSN. */
2339 remove_note (rtx insn
, const_rtx note
)
2343 if (note
== NULL_RTX
)
2346 if (REG_NOTES (insn
) == note
)
2347 REG_NOTES (insn
) = XEXP (note
, 1);
2349 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2350 if (XEXP (link
, 1) == note
)
2352 XEXP (link
, 1) = XEXP (note
, 1);
2356 switch (REG_NOTE_KIND (note
))
2360 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
2367 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2368 Return true if any note has been removed. */
2371 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2376 loc
= ®_NOTES (insn
);
2379 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2380 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2382 *loc
= XEXP (*loc
, 1);
2386 loc
= &XEXP (*loc
, 1);
2391 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2394 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2401 /* This loop is a little tricky. We cannot just go down the chain because
2402 it is being modified by some actions in the loop. So we just iterate
2403 over the head. We plan to drain the list anyway. */
2404 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2406 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2407 rtx note
= find_reg_equal_equiv_note (insn
);
2409 /* This assert is generally triggered when someone deletes a REG_EQUAL
2410 or REG_EQUIV note by hacking the list manually rather than calling
2414 remove_note (insn
, note
);
2418 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2419 return 1 if it is found. A simple equality test is used to determine if
2423 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2427 for (x
= listp
; x
; x
= XEXP (x
, 1))
2428 if (node
== XEXP (x
, 0))
2434 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2435 remove that entry from the list if it is found.
2437 A simple equality test is used to determine if NODE matches. */
2440 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2442 rtx_expr_list
*temp
= *listp
;
2443 rtx_expr_list
*prev
= NULL
;
2447 if (node
== temp
->element ())
2449 /* Splice the node out of the list. */
2451 XEXP (prev
, 1) = temp
->next ();
2453 *listp
= temp
->next ();
2459 temp
= temp
->next ();
2463 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2464 remove that entry from the list if it is found.
2466 A simple equality test is used to determine if NODE matches. */
2469 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2471 rtx_insn_list
*temp
= *listp
;
2472 rtx_insn_list
*prev
= NULL
;
2476 if (node
== temp
->insn ())
2478 /* Splice the node out of the list. */
2480 XEXP (prev
, 1) = temp
->next ();
2482 *listp
= temp
->next ();
2488 temp
= temp
->next ();
2492 /* Nonzero if X contains any volatile instructions. These are instructions
2493 which may cause unpredictable machine state instructions, and thus no
2494 instructions or register uses should be moved or combined across them.
2495 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2498 volatile_insn_p (const_rtx x
)
2500 const RTX_CODE code
= GET_CODE (x
);
2518 case UNSPEC_VOLATILE
:
2523 if (MEM_VOLATILE_P (x
))
2530 /* Recursively scan the operands of this expression. */
2533 const char *const fmt
= GET_RTX_FORMAT (code
);
2536 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2540 if (volatile_insn_p (XEXP (x
, i
)))
2543 else if (fmt
[i
] == 'E')
2546 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2547 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2555 /* Nonzero if X contains any volatile memory references
2556 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2559 volatile_refs_p (const_rtx x
)
2561 const RTX_CODE code
= GET_CODE (x
);
2577 case UNSPEC_VOLATILE
:
2583 if (MEM_VOLATILE_P (x
))
2590 /* Recursively scan the operands of this expression. */
2593 const char *const fmt
= GET_RTX_FORMAT (code
);
2596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2600 if (volatile_refs_p (XEXP (x
, i
)))
2603 else if (fmt
[i
] == 'E')
2606 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2607 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2615 /* Similar to above, except that it also rejects register pre- and post-
2619 side_effects_p (const_rtx x
)
2621 const RTX_CODE code
= GET_CODE (x
);
2638 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2639 when some combination can't be done. If we see one, don't think
2640 that we can simplify the expression. */
2641 return (GET_MODE (x
) != VOIDmode
);
2650 case UNSPEC_VOLATILE
:
2656 if (MEM_VOLATILE_P (x
))
2663 /* Recursively scan the operands of this expression. */
2666 const char *fmt
= GET_RTX_FORMAT (code
);
2669 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2673 if (side_effects_p (XEXP (x
, i
)))
2676 else if (fmt
[i
] == 'E')
2679 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2680 if (side_effects_p (XVECEXP (x
, i
, j
)))
2688 /* Return nonzero if evaluating rtx X might cause a trap.
2689 FLAGS controls how to consider MEMs. A nonzero means the context
2690 of the access may have changed from the original, such that the
2691 address may have become invalid. */
2694 may_trap_p_1 (const_rtx x
, unsigned flags
)
2700 /* We make no distinction currently, but this function is part of
2701 the internal target-hooks ABI so we keep the parameter as
2702 "unsigned flags". */
2703 bool code_changed
= flags
!= 0;
2707 code
= GET_CODE (x
);
2710 /* Handle these cases quickly. */
2722 return targetm
.unspec_may_trap_p (x
, flags
);
2724 case UNSPEC_VOLATILE
:
2730 return MEM_VOLATILE_P (x
);
2732 /* Memory ref can trap unless it's a static var or a stack slot. */
2734 /* Recognize specific pattern of stack checking probes. */
2735 if (flag_stack_check
2736 && MEM_VOLATILE_P (x
)
2737 && XEXP (x
, 0) == stack_pointer_rtx
)
2739 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2740 reference; moving it out of context such as when moving code
2741 when optimizing, might cause its address to become invalid. */
2743 || !MEM_NOTRAP_P (x
))
2745 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2746 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2747 GET_MODE (x
), code_changed
);
2752 /* Division by a non-constant might trap. */
2757 if (HONOR_SNANS (x
))
2759 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2760 return flag_trapping_math
;
2761 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2766 /* An EXPR_LIST is used to represent a function call. This
2767 certainly may trap. */
2776 /* Some floating point comparisons may trap. */
2777 if (!flag_trapping_math
)
2779 /* ??? There is no machine independent way to check for tests that trap
2780 when COMPARE is used, though many targets do make this distinction.
2781 For instance, sparc uses CCFPE for compares which generate exceptions
2782 and CCFP for compares which do not generate exceptions. */
2785 /* But often the compare has some CC mode, so check operand
2787 if (HONOR_NANS (XEXP (x
, 0))
2788 || HONOR_NANS (XEXP (x
, 1)))
2794 if (HONOR_SNANS (x
))
2796 /* Often comparison is CC mode, so check operand modes. */
2797 if (HONOR_SNANS (XEXP (x
, 0))
2798 || HONOR_SNANS (XEXP (x
, 1)))
2803 /* Conversion of floating point might trap. */
2804 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2811 /* These operations don't trap even with floating point. */
2815 /* Any floating arithmetic may trap. */
2816 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2820 fmt
= GET_RTX_FORMAT (code
);
2821 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2825 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2828 else if (fmt
[i
] == 'E')
2831 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2832 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2839 /* Return nonzero if evaluating rtx X might cause a trap. */
2842 may_trap_p (const_rtx x
)
2844 return may_trap_p_1 (x
, 0);
2847 /* Same as above, but additionally return nonzero if evaluating rtx X might
2848 cause a fault. We define a fault for the purpose of this function as a
2849 erroneous execution condition that cannot be encountered during the normal
2850 execution of a valid program; the typical example is an unaligned memory
2851 access on a strict alignment machine. The compiler guarantees that it
2852 doesn't generate code that will fault from a valid program, but this
2853 guarantee doesn't mean anything for individual instructions. Consider
2854 the following example:
2856 struct S { int d; union { char *cp; int *ip; }; };
2858 int foo(struct S *s)
2866 on a strict alignment machine. In a valid program, foo will never be
2867 invoked on a structure for which d is equal to 1 and the underlying
2868 unique field of the union not aligned on a 4-byte boundary, but the
2869 expression *s->ip might cause a fault if considered individually.
2871 At the RTL level, potentially problematic expressions will almost always
2872 verify may_trap_p; for example, the above dereference can be emitted as
2873 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2874 However, suppose that foo is inlined in a caller that causes s->cp to
2875 point to a local character variable and guarantees that s->d is not set
2876 to 1; foo may have been effectively translated into pseudo-RTL as:
2879 (set (reg:SI) (mem:SI (%fp - 7)))
2881 (set (reg:QI) (mem:QI (%fp - 7)))
2883 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2884 memory reference to a stack slot, but it will certainly cause a fault
2885 on a strict alignment machine. */
2888 may_trap_or_fault_p (const_rtx x
)
2890 return may_trap_p_1 (x
, 1);
2893 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2894 i.e., an inequality. */
2897 inequality_comparisons_p (const_rtx x
)
2901 const enum rtx_code code
= GET_CODE (x
);
2929 len
= GET_RTX_LENGTH (code
);
2930 fmt
= GET_RTX_FORMAT (code
);
2932 for (i
= 0; i
< len
; i
++)
2936 if (inequality_comparisons_p (XEXP (x
, i
)))
2939 else if (fmt
[i
] == 'E')
2942 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2943 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2951 /* Replace any occurrence of FROM in X with TO. The function does
2952 not enter into CONST_DOUBLE for the replace.
2954 Note that copying is not done so X must not be shared unless all copies
2957 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
2958 those pointer-equal ones. */
2961 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
2969 /* Allow this function to make replacements in EXPR_LISTs. */
2976 && REGNO (x
) == REGNO (from
))
2978 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2981 else if (GET_CODE (x
) == SUBREG
)
2983 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
2985 if (CONST_INT_P (new_rtx
))
2987 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2988 GET_MODE (SUBREG_REG (x
)),
2993 SUBREG_REG (x
) = new_rtx
;
2997 else if (GET_CODE (x
) == ZERO_EXTEND
)
2999 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3001 if (CONST_INT_P (new_rtx
))
3003 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3004 new_rtx
, GET_MODE (XEXP (x
, 0)));
3008 XEXP (x
, 0) = new_rtx
;
3013 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3014 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3017 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3018 else if (fmt
[i
] == 'E')
3019 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3020 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3021 from
, to
, all_regs
);
3027 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3028 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3031 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3033 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3035 if (JUMP_TABLE_DATA_P (x
))
3038 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3039 int len
= GET_NUM_ELEM (vec
);
3040 for (int i
= 0; i
< len
; ++i
)
3042 rtx ref
= RTVEC_ELT (vec
, i
);
3043 if (XEXP (ref
, 0) == old_label
)
3045 XEXP (ref
, 0) = new_label
;
3046 if (update_label_nuses
)
3048 ++LABEL_NUSES (new_label
);
3049 --LABEL_NUSES (old_label
);
3056 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3057 field. This is not handled by the iterator because it doesn't
3058 handle unprinted ('0') fields. */
3059 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3060 JUMP_LABEL (x
) = new_label
;
3062 subrtx_ptr_iterator::array_type array
;
3063 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3068 if (GET_CODE (x
) == SYMBOL_REF
3069 && CONSTANT_POOL_ADDRESS_P (x
))
3071 rtx c
= get_pool_constant (x
);
3072 if (rtx_referenced_p (old_label
, c
))
3074 /* Create a copy of constant C; replace the label inside
3075 but do not update LABEL_NUSES because uses in constant pool
3077 rtx new_c
= copy_rtx (c
);
3078 replace_label (&new_c
, old_label
, new_label
, false);
3080 /* Add the new constant NEW_C to constant pool and replace
3081 the old reference to constant by new reference. */
3082 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3083 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3087 if ((GET_CODE (x
) == LABEL_REF
3088 || GET_CODE (x
) == INSN_LIST
)
3089 && XEXP (x
, 0) == old_label
)
3091 XEXP (x
, 0) = new_label
;
3092 if (update_label_nuses
)
3094 ++LABEL_NUSES (new_label
);
3095 --LABEL_NUSES (old_label
);
3103 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3104 bool update_label_nuses
)
3106 rtx insn_as_rtx
= insn
;
3107 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3108 gcc_checking_assert (insn_as_rtx
== insn
);
3111 /* Return true if X is referenced in BODY. */
3114 rtx_referenced_p (const_rtx x
, const_rtx body
)
3116 subrtx_iterator::array_type array
;
3117 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3118 if (const_rtx y
= *iter
)
3120 /* Check if a label_ref Y refers to label X. */
3121 if (GET_CODE (y
) == LABEL_REF
3123 && LABEL_REF_LABEL (y
) == x
)
3126 if (rtx_equal_p (x
, y
))
3129 /* If Y is a reference to pool constant traverse the constant. */
3130 if (GET_CODE (y
) == SYMBOL_REF
3131 && CONSTANT_POOL_ADDRESS_P (y
))
3132 iter
.substitute (get_pool_constant (y
));
3137 /* If INSN is a tablejump return true and store the label (before jump table) to
3138 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3141 tablejump_p (const rtx_insn
*insn
, rtx
*labelp
, rtx_jump_table_data
**tablep
)
3149 label
= JUMP_LABEL (insn
);
3150 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
3151 && (table
= NEXT_INSN (as_a
<rtx_insn
*> (label
))) != NULL_RTX
3152 && JUMP_TABLE_DATA_P (table
))
3157 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3163 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3164 constant that is not in the constant pool and not in the condition
3165 of an IF_THEN_ELSE. */
3168 computed_jump_p_1 (const_rtx x
)
3170 const enum rtx_code code
= GET_CODE (x
);
3187 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3188 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3191 return (computed_jump_p_1 (XEXP (x
, 1))
3192 || computed_jump_p_1 (XEXP (x
, 2)));
3198 fmt
= GET_RTX_FORMAT (code
);
3199 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3202 && computed_jump_p_1 (XEXP (x
, i
)))
3205 else if (fmt
[i
] == 'E')
3206 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3207 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3214 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3216 Tablejumps and casesi insns are not considered indirect jumps;
3217 we can recognize them by a (use (label_ref)). */
3220 computed_jump_p (const rtx_insn
*insn
)
3225 rtx pat
= PATTERN (insn
);
3227 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3228 if (JUMP_LABEL (insn
) != NULL
)
3231 if (GET_CODE (pat
) == PARALLEL
)
3233 int len
= XVECLEN (pat
, 0);
3234 int has_use_labelref
= 0;
3236 for (i
= len
- 1; i
>= 0; i
--)
3237 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3238 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3241 has_use_labelref
= 1;
3245 if (! has_use_labelref
)
3246 for (i
= len
- 1; i
>= 0; i
--)
3247 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3248 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3249 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3252 else if (GET_CODE (pat
) == SET
3253 && SET_DEST (pat
) == pc_rtx
3254 && computed_jump_p_1 (SET_SRC (pat
)))
3262 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3263 the equivalent add insn and pass the result to FN, using DATA as the
3267 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3269 rtx x
= XEXP (mem
, 0);
3270 switch (GET_CODE (x
))
3275 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3276 rtx r1
= XEXP (x
, 0);
3277 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3278 return fn (mem
, x
, r1
, r1
, c
, data
);
3284 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3285 rtx r1
= XEXP (x
, 0);
3286 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3287 return fn (mem
, x
, r1
, r1
, c
, data
);
3293 rtx r1
= XEXP (x
, 0);
3294 rtx add
= XEXP (x
, 1);
3295 return fn (mem
, x
, r1
, add
, NULL
, data
);
3303 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3304 For each such autoinc operation found, call FN, passing it
3305 the innermost enclosing MEM, the operation itself, the RTX modified
3306 by the operation, two RTXs (the second may be NULL) that, once
3307 added, represent the value to be held by the modified RTX
3308 afterwards, and DATA. FN is to return 0 to continue the
3309 traversal or any other value to have it returned to the caller of
3310 for_each_inc_dec. */
3313 for_each_inc_dec (rtx x
,
3314 for_each_inc_dec_fn fn
,
3317 subrtx_var_iterator::array_type array
;
3318 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3323 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3325 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3328 iter
.skip_subrtxes ();
3335 /* Searches X for any reference to REGNO, returning the rtx of the
3336 reference found if any. Otherwise, returns NULL_RTX. */
3339 regno_use_in (unsigned int regno
, rtx x
)
3345 if (REG_P (x
) && REGNO (x
) == regno
)
3348 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3349 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3353 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3356 else if (fmt
[i
] == 'E')
3357 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3358 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3365 /* Return a value indicating whether OP, an operand of a commutative
3366 operation, is preferred as the first or second operand. The more
3367 positive the value, the stronger the preference for being the first
3371 commutative_operand_precedence (rtx op
)
3373 enum rtx_code code
= GET_CODE (op
);
3375 /* Constants always become the second operand. Prefer "nice" constants. */
3376 if (code
== CONST_INT
)
3378 if (code
== CONST_WIDE_INT
)
3380 if (code
== CONST_DOUBLE
)
3382 if (code
== CONST_FIXED
)
3384 op
= avoid_constant_pool_reference (op
);
3385 code
= GET_CODE (op
);
3387 switch (GET_RTX_CLASS (code
))
3390 if (code
== CONST_INT
)
3392 if (code
== CONST_WIDE_INT
)
3394 if (code
== CONST_DOUBLE
)
3396 if (code
== CONST_FIXED
)
3401 /* SUBREGs of objects should come second. */
3402 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3407 /* Complex expressions should be the first, so decrease priority
3408 of objects. Prefer pointer objects over non pointer objects. */
3409 if ((REG_P (op
) && REG_POINTER (op
))
3410 || (MEM_P (op
) && MEM_POINTER (op
)))
3414 case RTX_COMM_ARITH
:
3415 /* Prefer operands that are themselves commutative to be first.
3416 This helps to make things linear. In particular,
3417 (and (and (reg) (reg)) (not (reg))) is canonical. */
3421 /* If only one operand is a binary expression, it will be the first
3422 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3423 is canonical, although it will usually be further simplified. */
3427 /* Then prefer NEG and NOT. */
3428 if (code
== NEG
|| code
== NOT
)
3436 /* Return 1 iff it is necessary to swap operands of commutative operation
3437 in order to canonicalize expression. */
3440 swap_commutative_operands_p (rtx x
, rtx y
)
3442 return (commutative_operand_precedence (x
)
3443 < commutative_operand_precedence (y
));
3446 /* Return 1 if X is an autoincrement side effect and the register is
3447 not the stack pointer. */
3449 auto_inc_p (const_rtx x
)
3451 switch (GET_CODE (x
))
3459 /* There are no REG_INC notes for SP. */
3460 if (XEXP (x
, 0) != stack_pointer_rtx
)
3468 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3470 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3479 code
= GET_CODE (in
);
3480 fmt
= GET_RTX_FORMAT (code
);
3481 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3485 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3488 else if (fmt
[i
] == 'E')
3489 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3490 if (loc
== &XVECEXP (in
, i
, j
)
3491 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3497 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3498 and SUBREG_BYTE, return the bit offset where the subreg begins
3499 (counting from the least significant bit of the operand). */
3502 subreg_lsb_1 (machine_mode outer_mode
,
3503 machine_mode inner_mode
,
3504 unsigned int subreg_byte
)
3506 unsigned int bitpos
;
3510 /* A paradoxical subreg begins at bit position 0. */
3511 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3514 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3515 /* If the subreg crosses a word boundary ensure that
3516 it also begins and ends on a word boundary. */
3517 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3518 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3519 && (subreg_byte
% UNITS_PER_WORD
3520 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3522 if (WORDS_BIG_ENDIAN
)
3523 word
= (GET_MODE_SIZE (inner_mode
)
3524 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3526 word
= subreg_byte
/ UNITS_PER_WORD
;
3527 bitpos
= word
* BITS_PER_WORD
;
3529 if (BYTES_BIG_ENDIAN
)
3530 byte
= (GET_MODE_SIZE (inner_mode
)
3531 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3533 byte
= subreg_byte
% UNITS_PER_WORD
;
3534 bitpos
+= byte
* BITS_PER_UNIT
;
3539 /* Given a subreg X, return the bit offset where the subreg begins
3540 (counting from the least significant bit of the reg). */
3543 subreg_lsb (const_rtx x
)
3545 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3549 /* Fill in information about a subreg of a hard register.
3550 xregno - A regno of an inner hard subreg_reg (or what will become one).
3551 xmode - The mode of xregno.
3552 offset - The byte offset.
3553 ymode - The mode of a top level SUBREG (or what may become one).
3554 info - Pointer to structure to fill in.
3556 Rather than considering one particular inner register (and thus one
3557 particular "outer" register) in isolation, this function really uses
3558 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3559 function does not check whether adding INFO->offset to XREGNO gives
3560 a valid hard register; even if INFO->offset + XREGNO is out of range,
3561 there might be another register of the same type that is in range.
3562 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3563 register, since that can depend on things like whether the final
3564 register number is even or odd. Callers that want to check whether
3565 this particular subreg can be replaced by a simple (reg ...) should
3566 use simplify_subreg_regno. */
3569 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3570 unsigned int offset
, machine_mode ymode
,
3571 struct subreg_info
*info
)
3573 int nregs_xmode
, nregs_ymode
;
3574 int mode_multiple
, nregs_multiple
;
3575 int offset_adj
, y_offset
, y_offset_adj
;
3576 int regsize_xmode
, regsize_ymode
;
3579 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3583 /* If there are holes in a non-scalar mode in registers, we expect
3584 that it is made up of its units concatenated together. */
3585 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3587 machine_mode xmode_unit
;
3589 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3590 xmode_unit
= GET_MODE_INNER (xmode
);
3591 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3592 gcc_assert (nregs_xmode
3593 == (GET_MODE_NUNITS (xmode
)
3594 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3595 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3596 == (hard_regno_nregs
[xregno
][xmode_unit
]
3597 * GET_MODE_NUNITS (xmode
)));
3599 /* You can only ask for a SUBREG of a value with holes in the middle
3600 if you don't cross the holes. (Such a SUBREG should be done by
3601 picking a different register class, or doing it in memory if
3602 necessary.) An example of a value with holes is XCmode on 32-bit
3603 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3604 3 for each part, but in memory it's two 128-bit parts.
3605 Padding is assumed to be at the end (not necessarily the 'high part')
3607 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3608 < GET_MODE_NUNITS (xmode
))
3609 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3610 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3611 / GET_MODE_SIZE (xmode_unit
))))
3613 info
->representable_p
= false;
3618 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3620 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3622 /* Paradoxical subregs are otherwise valid. */
3625 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3627 info
->representable_p
= true;
3628 /* If this is a big endian paradoxical subreg, which uses more
3629 actual hard registers than the original register, we must
3630 return a negative offset so that we find the proper highpart
3632 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3633 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3634 info
->offset
= nregs_xmode
- nregs_ymode
;
3637 info
->nregs
= nregs_ymode
;
3641 /* If registers store different numbers of bits in the different
3642 modes, we cannot generally form this subreg. */
3643 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3644 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3645 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3646 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3648 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3649 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3650 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3652 info
->representable_p
= false;
3654 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3655 info
->offset
= offset
/ regsize_xmode
;
3658 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3660 info
->representable_p
= false;
3662 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3663 info
->offset
= offset
/ regsize_xmode
;
3666 /* Quick exit for the simple and common case of extracting whole
3667 subregisters from a multiregister value. */
3668 /* ??? It would be better to integrate this into the code below,
3669 if we can generalize the concept enough and figure out how
3670 odd-sized modes can coexist with the other weird cases we support. */
3672 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3673 && regsize_xmode
== regsize_ymode
3674 && (offset
% regsize_ymode
) == 0)
3676 info
->representable_p
= true;
3677 info
->nregs
= nregs_ymode
;
3678 info
->offset
= offset
/ regsize_ymode
;
3679 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3684 /* Lowpart subregs are otherwise valid. */
3685 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3687 info
->representable_p
= true;
3690 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3693 info
->nregs
= nregs_ymode
;
3698 /* This should always pass, otherwise we don't know how to verify
3699 the constraint. These conditions may be relaxed but
3700 subreg_regno_offset would need to be redesigned. */
3701 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3702 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3704 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3705 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3707 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3708 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3709 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3710 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3711 offset
= (xsize
- ysize
- off_high
) | off_low
;
3713 /* The XMODE value can be seen as a vector of NREGS_XMODE
3714 values. The subreg must represent a lowpart of given field.
3715 Compute what field it is. */
3716 offset_adj
= offset
;
3717 offset_adj
-= subreg_lowpart_offset (ymode
,
3718 mode_for_size (GET_MODE_BITSIZE (xmode
)
3722 /* Size of ymode must not be greater than the size of xmode. */
3723 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3724 gcc_assert (mode_multiple
!= 0);
3726 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3727 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3728 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3730 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3731 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3735 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3738 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3739 info
->nregs
= nregs_ymode
;
3742 /* This function returns the regno offset of a subreg expression.
3743 xregno - A regno of an inner hard subreg_reg (or what will become one).
3744 xmode - The mode of xregno.
3745 offset - The byte offset.
3746 ymode - The mode of a top level SUBREG (or what may become one).
3747 RETURN - The regno offset which would be used. */
3749 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3750 unsigned int offset
, machine_mode ymode
)
3752 struct subreg_info info
;
3753 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3757 /* This function returns true when the offset is representable via
3758 subreg_offset in the given regno.
3759 xregno - A regno of an inner hard subreg_reg (or what will become one).
3760 xmode - The mode of xregno.
3761 offset - The byte offset.
3762 ymode - The mode of a top level SUBREG (or what may become one).
3763 RETURN - Whether the offset is representable. */
3765 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3766 unsigned int offset
, machine_mode ymode
)
3768 struct subreg_info info
;
3769 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3770 return info
.representable_p
;
3773 /* Return the number of a YMODE register to which
3775 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3777 can be simplified. Return -1 if the subreg can't be simplified.
3779 XREGNO is a hard register number. */
3782 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3783 unsigned int offset
, machine_mode ymode
)
3785 struct subreg_info info
;
3786 unsigned int yregno
;
3788 #ifdef CANNOT_CHANGE_MODE_CLASS
3789 /* Give the backend a chance to disallow the mode change. */
3790 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3791 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3792 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3793 /* We can use mode change in LRA for some transformations. */
3794 && ! lra_in_progress
)
3798 /* We shouldn't simplify stack-related registers. */
3799 if ((!reload_completed
|| frame_pointer_needed
)
3800 && xregno
== FRAME_POINTER_REGNUM
)
3803 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3804 && xregno
== ARG_POINTER_REGNUM
)
3807 if (xregno
== STACK_POINTER_REGNUM
3808 /* We should convert hard stack register in LRA if it is
3810 && ! lra_in_progress
)
3813 /* Try to get the register offset. */
3814 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3815 if (!info
.representable_p
)
3818 /* Make sure that the offsetted register value is in range. */
3819 yregno
= xregno
+ info
.offset
;
3820 if (!HARD_REGISTER_NUM_P (yregno
))
3823 /* See whether (reg:YMODE YREGNO) is valid.
3825 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3826 This is a kludge to work around how complex FP arguments are passed
3827 on IA-64 and should be fixed. See PR target/49226. */
3828 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3829 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3832 return (int) yregno
;
3835 /* Return the final regno that a subreg expression refers to. */
3837 subreg_regno (const_rtx x
)
3840 rtx subreg
= SUBREG_REG (x
);
3841 int regno
= REGNO (subreg
);
3843 ret
= regno
+ subreg_regno_offset (regno
,
3851 /* Return the number of registers that a subreg expression refers
3854 subreg_nregs (const_rtx x
)
3856 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3859 /* Return the number of registers that a subreg REG with REGNO
3860 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3861 changed so that the regno can be passed in. */
3864 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3866 struct subreg_info info
;
3867 rtx subreg
= SUBREG_REG (x
);
3869 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3875 struct parms_set_data
3881 /* Helper function for noticing stores to parameter registers. */
3883 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3885 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3886 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3887 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3889 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3894 /* Look backward for first parameter to be loaded.
3895 Note that loads of all parameters will not necessarily be
3896 found if CSE has eliminated some of them (e.g., an argument
3897 to the outer function is passed down as a parameter).
3898 Do not skip BOUNDARY. */
3900 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3902 struct parms_set_data parm
;
3904 rtx_insn
*before
, *first_set
;
3906 /* Since different machines initialize their parameter registers
3907 in different orders, assume nothing. Collect the set of all
3908 parameter registers. */
3909 CLEAR_HARD_REG_SET (parm
.regs
);
3911 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3912 if (GET_CODE (XEXP (p
, 0)) == USE
3913 && REG_P (XEXP (XEXP (p
, 0), 0)))
3915 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3917 /* We only care about registers which can hold function
3919 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3922 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3926 first_set
= call_insn
;
3928 /* Search backward for the first set of a register in this set. */
3929 while (parm
.nregs
&& before
!= boundary
)
3931 before
= PREV_INSN (before
);
3933 /* It is possible that some loads got CSEed from one call to
3934 another. Stop in that case. */
3935 if (CALL_P (before
))
3938 /* Our caller needs either ensure that we will find all sets
3939 (in case code has not been optimized yet), or take care
3940 for possible labels in a way by setting boundary to preceding
3942 if (LABEL_P (before
))
3944 gcc_assert (before
== boundary
);
3948 if (INSN_P (before
))
3950 int nregs_old
= parm
.nregs
;
3951 note_stores (PATTERN (before
), parms_set
, &parm
);
3952 /* If we found something that did not set a parameter reg,
3953 we're done. Do not keep going, as that might result
3954 in hoisting an insn before the setting of a pseudo
3955 that is used by the hoisted insn. */
3956 if (nregs_old
!= parm
.nregs
)
3965 /* Return true if we should avoid inserting code between INSN and preceding
3966 call instruction. */
3969 keep_with_call_p (const rtx_insn
*insn
)
3973 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3975 if (REG_P (SET_DEST (set
))
3976 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3977 && fixed_regs
[REGNO (SET_DEST (set
))]
3978 && general_operand (SET_SRC (set
), VOIDmode
))
3980 if (REG_P (SET_SRC (set
))
3981 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3982 && REG_P (SET_DEST (set
))
3983 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3985 /* There may be a stack pop just after the call and before the store
3986 of the return register. Search for the actual store when deciding
3987 if we can break or not. */
3988 if (SET_DEST (set
) == stack_pointer_rtx
)
3990 /* This CONST_CAST is okay because next_nonnote_insn just
3991 returns its argument and we assign it to a const_rtx
3994 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3995 if (i2
&& keep_with_call_p (i2
))
4002 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4003 to non-complex jumps. That is, direct unconditional, conditional,
4004 and tablejumps, but not computed jumps or returns. It also does
4005 not apply to the fallthru case of a conditional jump. */
4008 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4010 rtx tmp
= JUMP_LABEL (jump_insn
);
4011 rtx_jump_table_data
*table
;
4016 if (tablejump_p (jump_insn
, NULL
, &table
))
4018 rtvec vec
= table
->get_labels ();
4019 int i
, veclen
= GET_NUM_ELEM (vec
);
4021 for (i
= 0; i
< veclen
; ++i
)
4022 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4026 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4033 /* Return an estimate of the cost of computing rtx X.
4034 One use is in cse, to decide which expression to keep in the hash table.
4035 Another is in rtl generation, to pick the cheapest way to multiply.
4036 Other uses like the latter are expected in the future.
4038 X appears as operand OPNO in an expression with code OUTER_CODE.
4039 SPEED specifies whether costs optimized for speed or size should
4043 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4044 int opno
, bool speed
)
4055 if (GET_MODE (x
) != VOIDmode
)
4056 mode
= GET_MODE (x
);
4058 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4059 many insns, taking N times as long. */
4060 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4064 /* Compute the default costs of certain things.
4065 Note that targetm.rtx_costs can override the defaults. */
4067 code
= GET_CODE (x
);
4071 /* Multiplication has time-complexity O(N*N), where N is the
4072 number of units (translated from digits) when using
4073 schoolbook long multiplication. */
4074 total
= factor
* factor
* COSTS_N_INSNS (5);
4080 /* Similarly, complexity for schoolbook long division. */
4081 total
= factor
* factor
* COSTS_N_INSNS (7);
4084 /* Used in combine.c as a marker. */
4088 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4089 the mode for the factor. */
4090 mode
= GET_MODE (SET_DEST (x
));
4091 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4096 total
= factor
* COSTS_N_INSNS (1);
4106 /* If we can't tie these modes, make this expensive. The larger
4107 the mode, the more expensive it is. */
4108 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4109 return COSTS_N_INSNS (2 + factor
);
4113 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4118 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4119 which is already in total. */
4121 fmt
= GET_RTX_FORMAT (code
);
4122 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4124 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4125 else if (fmt
[i
] == 'E')
4126 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4127 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4132 /* Fill in the structure C with information about both speed and size rtx
4133 costs for X, which is operand OPNO in an expression with code OUTER. */
4136 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4137 struct full_rtx_costs
*c
)
4139 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4140 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4144 /* Return cost of address expression X.
4145 Expect that X is properly formed address reference.
4147 SPEED parameter specify whether costs optimized for speed or size should
4151 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4153 /* We may be asked for cost of various unusual addresses, such as operands
4154 of push instruction. It is not worthwhile to complicate writing
4155 of the target hook by such cases. */
4157 if (!memory_address_addr_space_p (mode
, x
, as
))
4160 return targetm
.address_cost (x
, mode
, as
, speed
);
4163 /* If the target doesn't override, compute the cost as with arithmetic. */
4166 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4168 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4172 unsigned HOST_WIDE_INT
4173 nonzero_bits (const_rtx x
, machine_mode mode
)
4175 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4179 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4181 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4184 /* Return true if nonzero_bits1 might recurse into both operands
4188 nonzero_bits_binary_arith_p (const_rtx x
)
4190 if (!ARITHMETIC_P (x
))
4192 switch (GET_CODE (x
))
4214 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4215 It avoids exponential behavior in nonzero_bits1 when X has
4216 identical subexpressions on the first or the second level. */
4218 static unsigned HOST_WIDE_INT
4219 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4220 machine_mode known_mode
,
4221 unsigned HOST_WIDE_INT known_ret
)
4223 if (x
== known_x
&& mode
== known_mode
)
4226 /* Try to find identical subexpressions. If found call
4227 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4228 precomputed value for the subexpression as KNOWN_RET. */
4230 if (nonzero_bits_binary_arith_p (x
))
4232 rtx x0
= XEXP (x
, 0);
4233 rtx x1
= XEXP (x
, 1);
4235 /* Check the first level. */
4237 return nonzero_bits1 (x
, mode
, x0
, mode
,
4238 cached_nonzero_bits (x0
, mode
, known_x
,
4239 known_mode
, known_ret
));
4241 /* Check the second level. */
4242 if (nonzero_bits_binary_arith_p (x0
)
4243 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4244 return nonzero_bits1 (x
, mode
, x1
, mode
,
4245 cached_nonzero_bits (x1
, mode
, known_x
,
4246 known_mode
, known_ret
));
4248 if (nonzero_bits_binary_arith_p (x1
)
4249 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4250 return nonzero_bits1 (x
, mode
, x0
, mode
,
4251 cached_nonzero_bits (x0
, mode
, known_x
,
4252 known_mode
, known_ret
));
4255 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4258 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4259 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4260 is less useful. We can't allow both, because that results in exponential
4261 run time recursion. There is a nullstone testcase that triggered
4262 this. This macro avoids accidental uses of num_sign_bit_copies. */
4263 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4265 /* Given an expression, X, compute which bits in X can be nonzero.
4266 We don't care about bits outside of those defined in MODE.
4268 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4269 an arithmetic operation, we can do better. */
4271 static unsigned HOST_WIDE_INT
4272 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4273 machine_mode known_mode
,
4274 unsigned HOST_WIDE_INT known_ret
)
4276 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4277 unsigned HOST_WIDE_INT inner_nz
;
4279 machine_mode inner_mode
;
4280 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4282 /* For floating-point and vector values, assume all bits are needed. */
4283 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4284 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4287 /* If X is wider than MODE, use its mode instead. */
4288 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4290 mode
= GET_MODE (x
);
4291 nonzero
= GET_MODE_MASK (mode
);
4292 mode_width
= GET_MODE_PRECISION (mode
);
4295 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4296 /* Our only callers in this case look for single bit values. So
4297 just return the mode mask. Those tests will then be false. */
4300 /* If MODE is wider than X, but both are a single word for both the host
4301 and target machines, we can compute this from which bits of the
4302 object might be nonzero in its own mode, taking into account the fact
4303 that on many CISC machines, accessing an object in a wider mode
4304 causes the high-order bits to become undefined. So they are
4305 not known to be zero. */
4307 if (!WORD_REGISTER_OPERATIONS
4308 && GET_MODE (x
) != VOIDmode
4309 && GET_MODE (x
) != mode
4310 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4311 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4312 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4314 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4315 known_x
, known_mode
, known_ret
);
4316 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4320 /* Please keep nonzero_bits_binary_arith_p above in sync with
4321 the code in the switch below. */
4322 code
= GET_CODE (x
);
4326 #if defined(POINTERS_EXTEND_UNSIGNED)
4327 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4328 all the bits above ptr_mode are known to be zero. */
4329 /* As we do not know which address space the pointer is referring to,
4330 we can do this only if the target does not support different pointer
4331 or address modes depending on the address space. */
4332 if (target_default_pointer_address_modes_p ()
4333 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4335 && !targetm
.have_ptr_extend ())
4336 nonzero
&= GET_MODE_MASK (ptr_mode
);
4339 /* Include declared information about alignment of pointers. */
4340 /* ??? We don't properly preserve REG_POINTER changes across
4341 pointer-to-integer casts, so we can't trust it except for
4342 things that we know must be pointers. See execute/960116-1.c. */
4343 if ((x
== stack_pointer_rtx
4344 || x
== frame_pointer_rtx
4345 || x
== arg_pointer_rtx
)
4346 && REGNO_POINTER_ALIGN (REGNO (x
)))
4348 unsigned HOST_WIDE_INT alignment
4349 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4351 #ifdef PUSH_ROUNDING
4352 /* If PUSH_ROUNDING is defined, it is possible for the
4353 stack to be momentarily aligned only to that amount,
4354 so we pick the least alignment. */
4355 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4356 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4360 nonzero
&= ~(alignment
- 1);
4364 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4365 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4366 known_mode
, known_ret
,
4370 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4371 known_mode
, known_ret
);
4373 return nonzero_for_hook
;
4377 /* If X is negative in MODE, sign-extend the value. */
4378 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4379 && mode_width
< BITS_PER_WORD
4380 && (UINTVAL (x
) & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
4382 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4387 #ifdef LOAD_EXTEND_OP
4388 /* In many, if not most, RISC machines, reading a byte from memory
4389 zeros the rest of the register. Noticing that fact saves a lot
4390 of extra zero-extends. */
4391 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4392 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4397 case UNEQ
: case LTGT
:
4398 case GT
: case GTU
: case UNGT
:
4399 case LT
: case LTU
: case UNLT
:
4400 case GE
: case GEU
: case UNGE
:
4401 case LE
: case LEU
: case UNLE
:
4402 case UNORDERED
: case ORDERED
:
4403 /* If this produces an integer result, we know which bits are set.
4404 Code here used to clear bits outside the mode of X, but that is
4406 /* Mind that MODE is the mode the caller wants to look at this
4407 operation in, and not the actual operation mode. We can wind
4408 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4409 that describes the results of a vector compare. */
4410 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4411 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4412 nonzero
= STORE_FLAG_VALUE
;
4417 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4418 and num_sign_bit_copies. */
4419 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4420 == GET_MODE_PRECISION (GET_MODE (x
)))
4424 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4425 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4430 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4431 and num_sign_bit_copies. */
4432 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4433 == GET_MODE_PRECISION (GET_MODE (x
)))
4439 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4440 known_x
, known_mode
, known_ret
)
4441 & GET_MODE_MASK (mode
));
4445 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4446 known_x
, known_mode
, known_ret
);
4447 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4448 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4452 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4453 Otherwise, show all the bits in the outer mode but not the inner
4455 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4456 known_x
, known_mode
, known_ret
);
4457 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4459 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4460 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4461 inner_nz
|= (GET_MODE_MASK (mode
)
4462 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4465 nonzero
&= inner_nz
;
4469 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4470 known_x
, known_mode
, known_ret
)
4471 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4472 known_x
, known_mode
, known_ret
);
4476 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4478 unsigned HOST_WIDE_INT nonzero0
4479 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4480 known_x
, known_mode
, known_ret
);
4482 /* Don't call nonzero_bits for the second time if it cannot change
4484 if ((nonzero
& nonzero0
) != nonzero
)
4486 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4487 known_x
, known_mode
, known_ret
);
4491 case PLUS
: case MINUS
:
4493 case DIV
: case UDIV
:
4494 case MOD
: case UMOD
:
4495 /* We can apply the rules of arithmetic to compute the number of
4496 high- and low-order zero bits of these operations. We start by
4497 computing the width (position of the highest-order nonzero bit)
4498 and the number of low-order zero bits for each value. */
4500 unsigned HOST_WIDE_INT nz0
4501 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4502 known_x
, known_mode
, known_ret
);
4503 unsigned HOST_WIDE_INT nz1
4504 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4505 known_x
, known_mode
, known_ret
);
4506 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4507 int width0
= floor_log2 (nz0
) + 1;
4508 int width1
= floor_log2 (nz1
) + 1;
4509 int low0
= floor_log2 (nz0
& -nz0
);
4510 int low1
= floor_log2 (nz1
& -nz1
);
4511 unsigned HOST_WIDE_INT op0_maybe_minusp
4512 = nz0
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4513 unsigned HOST_WIDE_INT op1_maybe_minusp
4514 = nz1
& ((unsigned HOST_WIDE_INT
) 1 << sign_index
);
4515 unsigned int result_width
= mode_width
;
4521 result_width
= MAX (width0
, width1
) + 1;
4522 result_low
= MIN (low0
, low1
);
4525 result_low
= MIN (low0
, low1
);
4528 result_width
= width0
+ width1
;
4529 result_low
= low0
+ low1
;
4534 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4535 result_width
= width0
;
4540 result_width
= width0
;
4545 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4546 result_width
= MIN (width0
, width1
);
4547 result_low
= MIN (low0
, low1
);
4552 result_width
= MIN (width0
, width1
);
4553 result_low
= MIN (low0
, low1
);
4559 if (result_width
< mode_width
)
4560 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << result_width
) - 1;
4563 nonzero
&= ~(((unsigned HOST_WIDE_INT
) 1 << result_low
) - 1);
4568 if (CONST_INT_P (XEXP (x
, 1))
4569 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4570 nonzero
&= ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
4574 /* If this is a SUBREG formed for a promoted variable that has
4575 been zero-extended, we know that at least the high-order bits
4576 are zero, though others might be too. */
4578 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4579 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4580 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4581 known_x
, known_mode
, known_ret
);
4583 inner_mode
= GET_MODE (SUBREG_REG (x
));
4584 /* If the inner mode is a single word for both the host and target
4585 machines, we can compute this from which bits of the inner
4586 object might be nonzero. */
4587 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4588 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4590 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4591 known_x
, known_mode
, known_ret
);
4593 #if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
4594 /* If this is a typical RISC machine, we only have to worry
4595 about the way loads are extended. */
4596 if ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4597 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4598 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4599 || !MEM_P (SUBREG_REG (x
)))
4602 /* On many CISC machines, accessing an object in a wider mode
4603 causes the high-order bits to become undefined. So they are
4604 not known to be zero. */
4605 if (GET_MODE_PRECISION (GET_MODE (x
))
4606 > GET_MODE_PRECISION (inner_mode
))
4607 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4608 & ~GET_MODE_MASK (inner_mode
));
4617 /* The nonzero bits are in two classes: any bits within MODE
4618 that aren't in GET_MODE (x) are always significant. The rest of the
4619 nonzero bits are those that are significant in the operand of
4620 the shift when shifted the appropriate number of bits. This
4621 shows that high-order bits are cleared by the right shift and
4622 low-order bits by left shifts. */
4623 if (CONST_INT_P (XEXP (x
, 1))
4624 && INTVAL (XEXP (x
, 1)) >= 0
4625 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4626 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4628 machine_mode inner_mode
= GET_MODE (x
);
4629 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4630 int count
= INTVAL (XEXP (x
, 1));
4631 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4632 unsigned HOST_WIDE_INT op_nonzero
4633 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4634 known_x
, known_mode
, known_ret
);
4635 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4636 unsigned HOST_WIDE_INT outer
= 0;
4638 if (mode_width
> width
)
4639 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4641 if (code
== LSHIFTRT
)
4643 else if (code
== ASHIFTRT
)
4647 /* If the sign bit may have been nonzero before the shift, we
4648 need to mark all the places it could have been copied to
4649 by the shift as possibly nonzero. */
4650 if (inner
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
4651 inner
|= (((unsigned HOST_WIDE_INT
) 1 << count
) - 1)
4654 else if (code
== ASHIFT
)
4657 inner
= ((inner
<< (count
% width
)
4658 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4660 nonzero
&= (outer
| inner
);
4666 /* This is at most the number of bits in the mode. */
4667 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4671 /* If CLZ has a known value at zero, then the nonzero bits are
4672 that value, plus the number of bits in the mode minus one. */
4673 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4675 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4681 /* If CTZ has a known value at zero, then the nonzero bits are
4682 that value, plus the number of bits in the mode minus one. */
4683 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4685 |= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4691 /* This is at most the number of bits in the mode minus 1. */
4692 nonzero
= ((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
4701 unsigned HOST_WIDE_INT nonzero_true
4702 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4703 known_x
, known_mode
, known_ret
);
4705 /* Don't call nonzero_bits for the second time if it cannot change
4707 if ((nonzero
& nonzero_true
) != nonzero
)
4708 nonzero
&= nonzero_true
4709 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4710 known_x
, known_mode
, known_ret
);
4721 /* See the macro definition above. */
4722 #undef cached_num_sign_bit_copies
4725 /* Return true if num_sign_bit_copies1 might recurse into both operands
4729 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4731 if (!ARITHMETIC_P (x
))
4733 switch (GET_CODE (x
))
4751 /* The function cached_num_sign_bit_copies is a wrapper around
4752 num_sign_bit_copies1. It avoids exponential behavior in
4753 num_sign_bit_copies1 when X has identical subexpressions on the
4754 first or the second level. */
4757 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4758 machine_mode known_mode
,
4759 unsigned int known_ret
)
4761 if (x
== known_x
&& mode
== known_mode
)
4764 /* Try to find identical subexpressions. If found call
4765 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4766 the precomputed value for the subexpression as KNOWN_RET. */
4768 if (num_sign_bit_copies_binary_arith_p (x
))
4770 rtx x0
= XEXP (x
, 0);
4771 rtx x1
= XEXP (x
, 1);
4773 /* Check the first level. */
4776 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4777 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4781 /* Check the second level. */
4782 if (num_sign_bit_copies_binary_arith_p (x0
)
4783 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4785 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4786 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4790 if (num_sign_bit_copies_binary_arith_p (x1
)
4791 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4793 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4794 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4799 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4802 /* Return the number of bits at the high-order end of X that are known to
4803 be equal to the sign bit. X will be used in mode MODE; if MODE is
4804 VOIDmode, X will be used in its own mode. The returned value will always
4805 be between 1 and the number of bits in MODE. */
4808 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4809 machine_mode known_mode
,
4810 unsigned int known_ret
)
4812 enum rtx_code code
= GET_CODE (x
);
4813 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4814 int num0
, num1
, result
;
4815 unsigned HOST_WIDE_INT nonzero
;
4817 /* If we weren't given a mode, use the mode of X. If the mode is still
4818 VOIDmode, we don't know anything. Likewise if one of the modes is
4821 if (mode
== VOIDmode
)
4822 mode
= GET_MODE (x
);
4824 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4825 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4828 /* For a smaller object, just ignore the high bits. */
4829 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4831 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4832 known_x
, known_mode
, known_ret
);
4834 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4837 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4839 /* If this machine does not do all register operations on the entire
4840 register and MODE is wider than the mode of X, we can say nothing
4841 at all about the high-order bits. */
4842 if (!WORD_REGISTER_OPERATIONS
)
4845 /* Likewise on machines that do, if the mode of the object is smaller
4846 than a word and loads of that size don't sign extend, we can say
4847 nothing about the high order bits. */
4848 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4849 #ifdef LOAD_EXTEND_OP
4850 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4856 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4857 the code in the switch below. */
4862 #if defined(POINTERS_EXTEND_UNSIGNED)
4863 /* If pointers extend signed and this is a pointer in Pmode, say that
4864 all the bits above ptr_mode are known to be sign bit copies. */
4865 /* As we do not know which address space the pointer is referring to,
4866 we can do this only if the target does not support different pointer
4867 or address modes depending on the address space. */
4868 if (target_default_pointer_address_modes_p ()
4869 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4870 && mode
== Pmode
&& REG_POINTER (x
)
4871 && !targetm
.have_ptr_extend ())
4872 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4876 unsigned int copies_for_hook
= 1, copies
= 1;
4877 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4878 known_mode
, known_ret
,
4882 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4883 known_mode
, known_ret
);
4885 if (copies
> 1 || copies_for_hook
> 1)
4886 return MAX (copies
, copies_for_hook
);
4888 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4893 #ifdef LOAD_EXTEND_OP
4894 /* Some RISC machines sign-extend all loads of smaller than a word. */
4895 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4896 return MAX (1, ((int) bitwidth
4897 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4902 /* If the constant is negative, take its 1's complement and remask.
4903 Then see how many zero bits we have. */
4904 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4905 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4906 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
4907 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4909 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4912 /* If this is a SUBREG for a promoted object that is sign-extended
4913 and we are looking at it in a wider mode, we know that at least the
4914 high-order bits are known to be sign bit copies. */
4916 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4918 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4919 known_x
, known_mode
, known_ret
);
4920 return MAX ((int) bitwidth
4921 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4925 /* For a smaller object, just ignore the high bits. */
4926 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4928 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4929 known_x
, known_mode
, known_ret
);
4930 return MAX (1, (num0
4931 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4935 #ifdef LOAD_EXTEND_OP
4936 /* For paradoxical SUBREGs on machines where all register operations
4937 affect the entire register, just look inside. Note that we are
4938 passing MODE to the recursive call, so the number of sign bit copies
4939 will remain relative to that mode, not the inner mode. */
4941 /* This works only if loads sign extend. Otherwise, if we get a
4942 reload for the inner part, it may be loaded from the stack, and
4943 then we lose all sign bit copies that existed before the store
4946 if (WORD_REGISTER_OPERATIONS
4947 && paradoxical_subreg_p (x
)
4948 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4949 && MEM_P (SUBREG_REG (x
)))
4950 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4951 known_x
, known_mode
, known_ret
);
4956 if (CONST_INT_P (XEXP (x
, 1)))
4957 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4961 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4962 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4963 known_x
, known_mode
, known_ret
));
4966 /* For a smaller object, just ignore the high bits. */
4967 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4968 known_x
, known_mode
, known_ret
);
4969 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4973 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4974 known_x
, known_mode
, known_ret
);
4976 case ROTATE
: case ROTATERT
:
4977 /* If we are rotating left by a number of bits less than the number
4978 of sign bit copies, we can just subtract that amount from the
4980 if (CONST_INT_P (XEXP (x
, 1))
4981 && INTVAL (XEXP (x
, 1)) >= 0
4982 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4984 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4985 known_x
, known_mode
, known_ret
);
4986 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4987 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4992 /* In general, this subtracts one sign bit copy. But if the value
4993 is known to be positive, the number of sign bit copies is the
4994 same as that of the input. Finally, if the input has just one bit
4995 that might be nonzero, all the bits are copies of the sign bit. */
4996 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4997 known_x
, known_mode
, known_ret
);
4998 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4999 return num0
> 1 ? num0
- 1 : 1;
5001 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5006 && (((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
5011 case IOR
: case AND
: case XOR
:
5012 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5013 /* Logical operations will preserve the number of sign-bit copies.
5014 MIN and MAX operations always return one of the operands. */
5015 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5016 known_x
, known_mode
, known_ret
);
5017 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5018 known_x
, known_mode
, known_ret
);
5020 /* If num1 is clearing some of the top bits then regardless of
5021 the other term, we are guaranteed to have at least that many
5022 high-order zero bits. */
5025 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5026 && CONST_INT_P (XEXP (x
, 1))
5027 && (UINTVAL (XEXP (x
, 1))
5028 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) == 0)
5031 /* Similarly for IOR when setting high-order bits. */
5034 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5035 && CONST_INT_P (XEXP (x
, 1))
5036 && (UINTVAL (XEXP (x
, 1))
5037 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5040 return MIN (num0
, num1
);
5042 case PLUS
: case MINUS
:
5043 /* For addition and subtraction, we can have a 1-bit carry. However,
5044 if we are subtracting 1 from a positive number, there will not
5045 be such a carry. Furthermore, if the positive number is known to
5046 be 0 or 1, we know the result is either -1 or 0. */
5048 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5049 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5051 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5052 if ((((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
5053 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5054 : bitwidth
- floor_log2 (nonzero
) - 1);
5057 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5058 known_x
, known_mode
, known_ret
);
5059 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5060 known_x
, known_mode
, known_ret
);
5061 result
= MAX (1, MIN (num0
, num1
) - 1);
5066 /* The number of bits of the product is the sum of the number of
5067 bits of both terms. However, unless one of the terms if known
5068 to be positive, we must allow for an additional bit since negating
5069 a negative number can remove one sign bit copy. */
5071 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5072 known_x
, known_mode
, known_ret
);
5073 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5074 known_x
, known_mode
, known_ret
);
5076 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5078 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5079 || (((nonzero_bits (XEXP (x
, 0), mode
)
5080 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5081 && ((nonzero_bits (XEXP (x
, 1), mode
)
5082 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1)))
5086 return MAX (1, result
);
5089 /* The result must be <= the first operand. If the first operand
5090 has the high bit set, we know nothing about the number of sign
5092 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5094 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5095 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5098 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5099 known_x
, known_mode
, known_ret
);
5102 /* The result must be <= the second operand. If the second operand
5103 has (or just might have) the high bit set, we know nothing about
5104 the number of sign bit copies. */
5105 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5107 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5108 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5111 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5112 known_x
, known_mode
, known_ret
);
5115 /* Similar to unsigned division, except that we have to worry about
5116 the case where the divisor is negative, in which case we have
5118 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5119 known_x
, known_mode
, known_ret
);
5121 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5122 || (nonzero_bits (XEXP (x
, 1), mode
)
5123 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5129 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5130 known_x
, known_mode
, known_ret
);
5132 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5133 || (nonzero_bits (XEXP (x
, 1), mode
)
5134 & ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
5140 /* Shifts by a constant add to the number of bits equal to the
5142 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5143 known_x
, known_mode
, known_ret
);
5144 if (CONST_INT_P (XEXP (x
, 1))
5145 && INTVAL (XEXP (x
, 1)) > 0
5146 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5147 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5152 /* Left shifts destroy copies. */
5153 if (!CONST_INT_P (XEXP (x
, 1))
5154 || INTVAL (XEXP (x
, 1)) < 0
5155 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5156 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5159 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5160 known_x
, known_mode
, known_ret
);
5161 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5164 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5165 known_x
, known_mode
, known_ret
);
5166 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5167 known_x
, known_mode
, known_ret
);
5168 return MIN (num0
, num1
);
5170 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5171 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5172 case GEU
: case GTU
: case LEU
: case LTU
:
5173 case UNORDERED
: case ORDERED
:
5174 /* If the constant is negative, take its 1's complement and remask.
5175 Then see how many zero bits we have. */
5176 nonzero
= STORE_FLAG_VALUE
;
5177 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5178 && (nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
5179 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5181 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5187 /* If we haven't been able to figure it out by one of the above rules,
5188 see if some of the high-order bits are known to be zero. If so,
5189 count those bits and return one less than that amount. If we can't
5190 safely compute the mask for this mode, always return BITWIDTH. */
5192 bitwidth
= GET_MODE_PRECISION (mode
);
5193 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5196 nonzero
= nonzero_bits (x
, mode
);
5197 return nonzero
& ((unsigned HOST_WIDE_INT
) 1 << (bitwidth
- 1))
5198 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5201 /* Calculate the rtx_cost of a single instruction. A return value of
5202 zero indicates an instruction pattern without a known cost. */
5205 insn_rtx_cost (rtx pat
, bool speed
)
5210 /* Extract the single set rtx from the instruction pattern.
5211 We can't use single_set since we only have the pattern. */
5212 if (GET_CODE (pat
) == SET
)
5214 else if (GET_CODE (pat
) == PARALLEL
)
5217 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5219 rtx x
= XVECEXP (pat
, 0, i
);
5220 if (GET_CODE (x
) == SET
)
5233 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5234 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5237 /* Returns estimate on cost of computing SEQ. */
5240 seq_cost (const rtx_insn
*seq
, bool speed
)
5245 for (; seq
; seq
= NEXT_INSN (seq
))
5247 set
= single_set (seq
);
5249 cost
+= set_rtx_cost (set
, speed
);
5257 /* Given an insn INSN and condition COND, return the condition in a
5258 canonical form to simplify testing by callers. Specifically:
5260 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5261 (2) Both operands will be machine operands; (cc0) will have been replaced.
5262 (3) If an operand is a constant, it will be the second operand.
5263 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5264 for GE, GEU, and LEU.
5266 If the condition cannot be understood, or is an inequality floating-point
5267 comparison which needs to be reversed, 0 will be returned.
5269 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5271 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5272 insn used in locating the condition was found. If a replacement test
5273 of the condition is desired, it should be placed in front of that
5274 insn and we will be sure that the inputs are still valid.
5276 If WANT_REG is nonzero, we wish the condition to be relative to that
5277 register, if possible. Therefore, do not canonicalize the condition
5278 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5279 to be a compare to a CC mode register.
5281 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5285 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5286 rtx_insn
**earliest
,
5287 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5290 rtx_insn
*prev
= insn
;
5294 int reverse_code
= 0;
5296 basic_block bb
= BLOCK_FOR_INSN (insn
);
5298 code
= GET_CODE (cond
);
5299 mode
= GET_MODE (cond
);
5300 op0
= XEXP (cond
, 0);
5301 op1
= XEXP (cond
, 1);
5304 code
= reversed_comparison_code (cond
, insn
);
5305 if (code
== UNKNOWN
)
5311 /* If we are comparing a register with zero, see if the register is set
5312 in the previous insn to a COMPARE or a comparison operation. Perform
5313 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5316 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5317 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5318 && op1
== CONST0_RTX (GET_MODE (op0
))
5321 /* Set nonzero when we find something of interest. */
5324 /* If comparison with cc0, import actual comparison from compare
5328 if ((prev
= prev_nonnote_insn (prev
)) == 0
5329 || !NONJUMP_INSN_P (prev
)
5330 || (set
= single_set (prev
)) == 0
5331 || SET_DEST (set
) != cc0_rtx
)
5334 op0
= SET_SRC (set
);
5335 op1
= CONST0_RTX (GET_MODE (op0
));
5340 /* If this is a COMPARE, pick up the two things being compared. */
5341 if (GET_CODE (op0
) == COMPARE
)
5343 op1
= XEXP (op0
, 1);
5344 op0
= XEXP (op0
, 0);
5347 else if (!REG_P (op0
))
5350 /* Go back to the previous insn. Stop if it is not an INSN. We also
5351 stop if it isn't a single set or if it has a REG_INC note because
5352 we don't want to bother dealing with it. */
5354 prev
= prev_nonnote_nondebug_insn (prev
);
5357 || !NONJUMP_INSN_P (prev
)
5358 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5359 /* In cfglayout mode, there do not have to be labels at the
5360 beginning of a block, or jumps at the end, so the previous
5361 conditions would not stop us when we reach bb boundary. */
5362 || BLOCK_FOR_INSN (prev
) != bb
)
5365 set
= set_of (op0
, prev
);
5368 && (GET_CODE (set
) != SET
5369 || !rtx_equal_p (SET_DEST (set
), op0
)))
5372 /* If this is setting OP0, get what it sets it to if it looks
5376 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5377 #ifdef FLOAT_STORE_FLAG_VALUE
5378 REAL_VALUE_TYPE fsfv
;
5381 /* ??? We may not combine comparisons done in a CCmode with
5382 comparisons not done in a CCmode. This is to aid targets
5383 like Alpha that have an IEEE compliant EQ instruction, and
5384 a non-IEEE compliant BEQ instruction. The use of CCmode is
5385 actually artificial, simply to prevent the combination, but
5386 should not affect other platforms.
5388 However, we must allow VOIDmode comparisons to match either
5389 CCmode or non-CCmode comparison, because some ports have
5390 modeless comparisons inside branch patterns.
5392 ??? This mode check should perhaps look more like the mode check
5393 in simplify_comparison in combine. */
5394 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5395 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5397 && inner_mode
!= VOIDmode
)
5399 if (GET_CODE (SET_SRC (set
)) == COMPARE
5402 && val_signbit_known_set_p (inner_mode
,
5404 #ifdef FLOAT_STORE_FLAG_VALUE
5406 && SCALAR_FLOAT_MODE_P (inner_mode
)
5407 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5408 REAL_VALUE_NEGATIVE (fsfv
)))
5411 && COMPARISON_P (SET_SRC (set
))))
5413 else if (((code
== EQ
5415 && val_signbit_known_set_p (inner_mode
,
5417 #ifdef FLOAT_STORE_FLAG_VALUE
5419 && SCALAR_FLOAT_MODE_P (inner_mode
)
5420 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5421 REAL_VALUE_NEGATIVE (fsfv
)))
5424 && COMPARISON_P (SET_SRC (set
)))
5429 else if ((code
== EQ
|| code
== NE
)
5430 && GET_CODE (SET_SRC (set
)) == XOR
)
5431 /* Handle sequences like:
5434 ...(eq|ne op0 (const_int 0))...
5438 (eq op0 (const_int 0)) reduces to (eq X Y)
5439 (ne op0 (const_int 0)) reduces to (ne X Y)
5441 This is the form used by MIPS16, for example. */
5447 else if (reg_set_p (op0
, prev
))
5448 /* If this sets OP0, but not directly, we have to give up. */
5453 /* If the caller is expecting the condition to be valid at INSN,
5454 make sure X doesn't change before INSN. */
5455 if (valid_at_insn_p
)
5456 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5458 if (COMPARISON_P (x
))
5459 code
= GET_CODE (x
);
5462 code
= reversed_comparison_code (x
, prev
);
5463 if (code
== UNKNOWN
)
5468 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5474 /* If constant is first, put it last. */
5475 if (CONSTANT_P (op0
))
5476 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5478 /* If OP0 is the result of a comparison, we weren't able to find what
5479 was really being compared, so fail. */
5481 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5484 /* Canonicalize any ordered comparison with integers involving equality
5485 if we can do computations in the relevant mode and we do not
5488 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5489 && CONST_INT_P (op1
)
5490 && GET_MODE (op0
) != VOIDmode
5491 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5493 HOST_WIDE_INT const_val
= INTVAL (op1
);
5494 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5495 unsigned HOST_WIDE_INT max_val
5496 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5501 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5502 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5505 /* When cross-compiling, const_val might be sign-extended from
5506 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5508 if ((const_val
& max_val
)
5509 != ((unsigned HOST_WIDE_INT
) 1
5510 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5511 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5515 if (uconst_val
< max_val
)
5516 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5520 if (uconst_val
!= 0)
5521 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5529 /* Never return CC0; return zero instead. */
5533 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5536 /* Given a jump insn JUMP, return the condition that will cause it to branch
5537 to its JUMP_LABEL. If the condition cannot be understood, or is an
5538 inequality floating-point comparison which needs to be reversed, 0 will
5541 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5542 insn used in locating the condition was found. If a replacement test
5543 of the condition is desired, it should be placed in front of that
5544 insn and we will be sure that the inputs are still valid. If EARLIEST
5545 is null, the returned condition will be valid at INSN.
5547 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5548 compare CC mode register.
5550 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5553 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5554 int valid_at_insn_p
)
5560 /* If this is not a standard conditional jump, we can't parse it. */
5562 || ! any_condjump_p (jump
))
5564 set
= pc_set (jump
);
5566 cond
= XEXP (SET_SRC (set
), 0);
5568 /* If this branches to JUMP_LABEL when the condition is false, reverse
5571 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5572 && LABEL_REF_LABEL (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5574 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5575 allow_cc_mode
, valid_at_insn_p
);
5578 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5579 TARGET_MODE_REP_EXTENDED.
5581 Note that we assume that the property of
5582 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5583 narrower than mode B. I.e., if A is a mode narrower than B then in
5584 order to be able to operate on it in mode B, mode A needs to
5585 satisfy the requirements set by the representation of mode B. */
5588 init_num_sign_bit_copies_in_rep (void)
5590 machine_mode mode
, in_mode
;
5592 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5593 in_mode
= GET_MODE_WIDER_MODE (mode
))
5594 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5595 mode
= GET_MODE_WIDER_MODE (mode
))
5599 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5600 extends to the next widest mode. */
5601 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5602 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5604 /* We are in in_mode. Count how many bits outside of mode
5605 have to be copies of the sign-bit. */
5606 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5608 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5610 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5611 /* We can only check sign-bit copies starting from the
5612 top-bit. In order to be able to check the bits we
5613 have already seen we pretend that subsequent bits
5614 have to be sign-bit copies too. */
5615 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5616 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5617 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5622 /* Suppose that truncation from the machine mode of X to MODE is not a
5623 no-op. See if there is anything special about X so that we can
5624 assume it already contains a truncated value of MODE. */
5627 truncated_to_mode (machine_mode mode
, const_rtx x
)
5629 /* This register has already been used in MODE without explicit
5631 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5634 /* See if we already satisfy the requirements of MODE. If yes we
5635 can just switch to MODE. */
5636 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5637 && (num_sign_bit_copies (x
, GET_MODE (x
))
5638 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5644 /* Return true if RTX code CODE has a single sequence of zero or more
5645 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5646 entry in that case. */
5649 setup_reg_subrtx_bounds (unsigned int code
)
5651 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5653 for (; format
[i
] != 'e'; ++i
)
5656 /* No subrtxes. Leave start and count as 0. */
5658 if (format
[i
] == 'E' || format
[i
] == 'V')
5662 /* Record the sequence of 'e's. */
5663 rtx_all_subrtx_bounds
[code
].start
= i
;
5666 while (format
[i
] == 'e');
5667 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5668 /* rtl-iter.h relies on this. */
5669 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5671 for (; format
[i
]; ++i
)
5672 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5678 /* Initialize rtx_all_subrtx_bounds. */
5683 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5685 if (!setup_reg_subrtx_bounds (i
))
5686 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5687 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5688 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5691 init_num_sign_bit_copies_in_rep ();
5694 /* Check whether this is a constant pool constant. */
5696 constant_pool_constant_p (rtx x
)
5698 x
= avoid_constant_pool_reference (x
);
5699 return CONST_DOUBLE_P (x
);
5702 /* If M is a bitmask that selects a field of low-order bits within an item but
5703 not the entire word, return the length of the field. Return -1 otherwise.
5704 M is used in machine mode MODE. */
5707 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5709 if (mode
!= VOIDmode
)
5711 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5713 m
&= GET_MODE_MASK (mode
);
5716 return exact_log2 (m
+ 1);
5719 /* Return the mode of MEM's address. */
5722 get_address_mode (rtx mem
)
5726 gcc_assert (MEM_P (mem
));
5727 mode
= GET_MODE (XEXP (mem
, 0));
5728 if (mode
!= VOIDmode
)
5730 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5733 /* Split up a CONST_DOUBLE or integer constant rtx
5734 into two rtx's for single words,
5735 storing in *FIRST the word that comes first in memory in the target
5736 and in *SECOND the other.
5738 TODO: This function needs to be rewritten to work on any size
5742 split_double (rtx value
, rtx
*first
, rtx
*second
)
5744 if (CONST_INT_P (value
))
5746 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5748 /* In this case the CONST_INT holds both target words.
5749 Extract the bits from it into two word-sized pieces.
5750 Sign extend each half to HOST_WIDE_INT. */
5751 unsigned HOST_WIDE_INT low
, high
;
5752 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5753 unsigned bits_per_word
= BITS_PER_WORD
;
5755 /* Set sign_bit to the most significant bit of a word. */
5757 sign_bit
<<= bits_per_word
- 1;
5759 /* Set mask so that all bits of the word are set. We could
5760 have used 1 << BITS_PER_WORD instead of basing the
5761 calculation on sign_bit. However, on machines where
5762 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5763 compiler warning, even though the code would never be
5765 mask
= sign_bit
<< 1;
5768 /* Set sign_extend as any remaining bits. */
5769 sign_extend
= ~mask
;
5771 /* Pick the lower word and sign-extend it. */
5772 low
= INTVAL (value
);
5777 /* Pick the higher word, shifted to the least significant
5778 bits, and sign-extend it. */
5779 high
= INTVAL (value
);
5780 high
>>= bits_per_word
- 1;
5783 if (high
& sign_bit
)
5784 high
|= sign_extend
;
5786 /* Store the words in the target machine order. */
5787 if (WORDS_BIG_ENDIAN
)
5789 *first
= GEN_INT (high
);
5790 *second
= GEN_INT (low
);
5794 *first
= GEN_INT (low
);
5795 *second
= GEN_INT (high
);
5800 /* The rule for using CONST_INT for a wider mode
5801 is that we regard the value as signed.
5802 So sign-extend it. */
5803 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5804 if (WORDS_BIG_ENDIAN
)
5816 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5818 /* All of this is scary code and needs to be converted to
5819 properly work with any size integer. */
5820 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5821 if (WORDS_BIG_ENDIAN
)
5823 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5824 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5828 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5829 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5832 else if (!CONST_DOUBLE_P (value
))
5834 if (WORDS_BIG_ENDIAN
)
5836 *first
= const0_rtx
;
5842 *second
= const0_rtx
;
5845 else if (GET_MODE (value
) == VOIDmode
5846 /* This is the old way we did CONST_DOUBLE integers. */
5847 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5849 /* In an integer, the words are defined as most and least significant.
5850 So order them by the target's convention. */
5851 if (WORDS_BIG_ENDIAN
)
5853 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5854 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5858 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5859 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5866 /* Note, this converts the REAL_VALUE_TYPE to the target's
5867 format, splits up the floating point double and outputs
5868 exactly 32 bits of it into each of l[0] and l[1] --
5869 not necessarily BITS_PER_WORD bits. */
5870 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5872 /* If 32 bits is an entire word for the target, but not for the host,
5873 then sign-extend on the host so that the number will look the same
5874 way on the host that it would on the target. See for instance
5875 simplify_unary_operation. The #if is needed to avoid compiler
5878 #if HOST_BITS_PER_LONG > 32
5879 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5881 if (l
[0] & ((long) 1 << 31))
5882 l
[0] |= ((unsigned long) (-1) << 32);
5883 if (l
[1] & ((long) 1 << 31))
5884 l
[1] |= ((unsigned long) (-1) << 32);
5888 *first
= GEN_INT (l
[0]);
5889 *second
= GEN_INT (l
[1]);
5893 /* Return true if X is a sign_extract or zero_extract from the least
5897 lsb_bitfield_op_p (rtx x
)
5899 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5901 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5902 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5903 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5905 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5910 /* Strip outer address "mutations" from LOC and return a pointer to the
5911 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5912 stripped expression there.
5914 "Mutations" either convert between modes or apply some kind of
5915 extension, truncation or alignment. */
5918 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5922 enum rtx_code code
= GET_CODE (*loc
);
5923 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5924 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5925 used to convert between pointer sizes. */
5926 loc
= &XEXP (*loc
, 0);
5927 else if (lsb_bitfield_op_p (*loc
))
5928 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5929 acts as a combined truncation and extension. */
5930 loc
= &XEXP (*loc
, 0);
5931 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5932 /* (and ... (const_int -X)) is used to align to X bytes. */
5933 loc
= &XEXP (*loc
, 0);
5934 else if (code
== SUBREG
5935 && !OBJECT_P (SUBREG_REG (*loc
))
5936 && subreg_lowpart_p (*loc
))
5937 /* (subreg (operator ...) ...) inside and is used for mode
5939 loc
= &SUBREG_REG (*loc
);
5947 /* Return true if CODE applies some kind of scale. The scaled value is
5948 is the first operand and the scale is the second. */
5951 binary_scale_code_p (enum rtx_code code
)
5953 return (code
== MULT
5955 /* Needed by ARM targets. */
5959 || code
== ROTATERT
);
5962 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5963 (see address_info). Return null otherwise. */
5966 get_base_term (rtx
*inner
)
5968 if (GET_CODE (*inner
) == LO_SUM
)
5969 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5972 || GET_CODE (*inner
) == SUBREG
5973 || GET_CODE (*inner
) == SCRATCH
)
5978 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5979 (see address_info). Return null otherwise. */
5982 get_index_term (rtx
*inner
)
5984 /* At present, only constant scales are allowed. */
5985 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5986 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5989 || GET_CODE (*inner
) == SUBREG
5990 || GET_CODE (*inner
) == SCRATCH
)
5995 /* Set the segment part of address INFO to LOC, given that INNER is the
5999 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6001 gcc_assert (!info
->segment
);
6002 info
->segment
= loc
;
6003 info
->segment_term
= inner
;
6006 /* Set the base part of address INFO to LOC, given that INNER is the
6010 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6012 gcc_assert (!info
->base
);
6014 info
->base_term
= inner
;
6017 /* Set the index part of address INFO to LOC, given that INNER is the
6021 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6023 gcc_assert (!info
->index
);
6025 info
->index_term
= inner
;
6028 /* Set the displacement part of address INFO to LOC, given that INNER
6029 is the constant term. */
6032 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6034 gcc_assert (!info
->disp
);
6036 info
->disp_term
= inner
;
6039 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6040 rest of INFO accordingly. */
6043 decompose_incdec_address (struct address_info
*info
)
6045 info
->autoinc_p
= true;
6047 rtx
*base
= &XEXP (*info
->inner
, 0);
6048 set_address_base (info
, base
, base
);
6049 gcc_checking_assert (info
->base
== info
->base_term
);
6051 /* These addresses are only valid when the size of the addressed
6053 gcc_checking_assert (info
->mode
!= VOIDmode
);
6056 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6057 of INFO accordingly. */
6060 decompose_automod_address (struct address_info
*info
)
6062 info
->autoinc_p
= true;
6064 rtx
*base
= &XEXP (*info
->inner
, 0);
6065 set_address_base (info
, base
, base
);
6066 gcc_checking_assert (info
->base
== info
->base_term
);
6068 rtx plus
= XEXP (*info
->inner
, 1);
6069 gcc_assert (GET_CODE (plus
) == PLUS
);
6071 info
->base_term2
= &XEXP (plus
, 0);
6072 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6074 rtx
*step
= &XEXP (plus
, 1);
6075 rtx
*inner_step
= strip_address_mutations (step
);
6076 if (CONSTANT_P (*inner_step
))
6077 set_address_disp (info
, step
, inner_step
);
6079 set_address_index (info
, step
, inner_step
);
6082 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6083 values in [PTR, END). Return a pointer to the end of the used array. */
6086 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6089 if (GET_CODE (x
) == PLUS
)
6091 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6092 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6096 gcc_assert (ptr
!= end
);
6102 /* Evaluate the likelihood of X being a base or index value, returning
6103 positive if it is likely to be a base, negative if it is likely to be
6104 an index, and 0 if we can't tell. Make the magnitude of the return
6105 value reflect the amount of confidence we have in the answer.
6107 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6110 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6111 enum rtx_code outer_code
, enum rtx_code index_code
)
6113 /* Believe *_POINTER unless the address shape requires otherwise. */
6114 if (REG_P (x
) && REG_POINTER (x
))
6116 if (MEM_P (x
) && MEM_POINTER (x
))
6119 if (REG_P (x
) && HARD_REGISTER_P (x
))
6121 /* X is a hard register. If it only fits one of the base
6122 or index classes, choose that interpretation. */
6123 int regno
= REGNO (x
);
6124 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6125 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6126 if (base_p
!= index_p
)
6127 return base_p
? 1 : -1;
6132 /* INFO->INNER describes a normal, non-automodified address.
6133 Fill in the rest of INFO accordingly. */
6136 decompose_normal_address (struct address_info
*info
)
6138 /* Treat the address as the sum of up to four values. */
6140 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6141 ops
+ ARRAY_SIZE (ops
)) - ops
;
6143 /* If there is more than one component, any base component is in a PLUS. */
6145 info
->base_outer_code
= PLUS
;
6147 /* Try to classify each sum operand now. Leave those that could be
6148 either a base or an index in OPS. */
6151 for (size_t in
= 0; in
< n_ops
; ++in
)
6154 rtx
*inner
= strip_address_mutations (loc
);
6155 if (CONSTANT_P (*inner
))
6156 set_address_disp (info
, loc
, inner
);
6157 else if (GET_CODE (*inner
) == UNSPEC
)
6158 set_address_segment (info
, loc
, inner
);
6161 /* The only other possibilities are a base or an index. */
6162 rtx
*base_term
= get_base_term (inner
);
6163 rtx
*index_term
= get_index_term (inner
);
6164 gcc_assert (base_term
|| index_term
);
6166 set_address_index (info
, loc
, index_term
);
6167 else if (!index_term
)
6168 set_address_base (info
, loc
, base_term
);
6171 gcc_assert (base_term
== index_term
);
6173 inner_ops
[out
] = base_term
;
6179 /* Classify the remaining OPS members as bases and indexes. */
6182 /* If we haven't seen a base or an index yet, assume that this is
6183 the base. If we were confident that another term was the base
6184 or index, treat the remaining operand as the other kind. */
6186 set_address_base (info
, ops
[0], inner_ops
[0]);
6188 set_address_index (info
, ops
[0], inner_ops
[0]);
6192 /* In the event of a tie, assume the base comes first. */
6193 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6195 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6196 GET_CODE (*ops
[0])))
6198 set_address_base (info
, ops
[0], inner_ops
[0]);
6199 set_address_index (info
, ops
[1], inner_ops
[1]);
6203 set_address_base (info
, ops
[1], inner_ops
[1]);
6204 set_address_index (info
, ops
[0], inner_ops
[0]);
6208 gcc_assert (out
== 0);
6211 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6212 or VOIDmode if not known. AS is the address space associated with LOC.
6213 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6216 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6217 addr_space_t as
, enum rtx_code outer_code
)
6219 memset (info
, 0, sizeof (*info
));
6222 info
->addr_outer_code
= outer_code
;
6224 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6225 info
->base_outer_code
= outer_code
;
6226 switch (GET_CODE (*info
->inner
))
6232 decompose_incdec_address (info
);
6237 decompose_automod_address (info
);
6241 decompose_normal_address (info
);
6246 /* Describe address operand LOC in INFO. */
6249 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6251 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6254 /* Describe the address of MEM X in INFO. */
6257 decompose_mem_address (struct address_info
*info
, rtx x
)
6259 gcc_assert (MEM_P (x
));
6260 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6261 MEM_ADDR_SPACE (x
), MEM
);
6264 /* Update INFO after a change to the address it describes. */
6267 update_address (struct address_info
*info
)
6269 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6270 info
->addr_outer_code
);
6273 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6274 more complicated than that. */
6277 get_index_scale (const struct address_info
*info
)
6279 rtx index
= *info
->index
;
6280 if (GET_CODE (index
) == MULT
6281 && CONST_INT_P (XEXP (index
, 1))
6282 && info
->index_term
== &XEXP (index
, 0))
6283 return INTVAL (XEXP (index
, 1));
6285 if (GET_CODE (index
) == ASHIFT
6286 && CONST_INT_P (XEXP (index
, 1))
6287 && info
->index_term
== &XEXP (index
, 0))
6288 return (HOST_WIDE_INT
) 1 << INTVAL (XEXP (index
, 1));
6290 if (info
->index
== info
->index_term
)
6296 /* Return the "index code" of INFO, in the form required by
6300 get_index_code (const struct address_info
*info
)
6303 return GET_CODE (*info
->index
);
6306 return GET_CODE (*info
->disp
);
6311 /* Return true if RTL X contains a SYMBOL_REF. */
6314 contains_symbol_ref_p (const_rtx x
)
6316 subrtx_iterator::array_type array
;
6317 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6318 if (SYMBOL_REF_P (*iter
))
6324 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6327 contains_symbolic_reference_p (const_rtx x
)
6329 subrtx_iterator::array_type array
;
6330 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6331 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6337 /* Return true if X contains a thread-local symbol. */
6340 tls_referenced_p (const_rtx x
)
6342 if (!targetm
.have_tls
)
6345 subrtx_iterator::array_type array
;
6346 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6347 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)