| blob | 5fdbdbe860476d31ed3099ee73f3c60801e92fc4 |
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
12 ;; version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ;; for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;
24 ;; See constraints.md for a description of constraints specific to s390.
25 ;;
27 ;; Special formats used for outputting 390 instructions.
28 ;;
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
39 ;;
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
49 ;;
50 ;; We have a special constraint for pattern matching.
51 ;;
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
53 ;;
55 ;;
56 ;; UNSPEC usage
57 ;;
59 (define_c_enum "unspec" [
60 ; Miscellaneous
61 UNSPEC_ROUND
62 UNSPEC_ICM
63 UNSPEC_TIE
65 ; Convert CC into a str comparison result and copy it into an
66 ; integer register
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
71 UNSPEC_CC_TO_INT
73 ; GOT/PLT and lt-relative accesses
74 UNSPEC_LTREL_OFFSET
75 UNSPEC_LTREL_BASE
76 UNSPEC_POOL_OFFSET
77 UNSPEC_GOTENT
78 UNSPEC_GOT
79 UNSPEC_GOTOFF
80 UNSPEC_PLT
81 UNSPEC_PLTOFF
83 ; Literal pool
84 UNSPEC_RELOAD_BASE
85 UNSPEC_MAIN_BASE
86 UNSPEC_LTREF
87 UNSPEC_INSN
88 UNSPEC_EXECUTE
90 ; Atomic Support
91 UNSPEC_MB
92 UNSPEC_MOVA
94 ; TLS relocation specifiers
95 UNSPEC_TLSGD
96 UNSPEC_TLSLDM
97 UNSPEC_NTPOFF
98 UNSPEC_DTPOFF
99 UNSPEC_GOTNTPOFF
100 UNSPEC_INDNTPOFF
102 ; TLS support
103 UNSPEC_TLSLDM_NTPOFF
104 UNSPEC_TLS_LOAD
106 ; String Functions
107 UNSPEC_SRST
108 UNSPEC_MVST
110 ; Stack Smashing Protector
111 UNSPEC_SP_SET
112 UNSPEC_SP_TEST
114 ; Test Data Class (TDC)
115 UNSPEC_TDC_INSN
117 ; Population Count
118 UNSPEC_POPCNT
119 UNSPEC_COPYSIGN
121 ; Load FP Integer
122 UNSPEC_FPINT_FLOOR
123 UNSPEC_FPINT_BTRUNC
124 UNSPEC_FPINT_ROUND
125 UNSPEC_FPINT_CEIL
126 UNSPEC_FPINT_NEARBYINT
127 UNSPEC_FPINT_RINT
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv" [
135 ; Blockage
136 UNSPECV_BLOCKAGE
138 ; TPF Support
139 UNSPECV_TPF_PROLOGUE
140 UNSPECV_TPF_EPILOGUE
142 ; Literal pool
143 UNSPECV_POOL
144 UNSPECV_POOL_SECTION
145 UNSPECV_POOL_ALIGN
146 UNSPECV_POOL_ENTRY
147 UNSPECV_MAIN_POOL
149 ; TLS support
150 UNSPECV_SET_TP
152 ; Atomic Support
153 UNSPECV_CAS
154 UNSPECV_ATOMIC_OP
156 ; Transactional Execution support
157 UNSPECV_TBEGIN
158 UNSPECV_TBEGIN_TDB
159 UNSPECV_TBEGINC
160 UNSPECV_TEND
161 UNSPECV_TABORT
162 UNSPECV_ETND
163 UNSPECV_NTSTG
164 UNSPECV_PPA
165 ])
167 ;;
168 ;; Registers
169 ;;
171 ; Registers with special meaning
173 (define_constants
174 [
175 ; Sibling call register.
176 (SIBCALL_REGNUM 1)
177 ; Literal pool base register.
178 (BASE_REGNUM 13)
179 ; Return address register.
180 (RETURN_REGNUM 14)
181 ; Condition code register.
182 (CC_REGNUM 33)
183 ; Thread local storage pointer register.
184 (TP_REGNUM 36)
185 ])
187 ; Hardware register names
189 (define_constants
190 [
191 ; General purpose registers
192 (GPR0_REGNUM 0)
193 ; Floating point registers.
194 (FPR0_REGNUM 16)
195 (FPR1_REGNUM 20)
196 (FPR2_REGNUM 17)
197 (FPR3_REGNUM 21)
198 (FPR4_REGNUM 18)
199 (FPR5_REGNUM 22)
200 (FPR6_REGNUM 19)
201 (FPR7_REGNUM 23)
202 (FPR8_REGNUM 24)
203 (FPR9_REGNUM 28)
204 (FPR10_REGNUM 25)
205 (FPR11_REGNUM 29)
206 (FPR12_REGNUM 26)
207 (FPR13_REGNUM 30)
208 (FPR14_REGNUM 27)
209 (FPR15_REGNUM 31)
210 ])
212 ;;
213 ;; PFPO GPR0 argument format
214 ;;
216 (define_constants
217 [
218 ; PFPO operation type
219 (PFPO_CONVERT 0x1000000)
220 ; PFPO operand types
221 (PFPO_OP_TYPE_SF 0x5)
222 (PFPO_OP_TYPE_DF 0x6)
223 (PFPO_OP_TYPE_TF 0x7)
224 (PFPO_OP_TYPE_SD 0x8)
225 (PFPO_OP_TYPE_DD 0x9)
226 (PFPO_OP_TYPE_TD 0xa)
227 ; Bitposition of operand types
228 (PFPO_OP0_TYPE_SHIFT 16)
229 (PFPO_OP1_TYPE_SHIFT 8)
230 ])
232 ; Immediate operands for tbegin and tbeginc
233 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
234 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
236 ;; Instruction operand type as used in the Principles of Operation.
237 ;; Used to determine defaults for length and other attribute values.
239 (define_attr "op_type"
240 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
241 (const_string "NN"))
243 ;; Instruction type attribute used for scheduling.
245 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
246 cs,vs,store,sem,idiv,
247 imulhi,imulsi,imuldi,
248 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
249 floadtf,floaddf,floadsf,fstoredf,fstoresf,
250 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
251 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
252 fmadddf,fmaddsf,
253 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
254 itoftf, itofdf, itofsf, itofdd, itoftd,
255 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
256 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
257 ftoidfp, other"
258 (cond [(eq_attr "op_type" "NN") (const_string "other")
259 (eq_attr "op_type" "SS") (const_string "cs")]
260 (const_string "integer")))
262 ;; Another attribute used for scheduling purposes:
263 ;; agen: Instruction uses the address generation unit
264 ;; reg: Instruction does not use the agen unit
266 (define_attr "atype" "agen,reg"
267 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
268 (const_string "reg")
269 (const_string "agen")))
271 ;; Properties concerning Z10 execution grouping and value forwarding.
272 ;; z10_super: instruction is superscalar.
273 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
274 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
275 ;; target register. It can forward this value to a second instruction that reads
276 ;; the same register if that second instruction is issued in the same group.
277 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
278 ;; instruction in the S pipe writes to the register, then the T instruction
279 ;; can immediately read the new value.
280 ;; z10_fr: union of Z10_fwd and z10_rec.
281 ;; z10_c: second operand of instruction is a register and read with complemented bits.
282 ;;
283 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
286 (define_attr "z10prop" "none,
287 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
288 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
289 z10_rec,
290 z10_fr, z10_fr_A3, z10_fr_E1,
291 z10_c"
292 (const_string "none"))
294 ;; Properties concerning Z196 decoding
295 ;; z196_alone: must group alone
296 ;; z196_end: ends a group
297 ;; z196_cracked: instruction is cracked or expanded
298 (define_attr "z196prop" "none,
299 z196_alone, z196_ends,
300 z196_cracked"
301 (const_string "none"))
303 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
305 ;; Length in bytes.
307 (define_attr "length" ""
308 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
309 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
310 (const_int 6)))
313 ;; Processor type. This attribute must exactly match the processor_type
314 ;; enumeration in s390.h. The current machine description does not
315 ;; distinguish between g5 and g6, but there are differences between the two
316 ;; CPUs could in theory be modeled.
318 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
319 (const (symbol_ref "s390_tune_attr")))
321 (define_attr "cpu_facility"
322 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
323 (const_string "standard"))
325 (define_attr "enabled" ""
326 (cond [(eq_attr "cpu_facility" "standard")
327 (const_int 1)
329 (and (eq_attr "cpu_facility" "ieee")
330 (match_test "TARGET_CPU_IEEE_FLOAT"))
331 (const_int 1)
333 (and (eq_attr "cpu_facility" "zarch")
334 (match_test "TARGET_ZARCH"))
335 (const_int 1)
337 (and (eq_attr "cpu_facility" "longdisp")
338 (match_test "TARGET_LONG_DISPLACEMENT"))
339 (const_int 1)
341 (and (eq_attr "cpu_facility" "extimm")
342 (match_test "TARGET_EXTIMM"))
343 (const_int 1)
345 (and (eq_attr "cpu_facility" "dfp")
346 (match_test "TARGET_DFP"))
347 (const_int 1)
349 (and (eq_attr "cpu_facility" "cpu_zarch")
350 (match_test "TARGET_CPU_ZARCH"))
351 (const_int 1)
353 (and (eq_attr "cpu_facility" "z10")
354 (match_test "TARGET_Z10"))
355 (const_int 1)
357 (and (eq_attr "cpu_facility" "z196")
358 (match_test "TARGET_Z196"))
359 (const_int 1)
361 (and (eq_attr "cpu_facility" "zEC12")
362 (match_test "TARGET_ZEC12"))
363 (const_int 1)]
364 (const_int 0)))
366 ;; Pipeline description for z900. For lack of anything better,
367 ;; this description is also used for the g5 and g6.
368 (include "2064.md")
370 ;; Pipeline description for z990, z9-109 and z9-ec.
371 (include "2084.md")
373 ;; Pipeline description for z10
374 (include "2097.md")
376 ;; Pipeline description for z196
377 (include "2817.md")
379 ;; Pipeline description for zEC12
380 (include "2827.md")
382 ;; Predicates
383 (include "predicates.md")
385 ;; Constraint definitions
386 (include "constraints.md")
388 ;; Other includes
389 (include "tpf.md")
391 ;; Iterators
393 ;; These mode iterators allow floating point patterns to be generated from the
394 ;; same template.
395 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
396 (SD "TARGET_HARD_DFP")])
397 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
398 (define_mode_iterator FPALL [TF DF SF TD DD SD])
399 (define_mode_iterator BFP [TF DF SF])
400 (define_mode_iterator DFP [TD DD])
401 (define_mode_iterator DFP_ALL [TD DD SD])
402 (define_mode_iterator DSF [DF SF])
403 (define_mode_iterator SD_SF [SF SD])
404 (define_mode_iterator DD_DF [DF DD])
405 (define_mode_iterator TD_TF [TF TD])
407 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
408 ;; from the same template.
409 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
410 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
411 (define_mode_iterator DSI [DI SI])
412 (define_mode_iterator TDI [TI DI])
414 ;; These mode iterators allow :P to be used for patterns that operate on
415 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
416 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
418 ;; These macros refer to the actual word_mode of the configuration.
419 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
420 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
421 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
423 ;; Used by the umul pattern to express modes having half the size.
424 (define_mode_attr DWH [(TI "DI") (DI "SI")])
425 (define_mode_attr dwh [(TI "di") (DI "si")])
427 ;; This mode iterator allows the QI and HI patterns to be defined from
428 ;; the same template.
429 (define_mode_iterator HQI [HI QI])
431 ;; This mode iterator allows the integer patterns to be defined from the
432 ;; same template.
433 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
434 (define_mode_iterator INTALL [TI DI SI HI QI])
435 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
437 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
438 ;; the same template.
439 (define_code_iterator SHIFT [ashift lshiftrt])
441 ;; This iterator allows r[ox]sbg to be defined with the same template
442 (define_code_iterator IXOR [ior xor])
444 ;; This iterator is used to expand the patterns for the nearest
445 ;; integer functions.
446 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
447 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
448 UNSPEC_FPINT_NEARBYINT])
449 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
450 (UNSPEC_FPINT_BTRUNC "btrunc")
451 (UNSPEC_FPINT_ROUND "round")
452 (UNSPEC_FPINT_CEIL "ceil")
453 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
454 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
455 (UNSPEC_FPINT_BTRUNC "5")
456 (UNSPEC_FPINT_ROUND "1")
457 (UNSPEC_FPINT_CEIL "6")
458 (UNSPEC_FPINT_NEARBYINT "0")])
460 ;; This iterator and attribute allow to combine most atomic operations.
461 (define_code_iterator ATOMIC [and ior xor plus minus mult])
462 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
463 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
464 (plus "add") (minus "sub") (mult "nand")])
465 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
467 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
468 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
469 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
471 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
472 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
473 ;; SDmode.
474 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
476 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
477 ;; Likewise for "<RXe>".
478 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
479 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
481 ;; The decimal floating point variants of add, sub, div and mul support 3
482 ;; fp register operands. The following attributes allow to merge the bfp and
483 ;; dfp variants in a single insn definition.
485 ;; This attribute is used to set op_type accordingly.
486 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
487 (DD "RRR") (SD "RRR")])
489 ;; This attribute is used in the operand constraint list in order to have the
490 ;; first and the second operand match for bfp modes.
491 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
493 ;; This attribute is used in the operand list of the instruction to have an
494 ;; additional operand for the dfp instructions.
495 (define_mode_attr op1 [(TF "") (DF "") (SF "")
496 (TD "%1,") (DD "%1,") (SD "%1,")])
499 ;; This attribute is used in the operand constraint list
500 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
501 ;; TFmode values are represented by a fp register pair. Since the
502 ;; sign bit instructions only handle single source and target fp registers
503 ;; these instructions can only be used for TFmode values if the source and
504 ;; target operand uses the same fp register.
505 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
507 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
508 ;; This is used to disable the memory alternative in TFmode patterns.
509 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
511 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
512 ;; within instruction mnemonics.
513 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
515 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
516 ;; modes and to an empty string for bfp modes.
517 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
519 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
520 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
521 ;; version only operates on one register.
522 (define_mode_attr d0 [(DI "d") (SI "0")])
524 ;; In combination with d0 this allows to combine instructions of which the 31bit
525 ;; version only operates on one register. The DImode version needs an additional
526 ;; register for the assembler output.
527 (define_mode_attr 1 [(DI "%1,") (SI "")])
529 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
530 ;; 'ashift' and "srdl" in 'lshiftrt'.
531 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
533 ;; In SHIFT templates, this attribute holds the correct standard name for the
534 ;; pattern itself and the corresponding function calls.
535 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
537 ;; This attribute handles differences in the instruction 'type' and will result
538 ;; in "RRE" for DImode and "RR" for SImode.
539 (define_mode_attr E [(DI "E") (SI "")])
541 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
542 ;; to result in "RXY" for DImode and "RX" for SImode.
543 (define_mode_attr Y [(DI "Y") (SI "")])
545 ;; This attribute handles differences in the instruction 'type' and will result
546 ;; in "RSE" for TImode and "RS" for DImode.
547 (define_mode_attr TE [(TI "E") (DI "")])
549 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
550 ;; and "lcr" in SImode.
551 (define_mode_attr g [(DI "g") (SI "")])
553 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
554 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
555 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
556 ;; variant for long displacements.
557 (define_mode_attr y [(DI "g") (SI "y")])
559 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
560 ;; and "cds" in DImode.
561 (define_mode_attr tg [(TI "g") (DI "")])
563 ;; In TDI templates, a string like "c<d>sg".
564 (define_mode_attr td [(TI "d") (DI "")])
566 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
567 ;; and "cfdbr" in SImode.
568 (define_mode_attr gf [(DI "g") (SI "f")])
570 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
571 ;; and sllk for SI. This way it is possible to merge the new z196 SI
572 ;; 3 operands shift instructions into the existing patterns.
573 (define_mode_attr gk [(DI "g") (SI "k")])
575 ;; ICM mask required to load MODE value into the lowest subreg
576 ;; of a SImode register.
577 (define_mode_attr icm_lo [(HI "3") (QI "1")])
579 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
580 ;; HImode and "llgc" in QImode.
581 (define_mode_attr hc [(HI "h") (QI "c")])
583 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
584 ;; in SImode.
585 (define_mode_attr DBL [(DI "TI") (SI "DI")])
587 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
588 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
589 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
591 ;; Maximum unsigned integer that fits in MODE.
592 (define_mode_attr max_uint [(HI "65535") (QI "255")])
594 ;; Start and end field computations for RISBG et al.
595 (define_mode_attr bfstart [(DI "s") (SI "t")])
596 (define_mode_attr bfend [(DI "e") (SI "f")])
598 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
599 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
601 ;; Allow return and simple_return to be defined from a single template.
602 (define_code_iterator ANY_RETURN [return simple_return])
604 ;;
605 ;;- Compare instructions.
606 ;;
608 ; Test-under-Mask instructions
610 (define_insn "*tmqi_mem"
611 [(set (reg CC_REGNUM)
612 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
613 (match_operand:QI 1 "immediate_operand" "n,n"))
614 (match_operand:QI 2 "immediate_operand" "n,n")))]
615 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
616 "@
617 tm\t%S0,%b1
618 tmy\t%S0,%b1"
619 [(set_attr "op_type" "SI,SIY")
620 (set_attr "z10prop" "z10_super,z10_super")])
622 (define_insn "*tmdi_reg"
623 [(set (reg CC_REGNUM)
624 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
625 (match_operand:DI 1 "immediate_operand"
626 "N0HD0,N1HD0,N2HD0,N3HD0"))
627 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
628 "TARGET_ZARCH
629 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
630 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
631 "@
632 tmhh\t%0,%i1
633 tmhl\t%0,%i1
634 tmlh\t%0,%i1
635 tmll\t%0,%i1"
636 [(set_attr "op_type" "RI")
637 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
639 (define_insn "*tmsi_reg"
640 [(set (reg CC_REGNUM)
641 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
642 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
643 (match_operand:SI 2 "immediate_operand" "n,n")))]
644 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
645 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
646 "@
647 tmh\t%0,%i1
648 tml\t%0,%i1"
649 [(set_attr "op_type" "RI")
650 (set_attr "z10prop" "z10_super,z10_super")])
652 (define_insn "*tm<mode>_full"
653 [(set (reg CC_REGNUM)
654 (compare (match_operand:HQI 0 "register_operand" "d")
655 (match_operand:HQI 1 "immediate_operand" "n")))]
656 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
657 "tml\t%0,<max_uint>"
658 [(set_attr "op_type" "RI")
659 (set_attr "z10prop" "z10_super")])
662 ;
663 ; Load-and-Test instructions
664 ;
666 ; tst(di|si) instruction pattern(s).
668 (define_insn "*tstdi_sign"
669 [(set (reg CC_REGNUM)
670 (compare
671 (ashiftrt:DI
672 (ashift:DI
673 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
674 (const_int 32)) (const_int 32))
675 (match_operand:DI 1 "const0_operand" "")))
676 (set (match_operand:DI 2 "register_operand" "=d,d")
677 (sign_extend:DI (match_dup 0)))]
678 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
679 "ltgfr\t%2,%0
680 ltgf\t%2,%0"
681 [(set_attr "op_type" "RRE,RXY")
682 (set_attr "cpu_facility" "*,z10")
683 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
685 ; ltr, lt, ltgr, ltg
686 (define_insn "*tst<mode>_extimm"
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
689 (match_operand:GPR 1 "const0_operand" "")))
690 (set (match_operand:GPR 2 "register_operand" "=d,d")
691 (match_dup 0))]
692 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
693 "@
694 lt<g>r\t%2,%0
695 lt<g>\t%2,%0"
696 [(set_attr "op_type" "RR<E>,RXY")
697 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
699 ; ltr, lt, ltgr, ltg
700 (define_insn "*tst<mode>_cconly_extimm"
701 [(set (reg CC_REGNUM)
702 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
703 (match_operand:GPR 1 "const0_operand" "")))
704 (clobber (match_scratch:GPR 2 "=X,d"))]
705 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
706 "@
707 lt<g>r\t%0,%0
708 lt<g>\t%2,%0"
709 [(set_attr "op_type" "RR<E>,RXY")
710 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
712 (define_insn "*tstdi"
713 [(set (reg CC_REGNUM)
714 (compare (match_operand:DI 0 "register_operand" "d")
715 (match_operand:DI 1 "const0_operand" "")))
716 (set (match_operand:DI 2 "register_operand" "=d")
717 (match_dup 0))]
718 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
719 "ltgr\t%2,%0"
720 [(set_attr "op_type" "RRE")
721 (set_attr "z10prop" "z10_fr_E1")])
723 (define_insn "*tstsi"
724 [(set (reg CC_REGNUM)
725 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
726 (match_operand:SI 1 "const0_operand" "")))
727 (set (match_operand:SI 2 "register_operand" "=d,d,d")
728 (match_dup 0))]
729 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
730 "@
731 ltr\t%2,%0
732 icm\t%2,15,%S0
733 icmy\t%2,15,%S0"
734 [(set_attr "op_type" "RR,RS,RSY")
735 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
737 (define_insn "*tstsi_cconly"
738 [(set (reg CC_REGNUM)
739 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
740 (match_operand:SI 1 "const0_operand" "")))
741 (clobber (match_scratch:SI 2 "=X,d,d"))]
742 "s390_match_ccmode(insn, CCSmode)"
743 "@
744 ltr\t%0,%0
745 icm\t%2,15,%S0
746 icmy\t%2,15,%S0"
747 [(set_attr "op_type" "RR,RS,RSY")
748 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
750 (define_insn "*tstdi_cconly_31"
751 [(set (reg CC_REGNUM)
752 (compare (match_operand:DI 0 "register_operand" "d")
753 (match_operand:DI 1 "const0_operand" "")))]
754 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
755 "srda\t%0,0"
756 [(set_attr "op_type" "RS")
757 (set_attr "atype" "reg")])
759 ; ltr, ltgr
760 (define_insn "*tst<mode>_cconly2"
761 [(set (reg CC_REGNUM)
762 (compare (match_operand:GPR 0 "register_operand" "d")
763 (match_operand:GPR 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode)"
765 "lt<g>r\t%0,%0"
766 [(set_attr "op_type" "RR<E>")
767 (set_attr "z10prop" "z10_fr_E1")])
769 ; tst(hi|qi) instruction pattern(s).
771 (define_insn "*tst<mode>CCT"
772 [(set (reg CC_REGNUM)
773 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
774 (match_operand:HQI 1 "const0_operand" "")))
775 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
776 (match_dup 0))]
777 "s390_match_ccmode(insn, CCTmode)"
778 "@
779 icm\t%2,<icm_lo>,%S0
780 icmy\t%2,<icm_lo>,%S0
781 tml\t%0,<max_uint>"
782 [(set_attr "op_type" "RS,RSY,RI")
783 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
785 (define_insn "*tsthiCCT_cconly"
786 [(set (reg CC_REGNUM)
787 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
788 (match_operand:HI 1 "const0_operand" "")))
789 (clobber (match_scratch:HI 2 "=d,d,X"))]
790 "s390_match_ccmode(insn, CCTmode)"
791 "@
792 icm\t%2,3,%S0
793 icmy\t%2,3,%S0
794 tml\t%0,65535"
795 [(set_attr "op_type" "RS,RSY,RI")
796 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
798 (define_insn "*tstqiCCT_cconly"
799 [(set (reg CC_REGNUM)
800 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
801 (match_operand:QI 1 "const0_operand" "")))]
802 "s390_match_ccmode(insn, CCTmode)"
803 "@
804 cli\t%S0,0
805 cliy\t%S0,0
806 tml\t%0,255"
807 [(set_attr "op_type" "SI,SIY,RI")
808 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
810 (define_insn "*tst<mode>"
811 [(set (reg CC_REGNUM)
812 (compare (match_operand:HQI 0 "s_operand" "Q,S")
813 (match_operand:HQI 1 "const0_operand" "")))
814 (set (match_operand:HQI 2 "register_operand" "=d,d")
815 (match_dup 0))]
816 "s390_match_ccmode(insn, CCSmode)"
817 "@
818 icm\t%2,<icm_lo>,%S0
819 icmy\t%2,<icm_lo>,%S0"
820 [(set_attr "op_type" "RS,RSY")
821 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
823 (define_insn "*tst<mode>_cconly"
824 [(set (reg CC_REGNUM)
825 (compare (match_operand:HQI 0 "s_operand" "Q,S")
826 (match_operand:HQI 1 "const0_operand" "")))
827 (clobber (match_scratch:HQI 2 "=d,d"))]
828 "s390_match_ccmode(insn, CCSmode)"
829 "@
830 icm\t%2,<icm_lo>,%S0
831 icmy\t%2,<icm_lo>,%S0"
832 [(set_attr "op_type" "RS,RSY")
833 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
836 ; Compare (equality) instructions
838 (define_insn "*cmpdi_cct"
839 [(set (reg CC_REGNUM)
840 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
841 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
842 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
843 "@
844 cgr\t%0,%1
845 cghi\t%0,%h1
846 cgfi\t%0,%1
847 cg\t%0,%1
848 #"
849 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
850 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
852 (define_insn "*cmpsi_cct"
853 [(set (reg CC_REGNUM)
854 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
855 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
856 "s390_match_ccmode (insn, CCTmode)"
857 "@
858 cr\t%0,%1
859 chi\t%0,%h1
860 cfi\t%0,%1
861 c\t%0,%1
862 cy\t%0,%1
863 #"
864 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
865 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
867 ; Compare (signed) instructions
869 (define_insn "*cmpdi_ccs_sign"
870 [(set (reg CC_REGNUM)
871 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
872 "d,RT,b"))
873 (match_operand:DI 0 "register_operand" "d, d,d")))]
874 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
875 "@
876 cgfr\t%0,%1
877 cgf\t%0,%1
878 cgfrl\t%0,%1"
879 [(set_attr "op_type" "RRE,RXY,RIL")
880 (set_attr "z10prop" "z10_c,*,*")
881 (set_attr "type" "*,*,larl")])
885 (define_insn "*cmpsi_ccs_sign"
886 [(set (reg CC_REGNUM)
887 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
888 (match_operand:SI 0 "register_operand" "d,d,d")))]
889 "s390_match_ccmode(insn, CCSRmode)"
890 "@
891 ch\t%0,%1
892 chy\t%0,%1
893 chrl\t%0,%1"
894 [(set_attr "op_type" "RX,RXY,RIL")
895 (set_attr "cpu_facility" "*,*,z10")
896 (set_attr "type" "*,*,larl")
897 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
899 (define_insn "*cmphi_ccs_z10"
900 [(set (reg CC_REGNUM)
901 (compare (match_operand:HI 0 "s_operand" "Q")
902 (match_operand:HI 1 "immediate_operand" "K")))]
903 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
904 "chhsi\t%0,%1"
905 [(set_attr "op_type" "SIL")
906 (set_attr "z196prop" "z196_cracked")])
908 (define_insn "*cmpdi_ccs_signhi_rl"
909 [(set (reg CC_REGNUM)
910 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
911 (match_operand:GPR 0 "register_operand" "d,d")))]
912 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
913 "@
914 cgh\t%0,%1
915 cghrl\t%0,%1"
916 [(set_attr "op_type" "RXY,RIL")
917 (set_attr "type" "*,larl")])
919 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
920 (define_insn "*cmp<mode>_ccs"
921 [(set (reg CC_REGNUM)
922 (compare (match_operand:GPR 0 "nonimmediate_operand"
923 "d,d,Q, d,d,d,d")
924 (match_operand:GPR 1 "general_operand"
925 "d,K,K,Os,R,T,b")))]
926 "s390_match_ccmode(insn, CCSmode)"
927 "@
928 c<g>r\t%0,%1
929 c<g>hi\t%0,%h1
930 c<g>hsi\t%0,%h1
931 c<g>fi\t%0,%1
932 c<g>\t%0,%1
933 c<y>\t%0,%1
934 c<g>rl\t%0,%1"
935 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
936 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
937 (set_attr "type" "*,*,*,*,*,*,larl")
938 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
941 ; Compare (unsigned) instructions
943 (define_insn "*cmpsi_ccu_zerohi_rlsi"
944 [(set (reg CC_REGNUM)
945 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
946 "larl_operand" "X")))
947 (match_operand:SI 0 "register_operand" "d")))]
948 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
949 "clhrl\t%0,%1"
950 [(set_attr "op_type" "RIL")
951 (set_attr "type" "larl")
952 (set_attr "z10prop" "z10_super")])
954 ; clhrl, clghrl
955 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
956 [(set (reg CC_REGNUM)
957 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
958 "larl_operand" "X")))
959 (match_operand:GPR 0 "register_operand" "d")))]
960 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
961 "cl<g>hrl\t%0,%1"
962 [(set_attr "op_type" "RIL")
963 (set_attr "type" "larl")
964 (set_attr "z10prop" "z10_super")])
966 (define_insn "*cmpdi_ccu_zero"
967 [(set (reg CC_REGNUM)
968 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
969 "d,RT,b"))
970 (match_operand:DI 0 "register_operand" "d, d,d")))]
971 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
972 "@
973 clgfr\t%0,%1
974 clgf\t%0,%1
975 clgfrl\t%0,%1"
976 [(set_attr "op_type" "RRE,RXY,RIL")
977 (set_attr "cpu_facility" "*,*,z10")
978 (set_attr "type" "*,*,larl")
979 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
981 (define_insn "*cmpdi_ccu"
982 [(set (reg CC_REGNUM)
983 (compare (match_operand:DI 0 "nonimmediate_operand"
984 "d, d,d,Q, d, Q,BQ")
985 (match_operand:DI 1 "general_operand"
986 "d,Op,b,D,RT,BQ,Q")))]
987 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
988 "@
989 clgr\t%0,%1
990 clgfi\t%0,%1
991 clgrl\t%0,%1
992 clghsi\t%0,%x1
993 clg\t%0,%1
994 #
995 #"
996 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
997 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
998 (set_attr "type" "*,*,larl,*,*,*,*")
999 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1001 (define_insn "*cmpsi_ccu"
1002 [(set (reg CC_REGNUM)
1003 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1004 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1005 "s390_match_ccmode (insn, CCUmode)"
1006 "@
1007 clr\t%0,%1
1008 clfi\t%0,%o1
1009 clrl\t%0,%1
1010 clfhsi\t%0,%x1
1011 cl\t%0,%1
1012 cly\t%0,%1
1013 #
1014 #"
1015 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1016 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1017 (set_attr "type" "*,*,larl,*,*,*,*,*")
1018 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1020 (define_insn "*cmphi_ccu"
1021 [(set (reg CC_REGNUM)
1022 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1023 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1024 "s390_match_ccmode (insn, CCUmode)
1025 && !register_operand (operands[1], HImode)"
1026 "@
1027 clm\t%0,3,%S1
1028 clmy\t%0,3,%S1
1029 clhhsi\t%0,%1
1030 #
1031 #"
1032 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1033 (set_attr "cpu_facility" "*,*,z10,*,*")
1034 (set_attr "z10prop" "*,*,z10_super,*,*")])
1036 (define_insn "*cmpqi_ccu"
1037 [(set (reg CC_REGNUM)
1038 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1039 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1040 "s390_match_ccmode (insn, CCUmode)
1041 && !register_operand (operands[1], QImode)"
1042 "@
1043 clm\t%0,1,%S1
1044 clmy\t%0,1,%S1
1045 cli\t%S0,%b1
1046 cliy\t%S0,%b1
1047 #
1048 #"
1049 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1050 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1053 ; Block compare (CLC) instruction patterns.
1055 (define_insn "*clc"
1056 [(set (reg CC_REGNUM)
1057 (compare (match_operand:BLK 0 "memory_operand" "Q")
1058 (match_operand:BLK 1 "memory_operand" "Q")))
1059 (use (match_operand 2 "const_int_operand" "n"))]
1060 "s390_match_ccmode (insn, CCUmode)
1061 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1062 "clc\t%O0(%2,%R0),%S1"
1063 [(set_attr "op_type" "SS")])
1065 (define_split
1066 [(set (reg CC_REGNUM)
1067 (compare (match_operand 0 "memory_operand" "")
1068 (match_operand 1 "memory_operand" "")))]
1069 "reload_completed
1070 && s390_match_ccmode (insn, CCUmode)
1071 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1072 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1073 [(parallel
1074 [(set (match_dup 0) (match_dup 1))
1075 (use (match_dup 2))])]
1076 {
1077 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1078 operands[0] = adjust_address (operands[0], BLKmode, 0);
1079 operands[1] = adjust_address (operands[1], BLKmode, 0);
1081 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1082 operands[0], operands[1]);
1083 operands[0] = SET_DEST (PATTERN (curr_insn));
1084 })
1087 ; (TF|DF|SF|TD|DD|SD) instructions
1089 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1090 (define_insn "*cmp<mode>_ccs_0"
1091 [(set (reg CC_REGNUM)
1092 (compare (match_operand:FP 0 "register_operand" "f")
1093 (match_operand:FP 1 "const0_operand" "")))]
1094 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1095 "lt<xde><bt>r\t%0,%0"
1096 [(set_attr "op_type" "RRE")
1097 (set_attr "type" "fsimp<mode>")])
1099 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1100 (define_insn "*cmp<mode>_ccs"
1101 [(set (reg CC_REGNUM)
1102 (compare (match_operand:FP 0 "register_operand" "f,f")
1103 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1104 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1105 "@
1106 c<xde><bt>r\t%0,%1
1107 c<xde>b\t%0,%1"
1108 [(set_attr "op_type" "RRE,RXE")
1109 (set_attr "type" "fsimp<mode>")])
1112 ; Compare and Branch instructions
1114 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1115 ; The following instructions do a complementary access of their second
1116 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1117 (define_insn "*cmp_and_br_signed_<mode>"
1118 [(set (pc)
1119 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1120 [(match_operand:GPR 1 "register_operand" "d,d")
1121 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1122 (label_ref (match_operand 3 "" ""))
1123 (pc)))
1124 (clobber (reg:CC CC_REGNUM))]
1125 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1126 {
1127 if (get_attr_length (insn) == 6)
1128 return which_alternative ?
1129 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1130 else
1131 return which_alternative ?
1132 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1133 }
1134 [(set_attr "op_type" "RIE")
1135 (set_attr "type" "branch")
1136 (set_attr "z10prop" "z10_super_c,z10_super")
1137 (set (attr "length")
1138 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1139 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1140 ; 10 byte for cgr/jg
1142 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1143 ; The following instructions do a complementary access of their second
1144 ; operand (z10 only): clrj, clgrj, clr, clgr
1145 (define_insn "*cmp_and_br_unsigned_<mode>"
1146 [(set (pc)
1147 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1148 [(match_operand:GPR 1 "register_operand" "d,d")
1149 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1150 (label_ref (match_operand 3 "" ""))
1151 (pc)))
1152 (clobber (reg:CC CC_REGNUM))]
1153 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1154 {
1155 if (get_attr_length (insn) == 6)
1156 return which_alternative ?
1157 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1158 else
1159 return which_alternative ?
1160 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1161 }
1162 [(set_attr "op_type" "RIE")
1163 (set_attr "type" "branch")
1164 (set_attr "z10prop" "z10_super_c,z10_super")
1165 (set (attr "length")
1166 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1167 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1168 ; 10 byte for clgr/jg
1170 ; And now the same two patterns as above but with a negated CC mask.
1172 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1173 ; The following instructions do a complementary access of their second
1174 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1175 (define_insn "*icmp_and_br_signed_<mode>"
1176 [(set (pc)
1177 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1178 [(match_operand:GPR 1 "register_operand" "d,d")
1179 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1180 (pc)
1181 (label_ref (match_operand 3 "" ""))))
1182 (clobber (reg:CC CC_REGNUM))]
1183 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1184 {
1185 if (get_attr_length (insn) == 6)
1186 return which_alternative ?
1187 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1188 else
1189 return which_alternative ?
1190 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1191 }
1192 [(set_attr "op_type" "RIE")
1193 (set_attr "type" "branch")
1194 (set_attr "z10prop" "z10_super_c,z10_super")
1195 (set (attr "length")
1196 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1197 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1198 ; 10 byte for cgr/jg
1200 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1201 ; The following instructions do a complementary access of their second
1202 ; operand (z10 only): clrj, clgrj, clr, clgr
1203 (define_insn "*icmp_and_br_unsigned_<mode>"
1204 [(set (pc)
1205 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1206 [(match_operand:GPR 1 "register_operand" "d,d")
1207 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1208 (pc)
1209 (label_ref (match_operand 3 "" ""))))
1210 (clobber (reg:CC CC_REGNUM))]
1211 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1212 {
1213 if (get_attr_length (insn) == 6)
1214 return which_alternative ?
1215 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1216 else
1217 return which_alternative ?
1218 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1219 }
1220 [(set_attr "op_type" "RIE")
1221 (set_attr "type" "branch")
1222 (set_attr "z10prop" "z10_super_c,z10_super")
1223 (set (attr "length")
1224 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1225 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1226 ; 10 byte for clgr/jg
1228 ;;
1229 ;;- Move instructions.
1230 ;;
1232 ;
1233 ; movti instruction pattern(s).
1234 ;
1236 (define_insn "movti"
1237 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1238 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1239 "TARGET_ZARCH"
1240 "@
1241 lmg\t%0,%N0,%S1
1242 stmg\t%1,%N1,%S0
1243 #
1244 #"
1245 [(set_attr "op_type" "RSY,RSY,*,*")
1246 (set_attr "type" "lm,stm,*,*")])
1248 (define_split
1249 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1250 (match_operand:TI 1 "general_operand" ""))]
1251 "TARGET_ZARCH && reload_completed
1252 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1253 [(set (match_dup 2) (match_dup 4))
1254 (set (match_dup 3) (match_dup 5))]
1255 {
1256 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1257 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1258 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1259 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1260 })
1262 (define_split
1263 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1264 (match_operand:TI 1 "general_operand" ""))]
1265 "TARGET_ZARCH && reload_completed
1266 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1267 [(set (match_dup 2) (match_dup 4))
1268 (set (match_dup 3) (match_dup 5))]
1269 {
1270 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1271 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1272 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1273 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1274 })
1276 (define_split
1277 [(set (match_operand:TI 0 "register_operand" "")
1278 (match_operand:TI 1 "memory_operand" ""))]
1279 "TARGET_ZARCH && reload_completed
1280 && !s_operand (operands[1], VOIDmode)"
1281 [(set (match_dup 0) (match_dup 1))]
1282 {
1283 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1284 addr = gen_lowpart (Pmode, addr);
1285 s390_load_address (addr, XEXP (operands[1], 0));
1286 operands[1] = replace_equiv_address (operands[1], addr);
1287 })
1290 ;
1291 ; Patterns used for secondary reloads
1292 ;
1294 ; z10 provides move instructions accepting larl memory operands.
1295 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1296 ; These patterns are also used for unaligned SI and DI accesses.
1298 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1299 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1300 (match_operand:INTALL 1 "register_operand" "=d")
1301 (match_operand:P 2 "register_operand" "=&a")])]
1302 "TARGET_Z10"
1303 {
1304 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1305 DONE;
1306 })
1308 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1309 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1310 (match_operand:INTALL 1 "memory_operand" "")
1311 (match_operand:P 2 "register_operand" "=a")])]
1312 "TARGET_Z10"
1313 {
1314 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1315 DONE;
1316 })
1318 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1319 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1320 (match_operand:FPALL 1 "register_operand" "=d")
1321 (match_operand:P 2 "register_operand" "=&a")])]
1322 "TARGET_Z10"
1323 {
1324 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1325 DONE;
1326 })
1328 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1329 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1330 (match_operand:FPALL 1 "memory_operand" "")
1331 (match_operand:P 2 "register_operand" "=a")])]
1332 "TARGET_Z10"
1333 {
1334 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1335 DONE;
1336 })
1338 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1339 [(parallel [(match_operand:P 0 "register_operand" "=d")
1340 (match_operand:P 1 "larl_operand" "")
1341 (match_operand:P 2 "register_operand" "=a")])]
1342 "TARGET_Z10"
1343 {
1344 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1345 DONE;
1346 })
1348 ; Handles loading a PLUS (load address) expression
1350 (define_expand "reload<mode>_plus"
1351 [(parallel [(match_operand:P 0 "register_operand" "=a")
1352 (match_operand:P 1 "s390_plus_operand" "")
1353 (match_operand:P 2 "register_operand" "=&a")])]
1354 ""
1355 {
1356 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1357 DONE;
1358 })
1360 ; Handles assessing a non-offsetable memory address
1362 (define_expand "reload<mode>_nonoffmem_in"
1363 [(parallel [(match_operand 0 "register_operand" "")
1364 (match_operand 1 "" "")
1365 (match_operand:P 2 "register_operand" "=&a")])]
1366 ""
1367 {
1368 gcc_assert (MEM_P (operands[1]));
1369 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1370 operands[1] = replace_equiv_address (operands[1], operands[2]);
1371 emit_move_insn (operands[0], operands[1]);
1372 DONE;
1373 })
1375 (define_expand "reload<mode>_nonoffmem_out"
1376 [(parallel [(match_operand 0 "" "")
1377 (match_operand 1 "register_operand" "")
1378 (match_operand:P 2 "register_operand" "=&a")])]
1379 ""
1380 {
1381 gcc_assert (MEM_P (operands[0]));
1382 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1383 operands[0] = replace_equiv_address (operands[0], operands[2]);
1384 emit_move_insn (operands[0], operands[1]);
1385 DONE;
1386 })
1388 (define_expand "reload<mode>_PIC_addr"
1389 [(parallel [(match_operand 0 "register_operand" "=d")
1390 (match_operand 1 "larl_operand" "")
1391 (match_operand:P 2 "register_operand" "=a")])]
1392 ""
1393 {
1394 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1395 emit_move_insn (operands[0], new_rtx);
1396 })
1398 ;
1399 ; movdi instruction pattern(s).
1400 ;
1402 (define_expand "movdi"
1403 [(set (match_operand:DI 0 "general_operand" "")
1404 (match_operand:DI 1 "general_operand" ""))]
1405 ""
1406 {
1407 /* Handle symbolic constants. */
1408 if (TARGET_64BIT
1409 && (SYMBOLIC_CONST (operands[1])
1410 || (GET_CODE (operands[1]) == PLUS
1411 && XEXP (operands[1], 0) == pic_offset_table_rtx
1412 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1413 emit_symbolic_move (operands);
1414 })
1416 (define_insn "*movdi_larl"
1417 [(set (match_operand:DI 0 "register_operand" "=d")
1418 (match_operand:DI 1 "larl_operand" "X"))]
1419 "TARGET_64BIT
1420 && !FP_REG_P (operands[0])"
1421 "larl\t%0,%1"
1422 [(set_attr "op_type" "RIL")
1423 (set_attr "type" "larl")
1424 (set_attr "z10prop" "z10_super_A1")])
1426 (define_insn "*movdi_64"
1427 [(set (match_operand:DI 0 "nonimmediate_operand"
1428 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1429 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1430 (match_operand:DI 1 "general_operand"
1431 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1432 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1433 "TARGET_ZARCH"
1434 "@
1435 lghi\t%0,%h1
1436 llihh\t%0,%i1
1437 llihl\t%0,%i1
1438 llilh\t%0,%i1
1439 llill\t%0,%i1
1440 lgfi\t%0,%1
1441 llihf\t%0,%k1
1442 llilf\t%0,%k1
1443 ldgr\t%0,%1
1444 lgdr\t%0,%1
1445 lay\t%0,%a1
1446 lgrl\t%0,%1
1447 lgr\t%0,%1
1448 lg\t%0,%1
1449 stg\t%1,%0
1450 ldr\t%0,%1
1451 ld\t%0,%1
1452 ldy\t%0,%1
1453 std\t%1,%0
1454 stdy\t%1,%0
1455 stgrl\t%1,%0
1456 mvghi\t%0,%1
1457 #
1458 #
1459 stam\t%1,%N1,%S0
1460 lam\t%0,%N0,%S1"
1461 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1462 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1463 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1464 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1465 *,*")
1466 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1467 z10,*,*,*,*,*,longdisp,*,longdisp,
1468 z10,z10,*,*,*,*")
1469 (set_attr "z10prop" "z10_fwd_A1,
1470 z10_fwd_E1,
1471 z10_fwd_E1,
1472 z10_fwd_E1,
1473 z10_fwd_E1,
1474 z10_fwd_A1,
1475 z10_fwd_E1,
1476 z10_fwd_E1,
1477 *,
1478 *,
1479 z10_fwd_A1,
1480 z10_fwd_A3,
1481 z10_fr_E1,
1482 z10_fwd_A3,
1483 z10_rec,
1484 *,
1485 *,
1486 *,
1487 *,
1488 *,
1489 z10_rec,
1490 z10_super,
1491 *,
1492 *,
1493 *,
1494 *")
1495 ])
1497 (define_split
1498 [(set (match_operand:DI 0 "register_operand" "")
1499 (match_operand:DI 1 "register_operand" ""))]
1500 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1501 [(set (match_dup 2) (match_dup 3))
1502 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1503 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1504 "operands[2] = gen_lowpart (SImode, operands[0]);
1505 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1507 (define_split
1508 [(set (match_operand:DI 0 "register_operand" "")
1509 (match_operand:DI 1 "register_operand" ""))]
1510 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1511 && dead_or_set_p (insn, operands[1])"
1512 [(set (match_dup 3) (match_dup 2))
1513 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1514 (set (match_dup 4) (match_dup 2))]
1515 "operands[2] = gen_lowpart (SImode, operands[1]);
1516 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1518 (define_split
1519 [(set (match_operand:DI 0 "register_operand" "")
1520 (match_operand:DI 1 "register_operand" ""))]
1521 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1522 && !dead_or_set_p (insn, operands[1])"
1523 [(set (match_dup 3) (match_dup 2))
1524 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1525 (set (match_dup 4) (match_dup 2))
1526 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1527 "operands[2] = gen_lowpart (SImode, operands[1]);
1528 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1530 (define_insn "*movdi_31"
1531 [(set (match_operand:DI 0 "nonimmediate_operand"
1532 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1533 (match_operand:DI 1 "general_operand"
1534 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1535 "!TARGET_ZARCH"
1536 "@
1537 lm\t%0,%N0,%S1
1538 lmy\t%0,%N0,%S1
1539 stm\t%1,%N1,%S0
1540 stmy\t%1,%N1,%S0
1541 #
1542 #
1543 ldr\t%0,%1
1544 ld\t%0,%1
1545 ldy\t%0,%1
1546 std\t%1,%0
1547 stdy\t%1,%0
1548 #"
1549 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1550 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1551 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1553 ; For a load from a symbol ref we can use one of the target registers
1554 ; together with larl to load the address.
1555 (define_split
1556 [(set (match_operand:DI 0 "register_operand" "")
1557 (match_operand:DI 1 "memory_operand" ""))]
1558 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1559 && larl_operand (XEXP (operands[1], 0), SImode)"
1560 [(set (match_dup 2) (match_dup 3))
1561 (set (match_dup 0) (match_dup 1))]
1562 {
1563 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1564 operands[3] = XEXP (operands[1], 0);
1565 operands[1] = replace_equiv_address (operands[1], operands[2]);
1566 })
1568 (define_split
1569 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1570 (match_operand:DI 1 "general_operand" ""))]
1571 "!TARGET_ZARCH && reload_completed
1572 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1573 [(set (match_dup 2) (match_dup 4))
1574 (set (match_dup 3) (match_dup 5))]
1575 {
1576 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1577 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1578 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1579 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1580 })
1582 (define_split
1583 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1584 (match_operand:DI 1 "general_operand" ""))]
1585 "!TARGET_ZARCH && reload_completed
1586 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1587 [(set (match_dup 2) (match_dup 4))
1588 (set (match_dup 3) (match_dup 5))]
1589 {
1590 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1591 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1592 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1593 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1594 })
1596 (define_split
1597 [(set (match_operand:DI 0 "register_operand" "")
1598 (match_operand:DI 1 "memory_operand" ""))]
1599 "!TARGET_ZARCH && reload_completed
1600 && !FP_REG_P (operands[0])
1601 && !s_operand (operands[1], VOIDmode)"
1602 [(set (match_dup 0) (match_dup 1))]
1603 {
1604 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1605 s390_load_address (addr, XEXP (operands[1], 0));
1606 operands[1] = replace_equiv_address (operands[1], addr);
1607 })
1609 (define_peephole2
1610 [(set (match_operand:DI 0 "register_operand" "")
1611 (mem:DI (match_operand 1 "address_operand" "")))]
1612 "TARGET_ZARCH
1613 && !FP_REG_P (operands[0])
1614 && GET_CODE (operands[1]) == SYMBOL_REF
1615 && CONSTANT_POOL_ADDRESS_P (operands[1])
1616 && get_pool_mode (operands[1]) == DImode
1617 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1618 [(set (match_dup 0) (match_dup 2))]
1619 "operands[2] = get_pool_constant (operands[1]);")
1621 (define_insn "*la_64"
1622 [(set (match_operand:DI 0 "register_operand" "=d,d")
1623 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1624 "TARGET_64BIT"
1625 "@
1626 la\t%0,%a1
1627 lay\t%0,%a1"
1628 [(set_attr "op_type" "RX,RXY")
1629 (set_attr "type" "la")
1630 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1632 (define_peephole2
1633 [(parallel
1634 [(set (match_operand:DI 0 "register_operand" "")
1635 (match_operand:QI 1 "address_operand" ""))
1636 (clobber (reg:CC CC_REGNUM))])]
1637 "TARGET_64BIT
1638 && preferred_la_operand_p (operands[1], const0_rtx)"
1639 [(set (match_dup 0) (match_dup 1))]
1640 "")
1642 (define_peephole2
1643 [(set (match_operand:DI 0 "register_operand" "")
1644 (match_operand:DI 1 "register_operand" ""))
1645 (parallel
1646 [(set (match_dup 0)
1647 (plus:DI (match_dup 0)
1648 (match_operand:DI 2 "nonmemory_operand" "")))
1649 (clobber (reg:CC CC_REGNUM))])]
1650 "TARGET_64BIT
1651 && !reg_overlap_mentioned_p (operands[0], operands[2])
1652 && preferred_la_operand_p (operands[1], operands[2])"
1653 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1654 "")
1656 ;
1657 ; movsi instruction pattern(s).
1658 ;
1660 (define_expand "movsi"
1661 [(set (match_operand:SI 0 "general_operand" "")
1662 (match_operand:SI 1 "general_operand" ""))]
1663 ""
1664 {
1665 /* Handle symbolic constants. */
1666 if (!TARGET_64BIT
1667 && (SYMBOLIC_CONST (operands[1])
1668 || (GET_CODE (operands[1]) == PLUS
1669 && XEXP (operands[1], 0) == pic_offset_table_rtx
1670 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1671 emit_symbolic_move (operands);
1672 })
1674 (define_insn "*movsi_larl"
1675 [(set (match_operand:SI 0 "register_operand" "=d")
1676 (match_operand:SI 1 "larl_operand" "X"))]
1677 "!TARGET_64BIT && TARGET_CPU_ZARCH
1678 && !FP_REG_P (operands[0])"
1679 "larl\t%0,%1"
1680 [(set_attr "op_type" "RIL")
1681 (set_attr "type" "larl")
1682 (set_attr "z10prop" "z10_fwd_A1")])
1684 (define_insn "*movsi_zarch"
1685 [(set (match_operand:SI 0 "nonimmediate_operand"
1686 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1687 (match_operand:SI 1 "general_operand"
1688 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1689 "TARGET_ZARCH"
1690 "@
1691 lhi\t%0,%h1
1692 llilh\t%0,%i1
1693 llill\t%0,%i1
1694 iilf\t%0,%o1
1695 lay\t%0,%a1
1696 lrl\t%0,%1
1697 lr\t%0,%1
1698 l\t%0,%1
1699 ly\t%0,%1
1700 st\t%1,%0
1701 sty\t%1,%0
1702 ler\t%0,%1
1703 le\t%0,%1
1704 ley\t%0,%1
1705 ste\t%1,%0
1706 stey\t%1,%0
1707 ear\t%0,%1
1708 sar\t%0,%1
1709 stam\t%1,%1,%S0
1710 strl\t%1,%0
1711 mvhi\t%0,%1
1712 lam\t%0,%0,%S1"
1713 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1714 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1715 (set_attr "type" "*,
1716 *,
1717 *,
1718 *,
1719 la,
1720 larl,
1721 lr,
1722 load,
1723 load,
1724 store,
1725 store,
1726 floadsf,
1727 floadsf,
1728 floadsf,
1729 fstoresf,
1730 fstoresf,
1731 *,
1732 *,
1733 *,
1734 larl,
1735 *,
1736 *")
1737 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1738 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1739 (set_attr "z10prop" "z10_fwd_A1,
1740 z10_fwd_E1,
1741 z10_fwd_E1,
1742 z10_fwd_A1,
1743 z10_fwd_A1,
1744 z10_fwd_A3,
1745 z10_fr_E1,
1746 z10_fwd_A3,
1747 z10_fwd_A3,
1748 z10_rec,
1749 z10_rec,
1750 *,
1751 *,
1752 *,
1753 *,
1754 *,
1755 z10_super_E1,
1756 z10_super,
1757 *,
1758 z10_rec,
1759 z10_super,
1760 *")])
1762 (define_insn "*movsi_esa"
1763 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1764 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1765 "!TARGET_ZARCH"
1766 "@
1767 lhi\t%0,%h1
1768 lr\t%0,%1
1769 l\t%0,%1
1770 st\t%1,%0
1771 ler\t%0,%1
1772 le\t%0,%1
1773 ste\t%1,%0
1774 ear\t%0,%1
1775 sar\t%0,%1
1776 stam\t%1,%1,%S0
1777 lam\t%0,%0,%S1"
1778 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1779 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1780 (set_attr "z10prop" "z10_fwd_A1,
1781 z10_fr_E1,
1782 z10_fwd_A3,
1783 z10_rec,
1784 *,
1785 *,
1786 *,
1787 z10_super_E1,
1788 z10_super,
1789 *,
1790 *")
1791 ])
1793 (define_peephole2
1794 [(set (match_operand:SI 0 "register_operand" "")
1795 (mem:SI (match_operand 1 "address_operand" "")))]
1796 "!FP_REG_P (operands[0])
1797 && GET_CODE (operands[1]) == SYMBOL_REF
1798 && CONSTANT_POOL_ADDRESS_P (operands[1])
1799 && get_pool_mode (operands[1]) == SImode
1800 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1801 [(set (match_dup 0) (match_dup 2))]
1802 "operands[2] = get_pool_constant (operands[1]);")
1804 (define_insn "*la_31"
1805 [(set (match_operand:SI 0 "register_operand" "=d,d")
1806 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1807 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1808 "@
1809 la\t%0,%a1
1810 lay\t%0,%a1"
1811 [(set_attr "op_type" "RX,RXY")
1812 (set_attr "type" "la")
1813 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1815 (define_peephole2
1816 [(parallel
1817 [(set (match_operand:SI 0 "register_operand" "")
1818 (match_operand:QI 1 "address_operand" ""))
1819 (clobber (reg:CC CC_REGNUM))])]
1820 "!TARGET_64BIT
1821 && preferred_la_operand_p (operands[1], const0_rtx)"
1822 [(set (match_dup 0) (match_dup 1))]
1823 "")
1825 (define_peephole2
1826 [(set (match_operand:SI 0 "register_operand" "")
1827 (match_operand:SI 1 "register_operand" ""))
1828 (parallel
1829 [(set (match_dup 0)
1830 (plus:SI (match_dup 0)
1831 (match_operand:SI 2 "nonmemory_operand" "")))
1832 (clobber (reg:CC CC_REGNUM))])]
1833 "!TARGET_64BIT
1834 && !reg_overlap_mentioned_p (operands[0], operands[2])
1835 && preferred_la_operand_p (operands[1], operands[2])"
1836 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1837 "")
1839 (define_insn "*la_31_and"
1840 [(set (match_operand:SI 0 "register_operand" "=d,d")
1841 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1842 (const_int 2147483647)))]
1843 "!TARGET_64BIT"
1844 "@
1845 la\t%0,%a1
1846 lay\t%0,%a1"
1847 [(set_attr "op_type" "RX,RXY")
1848 (set_attr "type" "la")
1849 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1851 (define_insn_and_split "*la_31_and_cc"
1852 [(set (match_operand:SI 0 "register_operand" "=d")
1853 (and:SI (match_operand:QI 1 "address_operand" "p")
1854 (const_int 2147483647)))
1855 (clobber (reg:CC CC_REGNUM))]
1856 "!TARGET_64BIT"
1857 "#"
1858 "&& reload_completed"
1859 [(set (match_dup 0)
1860 (and:SI (match_dup 1) (const_int 2147483647)))]
1861 ""
1862 [(set_attr "op_type" "RX")
1863 (set_attr "type" "la")])
1865 (define_insn "force_la_31"
1866 [(set (match_operand:SI 0 "register_operand" "=d,d")
1867 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1868 (use (const_int 0))]
1869 "!TARGET_64BIT"
1870 "@
1871 la\t%0,%a1
1872 lay\t%0,%a1"
1873 [(set_attr "op_type" "RX")
1874 (set_attr "type" "la")
1875 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1877 ;
1878 ; movhi instruction pattern(s).
1879 ;
1881 (define_expand "movhi"
1882 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1883 (match_operand:HI 1 "general_operand" ""))]
1884 ""
1885 {
1886 /* Make it explicit that loading a register from memory
1887 always sign-extends (at least) to SImode. */
1888 if (optimize && can_create_pseudo_p ()
1889 && register_operand (operands[0], VOIDmode)
1890 && GET_CODE (operands[1]) == MEM)
1891 {
1892 rtx tmp = gen_reg_rtx (SImode);
1893 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1894 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1895 operands[1] = gen_lowpart (HImode, tmp);
1896 }
1897 })
1899 (define_insn "*movhi"
1900 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1901 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1902 ""
1903 "@
1904 lr\t%0,%1
1905 lhi\t%0,%h1
1906 lh\t%0,%1
1907 lhy\t%0,%1
1908 lhrl\t%0,%1
1909 sth\t%1,%0
1910 sthy\t%1,%0
1911 sthrl\t%1,%0
1912 mvhhi\t%0,%1"
1913 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1914 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1915 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1916 (set_attr "z10prop" "z10_fr_E1,
1917 z10_fwd_A1,
1918 z10_super_E1,
1919 z10_super_E1,
1920 z10_super_E1,
1921 z10_rec,
1922 z10_rec,
1923 z10_rec,
1924 z10_super")])
1926 (define_peephole2
1927 [(set (match_operand:HI 0 "register_operand" "")
1928 (mem:HI (match_operand 1 "address_operand" "")))]
1929 "GET_CODE (operands[1]) == SYMBOL_REF
1930 && CONSTANT_POOL_ADDRESS_P (operands[1])
1931 && get_pool_mode (operands[1]) == HImode
1932 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1933 [(set (match_dup 0) (match_dup 2))]
1934 "operands[2] = get_pool_constant (operands[1]);")
1936 ;
1937 ; movqi instruction pattern(s).
1938 ;
1940 (define_expand "movqi"
1941 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1942 (match_operand:QI 1 "general_operand" ""))]
1943 ""
1944 {
1945 /* On z/Architecture, zero-extending from memory to register
1946 is just as fast as a QImode load. */
1947 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1948 && register_operand (operands[0], VOIDmode)
1949 && GET_CODE (operands[1]) == MEM)
1950 {
1951 rtx tmp = gen_reg_rtx (DImode);
1952 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1953 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1954 operands[1] = gen_lowpart (QImode, tmp);
1955 }
1956 })
1958 (define_insn "*movqi"
1959 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1960 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1961 ""
1962 "@
1963 lr\t%0,%1
1964 lhi\t%0,%b1
1965 ic\t%0,%1
1966 icy\t%0,%1
1967 stc\t%1,%0
1968 stcy\t%1,%0
1969 mvi\t%S0,%b1
1970 mviy\t%S0,%b1
1971 #"
1972 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1973 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1974 (set_attr "z10prop" "z10_fr_E1,
1975 z10_fwd_A1,
1976 z10_super_E1,
1977 z10_super_E1,
1978 z10_rec,
1979 z10_rec,
1980 z10_super,
1981 z10_super,
1982 *")])
1984 (define_peephole2
1985 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1986 (mem:QI (match_operand 1 "address_operand" "")))]
1987 "GET_CODE (operands[1]) == SYMBOL_REF
1988 && CONSTANT_POOL_ADDRESS_P (operands[1])
1989 && get_pool_mode (operands[1]) == QImode
1990 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1991 [(set (match_dup 0) (match_dup 2))]
1992 "operands[2] = get_pool_constant (operands[1]);")
1994 ;
1995 ; movstrictqi instruction pattern(s).
1996 ;
1998 (define_insn "*movstrictqi"
1999 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2000 (match_operand:QI 1 "memory_operand" "R,T"))]
2001 ""
2002 "@
2003 ic\t%0,%1
2004 icy\t%0,%1"
2005 [(set_attr "op_type" "RX,RXY")
2006 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2008 ;
2009 ; movstricthi instruction pattern(s).
2010 ;
2012 (define_insn "*movstricthi"
2013 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2014 (match_operand:HI 1 "memory_operand" "Q,S"))
2015 (clobber (reg:CC CC_REGNUM))]
2016 ""
2017 "@
2018 icm\t%0,3,%S1
2019 icmy\t%0,3,%S1"
2020 [(set_attr "op_type" "RS,RSY")
2021 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2023 ;
2024 ; movstrictsi instruction pattern(s).
2025 ;
2027 (define_insn "movstrictsi"
2028 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2029 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2030 "TARGET_ZARCH"
2031 "@
2032 lr\t%0,%1
2033 l\t%0,%1
2034 ly\t%0,%1
2035 ear\t%0,%1"
2036 [(set_attr "op_type" "RR,RX,RXY,RRE")
2037 (set_attr "type" "lr,load,load,*")
2038 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2040 ;
2041 ; mov(tf|td) instruction pattern(s).
2042 ;
2044 (define_expand "mov<mode>"
2045 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2046 (match_operand:TD_TF 1 "general_operand" ""))]
2047 ""
2048 "")
2050 (define_insn "*mov<mode>_64"
2051 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2052 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2053 "TARGET_ZARCH"
2054 "@
2055 lzxr\t%0
2056 lxr\t%0,%1
2057 #
2058 #
2059 lmg\t%0,%N0,%S1
2060 stmg\t%1,%N1,%S0
2061 #
2062 #"
2063 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2064 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2065 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2067 (define_insn "*mov<mode>_31"
2068 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2069 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2070 "!TARGET_ZARCH"
2071 "@
2072 lzxr\t%0
2073 lxr\t%0,%1
2074 #
2075 #"
2076 [(set_attr "op_type" "RRE,RRE,*,*")
2077 (set_attr "type" "fsimptf,fsimptf,*,*")
2078 (set_attr "cpu_facility" "z196,*,*,*")])
2080 ; TFmode in GPRs splitters
2082 (define_split
2083 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2084 (match_operand:TD_TF 1 "general_operand" ""))]
2085 "TARGET_ZARCH && reload_completed
2086 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2087 [(set (match_dup 2) (match_dup 4))
2088 (set (match_dup 3) (match_dup 5))]
2089 {
2090 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2091 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2092 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2093 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2094 })
2096 (define_split
2097 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2098 (match_operand:TD_TF 1 "general_operand" ""))]
2099 "TARGET_ZARCH && reload_completed
2100 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2101 [(set (match_dup 2) (match_dup 4))
2102 (set (match_dup 3) (match_dup 5))]
2103 {
2104 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2105 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2106 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2107 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2108 })
2110 (define_split
2111 [(set (match_operand:TD_TF 0 "register_operand" "")
2112 (match_operand:TD_TF 1 "memory_operand" ""))]
2113 "TARGET_ZARCH && reload_completed
2114 && !FP_REG_P (operands[0])
2115 && !s_operand (operands[1], VOIDmode)"
2116 [(set (match_dup 0) (match_dup 1))]
2117 {
2118 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2119 addr = gen_lowpart (Pmode, addr);
2120 s390_load_address (addr, XEXP (operands[1], 0));
2121 operands[1] = replace_equiv_address (operands[1], addr);
2122 })
2124 ; TFmode in BFPs splitters
2126 (define_split
2127 [(set (match_operand:TD_TF 0 "register_operand" "")
2128 (match_operand:TD_TF 1 "memory_operand" ""))]
2129 "reload_completed && offsettable_memref_p (operands[1])
2130 && FP_REG_P (operands[0])"
2131 [(set (match_dup 2) (match_dup 4))
2132 (set (match_dup 3) (match_dup 5))]
2133 {
2134 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2135 <MODE>mode, 0);
2136 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2137 <MODE>mode, 8);
2138 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2139 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2140 })
2142 (define_split
2143 [(set (match_operand:TD_TF 0 "memory_operand" "")
2144 (match_operand:TD_TF 1 "register_operand" ""))]
2145 "reload_completed && offsettable_memref_p (operands[0])
2146 && FP_REG_P (operands[1])"
2147 [(set (match_dup 2) (match_dup 4))
2148 (set (match_dup 3) (match_dup 5))]
2149 {
2150 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2151 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2152 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2153 <MODE>mode, 0);
2154 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2155 <MODE>mode, 8);
2156 })
2158 ;
2159 ; mov(df|dd) instruction pattern(s).
2160 ;
2162 (define_expand "mov<mode>"
2163 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2164 (match_operand:DD_DF 1 "general_operand" ""))]
2165 ""
2166 "")
2168 (define_insn "*mov<mode>_64dfp"
2169 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2170 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2171 (match_operand:DD_DF 1 "general_operand"
2172 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2173 "TARGET_DFP"
2174 "@
2175 lzdr\t%0
2176 ldr\t%0,%1
2177 ldgr\t%0,%1
2178 lgdr\t%0,%1
2179 ld\t%0,%1
2180 ldy\t%0,%1
2181 std\t%1,%0
2182 stdy\t%1,%0
2183 lghi\t%0,0
2184 lgr\t%0,%1
2185 lg\t%0,%1
2186 stg\t%1,%0"
2187 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2188 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2189 fstoredf,fstoredf,*,lr,load,store")
2190 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2191 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2193 (define_insn "*mov<mode>_64"
2194 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2195 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2196 "TARGET_ZARCH"
2197 "@
2198 lzdr\t%0
2199 ldr\t%0,%1
2200 ld\t%0,%1
2201 ldy\t%0,%1
2202 std\t%1,%0
2203 stdy\t%1,%0
2204 lghi\t%0,0
2205 lgr\t%0,%1
2206 lg\t%0,%1
2207 stg\t%1,%0"
2208 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2209 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2210 fstore<mode>,fstore<mode>,*,lr,load,store")
2211 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2212 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2214 (define_insn "*mov<mode>_31"
2215 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2216 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2217 (match_operand:DD_DF 1 "general_operand"
2218 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2219 "!TARGET_ZARCH"
2220 "@
2221 lzdr\t%0
2222 ldr\t%0,%1
2223 ld\t%0,%1
2224 ldy\t%0,%1
2225 std\t%1,%0
2226 stdy\t%1,%0
2227 lm\t%0,%N0,%S1
2228 lmy\t%0,%N0,%S1
2229 stm\t%1,%N1,%S0
2230 stmy\t%1,%N1,%S0
2231 #
2232 #"
2233 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2234 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2235 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2236 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2238 (define_split
2239 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2240 (match_operand:DD_DF 1 "general_operand" ""))]
2241 "!TARGET_ZARCH && reload_completed
2242 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2243 [(set (match_dup 2) (match_dup 4))
2244 (set (match_dup 3) (match_dup 5))]
2245 {
2246 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2247 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2248 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2249 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2250 })
2252 (define_split
2253 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2254 (match_operand:DD_DF 1 "general_operand" ""))]
2255 "!TARGET_ZARCH && reload_completed
2256 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2257 [(set (match_dup 2) (match_dup 4))
2258 (set (match_dup 3) (match_dup 5))]
2259 {
2260 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2261 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2262 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2263 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2264 })
2266 (define_split
2267 [(set (match_operand:DD_DF 0 "register_operand" "")
2268 (match_operand:DD_DF 1 "memory_operand" ""))]
2269 "!TARGET_ZARCH && reload_completed
2270 && !FP_REG_P (operands[0])
2271 && !s_operand (operands[1], VOIDmode)"
2272 [(set (match_dup 0) (match_dup 1))]
2273 {
2274 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2275 s390_load_address (addr, XEXP (operands[1], 0));
2276 operands[1] = replace_equiv_address (operands[1], addr);
2277 })
2279 ;
2280 ; mov(sf|sd) instruction pattern(s).
2281 ;
2283 (define_insn "mov<mode>"
2284 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2285 "=f,f,f,f,R,T,d,d,d,d,R,T")
2286 (match_operand:SD_SF 1 "general_operand"
2287 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2288 ""
2289 "@
2290 lzer\t%0
2291 ler\t%0,%1
2292 le\t%0,%1
2293 ley\t%0,%1
2294 ste\t%1,%0
2295 stey\t%1,%0
2296 lhi\t%0,0
2297 lr\t%0,%1
2298 l\t%0,%1
2299 ly\t%0,%1
2300 st\t%1,%0
2301 sty\t%1,%0"
2302 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2303 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2304 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2305 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2306 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2308 ;
2309 ; movcc instruction pattern
2310 ;
2312 (define_insn "movcc"
2313 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2314 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2315 ""
2316 "@
2317 lr\t%0,%1
2318 tmh\t%1,12288
2319 ipm\t%0
2320 l\t%0,%1
2321 ly\t%0,%1
2322 st\t%1,%0
2323 sty\t%1,%0"
2324 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2325 (set_attr "type" "lr,*,*,load,load,store,store")
2326 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2327 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2329 ;
2330 ; Block move (MVC) patterns.
2331 ;
2333 (define_insn "*mvc"
2334 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2335 (match_operand:BLK 1 "memory_operand" "Q"))
2336 (use (match_operand 2 "const_int_operand" "n"))]
2337 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2338 "mvc\t%O0(%2,%R0),%S1"
2339 [(set_attr "op_type" "SS")])
2341 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2342 ; order to have it implemented with mvc.
2344 (define_split
2345 [(set (match_operand:QI 0 "memory_operand" "")
2346 (match_operand:QI 1 "memory_operand" ""))]
2347 "reload_completed"
2348 [(parallel
2349 [(set (match_dup 0) (match_dup 1))
2350 (use (const_int 1))])]
2351 {
2352 operands[0] = adjust_address (operands[0], BLKmode, 0);
2353 operands[1] = adjust_address (operands[1], BLKmode, 0);
2354 })
2357 (define_peephole2
2358 [(parallel
2359 [(set (match_operand:BLK 0 "memory_operand" "")
2360 (match_operand:BLK 1 "memory_operand" ""))
2361 (use (match_operand 2 "const_int_operand" ""))])
2362 (parallel
2363 [(set (match_operand:BLK 3 "memory_operand" "")
2364 (match_operand:BLK 4 "memory_operand" ""))
2365 (use (match_operand 5 "const_int_operand" ""))])]
2366 "s390_offset_p (operands[0], operands[3], operands[2])
2367 && s390_offset_p (operands[1], operands[4], operands[2])
2368 && !s390_overlap_p (operands[0], operands[1],
2369 INTVAL (operands[2]) + INTVAL (operands[5]))
2370 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2371 [(parallel
2372 [(set (match_dup 6) (match_dup 7))
2373 (use (match_dup 8))])]
2374 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2375 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2376 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2379 ;
2380 ; load_multiple pattern(s).
2381 ;
2382 ; ??? Due to reload problems with replacing registers inside match_parallel
2383 ; we currently support load_multiple/store_multiple only after reload.
2384 ;
2386 (define_expand "load_multiple"
2387 [(match_par_dup 3 [(set (match_operand 0 "" "")
2388 (match_operand 1 "" ""))
2389 (use (match_operand 2 "" ""))])]
2390 "reload_completed"
2391 {
2392 enum machine_mode mode;
2393 int regno;
2394 int count;
2395 rtx from;
2396 int i, off;
2398 /* Support only loading a constant number of fixed-point registers from
2399 memory and only bother with this if more than two */
2400 if (GET_CODE (operands[2]) != CONST_INT
2401 || INTVAL (operands[2]) < 2
2402 || INTVAL (operands[2]) > 16
2403 || GET_CODE (operands[1]) != MEM
2404 || GET_CODE (operands[0]) != REG
2405 || REGNO (operands[0]) >= 16)
2406 FAIL;
2408 count = INTVAL (operands[2]);
2409 regno = REGNO (operands[0]);
2410 mode = GET_MODE (operands[0]);
2411 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2412 FAIL;
2414 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2415 if (!can_create_pseudo_p ())
2416 {
2417 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2418 {
2419 from = XEXP (operands[1], 0);
2420 off = 0;
2421 }
2422 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2423 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2424 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2425 {
2426 from = XEXP (XEXP (operands[1], 0), 0);
2427 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2428 }
2429 else
2430 FAIL;
2431 }
2432 else
2433 {
2434 from = force_reg (Pmode, XEXP (operands[1], 0));
2435 off = 0;
2436 }
2438 for (i = 0; i < count; i++)
2439 XVECEXP (operands[3], 0, i)
2440 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2441 change_address (operands[1], mode,
2442 plus_constant (Pmode, from,
2443 off + i * GET_MODE_SIZE (mode))));
2444 })
2446 (define_insn "*load_multiple_di"
2447 [(match_parallel 0 "load_multiple_operation"
2448 [(set (match_operand:DI 1 "register_operand" "=r")
2449 (match_operand:DI 2 "s_operand" "QS"))])]
2450 "reload_completed && TARGET_ZARCH"
2451 {
2452 int words = XVECLEN (operands[0], 0);
2453 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2454 return "lmg\t%1,%0,%S2";
2455 }
2456 [(set_attr "op_type" "RSY")
2457 (set_attr "type" "lm")])
2459 (define_insn "*load_multiple_si"
2460 [(match_parallel 0 "load_multiple_operation"
2461 [(set (match_operand:SI 1 "register_operand" "=r,r")
2462 (match_operand:SI 2 "s_operand" "Q,S"))])]
2463 "reload_completed"
2464 {
2465 int words = XVECLEN (operands[0], 0);
2466 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2467 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2468 }
2469 [(set_attr "op_type" "RS,RSY")
2470 (set_attr "type" "lm")])
2472 ;
2473 ; store multiple pattern(s).
2474 ;
2476 (define_expand "store_multiple"
2477 [(match_par_dup 3 [(set (match_operand 0 "" "")
2478 (match_operand 1 "" ""))
2479 (use (match_operand 2 "" ""))])]
2480 "reload_completed"
2481 {
2482 enum machine_mode mode;
2483 int regno;
2484 int count;
2485 rtx to;
2486 int i, off;
2488 /* Support only storing a constant number of fixed-point registers to
2489 memory and only bother with this if more than two. */
2490 if (GET_CODE (operands[2]) != CONST_INT
2491 || INTVAL (operands[2]) < 2
2492 || INTVAL (operands[2]) > 16
2493 || GET_CODE (operands[0]) != MEM
2494 || GET_CODE (operands[1]) != REG
2495 || REGNO (operands[1]) >= 16)
2496 FAIL;
2498 count = INTVAL (operands[2]);
2499 regno = REGNO (operands[1]);
2500 mode = GET_MODE (operands[1]);
2501 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2502 FAIL;
2504 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2506 if (!can_create_pseudo_p ())
2507 {
2508 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2509 {
2510 to = XEXP (operands[0], 0);
2511 off = 0;
2512 }
2513 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2514 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2515 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2516 {
2517 to = XEXP (XEXP (operands[0], 0), 0);
2518 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2519 }
2520 else
2521 FAIL;
2522 }
2523 else
2524 {
2525 to = force_reg (Pmode, XEXP (operands[0], 0));
2526 off = 0;
2527 }
2529 for (i = 0; i < count; i++)
2530 XVECEXP (operands[3], 0, i)
2531 = gen_rtx_SET (VOIDmode,
2532 change_address (operands[0], mode,
2533 plus_constant (Pmode, to,
2534 off + i * GET_MODE_SIZE (mode))),
2535 gen_rtx_REG (mode, regno + i));
2536 })
2538 (define_insn "*store_multiple_di"
2539 [(match_parallel 0 "store_multiple_operation"
2540 [(set (match_operand:DI 1 "s_operand" "=QS")
2541 (match_operand:DI 2 "register_operand" "r"))])]
2542 "reload_completed && TARGET_ZARCH"
2543 {
2544 int words = XVECLEN (operands[0], 0);
2545 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2546 return "stmg\t%2,%0,%S1";
2547 }
2548 [(set_attr "op_type" "RSY")
2549 (set_attr "type" "stm")])
2552 (define_insn "*store_multiple_si"
2553 [(match_parallel 0 "store_multiple_operation"
2554 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2555 (match_operand:SI 2 "register_operand" "r,r"))])]
2556 "reload_completed"
2557 {
2558 int words = XVECLEN (operands[0], 0);
2559 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2560 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2561 }
2562 [(set_attr "op_type" "RS,RSY")
2563 (set_attr "type" "stm")])
2565 ;;
2566 ;; String instructions.
2567 ;;
2569 (define_insn "*execute_rl"
2570 [(match_parallel 0 "execute_operation"
2571 [(unspec [(match_operand 1 "register_operand" "a")
2572 (match_operand 2 "" "")
2573 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2574 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2575 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2576 "exrl\t%1,%3"
2577 [(set_attr "op_type" "RIL")
2578 (set_attr "type" "cs")])
2580 (define_insn "*execute"
2581 [(match_parallel 0 "execute_operation"
2582 [(unspec [(match_operand 1 "register_operand" "a")
2583 (match_operand:BLK 2 "memory_operand" "R")
2584 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2585 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2586 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2587 "ex\t%1,%2"
2588 [(set_attr "op_type" "RX")
2589 (set_attr "type" "cs")])
2592 ;
2593 ; strlenM instruction pattern(s).
2594 ;
2596 (define_expand "strlen<mode>"
2597 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2598 (parallel
2599 [(set (match_dup 4)
2600 (unspec:P [(const_int 0)
2601 (match_operand:BLK 1 "memory_operand" "")
2602 (reg:SI 0)
2603 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2604 (clobber (scratch:P))
2605 (clobber (reg:CC CC_REGNUM))])
2606 (parallel
2607 [(set (match_operand:P 0 "register_operand" "")
2608 (minus:P (match_dup 4) (match_dup 5)))
2609 (clobber (reg:CC CC_REGNUM))])]
2610 ""
2611 {
2612 operands[4] = gen_reg_rtx (Pmode);
2613 operands[5] = gen_reg_rtx (Pmode);
2614 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2615 operands[1] = replace_equiv_address (operands[1], operands[5]);
2616 })
2618 (define_insn "*strlen<mode>"
2619 [(set (match_operand:P 0 "register_operand" "=a")
2620 (unspec:P [(match_operand:P 2 "general_operand" "0")
2621 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2622 (reg:SI 0)
2623 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2624 (clobber (match_scratch:P 1 "=a"))
2625 (clobber (reg:CC CC_REGNUM))]
2626 ""
2627 "srst\t%0,%1\;jo\t.-4"
2628 [(set_attr "length" "8")
2629 (set_attr "type" "vs")])
2631 ;
2632 ; cmpstrM instruction pattern(s).
2633 ;
2635 (define_expand "cmpstrsi"
2636 [(set (reg:SI 0) (const_int 0))
2637 (parallel
2638 [(clobber (match_operand 3 "" ""))
2639 (clobber (match_dup 4))
2640 (set (reg:CCU CC_REGNUM)
2641 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2642 (match_operand:BLK 2 "memory_operand" "")))
2643 (use (reg:SI 0))])
2644 (parallel
2645 [(set (match_operand:SI 0 "register_operand" "=d")
2646 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2647 (clobber (reg:CC CC_REGNUM))])]
2648 ""
2649 {
2650 /* As the result of CMPINT is inverted compared to what we need,
2651 we have to swap the operands. */
2652 rtx op1 = operands[2];
2653 rtx op2 = operands[1];
2654 rtx addr1 = gen_reg_rtx (Pmode);
2655 rtx addr2 = gen_reg_rtx (Pmode);
2657 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2658 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2659 operands[1] = replace_equiv_address_nv (op1, addr1);
2660 operands[2] = replace_equiv_address_nv (op2, addr2);
2661 operands[3] = addr1;
2662 operands[4] = addr2;
2663 })
2665 (define_insn "*cmpstr<mode>"
2666 [(clobber (match_operand:P 0 "register_operand" "=d"))
2667 (clobber (match_operand:P 1 "register_operand" "=d"))
2668 (set (reg:CCU CC_REGNUM)
2669 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2670 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2671 (use (reg:SI 0))]
2672 ""
2673 "clst\t%0,%1\;jo\t.-4"
2674 [(set_attr "length" "8")
2675 (set_attr "type" "vs")])
2677 ;
2678 ; movstr instruction pattern.
2679 ;
2681 (define_expand "movstr"
2682 [(set (reg:SI 0) (const_int 0))
2683 (parallel
2684 [(clobber (match_dup 3))
2685 (set (match_operand:BLK 1 "memory_operand" "")
2686 (match_operand:BLK 2 "memory_operand" ""))
2687 (set (match_operand 0 "register_operand" "")
2688 (unspec [(match_dup 1)
2689 (match_dup 2)
2690 (reg:SI 0)] UNSPEC_MVST))
2691 (clobber (reg:CC CC_REGNUM))])]
2692 ""
2693 {
2694 rtx addr1 = gen_reg_rtx (Pmode);
2695 rtx addr2 = gen_reg_rtx (Pmode);
2697 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2698 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2699 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2700 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2701 operands[3] = addr2;
2702 })
2704 (define_insn "*movstr"
2705 [(clobber (match_operand:P 2 "register_operand" "=d"))
2706 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2707 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2708 (set (match_operand:P 0 "register_operand" "=d")
2709 (unspec [(mem:BLK (match_dup 1))
2710 (mem:BLK (match_dup 3))
2711 (reg:SI 0)] UNSPEC_MVST))
2712 (clobber (reg:CC CC_REGNUM))]
2713 ""
2714 "mvst\t%1,%2\;jo\t.-4"
2715 [(set_attr "length" "8")
2716 (set_attr "type" "vs")])
2719 ;
2720 ; movmemM instruction pattern(s).
2721 ;
2723 (define_expand "movmem<mode>"
2724 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2725 (match_operand:BLK 1 "memory_operand" "")) ; source
2726 (use (match_operand:GPR 2 "general_operand" "")) ; count
2727 (match_operand 3 "" "")]
2728 ""
2729 {
2730 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2731 DONE;
2732 else
2733 FAIL;
2734 })
2736 ; Move a block that is up to 256 bytes in length.
2737 ; The block length is taken as (operands[2] % 256) + 1.
2739 (define_expand "movmem_short"
2740 [(parallel
2741 [(set (match_operand:BLK 0 "memory_operand" "")
2742 (match_operand:BLK 1 "memory_operand" ""))
2743 (use (match_operand 2 "nonmemory_operand" ""))
2744 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2745 (clobber (match_dup 3))])]
2746 ""
2747 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2749 (define_insn "*movmem_short"
2750 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2751 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2752 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2753 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2754 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2755 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2756 "#"
2757 [(set_attr "type" "cs")
2758 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2760 (define_split
2761 [(set (match_operand:BLK 0 "memory_operand" "")
2762 (match_operand:BLK 1 "memory_operand" ""))
2763 (use (match_operand 2 "const_int_operand" ""))
2764 (use (match_operand 3 "immediate_operand" ""))
2765 (clobber (scratch))]
2766 "reload_completed"
2767 [(parallel
2768 [(set (match_dup 0) (match_dup 1))
2769 (use (match_dup 2))])]
2770 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2772 (define_split
2773 [(set (match_operand:BLK 0 "memory_operand" "")
2774 (match_operand:BLK 1 "memory_operand" ""))
2775 (use (match_operand 2 "register_operand" ""))
2776 (use (match_operand 3 "memory_operand" ""))
2777 (clobber (scratch))]
2778 "reload_completed"
2779 [(parallel
2780 [(unspec [(match_dup 2) (match_dup 3)
2781 (const_int 0)] UNSPEC_EXECUTE)
2782 (set (match_dup 0) (match_dup 1))
2783 (use (const_int 1))])]
2784 "")
2786 (define_split
2787 [(set (match_operand:BLK 0 "memory_operand" "")
2788 (match_operand:BLK 1 "memory_operand" ""))
2789 (use (match_operand 2 "register_operand" ""))
2790 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2791 (clobber (scratch))]
2792 "TARGET_Z10 && reload_completed"
2793 [(parallel
2794 [(unspec [(match_dup 2) (const_int 0)
2795 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2796 (set (match_dup 0) (match_dup 1))
2797 (use (const_int 1))])]
2798 "operands[3] = gen_label_rtx ();")
2800 (define_split
2801 [(set (match_operand:BLK 0 "memory_operand" "")
2802 (match_operand:BLK 1 "memory_operand" ""))
2803 (use (match_operand 2 "register_operand" ""))
2804 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2805 (clobber (match_operand 3 "register_operand" ""))]
2806 "reload_completed && TARGET_CPU_ZARCH"
2807 [(set (match_dup 3) (label_ref (match_dup 4)))
2808 (parallel
2809 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2810 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2811 (set (match_dup 0) (match_dup 1))
2812 (use (const_int 1))])]
2813 "operands[4] = gen_label_rtx ();")
2815 ; Move a block of arbitrary length.
2817 (define_expand "movmem_long"
2818 [(parallel
2819 [(clobber (match_dup 2))
2820 (clobber (match_dup 3))
2821 (set (match_operand:BLK 0 "memory_operand" "")
2822 (match_operand:BLK 1 "memory_operand" ""))
2823 (use (match_operand 2 "general_operand" ""))
2824 (use (match_dup 3))
2825 (clobber (reg:CC CC_REGNUM))])]
2826 ""
2827 {
2828 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2829 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2830 rtx reg0 = gen_reg_rtx (dreg_mode);
2831 rtx reg1 = gen_reg_rtx (dreg_mode);
2832 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2833 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2834 rtx len0 = gen_lowpart (Pmode, reg0);
2835 rtx len1 = gen_lowpart (Pmode, reg1);
2837 emit_clobber (reg0);
2838 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2839 emit_move_insn (len0, operands[2]);
2841 emit_clobber (reg1);
2842 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2843 emit_move_insn (len1, operands[2]);
2845 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2846 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2847 operands[2] = reg0;
2848 operands[3] = reg1;
2849 })
2851 (define_insn "*movmem_long"
2852 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2853 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2854 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2855 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2856 (use (match_dup 2))
2857 (use (match_dup 3))
2858 (clobber (reg:CC CC_REGNUM))]
2859 "TARGET_64BIT || !TARGET_ZARCH"
2860 "mvcle\t%0,%1,0\;jo\t.-4"
2861 [(set_attr "length" "8")
2862 (set_attr "type" "vs")])
2864 (define_insn "*movmem_long_31z"
2865 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2866 (clobber (match_operand:TI 1 "register_operand" "=d"))
2867 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2868 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2869 (use (match_dup 2))
2870 (use (match_dup 3))
2871 (clobber (reg:CC CC_REGNUM))]
2872 "!TARGET_64BIT && TARGET_ZARCH"
2873 "mvcle\t%0,%1,0\;jo\t.-4"
2874 [(set_attr "length" "8")
2875 (set_attr "type" "vs")])
2878 ;
2879 ; Test data class.
2880 ;
2882 (define_expand "signbit<mode>2"
2883 [(set (reg:CCZ CC_REGNUM)
2884 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2885 (match_dup 2)]
2886 UNSPEC_TDC_INSN))
2887 (set (match_operand:SI 0 "register_operand" "=d")
2888 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2889 "TARGET_HARD_FLOAT"
2890 {
2891 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2892 })
2894 (define_expand "isinf<mode>2"
2895 [(set (reg:CCZ CC_REGNUM)
2896 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2897 (match_dup 2)]
2898 UNSPEC_TDC_INSN))
2899 (set (match_operand:SI 0 "register_operand" "=d")
2900 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2901 "TARGET_HARD_FLOAT"
2902 {
2903 operands[2] = GEN_INT (S390_TDC_INFINITY);
2904 })
2906 (define_insn_and_split "*cc_to_int"
2907 [(set (match_operand:SI 0 "register_operand" "=d")
2908 (unspec:SI [(match_operand 1 "register_operand" "0")]
2909 UNSPEC_CC_TO_INT))]
2910 "operands != NULL"
2911 "#"
2912 "reload_completed"
2913 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2915 ; This insn is used to generate all variants of the Test Data Class
2916 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2917 ; is the register to be tested and the second one is the bit mask
2918 ; specifying the required test(s).
2919 ;
2920 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2921 (define_insn "*TDC_insn_<mode>"
2922 [(set (reg:CCZ CC_REGNUM)
2923 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2924 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2925 "TARGET_HARD_FLOAT"
2926 "t<_d>c<xde><bt>\t%0,%1"
2927 [(set_attr "op_type" "RXE")
2928 (set_attr "type" "fsimp<mode>")])
2932 ;
2933 ; setmemM instruction pattern(s).
2934 ;
2936 (define_expand "setmem<mode>"
2937 [(set (match_operand:BLK 0 "memory_operand" "")
2938 (match_operand:QI 2 "general_operand" ""))
2939 (use (match_operand:GPR 1 "general_operand" ""))
2940 (match_operand 3 "" "")]
2941 ""
2942 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2944 ; Clear a block that is up to 256 bytes in length.
2945 ; The block length is taken as (operands[1] % 256) + 1.
2947 (define_expand "clrmem_short"
2948 [(parallel
2949 [(set (match_operand:BLK 0 "memory_operand" "")
2950 (const_int 0))
2951 (use (match_operand 1 "nonmemory_operand" ""))
2952 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2953 (clobber (match_dup 2))
2954 (clobber (reg:CC CC_REGNUM))])]
2955 ""
2956 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2958 (define_insn "*clrmem_short"
2959 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2960 (const_int 0))
2961 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2962 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2963 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2964 (clobber (reg:CC CC_REGNUM))]
2965 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2966 "#"
2967 [(set_attr "type" "cs")
2968 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2970 (define_split
2971 [(set (match_operand:BLK 0 "memory_operand" "")
2972 (const_int 0))
2973 (use (match_operand 1 "const_int_operand" ""))
2974 (use (match_operand 2 "immediate_operand" ""))
2975 (clobber (scratch))
2976 (clobber (reg:CC CC_REGNUM))]
2977 "reload_completed"
2978 [(parallel
2979 [(set (match_dup 0) (const_int 0))
2980 (use (match_dup 1))
2981 (clobber (reg:CC CC_REGNUM))])]
2982 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2984 (define_split
2985 [(set (match_operand:BLK 0 "memory_operand" "")
2986 (const_int 0))
2987 (use (match_operand 1 "register_operand" ""))
2988 (use (match_operand 2 "memory_operand" ""))
2989 (clobber (scratch))
2990 (clobber (reg:CC CC_REGNUM))]
2991 "reload_completed"
2992 [(parallel
2993 [(unspec [(match_dup 1) (match_dup 2)
2994 (const_int 0)] UNSPEC_EXECUTE)
2995 (set (match_dup 0) (const_int 0))
2996 (use (const_int 1))
2997 (clobber (reg:CC CC_REGNUM))])]
2998 "")
3000 (define_split
3001 [(set (match_operand:BLK 0 "memory_operand" "")
3002 (const_int 0))
3003 (use (match_operand 1 "register_operand" ""))
3004 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3005 (clobber (scratch))
3006 (clobber (reg:CC CC_REGNUM))]
3007 "TARGET_Z10 && reload_completed"
3008 [(parallel
3009 [(unspec [(match_dup 1) (const_int 0)
3010 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3011 (set (match_dup 0) (const_int 0))
3012 (use (const_int 1))
3013 (clobber (reg:CC CC_REGNUM))])]
3014 "operands[3] = gen_label_rtx ();")
3016 (define_split
3017 [(set (match_operand:BLK 0 "memory_operand" "")
3018 (const_int 0))
3019 (use (match_operand 1 "register_operand" ""))
3020 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3021 (clobber (match_operand 2 "register_operand" ""))
3022 (clobber (reg:CC CC_REGNUM))]
3023 "reload_completed && TARGET_CPU_ZARCH"
3024 [(set (match_dup 2) (label_ref (match_dup 3)))
3025 (parallel
3026 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3027 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3028 (set (match_dup 0) (const_int 0))
3029 (use (const_int 1))
3030 (clobber (reg:CC CC_REGNUM))])]
3031 "operands[3] = gen_label_rtx ();")
3033 ; Initialize a block of arbitrary length with (operands[2] % 256).
3035 (define_expand "setmem_long"
3036 [(parallel
3037 [(clobber (match_dup 1))
3038 (set (match_operand:BLK 0 "memory_operand" "")
3039 (match_operand 2 "shift_count_or_setmem_operand" ""))
3040 (use (match_operand 1 "general_operand" ""))
3041 (use (match_dup 3))
3042 (clobber (reg:CC CC_REGNUM))])]
3043 ""
3044 {
3045 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3046 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3047 rtx reg0 = gen_reg_rtx (dreg_mode);
3048 rtx reg1 = gen_reg_rtx (dreg_mode);
3049 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3050 rtx len0 = gen_lowpart (Pmode, reg0);
3052 emit_clobber (reg0);
3053 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3054 emit_move_insn (len0, operands[1]);
3056 emit_move_insn (reg1, const0_rtx);
3058 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3059 operands[1] = reg0;
3060 operands[3] = reg1;
3061 })
3063 (define_insn "*setmem_long"
3064 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3065 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3066 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3067 (use (match_dup 3))
3068 (use (match_operand:<DBL> 1 "register_operand" "d"))
3069 (clobber (reg:CC CC_REGNUM))]
3070 "TARGET_64BIT || !TARGET_ZARCH"
3071 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3072 [(set_attr "length" "8")
3073 (set_attr "type" "vs")])
3075 (define_insn "*setmem_long_and"
3076 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3077 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3078 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3079 (match_operand 4 "const_int_operand" "n")))
3080 (use (match_dup 3))
3081 (use (match_operand:<DBL> 1 "register_operand" "d"))
3082 (clobber (reg:CC CC_REGNUM))]
3083 "(TARGET_64BIT || !TARGET_ZARCH) &&
3084 (INTVAL (operands[4]) & 255) == 255"
3085 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3086 [(set_attr "length" "8")
3087 (set_attr "type" "vs")])
3089 (define_insn "*setmem_long_31z"
3090 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3091 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3092 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3093 (use (match_dup 3))
3094 (use (match_operand:TI 1 "register_operand" "d"))
3095 (clobber (reg:CC CC_REGNUM))]
3096 "!TARGET_64BIT && TARGET_ZARCH"
3097 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3098 [(set_attr "length" "8")
3099 (set_attr "type" "vs")])
3101 ;
3102 ; cmpmemM instruction pattern(s).
3103 ;
3105 (define_expand "cmpmemsi"
3106 [(set (match_operand:SI 0 "register_operand" "")
3107 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3108 (match_operand:BLK 2 "memory_operand" "") ) )
3109 (use (match_operand:SI 3 "general_operand" ""))
3110 (use (match_operand:SI 4 "" ""))]
3111 ""
3112 {
3113 if (s390_expand_cmpmem (operands[0], operands[1],
3114 operands[2], operands[3]))
3115 DONE;
3116 else
3117 FAIL;
3118 })
3120 ; Compare a block that is up to 256 bytes in length.
3121 ; The block length is taken as (operands[2] % 256) + 1.
3123 (define_expand "cmpmem_short"
3124 [(parallel
3125 [(set (reg:CCU CC_REGNUM)
3126 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3127 (match_operand:BLK 1 "memory_operand" "")))
3128 (use (match_operand 2 "nonmemory_operand" ""))
3129 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3130 (clobber (match_dup 3))])]
3131 ""
3132 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3134 (define_insn "*cmpmem_short"
3135 [(set (reg:CCU CC_REGNUM)
3136 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3137 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3138 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3139 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3140 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3141 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3142 "#"
3143 [(set_attr "type" "cs")
3144 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3146 (define_split
3147 [(set (reg:CCU CC_REGNUM)
3148 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3149 (match_operand:BLK 1 "memory_operand" "")))
3150 (use (match_operand 2 "const_int_operand" ""))
3151 (use (match_operand 3 "immediate_operand" ""))
3152 (clobber (scratch))]
3153 "reload_completed"
3154 [(parallel
3155 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3156 (use (match_dup 2))])]
3157 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3159 (define_split
3160 [(set (reg:CCU CC_REGNUM)
3161 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3162 (match_operand:BLK 1 "memory_operand" "")))
3163 (use (match_operand 2 "register_operand" ""))
3164 (use (match_operand 3 "memory_operand" ""))
3165 (clobber (scratch))]
3166 "reload_completed"
3167 [(parallel
3168 [(unspec [(match_dup 2) (match_dup 3)
3169 (const_int 0)] UNSPEC_EXECUTE)
3170 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3171 (use (const_int 1))])]
3172 "")
3174 (define_split
3175 [(set (reg:CCU CC_REGNUM)
3176 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3177 (match_operand:BLK 1 "memory_operand" "")))
3178 (use (match_operand 2 "register_operand" ""))
3179 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3180 (clobber (scratch))]
3181 "TARGET_Z10 && reload_completed"
3182 [(parallel
3183 [(unspec [(match_dup 2) (const_int 0)
3184 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3185 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3186 (use (const_int 1))])]
3187 "operands[4] = gen_label_rtx ();")
3189 (define_split
3190 [(set (reg:CCU CC_REGNUM)
3191 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3192 (match_operand:BLK 1 "memory_operand" "")))
3193 (use (match_operand 2 "register_operand" ""))
3194 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3195 (clobber (match_operand 3 "register_operand" ""))]
3196 "reload_completed && TARGET_CPU_ZARCH"
3197 [(set (match_dup 3) (label_ref (match_dup 4)))
3198 (parallel
3199 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3200 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3201 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3202 (use (const_int 1))])]
3203 "operands[4] = gen_label_rtx ();")
3205 ; Compare a block of arbitrary length.
3207 (define_expand "cmpmem_long"
3208 [(parallel
3209 [(clobber (match_dup 2))
3210 (clobber (match_dup 3))
3211 (set (reg:CCU CC_REGNUM)
3212 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3213 (match_operand:BLK 1 "memory_operand" "")))
3214 (use (match_operand 2 "general_operand" ""))
3215 (use (match_dup 3))])]
3216 ""
3217 {
3218 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3219 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3220 rtx reg0 = gen_reg_rtx (dreg_mode);
3221 rtx reg1 = gen_reg_rtx (dreg_mode);
3222 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3223 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3224 rtx len0 = gen_lowpart (Pmode, reg0);
3225 rtx len1 = gen_lowpart (Pmode, reg1);
3227 emit_clobber (reg0);
3228 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3229 emit_move_insn (len0, operands[2]);
3231 emit_clobber (reg1);
3232 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3233 emit_move_insn (len1, operands[2]);
3235 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3236 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3237 operands[2] = reg0;
3238 operands[3] = reg1;
3239 })
3241 (define_insn "*cmpmem_long"
3242 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3243 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3244 (set (reg:CCU CC_REGNUM)
3245 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3246 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3247 (use (match_dup 2))
3248 (use (match_dup 3))]
3249 "TARGET_64BIT || !TARGET_ZARCH"
3250 "clcle\t%0,%1,0\;jo\t.-4"
3251 [(set_attr "length" "8")
3252 (set_attr "type" "vs")])
3254 (define_insn "*cmpmem_long_31z"
3255 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3256 (clobber (match_operand:TI 1 "register_operand" "=d"))
3257 (set (reg:CCU CC_REGNUM)
3258 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3259 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3260 (use (match_dup 2))
3261 (use (match_dup 3))]
3262 "!TARGET_64BIT && TARGET_ZARCH"
3263 "clcle\t%0,%1,0\;jo\t.-4"
3264 [(set_attr "op_type" "NN")
3265 (set_attr "type" "vs")
3266 (set_attr "length" "8")])
3268 ; Convert CCUmode condition code to integer.
3269 ; Result is zero if EQ, positive if LTU, negative if GTU.
3271 (define_insn_and_split "cmpint"
3272 [(set (match_operand:SI 0 "register_operand" "=d")
3273 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3274 UNSPEC_STRCMPCC_TO_INT))
3275 (clobber (reg:CC CC_REGNUM))]
3276 ""
3277 "#"
3278 "reload_completed"
3279 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3280 (parallel
3281 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3282 (clobber (reg:CC CC_REGNUM))])])
3284 (define_insn_and_split "*cmpint_cc"
3285 [(set (reg CC_REGNUM)
3286 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3287 UNSPEC_STRCMPCC_TO_INT)
3288 (const_int 0)))
3289 (set (match_operand:SI 0 "register_operand" "=d")
3290 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3291 "s390_match_ccmode (insn, CCSmode)"
3292 "#"
3293 "&& reload_completed"
3294 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3295 (parallel
3296 [(set (match_dup 2) (match_dup 3))
3297 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3298 {
3299 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3300 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3301 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3302 })
3304 (define_insn_and_split "*cmpint_sign"
3305 [(set (match_operand:DI 0 "register_operand" "=d")
3306 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3307 UNSPEC_STRCMPCC_TO_INT)))
3308 (clobber (reg:CC CC_REGNUM))]
3309 "TARGET_ZARCH"
3310 "#"
3311 "&& reload_completed"
3312 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3313 (parallel
3314 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3315 (clobber (reg:CC CC_REGNUM))])])
3317 (define_insn_and_split "*cmpint_sign_cc"
3318 [(set (reg CC_REGNUM)
3319 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3320 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3321 UNSPEC_STRCMPCC_TO_INT) 0)
3322 (const_int 32)) (const_int 32))
3323 (const_int 0)))
3324 (set (match_operand:DI 0 "register_operand" "=d")
3325 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3326 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3327 "#"
3328 "&& reload_completed"
3329 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3330 (parallel
3331 [(set (match_dup 2) (match_dup 3))
3332 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3333 {
3334 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3335 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3336 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3337 })
3340 ;;
3341 ;;- Conversion instructions.
3342 ;;
3344 (define_insn "*sethighpartsi"
3345 [(set (match_operand:SI 0 "register_operand" "=d,d")
3346 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3347 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3348 (clobber (reg:CC CC_REGNUM))]
3349 ""
3350 "@
3351 icm\t%0,%2,%S1
3352 icmy\t%0,%2,%S1"
3353 [(set_attr "op_type" "RS,RSY")
3354 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3356 (define_insn "*sethighpartdi_64"
3357 [(set (match_operand:DI 0 "register_operand" "=d")
3358 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3359 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3360 (clobber (reg:CC CC_REGNUM))]
3361 "TARGET_ZARCH"
3362 "icmh\t%0,%2,%S1"
3363 [(set_attr "op_type" "RSY")
3364 (set_attr "z10prop" "z10_super")])
3366 (define_insn "*sethighpartdi_31"
3367 [(set (match_operand:DI 0 "register_operand" "=d,d")
3368 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3369 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3370 (clobber (reg:CC CC_REGNUM))]
3371 "!TARGET_ZARCH"
3372 "@
3373 icm\t%0,%2,%S1
3374 icmy\t%0,%2,%S1"
3375 [(set_attr "op_type" "RS,RSY")
3376 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3378 ;
3379 ; extv instruction patterns
3380 ;
3382 ; FIXME: This expander needs to be converted from DI to GPR as well
3383 ; after resolving some issues with it.
3385 (define_expand "extzv"
3386 [(parallel
3387 [(set (match_operand:DI 0 "register_operand" "=d")
3388 (zero_extract:DI
3389 (match_operand:DI 1 "register_operand" "d")
3390 (match_operand 2 "const_int_operand" "") ; size
3391 (match_operand 3 "const_int_operand" ""))) ; start
3392 (clobber (reg:CC CC_REGNUM))])]
3393 "TARGET_Z10"
3394 {
3395 /* Starting with zEC12 there is risbgn not clobbering CC. */
3396 if (TARGET_ZEC12)
3397 {
3398 emit_move_insn (operands[0],
3399 gen_rtx_ZERO_EXTRACT (DImode,
3400 operands[1],
3401 operands[2],
3402 operands[3]));
3403 DONE;
3404 }
3405 })
3407 (define_insn "*extzv<mode>_zEC12"
3408 [(set (match_operand:GPR 0 "register_operand" "=d")
3409 (zero_extract:GPR
3410 (match_operand:GPR 1 "register_operand" "d")
3411 (match_operand 2 "const_int_operand" "") ; size
3412 (match_operand 3 "const_int_operand" "")))] ; start]
3413 "TARGET_ZEC12"
3414 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3415 [(set_attr "op_type" "RIE")])
3417 (define_insn "*extzv<mode>_z10"
3418 [(set (match_operand:GPR 0 "register_operand" "=d")
3419 (zero_extract:GPR
3420 (match_operand:GPR 1 "register_operand" "d")
3421 (match_operand 2 "const_int_operand" "") ; size
3422 (match_operand 3 "const_int_operand" ""))) ; start
3423 (clobber (reg:CC CC_REGNUM))]
3424 "TARGET_Z10"
3425 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3426 [(set_attr "op_type" "RIE")
3427 (set_attr "z10prop" "z10_super_E1")])
3429 (define_insn_and_split "*pre_z10_extzv<mode>"
3430 [(set (match_operand:GPR 0 "register_operand" "=d")
3431 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3432 (match_operand 2 "nonzero_shift_count_operand" "")
3433 (const_int 0)))
3434 (clobber (reg:CC CC_REGNUM))]
3435 "!TARGET_Z10"
3436 "#"
3437 "&& reload_completed"
3438 [(parallel
3439 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3440 (clobber (reg:CC CC_REGNUM))])
3441 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3442 {
3443 int bitsize = INTVAL (operands[2]);
3444 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3445 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3447 operands[1] = adjust_address (operands[1], BLKmode, 0);
3448 set_mem_size (operands[1], size);
3449 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3450 operands[3] = GEN_INT (mask);
3451 })
3453 (define_insn_and_split "*pre_z10_extv<mode>"
3454 [(set (match_operand:GPR 0 "register_operand" "=d")
3455 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3456 (match_operand 2 "nonzero_shift_count_operand" "")
3457 (const_int 0)))
3458 (clobber (reg:CC CC_REGNUM))]
3459 ""
3460 "#"
3461 "&& reload_completed"
3462 [(parallel
3463 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3464 (clobber (reg:CC CC_REGNUM))])
3465 (parallel
3466 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3467 (clobber (reg:CC CC_REGNUM))])]
3468 {
3469 int bitsize = INTVAL (operands[2]);
3470 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3471 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3473 operands[1] = adjust_address (operands[1], BLKmode, 0);
3474 set_mem_size (operands[1], size);
3475 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3476 operands[3] = GEN_INT (mask);
3477 })
3479 ;
3480 ; insv instruction patterns
3481 ;
3483 (define_expand "insv"
3484 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3485 (match_operand 1 "const_int_operand" "")
3486 (match_operand 2 "const_int_operand" ""))
3487 (match_operand 3 "general_operand" ""))]
3488 ""
3489 {
3490 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3491 DONE;
3492 FAIL;
3493 })
3496 ; The normal RTL expansion will never generate a zero_extract where
3497 ; the location operand isn't word mode. However, we do this in the
3498 ; back-end when generating atomic operations. See s390_two_part_insv.
3499 (define_insn "*insv<mode>_zEC12"
3500 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3501 (match_operand 1 "const_int_operand" "I") ; size
3502 (match_operand 2 "const_int_operand" "I")) ; pos
3503 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3504 "TARGET_ZEC12
3505 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3506 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3507 [(set_attr "op_type" "RIE")])
3509 (define_insn "*insv<mode>_z10"
3510 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3511 (match_operand 1 "const_int_operand" "I") ; size
3512 (match_operand 2 "const_int_operand" "I")) ; pos
3513 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3514 (clobber (reg:CC CC_REGNUM))]
3515 "TARGET_Z10
3516 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3517 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3518 [(set_attr "op_type" "RIE")
3519 (set_attr "z10prop" "z10_super_E1")])
3521 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3522 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3523 (define_insn "*insv<mode>_zEC12_noshift"
3524 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3525 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3526 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3527 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3528 (match_operand:GPR 4 "const_int_operand" ""))))]
3529 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3530 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3531 [(set_attr "op_type" "RIE")])
3533 (define_insn "*insv<mode>_z10_noshift"
3534 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3535 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3536 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3537 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3538 (match_operand:GPR 4 "const_int_operand" ""))))
3539 (clobber (reg:CC CC_REGNUM))]
3540 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3541 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3542 [(set_attr "op_type" "RIE")
3543 (set_attr "z10prop" "z10_super_E1")])
3545 (define_insn "*r<noxa>sbg_<mode>_noshift"
3546 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3547 (IXOR:GPR
3548 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3549 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3550 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3551 (clobber (reg:CC CC_REGNUM))]
3552 "TARGET_Z10"
3553 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3554 [(set_attr "op_type" "RIE")])
3556 (define_insn "*r<noxa>sbg_di_rotl"
3557 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3558 (IXOR:DI
3559 (and:DI
3560 (rotate:DI
3561 (match_operand:DI 1 "nonimmediate_operand" "d")
3562 (match_operand:DI 3 "const_int_operand" ""))
3563 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3564 (match_operand:DI 4 "nonimmediate_operand" "0")))
3565 (clobber (reg:CC CC_REGNUM))]
3566 "TARGET_Z10"
3567 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3568 [(set_attr "op_type" "RIE")])
3570 (define_insn "*r<noxa>sbg_<mode>_srl"
3571 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3572 (IXOR:GPR
3573 (and:GPR
3574 (lshiftrt:GPR
3575 (match_operand:GPR 1 "nonimmediate_operand" "d")
3576 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3577 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3578 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3579 (clobber (reg:CC CC_REGNUM))]
3580 "TARGET_Z10
3581 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3582 INTVAL (operands[2]))"
3583 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3584 [(set_attr "op_type" "RIE")])
3586 (define_insn "*r<noxa>sbg_<mode>_sll"
3587 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3588 (IXOR:GPR
3589 (and:GPR
3590 (ashift:GPR
3591 (match_operand:GPR 1 "nonimmediate_operand" "d")
3592 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3593 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3594 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3595 (clobber (reg:CC CC_REGNUM))]
3596 "TARGET_Z10
3597 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3598 INTVAL (operands[2]))"
3599 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3600 [(set_attr "op_type" "RIE")])
3602 ;; These two are generated by combine for s.bf &= val.
3603 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3604 ;; shifts and ands, which results in some truly awful patterns
3605 ;; including subregs of operations. Rather unnecessisarily, IMO.
3606 ;; Instead of
3607 ;;
3608 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3609 ;; (const_int 24 [0x18])
3610 ;; (const_int 0 [0]))
3611 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3612 ;; (const_int 40 [0x28])) 4)
3613 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3614 ;;
3615 ;; we should instead generate
3616 ;;
3617 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3618 ;; (const_int 24 [0x18])
3619 ;; (const_int 0 [0]))
3620 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3621 ;; (const_int 40 [0x28]))
3622 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3623 ;;
3624 ;; by noticing that we can push down the outer paradoxical subreg
3625 ;; into the operation.
3627 (define_insn "*insv_rnsbg_noshift"
3628 [(set (zero_extract:DI
3629 (match_operand:DI 0 "nonimmediate_operand" "+d")
3630 (match_operand 1 "const_int_operand" "")
3631 (match_operand 2 "const_int_operand" ""))
3632 (and:DI
3633 (match_dup 0)
3634 (match_operand:DI 3 "nonimmediate_operand" "d")))
3635 (clobber (reg:CC CC_REGNUM))]
3636 "TARGET_Z10
3637 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3638 "rnsbg\t%0,%3,%2,63,0"
3639 [(set_attr "op_type" "RIE")])
3641 (define_insn "*insv_rnsbg_srl"
3642 [(set (zero_extract:DI
3643 (match_operand:DI 0 "nonimmediate_operand" "+d")
3644 (match_operand 1 "const_int_operand" "")
3645 (match_operand 2 "const_int_operand" ""))
3646 (and:DI
3647 (lshiftrt:DI
3648 (match_dup 0)
3649 (match_operand 3 "const_int_operand" ""))
3650 (match_operand:DI 4 "nonimmediate_operand" "d")))
3651 (clobber (reg:CC CC_REGNUM))]
3652 "TARGET_Z10
3653 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3654 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3655 [(set_attr "op_type" "RIE")])
3657 (define_insn "*insv<mode>_mem_reg"
3658 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3659 (match_operand 1 "const_int_operand" "n,n")
3660 (const_int 0))
3661 (match_operand:W 2 "register_operand" "d,d"))]
3662 "INTVAL (operands[1]) > 0
3663 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3664 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3665 {
3666 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3668 operands[1] = GEN_INT ((1ul << size) - 1);
3669 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3670 : "stcmy\t%2,%1,%S0";
3671 }
3672 [(set_attr "op_type" "RS,RSY")
3673 (set_attr "z10prop" "z10_super,z10_super")])
3675 (define_insn "*insvdi_mem_reghigh"
3676 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3677 (match_operand 1 "const_int_operand" "n")
3678 (const_int 0))
3679 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3680 (const_int 32)))]
3681 "TARGET_ZARCH
3682 && INTVAL (operands[1]) > 0
3683 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3684 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3685 {
3686 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3688 operands[1] = GEN_INT ((1ul << size) - 1);
3689 return "stcmh\t%2,%1,%S0";
3690 }
3691 [(set_attr "op_type" "RSY")
3692 (set_attr "z10prop" "z10_super")])
3694 (define_insn "*insvdi_reg_imm"
3695 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3696 (const_int 16)
3697 (match_operand 1 "const_int_operand" "n"))
3698 (match_operand:DI 2 "const_int_operand" "n"))]
3699 "TARGET_ZARCH
3700 && INTVAL (operands[1]) >= 0
3701 && INTVAL (operands[1]) < BITS_PER_WORD
3702 && INTVAL (operands[1]) % 16 == 0"
3703 {
3704 switch (BITS_PER_WORD - INTVAL (operands[1]))
3705 {
3706 case 64: return "iihh\t%0,%x2"; break;
3707 case 48: return "iihl\t%0,%x2"; break;
3708 case 32: return "iilh\t%0,%x2"; break;
3709 case 16: return "iill\t%0,%x2"; break;
3710 default: gcc_unreachable();
3711 }
3712 }
3713 [(set_attr "op_type" "RI")
3714 (set_attr "z10prop" "z10_super_E1")])
3716 ; Update the left-most 32 bit of a DI.
3717 (define_insn "*insv_h_di_reg_extimm"
3718 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3719 (const_int 32)
3720 (const_int 0))
3721 (match_operand:DI 1 "const_int_operand" "n"))]
3722 "TARGET_EXTIMM"
3723 "iihf\t%0,%o1"
3724 [(set_attr "op_type" "RIL")
3725 (set_attr "z10prop" "z10_fwd_E1")])
3727 ; Update the right-most 32 bit of a DI.
3728 (define_insn "*insv_l_di_reg_extimm"
3729 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3730 (const_int 32)
3731 (const_int 32))
3732 (match_operand:DI 1 "const_int_operand" "n"))]
3733 "TARGET_EXTIMM"
3734 "iilf\t%0,%o1"
3735 [(set_attr "op_type" "RIL")
3736 (set_attr "z10prop" "z10_fwd_A1")])
3738 ;
3739 ; extendsidi2 instruction pattern(s).
3740 ;
3742 (define_expand "extendsidi2"
3743 [(set (match_operand:DI 0 "register_operand" "")
3744 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3745 ""
3746 {
3747 if (!TARGET_ZARCH)
3748 {
3749 emit_clobber (operands[0]);
3750 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3751 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3752 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3753 DONE;
3754 }
3755 })
3757 (define_insn "*extendsidi2"
3758 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3759 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3760 "TARGET_ZARCH"
3761 "@
3762 lgfr\t%0,%1
3763 lgf\t%0,%1
3764 lgfrl\t%0,%1"
3765 [(set_attr "op_type" "RRE,RXY,RIL")
3766 (set_attr "type" "*,*,larl")
3767 (set_attr "cpu_facility" "*,*,z10")
3768 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3770 ;
3771 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3772 ;
3774 (define_expand "extend<HQI:mode><DSI:mode>2"
3775 [(set (match_operand:DSI 0 "register_operand" "")
3776 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3777 ""
3778 {
3779 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3780 {
3781 rtx tmp = gen_reg_rtx (SImode);
3782 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3783 emit_insn (gen_extendsidi2 (operands[0], tmp));
3784 DONE;
3785 }
3786 else if (!TARGET_EXTIMM)
3787 {
3788 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3790 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3791 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3792 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3793 DONE;
3794 }
3795 })
3797 ;
3798 ; extendhidi2 instruction pattern(s).
3799 ;
3801 (define_insn "*extendhidi2_extimm"
3802 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3803 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3804 "TARGET_ZARCH && TARGET_EXTIMM"
3805 "@
3806 lghr\t%0,%1
3807 lgh\t%0,%1
3808 lghrl\t%0,%1"
3809 [(set_attr "op_type" "RRE,RXY,RIL")
3810 (set_attr "type" "*,*,larl")
3811 (set_attr "cpu_facility" "extimm,extimm,z10")
3812 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3814 (define_insn "*extendhidi2"
3815 [(set (match_operand:DI 0 "register_operand" "=d")
3816 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3817 "TARGET_ZARCH"
3818 "lgh\t%0,%1"
3819 [(set_attr "op_type" "RXY")
3820 (set_attr "z10prop" "z10_super_E1")])
3822 ;
3823 ; extendhisi2 instruction pattern(s).
3824 ;
3826 (define_insn "*extendhisi2_extimm"
3827 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3828 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3829 "TARGET_EXTIMM"
3830 "@
3831 lhr\t%0,%1
3832 lh\t%0,%1
3833 lhy\t%0,%1
3834 lhrl\t%0,%1"
3835 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3836 (set_attr "type" "*,*,*,larl")
3837 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3838 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3840 (define_insn "*extendhisi2"
3841 [(set (match_operand:SI 0 "register_operand" "=d,d")
3842 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3843 "!TARGET_EXTIMM"
3844 "@
3845 lh\t%0,%1
3846 lhy\t%0,%1"
3847 [(set_attr "op_type" "RX,RXY")
3848 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3850 ;
3851 ; extendqi(si|di)2 instruction pattern(s).
3852 ;
3854 ; lbr, lgbr, lb, lgb
3855 (define_insn "*extendqi<mode>2_extimm"
3856 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3857 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3858 "TARGET_EXTIMM"
3859 "@
3860 l<g>br\t%0,%1
3861 l<g>b\t%0,%1"
3862 [(set_attr "op_type" "RRE,RXY")
3863 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3865 ; lb, lgb
3866 (define_insn "*extendqi<mode>2"
3867 [(set (match_operand:GPR 0 "register_operand" "=d")
3868 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3869 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3870 "l<g>b\t%0,%1"
3871 [(set_attr "op_type" "RXY")
3872 (set_attr "z10prop" "z10_super_E1")])
3874 (define_insn_and_split "*extendqi<mode>2_short_displ"
3875 [(set (match_operand:GPR 0 "register_operand" "=d")
3876 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3877 (clobber (reg:CC CC_REGNUM))]
3878 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3879 "#"
3880 "&& reload_completed"
3881 [(parallel
3882 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3883 (clobber (reg:CC CC_REGNUM))])
3884 (parallel
3885 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3886 (clobber (reg:CC CC_REGNUM))])]
3887 {
3888 operands[1] = adjust_address (operands[1], BLKmode, 0);
3889 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3890 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3891 })
3893 ;
3894 ; zero_extendsidi2 instruction pattern(s).
3895 ;
3897 (define_expand "zero_extendsidi2"
3898 [(set (match_operand:DI 0 "register_operand" "")
3899 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3900 ""
3901 {
3902 if (!TARGET_ZARCH)
3903 {
3904 emit_clobber (operands[0]);
3905 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3906 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3907 DONE;
3908 }
3909 })
3911 (define_insn "*zero_extendsidi2"
3912 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3913 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3914 "TARGET_ZARCH"
3915 "@
3916 llgfr\t%0,%1
3917 llgf\t%0,%1
3918 llgfrl\t%0,%1"
3919 [(set_attr "op_type" "RRE,RXY,RIL")
3920 (set_attr "type" "*,*,larl")
3921 (set_attr "cpu_facility" "*,*,z10")
3922 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3924 ;
3925 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3926 ;
3928 (define_insn "*llgt_sidi"
3929 [(set (match_operand:DI 0 "register_operand" "=d")
3930 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3931 (const_int 2147483647)))]
3932 "TARGET_ZARCH"
3933 "llgt\t%0,%1"
3934 [(set_attr "op_type" "RXE")
3935 (set_attr "z10prop" "z10_super_E1")])
3937 (define_insn_and_split "*llgt_sidi_split"
3938 [(set (match_operand:DI 0 "register_operand" "=d")
3939 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3940 (const_int 2147483647)))
3941 (clobber (reg:CC CC_REGNUM))]
3942 "TARGET_ZARCH"
3943 "#"
3944 "&& reload_completed"
3945 [(set (match_dup 0)
3946 (and:DI (subreg:DI (match_dup 1) 0)
3947 (const_int 2147483647)))]
3948 "")
3950 (define_insn "*llgt_sisi"
3951 [(set (match_operand:SI 0 "register_operand" "=d,d")
3952 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3953 (const_int 2147483647)))]
3954 "TARGET_ZARCH"
3955 "@
3956 llgtr\t%0,%1
3957 llgt\t%0,%1"
3958 [(set_attr "op_type" "RRE,RXE")
3959 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3961 (define_insn "*llgt_didi"
3962 [(set (match_operand:DI 0 "register_operand" "=d,d")
3963 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3964 (const_int 2147483647)))]
3965 "TARGET_ZARCH"
3966 "@
3967 llgtr\t%0,%1
3968 llgt\t%0,%N1"
3969 [(set_attr "op_type" "RRE,RXE")
3970 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3972 (define_split
3973 [(set (match_operand:DSI 0 "register_operand" "")
3974 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3975 (const_int 2147483647)))
3976 (clobber (reg:CC CC_REGNUM))]
3977 "TARGET_ZARCH && reload_completed"
3978 [(set (match_dup 0)
3979 (and:DSI (match_dup 1)
3980 (const_int 2147483647)))]
3981 "")
3983 ;
3984 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3985 ;
3987 (define_expand "zero_extend<mode>di2"
3988 [(set (match_operand:DI 0 "register_operand" "")
3989 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3990 ""
3991 {
3992 if (!TARGET_ZARCH)
3993 {
3994 rtx tmp = gen_reg_rtx (SImode);
3995 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3996 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3997 DONE;
3998 }
3999 else if (!TARGET_EXTIMM)
4000 {
4001 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4002 operands[1] = gen_lowpart (DImode, operands[1]);
4003 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4004 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4005 DONE;
4006 }
4007 })
4009 (define_expand "zero_extend<mode>si2"
4010 [(set (match_operand:SI 0 "register_operand" "")
4011 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4012 ""
4013 {
4014 if (!TARGET_EXTIMM)
4015 {
4016 operands[1] = gen_lowpart (SImode, operands[1]);
4017 emit_insn (gen_andsi3 (operands[0], operands[1],
4018 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4019 DONE;
4020 }
4021 })
4023 ; llhrl, llghrl
4024 (define_insn "*zero_extendhi<mode>2_z10"
4025 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4026 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4027 "TARGET_Z10"
4028 "@
4029 ll<g>hr\t%0,%1
4030 ll<g>h\t%0,%1
4031 ll<g>hrl\t%0,%1"
4032 [(set_attr "op_type" "RXY,RRE,RIL")
4033 (set_attr "type" "*,*,larl")
4034 (set_attr "cpu_facility" "*,*,z10")
4035 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4037 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4038 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4039 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4040 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4041 "TARGET_EXTIMM"
4042 "@
4043 ll<g><hc>r\t%0,%1
4044 ll<g><hc>\t%0,%1"
4045 [(set_attr "op_type" "RRE,RXY")
4046 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4048 ; llgh, llgc
4049 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4050 [(set (match_operand:GPR 0 "register_operand" "=d")
4051 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4052 "TARGET_ZARCH && !TARGET_EXTIMM"
4053 "llg<hc>\t%0,%1"
4054 [(set_attr "op_type" "RXY")
4055 (set_attr "z10prop" "z10_fwd_A3")])
4057 (define_insn_and_split "*zero_extendhisi2_31"
4058 [(set (match_operand:SI 0 "register_operand" "=&d")
4059 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4060 (clobber (reg:CC CC_REGNUM))]
4061 "!TARGET_ZARCH"
4062 "#"
4063 "&& reload_completed"
4064 [(set (match_dup 0) (const_int 0))
4065 (parallel
4066 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4067 (clobber (reg:CC CC_REGNUM))])]
4068 "operands[2] = gen_lowpart (HImode, operands[0]);")
4070 (define_insn_and_split "*zero_extendqisi2_31"
4071 [(set (match_operand:SI 0 "register_operand" "=&d")
4072 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4073 "!TARGET_ZARCH"
4074 "#"
4075 "&& reload_completed"
4076 [(set (match_dup 0) (const_int 0))
4077 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4078 "operands[2] = gen_lowpart (QImode, operands[0]);")
4080 ;
4081 ; zero_extendqihi2 instruction pattern(s).
4082 ;
4084 (define_expand "zero_extendqihi2"
4085 [(set (match_operand:HI 0 "register_operand" "")
4086 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4087 "TARGET_ZARCH && !TARGET_EXTIMM"
4088 {
4089 operands[1] = gen_lowpart (HImode, operands[1]);
4090 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4091 DONE;
4092 })
4094 (define_insn "*zero_extendqihi2_64"
4095 [(set (match_operand:HI 0 "register_operand" "=d")
4096 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4097 "TARGET_ZARCH && !TARGET_EXTIMM"
4098 "llgc\t%0,%1"
4099 [(set_attr "op_type" "RXY")
4100 (set_attr "z10prop" "z10_fwd_A3")])
4102 (define_insn_and_split "*zero_extendqihi2_31"
4103 [(set (match_operand:HI 0 "register_operand" "=&d")
4104 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4105 "!TARGET_ZARCH"
4106 "#"
4107 "&& reload_completed"
4108 [(set (match_dup 0) (const_int 0))
4109 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4110 "operands[2] = gen_lowpart (QImode, operands[0]);")
4112 ;
4113 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4114 ;
4116 (define_expand "fixuns_truncdddi2"
4117 [(parallel
4118 [(set (match_operand:DI 0 "register_operand" "")
4119 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4120 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4121 (clobber (reg:CC CC_REGNUM))])]
4123 "TARGET_HARD_DFP"
4124 {
4125 if (!TARGET_Z196)
4126 {
4127 rtx label1 = gen_label_rtx ();
4128 rtx label2 = gen_label_rtx ();
4129 rtx temp = gen_reg_rtx (TDmode);
4130 REAL_VALUE_TYPE cmp, sub;
4132 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4133 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4135 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4136 solution is doing the check and the subtraction in TD mode and using a
4137 TD -> DI convert afterwards. */
4138 emit_insn (gen_extendddtd2 (temp, operands[1]));
4139 temp = force_reg (TDmode, temp);
4140 emit_cmp_and_jump_insns (temp,
4141 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4142 LT, NULL_RTX, VOIDmode, 0, label1);
4143 emit_insn (gen_subtd3 (temp, temp,
4144 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4145 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4146 emit_jump (label2);
4148 emit_label (label1);
4149 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4150 emit_label (label2);
4151 DONE;
4152 }
4153 })
4155 (define_expand "fixuns_trunctddi2"
4156 [(parallel
4157 [(set (match_operand:DI 0 "register_operand" "")
4158 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4159 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4160 (clobber (reg:CC CC_REGNUM))])]
4162 "TARGET_HARD_DFP"
4163 {
4164 if (!TARGET_Z196)
4165 {
4166 rtx label1 = gen_label_rtx ();
4167 rtx label2 = gen_label_rtx ();
4168 rtx temp = gen_reg_rtx (TDmode);
4169 REAL_VALUE_TYPE cmp, sub;
4171 operands[1] = force_reg (TDmode, operands[1]);
4172 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4173 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4175 emit_cmp_and_jump_insns (operands[1],
4176 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4177 LT, NULL_RTX, VOIDmode, 0, label1);
4178 emit_insn (gen_subtd3 (temp, operands[1],
4179 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4180 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4181 emit_jump (label2);
4183 emit_label (label1);
4184 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4185 emit_label (label2);
4186 DONE;
4187 }
4188 })
4190 ;
4191 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4192 ; instruction pattern(s).
4193 ;
4195 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4196 [(parallel
4197 [(set (match_operand:GPR 0 "register_operand" "")
4198 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4199 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4200 (clobber (reg:CC CC_REGNUM))])]
4201 "TARGET_HARD_FLOAT"
4202 {
4203 if (!TARGET_Z196)
4204 {
4205 rtx label1 = gen_label_rtx ();
4206 rtx label2 = gen_label_rtx ();
4207 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4208 REAL_VALUE_TYPE cmp, sub;
4210 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4211 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4212 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4214 emit_cmp_and_jump_insns (operands[1],
4215 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4216 LT, NULL_RTX, VOIDmode, 0, label1);
4217 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4218 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4219 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4220 GEN_INT (7)));
4221 emit_jump (label2);
4223 emit_label (label1);
4224 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4225 operands[1], GEN_INT (5)));
4226 emit_label (label2);
4227 DONE;
4228 }
4229 })
4231 ; fixuns_trunc(td|dd)si2 expander
4232 (define_expand "fixuns_trunc<mode>si2"
4233 [(parallel
4234 [(set (match_operand:SI 0 "register_operand" "")
4235 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4236 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4237 (clobber (reg:CC CC_REGNUM))])]
4238 "TARGET_Z196 && TARGET_HARD_DFP"
4239 "")
4241 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4243 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4244 ; clfdtr, clfxtr, clgdtr, clgxtr
4245 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4246 [(set (match_operand:GPR 0 "register_operand" "=r")
4247 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4248 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4249 (clobber (reg:CC CC_REGNUM))]
4250 "TARGET_Z196"
4251 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4252 [(set_attr "op_type" "RRF")
4253 (set_attr "type" "ftoi")])
4255 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4256 [(set (match_operand:GPR 0 "register_operand" "")
4257 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4258 "TARGET_HARD_FLOAT"
4259 {
4260 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4261 GEN_INT (5)));
4262 DONE;
4263 })
4265 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4266 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4267 [(set (match_operand:GPR 0 "register_operand" "=d")
4268 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4269 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4270 (clobber (reg:CC CC_REGNUM))]
4271 "TARGET_HARD_FLOAT"
4272 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4273 [(set_attr "op_type" "RRE")
4274 (set_attr "type" "ftoi")])
4277 ;
4278 ; fix_trunc(td|dd)di2 instruction pattern(s).
4279 ;
4281 (define_expand "fix_trunc<mode>di2"
4282 [(set (match_operand:DI 0 "register_operand" "")
4283 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4284 "TARGET_ZARCH && TARGET_HARD_DFP"
4285 {
4286 operands[1] = force_reg (<MODE>mode, operands[1]);
4287 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4288 GEN_INT (9)));
4289 DONE;
4290 })
4292 ; cgxtr, cgdtr
4293 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4294 [(set (match_operand:DI 0 "register_operand" "=d")
4295 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4296 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4297 (clobber (reg:CC CC_REGNUM))]
4298 "TARGET_ZARCH && TARGET_HARD_DFP"
4299 "cg<DFP:xde>tr\t%0,%h2,%1"
4300 [(set_attr "op_type" "RRF")
4301 (set_attr "type" "ftoidfp")])
4304 ;
4305 ; fix_trunctf(si|di)2 instruction pattern(s).
4306 ;
4308 (define_expand "fix_trunctf<mode>2"
4309 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4310 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4311 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4312 (clobber (reg:CC CC_REGNUM))])]
4313 "TARGET_HARD_FLOAT"
4314 "")
4317 ;
4318 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4319 ;
4321 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4322 (define_insn "floatdi<mode>2"
4323 [(set (match_operand:FP 0 "register_operand" "=f")
4324 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4325 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4326 "c<xde>g<bt>r\t%0,%1"
4327 [(set_attr "op_type" "RRE")
4328 (set_attr "type" "itof<mode>" )])
4330 ; cxfbr, cdfbr, cefbr
4331 (define_insn "floatsi<mode>2"
4332 [(set (match_operand:BFP 0 "register_operand" "=f")
4333 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4334 "TARGET_HARD_FLOAT"
4335 "c<xde>fbr\t%0,%1"
4336 [(set_attr "op_type" "RRE")
4337 (set_attr "type" "itof<mode>" )])
4339 ; cxftr, cdftr
4340 (define_insn "floatsi<mode>2"
4341 [(set (match_operand:DFP 0 "register_operand" "=f")
4342 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4343 "TARGET_Z196 && TARGET_HARD_FLOAT"
4344 "c<xde>ftr\t%0,0,%1,0"
4345 [(set_attr "op_type" "RRE")
4346 (set_attr "type" "itof<mode>" )])
4348 ;
4349 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4350 ;
4352 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4353 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4354 (define_insn "floatuns<GPR:mode><FP:mode>2"
4355 [(set (match_operand:FP 0 "register_operand" "=f")
4356 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4357 "TARGET_Z196 && TARGET_HARD_FLOAT"
4358 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4359 [(set_attr "op_type" "RRE")
4360 (set_attr "type" "itof<FP:mode>" )])
4362 ;
4363 ; truncdfsf2 instruction pattern(s).
4364 ;
4366 (define_insn "truncdfsf2"
4367 [(set (match_operand:SF 0 "register_operand" "=f")
4368 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4369 "TARGET_HARD_FLOAT"
4370 "ledbr\t%0,%1"
4371 [(set_attr "op_type" "RRE")
4372 (set_attr "type" "ftruncdf")])
4374 ;
4375 ; trunctf(df|sf)2 instruction pattern(s).
4376 ;
4378 ; ldxbr, lexbr
4379 (define_insn "trunctf<mode>2"
4380 [(set (match_operand:DSF 0 "register_operand" "=f")
4381 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4382 (clobber (match_scratch:TF 2 "=f"))]
4383 "TARGET_HARD_FLOAT"
4384 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4385 [(set_attr "length" "6")
4386 (set_attr "type" "ftrunctf")])
4388 ;
4389 ; trunctddd2 and truncddsd2 instruction pattern(s).
4390 ;
4392 (define_insn "trunctddd2"
4393 [(set (match_operand:DD 0 "register_operand" "=f")
4394 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4395 (clobber (match_scratch:TD 2 "=f"))]
4396 "TARGET_HARD_DFP"
4397 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4398 [(set_attr "length" "6")
4399 (set_attr "type" "ftruncdd")])
4401 (define_insn "truncddsd2"
4402 [(set (match_operand:SD 0 "register_operand" "=f")
4403 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4404 "TARGET_HARD_DFP"
4405 "ledtr\t%0,0,%1,0"
4406 [(set_attr "op_type" "RRF")
4407 (set_attr "type" "ftruncsd")])
4409 ;
4410 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4411 ;
4413 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4414 (define_insn "extend<DSF:mode><BFP:mode>2"
4415 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4416 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4417 "TARGET_HARD_FLOAT
4418 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4419 "@
4420 l<BFP:xde><DSF:xde>br\t%0,%1
4421 l<BFP:xde><DSF:xde>b\t%0,%1"
4422 [(set_attr "op_type" "RRE,RXE")
4423 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4425 ;
4426 ; extendddtd2 and extendsddd2 instruction pattern(s).
4427 ;
4429 (define_insn "extendddtd2"
4430 [(set (match_operand:TD 0 "register_operand" "=f")
4431 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4432 "TARGET_HARD_DFP"
4433 "lxdtr\t%0,%1,0"
4434 [(set_attr "op_type" "RRF")
4435 (set_attr "type" "fsimptf")])
4437 (define_insn "extendsddd2"
4438 [(set (match_operand:DD 0 "register_operand" "=f")
4439 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4440 "TARGET_HARD_DFP"
4441 "ldetr\t%0,%1,0"
4442 [(set_attr "op_type" "RRF")
4443 (set_attr "type" "fsimptf")])
4445 ; Binary Floating Point - load fp integer
4447 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4448 ; For all of them the inexact exceptions are suppressed.
4450 ; fiebra, fidbra, fixbra
4451 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4452 [(set (match_operand:BFP 0 "register_operand" "=f")
4453 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4454 FPINT))]
4455 "TARGET_Z196"
4456 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4457 [(set_attr "op_type" "RRF")
4458 (set_attr "type" "fsimp<BFP:mode>")])
4460 ; rint is supposed to raise an inexact exception so we can use the
4461 ; older instructions.
4463 ; fiebr, fidbr, fixbr
4464 (define_insn "rint<BFP:mode>2"
4465 [(set (match_operand:BFP 0 "register_operand" "=f")
4466 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4467 UNSPEC_FPINT_RINT))]
4468 ""
4469 "fi<BFP:xde>br\t%0,0,%1"
4470 [(set_attr "op_type" "RRF")
4471 (set_attr "type" "fsimp<BFP:mode>")])
4474 ; Decimal Floating Point - load fp integer
4476 ; fidtr, fixtr
4477 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4478 [(set (match_operand:DFP 0 "register_operand" "=f")
4479 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4480 FPINT))]
4481 "TARGET_HARD_DFP"
4482 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4483 [(set_attr "op_type" "RRF")
4484 (set_attr "type" "fsimp<DFP:mode>")])
4486 ; fidtr, fixtr
4487 (define_insn "rint<DFP:mode>2"
4488 [(set (match_operand:DFP 0 "register_operand" "=f")
4489 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4490 UNSPEC_FPINT_RINT))]
4491 "TARGET_HARD_DFP"
4492 "fi<DFP:xde>tr\t%0,0,%1,0"
4493 [(set_attr "op_type" "RRF")
4494 (set_attr "type" "fsimp<DFP:mode>")])
4496 ;
4497 ; Binary <-> Decimal floating point trunc patterns
4498 ;
4500 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4501 [(set (reg:DFP_ALL FPR0_REGNUM)
4502 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4503 (use (reg:SI GPR0_REGNUM))
4504 (clobber (reg:CC CC_REGNUM))]
4505 "TARGET_HARD_DFP"
4506 "pfpo")
4508 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4509 [(set (reg:BFP FPR0_REGNUM)
4510 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4511 (use (reg:SI GPR0_REGNUM))
4512 (clobber (reg:CC CC_REGNUM))]
4513 "TARGET_HARD_DFP"
4514 "pfpo")
4516 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4517 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4518 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4519 (parallel
4520 [(set (reg:DFP_ALL FPR0_REGNUM)
4521 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4522 (use (reg:SI GPR0_REGNUM))
4523 (clobber (reg:CC CC_REGNUM))])
4524 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4525 (reg:DFP_ALL FPR0_REGNUM))]
4526 "TARGET_HARD_DFP
4527 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4528 {
4529 HOST_WIDE_INT flags;
4531 flags = (PFPO_CONVERT |
4532 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4533 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4535 operands[2] = GEN_INT (flags);
4536 })
4538 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4539 [(set (reg:DFP_ALL FPR4_REGNUM)
4540 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4541 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4542 (parallel
4543 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4544 (use (reg:SI GPR0_REGNUM))
4545 (clobber (reg:CC CC_REGNUM))])
4546 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4547 "TARGET_HARD_DFP
4548 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4549 {
4550 HOST_WIDE_INT flags;
4552 flags = (PFPO_CONVERT |
4553 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4554 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4556 operands[2] = GEN_INT (flags);
4557 })
4559 ;
4560 ; Binary <-> Decimal floating point extend patterns
4561 ;
4563 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4564 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4565 (use (reg:SI GPR0_REGNUM))
4566 (clobber (reg:CC CC_REGNUM))]
4567 "TARGET_HARD_DFP"
4568 "pfpo")
4570 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4571 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4572 (use (reg:SI GPR0_REGNUM))
4573 (clobber (reg:CC CC_REGNUM))]
4574 "TARGET_HARD_DFP"
4575 "pfpo")
4577 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4578 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4579 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4580 (parallel
4581 [(set (reg:DFP_ALL FPR0_REGNUM)
4582 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4583 (use (reg:SI GPR0_REGNUM))
4584 (clobber (reg:CC CC_REGNUM))])
4585 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4586 (reg:DFP_ALL FPR0_REGNUM))]
4587 "TARGET_HARD_DFP
4588 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4589 {
4590 HOST_WIDE_INT flags;
4592 flags = (PFPO_CONVERT |
4593 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4594 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4596 operands[2] = GEN_INT (flags);
4597 })
4599 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4600 [(set (reg:DFP_ALL FPR4_REGNUM)
4601 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4602 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4603 (parallel
4604 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4605 (use (reg:SI GPR0_REGNUM))
4606 (clobber (reg:CC CC_REGNUM))])
4607 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4608 "TARGET_HARD_DFP
4609 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4610 {
4611 HOST_WIDE_INT flags;
4613 flags = (PFPO_CONVERT |
4614 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4615 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4617 operands[2] = GEN_INT (flags);
4618 })
4621 ;;
4622 ;; ARITHMETIC OPERATIONS
4623 ;;
4624 ; arithmetic operations set the ConditionCode,
4625 ; because of unpredictable Bits in Register for Halfword and Byte
4626 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4628 ;;
4629 ;;- Add instructions.
4630 ;;
4632 ;
4633 ; addti3 instruction pattern(s).
4634 ;
4636 (define_insn_and_split "addti3"
4637 [(set (match_operand:TI 0 "register_operand" "=&d")
4638 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4639 (match_operand:TI 2 "general_operand" "do") ) )
4640 (clobber (reg:CC CC_REGNUM))]
4641 "TARGET_ZARCH"
4642 "#"
4643 "&& reload_completed"
4644 [(parallel
4645 [(set (reg:CCL1 CC_REGNUM)
4646 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4647 (match_dup 7)))
4648 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4649 (parallel
4650 [(set (match_dup 3) (plus:DI
4651 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4652 (match_dup 4)) (match_dup 5)))
4653 (clobber (reg:CC CC_REGNUM))])]
4654 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4655 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4656 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4657 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4658 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4659 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4661 ;
4662 ; adddi3 instruction pattern(s).
4663 ;
4665 (define_expand "adddi3"
4666 [(parallel
4667 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4668 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4669 (match_operand:DI 2 "general_operand" "")))
4670 (clobber (reg:CC CC_REGNUM))])]
4671 ""
4672 "")
4674 (define_insn "*adddi3_sign"
4675 [(set (match_operand:DI 0 "register_operand" "=d,d")
4676 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4677 (match_operand:DI 1 "register_operand" "0,0")))
4678 (clobber (reg:CC CC_REGNUM))]
4679 "TARGET_ZARCH"
4680 "@
4681 agfr\t%0,%2
4682 agf\t%0,%2"
4683 [(set_attr "op_type" "RRE,RXY")
4684 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4686 (define_insn "*adddi3_zero_cc"
4687 [(set (reg CC_REGNUM)
4688 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4689 (match_operand:DI 1 "register_operand" "0,0"))
4690 (const_int 0)))
4691 (set (match_operand:DI 0 "register_operand" "=d,d")
4692 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4693 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4694 "@
4695 algfr\t%0,%2
4696 algf\t%0,%2"
4697 [(set_attr "op_type" "RRE,RXY")
4698 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4700 (define_insn "*adddi3_zero_cconly"
4701 [(set (reg CC_REGNUM)
4702 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4703 (match_operand:DI 1 "register_operand" "0,0"))
4704 (const_int 0)))
4705 (clobber (match_scratch:DI 0 "=d,d"))]
4706 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4707 "@
4708 algfr\t%0,%2
4709 algf\t%0,%2"
4710 [(set_attr "op_type" "RRE,RXY")
4711 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4713 (define_insn "*adddi3_zero"
4714 [(set (match_operand:DI 0 "register_operand" "=d,d")
4715 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4716 (match_operand:DI 1 "register_operand" "0,0")))
4717 (clobber (reg:CC CC_REGNUM))]
4718 "TARGET_ZARCH"
4719 "@
4720 algfr\t%0,%2
4721 algf\t%0,%2"
4722 [(set_attr "op_type" "RRE,RXY")
4723 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4725 (define_insn_and_split "*adddi3_31z"
4726 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4727 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4728 (match_operand:DI 2 "general_operand" "do") ) )
4729 (clobber (reg:CC CC_REGNUM))]
4730 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4731 "#"
4732 "&& reload_completed"
4733 [(parallel
4734 [(set (reg:CCL1 CC_REGNUM)
4735 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4736 (match_dup 7)))
4737 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4738 (parallel
4739 [(set (match_dup 3) (plus:SI
4740 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4741 (match_dup 4)) (match_dup 5)))
4742 (clobber (reg:CC CC_REGNUM))])]
4743 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4744 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4745 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4746 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4747 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4748 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4750 (define_insn_and_split "*adddi3_31"
4751 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4752 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4753 (match_operand:DI 2 "general_operand" "do") ) )
4754 (clobber (reg:CC CC_REGNUM))]
4755 "!TARGET_CPU_ZARCH"
4756 "#"
4757 "&& reload_completed"
4758 [(parallel
4759 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4760 (clobber (reg:CC CC_REGNUM))])
4761 (parallel
4762 [(set (reg:CCL1 CC_REGNUM)
4763 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4764 (match_dup 7)))
4765 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4766 (set (pc)
4767 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4768 (pc)
4769 (label_ref (match_dup 9))))
4770 (parallel
4771 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4772 (clobber (reg:CC CC_REGNUM))])
4773 (match_dup 9)]
4774 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4775 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4776 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4777 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4778 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4779 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4780 operands[9] = gen_label_rtx ();")
4782 ;
4783 ; addsi3 instruction pattern(s).
4784 ;
4786 (define_expand "addsi3"
4787 [(parallel
4788 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4789 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4790 (match_operand:SI 2 "general_operand" "")))
4791 (clobber (reg:CC CC_REGNUM))])]
4792 ""
4793 "")
4795 (define_insn "*addsi3_sign"
4796 [(set (match_operand:SI 0 "register_operand" "=d,d")
4797 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4798 (match_operand:SI 1 "register_operand" "0,0")))
4799 (clobber (reg:CC CC_REGNUM))]
4800 ""
4801 "@
4802 ah\t%0,%2
4803 ahy\t%0,%2"
4804 [(set_attr "op_type" "RX,RXY")
4805 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4807 ;
4808 ; add(di|si)3 instruction pattern(s).
4809 ;
4811 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4812 (define_insn "*add<mode>3"
4813 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4814 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4815 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4816 (clobber (reg:CC CC_REGNUM))]
4817 ""
4818 "@
4819 a<g>r\t%0,%2
4820 a<g>rk\t%0,%1,%2
4821 a<g>hi\t%0,%h2
4822 a<g>hik\t%0,%1,%h2
4823 al<g>fi\t%0,%2
4824 sl<g>fi\t%0,%n2
4825 a<g>\t%0,%2
4826 a<y>\t%0,%2
4827 a<g>si\t%0,%c2"
4828 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4829 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4830 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4831 z10_super_E1,z10_super_E1,z10_super_E1")])
4833 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4834 (define_insn "*add<mode>3_carry1_cc"
4835 [(set (reg CC_REGNUM)
4836 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4837 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4838 (match_dup 1)))
4839 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4840 (plus:GPR (match_dup 1) (match_dup 2)))]
4841 "s390_match_ccmode (insn, CCL1mode)"
4842 "@
4843 al<g>r\t%0,%2
4844 al<g>rk\t%0,%1,%2
4845 al<g>fi\t%0,%2
4846 sl<g>fi\t%0,%n2
4847 al<g>hsik\t%0,%1,%h2
4848 al<g>\t%0,%2
4849 al<y>\t%0,%2
4850 al<g>si\t%0,%c2"
4851 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4852 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4853 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4854 z10_super_E1,z10_super_E1,z10_super_E1")])
4856 ; alr, al, aly, algr, alg, alrk, algrk
4857 (define_insn "*add<mode>3_carry1_cconly"
4858 [(set (reg CC_REGNUM)
4859 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4860 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4861 (match_dup 1)))
4862 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4863 "s390_match_ccmode (insn, CCL1mode)"
4864 "@
4865 al<g>r\t%0,%2
4866 al<g>rk\t%0,%1,%2
4867 al<g>\t%0,%2
4868 al<y>\t%0,%2"
4869 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4870 (set_attr "cpu_facility" "*,z196,*,*")
4871 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4873 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4874 (define_insn "*add<mode>3_carry2_cc"
4875 [(set (reg CC_REGNUM)
4876 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4877 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4878 (match_dup 2)))
4879 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4880 (plus:GPR (match_dup 1) (match_dup 2)))]
4881 "s390_match_ccmode (insn, CCL1mode)"
4882 "@
4883 al<g>r\t%0,%2
4884 al<g>rk\t%0,%1,%2
4885 al<g>fi\t%0,%2
4886 sl<g>fi\t%0,%n2
4887 al<g>hsik\t%0,%1,%h2
4888 al<g>\t%0,%2
4889 al<y>\t%0,%2
4890 al<g>si\t%0,%c2"
4891 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4892 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4893 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4894 z10_super_E1,z10_super_E1,z10_super_E1")])
4896 ; alr, al, aly, algr, alg, alrk, algrk
4897 (define_insn "*add<mode>3_carry2_cconly"
4898 [(set (reg CC_REGNUM)
4899 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4900 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4901 (match_dup 2)))
4902 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4903 "s390_match_ccmode (insn, CCL1mode)"
4904 "@
4905 al<g>r\t%0,%2
4906 al<g>rk\t%0,%1,%2
4907 al<g>\t%0,%2
4908 al<y>\t%0,%2"
4909 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4910 (set_attr "cpu_facility" "*,z196,*,*")
4911 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4913 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4914 (define_insn "*add<mode>3_cc"
4915 [(set (reg CC_REGNUM)
4916 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4917 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4918 (const_int 0)))
4919 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4920 (plus:GPR (match_dup 1) (match_dup 2)))]
4921 "s390_match_ccmode (insn, CCLmode)"
4922 "@
4923 al<g>r\t%0,%2
4924 al<g>rk\t%0,%1,%2
4925 al<g>fi\t%0,%2
4926 sl<g>fi\t%0,%n2
4927 al<g>hsik\t%0,%1,%h2
4928 al<g>\t%0,%2
4929 al<y>\t%0,%2
4930 al<g>si\t%0,%c2"
4931 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4932 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4933 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4934 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4936 ; alr, al, aly, algr, alg, alrk, algrk
4937 (define_insn "*add<mode>3_cconly"
4938 [(set (reg CC_REGNUM)
4939 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4940 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4941 (const_int 0)))
4942 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4943 "s390_match_ccmode (insn, CCLmode)"
4944 "@
4945 al<g>r\t%0,%2
4946 al<g>rk\t%0,%1,%2
4947 al<g>\t%0,%2
4948 al<y>\t%0,%2"
4949 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4950 (set_attr "cpu_facility" "*,z196,*,*")
4951 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4953 ; alr, al, aly, algr, alg, alrk, algrk
4954 (define_insn "*add<mode>3_cconly2"
4955 [(set (reg CC_REGNUM)
4956 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4957 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4958 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4959 "s390_match_ccmode(insn, CCLmode)"
4960 "@
4961 al<g>r\t%0,%2
4962 al<g>rk\t%0,%1,%2
4963 al<g>\t%0,%2
4964 al<y>\t%0,%2"
4965 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4966 (set_attr "cpu_facility" "*,z196,*,*")
4967 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4969 ; ahi, afi, aghi, agfi, asi, agsi
4970 (define_insn "*add<mode>3_imm_cc"
4971 [(set (reg CC_REGNUM)
4972 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4973 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4974 (const_int 0)))
4975 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4976 (plus:GPR (match_dup 1) (match_dup 2)))]
4977 "s390_match_ccmode (insn, CCAmode)
4978 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4979 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4980 /* Avoid INT32_MIN on 32 bit. */
4981 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4982 "@
4983 a<g>hi\t%0,%h2
4984 a<g>hik\t%0,%1,%h2
4985 a<g>fi\t%0,%2
4986 a<g>si\t%0,%c2"
4987 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4988 (set_attr "cpu_facility" "*,z196,extimm,z10")
4989 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4991 ;
4992 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4993 ;
4995 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4996 (define_insn "add<mode>3"
4997 [(set (match_operand:FP 0 "register_operand" "=f, f")
4998 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4999 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5000 (clobber (reg:CC CC_REGNUM))]
5001 "TARGET_HARD_FLOAT"
5002 "@
5003 a<xde><bt>r\t%0,<op1>%2
5004 a<xde>b\t%0,%2"
5005 [(set_attr "op_type" "<RRer>,RXE")
5006 (set_attr "type" "fsimp<mode>")])
5008 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5009 (define_insn "*add<mode>3_cc"
5010 [(set (reg CC_REGNUM)
5011 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5012 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5013 (match_operand:FP 3 "const0_operand" "")))
5014 (set (match_operand:FP 0 "register_operand" "=f,f")
5015 (plus:FP (match_dup 1) (match_dup 2)))]
5016 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5017 "@
5018 a<xde><bt>r\t%0,<op1>%2
5019 a<xde>b\t%0,%2"
5020 [(set_attr "op_type" "<RRer>,RXE")
5021 (set_attr "type" "fsimp<mode>")])
5023 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5024 (define_insn "*add<mode>3_cconly"
5025 [(set (reg CC_REGNUM)
5026 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5027 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5028 (match_operand:FP 3 "const0_operand" "")))
5029 (clobber (match_scratch:FP 0 "=f,f"))]
5030 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5031 "@
5032 a<xde><bt>r\t%0,<op1>%2
5033 a<xde>b\t%0,%2"
5034 [(set_attr "op_type" "<RRer>,RXE")
5035 (set_attr "type" "fsimp<mode>")])
5037 ;
5038 ; Pointer add instruction patterns
5039 ;
5041 ; This will match "*la_64"
5042 (define_expand "addptrdi3"
5043 [(set (match_operand:DI 0 "register_operand" "")
5044 (plus:DI (match_operand:DI 1 "register_operand" "")
5045 (match_operand:DI 2 "nonmemory_operand" "")))]
5046 "TARGET_64BIT"
5047 {
5048 if (GET_CODE (operands[2]) == CONST_INT)
5049 {
5050 HOST_WIDE_INT c = INTVAL (operands[2]);
5052 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5053 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5054 {
5055 operands[2] = force_const_mem (DImode, operands[2]);
5056 operands[2] = force_reg (DImode, operands[2]);
5057 }
5058 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5059 operands[2] = force_reg (DImode, operands[2]);
5060 }
5061 })
5063 ; For 31 bit we have to prevent the generated pattern from matching
5064 ; normal ADDs since la only does a 31 bit add. This is supposed to
5065 ; match "force_la_31".
5066 (define_expand "addptrsi3"
5067 [(parallel
5068 [(set (match_operand:SI 0 "register_operand" "")
5069 (plus:SI (match_operand:SI 1 "register_operand" "")
5070 (match_operand:SI 2 "nonmemory_operand" "")))
5071 (use (const_int 0))])]
5072 "!TARGET_64BIT"
5073 {
5074 if (GET_CODE (operands[2]) == CONST_INT)
5075 {
5076 HOST_WIDE_INT c = INTVAL (operands[2]);
5078 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5079 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5080 {
5081 operands[2] = force_const_mem (SImode, operands[2]);
5082 operands[2] = force_reg (SImode, operands[2]);
5083 }
5084 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5085 operands[2] = force_reg (SImode, operands[2]);
5086 }
5087 })
5089 ;;
5090 ;;- Subtract instructions.
5091 ;;
5093 ;
5094 ; subti3 instruction pattern(s).
5095 ;
5097 (define_insn_and_split "subti3"
5098 [(set (match_operand:TI 0 "register_operand" "=&d")
5099 (minus:TI (match_operand:TI 1 "register_operand" "0")
5100 (match_operand:TI 2 "general_operand" "do") ) )
5101 (clobber (reg:CC CC_REGNUM))]
5102 "TARGET_ZARCH"
5103 "#"
5104 "&& reload_completed"
5105 [(parallel
5106 [(set (reg:CCL2 CC_REGNUM)
5107 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5108 (match_dup 7)))
5109 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5110 (parallel
5111 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5112 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5113 (clobber (reg:CC CC_REGNUM))])]
5114 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5115 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5116 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5117 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5118 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5119 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5121 ;
5122 ; subdi3 instruction pattern(s).
5123 ;
5125 (define_expand "subdi3"
5126 [(parallel
5127 [(set (match_operand:DI 0 "register_operand" "")
5128 (minus:DI (match_operand:DI 1 "register_operand" "")
5129 (match_operand:DI 2 "general_operand" "")))
5130 (clobber (reg:CC CC_REGNUM))])]
5131 ""
5132 "")
5134 (define_insn "*subdi3_sign"
5135 [(set (match_operand:DI 0 "register_operand" "=d,d")
5136 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5137 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5138 (clobber (reg:CC CC_REGNUM))]
5139 "TARGET_ZARCH"
5140 "@
5141 sgfr\t%0,%2
5142 sgf\t%0,%2"
5143 [(set_attr "op_type" "RRE,RXY")
5144 (set_attr "z10prop" "z10_c,*")
5145 (set_attr "z196prop" "z196_cracked")])
5147 (define_insn "*subdi3_zero_cc"
5148 [(set (reg CC_REGNUM)
5149 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5150 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5151 (const_int 0)))
5152 (set (match_operand:DI 0 "register_operand" "=d,d")
5153 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5154 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5155 "@
5156 slgfr\t%0,%2
5157 slgf\t%0,%2"
5158 [(set_attr "op_type" "RRE,RXY")
5159 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5161 (define_insn "*subdi3_zero_cconly"
5162 [(set (reg CC_REGNUM)
5163 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5164 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5165 (const_int 0)))
5166 (clobber (match_scratch:DI 0 "=d,d"))]
5167 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5168 "@
5169 slgfr\t%0,%2
5170 slgf\t%0,%2"
5171 [(set_attr "op_type" "RRE,RXY")
5172 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5174 (define_insn "*subdi3_zero"
5175 [(set (match_operand:DI 0 "register_operand" "=d,d")
5176 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5177 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5178 (clobber (reg:CC CC_REGNUM))]
5179 "TARGET_ZARCH"
5180 "@
5181 slgfr\t%0,%2
5182 slgf\t%0,%2"
5183 [(set_attr "op_type" "RRE,RXY")
5184 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5186 (define_insn_and_split "*subdi3_31z"
5187 [(set (match_operand:DI 0 "register_operand" "=&d")
5188 (minus:DI (match_operand:DI 1 "register_operand" "0")
5189 (match_operand:DI 2 "general_operand" "do") ) )
5190 (clobber (reg:CC CC_REGNUM))]
5191 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5192 "#"
5193 "&& reload_completed"
5194 [(parallel
5195 [(set (reg:CCL2 CC_REGNUM)
5196 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5197 (match_dup 7)))
5198 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5199 (parallel
5200 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5201 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5202 (clobber (reg:CC CC_REGNUM))])]
5203 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5204 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5205 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5206 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5207 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5208 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5210 (define_insn_and_split "*subdi3_31"
5211 [(set (match_operand:DI 0 "register_operand" "=&d")
5212 (minus:DI (match_operand:DI 1 "register_operand" "0")
5213 (match_operand:DI 2 "general_operand" "do") ) )
5214 (clobber (reg:CC CC_REGNUM))]
5215 "!TARGET_CPU_ZARCH"
5216 "#"
5217 "&& reload_completed"
5218 [(parallel
5219 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5220 (clobber (reg:CC CC_REGNUM))])
5221 (parallel
5222 [(set (reg:CCL2 CC_REGNUM)
5223 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5224 (match_dup 7)))
5225 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5226 (set (pc)
5227 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5228 (pc)
5229 (label_ref (match_dup 9))))
5230 (parallel
5231 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5232 (clobber (reg:CC CC_REGNUM))])
5233 (match_dup 9)]
5234 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5235 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5236 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5237 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5238 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5239 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5240 operands[9] = gen_label_rtx ();")
5242 ;
5243 ; subsi3 instruction pattern(s).
5244 ;
5246 (define_expand "subsi3"
5247 [(parallel
5248 [(set (match_operand:SI 0 "register_operand" "")
5249 (minus:SI (match_operand:SI 1 "register_operand" "")
5250 (match_operand:SI 2 "general_operand" "")))
5251 (clobber (reg:CC CC_REGNUM))])]
5252 ""
5253 "")
5255 (define_insn "*subsi3_sign"
5256 [(set (match_operand:SI 0 "register_operand" "=d,d")
5257 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5258 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5259 (clobber (reg:CC CC_REGNUM))]
5260 ""
5261 "@
5262 sh\t%0,%2
5263 shy\t%0,%2"
5264 [(set_attr "op_type" "RX,RXY")
5265 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5267 ;
5268 ; sub(di|si)3 instruction pattern(s).
5269 ;
5271 ; sr, s, sy, sgr, sg, srk, sgrk
5272 (define_insn "*sub<mode>3"
5273 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5274 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5275 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5276 (clobber (reg:CC CC_REGNUM))]
5277 ""
5278 "@
5279 s<g>r\t%0,%2
5280 s<g>rk\t%0,%1,%2
5281 s<g>\t%0,%2
5282 s<y>\t%0,%2"
5283 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5284 (set_attr "cpu_facility" "*,z196,*,*")
5285 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5287 ; slr, sl, sly, slgr, slg, slrk, slgrk
5288 (define_insn "*sub<mode>3_borrow_cc"
5289 [(set (reg CC_REGNUM)
5290 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5291 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5292 (match_dup 1)))
5293 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5294 (minus:GPR (match_dup 1) (match_dup 2)))]
5295 "s390_match_ccmode (insn, CCL2mode)"
5296 "@
5297 sl<g>r\t%0,%2
5298 sl<g>rk\t%0,%1,%2
5299 sl<g>\t%0,%2
5300 sl<y>\t%0,%2"
5301 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5302 (set_attr "cpu_facility" "*,z196,*,*")
5303 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5305 ; slr, sl, sly, slgr, slg, slrk, slgrk
5306 (define_insn "*sub<mode>3_borrow_cconly"
5307 [(set (reg CC_REGNUM)
5308 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5309 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5310 (match_dup 1)))
5311 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5312 "s390_match_ccmode (insn, CCL2mode)"
5313 "@
5314 sl<g>r\t%0,%2
5315 sl<g>rk\t%0,%1,%2
5316 sl<g>\t%0,%2
5317 sl<y>\t%0,%2"
5318 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5319 (set_attr "cpu_facility" "*,z196,*,*")
5320 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5322 ; slr, sl, sly, slgr, slg, slrk, slgrk
5323 (define_insn "*sub<mode>3_cc"
5324 [(set (reg CC_REGNUM)
5325 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5326 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5327 (const_int 0)))
5328 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5329 (minus:GPR (match_dup 1) (match_dup 2)))]
5330 "s390_match_ccmode (insn, CCLmode)"
5331 "@
5332 sl<g>r\t%0,%2
5333 sl<g>rk\t%0,%1,%2
5334 sl<g>\t%0,%2
5335 sl<y>\t%0,%2"
5336 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5337 (set_attr "cpu_facility" "*,z196,*,*")
5338 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5340 ; slr, sl, sly, slgr, slg, slrk, slgrk
5341 (define_insn "*sub<mode>3_cc2"
5342 [(set (reg CC_REGNUM)
5343 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5344 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5345 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5346 (minus:GPR (match_dup 1) (match_dup 2)))]
5347 "s390_match_ccmode (insn, CCL3mode)"
5348 "@
5349 sl<g>r\t%0,%2
5350 sl<g>rk\t%0,%1,%2
5351 sl<g>\t%0,%2
5352 sl<y>\t%0,%2"
5353 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5354 (set_attr "cpu_facility" "*,z196,*,*")
5355 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5357 ; slr, sl, sly, slgr, slg, slrk, slgrk
5358 (define_insn "*sub<mode>3_cconly"
5359 [(set (reg CC_REGNUM)
5360 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5361 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5362 (const_int 0)))
5363 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5364 "s390_match_ccmode (insn, CCLmode)"
5365 "@
5366 sl<g>r\t%0,%2
5367 sl<g>rk\t%0,%1,%2
5368 sl<g>\t%0,%2
5369 sl<y>\t%0,%2"
5370 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5371 (set_attr "cpu_facility" "*,z196,*,*")
5372 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5375 ; slr, sl, sly, slgr, slg, slrk, slgrk
5376 (define_insn "*sub<mode>3_cconly2"
5377 [(set (reg CC_REGNUM)
5378 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5379 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5380 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5381 "s390_match_ccmode (insn, CCL3mode)"
5382 "@
5383 sl<g>r\t%0,%2
5384 sl<g>rk\t%0,%1,%2
5385 sl<g>\t%0,%2
5386 sl<y>\t%0,%2"
5387 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5388 (set_attr "cpu_facility" "*,z196,*,*")
5389 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5392 ;
5393 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5394 ;
5396 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5397 (define_insn "sub<mode>3"
5398 [(set (match_operand:FP 0 "register_operand" "=f, f")
5399 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5400 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5401 (clobber (reg:CC CC_REGNUM))]
5402 "TARGET_HARD_FLOAT"
5403 "@
5404 s<xde><bt>r\t%0,<op1>%2
5405 s<xde>b\t%0,%2"
5406 [(set_attr "op_type" "<RRer>,RXE")
5407 (set_attr "type" "fsimp<mode>")])
5409 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5410 (define_insn "*sub<mode>3_cc"
5411 [(set (reg CC_REGNUM)
5412 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5413 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5414 (match_operand:FP 3 "const0_operand" "")))
5415 (set (match_operand:FP 0 "register_operand" "=f,f")
5416 (minus:FP (match_dup 1) (match_dup 2)))]
5417 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5418 "@
5419 s<xde><bt>r\t%0,<op1>%2
5420 s<xde>b\t%0,%2"
5421 [(set_attr "op_type" "<RRer>,RXE")
5422 (set_attr "type" "fsimp<mode>")])
5424 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5425 (define_insn "*sub<mode>3_cconly"
5426 [(set (reg CC_REGNUM)
5427 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5428 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5429 (match_operand:FP 3 "const0_operand" "")))
5430 (clobber (match_scratch:FP 0 "=f,f"))]
5431 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5432 "@
5433 s<xde><bt>r\t%0,<op1>%2
5434 s<xde>b\t%0,%2"
5435 [(set_attr "op_type" "<RRer>,RXE")
5436 (set_attr "type" "fsimp<mode>")])
5439 ;;
5440 ;;- Conditional add/subtract instructions.
5441 ;;
5443 ;
5444 ; add(di|si)cc instruction pattern(s).
5445 ;
5447 ; the following 4 patterns are used when the result of an add with
5448 ; carry is checked for an overflow condition
5450 ; op1 + op2 + c < op1
5452 ; alcr, alc, alcgr, alcg
5453 (define_insn "*add<mode>3_alc_carry1_cc"
5454 [(set (reg CC_REGNUM)
5455 (compare
5456 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5457 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5458 (match_operand:GPR 2 "general_operand" "d,RT"))
5459 (match_dup 1)))
5460 (set (match_operand:GPR 0 "register_operand" "=d,d")
5461 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5462 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5463 "@
5464 alc<g>r\t%0,%2
5465 alc<g>\t%0,%2"
5466 [(set_attr "op_type" "RRE,RXY")
5467 (set_attr "z196prop" "z196_alone,z196_alone")])
5469 ; alcr, alc, alcgr, alcg
5470 (define_insn "*add<mode>3_alc_carry1_cconly"
5471 [(set (reg CC_REGNUM)
5472 (compare
5473 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5474 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5475 (match_operand:GPR 2 "general_operand" "d,RT"))
5476 (match_dup 1)))
5477 (clobber (match_scratch:GPR 0 "=d,d"))]
5478 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5479 "@
5480 alc<g>r\t%0,%2
5481 alc<g>\t%0,%2"
5482 [(set_attr "op_type" "RRE,RXY")
5483 (set_attr "z196prop" "z196_alone,z196_alone")])
5485 ; op1 + op2 + c < op2
5487 ; alcr, alc, alcgr, alcg
5488 (define_insn "*add<mode>3_alc_carry2_cc"
5489 [(set (reg CC_REGNUM)
5490 (compare
5491 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5492 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5493 (match_operand:GPR 2 "general_operand" "d,RT"))
5494 (match_dup 2)))
5495 (set (match_operand:GPR 0 "register_operand" "=d,d")
5496 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5497 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5498 "@
5499 alc<g>r\t%0,%2
5500 alc<g>\t%0,%2"
5501 [(set_attr "op_type" "RRE,RXY")])
5503 ; alcr, alc, alcgr, alcg
5504 (define_insn "*add<mode>3_alc_carry2_cconly"
5505 [(set (reg CC_REGNUM)
5506 (compare
5507 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5508 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5509 (match_operand:GPR 2 "general_operand" "d,RT"))
5510 (match_dup 2)))
5511 (clobber (match_scratch:GPR 0 "=d,d"))]
5512 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5513 "@
5514 alc<g>r\t%0,%2
5515 alc<g>\t%0,%2"
5516 [(set_attr "op_type" "RRE,RXY")])
5518 ; alcr, alc, alcgr, alcg
5519 (define_insn "*add<mode>3_alc_cc"
5520 [(set (reg CC_REGNUM)
5521 (compare
5522 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5523 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5524 (match_operand:GPR 2 "general_operand" "d,RT"))
5525 (const_int 0)))
5526 (set (match_operand:GPR 0 "register_operand" "=d,d")
5527 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5528 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5529 "@
5530 alc<g>r\t%0,%2
5531 alc<g>\t%0,%2"
5532 [(set_attr "op_type" "RRE,RXY")])
5534 ; alcr, alc, alcgr, alcg
5535 (define_insn "*add<mode>3_alc"
5536 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5537 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5538 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5539 (match_operand:GPR 2 "general_operand" "d,RT")))
5540 (clobber (reg:CC CC_REGNUM))]
5541 "TARGET_CPU_ZARCH"
5542 "@
5543 alc<g>r\t%0,%2
5544 alc<g>\t%0,%2"
5545 [(set_attr "op_type" "RRE,RXY")])
5547 ; slbr, slb, slbgr, slbg
5548 (define_insn "*sub<mode>3_slb_cc"
5549 [(set (reg CC_REGNUM)
5550 (compare
5551 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5552 (match_operand:GPR 2 "general_operand" "d,RT"))
5553 (match_operand:GPR 3 "s390_slb_comparison" ""))
5554 (const_int 0)))
5555 (set (match_operand:GPR 0 "register_operand" "=d,d")
5556 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5557 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5558 "@
5559 slb<g>r\t%0,%2
5560 slb<g>\t%0,%2"
5561 [(set_attr "op_type" "RRE,RXY")
5562 (set_attr "z10prop" "z10_c,*")])
5564 ; slbr, slb, slbgr, slbg
5565 (define_insn "*sub<mode>3_slb"
5566 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5567 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5568 (match_operand:GPR 2 "general_operand" "d,RT"))
5569 (match_operand:GPR 3 "s390_slb_comparison" "")))
5570 (clobber (reg:CC CC_REGNUM))]
5571 "TARGET_CPU_ZARCH"
5572 "@
5573 slb<g>r\t%0,%2
5574 slb<g>\t%0,%2"
5575 [(set_attr "op_type" "RRE,RXY")
5576 (set_attr "z10prop" "z10_c,*")])
5578 (define_expand "add<mode>cc"
5579 [(match_operand:GPR 0 "register_operand" "")
5580 (match_operand 1 "comparison_operator" "")
5581 (match_operand:GPR 2 "register_operand" "")
5582 (match_operand:GPR 3 "const_int_operand" "")]
5583 "TARGET_CPU_ZARCH"
5584 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5585 XEXP (operands[1], 0), XEXP (operands[1], 1),
5586 operands[0], operands[2],
5587 operands[3])) FAIL; DONE;")
5589 ;
5590 ; scond instruction pattern(s).
5591 ;
5593 (define_insn_and_split "*scond<mode>"
5594 [(set (match_operand:GPR 0 "register_operand" "=&d")
5595 (match_operand:GPR 1 "s390_alc_comparison" ""))
5596 (clobber (reg:CC CC_REGNUM))]
5597 "TARGET_CPU_ZARCH"
5598 "#"
5599 "&& reload_completed"
5600 [(set (match_dup 0) (const_int 0))
5601 (parallel
5602 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5603 (match_dup 0)))
5604 (clobber (reg:CC CC_REGNUM))])]
5605 "")
5607 (define_insn_and_split "*scond<mode>_neg"
5608 [(set (match_operand:GPR 0 "register_operand" "=&d")
5609 (match_operand:GPR 1 "s390_slb_comparison" ""))
5610 (clobber (reg:CC CC_REGNUM))]
5611 "TARGET_CPU_ZARCH"
5612 "#"
5613 "&& reload_completed"
5614 [(set (match_dup 0) (const_int 0))
5615 (parallel
5616 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5617 (match_dup 1)))
5618 (clobber (reg:CC CC_REGNUM))])
5619 (parallel
5620 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5621 (clobber (reg:CC CC_REGNUM))])]
5622 "")
5625 (define_expand "cstore<mode>4"
5626 [(set (match_operand:SI 0 "register_operand" "")
5627 (match_operator:SI 1 "s390_scond_operator"
5628 [(match_operand:GPR 2 "register_operand" "")
5629 (match_operand:GPR 3 "general_operand" "")]))]
5630 "TARGET_CPU_ZARCH"
5631 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5632 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5634 (define_expand "cstorecc4"
5635 [(parallel
5636 [(set (match_operand:SI 0 "register_operand" "")
5637 (match_operator:SI 1 "s390_eqne_operator"
5638 [(match_operand:CCZ1 2 "register_operand")
5639 (match_operand 3 "const0_operand")]))
5640 (clobber (reg:CC CC_REGNUM))])]
5641 ""
5642 "emit_insn (gen_sne (operands[0], operands[2]));
5643 if (GET_CODE (operands[1]) == EQ)
5644 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5645 DONE;")
5647 (define_insn_and_split "sne"
5648 [(set (match_operand:SI 0 "register_operand" "=d")
5649 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5650 (const_int 0)))
5651 (clobber (reg:CC CC_REGNUM))]
5652 ""
5653 "#"
5654 "reload_completed"
5655 [(parallel
5656 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5657 (clobber (reg:CC CC_REGNUM))])])
5660 ;;
5661 ;; - Conditional move instructions (introduced with z196)
5662 ;;
5664 (define_expand "mov<mode>cc"
5665 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5666 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5667 (match_operand:GPR 2 "nonimmediate_operand" "")
5668 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5669 "TARGET_Z196"
5670 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5671 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5673 ; locr, loc, stoc, locgr, locg, stocg
5674 (define_insn_and_split "*mov<mode>cc"
5675 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5676 (if_then_else:GPR
5677 (match_operator 1 "s390_comparison"
5678 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5679 (match_operand 5 "const_int_operand" "")])
5680 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5681 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5682 "TARGET_Z196"
5683 "@
5684 loc<g>r%C1\t%0,%3
5685 loc<g>r%D1\t%0,%4
5686 loc<g>%C1\t%0,%3
5687 loc<g>%D1\t%0,%4
5688 stoc<g>%C1\t%3,%0
5689 stoc<g>%D1\t%4,%0
5690 #"
5691 "&& reload_completed
5692 && MEM_P (operands[3]) && MEM_P (operands[4])"
5693 [(set (match_dup 0)
5694 (if_then_else:GPR
5695 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5696 (match_dup 3)
5697 (match_dup 0)))
5698 (set (match_dup 0)
5699 (if_then_else:GPR
5700 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5701 (match_dup 0)
5702 (match_dup 4)))]
5703 ""
5704 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5706 ;;
5707 ;;- Multiply instructions.
5708 ;;
5710 ;
5711 ; muldi3 instruction pattern(s).
5712 ;
5714 (define_insn "*muldi3_sign"
5715 [(set (match_operand:DI 0 "register_operand" "=d,d")
5716 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5717 (match_operand:DI 1 "register_operand" "0,0")))]
5718 "TARGET_ZARCH"
5719 "@
5720 msgfr\t%0,%2
5721 msgf\t%0,%2"
5722 [(set_attr "op_type" "RRE,RXY")
5723 (set_attr "type" "imuldi")])
5725 (define_insn "muldi3"
5726 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5727 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5728 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5729 "TARGET_ZARCH"
5730 "@
5731 msgr\t%0,%2
5732 mghi\t%0,%h2
5733 msg\t%0,%2
5734 msgfi\t%0,%2"
5735 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5736 (set_attr "type" "imuldi")
5737 (set_attr "cpu_facility" "*,*,*,z10")])
5739 ;
5740 ; mulsi3 instruction pattern(s).
5741 ;
5743 (define_insn "*mulsi3_sign"
5744 [(set (match_operand:SI 0 "register_operand" "=d,d")
5745 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5746 (match_operand:SI 1 "register_operand" "0,0")))]
5747 ""
5748 "@
5749 mh\t%0,%2
5750 mhy\t%0,%2"
5751 [(set_attr "op_type" "RX,RXY")
5752 (set_attr "type" "imulhi")
5753 (set_attr "cpu_facility" "*,z10")])
5755 (define_insn "mulsi3"
5756 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5757 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5758 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5759 ""
5760 "@
5761 msr\t%0,%2
5762 mhi\t%0,%h2
5763 ms\t%0,%2
5764 msy\t%0,%2
5765 msfi\t%0,%2"
5766 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5767 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5768 (set_attr "cpu_facility" "*,*,*,*,z10")])
5770 ;
5771 ; mulsidi3 instruction pattern(s).
5772 ;
5774 (define_insn "mulsidi3"
5775 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5776 (mult:DI (sign_extend:DI
5777 (match_operand:SI 1 "register_operand" "%0,0,0"))
5778 (sign_extend:DI
5779 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5780 "!TARGET_ZARCH"
5781 "@
5782 mr\t%0,%2
5783 m\t%0,%2
5784 mfy\t%0,%2"
5785 [(set_attr "op_type" "RR,RX,RXY")
5786 (set_attr "type" "imulsi")
5787 (set_attr "cpu_facility" "*,*,z10")])
5789 ;
5790 ; umul instruction pattern(s).
5791 ;
5793 ; mlr, ml, mlgr, mlg
5794 (define_insn "umul<dwh><mode>3"
5795 [(set (match_operand:DW 0 "register_operand" "=d, d")
5796 (mult:DW (zero_extend:DW
5797 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5798 (zero_extend:DW
5799 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5800 "TARGET_CPU_ZARCH"
5801 "@
5802 ml<tg>r\t%0,%2
5803 ml<tg>\t%0,%2"
5804 [(set_attr "op_type" "RRE,RXY")
5805 (set_attr "type" "imul<dwh>")])
5807 ;
5808 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5809 ;
5811 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5812 (define_insn "mul<mode>3"
5813 [(set (match_operand:FP 0 "register_operand" "=f,f")
5814 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5815 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5816 "TARGET_HARD_FLOAT"
5817 "@
5818 m<xdee><bt>r\t%0,<op1>%2
5819 m<xdee>b\t%0,%2"
5820 [(set_attr "op_type" "<RRer>,RXE")
5821 (set_attr "type" "fmul<mode>")])
5823 ; madbr, maebr, maxb, madb, maeb
5824 (define_insn "fma<mode>4"
5825 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5826 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5827 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5828 (match_operand:DSF 3 "register_operand" "0,0")))]
5829 "TARGET_HARD_FLOAT"
5830 "@
5831 ma<xde>br\t%0,%1,%2
5832 ma<xde>b\t%0,%1,%2"
5833 [(set_attr "op_type" "RRE,RXE")
5834 (set_attr "type" "fmadd<mode>")])
5836 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5837 (define_insn "fms<mode>4"
5838 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5839 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5840 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5841 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5842 "TARGET_HARD_FLOAT"
5843 "@
5844 ms<xde>br\t%0,%1,%2
5845 ms<xde>b\t%0,%1,%2"
5846 [(set_attr "op_type" "RRE,RXE")
5847 (set_attr "type" "fmadd<mode>")])
5849 ;;
5850 ;;- Divide and modulo instructions.
5851 ;;
5853 ;
5854 ; divmoddi4 instruction pattern(s).
5855 ;
5857 (define_expand "divmoddi4"
5858 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5859 (div:DI (match_operand:DI 1 "register_operand" "")
5860 (match_operand:DI 2 "general_operand" "")))
5861 (set (match_operand:DI 3 "general_operand" "")
5862 (mod:DI (match_dup 1) (match_dup 2)))])
5863 (clobber (match_dup 4))]
5864 "TARGET_ZARCH"
5865 {
5866 rtx insn, div_equal, mod_equal;
5868 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5869 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5871 operands[4] = gen_reg_rtx(TImode);
5872 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5874 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5875 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5877 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5878 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5880 DONE;
5881 })
5883 (define_insn "divmodtidi3"
5884 [(set (match_operand:TI 0 "register_operand" "=d,d")
5885 (ior:TI
5886 (ashift:TI
5887 (zero_extend:TI
5888 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5889 (match_operand:DI 2 "general_operand" "d,RT")))
5890 (const_int 64))
5891 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5892 "TARGET_ZARCH"
5893 "@
5894 dsgr\t%0,%2
5895 dsg\t%0,%2"
5896 [(set_attr "op_type" "RRE,RXY")
5897 (set_attr "type" "idiv")])
5899 (define_insn "divmodtisi3"
5900 [(set (match_operand:TI 0 "register_operand" "=d,d")
5901 (ior:TI
5902 (ashift:TI
5903 (zero_extend:TI
5904 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5905 (sign_extend:DI
5906 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5907 (const_int 64))
5908 (zero_extend:TI
5909 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5910 "TARGET_ZARCH"
5911 "@
5912 dsgfr\t%0,%2
5913 dsgf\t%0,%2"
5914 [(set_attr "op_type" "RRE,RXY")
5915 (set_attr "type" "idiv")])
5917 ;
5918 ; udivmoddi4 instruction pattern(s).
5919 ;
5921 (define_expand "udivmoddi4"
5922 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5923 (udiv:DI (match_operand:DI 1 "general_operand" "")
5924 (match_operand:DI 2 "nonimmediate_operand" "")))
5925 (set (match_operand:DI 3 "general_operand" "")
5926 (umod:DI (match_dup 1) (match_dup 2)))])
5927 (clobber (match_dup 4))]
5928 "TARGET_ZARCH"
5929 {
5930 rtx insn, div_equal, mod_equal, equal;
5932 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5933 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5934 equal = gen_rtx_IOR (TImode,
5935 gen_rtx_ASHIFT (TImode,
5936 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5937 GEN_INT (64)),
5938 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5940 operands[4] = gen_reg_rtx(TImode);
5941 emit_clobber (operands[4]);
5942 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5943 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5945 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5946 set_unique_reg_note (insn, REG_EQUAL, equal);
5948 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5949 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5951 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5952 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5954 DONE;
5955 })
5957 (define_insn "udivmodtidi3"
5958 [(set (match_operand:TI 0 "register_operand" "=d,d")
5959 (ior:TI
5960 (ashift:TI
5961 (zero_extend:TI
5962 (truncate:DI
5963 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5964 (zero_extend:TI
5965 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5966 (const_int 64))
5967 (zero_extend:TI
5968 (truncate:DI
5969 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5970 "TARGET_ZARCH"
5971 "@
5972 dlgr\t%0,%2
5973 dlg\t%0,%2"
5974 [(set_attr "op_type" "RRE,RXY")
5975 (set_attr "type" "idiv")])
5977 ;
5978 ; divmodsi4 instruction pattern(s).
5979 ;
5981 (define_expand "divmodsi4"
5982 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5983 (div:SI (match_operand:SI 1 "general_operand" "")
5984 (match_operand:SI 2 "nonimmediate_operand" "")))
5985 (set (match_operand:SI 3 "general_operand" "")
5986 (mod:SI (match_dup 1) (match_dup 2)))])
5987 (clobber (match_dup 4))]
5988 "!TARGET_ZARCH"
5989 {
5990 rtx insn, div_equal, mod_equal, equal;
5992 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5993 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5994 equal = gen_rtx_IOR (DImode,
5995 gen_rtx_ASHIFT (DImode,
5996 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5997 GEN_INT (32)),
5998 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6000 operands[4] = gen_reg_rtx(DImode);
6001 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6003 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6004 set_unique_reg_note (insn, REG_EQUAL, equal);
6006 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6007 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6009 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6010 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6012 DONE;
6013 })
6015 (define_insn "divmoddisi3"
6016 [(set (match_operand:DI 0 "register_operand" "=d,d")
6017 (ior:DI
6018 (ashift:DI
6019 (zero_extend:DI
6020 (truncate:SI
6021 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6022 (sign_extend:DI
6023 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6024 (const_int 32))
6025 (zero_extend:DI
6026 (truncate:SI
6027 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6028 "!TARGET_ZARCH"
6029 "@
6030 dr\t%0,%2
6031 d\t%0,%2"
6032 [(set_attr "op_type" "RR,RX")
6033 (set_attr "type" "idiv")])
6035 ;
6036 ; udivsi3 and umodsi3 instruction pattern(s).
6037 ;
6039 (define_expand "udivmodsi4"
6040 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6041 (udiv:SI (match_operand:SI 1 "general_operand" "")
6042 (match_operand:SI 2 "nonimmediate_operand" "")))
6043 (set (match_operand:SI 3 "general_operand" "")
6044 (umod:SI (match_dup 1) (match_dup 2)))])
6045 (clobber (match_dup 4))]
6046 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6047 {
6048 rtx insn, div_equal, mod_equal, equal;
6050 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6051 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6052 equal = gen_rtx_IOR (DImode,
6053 gen_rtx_ASHIFT (DImode,
6054 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6055 GEN_INT (32)),
6056 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6058 operands[4] = gen_reg_rtx(DImode);
6059 emit_clobber (operands[4]);
6060 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6061 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6063 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6064 set_unique_reg_note (insn, REG_EQUAL, equal);
6066 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6067 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6069 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6070 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6072 DONE;
6073 })
6075 (define_insn "udivmoddisi3"
6076 [(set (match_operand:DI 0 "register_operand" "=d,d")
6077 (ior:DI
6078 (ashift:DI
6079 (zero_extend:DI
6080 (truncate:SI
6081 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6082 (zero_extend:DI
6083 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6084 (const_int 32))
6085 (zero_extend:DI
6086 (truncate:SI
6087 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6088 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6089 "@
6090 dlr\t%0,%2
6091 dl\t%0,%2"
6092 [(set_attr "op_type" "RRE,RXY")
6093 (set_attr "type" "idiv")])
6095 (define_expand "udivsi3"
6096 [(set (match_operand:SI 0 "register_operand" "=d")
6097 (udiv:SI (match_operand:SI 1 "general_operand" "")
6098 (match_operand:SI 2 "general_operand" "")))
6099 (clobber (match_dup 3))]
6100 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6101 {
6102 rtx insn, udiv_equal, umod_equal, equal;
6104 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6105 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6106 equal = gen_rtx_IOR (DImode,
6107 gen_rtx_ASHIFT (DImode,
6108 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6109 GEN_INT (32)),
6110 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6112 operands[3] = gen_reg_rtx (DImode);
6114 if (CONSTANT_P (operands[2]))
6115 {
6116 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6117 {
6118 rtx label1 = gen_label_rtx ();
6120 operands[1] = make_safe_from (operands[1], operands[0]);
6121 emit_move_insn (operands[0], const0_rtx);
6122 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6123 SImode, 1, label1);
6124 emit_move_insn (operands[0], const1_rtx);
6125 emit_label (label1);
6126 }
6127 else
6128 {
6129 operands[2] = force_reg (SImode, operands[2]);
6130 operands[2] = make_safe_from (operands[2], operands[0]);
6132 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6133 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6134 operands[2]));
6135 set_unique_reg_note (insn, REG_EQUAL, equal);
6137 insn = emit_move_insn (operands[0],
6138 gen_lowpart (SImode, operands[3]));
6139 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6140 }
6141 }
6142 else
6143 {
6144 rtx label1 = gen_label_rtx ();
6145 rtx label2 = gen_label_rtx ();
6146 rtx label3 = gen_label_rtx ();
6148 operands[1] = force_reg (SImode, operands[1]);
6149 operands[1] = make_safe_from (operands[1], operands[0]);
6150 operands[2] = force_reg (SImode, operands[2]);
6151 operands[2] = make_safe_from (operands[2], operands[0]);
6153 emit_move_insn (operands[0], const0_rtx);
6154 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6155 SImode, 1, label3);
6156 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6157 SImode, 0, label2);
6158 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6159 SImode, 0, label1);
6160 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6161 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6162 operands[2]));
6163 set_unique_reg_note (insn, REG_EQUAL, equal);
6165 insn = emit_move_insn (operands[0],
6166 gen_lowpart (SImode, operands[3]));
6167 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6169 emit_jump (label3);
6170 emit_label (label1);
6171 emit_move_insn (operands[0], operands[1]);
6172 emit_jump (label3);
6173 emit_label (label2);
6174 emit_move_insn (operands[0], const1_rtx);
6175 emit_label (label3);
6176 }
6177 emit_move_insn (operands[0], operands[0]);
6178 DONE;
6179 })
6181 (define_expand "umodsi3"
6182 [(set (match_operand:SI 0 "register_operand" "=d")
6183 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6184 (match_operand:SI 2 "nonimmediate_operand" "")))
6185 (clobber (match_dup 3))]
6186 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6187 {
6188 rtx insn, udiv_equal, umod_equal, equal;
6190 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6191 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6192 equal = gen_rtx_IOR (DImode,
6193 gen_rtx_ASHIFT (DImode,
6194 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6195 GEN_INT (32)),
6196 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6198 operands[3] = gen_reg_rtx (DImode);
6200 if (CONSTANT_P (operands[2]))
6201 {
6202 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6203 {
6204 rtx label1 = gen_label_rtx ();
6206 operands[1] = make_safe_from (operands[1], operands[0]);
6207 emit_move_insn (operands[0], operands[1]);
6208 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6209 SImode, 1, label1);
6210 emit_insn (gen_abssi2 (operands[0], operands[2]));
6211 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6212 emit_label (label1);
6213 }
6214 else
6215 {
6216 operands[2] = force_reg (SImode, operands[2]);
6217 operands[2] = make_safe_from (operands[2], operands[0]);
6219 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6220 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6221 operands[2]));
6222 set_unique_reg_note (insn, REG_EQUAL, equal);
6224 insn = emit_move_insn (operands[0],
6225 gen_highpart (SImode, operands[3]));
6226 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6227 }
6228 }
6229 else
6230 {
6231 rtx label1 = gen_label_rtx ();
6232 rtx label2 = gen_label_rtx ();
6233 rtx label3 = gen_label_rtx ();
6235 operands[1] = force_reg (SImode, operands[1]);
6236 operands[1] = make_safe_from (operands[1], operands[0]);
6237 operands[2] = force_reg (SImode, operands[2]);
6238 operands[2] = make_safe_from (operands[2], operands[0]);
6240 emit_move_insn(operands[0], operands[1]);
6241 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6242 SImode, 1, label3);
6243 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6244 SImode, 0, label2);
6245 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6246 SImode, 0, label1);
6247 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6248 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6249 operands[2]));
6250 set_unique_reg_note (insn, REG_EQUAL, equal);
6252 insn = emit_move_insn (operands[0],
6253 gen_highpart (SImode, operands[3]));
6254 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6256 emit_jump (label3);
6257 emit_label (label1);
6258 emit_move_insn (operands[0], const0_rtx);
6259 emit_jump (label3);
6260 emit_label (label2);
6261 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6262 emit_label (label3);
6263 }
6264 DONE;
6265 })
6267 ;
6268 ; div(df|sf)3 instruction pattern(s).
6269 ;
6271 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6272 (define_insn "div<mode>3"
6273 [(set (match_operand:FP 0 "register_operand" "=f,f")
6274 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6275 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6276 "TARGET_HARD_FLOAT"
6277 "@
6278 d<xde><bt>r\t%0,<op1>%2
6279 d<xde>b\t%0,%2"
6280 [(set_attr "op_type" "<RRer>,RXE")
6281 (set_attr "type" "fdiv<mode>")])
6284 ;;
6285 ;;- And instructions.
6286 ;;
6288 (define_expand "and<mode>3"
6289 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6290 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6291 (match_operand:INT 2 "general_operand" "")))
6292 (clobber (reg:CC CC_REGNUM))]
6293 ""
6294 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6296 ;
6297 ; anddi3 instruction pattern(s).
6298 ;
6300 (define_insn "*anddi3_cc"
6301 [(set (reg CC_REGNUM)
6302 (compare
6303 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6304 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6305 (const_int 0)))
6306 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6307 (and:DI (match_dup 1) (match_dup 2)))]
6308 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6309 "@
6310 ngr\t%0,%2
6311 ngrk\t%0,%1,%2
6312 ng\t%0,%2
6313 risbg\t%0,%1,%s2,128+%e2,0"
6314 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6315 (set_attr "cpu_facility" "*,z196,*,z10")
6316 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6318 (define_insn "*anddi3_cconly"
6319 [(set (reg CC_REGNUM)
6320 (compare
6321 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6322 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6323 (const_int 0)))
6324 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6325 "TARGET_ZARCH
6326 && s390_match_ccmode(insn, CCTmode)
6327 /* Do not steal TM patterns. */
6328 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6329 "@
6330 ngr\t%0,%2
6331 ngrk\t%0,%1,%2
6332 ng\t%0,%2
6333 risbg\t%0,%1,%s2,128+%e2,0"
6334 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6335 (set_attr "cpu_facility" "*,z196,*,z10")
6336 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6338 (define_insn "*anddi3"
6339 [(set (match_operand:DI 0 "nonimmediate_operand"
6340 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6341 (and:DI
6342 (match_operand:DI 1 "nonimmediate_operand"
6343 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6344 (match_operand:DI 2 "general_operand"
6345 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6346 (clobber (reg:CC CC_REGNUM))]
6347 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6348 "@
6349 #
6350 #
6351 nihh\t%0,%j2
6352 nihl\t%0,%j2
6353 nilh\t%0,%j2
6354 nill\t%0,%j2
6355 nihf\t%0,%m2
6356 nilf\t%0,%m2
6357 ngr\t%0,%2
6358 ngrk\t%0,%1,%2
6359 ng\t%0,%2
6360 risbg\t%0,%1,%s2,128+%e2,0
6361 #
6362 #"
6363 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6364 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6365 (set_attr "z10prop" "*,
6366 *,
6367 z10_super_E1,
6368 z10_super_E1,
6369 z10_super_E1,
6370 z10_super_E1,
6371 z10_super_E1,
6372 z10_super_E1,
6373 z10_super_E1,
6374 *,
6375 z10_super_E1,
6376 z10_super_E1,
6377 *,
6378 *")])
6380 (define_split
6381 [(set (match_operand:DI 0 "s_operand" "")
6382 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6383 (clobber (reg:CC CC_REGNUM))]
6384 "reload_completed"
6385 [(parallel
6386 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6387 (clobber (reg:CC CC_REGNUM))])]
6388 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6390 ;; These two are what combine generates for (ashift (zero_extract)).
6391 (define_insn "*extzv_<mode>_srl"
6392 [(set (match_operand:GPR 0 "register_operand" "=d")
6393 (and:GPR (lshiftrt:GPR
6394 (match_operand:GPR 1 "register_operand" "d")
6395 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6396 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6397 (clobber (reg:CC CC_REGNUM))]
6398 "TARGET_Z10
6399 /* Note that even for the SImode pattern, the rotate is always DImode. */
6400 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6401 INTVAL (operands[3]))"
6402 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6403 [(set_attr "op_type" "RIE")
6404 (set_attr "z10prop" "z10_super_E1")])
6406 (define_insn "*extzv_<mode>_sll"
6407 [(set (match_operand:GPR 0 "register_operand" "=d")
6408 (and:GPR (ashift:GPR
6409 (match_operand:GPR 1 "register_operand" "d")
6410 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6411 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6412 (clobber (reg:CC CC_REGNUM))]
6413 "TARGET_Z10
6414 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6415 INTVAL (operands[3]))"
6416 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6417 [(set_attr "op_type" "RIE")
6418 (set_attr "z10prop" "z10_super_E1")])
6421 ;
6422 ; andsi3 instruction pattern(s).
6423 ;
6425 (define_insn "*andsi3_cc"
6426 [(set (reg CC_REGNUM)
6427 (compare
6428 (and:SI
6429 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6430 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6431 (const_int 0)))
6432 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6433 (and:SI (match_dup 1) (match_dup 2)))]
6434 "s390_match_ccmode(insn, CCTmode)"
6435 "@
6436 nilf\t%0,%o2
6437 nr\t%0,%2
6438 nrk\t%0,%1,%2
6439 n\t%0,%2
6440 ny\t%0,%2
6441 risbg\t%0,%1,%t2,128+%f2,0"
6442 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6443 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6444 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6445 z10_super_E1,z10_super_E1,z10_super_E1")])
6447 (define_insn "*andsi3_cconly"
6448 [(set (reg CC_REGNUM)
6449 (compare
6450 (and:SI
6451 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6452 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6453 (const_int 0)))
6454 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6455 "s390_match_ccmode(insn, CCTmode)
6456 /* Do not steal TM patterns. */
6457 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6458 "@
6459 nilf\t%0,%o2
6460 nr\t%0,%2
6461 nrk\t%0,%1,%2
6462 n\t%0,%2
6463 ny\t%0,%2
6464 risbg\t%0,%1,%t2,128+%f2,0"
6465 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6466 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6467 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6468 z10_super_E1,z10_super_E1,z10_super_E1")])
6470 (define_insn "*andsi3_zarch"
6471 [(set (match_operand:SI 0 "nonimmediate_operand"
6472 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6473 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6474 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6475 (match_operand:SI 2 "general_operand"
6476 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6477 (clobber (reg:CC CC_REGNUM))]
6478 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6479 "@
6480 #
6481 #
6482 nilh\t%0,%j2
6483 nill\t%0,%j2
6484 nilf\t%0,%o2
6485 nr\t%0,%2
6486 nrk\t%0,%1,%2
6487 n\t%0,%2
6488 ny\t%0,%2
6489 risbg\t%0,%1,%t2,128+%f2,0
6490 #
6491 #"
6492 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6493 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6494 (set_attr "z10prop" "*,
6495 *,
6496 z10_super_E1,
6497 z10_super_E1,
6498 z10_super_E1,
6499 z10_super_E1,
6500 *,
6501 z10_super_E1,
6502 z10_super_E1,
6503 z10_super_E1,
6504 *,
6505 *")])
6507 (define_insn "*andsi3_esa"
6508 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6509 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6510 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6511 (clobber (reg:CC CC_REGNUM))]
6512 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6513 "@
6514 nr\t%0,%2
6515 n\t%0,%2
6516 #
6517 #"
6518 [(set_attr "op_type" "RR,RX,SI,SS")
6519 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6522 (define_split
6523 [(set (match_operand:SI 0 "s_operand" "")
6524 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6525 (clobber (reg:CC CC_REGNUM))]
6526 "reload_completed"
6527 [(parallel
6528 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6529 (clobber (reg:CC CC_REGNUM))])]
6530 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6532 ;
6533 ; andhi3 instruction pattern(s).
6534 ;
6536 (define_insn "*andhi3_zarch"
6537 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6538 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6539 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6540 (clobber (reg:CC CC_REGNUM))]
6541 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6542 "@
6543 nr\t%0,%2
6544 nrk\t%0,%1,%2
6545 nill\t%0,%x2
6546 #
6547 #"
6548 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6549 (set_attr "cpu_facility" "*,z196,*,*,*")
6550 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6551 ])
6553 (define_insn "*andhi3_esa"
6554 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6555 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6556 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6557 (clobber (reg:CC CC_REGNUM))]
6558 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6559 "@
6560 nr\t%0,%2
6561 #
6562 #"
6563 [(set_attr "op_type" "RR,SI,SS")
6564 (set_attr "z10prop" "z10_super_E1,*,*")
6565 ])
6567 (define_split
6568 [(set (match_operand:HI 0 "s_operand" "")
6569 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6570 (clobber (reg:CC CC_REGNUM))]
6571 "reload_completed"
6572 [(parallel
6573 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6574 (clobber (reg:CC CC_REGNUM))])]
6575 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6577 ;
6578 ; andqi3 instruction pattern(s).
6579 ;
6581 (define_insn "*andqi3_zarch"
6582 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6583 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6584 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6585 (clobber (reg:CC CC_REGNUM))]
6586 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6587 "@
6588 nr\t%0,%2
6589 nrk\t%0,%1,%2
6590 nill\t%0,%b2
6591 ni\t%S0,%b2
6592 niy\t%S0,%b2
6593 #"
6594 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6595 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6596 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6598 (define_insn "*andqi3_esa"
6599 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6600 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6601 (match_operand:QI 2 "general_operand" "d,n,Q")))
6602 (clobber (reg:CC CC_REGNUM))]
6603 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6604 "@
6605 nr\t%0,%2
6606 ni\t%S0,%b2
6607 #"
6608 [(set_attr "op_type" "RR,SI,SS")
6609 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6611 ;
6612 ; Block and (NC) patterns.
6613 ;
6615 (define_insn "*nc"
6616 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6617 (and:BLK (match_dup 0)
6618 (match_operand:BLK 1 "memory_operand" "Q")))
6619 (use (match_operand 2 "const_int_operand" "n"))
6620 (clobber (reg:CC CC_REGNUM))]
6621 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6622 "nc\t%O0(%2,%R0),%S1"
6623 [(set_attr "op_type" "SS")
6624 (set_attr "z196prop" "z196_cracked")])
6626 (define_split
6627 [(set (match_operand 0 "memory_operand" "")
6628 (and (match_dup 0)
6629 (match_operand 1 "memory_operand" "")))
6630 (clobber (reg:CC CC_REGNUM))]
6631 "reload_completed
6632 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6633 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6634 [(parallel
6635 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6636 (use (match_dup 2))
6637 (clobber (reg:CC CC_REGNUM))])]
6638 {
6639 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6640 operands[0] = adjust_address (operands[0], BLKmode, 0);
6641 operands[1] = adjust_address (operands[1], BLKmode, 0);
6642 })
6644 (define_peephole2
6645 [(parallel
6646 [(set (match_operand:BLK 0 "memory_operand" "")
6647 (and:BLK (match_dup 0)
6648 (match_operand:BLK 1 "memory_operand" "")))
6649 (use (match_operand 2 "const_int_operand" ""))
6650 (clobber (reg:CC CC_REGNUM))])
6651 (parallel
6652 [(set (match_operand:BLK 3 "memory_operand" "")
6653 (and:BLK (match_dup 3)
6654 (match_operand:BLK 4 "memory_operand" "")))
6655 (use (match_operand 5 "const_int_operand" ""))
6656 (clobber (reg:CC CC_REGNUM))])]
6657 "s390_offset_p (operands[0], operands[3], operands[2])
6658 && s390_offset_p (operands[1], operands[4], operands[2])
6659 && !s390_overlap_p (operands[0], operands[1],
6660 INTVAL (operands[2]) + INTVAL (operands[5]))
6661 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6662 [(parallel
6663 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6664 (use (match_dup 8))
6665 (clobber (reg:CC CC_REGNUM))])]
6666 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6667 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6668 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6671 ;;
6672 ;;- Bit set (inclusive or) instructions.
6673 ;;
6675 (define_expand "ior<mode>3"
6676 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6677 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6678 (match_operand:INT 2 "general_operand" "")))
6679 (clobber (reg:CC CC_REGNUM))]
6680 ""
6681 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6683 ;
6684 ; iordi3 instruction pattern(s).
6685 ;
6687 (define_insn "*iordi3_cc"
6688 [(set (reg CC_REGNUM)
6689 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6690 (match_operand:DI 2 "general_operand" " d,d,RT"))
6691 (const_int 0)))
6692 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6693 (ior:DI (match_dup 1) (match_dup 2)))]
6694 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6695 "@
6696 ogr\t%0,%2
6697 ogrk\t%0,%1,%2
6698 og\t%0,%2"
6699 [(set_attr "op_type" "RRE,RRF,RXY")
6700 (set_attr "cpu_facility" "*,z196,*")
6701 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6703 (define_insn "*iordi3_cconly"
6704 [(set (reg CC_REGNUM)
6705 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6706 (match_operand:DI 2 "general_operand" " d,d,RT"))
6707 (const_int 0)))
6708 (clobber (match_scratch:DI 0 "=d,d,d"))]
6709 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6710 "@
6711 ogr\t%0,%2
6712 ogrk\t%0,%1,%2
6713 og\t%0,%2"
6714 [(set_attr "op_type" "RRE,RRF,RXY")
6715 (set_attr "cpu_facility" "*,z196,*")
6716 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6718 (define_insn "*iordi3"
6719 [(set (match_operand:DI 0 "nonimmediate_operand"
6720 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6721 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6722 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6723 (match_operand:DI 2 "general_operand"
6724 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6725 (clobber (reg:CC CC_REGNUM))]
6726 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6727 "@
6728 oihh\t%0,%i2
6729 oihl\t%0,%i2
6730 oilh\t%0,%i2
6731 oill\t%0,%i2
6732 oihf\t%0,%k2
6733 oilf\t%0,%k2
6734 ogr\t%0,%2
6735 ogrk\t%0,%1,%2
6736 og\t%0,%2
6737 #
6738 #"
6739 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6740 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6741 (set_attr "z10prop" "z10_super_E1,
6742 z10_super_E1,
6743 z10_super_E1,
6744 z10_super_E1,
6745 z10_super_E1,
6746 z10_super_E1,
6747 z10_super_E1,
6748 *,
6749 z10_super_E1,
6750 *,
6751 *")])
6753 (define_split
6754 [(set (match_operand:DI 0 "s_operand" "")
6755 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6756 (clobber (reg:CC CC_REGNUM))]
6757 "reload_completed"
6758 [(parallel
6759 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6760 (clobber (reg:CC CC_REGNUM))])]
6761 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6763 ;
6764 ; iorsi3 instruction pattern(s).
6765 ;
6767 (define_insn "*iorsi3_cc"
6768 [(set (reg CC_REGNUM)
6769 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6770 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6771 (const_int 0)))
6772 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6773 (ior:SI (match_dup 1) (match_dup 2)))]
6774 "s390_match_ccmode(insn, CCTmode)"
6775 "@
6776 oilf\t%0,%o2
6777 or\t%0,%2
6778 ork\t%0,%1,%2
6779 o\t%0,%2
6780 oy\t%0,%2"
6781 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6782 (set_attr "cpu_facility" "*,*,z196,*,*")
6783 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6785 (define_insn "*iorsi3_cconly"
6786 [(set (reg CC_REGNUM)
6787 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6788 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6789 (const_int 0)))
6790 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6791 "s390_match_ccmode(insn, CCTmode)"
6792 "@
6793 oilf\t%0,%o2
6794 or\t%0,%2
6795 ork\t%0,%1,%2
6796 o\t%0,%2
6797 oy\t%0,%2"
6798 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6799 (set_attr "cpu_facility" "*,*,z196,*,*")
6800 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6802 (define_insn "*iorsi3_zarch"
6803 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6804 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6805 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6806 (clobber (reg:CC CC_REGNUM))]
6807 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6808 "@
6809 oilh\t%0,%i2
6810 oill\t%0,%i2
6811 oilf\t%0,%o2
6812 or\t%0,%2
6813 ork\t%0,%1,%2
6814 o\t%0,%2
6815 oy\t%0,%2
6816 #
6817 #"
6818 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6819 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6820 (set_attr "z10prop" "z10_super_E1,
6821 z10_super_E1,
6822 z10_super_E1,
6823 z10_super_E1,
6824 *,
6825 z10_super_E1,
6826 z10_super_E1,
6827 *,
6828 *")])
6830 (define_insn "*iorsi3_esa"
6831 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6832 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6833 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6834 (clobber (reg:CC CC_REGNUM))]
6835 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6836 "@
6837 or\t%0,%2
6838 o\t%0,%2
6839 #
6840 #"
6841 [(set_attr "op_type" "RR,RX,SI,SS")
6842 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6844 (define_split
6845 [(set (match_operand:SI 0 "s_operand" "")
6846 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6847 (clobber (reg:CC CC_REGNUM))]
6848 "reload_completed"
6849 [(parallel
6850 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6851 (clobber (reg:CC CC_REGNUM))])]
6852 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6854 ;
6855 ; iorhi3 instruction pattern(s).
6856 ;
6858 (define_insn "*iorhi3_zarch"
6859 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6860 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6861 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6862 (clobber (reg:CC CC_REGNUM))]
6863 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6864 "@
6865 or\t%0,%2
6866 ork\t%0,%1,%2
6867 oill\t%0,%x2
6868 #
6869 #"
6870 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6871 (set_attr "cpu_facility" "*,z196,*,*,*")
6872 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6874 (define_insn "*iorhi3_esa"
6875 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6876 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6877 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6878 (clobber (reg:CC CC_REGNUM))]
6879 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6880 "@
6881 or\t%0,%2
6882 #
6883 #"
6884 [(set_attr "op_type" "RR,SI,SS")
6885 (set_attr "z10prop" "z10_super_E1,*,*")])
6887 (define_split
6888 [(set (match_operand:HI 0 "s_operand" "")
6889 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6890 (clobber (reg:CC CC_REGNUM))]
6891 "reload_completed"
6892 [(parallel
6893 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6894 (clobber (reg:CC CC_REGNUM))])]
6895 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6897 ;
6898 ; iorqi3 instruction pattern(s).
6899 ;
6901 (define_insn "*iorqi3_zarch"
6902 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6903 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6904 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6905 (clobber (reg:CC CC_REGNUM))]
6906 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6907 "@
6908 or\t%0,%2
6909 ork\t%0,%1,%2
6910 oill\t%0,%b2
6911 oi\t%S0,%b2
6912 oiy\t%S0,%b2
6913 #"
6914 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6915 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6916 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6917 z10_super,z10_super,*")])
6919 (define_insn "*iorqi3_esa"
6920 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6921 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6922 (match_operand:QI 2 "general_operand" "d,n,Q")))
6923 (clobber (reg:CC CC_REGNUM))]
6924 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6925 "@
6926 or\t%0,%2
6927 oi\t%S0,%b2
6928 #"
6929 [(set_attr "op_type" "RR,SI,SS")
6930 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6932 ;
6933 ; Block inclusive or (OC) patterns.
6934 ;
6936 (define_insn "*oc"
6937 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6938 (ior:BLK (match_dup 0)
6939 (match_operand:BLK 1 "memory_operand" "Q")))
6940 (use (match_operand 2 "const_int_operand" "n"))
6941 (clobber (reg:CC CC_REGNUM))]
6942 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6943 "oc\t%O0(%2,%R0),%S1"
6944 [(set_attr "op_type" "SS")
6945 (set_attr "z196prop" "z196_cracked")])
6947 (define_split
6948 [(set (match_operand 0 "memory_operand" "")
6949 (ior (match_dup 0)
6950 (match_operand 1 "memory_operand" "")))
6951 (clobber (reg:CC CC_REGNUM))]
6952 "reload_completed
6953 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6954 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6955 [(parallel
6956 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6957 (use (match_dup 2))
6958 (clobber (reg:CC CC_REGNUM))])]
6959 {
6960 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6961 operands[0] = adjust_address (operands[0], BLKmode, 0);
6962 operands[1] = adjust_address (operands[1], BLKmode, 0);
6963 })
6965 (define_peephole2
6966 [(parallel
6967 [(set (match_operand:BLK 0 "memory_operand" "")
6968 (ior:BLK (match_dup 0)
6969 (match_operand:BLK 1 "memory_operand" "")))
6970 (use (match_operand 2 "const_int_operand" ""))
6971 (clobber (reg:CC CC_REGNUM))])
6972 (parallel
6973 [(set (match_operand:BLK 3 "memory_operand" "")
6974 (ior:BLK (match_dup 3)
6975 (match_operand:BLK 4 "memory_operand" "")))
6976 (use (match_operand 5 "const_int_operand" ""))
6977 (clobber (reg:CC CC_REGNUM))])]
6978 "s390_offset_p (operands[0], operands[3], operands[2])
6979 && s390_offset_p (operands[1], operands[4], operands[2])
6980 && !s390_overlap_p (operands[0], operands[1],
6981 INTVAL (operands[2]) + INTVAL (operands[5]))
6982 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6983 [(parallel
6984 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6985 (use (match_dup 8))
6986 (clobber (reg:CC CC_REGNUM))])]
6987 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6988 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6989 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6992 ;;
6993 ;;- Xor instructions.
6994 ;;
6996 (define_expand "xor<mode>3"
6997 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6998 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6999 (match_operand:INT 2 "general_operand" "")))
7000 (clobber (reg:CC CC_REGNUM))]
7001 ""
7002 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7004 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7005 ; simplifications. So its better to have something matching.
7006 (define_split
7007 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7008 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7009 ""
7010 [(parallel
7011 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7012 (clobber (reg:CC CC_REGNUM))])]
7013 {
7014 operands[2] = constm1_rtx;
7015 if (!s390_logical_operator_ok_p (operands))
7016 FAIL;
7017 })
7019 ;
7020 ; xordi3 instruction pattern(s).
7021 ;
7023 (define_insn "*xordi3_cc"
7024 [(set (reg CC_REGNUM)
7025 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7026 (match_operand:DI 2 "general_operand" " d,d,RT"))
7027 (const_int 0)))
7028 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7029 (xor:DI (match_dup 1) (match_dup 2)))]
7030 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7031 "@
7032 xgr\t%0,%2
7033 xgrk\t%0,%1,%2
7034 xg\t%0,%2"
7035 [(set_attr "op_type" "RRE,RRF,RXY")
7036 (set_attr "cpu_facility" "*,z196,*")
7037 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7039 (define_insn "*xordi3_cconly"
7040 [(set (reg CC_REGNUM)
7041 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7042 (match_operand:DI 2 "general_operand" " d,d,RT"))
7043 (const_int 0)))
7044 (clobber (match_scratch:DI 0 "=d,d, d"))]
7045 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7046 "@
7047 xgr\t%0,%2
7048 xgrk\t%0,%1,%2
7049 xg\t%0,%2"
7050 [(set_attr "op_type" "RRE,RRF,RXY")
7051 (set_attr "cpu_facility" "*,z196,*")
7052 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7054 (define_insn "*xordi3"
7055 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7056 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7057 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7058 (clobber (reg:CC CC_REGNUM))]
7059 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7060 "@
7061 xihf\t%0,%k2
7062 xilf\t%0,%k2
7063 xgr\t%0,%2
7064 xgrk\t%0,%1,%2
7065 xg\t%0,%2
7066 #
7067 #"
7068 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7069 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7070 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7071 *,z10_super_E1,*,*")])
7073 (define_split
7074 [(set (match_operand:DI 0 "s_operand" "")
7075 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7076 (clobber (reg:CC CC_REGNUM))]
7077 "reload_completed"
7078 [(parallel
7079 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7080 (clobber (reg:CC CC_REGNUM))])]
7081 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7083 ;
7084 ; xorsi3 instruction pattern(s).
7085 ;
7087 (define_insn "*xorsi3_cc"
7088 [(set (reg CC_REGNUM)
7089 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7090 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7091 (const_int 0)))
7092 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7093 (xor:SI (match_dup 1) (match_dup 2)))]
7094 "s390_match_ccmode(insn, CCTmode)"
7095 "@
7096 xilf\t%0,%o2
7097 xr\t%0,%2
7098 xrk\t%0,%1,%2
7099 x\t%0,%2
7100 xy\t%0,%2"
7101 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7102 (set_attr "cpu_facility" "*,*,z196,*,*")
7103 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7104 z10_super_E1,z10_super_E1")])
7106 (define_insn "*xorsi3_cconly"
7107 [(set (reg CC_REGNUM)
7108 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7109 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7110 (const_int 0)))
7111 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7112 "s390_match_ccmode(insn, CCTmode)"
7113 "@
7114 xilf\t%0,%o2
7115 xr\t%0,%2
7116 xrk\t%0,%1,%2
7117 x\t%0,%2
7118 xy\t%0,%2"
7119 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7120 (set_attr "cpu_facility" "*,*,z196,*,*")
7121 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7122 z10_super_E1,z10_super_E1")])
7124 (define_insn "*xorsi3"
7125 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7126 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7127 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7128 (clobber (reg:CC CC_REGNUM))]
7129 "s390_logical_operator_ok_p (operands)"
7130 "@
7131 xilf\t%0,%o2
7132 xr\t%0,%2
7133 xrk\t%0,%1,%2
7134 x\t%0,%2
7135 xy\t%0,%2
7136 #
7137 #"
7138 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7139 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7140 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7141 z10_super_E1,z10_super_E1,*,*")])
7143 (define_split
7144 [(set (match_operand:SI 0 "s_operand" "")
7145 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7146 (clobber (reg:CC CC_REGNUM))]
7147 "reload_completed"
7148 [(parallel
7149 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7150 (clobber (reg:CC CC_REGNUM))])]
7151 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7153 ;
7154 ; xorhi3 instruction pattern(s).
7155 ;
7157 (define_insn "*xorhi3"
7158 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7159 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7160 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7161 (clobber (reg:CC CC_REGNUM))]
7162 "s390_logical_operator_ok_p (operands)"
7163 "@
7164 xilf\t%0,%x2
7165 xr\t%0,%2
7166 xrk\t%0,%1,%2
7167 #
7168 #"
7169 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7170 (set_attr "cpu_facility" "*,*,z196,*,*")
7171 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7173 (define_split
7174 [(set (match_operand:HI 0 "s_operand" "")
7175 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7176 (clobber (reg:CC CC_REGNUM))]
7177 "reload_completed"
7178 [(parallel
7179 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7180 (clobber (reg:CC CC_REGNUM))])]
7181 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7183 ;
7184 ; xorqi3 instruction pattern(s).
7185 ;
7187 (define_insn "*xorqi3"
7188 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7189 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7190 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7191 (clobber (reg:CC CC_REGNUM))]
7192 "s390_logical_operator_ok_p (operands)"
7193 "@
7194 xilf\t%0,%b2
7195 xr\t%0,%2
7196 xrk\t%0,%1,%2
7197 xi\t%S0,%b2
7198 xiy\t%S0,%b2
7199 #"
7200 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7201 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7202 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7205 ;
7206 ; Block exclusive or (XC) patterns.
7207 ;
7209 (define_insn "*xc"
7210 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7211 (xor:BLK (match_dup 0)
7212 (match_operand:BLK 1 "memory_operand" "Q")))
7213 (use (match_operand 2 "const_int_operand" "n"))
7214 (clobber (reg:CC CC_REGNUM))]
7215 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7216 "xc\t%O0(%2,%R0),%S1"
7217 [(set_attr "op_type" "SS")])
7219 (define_split
7220 [(set (match_operand 0 "memory_operand" "")
7221 (xor (match_dup 0)
7222 (match_operand 1 "memory_operand" "")))
7223 (clobber (reg:CC CC_REGNUM))]
7224 "reload_completed
7225 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7226 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7227 [(parallel
7228 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7229 (use (match_dup 2))
7230 (clobber (reg:CC CC_REGNUM))])]
7231 {
7232 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7233 operands[0] = adjust_address (operands[0], BLKmode, 0);
7234 operands[1] = adjust_address (operands[1], BLKmode, 0);
7235 })
7237 (define_peephole2
7238 [(parallel
7239 [(set (match_operand:BLK 0 "memory_operand" "")
7240 (xor:BLK (match_dup 0)
7241 (match_operand:BLK 1 "memory_operand" "")))
7242 (use (match_operand 2 "const_int_operand" ""))
7243 (clobber (reg:CC CC_REGNUM))])
7244 (parallel
7245 [(set (match_operand:BLK 3 "memory_operand" "")
7246 (xor:BLK (match_dup 3)
7247 (match_operand:BLK 4 "memory_operand" "")))
7248 (use (match_operand 5 "const_int_operand" ""))
7249 (clobber (reg:CC CC_REGNUM))])]
7250 "s390_offset_p (operands[0], operands[3], operands[2])
7251 && s390_offset_p (operands[1], operands[4], operands[2])
7252 && !s390_overlap_p (operands[0], operands[1],
7253 INTVAL (operands[2]) + INTVAL (operands[5]))
7254 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7255 [(parallel
7256 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7257 (use (match_dup 8))
7258 (clobber (reg:CC CC_REGNUM))])]
7259 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7260 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7261 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7263 ;
7264 ; Block xor (XC) patterns with src == dest.
7265 ;
7267 (define_insn "*xc_zero"
7268 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7269 (const_int 0))
7270 (use (match_operand 1 "const_int_operand" "n"))
7271 (clobber (reg:CC CC_REGNUM))]
7272 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7273 "xc\t%O0(%1,%R0),%S0"
7274 [(set_attr "op_type" "SS")
7275 (set_attr "z196prop" "z196_cracked")])
7277 (define_peephole2
7278 [(parallel
7279 [(set (match_operand:BLK 0 "memory_operand" "")
7280 (const_int 0))
7281 (use (match_operand 1 "const_int_operand" ""))
7282 (clobber (reg:CC CC_REGNUM))])
7283 (parallel
7284 [(set (match_operand:BLK 2 "memory_operand" "")
7285 (const_int 0))
7286 (use (match_operand 3 "const_int_operand" ""))
7287 (clobber (reg:CC CC_REGNUM))])]
7288 "s390_offset_p (operands[0], operands[2], operands[1])
7289 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7290 [(parallel
7291 [(set (match_dup 4) (const_int 0))
7292 (use (match_dup 5))
7293 (clobber (reg:CC CC_REGNUM))])]
7294 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7295 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7298 ;;
7299 ;;- Negate instructions.
7300 ;;
7302 ;
7303 ; neg(di|si)2 instruction pattern(s).
7304 ;
7306 (define_expand "neg<mode>2"
7307 [(parallel
7308 [(set (match_operand:DSI 0 "register_operand" "=d")
7309 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7310 (clobber (reg:CC CC_REGNUM))])]
7311 ""
7312 "")
7314 (define_insn "*negdi2_sign_cc"
7315 [(set (reg CC_REGNUM)
7316 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7317 (match_operand:SI 1 "register_operand" "d") 0)
7318 (const_int 32)) (const_int 32)))
7319 (const_int 0)))
7320 (set (match_operand:DI 0 "register_operand" "=d")
7321 (neg:DI (sign_extend:DI (match_dup 1))))]
7322 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7323 "lcgfr\t%0,%1"
7324 [(set_attr "op_type" "RRE")
7325 (set_attr "z10prop" "z10_c")])
7327 (define_insn "*negdi2_sign"
7328 [(set (match_operand:DI 0 "register_operand" "=d")
7329 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7330 (clobber (reg:CC CC_REGNUM))]
7331 "TARGET_ZARCH"
7332 "lcgfr\t%0,%1"
7333 [(set_attr "op_type" "RRE")
7334 (set_attr "z10prop" "z10_c")])
7336 ; lcr, lcgr
7337 (define_insn "*neg<mode>2_cc"
7338 [(set (reg CC_REGNUM)
7339 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7340 (const_int 0)))
7341 (set (match_operand:GPR 0 "register_operand" "=d")
7342 (neg:GPR (match_dup 1)))]
7343 "s390_match_ccmode (insn, CCAmode)"
7344 "lc<g>r\t%0,%1"
7345 [(set_attr "op_type" "RR<E>")
7346 (set_attr "z10prop" "z10_super_c_E1")])
7348 ; lcr, lcgr
7349 (define_insn "*neg<mode>2_cconly"
7350 [(set (reg CC_REGNUM)
7351 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7352 (const_int 0)))
7353 (clobber (match_scratch:GPR 0 "=d"))]
7354 "s390_match_ccmode (insn, CCAmode)"
7355 "lc<g>r\t%0,%1"
7356 [(set_attr "op_type" "RR<E>")
7357 (set_attr "z10prop" "z10_super_c_E1")])
7359 ; lcr, lcgr
7360 (define_insn "*neg<mode>2"
7361 [(set (match_operand:GPR 0 "register_operand" "=d")
7362 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7363 (clobber (reg:CC CC_REGNUM))]
7364 ""
7365 "lc<g>r\t%0,%1"
7366 [(set_attr "op_type" "RR<E>")
7367 (set_attr "z10prop" "z10_super_c_E1")])
7369 (define_insn_and_split "*negdi2_31"
7370 [(set (match_operand:DI 0 "register_operand" "=d")
7371 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7372 (clobber (reg:CC CC_REGNUM))]
7373 "!TARGET_ZARCH"
7374 "#"
7375 "&& reload_completed"
7376 [(parallel
7377 [(set (match_dup 2) (neg:SI (match_dup 3)))
7378 (clobber (reg:CC CC_REGNUM))])
7379 (parallel
7380 [(set (reg:CCAP CC_REGNUM)
7381 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7382 (set (match_dup 4) (neg:SI (match_dup 5)))])
7383 (set (pc)
7384 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7385 (pc)
7386 (label_ref (match_dup 6))))
7387 (parallel
7388 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7389 (clobber (reg:CC CC_REGNUM))])
7390 (match_dup 6)]
7391 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7392 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7393 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7394 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7395 operands[6] = gen_label_rtx ();")
7397 ;
7398 ; neg(df|sf)2 instruction pattern(s).
7399 ;
7401 (define_expand "neg<mode>2"
7402 [(parallel
7403 [(set (match_operand:BFP 0 "register_operand" "=f")
7404 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7405 (clobber (reg:CC CC_REGNUM))])]
7406 "TARGET_HARD_FLOAT"
7407 "")
7409 ; lcxbr, lcdbr, lcebr
7410 (define_insn "*neg<mode>2_cc"
7411 [(set (reg CC_REGNUM)
7412 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7413 (match_operand:BFP 2 "const0_operand" "")))
7414 (set (match_operand:BFP 0 "register_operand" "=f")
7415 (neg:BFP (match_dup 1)))]
7416 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7417 "lc<xde>br\t%0,%1"
7418 [(set_attr "op_type" "RRE")
7419 (set_attr "type" "fsimp<mode>")])
7421 ; lcxbr, lcdbr, lcebr
7422 (define_insn "*neg<mode>2_cconly"
7423 [(set (reg CC_REGNUM)
7424 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7425 (match_operand:BFP 2 "const0_operand" "")))
7426 (clobber (match_scratch:BFP 0 "=f"))]
7427 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7428 "lc<xde>br\t%0,%1"
7429 [(set_attr "op_type" "RRE")
7430 (set_attr "type" "fsimp<mode>")])
7432 ; lcdfr
7433 (define_insn "*neg<mode>2_nocc"
7434 [(set (match_operand:FP 0 "register_operand" "=f")
7435 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7436 "TARGET_DFP"
7437 "lcdfr\t%0,%1"
7438 [(set_attr "op_type" "RRE")
7439 (set_attr "type" "fsimp<mode>")])
7441 ; lcxbr, lcdbr, lcebr
7442 (define_insn "*neg<mode>2"
7443 [(set (match_operand:BFP 0 "register_operand" "=f")
7444 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7445 (clobber (reg:CC CC_REGNUM))]
7446 "TARGET_HARD_FLOAT"
7447 "lc<xde>br\t%0,%1"
7448 [(set_attr "op_type" "RRE")
7449 (set_attr "type" "fsimp<mode>")])
7452 ;;
7453 ;;- Absolute value instructions.
7454 ;;
7456 ;
7457 ; abs(di|si)2 instruction pattern(s).
7458 ;
7460 (define_insn "*absdi2_sign_cc"
7461 [(set (reg CC_REGNUM)
7462 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7463 (match_operand:SI 1 "register_operand" "d") 0)
7464 (const_int 32)) (const_int 32)))
7465 (const_int 0)))
7466 (set (match_operand:DI 0 "register_operand" "=d")
7467 (abs:DI (sign_extend:DI (match_dup 1))))]
7468 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7469 "lpgfr\t%0,%1"
7470 [(set_attr "op_type" "RRE")
7471 (set_attr "z10prop" "z10_c")])
7473 (define_insn "*absdi2_sign"
7474 [(set (match_operand:DI 0 "register_operand" "=d")
7475 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7476 (clobber (reg:CC CC_REGNUM))]
7477 "TARGET_ZARCH"
7478 "lpgfr\t%0,%1"
7479 [(set_attr "op_type" "RRE")
7480 (set_attr "z10prop" "z10_c")])
7482 ; lpr, lpgr
7483 (define_insn "*abs<mode>2_cc"
7484 [(set (reg CC_REGNUM)
7485 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7486 (const_int 0)))
7487 (set (match_operand:GPR 0 "register_operand" "=d")
7488 (abs:GPR (match_dup 1)))]
7489 "s390_match_ccmode (insn, CCAmode)"
7490 "lp<g>r\t%0,%1"
7491 [(set_attr "op_type" "RR<E>")
7492 (set_attr "z10prop" "z10_c")])
7494 ; lpr, lpgr
7495 (define_insn "*abs<mode>2_cconly"
7496 [(set (reg CC_REGNUM)
7497 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7498 (const_int 0)))
7499 (clobber (match_scratch:GPR 0 "=d"))]
7500 "s390_match_ccmode (insn, CCAmode)"
7501 "lp<g>r\t%0,%1"
7502 [(set_attr "op_type" "RR<E>")
7503 (set_attr "z10prop" "z10_c")])
7505 ; lpr, lpgr
7506 (define_insn "abs<mode>2"
7507 [(set (match_operand:GPR 0 "register_operand" "=d")
7508 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7509 (clobber (reg:CC CC_REGNUM))]
7510 ""
7511 "lp<g>r\t%0,%1"
7512 [(set_attr "op_type" "RR<E>")
7513 (set_attr "z10prop" "z10_c")])
7515 ;
7516 ; abs(df|sf)2 instruction pattern(s).
7517 ;
7519 (define_expand "abs<mode>2"
7520 [(parallel
7521 [(set (match_operand:BFP 0 "register_operand" "=f")
7522 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7523 (clobber (reg:CC CC_REGNUM))])]
7524 "TARGET_HARD_FLOAT"
7525 "")
7527 ; lpxbr, lpdbr, lpebr
7528 (define_insn "*abs<mode>2_cc"
7529 [(set (reg CC_REGNUM)
7530 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7531 (match_operand:BFP 2 "const0_operand" "")))
7532 (set (match_operand:BFP 0 "register_operand" "=f")
7533 (abs:BFP (match_dup 1)))]
7534 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7535 "lp<xde>br\t%0,%1"
7536 [(set_attr "op_type" "RRE")
7537 (set_attr "type" "fsimp<mode>")])
7539 ; lpxbr, lpdbr, lpebr
7540 (define_insn "*abs<mode>2_cconly"
7541 [(set (reg CC_REGNUM)
7542 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7543 (match_operand:BFP 2 "const0_operand" "")))
7544 (clobber (match_scratch:BFP 0 "=f"))]
7545 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7546 "lp<xde>br\t%0,%1"
7547 [(set_attr "op_type" "RRE")
7548 (set_attr "type" "fsimp<mode>")])
7550 ; lpdfr
7551 (define_insn "*abs<mode>2_nocc"
7552 [(set (match_operand:FP 0 "register_operand" "=f")
7553 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7554 "TARGET_DFP"
7555 "lpdfr\t%0,%1"
7556 [(set_attr "op_type" "RRE")
7557 (set_attr "type" "fsimp<mode>")])
7559 ; lpxbr, lpdbr, lpebr
7560 (define_insn "*abs<mode>2"
7561 [(set (match_operand:BFP 0 "register_operand" "=f")
7562 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7563 (clobber (reg:CC CC_REGNUM))]
7564 "TARGET_HARD_FLOAT"
7565 "lp<xde>br\t%0,%1"
7566 [(set_attr "op_type" "RRE")
7567 (set_attr "type" "fsimp<mode>")])
7570 ;;
7571 ;;- Negated absolute value instructions
7572 ;;
7574 ;
7575 ; Integer
7576 ;
7578 (define_insn "*negabsdi2_sign_cc"
7579 [(set (reg CC_REGNUM)
7580 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7581 (match_operand:SI 1 "register_operand" "d") 0)
7582 (const_int 32)) (const_int 32))))
7583 (const_int 0)))
7584 (set (match_operand:DI 0 "register_operand" "=d")
7585 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7586 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7587 "lngfr\t%0,%1"
7588 [(set_attr "op_type" "RRE")
7589 (set_attr "z10prop" "z10_c")])
7591 (define_insn "*negabsdi2_sign"
7592 [(set (match_operand:DI 0 "register_operand" "=d")
7593 (neg:DI (abs:DI (sign_extend:DI
7594 (match_operand:SI 1 "register_operand" "d")))))
7595 (clobber (reg:CC CC_REGNUM))]
7596 "TARGET_ZARCH"
7597 "lngfr\t%0,%1"
7598 [(set_attr "op_type" "RRE")
7599 (set_attr "z10prop" "z10_c")])
7601 ; lnr, lngr
7602 (define_insn "*negabs<mode>2_cc"
7603 [(set (reg CC_REGNUM)
7604 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7605 (const_int 0)))
7606 (set (match_operand:GPR 0 "register_operand" "=d")
7607 (neg:GPR (abs:GPR (match_dup 1))))]
7608 "s390_match_ccmode (insn, CCAmode)"
7609 "ln<g>r\t%0,%1"
7610 [(set_attr "op_type" "RR<E>")
7611 (set_attr "z10prop" "z10_c")])
7613 ; lnr, lngr
7614 (define_insn "*negabs<mode>2_cconly"
7615 [(set (reg CC_REGNUM)
7616 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7617 (const_int 0)))
7618 (clobber (match_scratch:GPR 0 "=d"))]
7619 "s390_match_ccmode (insn, CCAmode)"
7620 "ln<g>r\t%0,%1"
7621 [(set_attr "op_type" "RR<E>")
7622 (set_attr "z10prop" "z10_c")])
7624 ; lnr, lngr
7625 (define_insn "*negabs<mode>2"
7626 [(set (match_operand:GPR 0 "register_operand" "=d")
7627 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7628 (clobber (reg:CC CC_REGNUM))]
7629 ""
7630 "ln<g>r\t%0,%1"
7631 [(set_attr "op_type" "RR<E>")
7632 (set_attr "z10prop" "z10_c")])
7634 ;
7635 ; Floating point
7636 ;
7638 ; lnxbr, lndbr, lnebr
7639 (define_insn "*negabs<mode>2_cc"
7640 [(set (reg CC_REGNUM)
7641 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7642 (match_operand:BFP 2 "const0_operand" "")))
7643 (set (match_operand:BFP 0 "register_operand" "=f")
7644 (neg:BFP (abs:BFP (match_dup 1))))]
7645 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7646 "ln<xde>br\t%0,%1"
7647 [(set_attr "op_type" "RRE")
7648 (set_attr "type" "fsimp<mode>")])
7650 ; lnxbr, lndbr, lnebr
7651 (define_insn "*negabs<mode>2_cconly"
7652 [(set (reg CC_REGNUM)
7653 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7654 (match_operand:BFP 2 "const0_operand" "")))
7655 (clobber (match_scratch:BFP 0 "=f"))]
7656 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7657 "ln<xde>br\t%0,%1"
7658 [(set_attr "op_type" "RRE")
7659 (set_attr "type" "fsimp<mode>")])
7661 ; lndfr
7662 (define_insn "*negabs<mode>2_nocc"
7663 [(set (match_operand:FP 0 "register_operand" "=f")
7664 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7665 "TARGET_DFP"
7666 "lndfr\t%0,%1"
7667 [(set_attr "op_type" "RRE")
7668 (set_attr "type" "fsimp<mode>")])
7670 ; lnxbr, lndbr, lnebr
7671 (define_insn "*negabs<mode>2"
7672 [(set (match_operand:BFP 0 "register_operand" "=f")
7673 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7674 (clobber (reg:CC CC_REGNUM))]
7675 "TARGET_HARD_FLOAT"
7676 "ln<xde>br\t%0,%1"
7677 [(set_attr "op_type" "RRE")
7678 (set_attr "type" "fsimp<mode>")])
7680 ;;
7681 ;;- Square root instructions.
7682 ;;
7684 ;
7685 ; sqrt(df|sf)2 instruction pattern(s).
7686 ;
7688 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7689 (define_insn "sqrt<mode>2"
7690 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7691 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7692 "TARGET_HARD_FLOAT"
7693 "@
7694 sq<xde>br\t%0,%1
7695 sq<xde>b\t%0,%1"
7696 [(set_attr "op_type" "RRE,RXE")
7697 (set_attr "type" "fsqrt<mode>")])
7700 ;;
7701 ;;- One complement instructions.
7702 ;;
7704 ;
7705 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7706 ;
7708 (define_expand "one_cmpl<mode>2"
7709 [(parallel
7710 [(set (match_operand:INT 0 "register_operand" "")
7711 (xor:INT (match_operand:INT 1 "register_operand" "")
7712 (const_int -1)))
7713 (clobber (reg:CC CC_REGNUM))])]
7714 ""
7715 "")
7718 ;;
7719 ;; Find leftmost bit instructions.
7720 ;;
7722 (define_expand "clzdi2"
7723 [(set (match_operand:DI 0 "register_operand" "=d")
7724 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7725 "TARGET_EXTIMM && TARGET_ZARCH"
7726 {
7727 rtx insn, clz_equal;
7728 rtx wide_reg = gen_reg_rtx (TImode);
7729 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7731 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7733 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7735 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7736 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7738 DONE;
7739 })
7741 (define_insn "clztidi2"
7742 [(set (match_operand:TI 0 "register_operand" "=d")
7743 (ior:TI
7744 (ashift:TI
7745 (zero_extend:TI
7746 (xor:DI (match_operand:DI 1 "register_operand" "d")
7747 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7748 (subreg:SI (clz:DI (match_dup 1)) 4))))
7750 (const_int 64))
7751 (zero_extend:TI (clz:DI (match_dup 1)))))
7752 (clobber (reg:CC CC_REGNUM))]
7753 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7754 == (unsigned HOST_WIDE_INT) 1 << 63
7755 && TARGET_EXTIMM && TARGET_ZARCH"
7756 "flogr\t%0,%1"
7757 [(set_attr "op_type" "RRE")])
7760 ;;
7761 ;;- Rotate instructions.
7762 ;;
7764 ;
7765 ; rotl(di|si)3 instruction pattern(s).
7766 ;
7768 ; rll, rllg
7769 (define_insn "rotl<mode>3"
7770 [(set (match_operand:GPR 0 "register_operand" "=d")
7771 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7772 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7773 "TARGET_CPU_ZARCH"
7774 "rll<g>\t%0,%1,%Y2"
7775 [(set_attr "op_type" "RSE")
7776 (set_attr "atype" "reg")
7777 (set_attr "z10prop" "z10_super_E1")])
7779 ; rll, rllg
7780 (define_insn "*rotl<mode>3_and"
7781 [(set (match_operand:GPR 0 "register_operand" "=d")
7782 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7783 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7784 (match_operand:SI 3 "const_int_operand" "n"))))]
7785 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7786 "rll<g>\t%0,%1,%Y2"
7787 [(set_attr "op_type" "RSE")
7788 (set_attr "atype" "reg")
7789 (set_attr "z10prop" "z10_super_E1")])
7792 ;;
7793 ;;- Shift instructions.
7794 ;;
7796 ;
7797 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7798 ; Left shifts and logical right shifts
7800 (define_expand "<shift><mode>3"
7801 [(set (match_operand:DSI 0 "register_operand" "")
7802 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7803 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7804 ""
7805 "")
7807 ; sldl, srdl
7808 (define_insn "*<shift>di3_31"
7809 [(set (match_operand:DI 0 "register_operand" "=d")
7810 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7811 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7812 "!TARGET_ZARCH"
7813 "s<lr>dl\t%0,%Y2"
7814 [(set_attr "op_type" "RS")
7815 (set_attr "atype" "reg")
7816 (set_attr "z196prop" "z196_cracked")])
7818 ; sll, srl, sllg, srlg, sllk, srlk
7819 (define_insn "*<shift><mode>3"
7820 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7821 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7822 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7823 ""
7824 "@
7825 s<lr>l<g>\t%0,<1>%Y2
7826 s<lr>l<gk>\t%0,%1,%Y2"
7827 [(set_attr "op_type" "RS<E>,RSY")
7828 (set_attr "atype" "reg,reg")
7829 (set_attr "cpu_facility" "*,z196")
7830 (set_attr "z10prop" "z10_super_E1,*")])
7832 ; sldl, srdl
7833 (define_insn "*<shift>di3_31_and"
7834 [(set (match_operand:DI 0 "register_operand" "=d")
7835 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7836 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7837 (match_operand:SI 3 "const_int_operand" "n"))))]
7838 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7839 "s<lr>dl\t%0,%Y2"
7840 [(set_attr "op_type" "RS")
7841 (set_attr "atype" "reg")])
7843 ; sll, srl, sllg, srlg, sllk, srlk
7844 (define_insn "*<shift><mode>3_and"
7845 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7846 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7847 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7848 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7849 "(INTVAL (operands[3]) & 63) == 63"
7850 "@
7851 s<lr>l<g>\t%0,<1>%Y2
7852 s<lr>l<gk>\t%0,%1,%Y2"
7853 [(set_attr "op_type" "RS<E>,RSY")
7854 (set_attr "atype" "reg,reg")
7855 (set_attr "cpu_facility" "*,z196")
7856 (set_attr "z10prop" "z10_super_E1,*")])
7858 ;
7859 ; ashr(di|si)3 instruction pattern(s).
7860 ; Arithmetic right shifts
7862 (define_expand "ashr<mode>3"
7863 [(parallel
7864 [(set (match_operand:DSI 0 "register_operand" "")
7865 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7866 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7867 (clobber (reg:CC CC_REGNUM))])]
7868 ""
7869 "")
7871 (define_insn "*ashrdi3_cc_31"
7872 [(set (reg CC_REGNUM)
7873 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7874 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7875 (const_int 0)))
7876 (set (match_operand:DI 0 "register_operand" "=d")
7877 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7878 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7879 "srda\t%0,%Y2"
7880 [(set_attr "op_type" "RS")
7881 (set_attr "atype" "reg")])
7883 (define_insn "*ashrdi3_cconly_31"
7884 [(set (reg CC_REGNUM)
7885 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7886 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7887 (const_int 0)))
7888 (clobber (match_scratch:DI 0 "=d"))]
7889 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7890 "srda\t%0,%Y2"
7891 [(set_attr "op_type" "RS")
7892 (set_attr "atype" "reg")])
7894 (define_insn "*ashrdi3_31"
7895 [(set (match_operand:DI 0 "register_operand" "=d")
7896 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7897 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7898 (clobber (reg:CC CC_REGNUM))]
7899 "!TARGET_ZARCH"
7900 "srda\t%0,%Y2"
7901 [(set_attr "op_type" "RS")
7902 (set_attr "atype" "reg")])
7904 ; sra, srag, srak
7905 (define_insn "*ashr<mode>3_cc"
7906 [(set (reg CC_REGNUM)
7907 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7908 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7909 (const_int 0)))
7910 (set (match_operand:GPR 0 "register_operand" "=d,d")
7911 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7912 "s390_match_ccmode(insn, CCSmode)"
7913 "@
7914 sra<g>\t%0,<1>%Y2
7915 sra<gk>\t%0,%1,%Y2"
7916 [(set_attr "op_type" "RS<E>,RSY")
7917 (set_attr "atype" "reg,reg")
7918 (set_attr "cpu_facility" "*,z196")
7919 (set_attr "z10prop" "z10_super_E1,*")])
7921 ; sra, srag, srak
7922 (define_insn "*ashr<mode>3_cconly"
7923 [(set (reg CC_REGNUM)
7924 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7925 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7926 (const_int 0)))
7927 (clobber (match_scratch:GPR 0 "=d,d"))]
7928 "s390_match_ccmode(insn, CCSmode)"
7929 "@
7930 sra<g>\t%0,<1>%Y2
7931 sra<gk>\t%0,%1,%Y2"
7932 [(set_attr "op_type" "RS<E>,RSY")
7933 (set_attr "atype" "reg,reg")
7934 (set_attr "cpu_facility" "*,z196")
7935 (set_attr "z10prop" "z10_super_E1,*")])
7937 ; sra, srag
7938 (define_insn "*ashr<mode>3"
7939 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7940 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7941 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7942 (clobber (reg:CC CC_REGNUM))]
7943 ""
7944 "@
7945 sra<g>\t%0,<1>%Y2
7946 sra<gk>\t%0,%1,%Y2"
7947 [(set_attr "op_type" "RS<E>,RSY")
7948 (set_attr "atype" "reg,reg")
7949 (set_attr "cpu_facility" "*,z196")
7950 (set_attr "z10prop" "z10_super_E1,*")])
7953 ; shift pattern with implicit ANDs
7955 (define_insn "*ashrdi3_cc_31_and"
7956 [(set (reg CC_REGNUM)
7957 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7958 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7959 (match_operand:SI 3 "const_int_operand" "n")))
7960 (const_int 0)))
7961 (set (match_operand:DI 0 "register_operand" "=d")
7962 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7963 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7964 && (INTVAL (operands[3]) & 63) == 63"
7965 "srda\t%0,%Y2"
7966 [(set_attr "op_type" "RS")
7967 (set_attr "atype" "reg")])
7969 (define_insn "*ashrdi3_cconly_31_and"
7970 [(set (reg CC_REGNUM)
7971 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7972 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7973 (match_operand:SI 3 "const_int_operand" "n")))
7974 (const_int 0)))
7975 (clobber (match_scratch:DI 0 "=d"))]
7976 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7977 && (INTVAL (operands[3]) & 63) == 63"
7978 "srda\t%0,%Y2"
7979 [(set_attr "op_type" "RS")
7980 (set_attr "atype" "reg")])
7982 (define_insn "*ashrdi3_31_and"
7983 [(set (match_operand:DI 0 "register_operand" "=d")
7984 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7985 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7986 (match_operand:SI 3 "const_int_operand" "n"))))
7987 (clobber (reg:CC CC_REGNUM))]
7988 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7989 "srda\t%0,%Y2"
7990 [(set_attr "op_type" "RS")
7991 (set_attr "atype" "reg")])
7993 ; sra, srag, srak
7994 (define_insn "*ashr<mode>3_cc_and"
7995 [(set (reg CC_REGNUM)
7996 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7997 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7998 (match_operand:SI 3 "const_int_operand" "n,n")))
7999 (const_int 0)))
8000 (set (match_operand:GPR 0 "register_operand" "=d,d")
8001 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8002 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8003 "@
8004 sra<g>\t%0,<1>%Y2
8005 sra<gk>\t%0,%1,%Y2"
8006 [(set_attr "op_type" "RS<E>,RSY")
8007 (set_attr "atype" "reg,reg")
8008 (set_attr "cpu_facility" "*,z196")
8009 (set_attr "z10prop" "z10_super_E1,*")])
8011 ; sra, srag, srak
8012 (define_insn "*ashr<mode>3_cconly_and"
8013 [(set (reg CC_REGNUM)
8014 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8015 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8016 (match_operand:SI 3 "const_int_operand" "n,n")))
8017 (const_int 0)))
8018 (clobber (match_scratch:GPR 0 "=d,d"))]
8019 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8020 "@
8021 sra<g>\t%0,<1>%Y2
8022 sra<gk>\t%0,%1,%Y2"
8023 [(set_attr "op_type" "RS<E>,RSY")
8024 (set_attr "atype" "reg,reg")
8025 (set_attr "cpu_facility" "*,z196")
8026 (set_attr "z10prop" "z10_super_E1,*")])
8028 ; sra, srag, srak
8029 (define_insn "*ashr<mode>3_and"
8030 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8031 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8032 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8033 (match_operand:SI 3 "const_int_operand" "n,n"))))
8034 (clobber (reg:CC CC_REGNUM))]
8035 "(INTVAL (operands[3]) & 63) == 63"
8036 "@
8037 sra<g>\t%0,<1>%Y2
8038 sra<gk>\t%0,%1,%Y2"
8039 [(set_attr "op_type" "RS<E>,RSY")
8040 (set_attr "atype" "reg,reg")
8041 (set_attr "cpu_facility" "*,z196")
8042 (set_attr "z10prop" "z10_super_E1,*")])
8045 ;;
8046 ;; Branch instruction patterns.
8047 ;;
8049 (define_expand "cbranch<mode>4"
8050 [(set (pc)
8051 (if_then_else (match_operator 0 "comparison_operator"
8052 [(match_operand:GPR 1 "register_operand" "")
8053 (match_operand:GPR 2 "general_operand" "")])
8054 (label_ref (match_operand 3 "" ""))
8055 (pc)))]
8056 ""
8057 "s390_emit_jump (operands[3],
8058 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8059 DONE;")
8061 (define_expand "cbranch<mode>4"
8062 [(set (pc)
8063 (if_then_else (match_operator 0 "comparison_operator"
8064 [(match_operand:FP 1 "register_operand" "")
8065 (match_operand:FP 2 "general_operand" "")])
8066 (label_ref (match_operand 3 "" ""))
8067 (pc)))]
8068 "TARGET_HARD_FLOAT"
8069 "s390_emit_jump (operands[3],
8070 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8071 DONE;")
8073 (define_expand "cbranchcc4"
8074 [(set (pc)
8075 (if_then_else (match_operator 0 "s390_eqne_operator"
8076 [(match_operand 1 "cc_reg_operand" "")
8077 (match_operand 2 "const0_operand" "")])
8078 (label_ref (match_operand 3 "" ""))
8079 (pc)))]
8080 "TARGET_HARD_FLOAT"
8081 "s390_emit_jump (operands[3],
8082 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8083 DONE;")
8087 ;;
8088 ;;- Conditional jump instructions.
8089 ;;
8091 (define_insn "*cjump_64"
8092 [(set (pc)
8093 (if_then_else
8094 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8095 (match_operand 2 "const_int_operand" "")])
8096 (label_ref (match_operand 0 "" ""))
8097 (pc)))]
8098 "TARGET_CPU_ZARCH"
8099 {
8100 if (get_attr_length (insn) == 4)
8101 return "j%C1\t%l0";
8102 else
8103 return "jg%C1\t%l0";
8104 }
8105 [(set_attr "op_type" "RI")
8106 (set_attr "type" "branch")
8107 (set (attr "length")
8108 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8109 (const_int 4) (const_int 6)))])
8111 (define_insn "*cjump_31"
8112 [(set (pc)
8113 (if_then_else
8114 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8115 (match_operand 2 "const_int_operand" "")])
8116 (label_ref (match_operand 0 "" ""))
8117 (pc)))]
8118 "!TARGET_CPU_ZARCH"
8119 {
8120 gcc_assert (get_attr_length (insn) == 4);
8121 return "j%C1\t%l0";
8122 }
8123 [(set_attr "op_type" "RI")
8124 (set_attr "type" "branch")
8125 (set (attr "length")
8126 (if_then_else (not (match_test "flag_pic"))
8127 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8128 (const_int 4) (const_int 6))
8129 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8130 (const_int 4) (const_int 8))))])
8132 (define_insn "*cjump_long"
8133 [(set (pc)
8134 (if_then_else
8135 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8136 (match_operand 0 "address_operand" "ZQZR")
8137 (pc)))]
8138 ""
8139 {
8140 if (get_attr_op_type (insn) == OP_TYPE_RR)
8141 return "b%C1r\t%0";
8142 else
8143 return "b%C1\t%a0";
8144 }
8145 [(set (attr "op_type")
8146 (if_then_else (match_operand 0 "register_operand" "")
8147 (const_string "RR") (const_string "RX")))
8148 (set_attr "type" "branch")
8149 (set_attr "atype" "agen")])
8151 ;; A conditional return instruction.
8152 (define_insn "*c<code>"
8153 [(set (pc)
8154 (if_then_else
8155 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8156 (ANY_RETURN)
8157 (pc)))]
8158 "s390_can_use_<code>_insn ()"
8159 "b%C0r\t%%r14"
8160 [(set_attr "op_type" "RR")
8161 (set_attr "type" "jsr")
8162 (set_attr "atype" "agen")])
8164 ;;
8165 ;;- Negated conditional jump instructions.
8166 ;;
8168 (define_insn "*icjump_64"
8169 [(set (pc)
8170 (if_then_else
8171 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8172 (pc)
8173 (label_ref (match_operand 0 "" ""))))]
8174 "TARGET_CPU_ZARCH"
8175 {
8176 if (get_attr_length (insn) == 4)
8177 return "j%D1\t%l0";
8178 else
8179 return "jg%D1\t%l0";
8180 }
8181 [(set_attr "op_type" "RI")
8182 (set_attr "type" "branch")
8183 (set (attr "length")
8184 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8185 (const_int 4) (const_int 6)))])
8187 (define_insn "*icjump_31"
8188 [(set (pc)
8189 (if_then_else
8190 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8191 (pc)
8192 (label_ref (match_operand 0 "" ""))))]
8193 "!TARGET_CPU_ZARCH"
8194 {
8195 gcc_assert (get_attr_length (insn) == 4);
8196 return "j%D1\t%l0";
8197 }
8198 [(set_attr "op_type" "RI")
8199 (set_attr "type" "branch")
8200 (set (attr "length")
8201 (if_then_else (not (match_test "flag_pic"))
8202 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8203 (const_int 4) (const_int 6))
8204 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8205 (const_int 4) (const_int 8))))])
8207 (define_insn "*icjump_long"
8208 [(set (pc)
8209 (if_then_else
8210 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8211 (pc)
8212 (match_operand 0 "address_operand" "ZQZR")))]
8213 ""
8214 {
8215 if (get_attr_op_type (insn) == OP_TYPE_RR)
8216 return "b%D1r\t%0";
8217 else
8218 return "b%D1\t%a0";
8219 }
8220 [(set (attr "op_type")
8221 (if_then_else (match_operand 0 "register_operand" "")
8222 (const_string "RR") (const_string "RX")))
8223 (set_attr "type" "branch")
8224 (set_attr "atype" "agen")])
8226 ;;
8227 ;;- Trap instructions.
8228 ;;
8230 (define_insn "trap"
8231 [(trap_if (const_int 1) (const_int 0))]
8232 ""
8233 "j\t.+2"
8234 [(set_attr "op_type" "RI")
8235 (set_attr "type" "branch")])
8237 (define_expand "ctrap<mode>4"
8238 [(trap_if (match_operator 0 "comparison_operator"
8239 [(match_operand:GPR 1 "register_operand" "")
8240 (match_operand:GPR 2 "general_operand" "")])
8241 (match_operand 3 "const0_operand" ""))]
8242 ""
8243 {
8244 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8245 operands[1], operands[2]);
8246 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8247 DONE;
8248 })
8250 (define_expand "ctrap<mode>4"
8251 [(trap_if (match_operator 0 "comparison_operator"
8252 [(match_operand:FP 1 "register_operand" "")
8253 (match_operand:FP 2 "general_operand" "")])
8254 (match_operand 3 "const0_operand" ""))]
8255 ""
8256 {
8257 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8258 operands[1], operands[2]);
8259 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8260 DONE;
8261 })
8263 (define_insn "condtrap"
8264 [(trap_if (match_operator 0 "s390_comparison"
8265 [(match_operand 1 "cc_reg_operand" "c")
8266 (const_int 0)])
8267 (const_int 0))]
8268 ""
8269 "j%C0\t.+2";
8270 [(set_attr "op_type" "RI")
8271 (set_attr "type" "branch")])
8273 ; crt, cgrt, cit, cgit
8274 (define_insn "*cmp_and_trap_signed_int<mode>"
8275 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8276 [(match_operand:GPR 1 "register_operand" "d,d")
8277 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8278 (const_int 0))]
8279 "TARGET_Z10"
8280 "@
8281 c<g>rt%C0\t%1,%2
8282 c<g>it%C0\t%1,%h2"
8283 [(set_attr "op_type" "RRF,RIE")
8284 (set_attr "type" "branch")
8285 (set_attr "z10prop" "z10_super_c,z10_super")])
8287 ; clrt, clgrt, clfit, clgit, clt, clgt
8288 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8289 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8290 [(match_operand:GPR 1 "register_operand" "d,d, d")
8291 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8292 (const_int 0))]
8293 "TARGET_Z10"
8294 "@
8295 cl<g>rt%C0\t%1,%2
8296 cl<gf>it%C0\t%1,%x2
8297 cl<g>t%C0\t%1,%2"
8298 [(set_attr "op_type" "RRF,RIE,RSY")
8299 (set_attr "type" "branch")
8300 (set_attr "z10prop" "z10_super_c,z10_super,*")
8301 (set_attr "cpu_facility" "z10,z10,zEC12")])
8303 ; lat, lgat
8304 (define_insn "*load_and_trap<mode>"
8305 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8306 (const_int 0))
8307 (const_int 0))
8308 (set (match_operand:GPR 1 "register_operand" "=d")
8309 (match_dup 0))]
8310 "TARGET_ZEC12"
8311 "l<g>at\t%1,%0"
8312 [(set_attr "op_type" "RXY")])
8315 ;;
8316 ;;- Loop instructions.
8317 ;;
8318 ;; This is all complicated by the fact that since this is a jump insn
8319 ;; we must handle our own output reloads.
8321 ;; branch on index
8323 ; This splitter will be matched by combine and has to add the 2 moves
8324 ; necessary to load the compare and the increment values into a
8325 ; register pair as needed by brxle.
8327 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8328 [(set (pc)
8329 (if_then_else
8330 (match_operator 6 "s390_brx_operator"
8331 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8332 (match_operand:GPR 2 "general_operand" ""))
8333 (match_operand:GPR 3 "register_operand" "")])
8334 (label_ref (match_operand 0 "" ""))
8335 (pc)))
8336 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8337 (plus:GPR (match_dup 1) (match_dup 2)))
8338 (clobber (match_scratch:GPR 5 ""))]
8339 "TARGET_CPU_ZARCH"
8340 "#"
8341 "!reload_completed && !reload_in_progress"
8342 [(set (match_dup 7) (match_dup 2)) ; the increment
8343 (set (match_dup 8) (match_dup 3)) ; the comparison value
8344 (parallel [(set (pc)
8345 (if_then_else
8346 (match_op_dup 6
8347 [(plus:GPR (match_dup 1) (match_dup 7))
8348 (match_dup 8)])
8349 (label_ref (match_dup 0))
8350 (pc)))
8351 (set (match_dup 4)
8352 (plus:GPR (match_dup 1) (match_dup 7)))
8353 (clobber (match_dup 5))
8354 (clobber (reg:CC CC_REGNUM))])]
8355 {
8356 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8357 operands[7] = gen_lowpart (<GPR:MODE>mode,
8358 gen_highpart (word_mode, dreg));
8359 operands[8] = gen_lowpart (<GPR:MODE>mode,
8360 gen_lowpart (word_mode, dreg));
8361 })
8363 ; brxlg, brxhg
8365 (define_insn_and_split "*brxg_64bit"
8366 [(set (pc)
8367 (if_then_else
8368 (match_operator 5 "s390_brx_operator"
8369 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8370 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8371 (subreg:DI (match_dup 2) 8)])
8372 (label_ref (match_operand 0 "" ""))
8373 (pc)))
8374 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8375 (plus:DI (match_dup 1)
8376 (subreg:DI (match_dup 2) 0)))
8377 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8378 (clobber (reg:CC CC_REGNUM))]
8379 "TARGET_ZARCH"
8380 {
8381 if (which_alternative != 0)
8382 return "#";
8383 else if (get_attr_length (insn) == 6)
8384 return "brx%E5g\t%1,%2,%l0";
8385 else
8386 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8387 }
8388 "&& reload_completed
8389 && (!REG_P (operands[3])
8390 || !rtx_equal_p (operands[1], operands[3]))"
8391 [(set (match_dup 4) (match_dup 1))
8392 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8393 (clobber (reg:CC CC_REGNUM))])
8394 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8395 (set (match_dup 3) (match_dup 4))
8396 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8397 (label_ref (match_dup 0))
8398 (pc)))]
8399 ""
8400 [(set_attr "op_type" "RIE")
8401 (set_attr "type" "branch")
8402 (set (attr "length")
8403 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8404 (const_int 6) (const_int 16)))])
8406 ; brxle, brxh
8408 (define_insn_and_split "*brx_64bit"
8409 [(set (pc)
8410 (if_then_else
8411 (match_operator 5 "s390_brx_operator"
8412 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8413 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8414 (subreg:SI (match_dup 2) 12)])
8415 (label_ref (match_operand 0 "" ""))
8416 (pc)))
8417 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8418 (plus:SI (match_dup 1)
8419 (subreg:SI (match_dup 2) 4)))
8420 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8421 (clobber (reg:CC CC_REGNUM))]
8422 "TARGET_ZARCH"
8423 {
8424 if (which_alternative != 0)
8425 return "#";
8426 else if (get_attr_length (insn) == 6)
8427 return "brx%C5\t%1,%2,%l0";
8428 else
8429 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8430 }
8431 "&& reload_completed
8432 && (!REG_P (operands[3])
8433 || !rtx_equal_p (operands[1], operands[3]))"
8434 [(set (match_dup 4) (match_dup 1))
8435 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8436 (clobber (reg:CC CC_REGNUM))])
8437 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8438 (set (match_dup 3) (match_dup 4))
8439 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8440 (label_ref (match_dup 0))
8441 (pc)))]
8442 ""
8443 [(set_attr "op_type" "RSI")
8444 (set_attr "type" "branch")
8445 (set (attr "length")
8446 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8447 (const_int 6) (const_int 14)))])
8449 ; brxle, brxh
8451 (define_insn_and_split "*brx_31bit"
8452 [(set (pc)
8453 (if_then_else
8454 (match_operator 5 "s390_brx_operator"
8455 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8456 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8457 (subreg:SI (match_dup 2) 4)])
8458 (label_ref (match_operand 0 "" ""))
8459 (pc)))
8460 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8461 (plus:SI (match_dup 1)
8462 (subreg:SI (match_dup 2) 0)))
8463 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8464 (clobber (reg:CC CC_REGNUM))]
8465 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8466 {
8467 if (which_alternative != 0)
8468 return "#";
8469 else if (get_attr_length (insn) == 6)
8470 return "brx%C5\t%1,%2,%l0";
8471 else
8472 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8473 }
8474 "&& reload_completed
8475 && (!REG_P (operands[3])
8476 || !rtx_equal_p (operands[1], operands[3]))"
8477 [(set (match_dup 4) (match_dup 1))
8478 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8479 (clobber (reg:CC CC_REGNUM))])
8480 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8481 (set (match_dup 3) (match_dup 4))
8482 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8483 (label_ref (match_dup 0))
8484 (pc)))]
8485 ""
8486 [(set_attr "op_type" "RSI")
8487 (set_attr "type" "branch")
8488 (set (attr "length")
8489 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8490 (const_int 6) (const_int 14)))])
8493 ;; branch on count
8495 (define_expand "doloop_end"
8496 [(use (match_operand 0 "" "")) ; loop pseudo
8497 (use (match_operand 1 "" ""))] ; label
8498 ""
8499 {
8500 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8501 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8502 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8503 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8504 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8505 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8506 else
8507 FAIL;
8509 DONE;
8510 })
8512 (define_insn_and_split "doloop_si64"
8513 [(set (pc)
8514 (if_then_else
8515 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8516 (const_int 1))
8517 (label_ref (match_operand 0 "" ""))
8518 (pc)))
8519 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8520 (plus:SI (match_dup 1) (const_int -1)))
8521 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8522 (clobber (reg:CC CC_REGNUM))]
8523 "TARGET_CPU_ZARCH"
8524 {
8525 if (which_alternative != 0)
8526 return "#";
8527 else if (get_attr_length (insn) == 4)
8528 return "brct\t%1,%l0";
8529 else
8530 return "ahi\t%1,-1\;jgne\t%l0";
8531 }
8532 "&& reload_completed
8533 && (! REG_P (operands[2])
8534 || ! rtx_equal_p (operands[1], operands[2]))"
8535 [(set (match_dup 3) (match_dup 1))
8536 (parallel [(set (reg:CCAN CC_REGNUM)
8537 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8538 (const_int 0)))
8539 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8540 (set (match_dup 2) (match_dup 3))
8541 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8542 (label_ref (match_dup 0))
8543 (pc)))]
8544 ""
8545 [(set_attr "op_type" "RI")
8546 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8547 ; hurt us in the (rare) case of ahi.
8548 (set_attr "z10prop" "z10_super_E1")
8549 (set_attr "type" "branch")
8550 (set (attr "length")
8551 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8552 (const_int 4) (const_int 10)))])
8554 (define_insn_and_split "doloop_si31"
8555 [(set (pc)
8556 (if_then_else
8557 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8558 (const_int 1))
8559 (label_ref (match_operand 0 "" ""))
8560 (pc)))
8561 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8562 (plus:SI (match_dup 1) (const_int -1)))
8563 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8564 (clobber (reg:CC CC_REGNUM))]
8565 "!TARGET_CPU_ZARCH"
8566 {
8567 if (which_alternative != 0)
8568 return "#";
8569 else if (get_attr_length (insn) == 4)
8570 return "brct\t%1,%l0";
8571 else
8572 gcc_unreachable ();
8573 }
8574 "&& reload_completed
8575 && (! REG_P (operands[2])
8576 || ! rtx_equal_p (operands[1], operands[2]))"
8577 [(set (match_dup 3) (match_dup 1))
8578 (parallel [(set (reg:CCAN CC_REGNUM)
8579 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8580 (const_int 0)))
8581 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8582 (set (match_dup 2) (match_dup 3))
8583 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8584 (label_ref (match_dup 0))
8585 (pc)))]
8586 ""
8587 [(set_attr "op_type" "RI")
8588 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8589 ; hurt us in the (rare) case of ahi.
8590 (set_attr "z10prop" "z10_super_E1")
8591 (set_attr "type" "branch")
8592 (set (attr "length")
8593 (if_then_else (not (match_test "flag_pic"))
8594 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8595 (const_int 4) (const_int 6))
8596 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8597 (const_int 4) (const_int 8))))])
8599 (define_insn "*doloop_si_long"
8600 [(set (pc)
8601 (if_then_else
8602 (ne (match_operand:SI 1 "register_operand" "d")
8603 (const_int 1))
8604 (match_operand 0 "address_operand" "ZQZR")
8605 (pc)))
8606 (set (match_operand:SI 2 "register_operand" "=1")
8607 (plus:SI (match_dup 1) (const_int -1)))
8608 (clobber (match_scratch:SI 3 "=X"))
8609 (clobber (reg:CC CC_REGNUM))]
8610 "!TARGET_CPU_ZARCH"
8611 {
8612 if (get_attr_op_type (insn) == OP_TYPE_RR)
8613 return "bctr\t%1,%0";
8614 else
8615 return "bct\t%1,%a0";
8616 }
8617 [(set (attr "op_type")
8618 (if_then_else (match_operand 0 "register_operand" "")
8619 (const_string "RR") (const_string "RX")))
8620 (set_attr "type" "branch")
8621 (set_attr "atype" "agen")
8622 (set_attr "z10prop" "z10_c")
8623 (set_attr "z196prop" "z196_cracked")])
8625 (define_insn_and_split "doloop_di"
8626 [(set (pc)
8627 (if_then_else
8628 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8629 (const_int 1))
8630 (label_ref (match_operand 0 "" ""))
8631 (pc)))
8632 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8633 (plus:DI (match_dup 1) (const_int -1)))
8634 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8635 (clobber (reg:CC CC_REGNUM))]
8636 "TARGET_ZARCH"
8637 {
8638 if (which_alternative != 0)
8639 return "#";
8640 else if (get_attr_length (insn) == 4)
8641 return "brctg\t%1,%l0";
8642 else
8643 return "aghi\t%1,-1\;jgne\t%l0";
8644 }
8645 "&& reload_completed
8646 && (! REG_P (operands[2])
8647 || ! rtx_equal_p (operands[1], operands[2]))"
8648 [(set (match_dup 3) (match_dup 1))
8649 (parallel [(set (reg:CCAN CC_REGNUM)
8650 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8651 (const_int 0)))
8652 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8653 (set (match_dup 2) (match_dup 3))
8654 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8655 (label_ref (match_dup 0))
8656 (pc)))]
8657 ""
8658 [(set_attr "op_type" "RI")
8659 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8660 ; hurt us in the (rare) case of ahi.
8661 (set_attr "z10prop" "z10_super_E1")
8662 (set_attr "type" "branch")
8663 (set (attr "length")
8664 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8665 (const_int 4) (const_int 10)))])
8667 ;;
8668 ;;- Unconditional jump instructions.
8669 ;;
8671 ;
8672 ; jump instruction pattern(s).
8673 ;
8675 (define_expand "jump"
8676 [(match_operand 0 "" "")]
8677 ""
8678 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8680 (define_insn "*jump64"
8681 [(set (pc) (label_ref (match_operand 0 "" "")))]
8682 "TARGET_CPU_ZARCH"
8683 {
8684 if (get_attr_length (insn) == 4)
8685 return "j\t%l0";
8686 else
8687 return "jg\t%l0";
8688 }
8689 [(set_attr "op_type" "RI")
8690 (set_attr "type" "branch")
8691 (set (attr "length")
8692 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8693 (const_int 4) (const_int 6)))])
8695 (define_insn "*jump31"
8696 [(set (pc) (label_ref (match_operand 0 "" "")))]
8697 "!TARGET_CPU_ZARCH"
8698 {
8699 gcc_assert (get_attr_length (insn) == 4);
8700 return "j\t%l0";
8701 }
8702 [(set_attr "op_type" "RI")
8703 (set_attr "type" "branch")
8704 (set (attr "length")
8705 (if_then_else (not (match_test "flag_pic"))
8706 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8707 (const_int 4) (const_int 6))
8708 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8709 (const_int 4) (const_int 8))))])
8711 ;
8712 ; indirect-jump instruction pattern(s).
8713 ;
8715 (define_insn "indirect_jump"
8716 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8717 ""
8718 {
8719 if (get_attr_op_type (insn) == OP_TYPE_RR)
8720 return "br\t%0";
8721 else
8722 return "b\t%a0";
8723 }
8724 [(set (attr "op_type")
8725 (if_then_else (match_operand 0 "register_operand" "")
8726 (const_string "RR") (const_string "RX")))
8727 (set_attr "type" "branch")
8728 (set_attr "atype" "agen")])
8730 ;
8731 ; casesi instruction pattern(s).
8732 ;
8734 (define_insn "casesi_jump"
8735 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8736 (use (label_ref (match_operand 1 "" "")))]
8737 ""
8738 {
8739 if (get_attr_op_type (insn) == OP_TYPE_RR)
8740 return "br\t%0";
8741 else
8742 return "b\t%a0";
8743 }
8744 [(set (attr "op_type")
8745 (if_then_else (match_operand 0 "register_operand" "")
8746 (const_string "RR") (const_string "RX")))
8747 (set_attr "type" "branch")
8748 (set_attr "atype" "agen")])
8750 (define_expand "casesi"
8751 [(match_operand:SI 0 "general_operand" "")
8752 (match_operand:SI 1 "general_operand" "")
8753 (match_operand:SI 2 "general_operand" "")
8754 (label_ref (match_operand 3 "" ""))
8755 (label_ref (match_operand 4 "" ""))]
8756 ""
8757 {
8758 rtx index = gen_reg_rtx (SImode);
8759 rtx base = gen_reg_rtx (Pmode);
8760 rtx target = gen_reg_rtx (Pmode);
8762 emit_move_insn (index, operands[0]);
8763 emit_insn (gen_subsi3 (index, index, operands[1]));
8764 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8765 operands[4]);
8767 if (Pmode != SImode)
8768 index = convert_to_mode (Pmode, index, 1);
8769 if (GET_CODE (index) != REG)
8770 index = copy_to_mode_reg (Pmode, index);
8772 if (TARGET_64BIT)
8773 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8774 else
8775 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8777 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8779 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8780 emit_move_insn (target, index);
8782 if (flag_pic)
8783 target = gen_rtx_PLUS (Pmode, base, target);
8784 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8786 DONE;
8787 })
8790 ;;
8791 ;;- Jump to subroutine.
8792 ;;
8793 ;;
8795 ;
8796 ; untyped call instruction pattern(s).
8797 ;
8799 ;; Call subroutine returning any type.
8800 (define_expand "untyped_call"
8801 [(parallel [(call (match_operand 0 "" "")
8802 (const_int 0))
8803 (match_operand 1 "" "")
8804 (match_operand 2 "" "")])]
8805 ""
8806 {
8807 int i;
8809 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8811 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8812 {
8813 rtx set = XVECEXP (operands[2], 0, i);
8814 emit_move_insn (SET_DEST (set), SET_SRC (set));
8815 }
8817 /* The optimizer does not know that the call sets the function value
8818 registers we stored in the result block. We avoid problems by
8819 claiming that all hard registers are used and clobbered at this
8820 point. */
8821 emit_insn (gen_blockage ());
8823 DONE;
8824 })
8826 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8827 ;; all of memory. This blocks insns from being moved across this point.
8829 (define_insn "blockage"
8830 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8831 ""
8832 ""
8833 [(set_attr "type" "none")
8834 (set_attr "length" "0")])
8836 ;
8837 ; sibcall patterns
8838 ;
8840 (define_expand "sibcall"
8841 [(call (match_operand 0 "" "")
8842 (match_operand 1 "" ""))]
8843 ""
8844 {
8845 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8846 DONE;
8847 })
8849 (define_insn "*sibcall_br"
8850 [(call (mem:QI (reg SIBCALL_REGNUM))
8851 (match_operand 0 "const_int_operand" "n"))]
8852 "SIBLING_CALL_P (insn)
8853 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8854 "br\t%%r1"
8855 [(set_attr "op_type" "RR")
8856 (set_attr "type" "branch")
8857 (set_attr "atype" "agen")])
8859 (define_insn "*sibcall_brc"
8860 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8861 (match_operand 1 "const_int_operand" "n"))]
8862 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8863 "j\t%0"
8864 [(set_attr "op_type" "RI")
8865 (set_attr "type" "branch")])
8867 (define_insn "*sibcall_brcl"
8868 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8869 (match_operand 1 "const_int_operand" "n"))]
8870 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8871 "jg\t%0"
8872 [(set_attr "op_type" "RIL")
8873 (set_attr "type" "branch")])
8875 ;
8876 ; sibcall_value patterns
8877 ;
8879 (define_expand "sibcall_value"
8880 [(set (match_operand 0 "" "")
8881 (call (match_operand 1 "" "")
8882 (match_operand 2 "" "")))]
8883 ""
8884 {
8885 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8886 DONE;
8887 })
8889 (define_insn "*sibcall_value_br"
8890 [(set (match_operand 0 "" "")
8891 (call (mem:QI (reg SIBCALL_REGNUM))
8892 (match_operand 1 "const_int_operand" "n")))]
8893 "SIBLING_CALL_P (insn)
8894 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8895 "br\t%%r1"
8896 [(set_attr "op_type" "RR")
8897 (set_attr "type" "branch")
8898 (set_attr "atype" "agen")])
8900 (define_insn "*sibcall_value_brc"
8901 [(set (match_operand 0 "" "")
8902 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8903 (match_operand 2 "const_int_operand" "n")))]
8904 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8905 "j\t%1"
8906 [(set_attr "op_type" "RI")
8907 (set_attr "type" "branch")])
8909 (define_insn "*sibcall_value_brcl"
8910 [(set (match_operand 0 "" "")
8911 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8912 (match_operand 2 "const_int_operand" "n")))]
8913 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8914 "jg\t%1"
8915 [(set_attr "op_type" "RIL")
8916 (set_attr "type" "branch")])
8919 ;
8920 ; call instruction pattern(s).
8921 ;
8923 (define_expand "call"
8924 [(call (match_operand 0 "" "")
8925 (match_operand 1 "" ""))
8926 (use (match_operand 2 "" ""))]
8927 ""
8928 {
8929 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8930 gen_rtx_REG (Pmode, RETURN_REGNUM));
8931 DONE;
8932 })
8934 (define_insn "*bras"
8935 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8936 (match_operand 1 "const_int_operand" "n"))
8937 (clobber (match_operand 2 "register_operand" "=r"))]
8938 "!SIBLING_CALL_P (insn)
8939 && TARGET_SMALL_EXEC
8940 && GET_MODE (operands[2]) == Pmode"
8941 "bras\t%2,%0"
8942 [(set_attr "op_type" "RI")
8943 (set_attr "type" "jsr")
8944 (set_attr "z196prop" "z196_cracked")])
8946 (define_insn "*brasl"
8947 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8948 (match_operand 1 "const_int_operand" "n"))
8949 (clobber (match_operand 2 "register_operand" "=r"))]
8950 "!SIBLING_CALL_P (insn)
8951 && TARGET_CPU_ZARCH
8952 && GET_MODE (operands[2]) == Pmode"
8953 "brasl\t%2,%0"
8954 [(set_attr "op_type" "RIL")
8955 (set_attr "type" "jsr")
8956 (set_attr "z196prop" "z196_cracked")])
8958 (define_insn "*basr"
8959 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8960 (match_operand 1 "const_int_operand" "n"))
8961 (clobber (match_operand 2 "register_operand" "=r"))]
8962 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8963 {
8964 if (get_attr_op_type (insn) == OP_TYPE_RR)
8965 return "basr\t%2,%0";
8966 else
8967 return "bas\t%2,%a0";
8968 }
8969 [(set (attr "op_type")
8970 (if_then_else (match_operand 0 "register_operand" "")
8971 (const_string "RR") (const_string "RX")))
8972 (set_attr "type" "jsr")
8973 (set_attr "atype" "agen")
8974 (set_attr "z196prop" "z196_cracked")])
8976 ;
8977 ; call_value instruction pattern(s).
8978 ;
8980 (define_expand "call_value"
8981 [(set (match_operand 0 "" "")
8982 (call (match_operand 1 "" "")
8983 (match_operand 2 "" "")))
8984 (use (match_operand 3 "" ""))]
8985 ""
8986 {
8987 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8988 gen_rtx_REG (Pmode, RETURN_REGNUM));
8989 DONE;
8990 })
8992 (define_insn "*bras_r"
8993 [(set (match_operand 0 "" "")
8994 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8995 (match_operand:SI 2 "const_int_operand" "n")))
8996 (clobber (match_operand 3 "register_operand" "=r"))]
8997 "!SIBLING_CALL_P (insn)
8998 && TARGET_SMALL_EXEC
8999 && GET_MODE (operands[3]) == Pmode"
9000 "bras\t%3,%1"
9001 [(set_attr "op_type" "RI")
9002 (set_attr "type" "jsr")
9003 (set_attr "z196prop" "z196_cracked")])
9005 (define_insn "*brasl_r"
9006 [(set (match_operand 0 "" "")
9007 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9008 (match_operand 2 "const_int_operand" "n")))
9009 (clobber (match_operand 3 "register_operand" "=r"))]
9010 "!SIBLING_CALL_P (insn)
9011 && TARGET_CPU_ZARCH
9012 && GET_MODE (operands[3]) == Pmode"
9013 "brasl\t%3,%1"
9014 [(set_attr "op_type" "RIL")
9015 (set_attr "type" "jsr")
9016 (set_attr "z196prop" "z196_cracked")])
9018 (define_insn "*basr_r"
9019 [(set (match_operand 0 "" "")
9020 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9021 (match_operand 2 "const_int_operand" "n")))
9022 (clobber (match_operand 3 "register_operand" "=r"))]
9023 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9024 {
9025 if (get_attr_op_type (insn) == OP_TYPE_RR)
9026 return "basr\t%3,%1";
9027 else
9028 return "bas\t%3,%a1";
9029 }
9030 [(set (attr "op_type")
9031 (if_then_else (match_operand 1 "register_operand" "")
9032 (const_string "RR") (const_string "RX")))
9033 (set_attr "type" "jsr")
9034 (set_attr "atype" "agen")
9035 (set_attr "z196prop" "z196_cracked")])
9037 ;;
9038 ;;- Thread-local storage support.
9039 ;;
9041 (define_expand "get_thread_pointer<mode>"
9042 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9043 ""
9044 "")
9046 (define_expand "set_thread_pointer<mode>"
9047 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9048 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9049 ""
9050 "")
9052 (define_insn "*set_tp"
9053 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9054 ""
9055 ""
9056 [(set_attr "type" "none")
9057 (set_attr "length" "0")])
9059 (define_insn "*tls_load_64"
9060 [(set (match_operand:DI 0 "register_operand" "=d")
9061 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9062 (match_operand:DI 2 "" "")]
9063 UNSPEC_TLS_LOAD))]
9064 "TARGET_64BIT"
9065 "lg\t%0,%1%J2"
9066 [(set_attr "op_type" "RXE")
9067 (set_attr "z10prop" "z10_fwd_A3")])
9069 (define_insn "*tls_load_31"
9070 [(set (match_operand:SI 0 "register_operand" "=d,d")
9071 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9072 (match_operand:SI 2 "" "")]
9073 UNSPEC_TLS_LOAD))]
9074 "!TARGET_64BIT"
9075 "@
9076 l\t%0,%1%J2
9077 ly\t%0,%1%J2"
9078 [(set_attr "op_type" "RX,RXY")
9079 (set_attr "type" "load")
9080 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9082 (define_insn "*bras_tls"
9083 [(set (match_operand 0 "" "")
9084 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9085 (match_operand 2 "const_int_operand" "n")))
9086 (clobber (match_operand 3 "register_operand" "=r"))
9087 (use (match_operand 4 "" ""))]
9088 "!SIBLING_CALL_P (insn)
9089 && TARGET_SMALL_EXEC
9090 && GET_MODE (operands[3]) == Pmode"
9091 "bras\t%3,%1%J4"
9092 [(set_attr "op_type" "RI")
9093 (set_attr "type" "jsr")
9094 (set_attr "z196prop" "z196_cracked")])
9096 (define_insn "*brasl_tls"
9097 [(set (match_operand 0 "" "")
9098 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9099 (match_operand 2 "const_int_operand" "n")))
9100 (clobber (match_operand 3 "register_operand" "=r"))
9101 (use (match_operand 4 "" ""))]
9102 "!SIBLING_CALL_P (insn)
9103 && TARGET_CPU_ZARCH
9104 && GET_MODE (operands[3]) == Pmode"
9105 "brasl\t%3,%1%J4"
9106 [(set_attr "op_type" "RIL")
9107 (set_attr "type" "jsr")
9108 (set_attr "z196prop" "z196_cracked")])
9110 (define_insn "*basr_tls"
9111 [(set (match_operand 0 "" "")
9112 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9113 (match_operand 2 "const_int_operand" "n")))
9114 (clobber (match_operand 3 "register_operand" "=r"))
9115 (use (match_operand 4 "" ""))]
9116 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9117 {
9118 if (get_attr_op_type (insn) == OP_TYPE_RR)
9119 return "basr\t%3,%1%J4";
9120 else
9121 return "bas\t%3,%a1%J4";
9122 }
9123 [(set (attr "op_type")
9124 (if_then_else (match_operand 1 "register_operand" "")
9125 (const_string "RR") (const_string "RX")))
9126 (set_attr "type" "jsr")
9127 (set_attr "atype" "agen")
9128 (set_attr "z196prop" "z196_cracked")])
9130 ;;
9131 ;;- Atomic operations
9132 ;;
9134 ;
9135 ; memory barrier patterns.
9136 ;
9138 (define_expand "mem_signal_fence"
9139 [(match_operand:SI 0 "const_int_operand")] ;; model
9140 ""
9141 {
9142 /* The s390 memory model is strong enough not to require any
9143 barrier in order to synchronize a thread with itself. */
9144 DONE;
9145 })
9147 (define_expand "mem_thread_fence"
9148 [(match_operand:SI 0 "const_int_operand")] ;; model
9149 ""
9150 {
9151 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9152 enough not to require barriers of any kind. */
9153 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9154 {
9155 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9156 MEM_VOLATILE_P (mem) = 1;
9157 emit_insn (gen_mem_thread_fence_1 (mem));
9158 }
9159 DONE;
9160 })
9162 ; Although bcr is superscalar on Z10, this variant will never
9163 ; become part of an execution group.
9164 ; With z196 we can make use of the fast-BCR-serialization facility.
9165 ; This allows for a slightly faster sync which is sufficient for our
9166 ; purposes.
9167 (define_insn "mem_thread_fence_1"
9168 [(set (match_operand:BLK 0 "" "")
9169 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9170 ""
9171 {
9172 if (TARGET_Z196)
9173 return "bcr\t14,0";
9174 else
9175 return "bcr\t15,0";
9176 }
9177 [(set_attr "op_type" "RR")
9178 (set_attr "mnemonic" "bcr_flush")
9179 (set_attr "z196prop" "z196_alone")])
9181 ;
9182 ; atomic load/store operations
9183 ;
9185 ; Atomic loads need not examine the memory model at all.
9186 (define_expand "atomic_load<mode>"
9187 [(match_operand:DINT 0 "register_operand") ;; output
9188 (match_operand:DINT 1 "memory_operand") ;; memory
9189 (match_operand:SI 2 "const_int_operand")] ;; model
9190 ""
9191 {
9192 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9193 FAIL;
9195 if (<MODE>mode == TImode)
9196 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9197 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9198 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9199 else
9200 emit_move_insn (operands[0], operands[1]);
9201 DONE;
9202 })
9204 ; Different from movdi_31 in that we want no splitters.
9205 (define_insn "atomic_loaddi_1"
9206 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9207 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9208 UNSPEC_MOVA))]
9209 "!TARGET_ZARCH"
9210 "@
9211 lm\t%0,%M0,%S1
9212 lmy\t%0,%M0,%S1
9213 ld\t%0,%1
9214 ldy\t%0,%1"
9215 [(set_attr "op_type" "RS,RSY,RS,RSY")
9216 (set_attr "type" "lm,lm,floaddf,floaddf")])
9218 (define_insn "atomic_loadti_1"
9219 [(set (match_operand:TI 0 "register_operand" "=r")
9220 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9221 UNSPEC_MOVA))]
9222 "TARGET_ZARCH"
9223 "lpq\t%0,%1"
9224 [(set_attr "op_type" "RXY")
9225 (set_attr "type" "other")])
9227 ; Atomic stores must(?) enforce sequential consistency.
9228 (define_expand "atomic_store<mode>"
9229 [(match_operand:DINT 0 "memory_operand") ;; memory
9230 (match_operand:DINT 1 "register_operand") ;; input
9231 (match_operand:SI 2 "const_int_operand")] ;; model
9232 ""
9233 {
9234 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9236 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9237 FAIL;
9239 if (<MODE>mode == TImode)
9240 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9241 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9242 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9243 else
9244 emit_move_insn (operands[0], operands[1]);
9245 if (model == MEMMODEL_SEQ_CST)
9246 emit_insn (gen_mem_thread_fence (operands[2]));
9247 DONE;
9248 })
9250 ; Different from movdi_31 in that we want no splitters.
9251 (define_insn "atomic_storedi_1"
9252 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9253 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9254 UNSPEC_MOVA))]
9255 "!TARGET_ZARCH"
9256 "@
9257 stm\t%1,%N1,%S0
9258 stmy\t%1,%N1,%S0
9259 std %1,%0
9260 stdy %1,%0"
9261 [(set_attr "op_type" "RS,RSY,RS,RSY")
9262 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9264 (define_insn "atomic_storeti_1"
9265 [(set (match_operand:TI 0 "memory_operand" "=RT")
9266 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9267 UNSPEC_MOVA))]
9268 "TARGET_ZARCH"
9269 "stpq\t%1,%0"
9270 [(set_attr "op_type" "RXY")
9271 (set_attr "type" "other")])
9273 ;
9274 ; compare and swap patterns.
9275 ;
9277 (define_expand "atomic_compare_and_swap<mode>"
9278 [(match_operand:SI 0 "register_operand") ;; bool success output
9279 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9280 (match_operand:DGPR 2 "memory_operand") ;; memory
9281 (match_operand:DGPR 3 "register_operand") ;; expected intput
9282 (match_operand:DGPR 4 "register_operand") ;; newval intput
9283 (match_operand:SI 5 "const_int_operand") ;; is_weak
9284 (match_operand:SI 6 "const_int_operand") ;; success model
9285 (match_operand:SI 7 "const_int_operand")] ;; failure model
9286 ""
9287 {
9288 rtx cc, cmp, output = operands[1];
9290 if (!register_operand (output, <MODE>mode))
9291 output = gen_reg_rtx (<MODE>mode);
9293 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9294 FAIL;
9296 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9297 (output, operands[2], operands[3], operands[4]));
9299 /* We deliberately accept non-register operands in the predicate
9300 to ensure the write back to the output operand happens *before*
9301 the store-flags code below. This makes it easier for combine
9302 to merge the store-flags code with a potential test-and-branch
9303 pattern following (immediately!) afterwards. */
9304 if (output != operands[1])
9305 emit_move_insn (operands[1], output);
9307 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9308 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9309 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9310 DONE;
9311 })
9313 (define_expand "atomic_compare_and_swap<mode>"
9314 [(match_operand:SI 0 "register_operand") ;; bool success output
9315 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9316 (match_operand:HQI 2 "memory_operand") ;; memory
9317 (match_operand:HQI 3 "general_operand") ;; expected intput
9318 (match_operand:HQI 4 "general_operand") ;; newval intput
9319 (match_operand:SI 5 "const_int_operand") ;; is_weak
9320 (match_operand:SI 6 "const_int_operand") ;; success model
9321 (match_operand:SI 7 "const_int_operand")] ;; failure model
9322 ""
9323 {
9324 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9325 operands[3], operands[4], INTVAL (operands[5]));
9326 DONE;
9327 })
9329 (define_expand "atomic_compare_and_swap<mode>_internal"
9330 [(parallel
9331 [(set (match_operand:DGPR 0 "register_operand")
9332 (match_operand:DGPR 1 "memory_operand"))
9333 (set (match_dup 1)
9334 (unspec_volatile:DGPR
9335 [(match_dup 1)
9336 (match_operand:DGPR 2 "register_operand")
9337 (match_operand:DGPR 3 "register_operand")]
9338 UNSPECV_CAS))
9339 (set (reg:CCZ1 CC_REGNUM)
9340 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9341 "")
9343 ; cdsg, csg
9344 (define_insn "*atomic_compare_and_swap<mode>_1"
9345 [(set (match_operand:TDI 0 "register_operand" "=r")
9346 (match_operand:TDI 1 "memory_operand" "+QS"))
9347 (set (match_dup 1)
9348 (unspec_volatile:TDI
9349 [(match_dup 1)
9350 (match_operand:TDI 2 "register_operand" "0")
9351 (match_operand:TDI 3 "register_operand" "r")]
9352 UNSPECV_CAS))
9353 (set (reg:CCZ1 CC_REGNUM)
9354 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9355 "TARGET_ZARCH"
9356 "c<td>sg\t%0,%3,%S1"
9357 [(set_attr "op_type" "RSY")
9358 (set_attr "type" "sem")])
9360 ; cds, cdsy
9361 (define_insn "*atomic_compare_and_swapdi_2"
9362 [(set (match_operand:DI 0 "register_operand" "=r,r")
9363 (match_operand:DI 1 "memory_operand" "+Q,S"))
9364 (set (match_dup 1)
9365 (unspec_volatile:DI
9366 [(match_dup 1)
9367 (match_operand:DI 2 "register_operand" "0,0")
9368 (match_operand:DI 3 "register_operand" "r,r")]
9369 UNSPECV_CAS))
9370 (set (reg:CCZ1 CC_REGNUM)
9371 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9372 "!TARGET_ZARCH"
9373 "@
9374 cds\t%0,%3,%S1
9375 cdsy\t%0,%3,%S1"
9376 [(set_attr "op_type" "RS,RSY")
9377 (set_attr "type" "sem")])
9379 ; cs, csy
9380 (define_insn "*atomic_compare_and_swapsi_3"
9381 [(set (match_operand:SI 0 "register_operand" "=r,r")
9382 (match_operand:SI 1 "memory_operand" "+Q,S"))
9383 (set (match_dup 1)
9384 (unspec_volatile:SI
9385 [(match_dup 1)
9386 (match_operand:SI 2 "register_operand" "0,0")
9387 (match_operand:SI 3 "register_operand" "r,r")]
9388 UNSPECV_CAS))
9389 (set (reg:CCZ1 CC_REGNUM)
9390 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9391 ""
9392 "@
9393 cs\t%0,%3,%S1
9394 csy\t%0,%3,%S1"
9395 [(set_attr "op_type" "RS,RSY")
9396 (set_attr "type" "sem")])
9398 ;
9399 ; Other atomic instruction patterns.
9400 ;
9402 ; z196 load and add, xor, or and and instructions
9404 (define_expand "atomic_fetch_<atomic><mode>"
9405 [(match_operand:GPR 0 "register_operand") ;; val out
9406 (ATOMIC_Z196:GPR
9407 (match_operand:GPR 1 "memory_operand") ;; memory
9408 (match_operand:GPR 2 "register_operand")) ;; val in
9409 (match_operand:SI 3 "const_int_operand")] ;; model
9410 "TARGET_Z196"
9411 {
9412 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9413 FAIL;
9415 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9416 (operands[0], operands[1], operands[2]));
9417 DONE;
9418 })
9420 ; lan, lang, lao, laog, lax, laxg, laa, laag
9421 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9422 [(set (match_operand:GPR 0 "register_operand" "=d")
9423 (match_operand:GPR 1 "memory_operand" "+QS"))
9424 (set (match_dup 1)
9425 (unspec_volatile:GPR
9426 [(ATOMIC_Z196:GPR (match_dup 1)
9427 (match_operand:GPR 2 "general_operand" "d"))]
9428 UNSPECV_ATOMIC_OP))
9429 (clobber (reg:CC CC_REGNUM))]
9430 "TARGET_Z196"
9431 "la<noxa><g>\t%0,%2,%1"
9432 [(set_attr "op_type" "RSY")
9433 (set_attr "type" "sem")])
9435 ;; For SImode and larger, the optabs.c code will do just fine in
9436 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9437 ;; better by expanding our own loop.
9439 (define_expand "atomic_<atomic><mode>"
9440 [(ATOMIC:HQI
9441 (match_operand:HQI 0 "memory_operand") ;; memory
9442 (match_operand:HQI 1 "general_operand")) ;; val in
9443 (match_operand:SI 2 "const_int_operand")] ;; model
9444 ""
9445 {
9446 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9447 operands[1], false);
9448 DONE;
9449 })
9451 (define_expand "atomic_fetch_<atomic><mode>"
9452 [(match_operand:HQI 0 "register_operand") ;; val out
9453 (ATOMIC:HQI
9454 (match_operand:HQI 1 "memory_operand") ;; memory
9455 (match_operand:HQI 2 "general_operand")) ;; val in
9456 (match_operand:SI 3 "const_int_operand")] ;; model
9457 ""
9458 {
9459 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9460 operands[2], false);
9461 DONE;
9462 })
9464 (define_expand "atomic_<atomic>_fetch<mode>"
9465 [(match_operand:HQI 0 "register_operand") ;; val out
9466 (ATOMIC:HQI
9467 (match_operand:HQI 1 "memory_operand") ;; memory
9468 (match_operand:HQI 2 "general_operand")) ;; val in
9469 (match_operand:SI 3 "const_int_operand")] ;; model
9470 ""
9471 {
9472 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9473 operands[2], true);
9474 DONE;
9475 })
9477 (define_expand "atomic_exchange<mode>"
9478 [(match_operand:HQI 0 "register_operand") ;; val out
9479 (match_operand:HQI 1 "memory_operand") ;; memory
9480 (match_operand:HQI 2 "general_operand") ;; val in
9481 (match_operand:SI 3 "const_int_operand")] ;; model
9482 ""
9483 {
9484 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9485 operands[2], false);
9486 DONE;
9487 })
9489 ;;
9490 ;;- Miscellaneous instructions.
9491 ;;
9493 ;
9494 ; allocate stack instruction pattern(s).
9495 ;
9497 (define_expand "allocate_stack"
9498 [(match_operand 0 "general_operand" "")
9499 (match_operand 1 "general_operand" "")]
9500 "TARGET_BACKCHAIN"
9501 {
9502 rtx temp = gen_reg_rtx (Pmode);
9504 emit_move_insn (temp, s390_back_chain_rtx ());
9505 anti_adjust_stack (operands[1]);
9506 emit_move_insn (s390_back_chain_rtx (), temp);
9508 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9509 DONE;
9510 })
9513 ;
9514 ; setjmp instruction pattern.
9515 ;
9517 (define_expand "builtin_setjmp_receiver"
9518 [(match_operand 0 "" "")]
9519 "flag_pic"
9520 {
9521 emit_insn (s390_load_got ());
9522 emit_use (pic_offset_table_rtx);
9523 DONE;
9524 })
9526 ;; These patterns say how to save and restore the stack pointer. We need not
9527 ;; save the stack pointer at function level since we are careful to
9528 ;; preserve the backchain. At block level, we have to restore the backchain
9529 ;; when we restore the stack pointer.
9530 ;;
9531 ;; For nonlocal gotos, we must save both the stack pointer and its
9532 ;; backchain and restore both. Note that in the nonlocal case, the
9533 ;; save area is a memory location.
9535 (define_expand "save_stack_function"
9536 [(match_operand 0 "general_operand" "")
9537 (match_operand 1 "general_operand" "")]
9538 ""
9539 "DONE;")
9541 (define_expand "restore_stack_function"
9542 [(match_operand 0 "general_operand" "")
9543 (match_operand 1 "general_operand" "")]
9544 ""
9545 "DONE;")
9547 (define_expand "restore_stack_block"
9548 [(match_operand 0 "register_operand" "")
9549 (match_operand 1 "register_operand" "")]
9550 "TARGET_BACKCHAIN"
9551 {
9552 rtx temp = gen_reg_rtx (Pmode);
9554 emit_move_insn (temp, s390_back_chain_rtx ());
9555 emit_move_insn (operands[0], operands[1]);
9556 emit_move_insn (s390_back_chain_rtx (), temp);
9558 DONE;
9559 })
9561 (define_expand "save_stack_nonlocal"
9562 [(match_operand 0 "memory_operand" "")
9563 (match_operand 1 "register_operand" "")]
9564 ""
9565 {
9566 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9568 /* Copy the backchain to the first word, sp to the second and the
9569 literal pool base to the third. */
9571 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9572 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9573 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9575 if (TARGET_BACKCHAIN)
9576 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9578 emit_move_insn (save_sp, operands[1]);
9579 emit_move_insn (save_bp, base);
9581 DONE;
9582 })
9584 (define_expand "restore_stack_nonlocal"
9585 [(match_operand 0 "register_operand" "")
9586 (match_operand 1 "memory_operand" "")]
9587 ""
9588 {
9589 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9590 rtx temp = NULL_RTX;
9592 /* Restore the backchain from the first word, sp from the second and the
9593 literal pool base from the third. */
9595 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9596 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9597 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9599 if (TARGET_BACKCHAIN)
9600 temp = force_reg (Pmode, save_bc);
9602 emit_move_insn (base, save_bp);
9603 emit_move_insn (operands[0], save_sp);
9605 if (temp)
9606 emit_move_insn (s390_back_chain_rtx (), temp);
9608 emit_use (base);
9609 DONE;
9610 })
9612 (define_expand "exception_receiver"
9613 [(const_int 0)]
9614 ""
9615 {
9616 s390_set_has_landing_pad_p (true);
9617 DONE;
9618 })
9620 ;
9621 ; nop instruction pattern(s).
9622 ;
9624 (define_insn "nop"
9625 [(const_int 0)]
9626 ""
9627 "lr\t0,0"
9628 [(set_attr "op_type" "RR")
9629 (set_attr "z10prop" "z10_fr_E1")])
9631 (define_insn "nop1"
9632 [(const_int 1)]
9633 ""
9634 "lr\t1,1"
9635 [(set_attr "op_type" "RR")])
9638 ;
9639 ; Special literal pool access instruction pattern(s).
9640 ;
9642 (define_insn "*pool_entry"
9643 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9644 UNSPECV_POOL_ENTRY)]
9645 ""
9646 {
9647 enum machine_mode mode = GET_MODE (PATTERN (insn));
9648 unsigned int align = GET_MODE_BITSIZE (mode);
9649 s390_output_pool_entry (operands[0], mode, align);
9650 return "";
9651 }
9652 [(set (attr "length")
9653 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9655 (define_insn "pool_align"
9656 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9657 UNSPECV_POOL_ALIGN)]
9658 ""
9659 ".align\t%0"
9660 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9662 (define_insn "pool_section_start"
9663 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9664 ""
9665 ".section\t.rodata"
9666 [(set_attr "length" "0")])
9668 (define_insn "pool_section_end"
9669 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9670 ""
9671 ".previous"
9672 [(set_attr "length" "0")])
9674 (define_insn "main_base_31_small"
9675 [(set (match_operand 0 "register_operand" "=a")
9676 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9677 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9678 "basr\t%0,0"
9679 [(set_attr "op_type" "RR")
9680 (set_attr "type" "la")
9681 (set_attr "z196prop" "z196_cracked")])
9683 (define_insn "main_base_31_large"
9684 [(set (match_operand 0 "register_operand" "=a")
9685 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9686 (set (pc) (label_ref (match_operand 2 "" "")))]
9687 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9688 "bras\t%0,%2"
9689 [(set_attr "op_type" "RI")
9690 (set_attr "z196prop" "z196_cracked")])
9692 (define_insn "main_base_64"
9693 [(set (match_operand 0 "register_operand" "=a")
9694 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9695 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9696 "larl\t%0,%1"
9697 [(set_attr "op_type" "RIL")
9698 (set_attr "type" "larl")
9699 (set_attr "z10prop" "z10_fwd_A1")])
9701 (define_insn "main_pool"
9702 [(set (match_operand 0 "register_operand" "=a")
9703 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9704 "GET_MODE (operands[0]) == Pmode"
9705 {
9706 gcc_unreachable ();
9707 }
9708 [(set (attr "type")
9709 (if_then_else (match_test "TARGET_CPU_ZARCH")
9710 (const_string "larl") (const_string "la")))])
9712 (define_insn "reload_base_31"
9713 [(set (match_operand 0 "register_operand" "=a")
9714 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9715 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9716 "basr\t%0,0\;la\t%0,%1-.(%0)"
9717 [(set_attr "length" "6")
9718 (set_attr "type" "la")
9719 (set_attr "z196prop" "z196_cracked")])
9721 (define_insn "reload_base_64"
9722 [(set (match_operand 0 "register_operand" "=a")
9723 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9724 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9725 "larl\t%0,%1"
9726 [(set_attr "op_type" "RIL")
9727 (set_attr "type" "larl")
9728 (set_attr "z10prop" "z10_fwd_A1")])
9730 (define_insn "pool"
9731 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9732 ""
9733 {
9734 gcc_unreachable ();
9735 }
9736 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9738 ;;
9739 ;; Insns related to generating the function prologue and epilogue.
9740 ;;
9743 (define_expand "prologue"
9744 [(use (const_int 0))]
9745 ""
9746 "s390_emit_prologue (); DONE;")
9748 (define_expand "epilogue"
9749 [(use (const_int 1))]
9750 ""
9751 "s390_emit_epilogue (false); DONE;")
9753 (define_expand "sibcall_epilogue"
9754 [(use (const_int 0))]
9755 ""
9756 "s390_emit_epilogue (true); DONE;")
9758 ;; A direct return instruction, without using an epilogue.
9759 (define_insn "<code>"
9760 [(ANY_RETURN)]
9761 "s390_can_use_<code>_insn ()"
9762 "br\t%%r14"
9763 [(set_attr "op_type" "RR")
9764 (set_attr "type" "jsr")
9765 (set_attr "atype" "agen")])
9767 (define_insn "*return"
9768 [(return)
9769 (use (match_operand 0 "register_operand" "a"))]
9770 "GET_MODE (operands[0]) == Pmode"
9771 "br\t%0"
9772 [(set_attr "op_type" "RR")
9773 (set_attr "type" "jsr")
9774 (set_attr "atype" "agen")])
9777 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9778 ;; pointer. This is used for compatibility.
9780 (define_expand "ptr_extend"
9781 [(set (match_operand:DI 0 "register_operand" "=r")
9782 (match_operand:SI 1 "register_operand" "r"))]
9783 "TARGET_64BIT"
9784 {
9785 emit_insn (gen_anddi3 (operands[0],
9786 gen_lowpart (DImode, operands[1]),
9787 GEN_INT (0x7fffffff)));
9788 DONE;
9789 })
9791 ;; Instruction definition to expand eh_return macro to support
9792 ;; swapping in special linkage return addresses.
9794 (define_expand "eh_return"
9795 [(use (match_operand 0 "register_operand" ""))]
9796 "TARGET_TPF"
9797 {
9798 s390_emit_tpf_eh_return (operands[0]);
9799 DONE;
9800 })
9802 ;
9803 ; Stack Protector Patterns
9804 ;
9806 (define_expand "stack_protect_set"
9807 [(set (match_operand 0 "memory_operand" "")
9808 (match_operand 1 "memory_operand" ""))]
9809 ""
9810 {
9811 #ifdef TARGET_THREAD_SSP_OFFSET
9812 operands[1]
9813 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9814 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9815 #endif
9816 if (TARGET_64BIT)
9817 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9818 else
9819 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9821 DONE;
9822 })
9824 (define_insn "stack_protect_set<mode>"
9825 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9826 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9827 ""
9828 "mvc\t%O0(%G0,%R0),%S1"
9829 [(set_attr "op_type" "SS")])
9831 (define_expand "stack_protect_test"
9832 [(set (reg:CC CC_REGNUM)
9833 (compare (match_operand 0 "memory_operand" "")
9834 (match_operand 1 "memory_operand" "")))
9835 (match_operand 2 "" "")]
9836 ""
9837 {
9838 rtx cc_reg, test;
9839 #ifdef TARGET_THREAD_SSP_OFFSET
9840 operands[1]
9841 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9842 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9843 #endif
9844 if (TARGET_64BIT)
9845 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9846 else
9847 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9849 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9850 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9851 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9852 DONE;
9853 })
9855 (define_insn "stack_protect_test<mode>"
9856 [(set (reg:CCZ CC_REGNUM)
9857 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9858 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9859 ""
9860 "clc\t%O0(%G0,%R0),%S1"
9861 [(set_attr "op_type" "SS")])
9863 ; This is used in s390_emit_prologue in order to prevent insns
9864 ; adjusting the stack pointer to be moved over insns writing stack
9865 ; slots using a copy of the stack pointer in a different register.
9866 (define_insn "stack_tie"
9867 [(set (match_operand:BLK 0 "memory_operand" "+m")
9868 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9869 ""
9870 ""
9871 [(set_attr "length" "0")])
9874 ;
9875 ; Data prefetch patterns
9876 ;
9878 (define_insn "prefetch"
9879 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9880 (match_operand:SI 1 "const_int_operand" " n,n")
9881 (match_operand:SI 2 "const_int_operand" " n,n"))]
9882 "TARGET_Z10"
9883 {
9884 switch (which_alternative)
9885 {
9886 case 0:
9887 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9888 case 1:
9889 if (larl_operand (operands[0], Pmode))
9890 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9891 default:
9893 /* This might be reached for symbolic operands with an odd
9894 addend. We simply omit the prefetch for such rare cases. */
9896 return "";
9897 }
9898 }
9899 [(set_attr "type" "load,larl")
9900 (set_attr "op_type" "RXY,RIL")
9901 (set_attr "z10prop" "z10_super")
9902 (set_attr "z196prop" "z196_alone")])
9905 ;
9906 ; Byte swap instructions
9907 ;
9909 (define_insn "bswap<mode>2"
9910 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9911 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9912 "TARGET_CPU_ZARCH"
9913 "@
9914 lrv<g>r\t%0,%1
9915 lrv<g>\t%0,%1"
9916 [(set_attr "type" "*,load")
9917 (set_attr "op_type" "RRE,RXY")
9918 (set_attr "z10prop" "z10_super")])
9921 ;
9922 ; Population count instruction
9923 ;
9925 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9926 ; portions and stores the result in the corresponding bytes in op0.
9927 (define_insn "*popcount<mode>"
9928 [(set (match_operand:INT 0 "register_operand" "=d")
9929 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9930 (clobber (reg:CC CC_REGNUM))]
9931 "TARGET_Z196"
9932 "popcnt\t%0,%1"
9933 [(set_attr "op_type" "RRE")])
9935 (define_expand "popcountdi2"
9936 [; popcnt op0, op1
9937 (parallel [(set (match_operand:DI 0 "register_operand" "")
9938 (unspec:DI [(match_operand:DI 1 "register_operand")]
9939 UNSPEC_POPCNT))
9940 (clobber (reg:CC CC_REGNUM))])
9941 ; sllg op2, op0, 32
9942 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9943 ; agr op0, op2
9944 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9945 (clobber (reg:CC CC_REGNUM))])
9946 ; sllg op2, op0, 16
9947 (set (match_dup 2)
9948 (ashift:DI (match_dup 0) (const_int 16)))
9949 ; agr op0, op2
9950 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9951 (clobber (reg:CC CC_REGNUM))])
9952 ; sllg op2, op0, 8
9953 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9954 ; agr op0, op2
9955 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9956 (clobber (reg:CC CC_REGNUM))])
9957 ; srlg op0, op0, 56
9958 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9959 "TARGET_Z196 && TARGET_64BIT"
9960 "operands[2] = gen_reg_rtx (DImode);")
9962 (define_expand "popcountsi2"
9963 [; popcnt op0, op1
9964 (parallel [(set (match_operand:SI 0 "register_operand" "")
9965 (unspec:SI [(match_operand:SI 1 "register_operand")]
9966 UNSPEC_POPCNT))
9967 (clobber (reg:CC CC_REGNUM))])
9968 ; sllk op2, op0, 16
9969 (set (match_dup 2)
9970 (ashift:SI (match_dup 0) (const_int 16)))
9971 ; ar op0, op2
9972 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9973 (clobber (reg:CC CC_REGNUM))])
9974 ; sllk op2, op0, 8
9975 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9976 ; ar op0, op2
9977 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9978 (clobber (reg:CC CC_REGNUM))])
9979 ; srl op0, op0, 24
9980 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9981 "TARGET_Z196"
9982 "operands[2] = gen_reg_rtx (SImode);")
9984 (define_expand "popcounthi2"
9985 [; popcnt op0, op1
9986 (parallel [(set (match_operand:HI 0 "register_operand" "")
9987 (unspec:HI [(match_operand:HI 1 "register_operand")]
9988 UNSPEC_POPCNT))
9989 (clobber (reg:CC CC_REGNUM))])
9990 ; sllk op2, op0, 8
9991 (set (match_dup 2)
9992 (ashift:SI (match_dup 0) (const_int 8)))
9993 ; ar op0, op2
9994 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9995 (clobber (reg:CC CC_REGNUM))])
9996 ; srl op0, op0, 8
9997 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9998 "TARGET_Z196"
9999 "operands[2] = gen_reg_rtx (SImode);")
10001 (define_expand "popcountqi2"
10002 [; popcnt op0, op1
10003 (parallel [(set (match_operand:QI 0 "register_operand" "")
10004 (unspec:QI [(match_operand:QI 1 "register_operand")]
10005 UNSPEC_POPCNT))
10006 (clobber (reg:CC CC_REGNUM))])]
10007 "TARGET_Z196"
10008 "")
10010 ;;
10011 ;;- Copy sign instructions
10012 ;;
10014 (define_insn "copysign<mode>3"
10015 [(set (match_operand:FP 0 "register_operand" "=f")
10016 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10017 (match_operand:FP 2 "register_operand" "f")]
10018 UNSPEC_COPYSIGN))]
10019 "TARGET_Z196"
10020 "cpsdr\t%0,%2,%1"
10021 [(set_attr "op_type" "RRF")
10022 (set_attr "type" "fsimp<mode>")])
10025 ;;
10026 ;;- Transactional execution instructions
10027 ;;
10029 ; This splitter helps combine to make use of CC directly when
10030 ; comparing the integer result of a tbegin builtin with a constant.
10031 ; The unspec is already removed by canonicalize_comparison. So this
10032 ; splitters only job is to turn the PARALLEL into separate insns
10033 ; again. Unfortunately this only works with the very first cc/int
10034 ; compare since combine is not able to deal with data flow across
10035 ; basic block boundaries.
10037 ; It needs to be an insn pattern as well since combine does not apply
10038 ; the splitter directly. Combine would only use it if it actually
10039 ; would reduce the number of instructions.
10040 (define_insn_and_split "*ccraw_to_int"
10041 [(set (pc)
10042 (if_then_else
10043 (match_operator 0 "s390_eqne_operator"
10044 [(reg:CCRAW CC_REGNUM)
10045 (match_operand 1 "const_int_operand" "")])
10046 (label_ref (match_operand 2 "" ""))
10047 (pc)))
10048 (set (match_operand:SI 3 "register_operand" "=d")
10049 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10050 ""
10051 "#"
10052 ""
10053 [(set (match_dup 3)
10054 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10055 (set (pc)
10056 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10057 (label_ref (match_dup 2))
10058 (pc)))]
10059 "")
10061 ; Non-constrained transaction begin
10063 (define_expand "tbegin"
10064 [(match_operand:SI 0 "register_operand" "")
10065 (match_operand:BLK 1 "memory_operand" "")]
10066 "TARGET_HTM"
10067 {
10068 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10069 DONE;
10070 })
10072 (define_expand "tbegin_nofloat"
10073 [(match_operand:SI 0 "register_operand" "")
10074 (match_operand:BLK 1 "memory_operand" "")]
10075 "TARGET_HTM"
10076 {
10077 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10078 DONE;
10079 })
10081 (define_expand "tbegin_retry"
10082 [(match_operand:SI 0 "register_operand" "")
10083 (match_operand:BLK 1 "memory_operand" "")
10084 (match_operand:SI 2 "general_operand" "")]
10085 "TARGET_HTM"
10086 {
10087 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10088 DONE;
10089 })
10091 (define_expand "tbegin_retry_nofloat"
10092 [(match_operand:SI 0 "register_operand" "")
10093 (match_operand:BLK 1 "memory_operand" "")
10094 (match_operand:SI 2 "general_operand" "")]
10095 "TARGET_HTM"
10096 {
10097 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10098 DONE;
10099 })
10101 (define_insn "tbegin_1"
10102 [(set (reg:CCRAW CC_REGNUM)
10103 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10104 UNSPECV_TBEGIN))
10105 (set (match_operand:BLK 1 "memory_operand" "=Q")
10106 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10107 (clobber (reg:DF 16))
10108 (clobber (reg:DF 17))
10109 (clobber (reg:DF 18))
10110 (clobber (reg:DF 19))
10111 (clobber (reg:DF 20))
10112 (clobber (reg:DF 21))
10113 (clobber (reg:DF 22))
10114 (clobber (reg:DF 23))
10115 (clobber (reg:DF 24))
10116 (clobber (reg:DF 25))
10117 (clobber (reg:DF 26))
10118 (clobber (reg:DF 27))
10119 (clobber (reg:DF 28))
10120 (clobber (reg:DF 29))
10121 (clobber (reg:DF 30))
10122 (clobber (reg:DF 31))]
10123 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10124 ; not supposed to be used for immediates (see genpreds.c).
10125 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10126 "tbegin\t%1,%x0"
10127 [(set_attr "op_type" "SIL")])
10129 ; Same as above but without the FPR clobbers
10130 (define_insn "tbegin_nofloat_1"
10131 [(set (reg:CCRAW CC_REGNUM)
10132 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10133 UNSPECV_TBEGIN))
10134 (set (match_operand:BLK 1 "memory_operand" "=Q")
10135 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10136 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10137 "tbegin\t%1,%x0"
10138 [(set_attr "op_type" "SIL")])
10141 ; Constrained transaction begin
10143 (define_expand "tbeginc"
10144 [(set (reg:CCRAW CC_REGNUM)
10145 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10146 UNSPECV_TBEGINC))]
10147 "TARGET_HTM"
10148 "")
10150 (define_insn "*tbeginc_1"
10151 [(set (reg:CCRAW CC_REGNUM)
10152 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10153 UNSPECV_TBEGINC))]
10154 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10155 "tbeginc\t0,%x0"
10156 [(set_attr "op_type" "SIL")])
10158 ; Transaction end
10160 (define_expand "tend"
10161 [(set (reg:CCRAW CC_REGNUM)
10162 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10163 (set (match_operand:SI 0 "register_operand" "")
10164 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10165 "TARGET_HTM"
10166 "")
10168 (define_insn "*tend_1"
10169 [(set (reg:CCRAW CC_REGNUM)
10170 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10171 "TARGET_HTM"
10172 "tend"
10173 [(set_attr "op_type" "S")])
10175 ; Transaction abort
10177 (define_expand "tabort"
10178 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10179 UNSPECV_TABORT)]
10180 "TARGET_HTM && operands != NULL"
10181 {
10182 if (CONST_INT_P (operands[0])
10183 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10184 {
10185 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10186 ". Values in range 0 through 255 are reserved.",
10187 INTVAL (operands[0]));
10188 FAIL;
10189 }
10190 })
10192 (define_insn "*tabort_1"
10193 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10194 UNSPECV_TABORT)]
10195 "TARGET_HTM && operands != NULL"
10196 "tabort\t%Y0"
10197 [(set_attr "op_type" "S")])
10199 ; Transaction extract nesting depth
10201 (define_insn "etnd"
10202 [(set (match_operand:SI 0 "register_operand" "=d")
10203 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10204 "TARGET_HTM"
10205 "etnd\t%0"
10206 [(set_attr "op_type" "RRE")])
10208 ; Non-transactional store
10210 (define_insn "ntstg"
10211 [(set (match_operand:DI 0 "memory_operand" "=RT")
10212 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10213 UNSPECV_NTSTG))]
10214 "TARGET_HTM"
10215 "ntstg\t%1,%0"
10216 [(set_attr "op_type" "RXY")])
10218 ; Transaction perform processor assist
10220 (define_expand "tx_assist"
10221 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10222 (reg:SI GPR0_REGNUM)
10223 (const_int 1)]
10224 UNSPECV_PPA)]
10225 "TARGET_HTM"
10226 "")
10228 (define_insn "*ppa"
10229 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10230 (match_operand:SI 1 "register_operand" "d")
10231 (match_operand 2 "const_int_operand" "I")]
10232 UNSPECV_PPA)]
10233 "TARGET_HTM && INTVAL (operands[2]) < 16"
10234 "ppa\t%0,%1,%2"
10235 [(set_attr "op_type" "RRF")])