1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
25 ;; reload. This will be fixed once scheduling support is turned on.
27 ;; ??? Optimize for post-increment addressing modes.
29 ;; ??? fselect is not supported, because there is no integer register
32 ;; ??? fp abs/min/max instructions may also work for integer values.
34 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
35 ;; it assumes the operand is a register and takes REGNO of it without checking.
37 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
38 ;; it assumes the operand is a register and takes REGNO of it without checking.
40 ;; ??? Go through list of documented named patterns and look for more to
43 ;; ??? Go through instruction manual and look for more instructions that
46 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
48 ;; ??? Need a better way to describe alternate fp status registers.
50 (define_c_enum "unspec"
64 UNSPEC_FR_RECIP_APPROX
75 UNSPEC_BUNDLE_SELECTOR
80 UNSPEC_FR_SQRT_RECIP_APPROX
93 UNSPEC_FR_RECIP_APPROX_RES
94 UNSPEC_FR_SQRT_RECIP_APPROX_RES
97 (define_c_enum "unspecv" [
100 UNSPECV_INSN_GROUP_BARRIER
103 UNSPECV_PSAC_ALL ; pred.safe_across_calls
105 UNSPECV_SETJMP_RECEIVER
106 UNSPECV_GOTO_RECEIVER
107 UNSPECV_PROBE_STACK_ADDRESS
108 UNSPECV_PROBE_STACK_RANGE
111 (include "predicates.md")
112 (include "constraints.md")
114 ;; ::::::::::::::::::::
118 ;; ::::::::::::::::::::
120 ;; Processor type. This attribute must exactly match the processor_type
121 ;; enumeration in ia64.h.
122 (define_attr "cpu" "itanium,itanium2"
123 (const (symbol_ref "((enum attr_cpu) ia64_tune)")))
125 ;; Instruction type. This primarily determines how instructions can be
126 ;; packed in bundles, and secondarily affects scheduling to function units.
128 ;; A alu, can go in I or M syllable of a bundle
133 ;; L long immediate, takes two syllables
136 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
137 ;; check this in md_reorg? Currently use unknown for patterns which emit
138 ;; multiple instructions, patterns which emit 0 instructions, and patterns
139 ;; which emit instruction that can go in any slot (e.g. nop).
141 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
142 fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
143 ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
144 st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
145 nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
146 (const_string "unknown"))
148 ;; chk_s_i has an I and an M form; use type A for convenience.
149 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
150 (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
151 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
152 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
153 (eq_attr "itanium_class" "lfetch") (const_string "M")
154 (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M")
155 (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua")
157 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
158 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
159 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
160 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
161 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
162 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
163 (eq_attr "itanium_class" "stop_bit") (const_string "S")
164 (eq_attr "itanium_class" "nop_x") (const_string "X")
165 (eq_attr "itanium_class" "long_i") (const_string "L")]
166 (const_string "unknown")))
168 (define_attr "itanium_requires_unit0" "no,yes"
169 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
170 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
171 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
172 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
173 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
174 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
175 (const_string "no")))
177 ;; Predication. True iff this instruction can be predicated.
179 (define_attr "predicable" "no,yes" (const_string "yes"))
181 ;; Empty. True iff this insn does not generate any code.
183 (define_attr "empty" "no,yes" (const_string "no"))
185 ;; True iff this insn must be the first insn of an instruction group.
186 ;; This is true for the alloc instruction, and will also be true of others
187 ;; when we have full intrinsics support.
189 (define_attr "first_insn" "no,yes" (const_string "no"))
191 (define_attr "data_speculative" "no,yes" (const_string "no"))
193 (define_attr "control_speculative" "no,yes" (const_string "no"))
195 (define_attr "check_load" "no,yes" (const_string "no"))
197 (define_attr "speculable1" "no,yes" (const_string "no"))
199 (define_attr "speculable2" "no,yes" (const_string "no"))
201 ;; DFA descriptions of ia64 processors used for insn scheduling and
204 (automata_option "ndfa")
206 ;; Uncomment the following line to output automata for debugging.
207 ;; (automata_option "v")
209 (automata_option "w")
211 (include "itanium2.md")
215 ; Used for truncations from XFmode.
216 (define_mode_iterator MODE_SDF [SF DF])
218 (define_mode_attr suffix [
224 ;; ::::::::::::::::::::
228 ;; ::::::::::::::::::::
230 ;; Set of a single predicate register. This is only used to implement
231 ;; pr-to-pr move and complement.
233 (define_insn "movcci"
234 [(set (match_operand:CCI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*m,*r")
235 (match_operand:CCI 1 "move_operand" " O,n, c, c,*r,*m,*r,*r"))]
238 cmp.ne %0, p0 = r0, r0
239 cmp.eq %0, p0 = r0, r0
240 (%1) cmp.eq.unc %0, p0 = r0, r0
242 tbit.nz %0, p0 = %1, 0
246 [(set_attr "itanium_class" "icmp,icmp,icmp,unknown,tbit,ld,st,ialu")
247 (set_attr "predicable" "no")])
250 [(set (match_operand:CCI 0 "register_operand" "")
251 (match_operand:CCI 1 "register_operand" ""))]
253 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
254 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
255 [(set (match_dup 2) (const_int 0))
256 (cond_exec (ne (match_dup 3) (const_int 0))
257 (set (match_dup 2) (const_int 1)))]
258 "operands[2] = gen_rtx_REG (BImode, REGNO (operands[0]));
259 operands[3] = gen_rtx_REG (BImode, REGNO (operands[1]));")
262 [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
263 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
266 cmp.ne %0, %I0 = r0, r0
267 cmp.eq %0, %I0 = r0, r0
270 tbit.nz %0, %I0 = %1, 0
275 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
276 (set_attr "speculable1" "yes")
277 (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")])
280 [(set (match_operand:BI 0 "register_operand" "")
281 (match_operand:BI 1 "register_operand" ""))]
283 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
284 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
285 [(cond_exec (ne (match_dup 1) (const_int 0))
286 (set (match_dup 0) (const_int 1)))
287 (cond_exec (eq (match_dup 1) (const_int 0))
288 (set (match_dup 0) (const_int 0)))]
292 [(set (match_operand:BI 0 "register_operand" "")
293 (match_operand:BI 1 "register_operand" ""))]
295 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
296 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
297 [(set (match_dup 2) (match_dup 4))
298 (set (match_dup 3) (match_dup 5))
299 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
300 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
301 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
302 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
303 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
305 (define_expand "movqi"
306 [(set (match_operand:QI 0 "general_operand" "")
307 (match_operand:QI 1 "general_operand" ""))]
310 rtx op1 = ia64_expand_move (operands[0], operands[1]);
316 (define_insn "movqi_internal"
317 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
318 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
319 "ia64_move_ok (operands[0], operands[1])"
328 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
329 (set_attr "speculable1" "yes")
330 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
332 (define_expand "movhi"
333 [(set (match_operand:HI 0 "general_operand" "")
334 (match_operand:HI 1 "general_operand" ""))]
337 rtx op1 = ia64_expand_move (operands[0], operands[1]);
343 (define_insn "movhi_internal"
344 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
345 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
346 "ia64_move_ok (operands[0], operands[1])"
355 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
356 (set_attr "speculable1" "yes")
357 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
359 (define_expand "movsi"
360 [(set (match_operand:SI 0 "general_operand" "")
361 (match_operand:SI 1 "general_operand" ""))]
364 rtx op1 = ia64_expand_move (operands[0], operands[1]);
370 (define_insn "movsi_internal"
371 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
372 (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
373 "ia64_move_ok (operands[0], operands[1])"
377 addp4 %0 = %1 - 0x100000000, r0
386 ;; frar_m, toar_m ??? why not frar_i and toar_i
387 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
388 (set_attr "speculable1" "yes")
389 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")])
391 (define_expand "movdi"
392 [(set (match_operand:DI 0 "general_operand" "")
393 (match_operand:DI 1 "general_operand" ""))]
396 rtx op1 = ia64_expand_move (operands[0], operands[1]);
402 (define_insn "movdi_internal"
403 [(set (match_operand:DI 0 "destination_operand"
404 "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
405 (match_operand:DI 1 "move_operand"
406 "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
407 "ia64_move_ok (operands[0], operands[1])"
409 static const char * const alt[] = {
411 "%,addl %0 = %1, r0",
412 "%,addp4 %0 = %1 - 0x100000000, r0",
414 "%,ld8%O1 %0 = %1%P1",
415 "%,st8%Q0 %0 = %r1%P0",
416 "%,getf.sig %0 = %1",
417 "%,setf.sig %0 = %r1",
431 gcc_assert (which_alternative != 2 || TARGET_NO_PIC
432 || !symbolic_operand (operands[1], VOIDmode));
434 return alt[which_alternative];
436 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
437 (set_attr "speculable1" "yes")
438 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
440 (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
441 (define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")])
442 (define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
444 (define_mode_attr output_a [
445 (BI "ld1.a %0 = %1%P1")
446 (QI "ld1.a %0 = %1%P1")
447 (HI "ld2.a %0 = %1%P1")
448 (SI "ld4.a %0 = %1%P1")
461 (XF "ldfe.a %0 = %1%P1")
462 (TI "ldfp8.a %X0 = %1%P1")])
464 (define_mode_attr output_s [
465 (BI "ld1.s %0 = %1%P1")
466 (QI "ld1.s %0 = %1%P1")
467 (HI "ld2.s %0 = %1%P1")
468 (SI "ld4.s %0 = %1%P1")
481 (XF "ldfe.s %0 = %1%P1")
482 (TI "ldfp8.s %X0 = %1%P1")])
484 (define_mode_attr output_sa [
485 (BI "ld1.sa %0 = %1%P1")
486 (QI "ld1.sa %0 = %1%P1")
487 (HI "ld2.sa %0 = %1%P1")
488 (SI "ld4.sa %0 = %1%P1")
501 (XF "ldfe.sa %0 = %1%P1")
502 (TI "ldfp8.sa %X0 = %1%P1")])
504 (define_mode_attr output_c_clr [
505 (BI "ld1.c.clr%O1 %0 = %1%P1")
506 (QI "ld1.c.clr%O1 %0 = %1%P1")
507 (HI "ld2.c.clr%O1 %0 = %1%P1")
508 (SI "ld4.c.clr%O1 %0 = %1%P1")
511 ld8.c.clr%O1 %0 = %1%P1
512 ldf8.c.clr %0 = %1%P1")
515 ldfs.c.clr %0 = %1%P1
516 ld4.c.clr%O1 %0 = %1%P1")
519 ldfd.c.clr %0 = %1%P1
520 ld8.c.clr%O1 %0 = %1%P1")
521 (XF "ldfe.c.clr %0 = %1%P1")
522 (TI "ldfp8.c.clr %X0 = %1%P1")])
524 (define_mode_attr output_c_nc [
525 (BI "ld1.c.nc%O1 %0 = %1%P1")
526 (QI "ld1.c.nc%O1 %0 = %1%P1")
527 (HI "ld2.c.nc%O1 %0 = %1%P1")
528 (SI "ld4.c.nc%O1 %0 = %1%P1")
531 ld8.c.nc%O1 %0 = %1%P1
532 ldf8.c.nc %0 = %1%P1")
536 ld4.c.nc%O1 %0 = %1%P1")
540 ld8.c.nc%O1 %0 = %1%P1")
541 (XF "ldfe.c.nc %0 = %1%P1")
542 (TI "ldfp8.c.nc %X0 = %1%P1")])
544 (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
545 (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
546 (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
548 (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")])
550 ;; Define register predicate prefix.
551 ;; We can generate speculative loads only for general and fp registers - this
552 ;; is constrained in ia64.c: ia64_speculate_insn ().
553 (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
555 (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
556 (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")])
557 (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")])
559 (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")])
561 (define_insn "mov<mode>_advanced"
562 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
563 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))]
564 "ia64_move_ok (operands[0], operands[1])"
566 [(set_attr "itanium_class" "<ld_class>")
567 (set_attr "data_speculative" "<attr_yes>")])
569 (define_insn "zero_extend<mode>di2_advanced"
570 [(set (match_operand:DI 0 "gr_register_operand" "=r")
571 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))]
574 [(set_attr "itanium_class" "<ld_class>")
575 (set_attr "data_speculative" "<attr_yes>")])
577 (define_insn "mov<mode>_speculative"
578 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
579 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))]
580 "ia64_move_ok (operands[0], operands[1])"
582 [(set_attr "itanium_class" "<ld_class>")
583 (set_attr "control_speculative" "<attr_yes>")])
585 (define_insn "zero_extend<mode>di2_speculative"
586 [(set (match_operand:DI 0 "gr_register_operand" "=r")
587 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))]
590 [(set_attr "itanium_class" "<ld_class>")
591 (set_attr "control_speculative" "<attr_yes>")])
593 (define_insn "mov<mode>_speculative_advanced"
594 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
595 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))]
596 "ia64_move_ok (operands[0], operands[1])"
598 [(set_attr "itanium_class" "<ld_class>")
599 (set_attr "data_speculative" "<attr_yes>")
600 (set_attr "control_speculative" "<attr_yes>")])
602 (define_insn "mov<mode>_speculative_a"
603 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
604 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
605 "ia64_move_ok (operands[0], operands[1])"
607 [(set_attr "itanium_class" "<ld_class>")
608 (set_attr "data_speculative" "<attr_yes>")
609 (set_attr "control_speculative" "<attr_yes>")])
611 (define_insn "zero_extend<mode>di2_speculative_advanced"
612 [(set (match_operand:DI 0 "gr_register_operand" "=r")
613 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
616 [(set_attr "itanium_class" "<ld_class>")
617 (set_attr "data_speculative" "<attr_yes>")
618 (set_attr "control_speculative" "<attr_yes>")])
620 (define_insn "zero_extend<mode>di2_speculative_a"
621 [(set (match_operand:DI 0 "gr_register_operand" "=r")
622 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
625 [(set_attr "itanium_class" "<ld_class>")
626 (set_attr "data_speculative" "<attr_yes>")
627 (set_attr "control_speculative" "<attr_yes>")])
629 (define_insn "mov<mode>_clr"
630 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
631 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
632 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
634 "ia64_move_ok (operands[0], operands[1])"
636 [(set_attr "itanium_class" "<ld_class>")
637 (set_attr "check_load" "<attr_yes>")])
639 (define_insn "mov<mode>_nc"
640 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
641 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
642 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
644 "ia64_move_ok (operands[0], operands[1])"
646 [(set_attr "itanium_class" "<ld_class>")
647 (set_attr "check_load" "<attr_yes>")])
649 (define_insn "zero_extend<mode>di2_clr"
650 [(set (match_operand:DI 0 "gr_register_operand" "+r")
651 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
652 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
656 [(set_attr "itanium_class" "<ld_class>")
657 (set_attr "check_load" "<attr_yes>")])
659 (define_insn "zero_extend<mode>di2_nc"
660 [(set (match_operand:DI 0 "gr_register_operand" "+r")
661 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
662 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
666 [(set_attr "itanium_class" "<ld_class>")
667 (set_attr "check_load" "<attr_yes>")])
669 (define_insn "advanced_load_check_clr_<mode>"
671 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
673 (label_ref (match_operand 1 "" ""))))]
676 [(set_attr "itanium_class" "<chka_class>")])
678 (define_insn "advanced_load_check_nc_<mode>"
680 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
682 (label_ref (match_operand 1 "" ""))))]
685 [(set_attr "itanium_class" "<chka_class>")])
687 (define_insn "speculation_check_<mode>"
689 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
691 (label_ref (match_operand 1 "" ""))))]
694 [(set_attr "itanium_class" "<chks_class>")])
697 [(set (match_operand 0 "register_operand" "")
698 (match_operand 1 "symbolic_operand" ""))]
702 if (ia64_expand_load_address (operands[0], operands[1]))
708 (define_expand "load_fptr"
709 [(set (match_operand:DI 0 "register_operand" "")
710 (plus:DI (match_dup 2) (match_operand 1 "function_operand" "")))
711 (set (match_dup 0) (match_dup 3))]
714 operands[2] = pic_offset_table_rtx;
715 operands[3] = gen_const_mem (DImode, operands[0]);
718 (define_insn "*load_fptr_internal1"
719 [(set (match_operand:DI 0 "register_operand" "=r")
720 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
722 "addl %0 = @ltoff(@fptr(%1)), gp"
723 [(set_attr "itanium_class" "ialu")])
725 (define_insn "load_gprel"
726 [(set (match_operand:DI 0 "register_operand" "=r")
727 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
729 "addl %0 = @gprel(%1), gp"
730 [(set_attr "itanium_class" "ialu")])
732 (define_insn "*gprel64_offset"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
736 "movl %0 = @gprel(%1)"
737 [(set_attr "itanium_class" "long_i")])
739 (define_expand "load_gprel64"
740 [(set (match_operand:DI 0 "register_operand" "")
741 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
743 (plus:DI (match_dup 2) (match_dup 0)))]
746 operands[2] = pic_offset_table_rtx;
749 ;; This is used as a placeholder for the return address during early
750 ;; compilation. We won't know where we've placed this until during
751 ;; reload, at which point it can wind up in b0, a general register,
752 ;; or memory. The only safe destination under these conditions is a
755 (define_insn_and_split "*movdi_ret_addr"
756 [(set (match_operand:DI 0 "register_operand" "=r")
757 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
763 ia64_split_return_addr_rtx (operands[0]);
766 [(set_attr "itanium_class" "ialu")])
768 (define_insn "*load_symptr_high"
769 [(set (match_operand:DI 0 "register_operand" "=r")
770 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
771 (match_operand:DI 2 "register_operand" "a")))]
774 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
775 return "%,addl %0 = @ltoffx(%1), %2";
777 return "%,addl %0 = @ltoff(%1), %2";
779 [(set_attr "itanium_class" "ialu")])
781 (define_insn "*load_symptr_low"
782 [(set (match_operand:DI 0 "register_operand" "=r")
783 (lo_sum:DI (mem:DI (match_operand:DI 1 "register_operand" "r"))
784 (match_operand 2 "got_symbolic_operand" "s")))]
787 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
788 return "%,ld8.mov %0 = [%1], %2";
790 return "%,ld8 %0 = [%1]";
792 [(set_attr "itanium_class" "ld")])
794 (define_insn_and_split "load_dtpmod"
795 [(set (match_operand:DI 0 "register_operand" "=r")
796 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
802 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
804 (set (match_dup 0) (match_dup 3))]
806 operands[2] = pic_offset_table_rtx;
807 operands[3] = gen_const_mem (DImode, operands[0]);
810 (define_insn "*load_ltoff_dtpmod"
811 [(set (match_operand:DI 0 "register_operand" "=r")
812 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
814 (match_operand:DI 2 "register_operand" "a")))]
816 "addl %0 = @ltoff(@dtpmod(%1)), %2"
817 [(set_attr "itanium_class" "ialu")])
819 (define_expand "load_dtprel"
820 [(set (match_operand:DI 0 "register_operand" "")
821 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
826 (define_insn "*load_dtprel64"
827 [(set (match_operand:DI 0 "register_operand" "=r")
828 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
831 "movl %0 = @dtprel(%1)"
832 [(set_attr "itanium_class" "long_i")])
834 (define_insn "*load_dtprel22"
835 [(set (match_operand:DI 0 "register_operand" "=r")
836 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
839 "addl %0 = @dtprel(%1), r0"
840 [(set_attr "itanium_class" "ialu")])
842 (define_insn_and_split "*load_dtprel_gd"
843 [(set (match_operand:DI 0 "register_operand" "=r")
844 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
850 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
852 (set (match_dup 0) (match_dup 3))]
854 operands[2] = pic_offset_table_rtx;
855 operands[3] = gen_const_mem (DImode, operands[0]);
858 (define_insn "*load_ltoff_dtprel"
859 [(set (match_operand:DI 0 "register_operand" "=r")
860 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
862 (match_operand:DI 2 "register_operand" "a")))]
864 "addl %0 = @ltoff(@dtprel(%1)), %2"
865 [(set_attr "itanium_class" "ialu")])
867 (define_expand "add_dtprel"
868 [(set (match_operand:DI 0 "register_operand" "")
869 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
871 (match_operand:DI 2 "register_operand" "")))]
875 (define_insn "*add_dtprel14"
876 [(set (match_operand:DI 0 "register_operand" "=r")
877 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
879 (match_operand:DI 2 "register_operand" "r")))]
881 "adds %0 = @dtprel(%1), %2"
882 [(set_attr "itanium_class" "ialu")])
884 (define_insn "*add_dtprel22"
885 [(set (match_operand:DI 0 "register_operand" "=r")
886 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
888 (match_operand:DI 2 "register_operand" "a")))]
890 "addl %0 = @dtprel(%1), %2"
891 [(set_attr "itanium_class" "ialu")])
893 (define_expand "load_tprel"
894 [(set (match_operand:DI 0 "register_operand" "")
895 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
900 (define_insn "*load_tprel64"
901 [(set (match_operand:DI 0 "register_operand" "=r")
902 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
905 "movl %0 = @tprel(%1)"
906 [(set_attr "itanium_class" "long_i")])
908 (define_insn "*load_tprel22"
909 [(set (match_operand:DI 0 "register_operand" "=r")
910 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
913 "addl %0 = @tprel(%1), r0"
914 [(set_attr "itanium_class" "ialu")])
916 (define_insn_and_split "*load_tprel_ie"
917 [(set (match_operand:DI 0 "register_operand" "=r")
918 (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
924 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
926 (set (match_dup 0) (match_dup 3))]
928 operands[2] = pic_offset_table_rtx;
929 operands[3] = gen_const_mem (DImode, operands[0]);
932 (define_insn "*load_ltoff_tprel"
933 [(set (match_operand:DI 0 "register_operand" "=r")
934 (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
936 (match_operand:DI 2 "register_operand" "a")))]
938 "addl %0 = @ltoff(@tprel(%1)), %2"
939 [(set_attr "itanium_class" "ialu")])
941 (define_expand "add_tprel"
942 [(set (match_operand:DI 0 "register_operand" "")
943 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
945 (match_operand:DI 2 "register_operand" "")))]
949 (define_insn "*add_tprel14"
950 [(set (match_operand:DI 0 "register_operand" "=r")
951 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
953 (match_operand:DI 2 "register_operand" "r")))]
955 "adds %0 = @tprel(%1), %2"
956 [(set_attr "itanium_class" "ialu")])
958 (define_insn "*add_tprel22"
959 [(set (match_operand:DI 0 "register_operand" "=r")
960 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
962 (match_operand:DI 2 "register_operand" "a")))]
964 "addl %0 = @tprel(%1), %2"
965 [(set_attr "itanium_class" "ialu")])
967 ;; With no offsettable memory references, we've got to have a scratch
968 ;; around to play with the second word. However, in order to avoid a
969 ;; reload nightmare we lie, claim we don't need one, and fix it up
970 ;; in ia64_split_tmode_move.
971 (define_expand "movti"
972 [(set (match_operand:TI 0 "general_operand" "")
973 (match_operand:TI 1 "general_operand" ""))]
976 rtx op1 = ia64_expand_move (operands[0], operands[1]);
982 (define_insn_and_split "movti_internal"
983 [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
984 (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
985 "ia64_move_ok (operands[0], operands[1])"
992 "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
995 ia64_split_tmode_move (operands);
998 [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
999 (set_attr "speculable1" "yes")
1000 (set_attr "speculable2" "no, no, yes, no, no")])
1002 ;; Floating Point Moves
1004 ;; Note - Patterns for SF mode moves are compulsory, but
1005 ;; patterns for DF are optional, as GCC can synthesize them.
1007 (define_expand "movsf"
1008 [(set (match_operand:SF 0 "general_operand" "")
1009 (match_operand:SF 1 "general_operand" ""))]
1012 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1018 (define_insn "movsf_internal"
1019 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
1020 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
1021 "ia64_move_ok (operands[0], operands[1])"
1032 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
1033 (set_attr "speculable1" "yes")
1034 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
1036 (define_expand "movdf"
1037 [(set (match_operand:DF 0 "general_operand" "")
1038 (match_operand:DF 1 "general_operand" ""))]
1041 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1047 (define_insn "movdf_internal"
1048 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
1049 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
1050 "ia64_move_ok (operands[0], operands[1])"
1061 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
1062 (set_attr "speculable1" "yes")
1063 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
1065 ;; With no offsettable memory references, we've got to have a scratch
1066 ;; around to play with the second word if the variable winds up in GRs.
1067 (define_expand "movxf"
1068 [(set (match_operand:XF 0 "general_operand" "")
1069 (match_operand:XF 1 "general_operand" ""))]
1072 if (ia64_expand_movxf_movrf (XFmode, operands))
1076 ;; ??? There's no easy way to mind volatile acquire/release semantics.
1078 (define_insn "movxf_internal"
1079 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
1080 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
1081 "ia64_move_ok (operands[0], operands[1])"
1086 [(set_attr "itanium_class" "fmisc,fld,stf")
1087 (set_attr "speculable1" "yes")
1088 (set_attr "speculable2" "no, yes,no")])
1090 ;; Same as for movxf, but for RFmode.
1091 (define_expand "movrf"
1092 [(set (match_operand:RF 0 "general_operand" "")
1093 (match_operand:RF 1 "general_operand" ""))]
1096 if (ia64_expand_movxf_movrf (RFmode, operands))
1100 (define_insn "*movrf_internal"
1101 [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
1102 (match_operand:RF 1 "general_operand" "fG,m,fG"))]
1103 "ia64_move_ok (operands[0], operands[1])"
1107 stf.spill %0 = %F1%P0"
1108 [(set_attr "itanium_class" "fmisc,fld,stf")])
1110 ;; Better code generation via insns that deal with TFmode register pairs
1111 ;; directly. Same concerns apply as for TImode.
1112 (define_expand "movtf"
1113 [(set (match_operand:TF 0 "general_operand" "")
1114 (match_operand:TF 1 "general_operand" ""))]
1117 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1123 (define_insn_and_split "*movtf_internal"
1124 [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
1125 (match_operand:TF 1 "general_operand" "ri,m,r"))]
1126 "ia64_move_ok (operands[0], operands[1])"
1131 ia64_split_tmode_move (operands);
1134 [(set_attr "itanium_class" "unknown")
1135 (set_attr "predicable" "no")])
1138 ;; ::::::::::::::::::::
1142 ;; ::::::::::::::::::::
1144 ;; Signed conversions from a smaller integer to a larger integer
1146 (define_insn "extendqidi2"
1147 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1148 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1151 [(set_attr "itanium_class" "xtd")])
1153 (define_insn "extendhidi2"
1154 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1155 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1158 [(set_attr "itanium_class" "xtd")])
1160 (define_insn "extendsidi2"
1161 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1162 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1167 [(set_attr "itanium_class" "xtd,fmisc")])
1169 ;; Unsigned conversions from a smaller integer to a larger integer
1171 (define_insn "zero_extendqidi2"
1172 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1173 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1178 [(set_attr "itanium_class" "xtd,ld")
1179 (set_attr "speculable1" "yes")
1180 (set_attr "speculable2" "no, yes")])
1182 (define_insn "zero_extendhidi2"
1183 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1184 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1189 [(set_attr "itanium_class" "xtd,ld")
1190 (set_attr "speculable1" "yes")
1191 (set_attr "speculable2" "no, yes")])
1193 (define_insn "zero_extendsidi2"
1194 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1196 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1202 [(set_attr "itanium_class" "ialu,ld,fmisc")
1203 (set_attr "speculable1" "yes")
1204 (set_attr "speculable2" "no, yes,no")])
1206 ;; Convert between floating point types of different sizes.
1208 ;; At first glance, it would appear that emitting fnorm for an extending
1209 ;; conversion is unnecessary. However, the stf and getf instructions work
1210 ;; correctly only if the input is properly rounded for its type. In
1211 ;; particular, we get the wrong result for getf.d/stfd if the input is a
1212 ;; denorm single. Since we don't know what the next instruction will be, we
1213 ;; have to emit an fnorm.
1215 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1216 ;; when we can. Should probably use a scheme like has been proposed
1217 ;; for ia32 in dealing with operands that match unary operators. This
1218 ;; would let combine merge the thing into adjacent insns. See also how the
1219 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
1220 ;; se_register_operand.
1222 (define_insn "extendsfdf2"
1223 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1224 (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1227 [(set_attr "itanium_class" "fmac")])
1229 (define_insn "extendsfxf2"
1230 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1231 (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1234 [(set_attr "itanium_class" "fmac")])
1236 (define_insn "extenddfxf2"
1237 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1238 (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1241 [(set_attr "itanium_class" "fmac")])
1243 (define_insn "truncdfsf2"
1244 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1245 (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1248 [(set_attr "itanium_class" "fmac")])
1250 (define_insn "truncxfsf2"
1251 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1252 (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1255 [(set_attr "itanium_class" "fmac")])
1257 (define_insn "truncxfdf2"
1258 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1259 (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1262 [(set_attr "itanium_class" "fmac")])
1264 ;; Convert between signed integer types and floating point.
1266 (define_insn "floatdirf2"
1267 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1268 (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1271 [(set_attr "itanium_class" "fcvtfx")])
1273 (define_insn "floatdixf2"
1274 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1275 (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1278 [(set_attr "itanium_class" "fcvtfx")])
1280 (define_insn "fix_truncsfdi2"
1281 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1282 (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1284 "fcvt.fx.trunc %0 = %F1"
1285 [(set_attr "itanium_class" "fcvtfx")])
1287 (define_insn "fix_truncdfdi2"
1288 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1289 (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1291 "fcvt.fx.trunc %0 = %F1"
1292 [(set_attr "itanium_class" "fcvtfx")])
1294 (define_insn "fix_truncxfdi2"
1295 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1296 (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1298 "fcvt.fx.trunc %0 = %F1"
1299 [(set_attr "itanium_class" "fcvtfx")])
1301 (define_insn "fix_truncrfdi2"
1302 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1303 (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
1305 "fcvt.fx.trunc %0 = %F1"
1306 [(set_attr "itanium_class" "fcvtfx")])
1308 ;; Convert between unsigned integer types and floating point.
1310 (define_insn "floatunsdisf2"
1311 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1312 (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1314 "fcvt.xuf.s %0 = %F1"
1315 [(set_attr "itanium_class" "fcvtfx")])
1317 (define_insn "floatunsdidf2"
1318 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1319 (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1321 "fcvt.xuf.d %0 = %F1"
1322 [(set_attr "itanium_class" "fcvtfx")])
1324 (define_insn "floatunsdixf2"
1325 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1326 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1329 [(set_attr "itanium_class" "fcvtfx")])
1331 (define_insn "floatunsdirf2"
1332 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1333 (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1336 [(set_attr "itanium_class" "fcvtfx")])
1338 (define_insn "fixuns_truncsfdi2"
1339 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1340 (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1342 "fcvt.fxu.trunc %0 = %F1"
1343 [(set_attr "itanium_class" "fcvtfx")])
1345 (define_insn "fixuns_truncdfdi2"
1346 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1347 (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1349 "fcvt.fxu.trunc %0 = %F1"
1350 [(set_attr "itanium_class" "fcvtfx")])
1352 (define_insn "fixuns_truncxfdi2"
1353 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1354 (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1356 "fcvt.fxu.trunc %0 = %F1"
1357 [(set_attr "itanium_class" "fcvtfx")])
1359 (define_insn "fixuns_truncrfdi2"
1360 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1361 (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
1363 "fcvt.fxu.trunc %0 = %F1"
1364 [(set_attr "itanium_class" "fcvtfx")])
1366 ;; ::::::::::::::::::::
1368 ;; :: Bit field extraction
1370 ;; ::::::::::::::::::::
1373 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1374 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1375 (match_operand:DI 2 "extr_len_operand" "n")
1376 (match_operand:DI 3 "shift_count_operand" "M")))]
1378 "extr %0 = %1, %3, %2"
1379 [(set_attr "itanium_class" "ishf")])
1381 (define_insn "extzv"
1382 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1383 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1384 (match_operand:DI 2 "extr_len_operand" "n")
1385 (match_operand:DI 3 "shift_count_operand" "M")))]
1387 "extr.u %0 = %1, %3, %2"
1388 [(set_attr "itanium_class" "ishf")])
1390 ;; Insert a bit field.
1391 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1392 ;; Source1 can be 0 or -1.
1393 ;; Source2 can be 0.
1395 ;; ??? Actual dep instruction is more powerful than what these insv
1396 ;; patterns support. Unfortunately, combine is unable to create patterns
1397 ;; where source2 != dest.
1399 (define_expand "insv"
1400 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1401 (match_operand:DI 1 "const_int_operand" "")
1402 (match_operand:DI 2 "const_int_operand" ""))
1403 (match_operand:DI 3 "nonmemory_operand" ""))]
1406 int width = INTVAL (operands[1]);
1407 int shift = INTVAL (operands[2]);
1409 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1411 if (! register_operand (operands[3], DImode)
1412 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1413 operands[3] = force_reg (DImode, operands[3]);
1415 /* If this is a single dep instruction, we have nothing to do. */
1416 if (! ((register_operand (operands[3], DImode) && width <= 16)
1417 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1419 /* Check for cases that can be implemented with a mix instruction. */
1420 if (width == 32 && shift == 0)
1422 /* Directly generating the mix4left instruction confuses
1423 optimize_bit_field in function.c. Since this is performing
1424 a useful optimization, we defer generation of the complicated
1425 mix4left RTL to the first splitting phase. */
1426 rtx tmp = gen_reg_rtx (DImode);
1427 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1430 else if (width == 32 && shift == 32)
1432 emit_insn (gen_mix4right (operands[0], operands[3]));
1436 /* We could handle remaining cases by emitting multiple dep
1439 If we need more than two dep instructions then we lose. A 6
1440 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1441 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1442 the latter is 6 cycles on an Itanium (TM) processor, because there is
1443 only one function unit that can execute dep and shr immed.
1445 If we only need two dep instruction, then we still lose.
1446 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1447 the unnecessary mov, this is still undesirable because it will be
1448 hard to optimize, and it creates unnecessary pressure on the I0
1454 /* This code may be useful for other IA-64 processors, so we leave it in
1460 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1464 tmp = gen_reg_rtx (DImode);
1465 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1468 operands[1] = GEN_INT (width);
1469 operands[2] = GEN_INT (shift);
1474 (define_insn "*insv_internal"
1475 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1476 (match_operand:DI 1 "const_int_operand" "n")
1477 (match_operand:DI 2 "const_int_operand" "n"))
1478 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1479 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1480 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1481 "dep %0 = %3, %0, %2, %1"
1482 [(set_attr "itanium_class" "ishf")])
1484 ;; Combine doesn't like to create bit-field insertions into zero.
1485 (define_insn "*shladdp4_internal"
1486 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1487 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1488 (match_operand:DI 2 "shladd_log2_operand" "n"))
1489 (match_operand:DI 3 "const_int_operand" "n")))]
1490 "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
1491 "shladdp4 %0 = %1, %2, r0"
1492 [(set_attr "itanium_class" "ialu")])
1494 (define_insn "*depz_internal"
1495 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1496 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1497 (match_operand:DI 2 "const_int_operand" "M"))
1498 (match_operand:DI 3 "const_int_operand" "n")))]
1499 "satisfies_constraint_M (operands[2])
1500 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1502 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1503 return "%,dep.z %0 = %1, %2, %3";
1505 [(set_attr "itanium_class" "ishf")])
1507 (define_insn "shift_mix4left"
1508 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1509 (const_int 32) (const_int 0))
1510 (match_operand:DI 1 "gr_register_operand" "r"))
1511 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1514 [(set_attr "itanium_class" "unknown")])
1517 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1518 (const_int 32) (const_int 0))
1519 (match_operand:DI 1 "register_operand" ""))
1520 (clobber (match_operand:DI 2 "register_operand" ""))]
1522 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1523 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1524 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1525 "operands[3] = operands[2];")
1527 (define_insn "*mix4left"
1528 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1529 (const_int 32) (const_int 0))
1530 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1533 "mix4.l %0 = %0, %r1"
1534 [(set_attr "itanium_class" "mmshf")])
1536 (define_insn "mix4right"
1537 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1538 (const_int 32) (const_int 32))
1539 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1541 "mix4.r %0 = %r1, %0"
1542 [(set_attr "itanium_class" "mmshf")])
1544 ;; This is used by the rotrsi3 pattern.
1546 (define_insn "*mix4right_3op"
1547 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1548 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1549 (ashift:DI (zero_extend:DI
1550 (match_operand:SI 2 "gr_register_operand" "r"))
1553 "mix4.r %0 = %2, %1"
1554 [(set_attr "itanium_class" "mmshf")])
1557 ;; ::::::::::::::::::::
1559 ;; :: 1-bit Integer arithmetic
1561 ;; ::::::::::::::::::::
1563 (define_insn_and_split "andbi3"
1564 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1565 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1566 (match_operand:BI 2 "register_operand" "c,r,r")))]
1570 tbit.nz.and.orcm %0, %I0 = %2, 0
1573 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1574 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1575 [(cond_exec (eq (match_dup 2) (const_int 0))
1576 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1579 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1581 (define_insn_and_split "*andcmbi3"
1582 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1583 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1584 (match_operand:BI 2 "register_operand" "0,0,r")))]
1588 tbit.z.and.orcm %0, %I0 = %1, 0
1591 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1592 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1593 [(cond_exec (ne (match_dup 1) (const_int 0))
1594 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1597 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1599 (define_insn_and_split "iorbi3"
1600 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1601 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1602 (match_operand:BI 2 "register_operand" "c,r,r")))]
1606 tbit.nz.or.andcm %0, %I0 = %2, 0
1609 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1610 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1611 [(cond_exec (ne (match_dup 2) (const_int 0))
1612 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1615 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1617 (define_insn_and_split "*iorcmbi3"
1618 [(set (match_operand:BI 0 "register_operand" "=c,c")
1619 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1620 (match_operand:BI 2 "register_operand" "0,0")))]
1624 tbit.z.or.andcm %0, %I0 = %1, 0"
1626 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1627 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1628 [(cond_exec (eq (match_dup 1) (const_int 0))
1629 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1632 [(set_attr "itanium_class" "unknown,tbit")])
1634 (define_insn "one_cmplbi2"
1635 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1636 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1637 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1640 tbit.z %0, %I0 = %1, 0
1644 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1647 [(set (match_operand:BI 0 "register_operand" "")
1648 (not:BI (match_operand:BI 1 "register_operand" "")))
1649 (clobber (match_scratch:BI 2 ""))]
1651 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1652 && rtx_equal_p (operands[0], operands[1])"
1653 [(set (match_dup 4) (match_dup 3))
1654 (set (match_dup 0) (const_int 1))
1655 (cond_exec (ne (match_dup 2) (const_int 0))
1656 (set (match_dup 0) (const_int 0)))
1657 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1658 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1659 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1662 [(set (match_operand:BI 0 "register_operand" "")
1663 (not:BI (match_operand:BI 1 "register_operand" "")))
1664 (clobber (match_scratch:BI 2 ""))]
1666 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1667 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1668 && ! rtx_equal_p (operands[0], operands[1])"
1669 [(cond_exec (ne (match_dup 1) (const_int 0))
1670 (set (match_dup 0) (const_int 0)))
1671 (cond_exec (eq (match_dup 1) (const_int 0))
1672 (set (match_dup 0) (const_int 1)))
1673 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1676 (define_insn "*cmpsi_and_0"
1677 [(set (match_operand:BI 0 "register_operand" "=c")
1678 (and:BI (match_operator:BI 4 "predicate_operator"
1679 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1680 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1681 (match_operand:BI 1 "register_operand" "0")))]
1683 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1684 [(set_attr "itanium_class" "icmp")])
1686 (define_insn "*cmpsi_and_1"
1687 [(set (match_operand:BI 0 "register_operand" "=c")
1688 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1689 [(match_operand:SI 2 "gr_register_operand" "r")
1691 (match_operand:BI 1 "register_operand" "0")))]
1693 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1694 [(set_attr "itanium_class" "icmp")])
1696 (define_insn "*cmpsi_andnot_0"
1697 [(set (match_operand:BI 0 "register_operand" "=c")
1698 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1699 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1700 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1701 (match_operand:BI 1 "register_operand" "0")))]
1703 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1704 [(set_attr "itanium_class" "icmp")])
1706 (define_insn "*cmpsi_andnot_1"
1707 [(set (match_operand:BI 0 "register_operand" "=c")
1708 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1709 [(match_operand:SI 2 "gr_register_operand" "r")
1711 (match_operand:BI 1 "register_operand" "0")))]
1713 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1714 [(set_attr "itanium_class" "icmp")])
1716 (define_insn "*cmpdi_and_0"
1717 [(set (match_operand:BI 0 "register_operand" "=c")
1718 (and:BI (match_operator:BI 4 "predicate_operator"
1719 [(match_operand:DI 2 "gr_register_operand" "r")
1720 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1721 (match_operand:BI 1 "register_operand" "0")))]
1723 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1724 [(set_attr "itanium_class" "icmp")])
1726 (define_insn "*cmpdi_and_1"
1727 [(set (match_operand:BI 0 "register_operand" "=c")
1728 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1729 [(match_operand:DI 2 "gr_register_operand" "r")
1731 (match_operand:BI 1 "register_operand" "0")))]
1733 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1734 [(set_attr "itanium_class" "icmp")])
1736 (define_insn "*cmpdi_andnot_0"
1737 [(set (match_operand:BI 0 "register_operand" "=c")
1738 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1739 [(match_operand:DI 2 "gr_register_operand" "r")
1740 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1741 (match_operand:BI 1 "register_operand" "0")))]
1743 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1744 [(set_attr "itanium_class" "icmp")])
1746 (define_insn "*cmpdi_andnot_1"
1747 [(set (match_operand:BI 0 "register_operand" "=c")
1748 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1749 [(match_operand:DI 2 "gr_register_operand" "r")
1751 (match_operand:BI 1 "register_operand" "0")))]
1753 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1754 [(set_attr "itanium_class" "icmp")])
1756 (define_insn "*tbit_and_0"
1757 [(set (match_operand:BI 0 "register_operand" "=c")
1758 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1761 (match_operand:BI 2 "register_operand" "0")))]
1763 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1764 [(set_attr "itanium_class" "tbit")])
1766 (define_insn "*tbit_and_1"
1767 [(set (match_operand:BI 0 "register_operand" "=c")
1768 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1771 (match_operand:BI 2 "register_operand" "0")))]
1773 "tbit.z.and.orcm %0, %I0 = %1, 0"
1774 [(set_attr "itanium_class" "tbit")])
1776 (define_insn "*tbit_and_2"
1777 [(set (match_operand:BI 0 "register_operand" "=c")
1778 (and:BI (ne:BI (zero_extract:DI
1779 (match_operand:DI 1 "gr_register_operand" "r")
1781 (match_operand:DI 2 "shift_count_operand" "M"))
1783 (match_operand:BI 3 "register_operand" "0")))]
1785 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1786 [(set_attr "itanium_class" "tbit")])
1788 (define_insn "*tbit_and_3"
1789 [(set (match_operand:BI 0 "register_operand" "=c")
1790 (and:BI (eq:BI (zero_extract:DI
1791 (match_operand:DI 1 "gr_register_operand" "r")
1793 (match_operand:DI 2 "shift_count_operand" "M"))
1795 (match_operand:BI 3 "register_operand" "0")))]
1797 "tbit.z.and.orcm %0, %I0 = %1, %2"
1798 [(set_attr "itanium_class" "tbit")])
1800 (define_insn "*cmpsi_or_0"
1801 [(set (match_operand:BI 0 "register_operand" "=c")
1802 (ior:BI (match_operator:BI 4 "predicate_operator"
1803 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1804 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1805 (match_operand:BI 1 "register_operand" "0")))]
1807 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1808 [(set_attr "itanium_class" "icmp")])
1810 (define_insn "*cmpsi_or_1"
1811 [(set (match_operand:BI 0 "register_operand" "=c")
1812 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1813 [(match_operand:SI 2 "gr_register_operand" "r")
1815 (match_operand:BI 1 "register_operand" "0")))]
1817 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1818 [(set_attr "itanium_class" "icmp")])
1820 (define_insn "*cmpsi_orcm_0"
1821 [(set (match_operand:BI 0 "register_operand" "=c")
1822 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1823 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1824 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1825 (match_operand:BI 1 "register_operand" "0")))]
1827 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1828 [(set_attr "itanium_class" "icmp")])
1830 (define_insn "*cmpsi_orcm_1"
1831 [(set (match_operand:BI 0 "register_operand" "=c")
1832 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1833 [(match_operand:SI 2 "gr_register_operand" "r")
1835 (match_operand:BI 1 "register_operand" "0")))]
1837 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1838 [(set_attr "itanium_class" "icmp")])
1840 (define_insn "*cmpdi_or_0"
1841 [(set (match_operand:BI 0 "register_operand" "=c")
1842 (ior:BI (match_operator:BI 4 "predicate_operator"
1843 [(match_operand:DI 2 "gr_register_operand" "r")
1844 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1845 (match_operand:BI 1 "register_operand" "0")))]
1847 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1848 [(set_attr "itanium_class" "icmp")])
1850 (define_insn "*cmpdi_or_1"
1851 [(set (match_operand:BI 0 "register_operand" "=c")
1852 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1853 [(match_operand:DI 2 "gr_register_operand" "r")
1855 (match_operand:BI 1 "register_operand" "0")))]
1857 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1858 [(set_attr "itanium_class" "icmp")])
1860 (define_insn "*cmpdi_orcm_0"
1861 [(set (match_operand:BI 0 "register_operand" "=c")
1862 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1863 [(match_operand:DI 2 "gr_register_operand" "r")
1864 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1865 (match_operand:BI 1 "register_operand" "0")))]
1867 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1868 [(set_attr "itanium_class" "icmp")])
1870 (define_insn "*cmpdi_orcm_1"
1871 [(set (match_operand:BI 0 "register_operand" "=c")
1872 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1873 [(match_operand:DI 2 "gr_register_operand" "r")
1875 (match_operand:BI 1 "register_operand" "0")))]
1877 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1878 [(set_attr "itanium_class" "icmp")])
1880 (define_insn "*tbit_or_0"
1881 [(set (match_operand:BI 0 "register_operand" "=c")
1882 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1885 (match_operand:BI 2 "register_operand" "0")))]
1887 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1888 [(set_attr "itanium_class" "tbit")])
1890 (define_insn "*tbit_or_1"
1891 [(set (match_operand:BI 0 "register_operand" "=c")
1892 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1895 (match_operand:BI 2 "register_operand" "0")))]
1897 "tbit.z.or.andcm %0, %I0 = %1, 0"
1898 [(set_attr "itanium_class" "tbit")])
1900 (define_insn "*tbit_or_2"
1901 [(set (match_operand:BI 0 "register_operand" "=c")
1902 (ior:BI (ne:BI (zero_extract:DI
1903 (match_operand:DI 1 "gr_register_operand" "r")
1905 (match_operand:DI 2 "shift_count_operand" "M"))
1907 (match_operand:BI 3 "register_operand" "0")))]
1909 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1910 [(set_attr "itanium_class" "tbit")])
1912 (define_insn "*tbit_or_3"
1913 [(set (match_operand:BI 0 "register_operand" "=c")
1914 (ior:BI (eq:BI (zero_extract:DI
1915 (match_operand:DI 1 "gr_register_operand" "r")
1917 (match_operand:DI 2 "shift_count_operand" "M"))
1919 (match_operand:BI 3 "register_operand" "0")))]
1921 "tbit.z.or.andcm %0, %I0 = %1, %2"
1922 [(set_attr "itanium_class" "tbit")])
1924 ;; Transform test of and/or of setcc into parallel comparisons.
1927 [(set (match_operand:BI 0 "register_operand" "")
1928 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1930 (match_operand:DI 3 "register_operand" ""))
1934 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1939 [(set (match_operand:BI 0 "register_operand" "")
1940 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1942 (match_operand:DI 3 "register_operand" ""))
1946 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1948 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1949 (clobber (scratch))])]
1953 [(set (match_operand:BI 0 "register_operand" "")
1954 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1956 (match_operand:DI 3 "register_operand" ""))
1960 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1965 [(set (match_operand:BI 0 "register_operand" "")
1966 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1968 (match_operand:DI 3 "register_operand" ""))
1972 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1974 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1975 (clobber (scratch))])]
1978 ;; ??? Incredibly hackish. Either need four proper patterns with all
1979 ;; the alternatives, or rely on sched1 to split the insn and hope that
1980 ;; nothing bad happens to the comparisons in the meantime.
1982 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1983 ;; that we're doing height reduction.
1985 ;(define_insn_and_split ""
1986 ; [(set (match_operand:BI 0 "register_operand" "=c")
1987 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1988 ; [(match_operand 2 "" "")
1989 ; (match_operand 3 "" "")])
1990 ; (match_operator:BI 4 "comparison_operator"
1991 ; [(match_operand 5 "" "")
1992 ; (match_operand 6 "" "")]))
1994 ; "flag_schedule_insns"
1997 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1998 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
2001 ;(define_insn_and_split ""
2002 ; [(set (match_operand:BI 0 "register_operand" "=c")
2003 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2004 ; [(match_operand 2 "" "")
2005 ; (match_operand 3 "" "")])
2006 ; (match_operator:BI 4 "comparison_operator"
2007 ; [(match_operand 5 "" "")
2008 ; (match_operand 6 "" "")]))
2010 ; "flag_schedule_insns"
2013 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
2014 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
2018 ; [(set (match_operand:BI 0 "register_operand" "")
2019 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
2020 ; [(match_operand 2 "" "")
2021 ; (match_operand 3 "" "")])
2022 ; (match_operand:BI 7 "register_operand" ""))
2023 ; (and:BI (match_operator:BI 4 "comparison_operator"
2024 ; [(match_operand 5 "" "")
2025 ; (match_operand 6 "" "")])
2026 ; (match_operand:BI 8 "register_operand" ""))))]
2028 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
2029 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
2034 ; [(set (match_operand:BI 0 "register_operand" "")
2035 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2036 ; [(match_operand 2 "" "")
2037 ; (match_operand 3 "" "")])
2038 ; (match_operand:BI 7 "register_operand" ""))
2039 ; (ior:BI (match_operator:BI 4 "comparison_operator"
2040 ; [(match_operand 5 "" "")
2041 ; (match_operand 6 "" "")])
2042 ; (match_operand:BI 8 "register_operand" ""))))]
2044 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
2045 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
2049 ;; Try harder to avoid predicate copies by duplicating compares.
2050 ;; Note that we'll have already split the predicate copy, which
2051 ;; is kind of a pain, but oh well.
2054 [(set (match_operand:BI 0 "register_operand" "")
2055 (match_operand:BI 1 "comparison_operator" ""))
2056 (set (match_operand:CCI 2 "register_operand" "")
2057 (match_operand:CCI 3 "register_operand" ""))
2058 (set (match_operand:CCI 4 "register_operand" "")
2059 (match_operand:CCI 5 "register_operand" ""))
2060 (set (match_operand:BI 6 "register_operand" "")
2061 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
2062 "REGNO (operands[3]) == REGNO (operands[0])
2063 && REGNO (operands[4]) == REGNO (operands[0]) + 1
2064 && REGNO (operands[4]) == REGNO (operands[2]) + 1
2065 && REGNO (operands[6]) == REGNO (operands[2])"
2066 [(set (match_dup 0) (match_dup 1))
2067 (set (match_dup 6) (match_dup 7))]
2068 "operands[7] = copy_rtx (operands[1]);")
2070 ;; ::::::::::::::::::::
2072 ;; :: 16-bit Integer arithmetic
2074 ;; ::::::::::::::::::::
2076 (define_insn "mulhi3"
2077 [(set (match_operand:HI 0 "gr_register_operand" "=r")
2078 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
2079 (match_operand:HI 2 "gr_register_operand" "r")))]
2081 "pmpy2.r %0 = %1, %2"
2082 [(set_attr "itanium_class" "mmmul")])
2085 ;; ::::::::::::::::::::
2087 ;; :: 32-bit Integer arithmetic
2089 ;; ::::::::::::::::::::
2091 (define_insn "addsi3"
2092 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
2093 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
2094 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2100 [(set_attr "itanium_class" "ialu")])
2102 (define_insn "*addsi3_plus1"
2103 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2104 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
2105 (match_operand:SI 2 "gr_register_operand" "r"))
2108 "add %0 = %1, %2, 1"
2109 [(set_attr "itanium_class" "ialu")])
2111 (define_insn "*addsi3_plus1_alt"
2112 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2113 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2117 "add %0 = %1, %1, 1"
2118 [(set_attr "itanium_class" "ialu")])
2120 (define_insn "*addsi3_shladd"
2121 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2122 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2123 (match_operand:SI 2 "shladd_operand" "n"))
2124 (match_operand:SI 3 "gr_register_operand" "r")))]
2126 "shladd %0 = %1, %S2, %3"
2127 [(set_attr "itanium_class" "ialu")])
2129 (define_insn "subsi3"
2130 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2131 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
2132 (match_operand:SI 2 "gr_register_operand" "r")))]
2135 [(set_attr "itanium_class" "ialu")])
2137 (define_insn "*subsi3_minus1"
2138 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2139 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
2140 (match_operand:SI 2 "gr_register_operand" "r")))]
2142 "sub %0 = %2, %1, 1"
2143 [(set_attr "itanium_class" "ialu")])
2145 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
2147 (define_insn "mulsi3"
2148 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2149 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2150 (match_operand:SI 2 "grfr_register_operand" "f")))]
2152 "xmpy.l %0 = %1, %2"
2153 [(set_attr "itanium_class" "xmpy")])
2155 (define_insn "maddsi4"
2156 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2157 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2158 (match_operand:SI 2 "grfr_register_operand" "f"))
2159 (match_operand:SI 3 "grfr_register_operand" "f")))]
2161 "xma.l %0 = %1, %2, %3"
2162 [(set_attr "itanium_class" "xmpy")])
2164 (define_insn "negsi2"
2165 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2166 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2169 [(set_attr "itanium_class" "ialu")])
2171 (define_expand "abssi2"
2173 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2174 (set (match_operand:SI 0 "gr_register_operand" "")
2175 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2176 (neg:SI (match_dup 1))
2179 { operands[2] = gen_reg_rtx (BImode); })
2181 (define_expand "sminsi3"
2183 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2184 (match_operand:SI 2 "gr_register_operand" "")))
2185 (set (match_operand:SI 0 "gr_register_operand" "")
2186 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2187 (match_dup 2) (match_dup 1)))]
2189 { operands[3] = gen_reg_rtx (BImode); })
2191 (define_expand "smaxsi3"
2193 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2194 (match_operand:SI 2 "gr_register_operand" "")))
2195 (set (match_operand:SI 0 "gr_register_operand" "")
2196 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2197 (match_dup 1) (match_dup 2)))]
2199 { operands[3] = gen_reg_rtx (BImode); })
2201 (define_expand "uminsi3"
2203 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2204 (match_operand:SI 2 "gr_register_operand" "")))
2205 (set (match_operand:SI 0 "gr_register_operand" "")
2206 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2207 (match_dup 2) (match_dup 1)))]
2209 { operands[3] = gen_reg_rtx (BImode); })
2211 (define_expand "umaxsi3"
2213 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2214 (match_operand:SI 2 "gr_register_operand" "")))
2215 (set (match_operand:SI 0 "gr_register_operand" "")
2216 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2217 (match_dup 1) (match_dup 2)))]
2219 { operands[3] = gen_reg_rtx (BImode); })
2221 ;; ::::::::::::::::::::
2223 ;; :: 64-bit Integer arithmetic
2225 ;; ::::::::::::::::::::
2227 (define_insn "adddi3"
2228 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2229 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2230 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2236 [(set_attr "itanium_class" "ialu")])
2238 (define_insn "*adddi3_plus1"
2239 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2240 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2241 (match_operand:DI 2 "gr_register_operand" "r"))
2244 "add %0 = %1, %2, 1"
2245 [(set_attr "itanium_class" "ialu")])
2247 ;; This has some of the same problems as shladd. We let the shladd
2248 ;; eliminator hack handle it, which results in the 1 being forced into
2249 ;; a register, but not more ugliness here.
2250 (define_insn "*adddi3_plus1_alt"
2251 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2252 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2256 "add %0 = %1, %1, 1"
2257 [(set_attr "itanium_class" "ialu")])
2259 (define_insn "subdi3"
2260 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2261 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2262 (match_operand:DI 2 "gr_register_operand" "r")))]
2265 [(set_attr "itanium_class" "ialu")])
2267 (define_insn "*subdi3_minus1"
2268 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2269 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2270 (match_operand:DI 2 "gr_register_operand" "r")))]
2272 "sub %0 = %2, %1, 1"
2273 [(set_attr "itanium_class" "ialu")])
2275 ;; ??? Use grfr instead of fr because of virtual register elimination
2276 ;; and silly test cases multiplying by the frame pointer.
2277 (define_insn "muldi3"
2278 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2279 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2280 (match_operand:DI 2 "grfr_register_operand" "f")))]
2282 "xmpy.l %0 = %1, %2"
2283 [(set_attr "itanium_class" "xmpy")])
2285 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2286 ;; same problem that we have with shladd below. Unfortunately, this case is
2287 ;; much harder to fix because the multiply puts the result in an FP register,
2288 ;; but the add needs inputs from a general register. We add a spurious clobber
2289 ;; here so that it will be present just in case register elimination gives us
2290 ;; the funny result.
2292 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2294 ;; ??? Maybe we should change how adds are canonicalized.
2296 (define_insn "madddi4"
2297 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2298 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2299 (match_operand:DI 2 "grfr_register_operand" "f"))
2300 (match_operand:DI 3 "grfr_register_operand" "f")))
2301 (clobber (match_scratch:DI 4 "=X"))]
2303 "xma.l %0 = %1, %2, %3"
2304 [(set_attr "itanium_class" "xmpy")])
2306 ;; This can be created by register elimination if operand3 of shladd is an
2307 ;; eliminable register or has reg_equiv_constant set.
2309 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2310 ;; validate_changes call inside eliminate_regs will always succeed. If it
2311 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2314 (define_insn "*madddi4_elim"
2315 [(set (match_operand:DI 0 "register_operand" "=&r")
2316 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2317 (match_operand:DI 2 "register_operand" "f"))
2318 (match_operand:DI 3 "register_operand" "f"))
2319 (match_operand:DI 4 "nonmemory_operand" "rI")))
2320 (clobber (match_scratch:DI 5 "=f"))]
2321 "reload_in_progress"
2323 [(set_attr "itanium_class" "unknown")])
2326 [(set (match_operand:DI 0 "register_operand" "")
2327 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2328 (match_operand:DI 2 "register_operand" ""))
2329 (match_operand:DI 3 "register_operand" ""))
2330 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2331 (clobber (match_scratch:DI 5 ""))]
2333 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2335 (clobber (match_dup 0))])
2336 (set (match_dup 0) (match_dup 5))
2337 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2340 (define_insn "smuldi3_highpart"
2341 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2344 (mult:TI (sign_extend:TI
2345 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2347 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
2350 "xmpy.h %0 = %F1, %F2"
2351 [(set_attr "itanium_class" "xmpy")])
2353 (define_insn "umuldi3_highpart"
2354 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2357 (mult:TI (zero_extend:TI
2358 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2360 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
2363 "xmpy.hu %0 = %F1, %F2"
2364 [(set_attr "itanium_class" "xmpy")])
2366 (define_insn "negdi2"
2367 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2368 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2371 [(set_attr "itanium_class" "ialu")])
2373 (define_expand "absdi2"
2375 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2376 (set (match_operand:DI 0 "gr_register_operand" "")
2377 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2378 (neg:DI (match_dup 1))
2381 { operands[2] = gen_reg_rtx (BImode); })
2383 (define_expand "smindi3"
2385 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2386 (match_operand:DI 2 "gr_register_operand" "")))
2387 (set (match_operand:DI 0 "gr_register_operand" "")
2388 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2389 (match_dup 2) (match_dup 1)))]
2391 { operands[3] = gen_reg_rtx (BImode); })
2393 (define_expand "smaxdi3"
2395 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2396 (match_operand:DI 2 "gr_register_operand" "")))
2397 (set (match_operand:DI 0 "gr_register_operand" "")
2398 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2399 (match_dup 1) (match_dup 2)))]
2401 { operands[3] = gen_reg_rtx (BImode); })
2403 (define_expand "umindi3"
2405 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2406 (match_operand:DI 2 "gr_register_operand" "")))
2407 (set (match_operand:DI 0 "gr_register_operand" "")
2408 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2409 (match_dup 2) (match_dup 1)))]
2411 { operands[3] = gen_reg_rtx (BImode); })
2413 (define_expand "umaxdi3"
2415 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2416 (match_operand:DI 2 "gr_register_operand" "")))
2417 (set (match_operand:DI 0 "gr_register_operand" "")
2418 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2419 (match_dup 1) (match_dup 2)))]
2421 { operands[3] = gen_reg_rtx (BImode); })
2423 (define_expand "ffsdi2"
2425 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2426 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2427 (set (match_dup 5) (const_int 0))
2428 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2429 (set (match_dup 4) (popcount:DI (match_dup 3)))
2430 (set (match_operand:DI 0 "gr_register_operand" "")
2431 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2432 (match_dup 5) (match_dup 4)))]
2435 operands[2] = gen_reg_rtx (DImode);
2436 operands[3] = gen_reg_rtx (DImode);
2437 operands[4] = gen_reg_rtx (DImode);
2438 operands[5] = gen_reg_rtx (DImode);
2439 operands[6] = gen_reg_rtx (BImode);
2442 (define_expand "ctzdi2"
2443 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2445 (set (match_dup 3) (not:DI (match_dup 1)))
2446 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2447 (set (match_operand:DI 0 "gr_register_operand" "")
2448 (popcount:DI (match_dup 4)))]
2451 operands[2] = gen_reg_rtx (DImode);
2452 operands[3] = gen_reg_rtx (DImode);
2453 operands[4] = gen_reg_rtx (DImode);
2456 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2457 (define_expand "clzdi2"
2459 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "")))
2461 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2462 (set (match_dup 4) (const_int 65598))
2463 (set (match_operand:DI 0 "gr_register_operand" "")
2464 (minus:DI (match_dup 4) (match_dup 3)))]
2467 operands[2] = gen_reg_rtx (XFmode);
2468 operands[3] = gen_reg_rtx (DImode);
2469 operands[4] = gen_reg_rtx (DImode);
2472 (define_insn "popcountdi2"
2473 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2474 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2477 [(set_attr "itanium_class" "mmmul")])
2479 (define_insn "bswapdi2"
2480 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2481 (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2483 "mux1 %0 = %1, @rev"
2484 [(set_attr "itanium_class" "mmshf")])
2486 (define_insn "*getf_exp_xf"
2487 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2488 (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")]
2492 [(set_attr "itanium_class" "frfr")])
2494 ;; ::::::::::::::::::::
2496 ;; :: 128-bit Integer arithmetic
2498 ;; ::::::::::::::::::::
2500 (define_insn "addti3"
2501 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2502 (plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
2503 (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
2504 (clobber (match_scratch:BI 3 "=&c"))]
2507 [(set_attr "itanium_class" "unknown")])
2510 [(set (match_operand:TI 0 "register_operand" "")
2511 (plus:TI (match_operand:TI 1 "register_operand" "")
2512 (match_operand:TI 2 "register_operand" "")))
2513 (clobber (match_scratch:BI 3 ""))]
2515 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2516 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2517 (cond_exec (eq (match_dup 3) (const_int 0))
2518 (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
2519 (cond_exec (ne (match_dup 3) (const_int 0))
2521 (plus:DI (plus:DI (match_dup 5) (match_dup 6))
2524 operands[4] = gen_highpart (DImode, operands[0]);
2525 operands[0] = gen_lowpart (DImode, operands[0]);
2526 operands[5] = gen_highpart (DImode, operands[1]);
2527 operands[1] = gen_lowpart (DImode, operands[1]);
2528 operands[6] = gen_highpart (DImode, operands[2]);
2529 operands[2] = gen_lowpart (DImode, operands[2]);
2533 [(set (match_operand:TI 0 "register_operand" "")
2534 (plus:TI (match_operand:TI 1 "register_operand" "")
2535 (match_operand:TI 2 "immediate_operand" "")))
2536 (clobber (match_scratch:BI 3 ""))]
2538 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2539 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2540 (cond_exec (eq (match_dup 3) (const_int 0))
2542 (plus:DI (match_dup 5) (match_dup 6))))
2543 (cond_exec (ne (match_dup 3) (const_int 0))
2545 (plus:DI (match_dup 5) (match_dup 7))))]
2547 operands[4] = gen_highpart (DImode, operands[0]);
2548 operands[0] = gen_lowpart (DImode, operands[0]);
2549 operands[5] = gen_highpart (DImode, operands[1]);
2550 operands[1] = gen_lowpart (DImode, operands[1]);
2551 operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2552 operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
2555 (define_insn "subti3"
2556 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2557 (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
2558 (match_operand:TI 2 "gr_register_operand" "r")))
2559 (clobber (match_scratch:BI 3 "=&c"))]
2562 [(set_attr "itanium_class" "unknown")])
2565 [(set (match_operand:TI 0 "register_operand" "")
2566 (minus:TI (match_operand:TI 1 "register_operand" "")
2567 (match_operand:TI 2 "register_operand" "")))
2568 (clobber (match_scratch:BI 3 "=&c"))]
2570 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2571 (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
2572 (cond_exec (eq (match_dup 3) (const_int 0))
2573 (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
2574 (cond_exec (ne (match_dup 3) (const_int 0))
2576 (plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
2578 operands[4] = gen_highpart (DImode, operands[0]);
2579 operands[0] = gen_lowpart (DImode, operands[0]);
2580 operands[5] = gen_highpart (DImode, operands[1]);
2581 operands[1] = gen_lowpart (DImode, operands[1]);
2582 operands[6] = gen_highpart (DImode, operands[2]);
2583 operands[2] = gen_lowpart (DImode, operands[2]);
2587 [(set (match_operand:TI 0 "register_operand" "")
2588 (minus:TI (match_operand:TI 1 "immediate_operand" "")
2589 (match_operand:TI 2 "register_operand" "")))
2590 (clobber (match_scratch:BI 3 "=&c"))]
2591 "reload_completed && satisfies_constraint_K (operands[1])"
2592 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2593 (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
2594 (cond_exec (ne (match_dup 3) (const_int 0))
2595 (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
2596 (cond_exec (eq (match_dup 3) (const_int 0))
2597 (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
2599 operands[4] = gen_highpart (DImode, operands[0]);
2600 operands[0] = gen_lowpart (DImode, operands[0]);
2601 operands[5] = gen_highpart (DImode, operands[2]);
2602 operands[2] = gen_lowpart (DImode, operands[2]);
2603 operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
2604 operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
2607 (define_expand "mulditi3"
2608 [(set (match_operand:TI 0 "fr_register_operand" "")
2609 (mult:TI (sign_extend:TI
2610 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
2612 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
2616 (define_insn_and_split "*mulditi3_internal"
2617 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2618 (mult:TI (sign_extend:TI
2619 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2621 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
2625 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2626 (set (match_dup 3) (truncate:DI
2628 (mult:TI (sign_extend:TI (match_dup 1))
2629 (sign_extend:TI (match_dup 2)))
2632 operands[3] = gen_highpart (DImode, operands[0]);
2633 operands[0] = gen_lowpart (DImode, operands[0]);
2635 [(set_attr "itanium_class" "unknown")])
2637 (define_expand "umulditi3"
2638 [(set (match_operand:TI 0 "fr_register_operand" "")
2639 (mult:TI (zero_extend:TI
2640 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
2642 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
2646 (define_insn_and_split "*umulditi3_internal"
2647 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2648 (mult:TI (zero_extend:TI
2649 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2651 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
2655 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2656 (set (match_dup 3) (truncate:DI
2658 (mult:TI (zero_extend:TI (match_dup 1))
2659 (zero_extend:TI (match_dup 2)))
2662 operands[3] = gen_highpart (DImode, operands[0]);
2663 operands[0] = gen_lowpart (DImode, operands[0]);
2665 [(set_attr "itanium_class" "unknown")])
2667 (define_insn_and_split "negti2"
2668 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2669 (neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
2670 (clobber (match_scratch:BI 2 "=&c"))]
2674 [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
2675 (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
2676 (cond_exec (eq (match_dup 2) (const_int 0))
2677 (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
2678 (cond_exec (ne (match_dup 2) (const_int 0))
2679 (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
2681 operands[3] = gen_highpart (DImode, operands[0]);
2682 operands[0] = gen_lowpart (DImode, operands[0]);
2683 operands[4] = gen_highpart (DImode, operands[1]);
2684 operands[1] = gen_lowpart (DImode, operands[1]);
2686 [(set_attr "itanium_class" "unknown")])
2688 ;; ::::::::::::::::::::
2690 ;; :: 32-bit floating point arithmetic
2692 ;; ::::::::::::::::::::
2694 (define_insn "addsf3"
2695 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2696 (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "%fG")
2697 (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
2699 "fadd.s %0 = %F1, %F2"
2700 [(set_attr "itanium_class" "fmac")])
2702 (define_insn "subsf3"
2703 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2704 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2705 (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
2707 "fsub.s %0 = %F1, %F2"
2708 [(set_attr "itanium_class" "fmac")])
2710 (define_insn "mulsf3"
2711 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2712 (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2713 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2715 "fmpy.s %0 = %F1, %F2"
2716 [(set_attr "itanium_class" "fmac")])
2718 (define_insn "abssf2"
2719 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2720 (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
2723 [(set_attr "itanium_class" "fmisc")])
2725 (define_insn "negsf2"
2726 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2727 (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
2730 [(set_attr "itanium_class" "fmisc")])
2732 (define_insn "*nabssf2"
2733 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2734 (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))]
2737 [(set_attr "itanium_class" "fmisc")])
2739 (define_insn "copysignsf3"
2740 [(set (match_operand:SF 0 "register_operand" "=f")
2741 (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2742 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2745 "fmerge.s %0 = %F2, %F1"
2746 [(set_attr "itanium_class" "fmisc")])
2748 (define_insn "*ncopysignsf3"
2749 [(set (match_operand:SF 0 "register_operand" "=f")
2750 (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2751 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2754 "fmerge.ns %0 = %F2, %F1"
2755 [(set_attr "itanium_class" "fmisc")])
2757 (define_insn "sminsf3"
2758 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2759 (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2760 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2762 "fmin %0 = %F1, %F2"
2763 [(set_attr "itanium_class" "fmisc")])
2765 (define_insn "smaxsf3"
2766 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2767 (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2768 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2770 "fmax %0 = %F1, %F2"
2771 [(set_attr "itanium_class" "fmisc")])
2773 (define_insn "*nmulsf3"
2774 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2775 (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2776 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
2778 "fnmpy.s %0 = %F1, %F2"
2779 [(set_attr "itanium_class" "fmac")])
2781 (define_insn "fmasf4"
2782 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2783 (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2784 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2785 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2787 "fma.s %0 = %F1, %F2, %F3"
2788 [(set_attr "itanium_class" "fmac")])
2790 (define_insn "fmssf4"
2791 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2792 (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2793 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2795 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2797 "fms.s %0 = %F1, %F2, %F3"
2798 [(set_attr "itanium_class" "fmac")])
2800 (define_insn "fnmasf4"
2801 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2802 (fma:SF (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))
2803 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2804 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2806 "fnma.s %0 = %F1, %F2, %F3"
2807 [(set_attr "itanium_class" "fmac")])
2809 ;; ::::::::::::::::::::
2811 ;; :: 64-bit floating point arithmetic
2813 ;; ::::::::::::::::::::
2815 (define_insn "adddf3"
2816 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2817 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
2818 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
2820 "fadd.d %0 = %F1, %F2"
2821 [(set_attr "itanium_class" "fmac")])
2823 (define_insn "*adddf3_trunc"
2824 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2826 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
2827 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2829 "fadd.s %0 = %F1, %F2"
2830 [(set_attr "itanium_class" "fmac")])
2832 (define_insn "subdf3"
2833 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2834 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2835 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
2837 "fsub.d %0 = %F1, %F2"
2838 [(set_attr "itanium_class" "fmac")])
2840 (define_insn "*subdf3_trunc"
2841 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2843 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2844 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2846 "fsub.s %0 = %F1, %F2"
2847 [(set_attr "itanium_class" "fmac")])
2849 (define_insn "muldf3"
2850 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2851 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2852 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2854 "fmpy.d %0 = %F1, %F2"
2855 [(set_attr "itanium_class" "fmac")])
2857 (define_insn "*muldf3_trunc"
2858 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2860 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2861 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2863 "fmpy.s %0 = %F1, %F2"
2864 [(set_attr "itanium_class" "fmac")])
2866 (define_insn "absdf2"
2867 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2868 (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
2871 [(set_attr "itanium_class" "fmisc")])
2873 (define_insn "negdf2"
2874 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2875 (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
2878 [(set_attr "itanium_class" "fmisc")])
2880 (define_insn "*nabsdf2"
2881 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2882 (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))]
2885 [(set_attr "itanium_class" "fmisc")])
2887 (define_insn "copysigndf3"
2888 [(set (match_operand:DF 0 "register_operand" "=f")
2889 (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2890 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2893 "fmerge.s %0 = %F2, %F1"
2894 [(set_attr "itanium_class" "fmisc")])
2896 (define_insn "*ncopysigndf3"
2897 [(set (match_operand:DF 0 "register_operand" "=f")
2898 (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2899 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2902 "fmerge.ns %0 = %F2, %F1"
2903 [(set_attr "itanium_class" "fmisc")])
2905 (define_insn "smindf3"
2906 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2907 (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2908 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2910 "fmin %0 = %F1, %F2"
2911 [(set_attr "itanium_class" "fmisc")])
2913 (define_insn "smaxdf3"
2914 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2915 (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2916 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2918 "fmax %0 = %F1, %F2"
2919 [(set_attr "itanium_class" "fmisc")])
2921 (define_insn "*nmuldf3"
2922 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2923 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2924 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2926 "fnmpy.d %0 = %F1, %F2"
2927 [(set_attr "itanium_class" "fmac")])
2929 (define_insn "*nmuldf3_trunc"
2930 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2932 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2933 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
2935 "fnmpy.s %0 = %F1, %F2"
2936 [(set_attr "itanium_class" "fmac")])
2938 (define_insn "fmadf4"
2939 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2940 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2941 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2942 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2944 "fma.d %0 = %F1, %F2, %F3"
2945 [(set_attr "itanium_class" "fmac")])
2947 (define_insn "*fmadf_trunc_sf"
2948 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2950 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2951 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2952 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2954 "fma.s %0 = %F1, %F2, %F3"
2955 [(set_attr "itanium_class" "fmac")])
2957 (define_insn "fmsdf4"
2958 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2959 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2960 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2962 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2964 "fms.d %0 = %F1, %F2, %F3"
2965 [(set_attr "itanium_class" "fmac")])
2967 (define_insn "*fmsdf_trunc_sf"
2968 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2971 (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2972 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2974 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))]
2976 "fms.s %0 = %F1, %F2, %F3"
2977 [(set_attr "itanium_class" "fmac")])
2979 (define_insn "fnmadf4"
2980 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2981 (fma:DF (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))
2982 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2983 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2985 "fnma.d %0 = %F1, %F2, %F3"
2986 [(set_attr "itanium_class" "fmac")])
2988 (define_insn "*fnmadf_trunc_sf"
2989 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2992 (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))
2993 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2994 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2996 "fnma.s %0 = %F1, %F2, %F3"
2997 [(set_attr "itanium_class" "fmac")])
2999 ;; ::::::::::::::::::::
3001 ;; :: 80-bit floating point arithmetic
3003 ;; ::::::::::::::::::::
3005 (define_insn "addxf3"
3006 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3007 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3008 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
3010 "fadd %0 = %F1, %F2"
3011 [(set_attr "itanium_class" "fmac")])
3013 (define_insn "*addxf3_truncsf"
3014 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3016 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3017 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
3019 "fadd.s %0 = %F1, %F2"
3020 [(set_attr "itanium_class" "fmac")])
3022 (define_insn "*addxf3_truncdf"
3023 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3025 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3026 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
3028 "fadd.d %0 = %F1, %F2"
3029 [(set_attr "itanium_class" "fmac")])
3031 (define_insn "subxf3"
3032 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3033 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3034 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
3036 "fsub %0 = %F1, %F2"
3037 [(set_attr "itanium_class" "fmac")])
3039 (define_insn "*subxf3_truncsf"
3040 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3042 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3043 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
3045 "fsub.s %0 = %F1, %F2"
3046 [(set_attr "itanium_class" "fmac")])
3048 (define_insn "*subxf3_truncdf"
3049 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3051 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3052 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
3054 "fsub.d %0 = %F1, %F2"
3055 [(set_attr "itanium_class" "fmac")])
3057 (define_insn "mulxf3"
3058 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3059 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3060 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3062 "fmpy %0 = %F1, %F2"
3063 [(set_attr "itanium_class" "fmac")])
3065 (define_insn "*mulxf3_truncsf"
3066 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3068 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3069 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3071 "fmpy.s %0 = %F1, %F2"
3072 [(set_attr "itanium_class" "fmac")])
3074 (define_insn "*mulxf3_truncdf"
3075 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3077 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3078 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3080 "fmpy.d %0 = %F1, %F2"
3081 [(set_attr "itanium_class" "fmac")])
3083 (define_insn "absxf2"
3084 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3085 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3088 [(set_attr "itanium_class" "fmisc")])
3090 (define_insn "negxf2"
3091 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3092 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3095 [(set_attr "itanium_class" "fmisc")])
3097 (define_insn "*nabsxf2"
3098 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3099 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3102 [(set_attr "itanium_class" "fmisc")])
3104 (define_insn "copysignxf3"
3105 [(set (match_operand:XF 0 "register_operand" "=f")
3106 (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3107 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3110 "fmerge.s %0 = %F2, %F1"
3111 [(set_attr "itanium_class" "fmisc")])
3113 (define_insn "*ncopysignxf3"
3114 [(set (match_operand:XF 0 "register_operand" "=f")
3115 (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3116 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3119 "fmerge.ns %0 = %F2, %F1"
3120 [(set_attr "itanium_class" "fmisc")])
3122 (define_insn "sminxf3"
3123 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3124 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3125 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3127 "fmin %0 = %F1, %F2"
3128 [(set_attr "itanium_class" "fmisc")])
3130 (define_insn "smaxxf3"
3131 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3132 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3133 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3135 "fmax %0 = %F1, %F2"
3136 [(set_attr "itanium_class" "fmisc")])
3138 (define_insn "*nmulxf3"
3139 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3140 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3141 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3143 "fnmpy %0 = %F1, %F2"
3144 [(set_attr "itanium_class" "fmac")])
3146 (define_insn "*nmulxf3_truncsf"
3147 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3150 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3151 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3153 "fnmpy.s %0 = %F1, %F2"
3154 [(set_attr "itanium_class" "fmac")])
3156 (define_insn "*nmulxf3_truncdf"
3157 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3160 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3161 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3163 "fnmpy.d %0 = %F1, %F2"
3164 [(set_attr "itanium_class" "fmac")])
3166 (define_insn "fmaxf4"
3167 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3168 (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3169 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3170 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
3172 "fma %0 = %F1, %F2, %F3"
3173 [(set_attr "itanium_class" "fmac")])
3175 (define_insn "*fmaxf_trunc_<mode>"
3176 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3177 (float_truncate:MODE_SDF
3179 (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3180 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3181 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3183 "fma<suffix> %0 = %F1, %F2, %F3"
3184 [(set_attr "itanium_class" "fmac")])
3186 (define_insn "fmsxf4"
3187 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3188 (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3189 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3191 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3193 "fms %0 = %F1, %F2, %F3"
3194 [(set_attr "itanium_class" "fmac")])
3196 (define_insn "*fmsxf_trunc_<mode>"
3197 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3198 (float_truncate:MODE_SDF
3200 (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3201 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3203 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))]
3205 "fms<suffix> %0 = %F1, %F2, %F3"
3206 [(set_attr "itanium_class" "fmac")])
3208 (define_insn "fnmaxf4"
3209 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3210 (fma:XF (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))
3211 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3212 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
3214 "fnma %0 = %F1, %F2, %F3"
3215 [(set_attr "itanium_class" "fmac")])
3217 (define_insn "*fnmaxf_trunc_<mode>"
3218 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3219 (float_truncate:MODE_SDF
3221 (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))
3222 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3223 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3225 "fnma<suffix> %0 = %F1, %F2, %F3"
3226 [(set_attr "itanium_class" "fmac")])
3228 ;; ::::::::::::::::::::
3230 ;; :: 32-bit Integer Shifts and Rotates
3232 ;; ::::::::::::::::::::
3234 (define_expand "ashlsi3"
3235 [(set (match_operand:SI 0 "gr_register_operand" "")
3236 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3237 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3240 if (GET_CODE (operands[2]) != CONST_INT)
3242 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3243 we've got to get rid of stray bits outside the SImode register. */
3244 rtx subshift = gen_reg_rtx (DImode);
3245 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3246 operands[2] = subshift;
3250 (define_insn "*ashlsi3_internal"
3251 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3252 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3253 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3256 shladd %0 = %1, %2, r0
3257 dep.z %0 = %1, %2, %E2
3259 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
3261 (define_expand "ashrsi3"
3262 [(set (match_operand:SI 0 "gr_register_operand" "")
3263 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3264 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3267 rtx subtarget = gen_reg_rtx (DImode);
3268 if (GET_CODE (operands[2]) == CONST_INT)
3269 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3270 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3273 rtx subshift = gen_reg_rtx (DImode);
3274 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3275 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3276 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3278 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3282 (define_expand "lshrsi3"
3283 [(set (match_operand:SI 0 "gr_register_operand" "")
3284 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3285 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3288 rtx subtarget = gen_reg_rtx (DImode);
3289 if (GET_CODE (operands[2]) == CONST_INT)
3290 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3291 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3294 rtx subshift = gen_reg_rtx (DImode);
3295 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3296 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3297 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3299 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3303 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3304 ;; here, instead of 64 like the patterns above. Keep the pattern together
3305 ;; until after combine; otherwise it won't get matched often.
3307 (define_expand "rotrsi3"
3308 [(set (match_operand:SI 0 "gr_register_operand" "")
3309 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3310 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3313 if (GET_MODE (operands[2]) != VOIDmode)
3315 rtx tmp = gen_reg_rtx (DImode);
3316 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3321 (define_insn_and_split "*rotrsi3_internal"
3322 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3323 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3324 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3329 (ior:DI (zero_extend:DI (match_dup 1))
3330 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3332 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3333 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3335 (define_expand "rotlsi3"
3336 [(set (match_operand:SI 0 "gr_register_operand" "")
3337 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3338 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3341 if (! shift_32bit_count_operand (operands[2], SImode))
3343 rtx tmp = gen_reg_rtx (SImode);
3344 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3345 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3350 (define_insn_and_split "*rotlsi3_internal"
3351 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3352 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3353 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3355 "mux2 %0 = %1, 0xe1"
3356 "reload_completed && INTVAL (operands[2]) != 16"
3358 (ior:DI (zero_extend:DI (match_dup 1))
3359 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3361 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3363 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3364 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
3366 [(set_attr "itanium_class" "mmshf")])
3368 ;; ::::::::::::::::::::
3370 ;; :: 64-bit Integer Shifts and Rotates
3372 ;; ::::::::::::::::::::
3374 (define_insn "ashldi3"
3375 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3376 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3377 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
3380 shladd %0 = %1, %2, r0
3383 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
3385 ;; ??? Maybe combine this with the multiply and add instruction?
3387 (define_insn "*shladd"
3388 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3389 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3390 (match_operand:DI 2 "shladd_operand" "n"))
3391 (match_operand:DI 3 "gr_register_operand" "r")))]
3393 "shladd %0 = %1, %S2, %3"
3394 [(set_attr "itanium_class" "ialu")])
3396 ;; This can be created by register elimination if operand3 of shladd is an
3397 ;; eliminable register or has reg_equiv_constant set.
3399 ;; We have to use nonmemory_operand for operand 4, to ensure that the
3400 ;; validate_changes call inside eliminate_regs will always succeed. If it
3401 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3404 (define_insn_and_split "*shladd_elim"
3405 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3406 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3407 (match_operand:DI 2 "shladd_operand" "n"))
3408 (match_operand:DI 3 "nonmemory_operand" "r"))
3409 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3410 "reload_in_progress"
3411 "* gcc_unreachable ();"
3413 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3415 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3417 [(set_attr "itanium_class" "unknown")])
3419 (define_insn "ashrdi3"
3420 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3421 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3422 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3427 [(set_attr "itanium_class" "mmshf,mmshfi")])
3429 (define_insn "lshrdi3"
3430 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3431 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3432 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3437 [(set_attr "itanium_class" "mmshf,mmshfi")])
3439 ;; Using a predicate that accepts only constants doesn't work, because optabs
3440 ;; will load the operand into a register and call the pattern if the predicate
3441 ;; did not accept it on the first try. So we use nonmemory_operand and then
3442 ;; verify that we have an appropriate constant in the expander.
3444 (define_expand "rotrdi3"
3445 [(set (match_operand:DI 0 "gr_register_operand" "")
3446 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
3447 (match_operand:DI 2 "nonmemory_operand" "")))]
3450 if (! shift_count_operand (operands[2], DImode))
3454 (define_insn "*rotrdi3_internal"
3455 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3456 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
3457 (match_operand:DI 2 "shift_count_operand" "M")))]
3459 "shrp %0 = %1, %1, %2"
3460 [(set_attr "itanium_class" "ishf")])
3462 (define_expand "rotldi3"
3463 [(set (match_operand:DI 0 "gr_register_operand" "")
3464 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3465 (match_operand:DI 2 "nonmemory_operand" "")))]
3468 if (! shift_count_operand (operands[2], DImode))
3472 (define_insn "*rotldi3_internal"
3473 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3474 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3475 (match_operand:DI 2 "shift_count_operand" "M")))]
3477 "shrp %0 = %1, %1, %e2"
3478 [(set_attr "itanium_class" "ishf")])
3480 ;; ::::::::::::::::::::
3482 ;; :: 128-bit Integer Shifts and Rotates
3484 ;; ::::::::::::::::::::
3486 (define_expand "ashlti3"
3487 [(set (match_operand:TI 0 "gr_register_operand" "")
3488 (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
3489 (match_operand:DI 2 "nonmemory_operand" "")))]
3492 if (!dshift_count_operand (operands[2], DImode))
3496 (define_insn_and_split "*ashlti3_internal"
3497 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3498 (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
3499 (match_operand:DI 2 "dshift_count_operand" "n")))]
3505 HOST_WIDE_INT shift = INTVAL (operands[2]);
3506 rtx rl = gen_lowpart (DImode, operands[0]);
3507 rtx rh = gen_highpart (DImode, operands[0]);
3508 rtx lo = gen_lowpart (DImode, operands[1]);
3509 rtx shiftlo = GEN_INT (shift & 63);
3513 emit_move_insn (rl, const0_rtx);
3515 emit_insn (gen_ashldi3 (rh, lo, shiftlo));
3517 emit_move_insn (rh, lo);
3521 rtx hi = gen_highpart (DImode, operands[1]);
3523 emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
3524 emit_insn (gen_ashldi3 (rl, lo, shiftlo));
3529 (define_expand "ashrti3"
3530 [(set (match_operand:TI 0 "gr_register_operand" "")
3531 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3532 (match_operand:DI 2 "nonmemory_operand" "")))]
3535 if (!dshift_count_operand (operands[2], DImode))
3539 (define_insn_and_split "*ashrti3_internal"
3540 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3541 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3542 (match_operand:DI 2 "dshift_count_operand" "n")))]
3548 HOST_WIDE_INT shift = INTVAL (operands[2]);
3549 rtx rl = gen_lowpart (DImode, operands[0]);
3550 rtx rh = gen_highpart (DImode, operands[0]);
3551 rtx hi = gen_highpart (DImode, operands[1]);
3552 rtx shiftlo = GEN_INT (shift & 63);
3557 emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
3559 emit_move_insn (rl, hi);
3560 emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
3564 rtx lo = gen_lowpart (DImode, operands[1]);
3566 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3567 emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
3572 (define_expand "lshrti3"
3573 [(set (match_operand:TI 0 "gr_register_operand" "")
3574 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3575 (match_operand:DI 2 "nonmemory_operand" "")))]
3578 if (!dshift_count_operand (operands[2], DImode))
3582 (define_insn_and_split "*lshrti3_internal"
3583 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3584 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3585 (match_operand:DI 2 "dshift_count_operand" "n")))]
3591 HOST_WIDE_INT shift = INTVAL (operands[2]);
3592 rtx rl = gen_lowpart (DImode, operands[0]);
3593 rtx rh = gen_highpart (DImode, operands[0]);
3594 rtx hi = gen_highpart (DImode, operands[1]);
3595 rtx shiftlo = GEN_INT (shift & 63);
3600 emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
3602 emit_move_insn (rl, hi);
3603 emit_move_insn (rh, const0_rtx);
3607 rtx lo = gen_lowpart (DImode, operands[1]);
3609 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3610 emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
3615 (define_expand "rotlti3"
3616 [(set (match_operand:TI 0 "gr_register_operand" "")
3617 (rotate:TI (match_operand:TI 1 "gr_register_operand" "")
3618 (match_operand:DI 2 "nonmemory_operand" "")))]
3621 if (! dshift_count_operand (operands[2], DImode))
3625 (define_insn_and_split "*rotlti3_internal"
3626 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3627 (rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
3628 (match_operand:DI 2 "dshift_count_operand" "n")))]
3634 HOST_WIDE_INT count = INTVAL (operands[2]);
3635 rtx rl = gen_lowpart (DImode, operands[0]);
3636 rtx rh = gen_highpart (DImode, operands[0]);
3637 rtx lo = gen_lowpart (DImode, operands[1]);
3638 rtx hi = gen_highpart (DImode, operands[1]);
3639 rtx countlo = GEN_INT (-count & 63);
3645 emit_insn (gen_shrp (rl, hi, lo, countlo));
3646 emit_insn (gen_shrp (rh, lo, hi, countlo));
3650 emit_move_insn (rl, hi);
3651 emit_move_insn (rh, lo);
3656 emit_insn (gen_shrp (rl, lo, hi, countlo));
3657 emit_insn (gen_shrp (rh, hi, lo, countlo));
3661 [(set_attr "itanium_class" "unknown")])
3664 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3665 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
3666 (match_operand:DI 2 "gr_register_operand" "r")
3667 (match_operand:DI 3 "shift_count_operand" "M")]
3670 "shrp %0 = %1, %2, %3"
3671 [(set_attr "itanium_class" "ishf")])
3673 ;; ::::::::::::::::::::
3675 ;; :: 32-bit Integer Logical operations
3677 ;; ::::::::::::::::::::
3679 ;; We don't seem to need any other 32-bit logical operations, because gcc
3680 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3681 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3682 ;; This doesn't work for unary logical operations, because we don't call
3683 ;; apply_distributive_law for them.
3685 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3686 ;; apply_distributive_law. We get inefficient code for
3687 ;; int sub4 (int i, int j) { return i & ~j; }
3688 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3689 ;; (zero_extend (and (not A) B)) in combine.
3690 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3691 ;; one_cmplsi2 pattern.
3693 (define_insn "one_cmplsi2"
3694 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3695 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
3698 [(set_attr "itanium_class" "ilog")])
3700 ;; ::::::::::::::::::::
3702 ;; :: 64-bit Integer Logical operations
3704 ;; ::::::::::::::::::::
3706 (define_insn "anddi3"
3707 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3708 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3709 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3714 [(set_attr "itanium_class" "ilog,fmisc")])
3716 (define_insn "*andnot"
3717 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3718 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3719 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3724 [(set_attr "itanium_class" "ilog,fmisc")])
3726 (define_insn "iordi3"
3727 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3728 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3729 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3734 [(set_attr "itanium_class" "ilog,fmisc")])
3736 (define_insn "xordi3"
3737 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3738 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3739 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3744 [(set_attr "itanium_class" "ilog,fmisc")])
3746 (define_insn "one_cmpldi2"
3747 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3748 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
3751 [(set_attr "itanium_class" "ilog")])
3753 ;; ::::::::::::::::::::
3757 ;; ::::::::::::::::::::
3759 (define_expand "cbranchbi4"
3761 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3762 [(match_operand:BI 1 "register_operand" "")
3763 (match_operand:BI 2 "const_int_operand" "")])
3764 (label_ref (match_operand 3 "" ""))
3767 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3769 (define_expand "cbranchsi4"
3771 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3772 [(match_operand:SI 1 "gr_register_operand" "")
3773 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3774 (label_ref (match_operand 3 "" ""))
3777 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3779 (define_expand "cbranchdi4"
3781 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3782 [(match_operand:DI 1 "gr_register_operand" "")
3783 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3784 (label_ref (match_operand 3 "" ""))
3787 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3789 (define_expand "cbranchsf4"
3791 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3792 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
3793 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
3794 (label_ref (match_operand 3 "" ""))
3797 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3799 (define_expand "cbranchdf4"
3801 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3802 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
3803 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
3804 (label_ref (match_operand 3 "" ""))
3807 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3809 (define_expand "cbranchxf4"
3811 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3812 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
3813 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
3814 (label_ref (match_operand 3 "" ""))
3817 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3819 (define_expand "cbranchtf4"
3821 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3822 [(match_operand:TF 1 "gr_register_operand" "")
3823 (match_operand:TF 2 "gr_register_operand" "")])
3824 (label_ref (match_operand 3 "" ""))
3827 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3830 (define_insn "*cmpsi_normal"
3831 [(set (match_operand:BI 0 "register_operand" "=c")
3832 (match_operator:BI 1 "normal_comparison_operator"
3833 [(match_operand:SI 2 "gr_register_operand" "r")
3834 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
3836 "cmp4.%C1 %0, %I0 = %3, %2"
3837 [(set_attr "itanium_class" "icmp")])
3839 ;; We use %r3 because it is possible for us to match a 0, and two of the
3840 ;; unsigned comparisons don't accept immediate operands of zero.
3842 (define_insn "*cmpsi_adjusted"
3843 [(set (match_operand:BI 0 "register_operand" "=c")
3844 (match_operator:BI 1 "adjusted_comparison_operator"
3845 [(match_operand:SI 2 "gr_register_operand" "r")
3846 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
3848 "cmp4.%C1 %0, %I0 = %r3, %2"
3849 [(set_attr "itanium_class" "icmp")])
3851 (define_insn "*cmpdi_normal"
3852 [(set (match_operand:BI 0 "register_operand" "=c")
3853 (match_operator:BI 1 "normal_comparison_operator"
3854 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
3855 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
3857 "cmp.%C1 %0, %I0 = %3, %r2"
3858 [(set_attr "itanium_class" "icmp")])
3860 ;; We use %r3 because it is possible for us to match a 0, and two of the
3861 ;; unsigned comparisons don't accept immediate operands of zero.
3863 (define_insn "*cmpdi_adjusted"
3864 [(set (match_operand:BI 0 "register_operand" "=c")
3865 (match_operator:BI 1 "adjusted_comparison_operator"
3866 [(match_operand:DI 2 "gr_register_operand" "r")
3867 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
3869 "cmp.%C1 %0, %I0 = %r3, %2"
3870 [(set_attr "itanium_class" "icmp")])
3872 (define_insn "*cmpsf_internal"
3873 [(set (match_operand:BI 0 "register_operand" "=c")
3874 (match_operator:BI 1 "comparison_operator"
3875 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
3876 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
3878 "fcmp.%D1 %0, %I0 = %F2, %F3"
3879 [(set_attr "itanium_class" "fcmp")])
3881 (define_insn "*cmpdf_internal"
3882 [(set (match_operand:BI 0 "register_operand" "=c")
3883 (match_operator:BI 1 "comparison_operator"
3884 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
3885 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
3887 "fcmp.%D1 %0, %I0 = %F2, %F3"
3888 [(set_attr "itanium_class" "fcmp")])
3890 (define_insn "*cmpxf_internal"
3891 [(set (match_operand:BI 0 "register_operand" "=c")
3892 (match_operator:BI 1 "comparison_operator"
3893 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3894 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
3896 "fcmp.%D1 %0, %I0 = %F2, %F3"
3897 [(set_attr "itanium_class" "fcmp")])
3899 ;; ??? Can this pattern be generated?
3901 (define_insn "*bit_zero"
3902 [(set (match_operand:BI 0 "register_operand" "=c")
3903 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
3905 (match_operand:DI 2 "shift_count_operand" "M"))
3908 "tbit.z %0, %I0 = %1, %2"
3909 [(set_attr "itanium_class" "tbit")])
3911 (define_insn "*bit_one"
3912 [(set (match_operand:BI 0 "register_operand" "=c")
3913 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
3915 (match_operand:DI 2 "shift_count_operand" "M"))
3918 "tbit.nz %0, %I0 = %1, %2"
3919 [(set_attr "itanium_class" "tbit")])
3921 ;; ::::::::::::::::::::
3925 ;; ::::::::::::::::::::
3927 (define_insn "*br_true"
3929 (if_then_else (match_operator 0 "predicate_operator"
3930 [(match_operand:BI 1 "register_operand" "c")
3932 (label_ref (match_operand 2 "" ""))
3935 "(%J0) br.cond%+ %l2"
3936 [(set_attr "itanium_class" "br")
3937 (set_attr "predicable" "no")])
3939 (define_insn "*br_false"
3941 (if_then_else (match_operator 0 "predicate_operator"
3942 [(match_operand:BI 1 "register_operand" "c")
3945 (label_ref (match_operand 2 "" ""))))]
3947 "(%j0) br.cond%+ %l2"
3948 [(set_attr "itanium_class" "br")
3949 (set_attr "predicable" "no")])
3951 ;; ::::::::::::::::::::
3953 ;; :: Counted loop operations
3955 ;; ::::::::::::::::::::
3957 (define_expand "doloop_end"
3958 [(use (match_operand 0 "" "")) ; loop pseudo
3959 (use (match_operand 1 "" ""))] ; label
3962 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
3967 (define_insn "doloop_end_internal"
3968 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
3970 (label_ref (match_operand 1 "" ""))
3972 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
3973 (plus:DI (match_dup 0) (const_int -1))
3976 "br.cloop.sptk.few %l1"
3977 [(set_attr "itanium_class" "br")
3978 (set_attr "predicable" "no")])
3980 ;; ::::::::::::::::::::
3982 ;; :: Set flag operations
3984 ;; ::::::::::::::::::::
3986 (define_expand "cstorebi4"
3987 [(set (match_operand:DI 0 "gr_register_operand" "")
3988 (match_operator:DI 1 "ia64_cbranch_operator"
3989 [(match_operand:BI 2 "register_operand" "")
3990 (match_operand:BI 3 "const_int_operand" "")]))]
3992 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
3994 (define_expand "cstoresi4"
3995 [(set (match_operand:DI 0 "gr_register_operand" "")
3996 (match_operator:DI 1 "ia64_cbranch_operator"
3997 [(match_operand:SI 2 "gr_register_operand" "")
3998 (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
4000 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4002 (define_expand "cstoredi4"
4003 [(set (match_operand:DI 0 "gr_register_operand" "")
4004 (match_operator:DI 1 "ia64_cbranch_operator"
4005 [(match_operand:DI 2 "gr_register_operand" "")
4006 (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
4008 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4010 (define_expand "cstoresf4"
4011 [(set (match_operand:DI 0 "gr_register_operand" "")
4012 (match_operator:DI 1 "ia64_cbranch_operator"
4013 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "")
4014 (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))]
4016 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4018 (define_expand "cstoredf4"
4019 [(set (match_operand:DI 0 "gr_register_operand" "")
4020 (match_operator:DI 1 "ia64_cbranch_operator"
4021 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "")
4022 (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))]
4024 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4026 (define_expand "cstorexf4"
4027 [(set (match_operand:DI 0 "gr_register_operand" "")
4028 (match_operator:DI 1 "ia64_cbranch_operator"
4029 [(match_operand:XF 2 "xfreg_or_fp01_operand" "")
4030 (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))]
4032 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4034 (define_expand "cstoretf4"
4035 [(set (match_operand:DI 0 "gr_register_operand" "")
4036 (match_operator:DI 1 "ia64_cbranch_operator"
4037 [(match_operand:TF 2 "gr_register_operand" "")
4038 (match_operand:TF 3 "gr_register_operand" "")]))]
4040 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4042 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4043 ;; efficient than mov/mov/cst/cst.
4045 (define_insn_and_split "*sne_internal"
4046 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4047 (ne:DI (match_operand:BI 1 "register_operand" "c")
4052 [(cond_exec (ne (match_dup 1) (const_int 0))
4053 (set (match_dup 0) (const_int 1)))
4054 (cond_exec (eq (match_dup 1) (const_int 0))
4055 (set (match_dup 0) (const_int 0)))]
4057 [(set_attr "itanium_class" "unknown")])
4059 (define_insn_and_split "*seq_internal"
4060 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4061 (eq:DI (match_operand:BI 1 "register_operand" "c")
4066 [(cond_exec (ne (match_dup 1) (const_int 0))
4067 (set (match_dup 0) (const_int 0)))
4068 (cond_exec (eq (match_dup 1) (const_int 0))
4069 (set (match_dup 0) (const_int 1)))]
4071 [(set_attr "itanium_class" "unknown")])
4073 ;; ::::::::::::::::::::
4075 ;; :: Conditional move instructions.
4077 ;; ::::::::::::::::::::
4079 ;; ??? Add movXXcc patterns?
4082 ;; DImode if_then_else patterns.
4085 (define_insn "*cmovdi_internal"
4086 [(set (match_operand:DI 0 "not_postinc_destination_operand"
4087 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4089 (match_operator 4 "predicate_operator"
4090 [(match_operand:BI 1 "register_operand"
4091 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4093 (match_operand:DI 2 "not_postinc_move_operand"
4094 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4095 (match_operand:DI 3 "not_postinc_move_operand"
4096 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4097 "ia64_move_ok (operands[0], operands[2])
4098 && ia64_move_ok (operands[0], operands[3])"
4099 { gcc_unreachable (); }
4100 [(set_attr "predicable" "no")])
4103 [(set (match_operand 0 "not_postinc_destination_operand" "")
4105 (match_operator 4 "predicate_operator"
4106 [(match_operand:BI 1 "register_operand" "")
4108 (match_operand 2 "not_postinc_move_operand" "")
4109 (match_operand 3 "not_postinc_move_operand" "")))]
4113 bool emitted_something = false;
4114 rtx dest = operands[0];
4115 rtx srct = operands[2];
4116 rtx srcf = operands[3];
4117 rtx cond = operands[4];
4119 if (! rtx_equal_p (dest, srct))
4121 ia64_emit_cond_move (dest, srct, cond);
4122 emitted_something = true;
4124 if (! rtx_equal_p (dest, srcf))
4126 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
4127 VOIDmode, operands[1], const0_rtx);
4128 ia64_emit_cond_move (dest, srcf, cond);
4129 emitted_something = true;
4131 if (! emitted_something)
4132 emit_note (NOTE_INSN_DELETED);
4136 ;; Absolute value pattern.
4138 (define_insn "*absdi2_internal"
4139 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4141 (match_operator 4 "predicate_operator"
4142 [(match_operand:BI 1 "register_operand" "c,c")
4144 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4145 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4148 [(set_attr "itanium_class" "ialu,unknown")
4149 (set_attr "predicable" "no")])
4152 [(set (match_operand:DI 0 "register_operand" "")
4154 (match_operator 4 "predicate_operator"
4155 [(match_operand:BI 1 "register_operand" "c,c")
4157 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4158 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4159 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4163 (neg:DI (match_dup 2))))]
4167 [(set (match_operand:DI 0 "register_operand" "")
4169 (match_operator 4 "predicate_operator"
4170 [(match_operand:BI 1 "register_operand" "c,c")
4172 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4173 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4177 (set (match_dup 0) (neg:DI (match_dup 2))))
4180 (set (match_dup 0) (match_dup 3)))]
4182 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4183 VOIDmode, operands[1], const0_rtx);
4187 ;; SImode if_then_else patterns.
4190 (define_insn "*cmovsi_internal"
4191 [(set (match_operand:SI 0 "not_postinc_destination_operand"
4192 "=r,m,*f,r,m,*f,r,m,*f")
4194 (match_operator 4 "predicate_operator"
4195 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4197 (match_operand:SI 2 "not_postinc_move_operand"
4198 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4199 (match_operand:SI 3 "not_postinc_move_operand"
4200 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4201 "ia64_move_ok (operands[0], operands[2])
4202 && ia64_move_ok (operands[0], operands[3])"
4203 { gcc_unreachable (); }
4204 [(set_attr "predicable" "no")])
4206 (define_insn "*abssi2_internal"
4207 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4209 (match_operator 4 "predicate_operator"
4210 [(match_operand:BI 1 "register_operand" "c,c")
4212 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4213 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4216 [(set_attr "itanium_class" "ialu,unknown")
4217 (set_attr "predicable" "no")])
4220 [(set (match_operand:SI 0 "register_operand" "")
4222 (match_operator 4 "predicate_operator"
4223 [(match_operand:BI 1 "register_operand" "c,c")
4225 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4226 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4227 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4231 (neg:SI (match_dup 2))))]
4235 [(set (match_operand:SI 0 "register_operand" "")
4237 (match_operator 4 "predicate_operator"
4238 [(match_operand:BI 1 "register_operand" "c,c")
4240 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4241 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4245 (set (match_dup 0) (neg:SI (match_dup 2))))
4248 (set (match_dup 0) (match_dup 3)))]
4250 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4251 VOIDmode, operands[1], const0_rtx);
4254 (define_insn_and_split "*cond_opsi2_internal"
4255 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4256 (match_operator:SI 5 "condop_operator"
4258 (match_operator 6 "predicate_operator"
4259 [(match_operand:BI 1 "register_operand" "c")
4261 (match_operand:SI 2 "gr_register_operand" "r")
4262 (match_operand:SI 3 "gr_register_operand" "r"))
4263 (match_operand:SI 4 "gr_register_operand" "r")]))]
4269 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
4272 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
4274 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4275 VOIDmode, operands[1], const0_rtx);
4277 [(set_attr "itanium_class" "ialu")
4278 (set_attr "predicable" "no")])
4281 (define_insn_and_split "*cond_opsi2_internal_b"
4282 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4283 (match_operator:SI 5 "condop_operator"
4284 [(match_operand:SI 4 "gr_register_operand" "r")
4286 (match_operator 6 "predicate_operator"
4287 [(match_operand:BI 1 "register_operand" "c")
4289 (match_operand:SI 2 "gr_register_operand" "r")
4290 (match_operand:SI 3 "gr_register_operand" "r"))]))]
4296 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
4299 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
4301 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4302 VOIDmode, operands[1], const0_rtx);
4304 [(set_attr "itanium_class" "ialu")
4305 (set_attr "predicable" "no")])
4308 ;; ::::::::::::::::::::
4310 ;; :: Call and branch instructions
4312 ;; ::::::::::::::::::::
4314 ;; Subroutine call instruction returning no value. Operand 0 is the function
4315 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4316 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4317 ;; registers used as operands.
4319 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4320 ;; is supplied for the sake of some RISC machines which need to put this
4321 ;; information into the assembler code; they can put it in the RTL instead of
4324 (define_expand "call"
4325 [(use (match_operand:DI 0 "" ""))
4326 (use (match_operand 1 "" ""))
4327 (use (match_operand 2 "" ""))
4328 (use (match_operand 3 "" ""))]
4331 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
4335 (define_expand "sibcall"
4336 [(use (match_operand:DI 0 "" ""))
4337 (use (match_operand 1 "" ""))
4338 (use (match_operand 2 "" ""))
4339 (use (match_operand 3 "" ""))]
4342 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
4346 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4347 ;; register in which the value is returned. There are three more operands,
4348 ;; the same as the three operands of the `call' instruction (but with numbers
4349 ;; increased by one).
4351 ;; Subroutines that return `BLKmode' objects use the `call' insn.
4353 (define_expand "call_value"
4354 [(use (match_operand 0 "" ""))
4355 (use (match_operand:DI 1 "" ""))
4356 (use (match_operand 2 "" ""))
4357 (use (match_operand 3 "" ""))
4358 (use (match_operand 4 "" ""))]
4361 ia64_expand_call (operands[0], operands[1], operands[3], false);
4365 (define_expand "sibcall_value"
4366 [(use (match_operand 0 "" ""))
4367 (use (match_operand:DI 1 "" ""))
4368 (use (match_operand 2 "" ""))
4369 (use (match_operand 3 "" ""))
4370 (use (match_operand 4 "" ""))]
4373 ia64_expand_call (operands[0], operands[1], operands[3], true);
4377 ;; Call subroutine returning any type.
4379 (define_expand "untyped_call"
4380 [(parallel [(call (match_operand 0 "" "")
4382 (match_operand 1 "" "")
4383 (match_operand 2 "" "")])]
4388 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4390 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4392 rtx set = XVECEXP (operands[2], 0, i);
4393 emit_move_insn (SET_DEST (set), SET_SRC (set));
4396 /* The optimizer does not know that the call sets the function value
4397 registers we stored in the result block. We avoid problems by
4398 claiming that all hard registers are used and clobbered at this
4400 emit_insn (gen_blockage ());
4405 (define_insn "call_nogp"
4406 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s"))
4408 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
4410 "br.call%+.many %1 = %0"
4411 [(set_attr "itanium_class" "br,scall")])
4413 (define_insn "call_value_nogp"
4414 [(set (match_operand 0 "" "=X,X")
4415 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,s"))
4417 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4419 "br.call%+.many %2 = %1"
4420 [(set_attr "itanium_class" "br,scall")])
4422 (define_insn "sibcall_nogp"
4423 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s"))
4427 [(set_attr "itanium_class" "br,scall")])
4429 (define_insn "call_gp"
4430 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s"))
4432 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
4433 (clobber (match_scratch:DI 2 "=&r,X"))
4434 (clobber (match_scratch:DI 3 "=b,X"))]
4437 [(set_attr "itanium_class" "br,scall")])
4439 ;; Irritatingly, we don't have access to INSN within the split body.
4440 ;; See commentary in ia64_split_call as to why these aren't peep2.
4442 [(call (mem (match_operand 0 "call_operand" ""))
4444 (clobber (match_operand:DI 1 "register_operand" ""))
4445 (clobber (match_scratch:DI 2 ""))
4446 (clobber (match_scratch:DI 3 ""))]
4447 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4450 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4451 operands[3], true, false);
4456 [(call (mem (match_operand 0 "call_operand" ""))
4458 (clobber (match_operand:DI 1 "register_operand" ""))
4459 (clobber (match_scratch:DI 2 ""))
4460 (clobber (match_scratch:DI 3 ""))]
4464 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4465 operands[3], false, false);
4469 (define_insn "call_value_gp"
4470 [(set (match_operand 0 "" "=X,X")
4471 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,s"))
4473 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
4474 (clobber (match_scratch:DI 3 "=&r,X"))
4475 (clobber (match_scratch:DI 4 "=b,X"))]
4478 [(set_attr "itanium_class" "br,scall")])
4481 [(set (match_operand 0 "" "")
4482 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4484 (clobber (match_operand:DI 2 "register_operand" ""))
4485 (clobber (match_scratch:DI 3 ""))
4486 (clobber (match_scratch:DI 4 ""))]
4487 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4490 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4491 operands[4], true, false);
4496 [(set (match_operand 0 "" "")
4497 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4499 (clobber (match_operand:DI 2 "register_operand" ""))
4500 (clobber (match_scratch:DI 3 ""))
4501 (clobber (match_scratch:DI 4 ""))]
4505 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4506 operands[4], false, false);
4510 (define_insn_and_split "sibcall_gp"
4511 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s"))
4513 (clobber (match_scratch:DI 1 "=&r,X"))
4514 (clobber (match_scratch:DI 2 "=b,X"))]
4520 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
4521 operands[2], true, true);
4524 [(set_attr "itanium_class" "br")])
4526 (define_insn "return_internal"
4528 (use (match_operand:DI 0 "register_operand" "b"))]
4530 "br.ret.sptk.many %0"
4531 [(set_attr "itanium_class" "br")])
4533 (define_insn "return"
4535 "ia64_direct_return ()"
4536 "br.ret.sptk.many rp"
4537 [(set_attr "itanium_class" "br")])
4539 (define_insn "*return_true"
4541 (if_then_else (match_operator 0 "predicate_operator"
4542 [(match_operand:BI 1 "register_operand" "c")
4546 "ia64_direct_return ()"
4547 "(%J0) br.ret%+.many rp"
4548 [(set_attr "itanium_class" "br")
4549 (set_attr "predicable" "no")])
4551 (define_insn "*return_false"
4553 (if_then_else (match_operator 0 "predicate_operator"
4554 [(match_operand:BI 1 "register_operand" "c")
4558 "ia64_direct_return ()"
4559 "(%j0) br.ret%+.many rp"
4560 [(set_attr "itanium_class" "br")
4561 (set_attr "predicable" "no")])
4564 [(set (pc) (label_ref (match_operand 0 "" "")))]
4567 [(set_attr "itanium_class" "br")])
4569 (define_insn "indirect_jump"
4570 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4573 [(set_attr "itanium_class" "br")])
4575 (define_expand "tablejump"
4576 [(parallel [(set (pc) (match_operand 0 "memory_operand" ""))
4577 (use (label_ref (match_operand 1 "" "")))])]
4580 rtx op0 = operands[0];
4583 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
4584 element into a register without bothering to see whether that
4585 is necessary given the operand predicate. Check for MEM just
4586 in case someone fixes this. */
4587 if (GET_CODE (op0) == MEM)
4588 addr = XEXP (op0, 0);
4591 /* Otherwise, cheat and guess that the previous insn in the
4592 stream was the memory load. Grab the address from that.
4593 Note we have to momentarily pop out of the sequence started
4594 by the insn-emit wrapper in order to grab the last insn. */
4598 last = get_last_insn ();
4600 set = single_set (last);
4602 gcc_assert (rtx_equal_p (SET_DEST (set), op0)
4603 && GET_CODE (SET_SRC (set)) == MEM);
4604 addr = XEXP (SET_SRC (set), 0);
4605 gcc_assert (!rtx_equal_p (addr, op0));
4608 /* Jump table elements are stored pc-relative. That is, a displacement
4609 from the entry to the label. Thus to convert to an absolute address
4610 we add the address of the memory from which the value is loaded. */
4611 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
4612 NULL_RTX, 0, OPTAB_DIRECT);
4615 (define_insn "*tablejump_internal"
4616 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4617 (use (label_ref (match_operand 1 "" "")))]
4620 [(set_attr "itanium_class" "br")])
4623 ;; ::::::::::::::::::::
4625 ;; :: Prologue and Epilogue instructions
4627 ;; ::::::::::::::::::::
4629 (define_expand "prologue"
4633 ia64_expand_prologue ();
4637 (define_expand "epilogue"
4641 ia64_expand_epilogue (0);
4645 (define_expand "sibcall_epilogue"
4649 ia64_expand_epilogue (1);
4653 ;; This prevents the scheduler from moving the SP decrement past FP-relative
4654 ;; stack accesses. This is the same as adddi3 plus the extra set.
4655 ;; Explicit predicated version of insn needed to check by CODE_FOR_
4656 ;; in ia64_single_set, where despite of 2 sets this define_insn should be OK.
4658 (define_insn "prologue_allocate_stack"
4659 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4660 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
4661 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
4662 (set (match_operand:DI 3 "register_operand" "+r,r,r")
4669 [(set_attr "itanium_class" "ialu")
4670 (set_attr "predicable" "no")])
4672 (define_insn "prologue_allocate_stack_pr"
4673 [(cond_exec (match_operator 0 ("predicate_operator")
4674 [(match_operand:BI 1 ("register_operand") ("c,c,c"))
4677 [(set (match_operand:DI 2 "register_operand" "=r,r,r")
4678 (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a")
4679 (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J")))
4680 (set (match_operand:DI 5 "register_operand" "+r,r,r")
4684 (%J0) add %2 = %3, %4
4685 (%J0) adds %2 = %3, %4
4686 (%J0) addl %2 = %3, %4"
4687 [(set_attr "itanium_class" "ialu")
4688 (set_attr "predicable" "no")])
4690 ;; This prevents the scheduler from moving the SP restore past FP-relative
4691 ;; stack accesses. This is similar to movdi plus the extra set.
4692 ;; Explicit predicated version of insn needed to check by CODE_FOR_
4693 ;; in ia64_single_set, where despite of 2 sets this define_insn should be OK.
4695 (define_insn "epilogue_deallocate_stack"
4696 [(set (match_operand:DI 0 "register_operand" "=r")
4697 (match_operand:DI 1 "register_operand" "+r"))
4698 (set (match_dup 1) (match_dup 1))]
4701 [(set_attr "itanium_class" "ialu")
4702 (set_attr "predicable" "no")])
4704 (define_insn "epilogue_deallocate_stack_pr"
4705 [(cond_exec (match_operator 0 ("predicate_operator")
4706 [(match_operand:BI 1 ("register_operand") ("c"))
4709 [(set (match_operand:DI 2 "register_operand" "=r")
4710 (match_operand:DI 3 "register_operand" "+r"))
4711 (set (match_dup 3) (match_dup 3))]))]
4714 [(set_attr "itanium_class" "ialu")
4715 (set_attr "predicable" "no")])
4717 ;; As USE insns aren't meaningful after reload, this is used instead
4718 ;; to prevent deleting instructions setting registers for EH handling
4719 (define_insn "prologue_use"
4720 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
4721 UNSPEC_PROLOGUE_USE)]
4724 [(set_attr "itanium_class" "ignore")
4725 (set_attr "predicable" "no")
4726 (set_attr "empty" "yes")])
4728 ;; Allocate a new register frame.
4730 (define_insn "alloc"
4731 [(set (match_operand:DI 0 "register_operand" "=r")
4732 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
4733 (use (match_operand:DI 1 "const_int_operand" "i"))
4734 (use (match_operand:DI 2 "const_int_operand" "i"))
4735 (use (match_operand:DI 3 "const_int_operand" "i"))
4736 (use (match_operand:DI 4 "const_int_operand" "i"))]
4738 "alloc %0 = ar.pfs, %1, %2, %3, %4"
4739 [(set_attr "itanium_class" "syst_m0")
4740 (set_attr "predicable" "no")
4741 (set_attr "first_insn" "yes")])
4744 (define_expand "gr_spill"
4745 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
4746 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4747 (match_operand:DI 2 "const_int_operand" "")]
4749 (clobber (match_dup 3))])]
4751 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4753 (define_insn "gr_spill_internal"
4754 [(set (match_operand:DI 0 "destination_operand" "=m")
4755 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4756 (match_operand:DI 2 "const_int_operand" "")]
4758 (clobber (match_operand:DI 3 "register_operand" ""))]
4761 /* Note that we use a C output pattern here to avoid the predicate
4762 being automatically added before the .mem.offset directive. */
4763 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
4765 [(set_attr "itanium_class" "st")])
4768 (define_expand "gr_restore"
4769 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
4770 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4771 (match_operand:DI 2 "const_int_operand" "")]
4773 (use (match_dup 3))])]
4775 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4777 (define_insn "gr_restore_internal"
4778 [(set (match_operand:DI 0 "register_operand" "=r")
4779 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4780 (match_operand:DI 2 "const_int_operand" "")]
4782 (use (match_operand:DI 3 "register_operand" ""))]
4784 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
4785 [(set_attr "itanium_class" "ld")])
4787 (define_insn "fr_spill"
4788 [(set (match_operand:XF 0 "destination_operand" "=m")
4789 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
4792 "stf.spill %0 = %1%P0"
4793 [(set_attr "itanium_class" "stf")])
4795 (define_insn "fr_restore"
4796 [(set (match_operand:XF 0 "register_operand" "=f")
4797 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
4798 UNSPEC_FR_RESTORE))]
4800 "ldf.fill %0 = %1%P1"
4801 [(set_attr "itanium_class" "fld")])
4803 ;; ??? The explicit stop is not ideal. It would be better if
4804 ;; rtx_needs_barrier took care of this, but this is something that can be
4805 ;; fixed later. This avoids an RSE DV.
4807 (define_insn "bsp_value"
4808 [(set (match_operand:DI 0 "register_operand" "=r")
4809 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
4813 return \";;\;%,mov %0 = ar.bsp\";
4815 [(set_attr "itanium_class" "frar_i")])
4817 (define_insn "set_bsp"
4818 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
4836 [(set_attr "itanium_class" "unknown")
4837 (set_attr "predicable" "no")])
4839 ;; ??? The explicit stops are not ideal. It would be better if
4840 ;; rtx_needs_barrier took care of this, but this is something that can be
4841 ;; fixed later. This avoids an RSE DV.
4843 (define_insn "flushrs"
4844 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
4847 [(set_attr "itanium_class" "rse_m")
4848 (set_attr "predicable" "no")])
4850 ;; ::::::::::::::::::::
4852 ;; :: Miscellaneous instructions
4854 ;; ::::::::::::::::::::
4856 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
4857 ;; be emitting ";;" to force a break in the instruction packing.
4859 ;; No operation, needed in case the user uses -g but not -O.
4864 [(set_attr "itanium_class" "nop")])
4866 (define_insn "nop_m"
4870 [(set_attr "itanium_class" "nop_m")])
4872 (define_insn "nop_i"
4876 [(set_attr "itanium_class" "nop_i")])
4878 (define_insn "nop_f"
4882 [(set_attr "itanium_class" "nop_f")])
4884 (define_insn "nop_b"
4888 [(set_attr "itanium_class" "nop_b")])
4890 (define_insn "nop_x"
4894 [(set_attr "itanium_class" "nop_x")
4895 (set_attr "empty" "yes")])
4897 ;; The following insn will be never generated. It is used only by
4898 ;; insn scheduler to change state before advancing cycle.
4899 (define_insn "pre_cycle"
4903 [(set_attr "itanium_class" "pre_cycle")])
4905 (define_insn "bundle_selector"
4906 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
4908 { return get_bundle_name (INTVAL (operands[0])); }
4909 [(set_attr "itanium_class" "ignore")
4910 (set_attr "predicable" "no")])
4912 ;; Pseudo instruction that prevents the scheduler from moving code above this
4914 (define_insn "blockage"
4915 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4918 [(set_attr "itanium_class" "ignore")
4919 (set_attr "predicable" "no")])
4921 (define_insn "insn_group_barrier"
4922 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
4923 UNSPECV_INSN_GROUP_BARRIER)]
4926 [(set_attr "itanium_class" "stop_bit")
4927 (set_attr "predicable" "no")
4928 (set_attr "empty" "yes")])
4930 (define_expand "trap"
4931 [(trap_if (const_int 1) (const_int 0))]
4935 ;; ??? We don't have a match-any slot type. Setting the type to unknown
4936 ;; produces worse code that setting the slot type to A.
4938 (define_insn "*trap"
4939 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
4942 [(set_attr "itanium_class" "chk_s_i")])
4944 (define_expand "ctrapbi4"
4945 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4946 [(match_operand:BI 1 "register_operand" "")
4947 (match_operand:BI 2 "const_int_operand" "")])
4948 (match_operand 3 "" ""))]
4950 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4952 (define_expand "ctrapsi4"
4953 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4954 [(match_operand:SI 1 "gr_register_operand" "")
4955 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4956 (match_operand 3 "" ""))]
4958 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4960 (define_expand "ctrapdi4"
4961 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4962 [(match_operand:DI 1 "gr_register_operand" "")
4963 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4964 (match_operand 3 "" ""))]
4966 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4968 (define_expand "ctrapsf4"
4969 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4970 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
4971 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
4972 (match_operand 3 "" ""))]
4974 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4976 (define_expand "ctrapdf4"
4977 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4978 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
4979 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
4980 (match_operand 3 "" ""))]
4982 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4984 (define_expand "ctrapxf4"
4985 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4986 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
4987 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
4988 (match_operand 3 "" ""))]
4990 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4992 (define_expand "ctraptf4"
4993 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4994 [(match_operand:TF 1 "gr_register_operand" "")
4995 (match_operand:TF 2 "gr_register_operand" "")])
4996 (match_operand 3 "" ""))]
4998 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
5001 (define_insn "*conditional_trap"
5002 [(trap_if (match_operator 0 "predicate_operator"
5003 [(match_operand:BI 1 "register_operand" "c")
5005 (match_operand 2 "const_int_operand" ""))]
5008 [(set_attr "itanium_class" "chk_s_i")
5009 (set_attr "predicable" "no")])
5011 (define_insn "break_f"
5012 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
5015 [(set_attr "itanium_class" "nop_f")])
5017 (define_insn "prefetch"
5018 [(prefetch (match_operand:DI 0 "address_operand" "p")
5019 (match_operand:DI 1 "const_int_operand" "n")
5020 (match_operand:DI 2 "const_int_operand" "n"))]
5023 static const char * const alt[2][4] = {
5025 "%,lfetch.nta [%0]",
5026 "%,lfetch.nt1 [%0]",
5027 "%,lfetch.nt2 [%0]",
5031 "%,lfetch.excl.nta [%0]",
5032 "%,lfetch.excl.nt1 [%0]",
5033 "%,lfetch.excl.nt2 [%0]",
5034 "%,lfetch.excl [%0]"
5037 int i = (INTVAL (operands[1]));
5038 int j = (INTVAL (operands[2]));
5040 gcc_assert (i == 0 || i == 1);
5041 gcc_assert (j >= 0 && j <= 3);
5044 [(set_attr "itanium_class" "lfetch")])
5046 ;; Non-local goto support.
5048 (define_expand "save_stack_nonlocal"
5049 [(use (match_operand:OI 0 "memory_operand" ""))
5050 (use (match_operand:DI 1 "register_operand" ""))]
5053 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5054 \"__ia64_save_stack_nonlocal\"),
5055 LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5056 operands[1], Pmode);
5060 (define_expand "nonlocal_goto"
5061 [(use (match_operand 0 "general_operand" ""))
5062 (use (match_operand 1 "general_operand" ""))
5063 (use (match_operand 2 "general_operand" ""))
5064 (use (match_operand 3 "general_operand" ""))]
5067 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5068 LCT_NORETURN, VOIDmode, 3,
5070 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5071 operands[3], Pmode);
5076 (define_insn_and_split "nonlocal_goto_receiver"
5077 [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)]
5087 (define_insn_and_split "builtin_setjmp_receiver"
5088 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
5098 (define_expand "eh_epilogue"
5099 [(use (match_operand:DI 0 "register_operand" "r"))
5100 (use (match_operand:DI 1 "register_operand" "r"))
5101 (use (match_operand:DI 2 "register_operand" "r"))]
5104 rtx bsp = gen_rtx_REG (Pmode, 10);
5105 rtx sp = gen_rtx_REG (Pmode, 9);
5107 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5109 emit_move_insn (bsp, operands[0]);
5112 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5114 emit_move_insn (sp, operands[2]);
5120 cfun->machine->ia64_eh_epilogue_sp = sp;
5121 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5124 ;; Builtin apply support.
5126 (define_expand "restore_stack_nonlocal"
5127 [(use (match_operand:DI 0 "register_operand" ""))
5128 (use (match_operand:OI 1 "memory_operand" ""))]
5131 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5132 "__ia64_restore_stack_nonlocal"),
5133 LCT_NORMAL, VOIDmode, 1,
5134 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5142 [(match_operator 0 "predicate_operator"
5143 [(match_operand:BI 1 "register_operand" "c")
5148 (define_insn "pred_rel_mutex"
5149 [(set (match_operand:BI 0 "register_operand" "+c")
5150 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
5152 ".pred.rel.mutex %0, %I0"
5153 [(set_attr "itanium_class" "ignore")
5154 (set_attr "predicable" "no")])
5156 (define_insn "safe_across_calls_all"
5157 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
5159 ".pred.safe_across_calls p1-p63"
5160 [(set_attr "itanium_class" "ignore")
5161 (set_attr "predicable" "no")])
5163 (define_insn "safe_across_calls_normal"
5164 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
5167 emit_safe_across_calls ();
5170 [(set_attr "itanium_class" "ignore")
5171 (set_attr "predicable" "no")])
5173 ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit
5174 ;; pointer. This is used by the HP-UX 32 bit mode.
5176 (define_insn "ptr_extend"
5177 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5178 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5182 [(set_attr "itanium_class" "ialu")])
5185 ;; Optimizations for ptr_extend
5187 (define_insn "ptr_extend_plus_imm"
5188 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5190 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5191 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
5193 "addp4_optimize_ok (operands[1], operands[2])"
5195 [(set_attr "itanium_class" "ialu")])
5197 (define_insn "*ptr_extend_plus_2"
5198 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5200 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5201 (match_operand:SI 2 "basereg_operand" "r"))]
5203 "addp4_optimize_ok (operands[1], operands[2])"
5205 [(set_attr "itanium_class" "ialu")])
5208 ;; Get instruction pointer
5210 (define_insn "ip_value"
5211 [(set (match_operand:DI 0 "register_operand" "=r")
5215 [(set_attr "itanium_class" "frbr")])
5220 (define_insn "probe_stack_address"
5221 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5222 UNSPECV_PROBE_STACK_ADDRESS)]
5224 "probe.w.fault %0, 0"
5225 [(set_attr "itanium_class" "chk_s_i")])
5227 (define_insn "probe_stack_range"
5228 [(set (match_operand:DI 0 "register_operand" "=r")
5229 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")
5230 (match_operand:DI 2 "register_operand" "r")]
5231 UNSPECV_PROBE_STACK_RANGE))]
5233 "* return output_probe_stack_range (operands[0], operands[2]);"
5234 [(set_attr "itanium_class" "unknown")
5235 (set_attr "predicable" "no")])
5237 ;; Vector operations
5239 ;; Atomic operations
5241 ;; New division operations