1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "diagnostic-core.h"
37 #include "selftest-rtl.h"
38 #include "rtx-vector-builder.h"
41 /* Simplification and canonicalization of RTL. */
43 /* Much code operates on (low, high) pairs; the low value is an
44 unsigned wide int, the high value a signed wide int. We
45 occasionally need to sign extend from low to high as if low were a
47 #define HWI_SIGN_EXTEND(low) \
48 ((((HOST_WIDE_INT) low) < 0) ? HOST_WIDE_INT_M1 : HOST_WIDE_INT_0)
50 static bool plus_minus_operand_p (const_rtx
);
52 /* Negate I, which satisfies poly_int_rtx_p. MODE is the mode of I. */
55 neg_poly_int_rtx (machine_mode mode
, const_rtx i
)
57 return immed_wide_int_const (-wi::to_poly_wide (i
, mode
), mode
);
60 /* Test whether expression, X, is an immediate constant that represents
61 the most significant bit of machine mode MODE. */
64 mode_signbit_p (machine_mode mode
, const_rtx x
)
66 unsigned HOST_WIDE_INT val
;
68 scalar_int_mode int_mode
;
70 if (!is_int_mode (mode
, &int_mode
))
73 width
= GET_MODE_PRECISION (int_mode
);
77 if (width
<= HOST_BITS_PER_WIDE_INT
80 #if TARGET_SUPPORTS_WIDE_INT
81 else if (CONST_WIDE_INT_P (x
))
84 unsigned int elts
= CONST_WIDE_INT_NUNITS (x
);
85 if (elts
!= (width
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
)
87 for (i
= 0; i
< elts
- 1; i
++)
88 if (CONST_WIDE_INT_ELT (x
, i
) != 0)
90 val
= CONST_WIDE_INT_ELT (x
, elts
- 1);
91 width
%= HOST_BITS_PER_WIDE_INT
;
93 width
= HOST_BITS_PER_WIDE_INT
;
96 else if (width
<= HOST_BITS_PER_DOUBLE_INT
97 && CONST_DOUBLE_AS_INT_P (x
)
98 && CONST_DOUBLE_LOW (x
) == 0)
100 val
= CONST_DOUBLE_HIGH (x
);
101 width
-= HOST_BITS_PER_WIDE_INT
;
105 /* X is not an integer constant. */
108 if (width
< HOST_BITS_PER_WIDE_INT
)
109 val
&= (HOST_WIDE_INT_1U
<< width
) - 1;
110 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
113 /* Test whether VAL is equal to the most significant bit of mode MODE
114 (after masking with the mode mask of MODE). Returns false if the
115 precision of MODE is too large to handle. */
118 val_signbit_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
121 scalar_int_mode int_mode
;
123 if (!is_int_mode (mode
, &int_mode
))
126 width
= GET_MODE_PRECISION (int_mode
);
127 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
130 val
&= GET_MODE_MASK (int_mode
);
131 return val
== (HOST_WIDE_INT_1U
<< (width
- 1));
134 /* Test whether the most significant bit of mode MODE is set in VAL.
135 Returns false if the precision of MODE is too large to handle. */
137 val_signbit_known_set_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
141 scalar_int_mode int_mode
;
142 if (!is_int_mode (mode
, &int_mode
))
145 width
= GET_MODE_PRECISION (int_mode
);
146 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
149 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
153 /* Test whether the most significant bit of mode MODE is clear in VAL.
154 Returns false if the precision of MODE is too large to handle. */
156 val_signbit_known_clear_p (machine_mode mode
, unsigned HOST_WIDE_INT val
)
160 scalar_int_mode int_mode
;
161 if (!is_int_mode (mode
, &int_mode
))
164 width
= GET_MODE_PRECISION (int_mode
);
165 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
168 val
&= HOST_WIDE_INT_1U
<< (width
- 1);
172 /* Make a binary operation by properly ordering the operands and
173 seeing if the expression folds. */
176 simplify_context::simplify_gen_binary (rtx_code code
, machine_mode mode
,
181 /* If this simplifies, do it. */
182 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
186 /* Put complex operands first and constants second if commutative. */
187 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
188 && swap_commutative_operands_p (op0
, op1
))
189 std::swap (op0
, op1
);
191 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
194 /* If X is a MEM referencing the constant pool, return the real value.
195 Otherwise return X. */
197 avoid_constant_pool_reference (rtx x
)
201 poly_int64 offset
= 0;
203 switch (GET_CODE (x
))
209 /* Handle float extensions of constant pool references. */
211 c
= avoid_constant_pool_reference (tmp
);
212 if (c
!= tmp
&& CONST_DOUBLE_AS_FLOAT_P (c
))
213 return const_double_from_real_value (*CONST_DOUBLE_REAL_VALUE (c
),
221 if (GET_MODE (x
) == BLKmode
)
226 /* Call target hook to avoid the effects of -fpic etc.... */
227 addr
= targetm
.delegitimize_address (addr
);
229 /* Split the address into a base and integer offset. */
230 addr
= strip_offset (addr
, &offset
);
232 if (GET_CODE (addr
) == LO_SUM
)
233 addr
= XEXP (addr
, 1);
235 /* If this is a constant pool reference, we can turn it into its
236 constant and hope that simplifications happen. */
237 if (GET_CODE (addr
) == SYMBOL_REF
238 && CONSTANT_POOL_ADDRESS_P (addr
))
240 c
= get_pool_constant (addr
);
241 cmode
= get_pool_mode (addr
);
243 /* If we're accessing the constant in a different mode than it was
244 originally stored, attempt to fix that up via subreg simplifications.
245 If that fails we have no choice but to return the original memory. */
246 if (known_eq (offset
, 0) && cmode
== GET_MODE (x
))
248 else if (known_in_range_p (offset
, 0, GET_MODE_SIZE (cmode
)))
250 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
251 if (tem
&& CONSTANT_P (tem
))
259 /* Simplify a MEM based on its attributes. This is the default
260 delegitimize_address target hook, and it's recommended that every
261 overrider call it. */
264 delegitimize_mem_from_attrs (rtx x
)
266 /* MEMs without MEM_OFFSETs may have been offset, so we can't just
267 use their base addresses as equivalent. */
270 && MEM_OFFSET_KNOWN_P (x
))
272 tree decl
= MEM_EXPR (x
);
273 machine_mode mode
= GET_MODE (x
);
274 poly_int64 offset
= 0;
276 switch (TREE_CODE (decl
))
286 case ARRAY_RANGE_REF
:
291 case VIEW_CONVERT_EXPR
:
293 poly_int64 bitsize
, bitpos
, bytepos
, toffset_val
= 0;
295 int unsignedp
, reversep
, volatilep
= 0;
298 = get_inner_reference (decl
, &bitsize
, &bitpos
, &toffset
, &mode
,
299 &unsignedp
, &reversep
, &volatilep
);
300 if (maybe_ne (bitsize
, GET_MODE_BITSIZE (mode
))
301 || !multiple_p (bitpos
, BITS_PER_UNIT
, &bytepos
)
302 || (toffset
&& !poly_int_tree_p (toffset
, &toffset_val
)))
305 offset
+= bytepos
+ toffset_val
;
311 && mode
== GET_MODE (x
)
313 && (TREE_STATIC (decl
)
314 || DECL_THREAD_LOCAL_P (decl
))
315 && DECL_RTL_SET_P (decl
)
316 && MEM_P (DECL_RTL (decl
)))
320 offset
+= MEM_OFFSET (x
);
322 newx
= DECL_RTL (decl
);
326 rtx n
= XEXP (newx
, 0), o
= XEXP (x
, 0);
327 poly_int64 n_offset
, o_offset
;
329 /* Avoid creating a new MEM needlessly if we already had
330 the same address. We do if there's no OFFSET and the
331 old address X is identical to NEWX, or if X is of the
332 form (plus NEWX OFFSET), or the NEWX is of the form
333 (plus Y (const_int Z)) and X is that with the offset
334 added: (plus Y (const_int Z+OFFSET)). */
335 n
= strip_offset (n
, &n_offset
);
336 o
= strip_offset (o
, &o_offset
);
337 if (!(known_eq (o_offset
, n_offset
+ offset
)
338 && rtx_equal_p (o
, n
)))
339 x
= adjust_address_nv (newx
, mode
, offset
);
341 else if (GET_MODE (x
) == GET_MODE (newx
)
342 && known_eq (offset
, 0))
350 /* Make a unary operation by first seeing if it folds and otherwise making
351 the specified operation. */
354 simplify_context::simplify_gen_unary (rtx_code code
, machine_mode mode
, rtx op
,
355 machine_mode op_mode
)
359 /* If this simplifies, use it. */
360 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
363 return gen_rtx_fmt_e (code
, mode
, op
);
366 /* Likewise for ternary operations. */
369 simplify_context::simplify_gen_ternary (rtx_code code
, machine_mode mode
,
370 machine_mode op0_mode
,
371 rtx op0
, rtx op1
, rtx op2
)
375 /* If this simplifies, use it. */
376 if ((tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
377 op0
, op1
, op2
)) != 0)
380 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
383 /* Likewise, for relational operations.
384 CMP_MODE specifies mode comparison is done in. */
387 simplify_context::simplify_gen_relational (rtx_code code
, machine_mode mode
,
388 machine_mode cmp_mode
,
393 if ((tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
397 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
400 /* If FN is NULL, replace all occurrences of OLD_RTX in X with copy_rtx (DATA)
401 and simplify the result. If FN is non-NULL, call this callback on each
402 X, if it returns non-NULL, replace X with its return value and simplify the
406 simplify_replace_fn_rtx (rtx x
, const_rtx old_rtx
,
407 rtx (*fn
) (rtx
, const_rtx
, void *), void *data
)
409 enum rtx_code code
= GET_CODE (x
);
410 machine_mode mode
= GET_MODE (x
);
411 machine_mode op_mode
;
413 rtx op0
, op1
, op2
, newx
, op
;
417 if (UNLIKELY (fn
!= NULL
))
419 newx
= fn (x
, old_rtx
, data
);
423 else if (rtx_equal_p (x
, old_rtx
))
424 return copy_rtx ((rtx
) data
);
426 switch (GET_RTX_CLASS (code
))
430 op_mode
= GET_MODE (op0
);
431 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
432 if (op0
== XEXP (x
, 0))
434 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
438 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
439 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
440 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
442 return simplify_gen_binary (code
, mode
, op0
, op1
);
445 case RTX_COMM_COMPARE
:
448 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
449 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
450 op1
= simplify_replace_fn_rtx (op1
, old_rtx
, fn
, data
);
451 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
453 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
456 case RTX_BITFIELD_OPS
:
458 op_mode
= GET_MODE (op0
);
459 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
460 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
461 op2
= simplify_replace_fn_rtx (XEXP (x
, 2), old_rtx
, fn
, data
);
462 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
464 if (op_mode
== VOIDmode
)
465 op_mode
= GET_MODE (op0
);
466 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
471 op0
= simplify_replace_fn_rtx (SUBREG_REG (x
), old_rtx
, fn
, data
);
472 if (op0
== SUBREG_REG (x
))
474 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
475 GET_MODE (SUBREG_REG (x
)),
477 return op0
? op0
: x
;
484 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
485 if (op0
== XEXP (x
, 0))
487 return replace_equiv_address_nv (x
, op0
);
489 else if (code
== LO_SUM
)
491 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
492 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
494 /* (lo_sum (high x) y) -> y where x and y have the same base. */
495 if (GET_CODE (op0
) == HIGH
)
497 rtx base0
, base1
, offset0
, offset1
;
498 split_const (XEXP (op0
, 0), &base0
, &offset0
);
499 split_const (op1
, &base1
, &offset1
);
500 if (rtx_equal_p (base0
, base1
))
504 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
506 return gen_rtx_LO_SUM (mode
, op0
, op1
);
515 fmt
= GET_RTX_FORMAT (code
);
516 for (i
= 0; fmt
[i
]; i
++)
521 newvec
= XVEC (newx
, i
);
522 for (j
= 0; j
< GET_NUM_ELEM (vec
); j
++)
524 op
= simplify_replace_fn_rtx (RTVEC_ELT (vec
, j
),
526 if (op
!= RTVEC_ELT (vec
, j
))
530 newvec
= shallow_copy_rtvec (vec
);
532 newx
= shallow_copy_rtx (x
);
533 XVEC (newx
, i
) = newvec
;
535 RTVEC_ELT (newvec
, j
) = op
;
543 op
= simplify_replace_fn_rtx (XEXP (x
, i
), old_rtx
, fn
, data
);
544 if (op
!= XEXP (x
, i
))
547 newx
= shallow_copy_rtx (x
);
556 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
557 resulting RTX. Return a new RTX which is as simplified as possible. */
560 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
562 return simplify_replace_fn_rtx (x
, old_rtx
, 0, new_rtx
);
565 /* Try to simplify a MODE truncation of OP, which has OP_MODE.
566 Only handle cases where the truncated value is inherently an rvalue.
568 RTL provides two ways of truncating a value:
570 1. a lowpart subreg. This form is only a truncation when both
571 the outer and inner modes (here MODE and OP_MODE respectively)
572 are scalar integers, and only then when the subreg is used as
575 It is only valid to form such truncating subregs if the
576 truncation requires no action by the target. The onus for
577 proving this is on the creator of the subreg -- e.g. the
578 caller to simplify_subreg or simplify_gen_subreg -- and typically
579 involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
581 2. a TRUNCATE. This form handles both scalar and compound integers.
583 The first form is preferred where valid. However, the TRUNCATE
584 handling in simplify_unary_operation turns the second form into the
585 first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
586 so it is generally safe to form rvalue truncations using:
588 simplify_gen_unary (TRUNCATE, ...)
590 and leave simplify_unary_operation to work out which representation
593 Because of the proof requirements on (1), simplify_truncation must
594 also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
595 regardless of whether the outer truncation came from a SUBREG or a
596 TRUNCATE. For example, if the caller has proven that an SImode
601 is a no-op and can be represented as a subreg, it does not follow
602 that SImode truncations of X and Y are also no-ops. On a target
603 like 64-bit MIPS that requires SImode values to be stored in
604 sign-extended form, an SImode truncation of:
606 (and:DI (reg:DI X) (const_int 63))
608 is trivially a no-op because only the lower 6 bits can be set.
609 However, X is still an arbitrary 64-bit number and so we cannot
610 assume that truncating it too is a no-op. */
613 simplify_context::simplify_truncation (machine_mode mode
, rtx op
,
614 machine_mode op_mode
)
616 unsigned int precision
= GET_MODE_UNIT_PRECISION (mode
);
617 unsigned int op_precision
= GET_MODE_UNIT_PRECISION (op_mode
);
618 scalar_int_mode int_mode
, int_op_mode
, subreg_mode
;
620 gcc_assert (precision
<= op_precision
);
622 /* Optimize truncations of zero and sign extended values. */
623 if (GET_CODE (op
) == ZERO_EXTEND
624 || GET_CODE (op
) == SIGN_EXTEND
)
626 /* There are three possibilities. If MODE is the same as the
627 origmode, we can omit both the extension and the subreg.
628 If MODE is not larger than the origmode, we can apply the
629 truncation without the extension. Finally, if the outermode
630 is larger than the origmode, we can just extend to the appropriate
632 machine_mode origmode
= GET_MODE (XEXP (op
, 0));
633 if (mode
== origmode
)
635 else if (precision
<= GET_MODE_UNIT_PRECISION (origmode
))
636 return simplify_gen_unary (TRUNCATE
, mode
,
637 XEXP (op
, 0), origmode
);
639 return simplify_gen_unary (GET_CODE (op
), mode
,
640 XEXP (op
, 0), origmode
);
643 /* If the machine can perform operations in the truncated mode, distribute
644 the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
645 (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
647 && (!WORD_REGISTER_OPERATIONS
|| precision
>= BITS_PER_WORD
)
648 && (GET_CODE (op
) == PLUS
649 || GET_CODE (op
) == MINUS
650 || GET_CODE (op
) == MULT
))
652 rtx op0
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0), op_mode
);
655 rtx op1
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 1), op_mode
);
657 return simplify_gen_binary (GET_CODE (op
), mode
, op0
, op1
);
661 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
662 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
663 the outer subreg is effectively a truncation to the original mode. */
664 if ((GET_CODE (op
) == LSHIFTRT
665 || GET_CODE (op
) == ASHIFTRT
)
666 /* Ensure that OP_MODE is at least twice as wide as MODE
667 to avoid the possibility that an outer LSHIFTRT shifts by more
668 than the sign extension's sign_bit_copies and introduces zeros
669 into the high bits of the result. */
670 && 2 * precision
<= op_precision
671 && CONST_INT_P (XEXP (op
, 1))
672 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
673 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
674 && UINTVAL (XEXP (op
, 1)) < precision
)
675 return simplify_gen_binary (ASHIFTRT
, mode
,
676 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
678 /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
679 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
680 the outer subreg is effectively a truncation to the original mode. */
681 if ((GET_CODE (op
) == LSHIFTRT
682 || GET_CODE (op
) == ASHIFTRT
)
683 && CONST_INT_P (XEXP (op
, 1))
684 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
685 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
686 && UINTVAL (XEXP (op
, 1)) < precision
)
687 return simplify_gen_binary (LSHIFTRT
, mode
,
688 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
690 /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
691 to (ashift:QI (x:QI) C), where C is a suitable small constant and
692 the outer subreg is effectively a truncation to the original mode. */
693 if (GET_CODE (op
) == ASHIFT
694 && CONST_INT_P (XEXP (op
, 1))
695 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
696 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
697 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
698 && UINTVAL (XEXP (op
, 1)) < precision
)
699 return simplify_gen_binary (ASHIFT
, mode
,
700 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
702 /* Likewise (truncate:QI (and:SI (lshiftrt:SI (x:SI) C) C2)) into
703 (and:QI (lshiftrt:QI (truncate:QI (x:SI)) C) C2) for suitable C
705 if (GET_CODE (op
) == AND
706 && (GET_CODE (XEXP (op
, 0)) == LSHIFTRT
707 || GET_CODE (XEXP (op
, 0)) == ASHIFTRT
)
708 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
709 && CONST_INT_P (XEXP (op
, 1)))
711 rtx op0
= (XEXP (XEXP (op
, 0), 0));
712 rtx shift_op
= XEXP (XEXP (op
, 0), 1);
713 rtx mask_op
= XEXP (op
, 1);
714 unsigned HOST_WIDE_INT shift
= UINTVAL (shift_op
);
715 unsigned HOST_WIDE_INT mask
= UINTVAL (mask_op
);
717 if (shift
< precision
718 /* If doing this transform works for an X with all bits set,
719 it works for any X. */
720 && ((GET_MODE_MASK (mode
) >> shift
) & mask
)
721 == ((GET_MODE_MASK (op_mode
) >> shift
) & mask
)
722 && (op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, op_mode
))
723 && (op0
= simplify_gen_binary (LSHIFTRT
, mode
, op0
, shift_op
)))
725 mask_op
= GEN_INT (trunc_int_for_mode (mask
, mode
));
726 return simplify_gen_binary (AND
, mode
, op0
, mask_op
);
730 /* Turn (truncate:M1 (*_extract:M2 (reg:M2) (len) (pos))) into
731 (*_extract:M1 (truncate:M1 (reg:M2)) (len) (pos')) if possible without
733 if ((GET_CODE (op
) == ZERO_EXTRACT
|| GET_CODE (op
) == SIGN_EXTRACT
)
734 && REG_P (XEXP (op
, 0))
735 && GET_MODE (XEXP (op
, 0)) == GET_MODE (op
)
736 && CONST_INT_P (XEXP (op
, 1))
737 && CONST_INT_P (XEXP (op
, 2)))
739 rtx op0
= XEXP (op
, 0);
740 unsigned HOST_WIDE_INT len
= UINTVAL (XEXP (op
, 1));
741 unsigned HOST_WIDE_INT pos
= UINTVAL (XEXP (op
, 2));
742 if (BITS_BIG_ENDIAN
&& pos
>= op_precision
- precision
)
744 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
747 pos
-= op_precision
- precision
;
748 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
749 XEXP (op
, 1), GEN_INT (pos
));
752 else if (!BITS_BIG_ENDIAN
&& precision
>= len
+ pos
)
754 op0
= simplify_gen_unary (TRUNCATE
, mode
, op0
, GET_MODE (op0
));
756 return simplify_gen_ternary (GET_CODE (op
), mode
, mode
, op0
,
757 XEXP (op
, 1), XEXP (op
, 2));
761 /* Recognize a word extraction from a multi-word subreg. */
762 if ((GET_CODE (op
) == LSHIFTRT
763 || GET_CODE (op
) == ASHIFTRT
)
764 && SCALAR_INT_MODE_P (mode
)
765 && SCALAR_INT_MODE_P (op_mode
)
766 && precision
>= BITS_PER_WORD
767 && 2 * precision
<= op_precision
768 && CONST_INT_P (XEXP (op
, 1))
769 && (INTVAL (XEXP (op
, 1)) & (precision
- 1)) == 0
770 && UINTVAL (XEXP (op
, 1)) < op_precision
)
772 poly_int64 byte
= subreg_lowpart_offset (mode
, op_mode
);
773 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
774 return simplify_gen_subreg (mode
, XEXP (op
, 0), op_mode
,
776 ? byte
- shifted_bytes
777 : byte
+ shifted_bytes
));
780 /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
781 and try replacing the TRUNCATE and shift with it. Don't do this
782 if the MEM has a mode-dependent address. */
783 if ((GET_CODE (op
) == LSHIFTRT
784 || GET_CODE (op
) == ASHIFTRT
)
785 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
786 && is_a
<scalar_int_mode
> (op_mode
, &int_op_mode
)
787 && MEM_P (XEXP (op
, 0))
788 && CONST_INT_P (XEXP (op
, 1))
789 && INTVAL (XEXP (op
, 1)) % GET_MODE_BITSIZE (int_mode
) == 0
790 && INTVAL (XEXP (op
, 1)) > 0
791 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (int_op_mode
)
792 && ! mode_dependent_address_p (XEXP (XEXP (op
, 0), 0),
793 MEM_ADDR_SPACE (XEXP (op
, 0)))
794 && ! MEM_VOLATILE_P (XEXP (op
, 0))
795 && (GET_MODE_SIZE (int_mode
) >= UNITS_PER_WORD
796 || WORDS_BIG_ENDIAN
== BYTES_BIG_ENDIAN
))
798 poly_int64 byte
= subreg_lowpart_offset (int_mode
, int_op_mode
);
799 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
800 return adjust_address_nv (XEXP (op
, 0), int_mode
,
802 ? byte
- shifted_bytes
803 : byte
+ shifted_bytes
));
806 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
807 (OP:SI foo:SI) if OP is NEG or ABS. */
808 if ((GET_CODE (op
) == ABS
809 || GET_CODE (op
) == NEG
)
810 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
811 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
812 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
813 return simplify_gen_unary (GET_CODE (op
), mode
,
814 XEXP (XEXP (op
, 0), 0), mode
);
816 /* Simplifications of (truncate:A (subreg:B X 0)). */
817 if (GET_CODE (op
) == SUBREG
818 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
819 && SCALAR_INT_MODE_P (op_mode
)
820 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &subreg_mode
)
821 && subreg_lowpart_p (op
))
823 /* (truncate:A (subreg:B (truncate:C X) 0)) is (truncate:A X). */
824 if (GET_CODE (SUBREG_REG (op
)) == TRUNCATE
)
826 rtx inner
= XEXP (SUBREG_REG (op
), 0);
827 if (GET_MODE_PRECISION (int_mode
)
828 <= GET_MODE_PRECISION (subreg_mode
))
829 return simplify_gen_unary (TRUNCATE
, int_mode
, inner
,
832 /* If subreg above is paradoxical and C is narrower
833 than A, return (subreg:A (truncate:C X) 0). */
834 return simplify_gen_subreg (int_mode
, SUBREG_REG (op
),
838 /* Simplifications of (truncate:A (subreg:B X:C 0)) with
839 paradoxical subregs (B is wider than C). */
840 if (is_a
<scalar_int_mode
> (op_mode
, &int_op_mode
))
842 unsigned int int_op_prec
= GET_MODE_PRECISION (int_op_mode
);
843 unsigned int subreg_prec
= GET_MODE_PRECISION (subreg_mode
);
844 if (int_op_prec
> subreg_prec
)
846 if (int_mode
== subreg_mode
)
847 return SUBREG_REG (op
);
848 if (GET_MODE_PRECISION (int_mode
) < subreg_prec
)
849 return simplify_gen_unary (TRUNCATE
, int_mode
,
850 SUBREG_REG (op
), subreg_mode
);
852 /* Simplification of (truncate:A (subreg:B X:C 0)) where
853 A is narrower than B and B is narrower than C. */
854 else if (int_op_prec
< subreg_prec
855 && GET_MODE_PRECISION (int_mode
) < int_op_prec
)
856 return simplify_gen_unary (TRUNCATE
, int_mode
,
857 SUBREG_REG (op
), subreg_mode
);
861 /* (truncate:A (truncate:B X)) is (truncate:A X). */
862 if (GET_CODE (op
) == TRUNCATE
)
863 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0),
864 GET_MODE (XEXP (op
, 0)));
866 /* (truncate:A (ior X C)) is (const_int -1) if C is equal to that already,
868 if (GET_CODE (op
) == IOR
869 && SCALAR_INT_MODE_P (mode
)
870 && SCALAR_INT_MODE_P (op_mode
)
871 && CONST_INT_P (XEXP (op
, 1))
872 && trunc_int_for_mode (INTVAL (XEXP (op
, 1)), mode
) == -1)
878 /* Try to simplify a unary operation CODE whose output mode is to be
879 MODE with input operand OP whose mode was originally OP_MODE.
880 Return zero if no simplification can be made. */
882 simplify_context::simplify_unary_operation (rtx_code code
, machine_mode mode
,
883 rtx op
, machine_mode op_mode
)
887 trueop
= avoid_constant_pool_reference (op
);
889 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
893 return simplify_unary_operation_1 (code
, mode
, op
);
896 /* Return true if FLOAT or UNSIGNED_FLOAT operation OP is known
900 exact_int_to_float_conversion_p (const_rtx op
)
902 machine_mode op0_mode
= GET_MODE (XEXP (op
, 0));
903 /* Constants can reach here with -frounding-math, if they do then
904 the conversion isn't exact. */
905 if (op0_mode
== VOIDmode
)
907 int out_bits
= significand_size (GET_MODE_INNER (GET_MODE (op
)));
908 int in_prec
= GET_MODE_UNIT_PRECISION (op0_mode
);
909 int in_bits
= in_prec
;
910 if (HWI_COMPUTABLE_MODE_P (op0_mode
))
912 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (XEXP (op
, 0), op0_mode
);
913 if (GET_CODE (op
) == FLOAT
)
914 in_bits
-= num_sign_bit_copies (XEXP (op
, 0), op0_mode
);
915 else if (GET_CODE (op
) == UNSIGNED_FLOAT
)
916 in_bits
= wi::min_precision (wi::uhwi (nonzero
, in_prec
), UNSIGNED
);
919 in_bits
-= wi::ctz (wi::uhwi (nonzero
, in_prec
));
921 return in_bits
<= out_bits
;
924 /* Perform some simplifications we can do even if the operands
927 simplify_context::simplify_unary_operation_1 (rtx_code code
, machine_mode mode
,
930 enum rtx_code reversed
;
931 rtx temp
, elt
, base
, step
;
932 scalar_int_mode inner
, int_mode
, op_mode
, op0_mode
;
937 /* (not (not X)) == X. */
938 if (GET_CODE (op
) == NOT
)
941 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
942 comparison is all ones. */
943 if (COMPARISON_P (op
)
944 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
945 && ((reversed
= reversed_comparison_code (op
, NULL
)) != UNKNOWN
))
946 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
947 XEXP (op
, 0), XEXP (op
, 1));
949 /* (not (plus X -1)) can become (neg X). */
950 if (GET_CODE (op
) == PLUS
951 && XEXP (op
, 1) == constm1_rtx
)
952 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
954 /* Similarly, (not (neg X)) is (plus X -1). Only do this for
955 modes that have CONSTM1_RTX, i.e. MODE_INT, MODE_PARTIAL_INT
956 and MODE_VECTOR_INT. */
957 if (GET_CODE (op
) == NEG
&& CONSTM1_RTX (mode
))
958 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
961 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
962 if (GET_CODE (op
) == XOR
963 && CONST_INT_P (XEXP (op
, 1))
964 && (temp
= simplify_unary_operation (NOT
, mode
,
965 XEXP (op
, 1), mode
)) != 0)
966 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
968 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
969 if (GET_CODE (op
) == PLUS
970 && CONST_INT_P (XEXP (op
, 1))
971 && mode_signbit_p (mode
, XEXP (op
, 1))
972 && (temp
= simplify_unary_operation (NOT
, mode
,
973 XEXP (op
, 1), mode
)) != 0)
974 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
977 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
978 operands other than 1, but that is not valid. We could do a
979 similar simplification for (not (lshiftrt C X)) where C is
980 just the sign bit, but this doesn't seem common enough to
982 if (GET_CODE (op
) == ASHIFT
983 && XEXP (op
, 0) == const1_rtx
)
985 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
986 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
989 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
990 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
991 so we can perform the above simplification. */
992 if (STORE_FLAG_VALUE
== -1
993 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
994 && GET_CODE (op
) == ASHIFTRT
995 && CONST_INT_P (XEXP (op
, 1))
996 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
997 return simplify_gen_relational (GE
, int_mode
, VOIDmode
,
998 XEXP (op
, 0), const0_rtx
);
1001 if (partial_subreg_p (op
)
1002 && subreg_lowpart_p (op
)
1003 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
1004 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
1006 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
1009 x
= gen_rtx_ROTATE (inner_mode
,
1010 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
1012 XEXP (SUBREG_REG (op
), 1));
1013 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
1018 /* Apply De Morgan's laws to reduce number of patterns for machines
1019 with negating logical insns (and-not, nand, etc.). If result has
1020 only one NOT, put it first, since that is how the patterns are
1022 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
1024 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
1025 machine_mode op_mode
;
1027 op_mode
= GET_MODE (in1
);
1028 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
1030 op_mode
= GET_MODE (in2
);
1031 if (op_mode
== VOIDmode
)
1033 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
1035 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
1036 std::swap (in1
, in2
);
1038 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
1042 /* (not (bswap x)) -> (bswap (not x)). */
1043 if (GET_CODE (op
) == BSWAP
|| GET_CODE (op
) == BITREVERSE
)
1045 rtx x
= simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1046 return simplify_gen_unary (GET_CODE (op
), mode
, x
, mode
);
1051 /* (neg (neg X)) == X. */
1052 if (GET_CODE (op
) == NEG
)
1053 return XEXP (op
, 0);
1055 /* (neg (x ? (neg y) : y)) == !x ? (neg y) : y.
1056 If comparison is not reversible use
1058 if (GET_CODE (op
) == IF_THEN_ELSE
)
1060 rtx cond
= XEXP (op
, 0);
1061 rtx true_rtx
= XEXP (op
, 1);
1062 rtx false_rtx
= XEXP (op
, 2);
1064 if ((GET_CODE (true_rtx
) == NEG
1065 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
1066 || (GET_CODE (false_rtx
) == NEG
1067 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
)))
1069 if (reversed_comparison_code (cond
, NULL
) != UNKNOWN
)
1070 temp
= reversed_comparison (cond
, mode
);
1074 std::swap (true_rtx
, false_rtx
);
1076 return simplify_gen_ternary (IF_THEN_ELSE
, mode
,
1077 mode
, temp
, true_rtx
, false_rtx
);
1081 /* (neg (plus X 1)) can become (not X). */
1082 if (GET_CODE (op
) == PLUS
1083 && XEXP (op
, 1) == const1_rtx
)
1084 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
1086 /* Similarly, (neg (not X)) is (plus X 1). */
1087 if (GET_CODE (op
) == NOT
)
1088 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
1091 /* (neg (minus X Y)) can become (minus Y X). This transformation
1092 isn't safe for modes with signed zeros, since if X and Y are
1093 both +0, (minus Y X) is the same as (minus X Y). If the
1094 rounding mode is towards +infinity (or -infinity) then the two
1095 expressions will be rounded differently. */
1096 if (GET_CODE (op
) == MINUS
1097 && !HONOR_SIGNED_ZEROS (mode
)
1098 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1099 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
1101 if (GET_CODE (op
) == PLUS
1102 && !HONOR_SIGNED_ZEROS (mode
)
1103 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1105 /* (neg (plus A C)) is simplified to (minus -C A). */
1106 if (CONST_SCALAR_INT_P (XEXP (op
, 1))
1107 || CONST_DOUBLE_AS_FLOAT_P (XEXP (op
, 1)))
1109 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
1111 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
1114 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
1115 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
1116 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
1119 /* (neg (mult A B)) becomes (mult A (neg B)).
1120 This works even for floating-point values. */
1121 if (GET_CODE (op
) == MULT
1122 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
1124 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 1), mode
);
1125 return simplify_gen_binary (MULT
, mode
, XEXP (op
, 0), temp
);
1128 /* NEG commutes with ASHIFT since it is multiplication. Only do
1129 this if we can then eliminate the NEG (e.g., if the operand
1131 if (GET_CODE (op
) == ASHIFT
)
1133 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
1135 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
1138 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
1139 C is equal to the width of MODE minus 1. */
1140 if (GET_CODE (op
) == ASHIFTRT
1141 && CONST_INT_P (XEXP (op
, 1))
1142 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1143 return simplify_gen_binary (LSHIFTRT
, mode
,
1144 XEXP (op
, 0), XEXP (op
, 1));
1146 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
1147 C is equal to the width of MODE minus 1. */
1148 if (GET_CODE (op
) == LSHIFTRT
1149 && CONST_INT_P (XEXP (op
, 1))
1150 && INTVAL (XEXP (op
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
1151 return simplify_gen_binary (ASHIFTRT
, mode
,
1152 XEXP (op
, 0), XEXP (op
, 1));
1154 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
1155 if (GET_CODE (op
) == XOR
1156 && XEXP (op
, 1) == const1_rtx
1157 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
1158 return plus_constant (mode
, XEXP (op
, 0), -1);
1160 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
1161 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
1162 if (GET_CODE (op
) == LT
1163 && XEXP (op
, 1) == const0_rtx
1164 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op
, 0)), &inner
))
1166 int_mode
= as_a
<scalar_int_mode
> (mode
);
1167 int isize
= GET_MODE_PRECISION (inner
);
1168 if (STORE_FLAG_VALUE
== 1)
1170 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
1171 gen_int_shift_amount (inner
,
1173 if (int_mode
== inner
)
1175 if (GET_MODE_PRECISION (int_mode
) > isize
)
1176 return simplify_gen_unary (SIGN_EXTEND
, int_mode
, temp
, inner
);
1177 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1179 else if (STORE_FLAG_VALUE
== -1)
1181 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
1182 gen_int_shift_amount (inner
,
1184 if (int_mode
== inner
)
1186 if (GET_MODE_PRECISION (int_mode
) > isize
)
1187 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, temp
, inner
);
1188 return simplify_gen_unary (TRUNCATE
, int_mode
, temp
, inner
);
1192 if (vec_series_p (op
, &base
, &step
))
1194 /* Only create a new series if we can simplify both parts. In other
1195 cases this isn't really a simplification, and it's not necessarily
1196 a win to replace a vector operation with a scalar operation. */
1197 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
1198 base
= simplify_unary_operation (NEG
, inner_mode
, base
, inner_mode
);
1201 step
= simplify_unary_operation (NEG
, inner_mode
,
1204 return gen_vec_series (mode
, base
, step
);
1210 /* Don't optimize (lshiftrt (mult ...)) as it would interfere
1211 with the umulXi3_highpart patterns. */
1212 if (GET_CODE (op
) == LSHIFTRT
1213 && GET_CODE (XEXP (op
, 0)) == MULT
)
1216 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
1218 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1220 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1224 /* We can't handle truncation to a partial integer mode here
1225 because we don't know the real bitsize of the partial
1230 if (GET_MODE (op
) != VOIDmode
)
1232 temp
= simplify_truncation (mode
, op
, GET_MODE (op
));
1237 /* If we know that the value is already truncated, we can
1238 replace the TRUNCATE with a SUBREG. */
1239 if (known_eq (GET_MODE_NUNITS (mode
), 1)
1240 && (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
))
1241 || truncated_to_mode (mode
, op
)))
1243 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1248 /* A truncate of a comparison can be replaced with a subreg if
1249 STORE_FLAG_VALUE permits. This is like the previous test,
1250 but it works even if the comparison is done in a mode larger
1251 than HOST_BITS_PER_WIDE_INT. */
1252 if (HWI_COMPUTABLE_MODE_P (mode
)
1253 && COMPARISON_P (op
)
1254 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
1255 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1257 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1262 /* A truncate of a memory is just loading the low part of the memory
1263 if we are not changing the meaning of the address. */
1264 if (GET_CODE (op
) == MEM
1265 && !VECTOR_MODE_P (mode
)
1266 && !MEM_VOLATILE_P (op
)
1267 && !mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
)))
1269 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1274 /* Check for useless truncation. */
1275 if (GET_MODE (op
) == mode
)
1279 case FLOAT_TRUNCATE
:
1280 /* Check for useless truncation. */
1281 if (GET_MODE (op
) == mode
)
1284 if (DECIMAL_FLOAT_MODE_P (mode
))
1287 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
1288 if (GET_CODE (op
) == FLOAT_EXTEND
1289 && GET_MODE (XEXP (op
, 0)) == mode
)
1290 return XEXP (op
, 0);
1292 /* (float_truncate:SF (float_truncate:DF foo:XF))
1293 = (float_truncate:SF foo:XF).
1294 This may eliminate double rounding, so it is unsafe.
1296 (float_truncate:SF (float_extend:XF foo:DF))
1297 = (float_truncate:SF foo:DF).
1299 (float_truncate:DF (float_extend:XF foo:SF))
1300 = (float_extend:DF foo:SF). */
1301 if ((GET_CODE (op
) == FLOAT_TRUNCATE
1302 && flag_unsafe_math_optimizations
)
1303 || GET_CODE (op
) == FLOAT_EXTEND
)
1304 return simplify_gen_unary (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)))
1305 > GET_MODE_UNIT_SIZE (mode
)
1306 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
1308 XEXP (op
, 0), mode
);
1310 /* (float_truncate (float x)) is (float x) */
1311 if ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1312 && (flag_unsafe_math_optimizations
1313 || exact_int_to_float_conversion_p (op
)))
1314 return simplify_gen_unary (GET_CODE (op
), mode
,
1316 GET_MODE (XEXP (op
, 0)));
1318 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
1319 (OP:SF foo:SF) if OP is NEG or ABS. */
1320 if ((GET_CODE (op
) == ABS
1321 || GET_CODE (op
) == NEG
)
1322 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
1323 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
1324 return simplify_gen_unary (GET_CODE (op
), mode
,
1325 XEXP (XEXP (op
, 0), 0), mode
);
1327 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
1328 is (float_truncate:SF x). */
1329 if (GET_CODE (op
) == SUBREG
1330 && subreg_lowpart_p (op
)
1331 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
1332 return SUBREG_REG (op
);
1336 /* Check for useless extension. */
1337 if (GET_MODE (op
) == mode
)
1340 if (DECIMAL_FLOAT_MODE_P (mode
))
1343 /* (float_extend (float_extend x)) is (float_extend x)
1345 (float_extend (float x)) is (float x) assuming that double
1346 rounding can't happen.
1348 if (GET_CODE (op
) == FLOAT_EXTEND
1349 || ((GET_CODE (op
) == FLOAT
|| GET_CODE (op
) == UNSIGNED_FLOAT
)
1350 && exact_int_to_float_conversion_p (op
)))
1351 return simplify_gen_unary (GET_CODE (op
), mode
,
1353 GET_MODE (XEXP (op
, 0)));
1358 /* (abs (neg <foo>)) -> (abs <foo>) */
1359 if (GET_CODE (op
) == NEG
)
1360 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
1361 GET_MODE (XEXP (op
, 0)));
1363 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
1365 if (GET_MODE (op
) == VOIDmode
)
1368 /* If operand is something known to be positive, ignore the ABS. */
1369 if (val_signbit_known_clear_p (GET_MODE (op
),
1370 nonzero_bits (op
, GET_MODE (op
))))
1373 /* Using nonzero_bits doesn't (currently) work for modes wider than
1374 HOST_WIDE_INT, so the following transformations help simplify
1375 ABS for TImode and wider. */
1376 switch (GET_CODE (op
))
1387 if (CONST_INT_P (XEXP (op
, 1))
1388 && INTVAL (XEXP (op
, 1)) > 0
1389 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1390 && INTVAL (XEXP (op
, 1)) < GET_MODE_PRECISION (int_mode
))
1398 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1399 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
1400 && (num_sign_bit_copies (op
, int_mode
)
1401 == GET_MODE_PRECISION (int_mode
)))
1402 return gen_rtx_NEG (int_mode
, op
);
1407 /* (ffs (*_extend <X>)) = (*_extend (ffs <X>)). */
1408 if (GET_CODE (op
) == SIGN_EXTEND
1409 || GET_CODE (op
) == ZERO_EXTEND
)
1411 temp
= simplify_gen_unary (FFS
, GET_MODE (XEXP (op
, 0)),
1412 XEXP (op
, 0), GET_MODE (XEXP (op
, 0)));
1413 return simplify_gen_unary (GET_CODE (op
), mode
, temp
,
1419 switch (GET_CODE (op
))
1423 /* (popcount (bswap <X>)) = (popcount <X>). */
1424 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1425 GET_MODE (XEXP (op
, 0)));
1428 /* (popcount (zero_extend <X>)) = (zero_extend (popcount <X>)). */
1429 temp
= simplify_gen_unary (POPCOUNT
, GET_MODE (XEXP (op
, 0)),
1430 XEXP (op
, 0), GET_MODE (XEXP (op
, 0)));
1431 return simplify_gen_unary (ZERO_EXTEND
, mode
, temp
,
1436 /* Rotations don't affect popcount. */
1437 if (!side_effects_p (XEXP (op
, 1)))
1438 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1439 GET_MODE (XEXP (op
, 0)));
1448 switch (GET_CODE (op
))
1453 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1454 GET_MODE (XEXP (op
, 0)));
1458 temp
= simplify_gen_unary (PARITY
, GET_MODE (XEXP (op
, 0)),
1459 XEXP (op
, 0), GET_MODE (XEXP (op
, 0)));
1460 return simplify_gen_unary (GET_CODE (op
), mode
, temp
,
1465 /* Rotations don't affect parity. */
1466 if (!side_effects_p (XEXP (op
, 1)))
1467 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1468 GET_MODE (XEXP (op
, 0)));
1472 /* (parity (parity x)) -> parity (x). */
1481 /* (bswap (bswap x)) -> x. */
1482 if (GET_CODE (op
) == BSWAP
)
1483 return XEXP (op
, 0);
1487 /* (bitreverse (bitreverse x)) -> x. */
1488 if (GET_CODE (op
) == BITREVERSE
)
1489 return XEXP (op
, 0);
1493 /* (float (sign_extend <X>)) = (float <X>). */
1494 if (GET_CODE (op
) == SIGN_EXTEND
)
1495 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
1496 GET_MODE (XEXP (op
, 0)));
1500 /* Check for useless extension. */
1501 if (GET_MODE (op
) == mode
)
1504 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1505 becomes just the MINUS if its mode is MODE. This allows
1506 folding switch statements on machines using casesi (such as
1508 if (GET_CODE (op
) == TRUNCATE
1509 && GET_MODE (XEXP (op
, 0)) == mode
1510 && GET_CODE (XEXP (op
, 0)) == MINUS
1511 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1512 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1513 return XEXP (op
, 0);
1515 /* Extending a widening multiplication should be canonicalized to
1516 a wider widening multiplication. */
1517 if (GET_CODE (op
) == MULT
)
1519 rtx lhs
= XEXP (op
, 0);
1520 rtx rhs
= XEXP (op
, 1);
1521 enum rtx_code lcode
= GET_CODE (lhs
);
1522 enum rtx_code rcode
= GET_CODE (rhs
);
1524 /* Widening multiplies usually extend both operands, but sometimes
1525 they use a shift to extract a portion of a register. */
1526 if ((lcode
== SIGN_EXTEND
1527 || (lcode
== ASHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1528 && (rcode
== SIGN_EXTEND
1529 || (rcode
== ASHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1531 machine_mode lmode
= GET_MODE (lhs
);
1532 machine_mode rmode
= GET_MODE (rhs
);
1535 if (lcode
== ASHIFTRT
)
1536 /* Number of bits not shifted off the end. */
1537 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1538 - INTVAL (XEXP (lhs
, 1)));
1539 else /* lcode == SIGN_EXTEND */
1540 /* Size of inner mode. */
1541 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1543 if (rcode
== ASHIFTRT
)
1544 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1545 - INTVAL (XEXP (rhs
, 1)));
1546 else /* rcode == SIGN_EXTEND */
1547 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1549 /* We can only widen multiplies if the result is mathematiclly
1550 equivalent. I.e. if overflow was impossible. */
1551 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1552 return simplify_gen_binary
1554 simplify_gen_unary (SIGN_EXTEND
, mode
, lhs
, lmode
),
1555 simplify_gen_unary (SIGN_EXTEND
, mode
, rhs
, rmode
));
1559 /* Check for a sign extension of a subreg of a promoted
1560 variable, where the promotion is sign-extended, and the
1561 target mode is the same as the variable's promotion. */
1562 if (GET_CODE (op
) == SUBREG
1563 && SUBREG_PROMOTED_VAR_P (op
)
1564 && SUBREG_PROMOTED_SIGNED_P (op
))
1566 rtx subreg
= SUBREG_REG (op
);
1567 machine_mode subreg_mode
= GET_MODE (subreg
);
1568 if (!paradoxical_subreg_p (mode
, subreg_mode
))
1570 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, subreg
);
1573 /* Preserve SUBREG_PROMOTED_VAR_P. */
1574 if (partial_subreg_p (temp
))
1576 SUBREG_PROMOTED_VAR_P (temp
) = 1;
1577 SUBREG_PROMOTED_SET (temp
, SRP_SIGNED
);
1583 /* Sign-extending a sign-extended subreg. */
1584 return simplify_gen_unary (SIGN_EXTEND
, mode
,
1585 subreg
, subreg_mode
);
1588 /* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
1589 (sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1590 if (GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
)
1592 gcc_assert (GET_MODE_UNIT_PRECISION (mode
)
1593 > GET_MODE_UNIT_PRECISION (GET_MODE (op
)));
1594 return simplify_gen_unary (GET_CODE (op
), mode
, XEXP (op
, 0),
1595 GET_MODE (XEXP (op
, 0)));
1598 /* (sign_extend:M (ashiftrt:N (ashift <X> (const_int I)) (const_int I)))
1599 is (sign_extend:M (subreg:O <X>)) if there is mode with
1600 GET_MODE_BITSIZE (N) - I bits.
1601 (sign_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1602 is similarly (zero_extend:M (subreg:O <X>)). */
1603 if ((GET_CODE (op
) == ASHIFTRT
|| GET_CODE (op
) == LSHIFTRT
)
1604 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1605 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1606 && CONST_INT_P (XEXP (op
, 1))
1607 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1608 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1609 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1611 scalar_int_mode tmode
;
1612 gcc_assert (GET_MODE_PRECISION (int_mode
)
1613 > GET_MODE_PRECISION (op_mode
));
1614 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1615 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1618 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1620 return simplify_gen_unary (GET_CODE (op
) == ASHIFTRT
1621 ? SIGN_EXTEND
: ZERO_EXTEND
,
1622 int_mode
, inner
, tmode
);
1626 /* (sign_extend:M (lshiftrt:N <X> (const_int I))) is better as
1627 (zero_extend:M (lshiftrt:N <X> (const_int I))) if I is not 0. */
1628 if (GET_CODE (op
) == LSHIFTRT
1629 && CONST_INT_P (XEXP (op
, 1))
1630 && XEXP (op
, 1) != const0_rtx
)
1631 return simplify_gen_unary (ZERO_EXTEND
, mode
, op
, GET_MODE (op
));
1633 /* (sign_extend:M (truncate:N (lshiftrt:O <X> (const_int I)))) where
1634 I is GET_MODE_PRECISION(O) - GET_MODE_PRECISION(N), simplifies to
1635 (ashiftrt:M <X> (const_int I)) if modes M and O are the same, and
1636 (truncate:M (ashiftrt:O <X> (const_int I))) if M is narrower than
1637 O, and (sign_extend:M (ashiftrt:O <X> (const_int I))) if M is
1639 if (GET_CODE (op
) == TRUNCATE
1640 && GET_CODE (XEXP (op
, 0)) == LSHIFTRT
1641 && CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
1643 scalar_int_mode m_mode
, n_mode
, o_mode
;
1644 rtx old_shift
= XEXP (op
, 0);
1645 if (is_a
<scalar_int_mode
> (mode
, &m_mode
)
1646 && is_a
<scalar_int_mode
> (GET_MODE (op
), &n_mode
)
1647 && is_a
<scalar_int_mode
> (GET_MODE (old_shift
), &o_mode
)
1648 && GET_MODE_PRECISION (o_mode
) - GET_MODE_PRECISION (n_mode
)
1649 == INTVAL (XEXP (old_shift
, 1)))
1651 rtx new_shift
= simplify_gen_binary (ASHIFTRT
,
1652 GET_MODE (old_shift
),
1653 XEXP (old_shift
, 0),
1654 XEXP (old_shift
, 1));
1655 if (GET_MODE_PRECISION (m_mode
) > GET_MODE_PRECISION (o_mode
))
1656 return simplify_gen_unary (SIGN_EXTEND
, mode
, new_shift
,
1657 GET_MODE (new_shift
));
1658 if (mode
!= GET_MODE (new_shift
))
1659 return simplify_gen_unary (TRUNCATE
, mode
, new_shift
,
1660 GET_MODE (new_shift
));
1665 /* We can canonicalize SIGN_EXTEND (op) as ZERO_EXTEND (op) when
1666 we know the sign bit of OP must be clear. */
1667 if (val_signbit_known_clear_p (GET_MODE (op
),
1668 nonzero_bits (op
, GET_MODE (op
))))
1669 return simplify_gen_unary (ZERO_EXTEND
, mode
, op
, GET_MODE (op
));
1671 /* (sign_extend:DI (subreg:SI (ctz:DI ...))) is (ctz:DI ...). */
1672 if (GET_CODE (op
) == SUBREG
1673 && subreg_lowpart_p (op
)
1674 && GET_MODE (SUBREG_REG (op
)) == mode
1675 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1676 && is_a
<scalar_int_mode
> (GET_MODE (op
), &op_mode
)
1677 && GET_MODE_PRECISION (int_mode
) <= HOST_BITS_PER_WIDE_INT
1678 && GET_MODE_PRECISION (op_mode
) < GET_MODE_PRECISION (int_mode
)
1679 && (nonzero_bits (SUBREG_REG (op
), mode
)
1680 & ~(GET_MODE_MASK (op_mode
) >> 1)) == 0)
1681 return SUBREG_REG (op
);
1683 #if defined(POINTERS_EXTEND_UNSIGNED)
1684 /* As we do not know which address space the pointer is referring to,
1685 we can do this only if the target does not support different pointer
1686 or address modes depending on the address space. */
1687 if (target_default_pointer_address_modes_p ()
1688 && ! POINTERS_EXTEND_UNSIGNED
1689 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1691 || (GET_CODE (op
) == SUBREG
1692 && REG_P (SUBREG_REG (op
))
1693 && REG_POINTER (SUBREG_REG (op
))
1694 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1695 && !targetm
.have_ptr_extend ())
1698 = convert_memory_address_addr_space_1 (Pmode
, op
,
1699 ADDR_SPACE_GENERIC
, false,
1708 /* Check for useless extension. */
1709 if (GET_MODE (op
) == mode
)
1712 /* Check for a zero extension of a subreg of a promoted
1713 variable, where the promotion is zero-extended, and the
1714 target mode is the same as the variable's promotion. */
1715 if (GET_CODE (op
) == SUBREG
1716 && SUBREG_PROMOTED_VAR_P (op
)
1717 && SUBREG_PROMOTED_UNSIGNED_P (op
))
1719 rtx subreg
= SUBREG_REG (op
);
1720 machine_mode subreg_mode
= GET_MODE (subreg
);
1721 if (!paradoxical_subreg_p (mode
, subreg_mode
))
1723 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, subreg
);
1726 /* Preserve SUBREG_PROMOTED_VAR_P. */
1727 if (partial_subreg_p (temp
))
1729 SUBREG_PROMOTED_VAR_P (temp
) = 1;
1730 SUBREG_PROMOTED_SET (temp
, SRP_UNSIGNED
);
1736 /* Zero-extending a zero-extended subreg. */
1737 return simplify_gen_unary (ZERO_EXTEND
, mode
,
1738 subreg
, subreg_mode
);
1741 /* Extending a widening multiplication should be canonicalized to
1742 a wider widening multiplication. */
1743 if (GET_CODE (op
) == MULT
)
1745 rtx lhs
= XEXP (op
, 0);
1746 rtx rhs
= XEXP (op
, 1);
1747 enum rtx_code lcode
= GET_CODE (lhs
);
1748 enum rtx_code rcode
= GET_CODE (rhs
);
1750 /* Widening multiplies usually extend both operands, but sometimes
1751 they use a shift to extract a portion of a register. */
1752 if ((lcode
== ZERO_EXTEND
1753 || (lcode
== LSHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1754 && (rcode
== ZERO_EXTEND
1755 || (rcode
== LSHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1757 machine_mode lmode
= GET_MODE (lhs
);
1758 machine_mode rmode
= GET_MODE (rhs
);
1761 if (lcode
== LSHIFTRT
)
1762 /* Number of bits not shifted off the end. */
1763 bits
= (GET_MODE_UNIT_PRECISION (lmode
)
1764 - INTVAL (XEXP (lhs
, 1)));
1765 else /* lcode == ZERO_EXTEND */
1766 /* Size of inner mode. */
1767 bits
= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1769 if (rcode
== LSHIFTRT
)
1770 bits
+= (GET_MODE_UNIT_PRECISION (rmode
)
1771 - INTVAL (XEXP (rhs
, 1)));
1772 else /* rcode == ZERO_EXTEND */
1773 bits
+= GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1775 /* We can only widen multiplies if the result is mathematiclly
1776 equivalent. I.e. if overflow was impossible. */
1777 if (bits
<= GET_MODE_UNIT_PRECISION (GET_MODE (op
)))
1778 return simplify_gen_binary
1780 simplify_gen_unary (ZERO_EXTEND
, mode
, lhs
, lmode
),
1781 simplify_gen_unary (ZERO_EXTEND
, mode
, rhs
, rmode
));
1785 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1786 if (GET_CODE (op
) == ZERO_EXTEND
)
1787 return simplify_gen_unary (ZERO_EXTEND
, mode
, XEXP (op
, 0),
1788 GET_MODE (XEXP (op
, 0)));
1790 /* (zero_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1791 is (zero_extend:M (subreg:O <X>)) if there is mode with
1792 GET_MODE_PRECISION (N) - I bits. */
1793 if (GET_CODE (op
) == LSHIFTRT
1794 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1795 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1796 && CONST_INT_P (XEXP (op
, 1))
1797 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1798 && (op_mode
= as_a
<scalar_int_mode
> (GET_MODE (op
)),
1799 GET_MODE_PRECISION (op_mode
) > INTVAL (XEXP (op
, 1))))
1801 scalar_int_mode tmode
;
1802 if (int_mode_for_size (GET_MODE_PRECISION (op_mode
)
1803 - INTVAL (XEXP (op
, 1)), 1).exists (&tmode
))
1806 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1808 return simplify_gen_unary (ZERO_EXTEND
, int_mode
,
1813 /* (zero_extend:M (subreg:N <X:O>)) is <X:O> (for M == O) or
1814 (zero_extend:M <X:O>), if X doesn't have any non-zero bits outside
1816 (zero_extend:SI (subreg:QI (and:SI (reg:SI) (const_int 63)) 0)) is
1817 (and:SI (reg:SI) (const_int 63)). */
1818 if (partial_subreg_p (op
)
1819 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1820 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op
)), &op0_mode
)
1821 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
1822 && GET_MODE_PRECISION (int_mode
) >= GET_MODE_PRECISION (op0_mode
)
1823 && subreg_lowpart_p (op
)
1824 && (nonzero_bits (SUBREG_REG (op
), op0_mode
)
1825 & ~GET_MODE_MASK (GET_MODE (op
))) == 0)
1827 if (GET_MODE_PRECISION (int_mode
) == GET_MODE_PRECISION (op0_mode
))
1828 return SUBREG_REG (op
);
1829 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, SUBREG_REG (op
),
1833 /* (zero_extend:DI (subreg:SI (ctz:DI ...))) is (ctz:DI ...). */
1834 if (GET_CODE (op
) == SUBREG
1835 && subreg_lowpart_p (op
)
1836 && GET_MODE (SUBREG_REG (op
)) == mode
1837 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1838 && is_a
<scalar_int_mode
> (GET_MODE (op
), &op_mode
)
1839 && GET_MODE_PRECISION (int_mode
) <= HOST_BITS_PER_WIDE_INT
1840 && GET_MODE_PRECISION (op_mode
) < GET_MODE_PRECISION (int_mode
)
1841 && (nonzero_bits (SUBREG_REG (op
), mode
)
1842 & ~GET_MODE_MASK (op_mode
)) == 0)
1843 return SUBREG_REG (op
);
1845 #if defined(POINTERS_EXTEND_UNSIGNED)
1846 /* As we do not know which address space the pointer is referring to,
1847 we can do this only if the target does not support different pointer
1848 or address modes depending on the address space. */
1849 if (target_default_pointer_address_modes_p ()
1850 && POINTERS_EXTEND_UNSIGNED
> 0
1851 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1853 || (GET_CODE (op
) == SUBREG
1854 && REG_P (SUBREG_REG (op
))
1855 && REG_POINTER (SUBREG_REG (op
))
1856 && GET_MODE (SUBREG_REG (op
)) == Pmode
))
1857 && !targetm
.have_ptr_extend ())
1860 = convert_memory_address_addr_space_1 (Pmode
, op
,
1861 ADDR_SPACE_GENERIC
, false,
1873 if (VECTOR_MODE_P (mode
)
1874 && vec_duplicate_p (op
, &elt
)
1875 && code
!= VEC_DUPLICATE
)
1877 if (code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
)
1878 /* Enforce a canonical order of VEC_DUPLICATE wrt other unary
1879 operations by promoting VEC_DUPLICATE to the root of the expression
1880 (as far as possible). */
1881 temp
= simplify_gen_unary (code
, GET_MODE_INNER (mode
),
1882 elt
, GET_MODE_INNER (GET_MODE (op
)));
1884 /* Try applying the operator to ELT and see if that simplifies.
1885 We can duplicate the result if so.
1887 The reason we traditionally haven't used simplify_gen_unary
1888 for these codes is that it didn't necessarily seem to be a
1889 win to convert things like:
1891 (neg:V (vec_duplicate:V (reg:S R)))
1895 (vec_duplicate:V (neg:S (reg:S R)))
1897 The first might be done entirely in vector registers while the
1898 second might need a move between register files.
1900 However, there also cases where promoting the vec_duplicate is
1901 more efficient, and there is definite value in having a canonical
1902 form when matching instruction patterns. We should consider
1903 extending the simplify_gen_unary code above to more cases. */
1904 temp
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1905 elt
, GET_MODE_INNER (GET_MODE (op
)));
1907 return gen_vec_duplicate (mode
, temp
);
1913 /* Try to compute the value of a unary operation CODE whose output mode is to
1914 be MODE with input operand OP whose mode was originally OP_MODE.
1915 Return zero if the value cannot be computed. */
1917 simplify_const_unary_operation (enum rtx_code code
, machine_mode mode
,
1918 rtx op
, machine_mode op_mode
)
1920 scalar_int_mode result_mode
;
1922 if (code
== VEC_DUPLICATE
)
1924 gcc_assert (VECTOR_MODE_P (mode
));
1925 if (GET_MODE (op
) != VOIDmode
)
1927 if (!VECTOR_MODE_P (GET_MODE (op
)))
1928 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
1930 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
1933 if (CONST_SCALAR_INT_P (op
) || CONST_DOUBLE_AS_FLOAT_P (op
))
1934 return gen_const_vec_duplicate (mode
, op
);
1935 if (GET_CODE (op
) == CONST_VECTOR
1936 && (CONST_VECTOR_DUPLICATE_P (op
)
1937 || CONST_VECTOR_NUNITS (op
).is_constant ()))
1939 unsigned int npatterns
= (CONST_VECTOR_DUPLICATE_P (op
)
1940 ? CONST_VECTOR_NPATTERNS (op
)
1941 : CONST_VECTOR_NUNITS (op
).to_constant ());
1942 gcc_assert (multiple_p (GET_MODE_NUNITS (mode
), npatterns
));
1943 rtx_vector_builder
builder (mode
, npatterns
, 1);
1944 for (unsigned i
= 0; i
< npatterns
; i
++)
1945 builder
.quick_push (CONST_VECTOR_ELT (op
, i
));
1946 return builder
.build ();
1950 if (VECTOR_MODE_P (mode
)
1951 && GET_CODE (op
) == CONST_VECTOR
1952 && known_eq (GET_MODE_NUNITS (mode
), CONST_VECTOR_NUNITS (op
)))
1954 gcc_assert (GET_MODE (op
) == op_mode
);
1956 rtx_vector_builder builder
;
1957 if (!builder
.new_unary_operation (mode
, op
, false))
1960 unsigned int count
= builder
.encoded_nelts ();
1961 for (unsigned int i
= 0; i
< count
; i
++)
1963 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1964 CONST_VECTOR_ELT (op
, i
),
1965 GET_MODE_INNER (op_mode
));
1966 if (!x
|| !valid_for_const_vector_p (mode
, x
))
1968 builder
.quick_push (x
);
1970 return builder
.build ();
1973 /* The order of these tests is critical so that, for example, we don't
1974 check the wrong mode (input vs. output) for a conversion operation,
1975 such as FIX. At some point, this should be simplified. */
1977 if (code
== FLOAT
&& CONST_SCALAR_INT_P (op
))
1981 if (op_mode
== VOIDmode
)
1983 /* CONST_INT have VOIDmode as the mode. We assume that all
1984 the bits of the constant are significant, though, this is
1985 a dangerous assumption as many times CONST_INTs are
1986 created and used with garbage in the bits outside of the
1987 precision of the implied mode of the const_int. */
1988 op_mode
= MAX_MODE_INT
;
1991 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), SIGNED
);
1993 /* Avoid the folding if flag_signaling_nans is on and
1994 operand is a signaling NaN. */
1995 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
1998 d
= real_value_truncate (mode
, d
);
2000 /* Avoid the folding if flag_rounding_math is on and the
2001 conversion is not exact. */
2002 if (HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2005 wide_int w
= real_to_integer (&d
, &fail
,
2007 (as_a
<scalar_int_mode
> (op_mode
)));
2008 if (fail
|| wi::ne_p (w
, wide_int (rtx_mode_t (op
, op_mode
))))
2012 return const_double_from_real_value (d
, mode
);
2014 else if (code
== UNSIGNED_FLOAT
&& CONST_SCALAR_INT_P (op
))
2018 if (op_mode
== VOIDmode
)
2020 /* CONST_INT have VOIDmode as the mode. We assume that all
2021 the bits of the constant are significant, though, this is
2022 a dangerous assumption as many times CONST_INTs are
2023 created and used with garbage in the bits outside of the
2024 precision of the implied mode of the const_int. */
2025 op_mode
= MAX_MODE_INT
;
2028 real_from_integer (&d
, mode
, rtx_mode_t (op
, op_mode
), UNSIGNED
);
2030 /* Avoid the folding if flag_signaling_nans is on and
2031 operand is a signaling NaN. */
2032 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
2035 d
= real_value_truncate (mode
, d
);
2037 /* Avoid the folding if flag_rounding_math is on and the
2038 conversion is not exact. */
2039 if (HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2042 wide_int w
= real_to_integer (&d
, &fail
,
2044 (as_a
<scalar_int_mode
> (op_mode
)));
2045 if (fail
|| wi::ne_p (w
, wide_int (rtx_mode_t (op
, op_mode
))))
2049 return const_double_from_real_value (d
, mode
);
2052 if (CONST_SCALAR_INT_P (op
) && is_a
<scalar_int_mode
> (mode
, &result_mode
))
2054 unsigned int width
= GET_MODE_PRECISION (result_mode
);
2055 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
2059 scalar_int_mode imode
= (op_mode
== VOIDmode
2061 : as_a
<scalar_int_mode
> (op_mode
));
2062 rtx_mode_t op0
= rtx_mode_t (op
, imode
);
2065 #if TARGET_SUPPORTS_WIDE_INT == 0
2066 /* This assert keeps the simplification from producing a result
2067 that cannot be represented in a CONST_DOUBLE but a lot of
2068 upstream callers expect that this function never fails to
2069 simplify something and so you if you added this to the test
2070 above the code would die later anyway. If this assert
2071 happens, you just need to make the port support wide int. */
2072 gcc_assert (width
<= HOST_BITS_PER_DOUBLE_INT
);
2078 result
= wi::bit_not (op0
);
2082 result
= wi::neg (op0
);
2086 result
= wi::abs (op0
);
2090 result
= wi::shwi (wi::ffs (op0
), result_mode
);
2094 if (wi::ne_p (op0
, 0))
2095 int_value
= wi::clz (op0
);
2096 else if (! CLZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
2098 result
= wi::shwi (int_value
, result_mode
);
2102 result
= wi::shwi (wi::clrsb (op0
), result_mode
);
2106 if (wi::ne_p (op0
, 0))
2107 int_value
= wi::ctz (op0
);
2108 else if (! CTZ_DEFINED_VALUE_AT_ZERO (imode
, int_value
))
2110 result
= wi::shwi (int_value
, result_mode
);
2114 result
= wi::shwi (wi::popcount (op0
), result_mode
);
2118 result
= wi::shwi (wi::parity (op0
), result_mode
);
2122 result
= wi::bswap (op0
);
2126 result
= wi::bitreverse (op0
);
2131 result
= wide_int::from (op0
, width
, UNSIGNED
);
2137 signop sgn
= code
== US_TRUNCATE
? UNSIGNED
: SIGNED
;
2139 = wide_int::from (wi::max_value (width
, sgn
),
2140 GET_MODE_PRECISION (imode
), sgn
);
2142 = wide_int::from (wi::min_value (width
, sgn
),
2143 GET_MODE_PRECISION (imode
), sgn
);
2144 result
= wi::min (wi::max (op0
, nmin
, sgn
), nmax
, sgn
);
2145 result
= wide_int::from (result
, width
, sgn
);
2149 result
= wide_int::from (op0
, width
, SIGNED
);
2153 if (wi::only_sign_bit_p (op0
))
2154 result
= wi::max_value (GET_MODE_PRECISION (imode
), SIGNED
);
2156 result
= wi::neg (op0
);
2160 if (wi::only_sign_bit_p (op0
))
2161 result
= wi::max_value (GET_MODE_PRECISION (imode
), SIGNED
);
2163 result
= wi::abs (op0
);
2171 return immed_wide_int_const (result
, result_mode
);
2174 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
2175 && SCALAR_FLOAT_MODE_P (mode
)
2176 && SCALAR_FLOAT_MODE_P (GET_MODE (op
)))
2178 REAL_VALUE_TYPE d
= *CONST_DOUBLE_REAL_VALUE (op
);
2184 d
= real_value_abs (&d
);
2187 d
= real_value_negate (&d
);
2189 case FLOAT_TRUNCATE
:
2190 /* Don't perform the operation if flag_signaling_nans is on
2191 and the operand is a signaling NaN. */
2192 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
2194 /* Or if flag_rounding_math is on and the truncation is not
2196 if (HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2197 && !exact_real_truncate (mode
, &d
))
2199 d
= real_value_truncate (mode
, d
);
2202 /* Don't perform the operation if flag_signaling_nans is on
2203 and the operand is a signaling NaN. */
2204 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
2206 /* All this does is change the mode, unless changing
2208 if (GET_MODE_CLASS (mode
) != GET_MODE_CLASS (GET_MODE (op
)))
2209 real_convert (&d
, mode
, &d
);
2212 /* Don't perform the operation if flag_signaling_nans is on
2213 and the operand is a signaling NaN. */
2214 if (HONOR_SNANS (mode
) && REAL_VALUE_ISSIGNALING_NAN (d
))
2216 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
2223 real_to_target (tmp
, &d
, GET_MODE (op
));
2224 for (i
= 0; i
< 4; i
++)
2226 real_from_target (&d
, tmp
, mode
);
2232 return const_double_from_real_value (d
, mode
);
2234 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
2235 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
2236 && is_int_mode (mode
, &result_mode
))
2238 unsigned int width
= GET_MODE_PRECISION (result_mode
);
2239 if (width
> MAX_BITSIZE_MODE_ANY_INT
)
2242 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
2243 operators are intentionally left unspecified (to ease implementation
2244 by target backends), for consistency, this routine implements the
2245 same semantics for constant folding as used by the middle-end. */
2247 /* This was formerly used only for non-IEEE float.
2248 eggert@twinsun.com says it is safe for IEEE also. */
2250 const REAL_VALUE_TYPE
*x
= CONST_DOUBLE_REAL_VALUE (op
);
2251 wide_int wmax
, wmin
;
2252 /* This is part of the abi to real_to_integer, but we check
2253 things before making this call. */
2259 if (REAL_VALUE_ISNAN (*x
))
2262 /* Test against the signed upper bound. */
2263 wmax
= wi::max_value (width
, SIGNED
);
2264 real_from_integer (&t
, VOIDmode
, wmax
, SIGNED
);
2265 if (real_less (&t
, x
))
2266 return immed_wide_int_const (wmax
, mode
);
2268 /* Test against the signed lower bound. */
2269 wmin
= wi::min_value (width
, SIGNED
);
2270 real_from_integer (&t
, VOIDmode
, wmin
, SIGNED
);
2271 if (real_less (x
, &t
))
2272 return immed_wide_int_const (wmin
, mode
);
2274 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2278 if (REAL_VALUE_ISNAN (*x
) || REAL_VALUE_NEGATIVE (*x
))
2281 /* Test against the unsigned upper bound. */
2282 wmax
= wi::max_value (width
, UNSIGNED
);
2283 real_from_integer (&t
, VOIDmode
, wmax
, UNSIGNED
);
2284 if (real_less (&t
, x
))
2285 return immed_wide_int_const (wmax
, mode
);
2287 return immed_wide_int_const (real_to_integer (x
, &fail
, width
),
2295 /* Handle polynomial integers. */
2296 else if (CONST_POLY_INT_P (op
))
2298 poly_wide_int result
;
2302 result
= -const_poly_int_value (op
);
2306 result
= ~const_poly_int_value (op
);
2312 return immed_wide_int_const (result
, mode
);
2318 /* Subroutine of simplify_binary_operation to simplify a binary operation
2319 CODE that can commute with byte swapping, with result mode MODE and
2320 operating on OP0 and OP1. CODE is currently one of AND, IOR or XOR.
2321 Return zero if no simplification or canonicalization is possible. */
2324 simplify_context::simplify_byte_swapping_operation (rtx_code code
,
2330 /* (op (bswap x) C1)) -> (bswap (op x C2)) with C2 swapped. */
2331 if (GET_CODE (op0
) == BSWAP
&& CONST_SCALAR_INT_P (op1
))
2333 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0),
2334 simplify_gen_unary (BSWAP
, mode
, op1
, mode
));
2335 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2338 /* (op (bswap x) (bswap y)) -> (bswap (op x y)). */
2339 if (GET_CODE (op0
) == BSWAP
&& GET_CODE (op1
) == BSWAP
)
2341 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2342 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
2348 /* Subroutine of simplify_binary_operation to simplify a commutative,
2349 associative binary operation CODE with result mode MODE, operating
2350 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
2351 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2352 canonicalization is possible. */
2355 simplify_context::simplify_associative_operation (rtx_code code
,
2361 /* Normally expressions simplified by simplify-rtx.cc are combined
2362 at most from a few machine instructions and therefore the
2363 expressions should be fairly small. During var-tracking
2364 we can see arbitrarily large expressions though and reassociating
2365 those can be quadratic, so punt after encountering max_assoc_count
2366 simplify_associative_operation calls during outermost simplify_*
2368 if (++assoc_count
>= max_assoc_count
)
2371 /* Linearize the operator to the left. */
2372 if (GET_CODE (op1
) == code
)
2374 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
2375 if (GET_CODE (op0
) == code
)
2377 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
2378 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
2381 /* "a op (b op c)" becomes "(b op c) op a". */
2382 if (! swap_commutative_operands_p (op1
, op0
))
2383 return simplify_gen_binary (code
, mode
, op1
, op0
);
2385 std::swap (op0
, op1
);
2388 if (GET_CODE (op0
) == code
)
2390 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
2391 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
2393 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
2394 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2397 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
2398 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
2400 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
2402 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
2403 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
2405 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
2411 /* Return a mask describing the COMPARISON. */
2413 comparison_to_mask (enum rtx_code comparison
)
2453 /* Return a comparison corresponding to the MASK. */
2454 static enum rtx_code
2455 mask_to_comparison (int mask
)
2495 /* Return true if CODE is valid for comparisons of mode MODE, false
2498 It is always safe to return false, even if the code was valid for the
2499 given mode as that will merely suppress optimizations. */
2502 comparison_code_valid_for_mode (enum rtx_code code
, enum machine_mode mode
)
2506 /* These are valid for integral, floating and vector modes. */
2513 return (INTEGRAL_MODE_P (mode
)
2514 || FLOAT_MODE_P (mode
)
2515 || VECTOR_MODE_P (mode
));
2517 /* These are valid for floating point modes. */
2526 return FLOAT_MODE_P (mode
);
2528 /* These are filtered out in simplify_logical_operation, but
2529 we check for them too as a matter of safety. They are valid
2530 for integral and vector modes. */
2535 return INTEGRAL_MODE_P (mode
) || VECTOR_MODE_P (mode
);
2542 /* Canonicalize RES, a scalar const0_rtx/const_true_rtx to the right
2543 false/true value of comparison with MODE where comparison operands
2547 relational_result (machine_mode mode
, machine_mode cmp_mode
, rtx res
)
2549 if (SCALAR_FLOAT_MODE_P (mode
))
2551 if (res
== const0_rtx
)
2552 return CONST0_RTX (mode
);
2553 #ifdef FLOAT_STORE_FLAG_VALUE
2554 REAL_VALUE_TYPE val
= FLOAT_STORE_FLAG_VALUE (mode
);
2555 return const_double_from_real_value (val
, mode
);
2560 if (VECTOR_MODE_P (mode
))
2562 if (res
== const0_rtx
)
2563 return CONST0_RTX (mode
);
2564 #ifdef VECTOR_STORE_FLAG_VALUE
2565 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
2566 if (val
== NULL_RTX
)
2568 if (val
== const1_rtx
)
2569 return CONST1_RTX (mode
);
2571 return gen_const_vec_duplicate (mode
, val
);
2576 /* For vector comparison with scalar int result, it is unknown
2577 if the target means here a comparison into an integral bitmask,
2578 or comparison where all comparisons true mean const_true_rtx
2579 whole result, or where any comparisons true mean const_true_rtx
2580 whole result. For const0_rtx all the cases are the same. */
2581 if (VECTOR_MODE_P (cmp_mode
)
2582 && SCALAR_INT_MODE_P (mode
)
2583 && res
== const_true_rtx
)
2589 /* Simplify a logical operation CODE with result mode MODE, operating on OP0
2590 and OP1, which should be both relational operations. Return 0 if no such
2591 simplification is possible. */
2593 simplify_context::simplify_logical_relational_operation (rtx_code code
,
2597 /* We only handle IOR of two relational operations. */
2601 if (!(COMPARISON_P (op0
) && COMPARISON_P (op1
)))
2604 if (!(rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2605 && rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 1))))
2608 enum rtx_code code0
= GET_CODE (op0
);
2609 enum rtx_code code1
= GET_CODE (op1
);
2611 /* We don't handle unsigned comparisons currently. */
2612 if (code0
== LTU
|| code0
== GTU
|| code0
== LEU
|| code0
== GEU
)
2614 if (code1
== LTU
|| code1
== GTU
|| code1
== LEU
|| code1
== GEU
)
2617 int mask0
= comparison_to_mask (code0
);
2618 int mask1
= comparison_to_mask (code1
);
2620 int mask
= mask0
| mask1
;
2623 return relational_result (mode
, GET_MODE (op0
), const_true_rtx
);
2625 code
= mask_to_comparison (mask
);
2627 /* Many comparison codes are only valid for certain mode classes. */
2628 if (!comparison_code_valid_for_mode (code
, mode
))
2631 op0
= XEXP (op1
, 0);
2632 op1
= XEXP (op1
, 1);
2634 return simplify_gen_relational (code
, mode
, VOIDmode
, op0
, op1
);
2637 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
2638 and OP1. Return 0 if no simplification is possible.
2640 Don't use this for relational operations such as EQ or LT.
2641 Use simplify_relational_operation instead. */
2643 simplify_context::simplify_binary_operation (rtx_code code
, machine_mode mode
,
2646 rtx trueop0
, trueop1
;
2649 /* Relational operations don't work here. We must know the mode
2650 of the operands in order to do the comparison correctly.
2651 Assuming a full word can give incorrect results.
2652 Consider comparing 128 with -128 in QImode. */
2653 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
2654 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
2656 /* Make sure the constant is second. */
2657 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
2658 && swap_commutative_operands_p (op0
, op1
))
2659 std::swap (op0
, op1
);
2661 trueop0
= avoid_constant_pool_reference (op0
);
2662 trueop1
= avoid_constant_pool_reference (op1
);
2664 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
2667 tem
= simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
2672 /* If the above steps did not result in a simplification and op0 or op1
2673 were constant pool references, use the referenced constants directly. */
2674 if (trueop0
!= op0
|| trueop1
!= op1
)
2675 return simplify_gen_binary (code
, mode
, trueop0
, trueop1
);
2680 /* Subroutine of simplify_binary_operation_1 that looks for cases in
2681 which OP0 and OP1 are both vector series or vector duplicates
2682 (which are really just series with a step of 0). If so, try to
2683 form a new series by applying CODE to the bases and to the steps.
2684 Return null if no simplification is possible.
2686 MODE is the mode of the operation and is known to be a vector
2690 simplify_context::simplify_binary_operation_series (rtx_code code
,
2695 if (vec_duplicate_p (op0
, &base0
))
2697 else if (!vec_series_p (op0
, &base0
, &step0
))
2701 if (vec_duplicate_p (op1
, &base1
))
2703 else if (!vec_series_p (op1
, &base1
, &step1
))
2706 /* Only create a new series if we can simplify both parts. In other
2707 cases this isn't really a simplification, and it's not necessarily
2708 a win to replace a vector operation with a scalar operation. */
2709 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
2710 rtx new_base
= simplify_binary_operation (code
, inner_mode
, base0
, base1
);
2714 rtx new_step
= simplify_binary_operation (code
, inner_mode
, step0
, step1
);
2718 return gen_vec_series (mode
, new_base
, new_step
);
2721 /* Subroutine of simplify_binary_operation_1. Un-distribute a binary
2722 operation CODE with result mode MODE, operating on OP0 and OP1.
2723 e.g. simplify (xor (and A C) (and (B C)) to (and (xor (A B) C).
2724 Returns NULL_RTX if no simplification is possible. */
2727 simplify_context::simplify_distributive_operation (rtx_code code
,
2731 enum rtx_code op
= GET_CODE (op0
);
2732 gcc_assert (GET_CODE (op1
) == op
);
2734 if (rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 1))
2735 && ! side_effects_p (XEXP (op0
, 1)))
2736 return simplify_gen_binary (op
, mode
,
2737 simplify_gen_binary (code
, mode
,
2742 if (GET_RTX_CLASS (op
) == RTX_COMM_ARITH
)
2744 if (rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2745 && ! side_effects_p (XEXP (op0
, 0)))
2746 return simplify_gen_binary (op
, mode
,
2747 simplify_gen_binary (code
, mode
,
2751 if (rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 1))
2752 && ! side_effects_p (XEXP (op0
, 0)))
2753 return simplify_gen_binary (op
, mode
,
2754 simplify_gen_binary (code
, mode
,
2758 if (rtx_equal_p (XEXP (op0
, 1), XEXP (op1
, 0))
2759 && ! side_effects_p (XEXP (op0
, 1)))
2760 return simplify_gen_binary (op
, mode
,
2761 simplify_gen_binary (code
, mode
,
2770 /* Return TRUE if a rotate in mode MODE with a constant count in OP1
2773 If the rotate should not be reversed, return FALSE.
2775 LEFT indicates if this is a rotate left or a rotate right. */
2778 reverse_rotate_by_imm_p (machine_mode mode
, unsigned int left
, rtx op1
)
2780 if (!CONST_INT_P (op1
))
2783 /* Some targets may only be able to rotate by a constant
2784 in one direction. So we need to query the optab interface
2785 to see what is possible. */
2786 optab binoptab
= left
? rotl_optab
: rotr_optab
;
2787 optab re_binoptab
= left
? rotr_optab
: rotl_optab
;
2788 enum insn_code icode
= optab_handler (binoptab
, mode
);
2789 enum insn_code re_icode
= optab_handler (re_binoptab
, mode
);
2791 /* If the target can not support the reversed optab, then there
2792 is nothing to do. */
2793 if (re_icode
== CODE_FOR_nothing
)
2796 /* If the target does not support the requested rotate-by-immediate,
2797 then we want to try reversing the rotate. We also want to try
2798 reversing to minimize the count. */
2799 if ((icode
== CODE_FOR_nothing
)
2800 || (!insn_operand_matches (icode
, 2, op1
))
2801 || (IN_RANGE (INTVAL (op1
),
2802 GET_MODE_UNIT_PRECISION (mode
) / 2 + left
,
2803 GET_MODE_UNIT_PRECISION (mode
) - 1)))
2804 return (insn_operand_matches (re_icode
, 2, op1
));
2808 /* Subroutine of simplify_binary_operation. Simplify a binary operation
2809 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
2810 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
2811 actual constants. */
2814 simplify_context::simplify_binary_operation_1 (rtx_code code
,
2817 rtx trueop0
, rtx trueop1
)
2819 rtx tem
, reversed
, opleft
, opright
, elt0
, elt1
;
2821 scalar_int_mode int_mode
, inner_mode
;
2824 /* Even if we can't compute a constant result,
2825 there are some cases worth simplifying. */
2830 /* Maybe simplify x + 0 to x. The two expressions are equivalent
2831 when x is NaN, infinite, or finite and nonzero. They aren't
2832 when x is -0 and the rounding mode is not towards -infinity,
2833 since (-0) + 0 is then 0. */
2834 if (!HONOR_SIGNED_ZEROS (mode
) && !HONOR_SNANS (mode
)
2835 && trueop1
== CONST0_RTX (mode
))
2838 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
2839 transformations are safe even for IEEE. */
2840 if (GET_CODE (op0
) == NEG
)
2841 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
2842 else if (GET_CODE (op1
) == NEG
)
2843 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
2845 /* (~a) + 1 -> -a */
2846 if (INTEGRAL_MODE_P (mode
)
2847 && GET_CODE (op0
) == NOT
2848 && trueop1
== const1_rtx
)
2849 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
2851 /* Handle both-operands-constant cases. We can only add
2852 CONST_INTs to constants since the sum of relocatable symbols
2853 can't be handled by most assemblers. Don't add CONST_INT
2854 to CONST_INT since overflow won't be computed properly if wider
2855 than HOST_BITS_PER_WIDE_INT. */
2857 if ((GET_CODE (op0
) == CONST
2858 || GET_CODE (op0
) == SYMBOL_REF
2859 || GET_CODE (op0
) == LABEL_REF
)
2860 && poly_int_rtx_p (op1
, &offset
))
2861 return plus_constant (mode
, op0
, offset
);
2862 else if ((GET_CODE (op1
) == CONST
2863 || GET_CODE (op1
) == SYMBOL_REF
2864 || GET_CODE (op1
) == LABEL_REF
)
2865 && poly_int_rtx_p (op0
, &offset
))
2866 return plus_constant (mode
, op1
, offset
);
2868 /* See if this is something like X * C - X or vice versa or
2869 if the multiplication is written as a shift. If so, we can
2870 distribute and make a new multiply, shift, or maybe just
2871 have X (if C is 2 in the example above). But don't make
2872 something more expensive than we had before. */
2874 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2876 rtx lhs
= op0
, rhs
= op1
;
2878 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
2879 wide_int coeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
2881 if (GET_CODE (lhs
) == NEG
)
2883 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2884 lhs
= XEXP (lhs
, 0);
2886 else if (GET_CODE (lhs
) == MULT
2887 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2889 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
2890 lhs
= XEXP (lhs
, 0);
2892 else if (GET_CODE (lhs
) == ASHIFT
2893 && CONST_INT_P (XEXP (lhs
, 1))
2894 && INTVAL (XEXP (lhs
, 1)) >= 0
2895 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2897 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2898 GET_MODE_PRECISION (int_mode
));
2899 lhs
= XEXP (lhs
, 0);
2902 if (GET_CODE (rhs
) == NEG
)
2904 coeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
2905 rhs
= XEXP (rhs
, 0);
2907 else if (GET_CODE (rhs
) == MULT
2908 && CONST_INT_P (XEXP (rhs
, 1)))
2910 coeff1
= rtx_mode_t (XEXP (rhs
, 1), int_mode
);
2911 rhs
= XEXP (rhs
, 0);
2913 else if (GET_CODE (rhs
) == ASHIFT
2914 && CONST_INT_P (XEXP (rhs
, 1))
2915 && INTVAL (XEXP (rhs
, 1)) >= 0
2916 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
2918 coeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2919 GET_MODE_PRECISION (int_mode
));
2920 rhs
= XEXP (rhs
, 0);
2923 if (rtx_equal_p (lhs
, rhs
))
2925 rtx orig
= gen_rtx_PLUS (int_mode
, op0
, op1
);
2927 bool speed
= optimize_function_for_speed_p (cfun
);
2929 coeff
= immed_wide_int_const (coeff0
+ coeff1
, int_mode
);
2931 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
2932 return (set_src_cost (tem
, int_mode
, speed
)
2933 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
2936 /* Optimize (X - 1) * Y + Y to X * Y. */
2939 if (GET_CODE (op0
) == MULT
)
2941 if (((GET_CODE (XEXP (op0
, 0)) == PLUS
2942 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
)
2943 || (GET_CODE (XEXP (op0
, 0)) == MINUS
2944 && XEXP (XEXP (op0
, 0), 1) == const1_rtx
))
2945 && rtx_equal_p (XEXP (op0
, 1), op1
))
2946 lhs
= XEXP (XEXP (op0
, 0), 0);
2947 else if (((GET_CODE (XEXP (op0
, 1)) == PLUS
2948 && XEXP (XEXP (op0
, 1), 1) == constm1_rtx
)
2949 || (GET_CODE (XEXP (op0
, 1)) == MINUS
2950 && XEXP (XEXP (op0
, 1), 1) == const1_rtx
))
2951 && rtx_equal_p (XEXP (op0
, 0), op1
))
2952 lhs
= XEXP (XEXP (op0
, 1), 0);
2954 else if (GET_CODE (op1
) == MULT
)
2956 if (((GET_CODE (XEXP (op1
, 0)) == PLUS
2957 && XEXP (XEXP (op1
, 0), 1) == constm1_rtx
)
2958 || (GET_CODE (XEXP (op1
, 0)) == MINUS
2959 && XEXP (XEXP (op1
, 0), 1) == const1_rtx
))
2960 && rtx_equal_p (XEXP (op1
, 1), op0
))
2961 rhs
= XEXP (XEXP (op1
, 0), 0);
2962 else if (((GET_CODE (XEXP (op1
, 1)) == PLUS
2963 && XEXP (XEXP (op1
, 1), 1) == constm1_rtx
)
2964 || (GET_CODE (XEXP (op1
, 1)) == MINUS
2965 && XEXP (XEXP (op1
, 1), 1) == const1_rtx
))
2966 && rtx_equal_p (XEXP (op1
, 0), op0
))
2967 rhs
= XEXP (XEXP (op1
, 1), 0);
2969 if (lhs
!= op0
|| rhs
!= op1
)
2970 return simplify_gen_binary (MULT
, int_mode
, lhs
, rhs
);
2973 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
2974 if (CONST_SCALAR_INT_P (op1
)
2975 && GET_CODE (op0
) == XOR
2976 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2977 && mode_signbit_p (mode
, op1
))
2978 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2979 simplify_gen_binary (XOR
, mode
, op1
,
2982 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
2983 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2984 && GET_CODE (op0
) == MULT
2985 && GET_CODE (XEXP (op0
, 0)) == NEG
)
2989 in1
= XEXP (XEXP (op0
, 0), 0);
2990 in2
= XEXP (op0
, 1);
2991 return simplify_gen_binary (MINUS
, mode
, op1
,
2992 simplify_gen_binary (MULT
, mode
,
2996 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
2997 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
2999 if (COMPARISON_P (op0
)
3000 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
3001 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
3002 && (reversed
= reversed_comparison (op0
, mode
)))
3004 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
3006 /* If one of the operands is a PLUS or a MINUS, see if we can
3007 simplify this by the associative law.
3008 Don't use the associative law for floating point.
3009 The inaccuracy makes it nonassociative,
3010 and subtle programs can break if operations are associated. */
3012 if (INTEGRAL_MODE_P (mode
)
3013 && (plus_minus_operand_p (op0
)
3014 || plus_minus_operand_p (op1
))
3015 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
3018 /* Reassociate floating point addition only when the user
3019 specifies associative math operations. */
3020 if (FLOAT_MODE_P (mode
)
3021 && flag_associative_math
)
3023 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3028 /* Handle vector series. */
3029 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
3031 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
3038 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
3039 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
3040 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
3041 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
3043 rtx xop00
= XEXP (op0
, 0);
3044 rtx xop10
= XEXP (op1
, 0);
3046 if (REG_P (xop00
) && REG_P (xop10
)
3047 && REGNO (xop00
) == REGNO (xop10
)
3048 && GET_MODE (xop00
) == mode
3049 && GET_MODE (xop10
) == mode
3050 && GET_MODE_CLASS (mode
) == MODE_CC
)
3056 /* We can't assume x-x is 0 even with non-IEEE floating point,
3057 but since it is zero except in very strange circumstances, we
3058 will treat it as zero with -ffinite-math-only. */
3059 if (rtx_equal_p (trueop0
, trueop1
)
3060 && ! side_effects_p (op0
)
3061 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
3062 return CONST0_RTX (mode
);
3064 /* Change subtraction from zero into negation. (0 - x) is the
3065 same as -x when x is NaN, infinite, or finite and nonzero.
3066 But if the mode has signed zeros, and does not round towards
3067 -infinity, then 0 - 0 is 0, not -0. */
3068 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
3069 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
3071 /* (-1 - a) is ~a, unless the expression contains symbolic
3072 constants, in which case not retaining additions and
3073 subtractions could cause invalid assembly to be produced. */
3074 if (trueop0
== CONSTM1_RTX (mode
)
3075 && !contains_symbolic_reference_p (op1
))
3076 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
3078 /* Subtracting 0 has no effect unless the mode has signalling NaNs,
3079 or has signed zeros and supports rounding towards -infinity.
3080 In such a case, 0 - 0 is -0. */
3081 if (!(HONOR_SIGNED_ZEROS (mode
)
3082 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
3083 && !HONOR_SNANS (mode
)
3084 && trueop1
== CONST0_RTX (mode
))
3087 /* See if this is something like X * C - X or vice versa or
3088 if the multiplication is written as a shift. If so, we can
3089 distribute and make a new multiply, shift, or maybe just
3090 have X (if C is 2 in the example above). But don't make
3091 something more expensive than we had before. */
3093 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
3095 rtx lhs
= op0
, rhs
= op1
;
3097 wide_int coeff0
= wi::one (GET_MODE_PRECISION (int_mode
));
3098 wide_int negcoeff1
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
3100 if (GET_CODE (lhs
) == NEG
)
3102 coeff0
= wi::minus_one (GET_MODE_PRECISION (int_mode
));
3103 lhs
= XEXP (lhs
, 0);
3105 else if (GET_CODE (lhs
) == MULT
3106 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
3108 coeff0
= rtx_mode_t (XEXP (lhs
, 1), int_mode
);
3109 lhs
= XEXP (lhs
, 0);
3111 else if (GET_CODE (lhs
) == ASHIFT
3112 && CONST_INT_P (XEXP (lhs
, 1))
3113 && INTVAL (XEXP (lhs
, 1)) >= 0
3114 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (int_mode
))
3116 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
3117 GET_MODE_PRECISION (int_mode
));
3118 lhs
= XEXP (lhs
, 0);
3121 if (GET_CODE (rhs
) == NEG
)
3123 negcoeff1
= wi::one (GET_MODE_PRECISION (int_mode
));
3124 rhs
= XEXP (rhs
, 0);
3126 else if (GET_CODE (rhs
) == MULT
3127 && CONST_INT_P (XEXP (rhs
, 1)))
3129 negcoeff1
= wi::neg (rtx_mode_t (XEXP (rhs
, 1), int_mode
));
3130 rhs
= XEXP (rhs
, 0);
3132 else if (GET_CODE (rhs
) == ASHIFT
3133 && CONST_INT_P (XEXP (rhs
, 1))
3134 && INTVAL (XEXP (rhs
, 1)) >= 0
3135 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (int_mode
))
3137 negcoeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
3138 GET_MODE_PRECISION (int_mode
));
3139 negcoeff1
= -negcoeff1
;
3140 rhs
= XEXP (rhs
, 0);
3143 if (rtx_equal_p (lhs
, rhs
))
3145 rtx orig
= gen_rtx_MINUS (int_mode
, op0
, op1
);
3147 bool speed
= optimize_function_for_speed_p (cfun
);
3149 coeff
= immed_wide_int_const (coeff0
+ negcoeff1
, int_mode
);
3151 tem
= simplify_gen_binary (MULT
, int_mode
, lhs
, coeff
);
3152 return (set_src_cost (tem
, int_mode
, speed
)
3153 <= set_src_cost (orig
, int_mode
, speed
) ? tem
: 0);
3156 /* Optimize (X + 1) * Y - Y to X * Y. */
3158 if (GET_CODE (op0
) == MULT
)
3160 if (((GET_CODE (XEXP (op0
, 0)) == PLUS
3161 && XEXP (XEXP (op0
, 0), 1) == const1_rtx
)
3162 || (GET_CODE (XEXP (op0
, 0)) == MINUS
3163 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
))
3164 && rtx_equal_p (XEXP (op0
, 1), op1
))
3165 lhs
= XEXP (XEXP (op0
, 0), 0);
3166 else if (((GET_CODE (XEXP (op0
, 1)) == PLUS
3167 && XEXP (XEXP (op0
, 1), 1) == const1_rtx
)
3168 || (GET_CODE (XEXP (op0
, 1)) == MINUS
3169 && XEXP (XEXP (op0
, 1), 1) == constm1_rtx
))
3170 && rtx_equal_p (XEXP (op0
, 0), op1
))
3171 lhs
= XEXP (XEXP (op0
, 1), 0);
3174 return simplify_gen_binary (MULT
, int_mode
, lhs
, op1
);
3177 /* (a - (-b)) -> (a + b). True even for IEEE. */
3178 if (GET_CODE (op1
) == NEG
)
3179 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
3181 /* (-x - c) may be simplified as (-c - x). */
3182 if (GET_CODE (op0
) == NEG
3183 && (CONST_SCALAR_INT_P (op1
) || CONST_DOUBLE_AS_FLOAT_P (op1
)))
3185 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
3187 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
3190 if ((GET_CODE (op0
) == CONST
3191 || GET_CODE (op0
) == SYMBOL_REF
3192 || GET_CODE (op0
) == LABEL_REF
)
3193 && poly_int_rtx_p (op1
, &offset
))
3194 return plus_constant (mode
, op0
, trunc_int_for_mode (-offset
, mode
));
3196 /* Don't let a relocatable value get a negative coeff. */
3197 if (poly_int_rtx_p (op1
) && GET_MODE (op0
) != VOIDmode
)
3198 return simplify_gen_binary (PLUS
, mode
,
3200 neg_poly_int_rtx (mode
, op1
));
3202 /* (x - (x & y)) -> (x & ~y) */
3203 if (INTEGRAL_MODE_P (mode
) && GET_CODE (op1
) == AND
)
3205 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
3207 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
3208 GET_MODE (XEXP (op1
, 1)));
3209 return simplify_gen_binary (AND
, mode
, op0
, tem
);
3211 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
3213 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
3214 GET_MODE (XEXP (op1
, 0)));
3215 return simplify_gen_binary (AND
, mode
, op0
, tem
);
3219 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3220 by reversing the comparison code if valid. */
3221 if (STORE_FLAG_VALUE
== 1
3222 && trueop0
== const1_rtx
3223 && COMPARISON_P (op1
)
3224 && (reversed
= reversed_comparison (op1
, mode
)))
3227 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
3228 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
3229 && GET_CODE (op1
) == MULT
3230 && GET_CODE (XEXP (op1
, 0)) == NEG
)
3234 in1
= XEXP (XEXP (op1
, 0), 0);
3235 in2
= XEXP (op1
, 1);
3236 return simplify_gen_binary (PLUS
, mode
,
3237 simplify_gen_binary (MULT
, mode
,
3242 /* Canonicalize (minus (neg A) (mult B C)) to
3243 (minus (mult (neg B) C) A). */
3244 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
3245 && GET_CODE (op1
) == MULT
3246 && GET_CODE (op0
) == NEG
)
3250 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
3251 in2
= XEXP (op1
, 1);
3252 return simplify_gen_binary (MINUS
, mode
,
3253 simplify_gen_binary (MULT
, mode
,
3258 /* If one of the operands is a PLUS or a MINUS, see if we can
3259 simplify this by the associative law. This will, for example,
3260 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
3261 Don't use the associative law for floating point.
3262 The inaccuracy makes it nonassociative,
3263 and subtle programs can break if operations are associated. */
3265 if (INTEGRAL_MODE_P (mode
)
3266 && (plus_minus_operand_p (op0
)
3267 || plus_minus_operand_p (op1
))
3268 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
3271 /* Handle vector series. */
3272 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
3274 tem
= simplify_binary_operation_series (code
, mode
, op0
, op1
);
3281 if (trueop1
== constm1_rtx
)
3282 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
3284 if (GET_CODE (op0
) == NEG
)
3286 rtx temp
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
3287 /* If op1 is a MULT as well and simplify_unary_operation
3288 just moved the NEG to the second operand, simplify_gen_binary
3289 below could through simplify_associative_operation move
3290 the NEG around again and recurse endlessly. */
3292 && GET_CODE (op1
) == MULT
3293 && GET_CODE (temp
) == MULT
3294 && XEXP (op1
, 0) == XEXP (temp
, 0)
3295 && GET_CODE (XEXP (temp
, 1)) == NEG
3296 && XEXP (op1
, 1) == XEXP (XEXP (temp
, 1), 0))
3299 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), temp
);
3301 if (GET_CODE (op1
) == NEG
)
3303 rtx temp
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3304 /* If op0 is a MULT as well and simplify_unary_operation
3305 just moved the NEG to the second operand, simplify_gen_binary
3306 below could through simplify_associative_operation move
3307 the NEG around again and recurse endlessly. */
3309 && GET_CODE (op0
) == MULT
3310 && GET_CODE (temp
) == MULT
3311 && XEXP (op0
, 0) == XEXP (temp
, 0)
3312 && GET_CODE (XEXP (temp
, 1)) == NEG
3313 && XEXP (op0
, 1) == XEXP (XEXP (temp
, 1), 0))
3316 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op1
, 0));
3319 /* Maybe simplify x * 0 to 0. The reduction is not valid if
3320 x is NaN, since x * 0 is then also NaN. Nor is it valid
3321 when the mode has signed zeros, since multiplying a negative
3322 number by 0 will give -0, not 0. */
3323 if (!HONOR_NANS (mode
)
3324 && !HONOR_SIGNED_ZEROS (mode
)
3325 && trueop1
== CONST0_RTX (mode
)
3326 && ! side_effects_p (op0
))
3329 /* In IEEE floating point, x*1 is not equivalent to x for
3331 if (!HONOR_SNANS (mode
)
3332 && trueop1
== CONST1_RTX (mode
))
3335 /* Convert multiply by constant power of two into shift. */
3336 if (mem_depth
== 0 && CONST_SCALAR_INT_P (trueop1
))
3338 val
= wi::exact_log2 (rtx_mode_t (trueop1
, mode
));
3340 return simplify_gen_binary (ASHIFT
, mode
, op0
,
3341 gen_int_shift_amount (mode
, val
));
3344 /* x*2 is x+x and x*(-1) is -x */
3345 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
3346 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
3347 && !DECIMAL_FLOAT_MODE_P (GET_MODE (trueop1
))
3348 && GET_MODE (op0
) == mode
)
3350 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
3352 if (real_equal (d1
, &dconst2
))
3353 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
3355 if (!HONOR_SNANS (mode
)
3356 && real_equal (d1
, &dconstm1
))
3357 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
3360 /* Optimize -x * -x as x * x. */
3361 if (FLOAT_MODE_P (mode
)
3362 && GET_CODE (op0
) == NEG
3363 && GET_CODE (op1
) == NEG
3364 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
3365 && !side_effects_p (XEXP (op0
, 0)))
3366 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
3368 /* Likewise, optimize abs(x) * abs(x) as x * x. */
3369 if (SCALAR_FLOAT_MODE_P (mode
)
3370 && GET_CODE (op0
) == ABS
3371 && GET_CODE (op1
) == ABS
3372 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
3373 && !side_effects_p (XEXP (op0
, 0)))
3374 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
3376 /* Reassociate multiplication, but for floating point MULTs
3377 only when the user specifies unsafe math optimizations. */
3378 if (! FLOAT_MODE_P (mode
)
3379 || flag_unsafe_math_optimizations
)
3381 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3388 if (trueop1
== CONST0_RTX (mode
))
3390 if (INTEGRAL_MODE_P (mode
)
3391 && trueop1
== CONSTM1_RTX (mode
)
3392 && !side_effects_p (op0
))
3394 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3396 /* A | (~A) -> -1 */
3397 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
3398 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
3399 && ! side_effects_p (op0
)
3400 && GET_MODE_CLASS (mode
) != MODE_CC
)
3401 return CONSTM1_RTX (mode
);
3403 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
3404 if (CONST_INT_P (op1
)
3405 && HWI_COMPUTABLE_MODE_P (mode
)
3406 && (nonzero_bits (op0
, mode
) & ~UINTVAL (op1
)) == 0
3407 && !side_effects_p (op0
))
3410 /* Canonicalize (X & C1) | C2. */
3411 if (GET_CODE (op0
) == AND
3412 && CONST_INT_P (trueop1
)
3413 && CONST_INT_P (XEXP (op0
, 1)))
3415 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
3416 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
3417 HOST_WIDE_INT c2
= INTVAL (trueop1
);
3419 /* If (C1&C2) == C1, then (X&C1)|C2 becomes C2. */
3421 && !side_effects_p (XEXP (op0
, 0)))
3424 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
3425 if (((c1
|c2
) & mask
) == mask
)
3426 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
3429 /* Convert (A & B) | A to A. */
3430 if (GET_CODE (op0
) == AND
3431 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3432 || rtx_equal_p (XEXP (op0
, 1), op1
))
3433 && ! side_effects_p (XEXP (op0
, 0))
3434 && ! side_effects_p (XEXP (op0
, 1)))
3437 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3438 mode size to (rotate A CX). */
3440 if (GET_CODE (op1
) == ASHIFT
3441 || GET_CODE (op1
) == SUBREG
)
3452 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
3453 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
3454 && CONST_INT_P (XEXP (opleft
, 1))
3455 && CONST_INT_P (XEXP (opright
, 1))
3456 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
3457 == GET_MODE_UNIT_PRECISION (mode
)))
3458 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
3460 /* Same, but for ashift that has been "simplified" to a wider mode
3461 by simplify_shift_const. */
3463 if (GET_CODE (opleft
) == SUBREG
3464 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
3465 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (opleft
)),
3467 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
3468 && GET_CODE (opright
) == LSHIFTRT
3469 && GET_CODE (XEXP (opright
, 0)) == SUBREG
3470 && known_eq (SUBREG_BYTE (opleft
), SUBREG_BYTE (XEXP (opright
, 0)))
3471 && GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (inner_mode
)
3472 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
3473 SUBREG_REG (XEXP (opright
, 0)))
3474 && CONST_INT_P (XEXP (SUBREG_REG (opleft
), 1))
3475 && CONST_INT_P (XEXP (opright
, 1))
3476 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1))
3477 + INTVAL (XEXP (opright
, 1))
3478 == GET_MODE_PRECISION (int_mode
)))
3479 return gen_rtx_ROTATE (int_mode
, XEXP (opright
, 0),
3480 XEXP (SUBREG_REG (opleft
), 1));
3482 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
3483 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
3484 the PLUS does not affect any of the bits in OP1: then we can do
3485 the IOR as a PLUS and we can associate. This is valid if OP1
3486 can be safely shifted left C bits. */
3487 if (CONST_INT_P (trueop1
) && GET_CODE (op0
) == ASHIFTRT
3488 && GET_CODE (XEXP (op0
, 0)) == PLUS
3489 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
3490 && CONST_INT_P (XEXP (op0
, 1))
3491 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
3493 int count
= INTVAL (XEXP (op0
, 1));
3494 HOST_WIDE_INT mask
= UINTVAL (trueop1
) << count
;
3496 if (mask
>> count
== INTVAL (trueop1
)
3497 && trunc_int_for_mode (mask
, mode
) == mask
3498 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
3499 return simplify_gen_binary (ASHIFTRT
, mode
,
3500 plus_constant (mode
, XEXP (op0
, 0),
3505 /* The following happens with bitfield merging.
3506 (X & C) | ((X | Y) & ~C) -> X | (Y & ~C) */
3507 if (GET_CODE (op0
) == AND
3508 && GET_CODE (op1
) == AND
3509 && CONST_INT_P (XEXP (op0
, 1))
3510 && CONST_INT_P (XEXP (op1
, 1))
3511 && (INTVAL (XEXP (op0
, 1))
3512 == ~INTVAL (XEXP (op1
, 1))))
3514 /* The IOR may be on both sides. */
3515 rtx top0
= NULL_RTX
, top1
= NULL_RTX
;
3516 if (GET_CODE (XEXP (op1
, 0)) == IOR
)
3517 top0
= op0
, top1
= op1
;
3518 else if (GET_CODE (XEXP (op0
, 0)) == IOR
)
3519 top0
= op1
, top1
= op0
;
3522 /* X may be on either side of the inner IOR. */
3524 if (rtx_equal_p (XEXP (top0
, 0),
3525 XEXP (XEXP (top1
, 0), 0)))
3526 tem
= XEXP (XEXP (top1
, 0), 1);
3527 else if (rtx_equal_p (XEXP (top0
, 0),
3528 XEXP (XEXP (top1
, 0), 1)))
3529 tem
= XEXP (XEXP (top1
, 0), 0);
3531 return simplify_gen_binary (IOR
, mode
, XEXP (top0
, 0),
3533 (AND
, mode
, tem
, XEXP (top1
, 1)));
3537 /* Convert (ior (and A C) (and B C)) into (and (ior A B) C). */
3538 if (GET_CODE (op0
) == GET_CODE (op1
)
3539 && (GET_CODE (op0
) == AND
3540 || GET_CODE (op0
) == IOR
3541 || GET_CODE (op0
) == LSHIFTRT
3542 || GET_CODE (op0
) == ASHIFTRT
3543 || GET_CODE (op0
) == ASHIFT
3544 || GET_CODE (op0
) == ROTATE
3545 || GET_CODE (op0
) == ROTATERT
))
3547 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
3552 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3556 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3560 tem
= simplify_logical_relational_operation (code
, mode
, op0
, op1
);
3566 if (trueop1
== CONST0_RTX (mode
))
3568 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3569 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
3570 if (rtx_equal_p (trueop0
, trueop1
)
3571 && ! side_effects_p (op0
)
3572 && GET_MODE_CLASS (mode
) != MODE_CC
)
3573 return CONST0_RTX (mode
);
3575 /* Canonicalize XOR of the most significant bit to PLUS. */
3576 if (CONST_SCALAR_INT_P (op1
)
3577 && mode_signbit_p (mode
, op1
))
3578 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
3579 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
3580 if (CONST_SCALAR_INT_P (op1
)
3581 && GET_CODE (op0
) == PLUS
3582 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
3583 && mode_signbit_p (mode
, XEXP (op0
, 1)))
3584 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
3585 simplify_gen_binary (XOR
, mode
, op1
,
3588 /* If we are XORing two things that have no bits in common,
3589 convert them into an IOR. This helps to detect rotation encoded
3590 using those methods and possibly other simplifications. */
3592 if (HWI_COMPUTABLE_MODE_P (mode
)
3593 && (nonzero_bits (op0
, mode
)
3594 & nonzero_bits (op1
, mode
)) == 0)
3595 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
3597 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3598 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3601 int num_negated
= 0;
3603 if (GET_CODE (op0
) == NOT
)
3604 num_negated
++, op0
= XEXP (op0
, 0);
3605 if (GET_CODE (op1
) == NOT
)
3606 num_negated
++, op1
= XEXP (op1
, 0);
3608 if (num_negated
== 2)
3609 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
3610 else if (num_negated
== 1)
3611 return simplify_gen_unary (NOT
, mode
,
3612 simplify_gen_binary (XOR
, mode
, op0
, op1
),
3616 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3617 correspond to a machine insn or result in further simplifications
3618 if B is a constant. */
3620 if (GET_CODE (op0
) == AND
3621 && rtx_equal_p (XEXP (op0
, 1), op1
)
3622 && ! side_effects_p (op1
))
3623 return simplify_gen_binary (AND
, mode
,
3624 simplify_gen_unary (NOT
, mode
,
3625 XEXP (op0
, 0), mode
),
3628 else if (GET_CODE (op0
) == AND
3629 && rtx_equal_p (XEXP (op0
, 0), op1
)
3630 && ! side_effects_p (op1
))
3631 return simplify_gen_binary (AND
, mode
,
3632 simplify_gen_unary (NOT
, mode
,
3633 XEXP (op0
, 1), mode
),
3636 /* Given (xor (ior (xor A B) C) D), where B, C and D are
3637 constants, simplify to (xor (ior A C) (B&~C)^D), canceling
3638 out bits inverted twice and not set by C. Similarly, given
3639 (xor (and (xor A B) C) D), simplify without inverting C in
3640 the xor operand: (xor (and A C) (B&C)^D).
3642 else if ((GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == AND
)
3643 && GET_CODE (XEXP (op0
, 0)) == XOR
3644 && CONST_INT_P (op1
)
3645 && CONST_INT_P (XEXP (op0
, 1))
3646 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1)))
3648 enum rtx_code op
= GET_CODE (op0
);
3649 rtx a
= XEXP (XEXP (op0
, 0), 0);
3650 rtx b
= XEXP (XEXP (op0
, 0), 1);
3651 rtx c
= XEXP (op0
, 1);
3653 HOST_WIDE_INT bval
= INTVAL (b
);
3654 HOST_WIDE_INT cval
= INTVAL (c
);
3655 HOST_WIDE_INT dval
= INTVAL (d
);
3656 HOST_WIDE_INT xcval
;
3663 return simplify_gen_binary (XOR
, mode
,
3664 simplify_gen_binary (op
, mode
, a
, c
),
3665 gen_int_mode ((bval
& xcval
) ^ dval
,
3669 /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
3670 we can transform like this:
3671 (A&B)^C == ~(A&B)&C | ~C&(A&B)
3672 == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
3673 == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
3674 Attempt a few simplifications when B and C are both constants. */
3675 if (GET_CODE (op0
) == AND
3676 && CONST_INT_P (op1
)
3677 && CONST_INT_P (XEXP (op0
, 1)))
3679 rtx a
= XEXP (op0
, 0);
3680 rtx b
= XEXP (op0
, 1);
3682 HOST_WIDE_INT bval
= INTVAL (b
);
3683 HOST_WIDE_INT cval
= INTVAL (c
);
3685 /* Instead of computing ~A&C, we compute its negated value,
3686 ~(A|~C). If it yields -1, ~A&C is zero, so we can
3687 optimize for sure. If it does not simplify, we still try
3688 to compute ~A&C below, but since that always allocates
3689 RTL, we don't try that before committing to returning a
3690 simplified expression. */
3691 rtx n_na_c
= simplify_binary_operation (IOR
, mode
, a
,
3694 if ((~cval
& bval
) == 0)
3696 rtx na_c
= NULL_RTX
;
3698 na_c
= simplify_gen_unary (NOT
, mode
, n_na_c
, mode
);
3701 /* If ~A does not simplify, don't bother: we don't
3702 want to simplify 2 operations into 3, and if na_c
3703 were to simplify with na, n_na_c would have
3704 simplified as well. */
3705 rtx na
= simplify_unary_operation (NOT
, mode
, a
, mode
);
3707 na_c
= simplify_gen_binary (AND
, mode
, na
, c
);
3710 /* Try to simplify ~A&C | ~B&C. */
3711 if (na_c
!= NULL_RTX
)
3712 return simplify_gen_binary (IOR
, mode
, na_c
,
3713 gen_int_mode (~bval
& cval
, mode
));
3717 /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
3718 if (n_na_c
== CONSTM1_RTX (mode
))
3720 rtx a_nc_b
= simplify_gen_binary (AND
, mode
, a
,
3721 gen_int_mode (~cval
& bval
,
3723 return simplify_gen_binary (IOR
, mode
, a_nc_b
,
3724 gen_int_mode (~bval
& cval
,
3730 /* If we have (xor (and (xor A B) C) A) with C a constant we can instead
3731 do (ior (and A ~C) (and B C)) which is a machine instruction on some
3732 machines, and also has shorter instruction path length. */
3733 if (GET_CODE (op0
) == AND
3734 && GET_CODE (XEXP (op0
, 0)) == XOR
3735 && CONST_INT_P (XEXP (op0
, 1))
3736 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), trueop1
))
3739 rtx b
= XEXP (XEXP (op0
, 0), 1);
3740 rtx c
= XEXP (op0
, 1);
3741 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3742 rtx a_nc
= simplify_gen_binary (AND
, mode
, a
, nc
);
3743 rtx bc
= simplify_gen_binary (AND
, mode
, b
, c
);
3744 return simplify_gen_binary (IOR
, mode
, a_nc
, bc
);
3746 /* Similarly, (xor (and (xor A B) C) B) as (ior (and A C) (and B ~C)) */
3747 else if (GET_CODE (op0
) == AND
3748 && GET_CODE (XEXP (op0
, 0)) == XOR
3749 && CONST_INT_P (XEXP (op0
, 1))
3750 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), trueop1
))
3752 rtx a
= XEXP (XEXP (op0
, 0), 0);
3754 rtx c
= XEXP (op0
, 1);
3755 rtx nc
= simplify_gen_unary (NOT
, mode
, c
, mode
);
3756 rtx b_nc
= simplify_gen_binary (AND
, mode
, b
, nc
);
3757 rtx ac
= simplify_gen_binary (AND
, mode
, a
, c
);
3758 return simplify_gen_binary (IOR
, mode
, ac
, b_nc
);
3761 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3762 comparison if STORE_FLAG_VALUE is 1. */
3763 if (STORE_FLAG_VALUE
== 1
3764 && trueop1
== const1_rtx
3765 && COMPARISON_P (op0
)
3766 && (reversed
= reversed_comparison (op0
, mode
)))
3769 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
3770 is (lt foo (const_int 0)), so we can perform the above
3771 simplification if STORE_FLAG_VALUE is 1. */
3773 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3774 && STORE_FLAG_VALUE
== 1
3775 && trueop1
== const1_rtx
3776 && GET_CODE (op0
) == LSHIFTRT
3777 && CONST_INT_P (XEXP (op0
, 1))
3778 && INTVAL (XEXP (op0
, 1)) == GET_MODE_PRECISION (int_mode
) - 1)
3779 return gen_rtx_GE (int_mode
, XEXP (op0
, 0), const0_rtx
);
3781 /* (xor (comparison foo bar) (const_int sign-bit))
3782 when STORE_FLAG_VALUE is the sign bit. */
3783 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
3784 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
3785 && trueop1
== const_true_rtx
3786 && COMPARISON_P (op0
)
3787 && (reversed
= reversed_comparison (op0
, int_mode
)))
3790 /* Convert (xor (and A C) (and B C)) into (and (xor A B) C). */
3791 if (GET_CODE (op0
) == GET_CODE (op1
)
3792 && (GET_CODE (op0
) == AND
3793 || GET_CODE (op0
) == LSHIFTRT
3794 || GET_CODE (op0
) == ASHIFTRT
3795 || GET_CODE (op0
) == ASHIFT
3796 || GET_CODE (op0
) == ROTATE
3797 || GET_CODE (op0
) == ROTATERT
))
3799 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
3804 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
3808 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3814 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3816 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
3818 if (HWI_COMPUTABLE_MODE_P (mode
))
3820 /* When WORD_REGISTER_OPERATIONS is true, we need to know the
3821 nonzero bits in WORD_MODE rather than MODE. */
3822 scalar_int_mode tmode
= as_a
<scalar_int_mode
> (mode
);
3823 if (WORD_REGISTER_OPERATIONS
3824 && GET_MODE_BITSIZE (tmode
) < BITS_PER_WORD
)
3826 HOST_WIDE_INT nzop0
= nonzero_bits (trueop0
, tmode
);
3827 HOST_WIDE_INT nzop1
;
3828 if (CONST_INT_P (trueop1
))
3830 HOST_WIDE_INT val1
= INTVAL (trueop1
);
3831 /* If we are turning off bits already known off in OP0, we need
3833 if ((nzop0
& ~val1
) == 0)
3836 nzop1
= nonzero_bits (trueop1
, mode
);
3837 /* If we are clearing all the nonzero bits, the result is zero. */
3838 if ((nzop1
& nzop0
) == 0
3839 && !side_effects_p (op0
) && !side_effects_p (op1
))
3840 return CONST0_RTX (mode
);
3842 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
3843 && GET_MODE_CLASS (mode
) != MODE_CC
)
3846 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
3847 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
3848 && ! side_effects_p (op0
)
3849 && GET_MODE_CLASS (mode
) != MODE_CC
)
3850 return CONST0_RTX (mode
);
3852 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
3853 there are no nonzero bits of C outside of X's mode. */
3854 if ((GET_CODE (op0
) == SIGN_EXTEND
3855 || GET_CODE (op0
) == ZERO_EXTEND
)
3856 && CONST_SCALAR_INT_P (trueop1
)
3857 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
3858 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op0
, 0)), &inner_mode
)
3859 && (wi::mask (GET_MODE_PRECISION (inner_mode
), true,
3860 GET_MODE_PRECISION (int_mode
))
3861 & rtx_mode_t (trueop1
, mode
)) == 0)
3863 machine_mode imode
= GET_MODE (XEXP (op0
, 0));
3864 tem
= immed_wide_int_const (rtx_mode_t (trueop1
, mode
), imode
);
3865 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0), tem
);
3866 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
3869 /* Transform (and (truncate X) C) into (truncate (and X C)). This way
3870 we might be able to further simplify the AND with X and potentially
3871 remove the truncation altogether. */
3872 if (GET_CODE (op0
) == TRUNCATE
&& CONST_INT_P (trueop1
))
3874 rtx x
= XEXP (op0
, 0);
3875 machine_mode xmode
= GET_MODE (x
);
3876 tem
= simplify_gen_binary (AND
, xmode
, x
,
3877 gen_int_mode (INTVAL (trueop1
), xmode
));
3878 return simplify_gen_unary (TRUNCATE
, mode
, tem
, xmode
);
3881 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
3882 if (GET_CODE (op0
) == IOR
3883 && CONST_INT_P (trueop1
)
3884 && CONST_INT_P (XEXP (op0
, 1)))
3886 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
3887 return simplify_gen_binary (IOR
, mode
,
3888 simplify_gen_binary (AND
, mode
,
3889 XEXP (op0
, 0), op1
),
3890 gen_int_mode (tmp
, mode
));
3893 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
3894 insn (and may simplify more). */
3895 if (GET_CODE (op0
) == XOR
3896 && rtx_equal_p (XEXP (op0
, 0), op1
)
3897 && ! side_effects_p (op1
))
3898 return simplify_gen_binary (AND
, mode
,
3899 simplify_gen_unary (NOT
, mode
,
3900 XEXP (op0
, 1), mode
),
3903 if (GET_CODE (op0
) == XOR
3904 && rtx_equal_p (XEXP (op0
, 1), op1
)
3905 && ! side_effects_p (op1
))
3906 return simplify_gen_binary (AND
, mode
,
3907 simplify_gen_unary (NOT
, mode
,
3908 XEXP (op0
, 0), mode
),
3911 /* Similarly for (~(A ^ B)) & A. */
3912 if (GET_CODE (op0
) == NOT
3913 && GET_CODE (XEXP (op0
, 0)) == XOR
3914 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
3915 && ! side_effects_p (op1
))
3916 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
3918 if (GET_CODE (op0
) == NOT
3919 && GET_CODE (XEXP (op0
, 0)) == XOR
3920 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
3921 && ! side_effects_p (op1
))
3922 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
3924 /* Convert (A | B) & A to A. */
3925 if (GET_CODE (op0
) == IOR
3926 && (rtx_equal_p (XEXP (op0
, 0), op1
)
3927 || rtx_equal_p (XEXP (op0
, 1), op1
))
3928 && ! side_effects_p (XEXP (op0
, 0))
3929 && ! side_effects_p (XEXP (op0
, 1)))
3932 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
3933 ((A & N) + B) & M -> (A + B) & M
3934 Similarly if (N & M) == 0,
3935 ((A | N) + B) & M -> (A + B) & M
3936 and for - instead of + and/or ^ instead of |.
3937 Also, if (N & M) == 0, then
3938 (A +- N) & M -> A & M. */
3939 if (CONST_INT_P (trueop1
)
3940 && HWI_COMPUTABLE_MODE_P (mode
)
3941 && ~UINTVAL (trueop1
)
3942 && (UINTVAL (trueop1
) & (UINTVAL (trueop1
) + 1)) == 0
3943 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
3948 pmop
[0] = XEXP (op0
, 0);
3949 pmop
[1] = XEXP (op0
, 1);
3951 if (CONST_INT_P (pmop
[1])
3952 && (UINTVAL (pmop
[1]) & UINTVAL (trueop1
)) == 0)
3953 return simplify_gen_binary (AND
, mode
, pmop
[0], op1
);
3955 for (which
= 0; which
< 2; which
++)
3958 switch (GET_CODE (tem
))
3961 if (CONST_INT_P (XEXP (tem
, 1))
3962 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
))
3963 == UINTVAL (trueop1
))
3964 pmop
[which
] = XEXP (tem
, 0);
3968 if (CONST_INT_P (XEXP (tem
, 1))
3969 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
)) == 0)
3970 pmop
[which
] = XEXP (tem
, 0);
3977 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
3979 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
3981 return simplify_gen_binary (code
, mode
, tem
, op1
);
3985 /* (and X (ior (not X) Y) -> (and X Y) */
3986 if (GET_CODE (op1
) == IOR
3987 && GET_CODE (XEXP (op1
, 0)) == NOT
3988 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 0), 0)))
3989 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
3991 /* (and (ior (not X) Y) X) -> (and X Y) */
3992 if (GET_CODE (op0
) == IOR
3993 && GET_CODE (XEXP (op0
, 0)) == NOT
3994 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 0), 0)))
3995 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
3997 /* (and X (ior Y (not X)) -> (and X Y) */
3998 if (GET_CODE (op1
) == IOR
3999 && GET_CODE (XEXP (op1
, 1)) == NOT
4000 && rtx_equal_p (op0
, XEXP (XEXP (op1
, 1), 0)))
4001 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 0));
4003 /* (and (ior Y (not X)) X) -> (and X Y) */
4004 if (GET_CODE (op0
) == IOR
4005 && GET_CODE (XEXP (op0
, 1)) == NOT
4006 && rtx_equal_p (op1
, XEXP (XEXP (op0
, 1), 0)))
4007 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 0));
4009 /* Convert (and (ior A C) (ior B C)) into (ior (and A B) C). */
4010 if (GET_CODE (op0
) == GET_CODE (op1
)
4011 && (GET_CODE (op0
) == AND
4012 || GET_CODE (op0
) == IOR
4013 || GET_CODE (op0
) == LSHIFTRT
4014 || GET_CODE (op0
) == ASHIFTRT
4015 || GET_CODE (op0
) == ASHIFT
4016 || GET_CODE (op0
) == ROTATE
4017 || GET_CODE (op0
) == ROTATERT
))
4019 tem
= simplify_distributive_operation (code
, mode
, op0
, op1
);
4024 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
4028 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
4034 /* 0/x is 0 (or x&0 if x has side-effects). */
4035 if (trueop0
== CONST0_RTX (mode
)
4036 && !cfun
->can_throw_non_call_exceptions
)
4038 if (side_effects_p (op1
))
4039 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
4043 if (trueop1
== CONST1_RTX (mode
))
4045 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
4049 /* Convert divide by power of two into shift. */
4050 if (CONST_INT_P (trueop1
)
4051 && (val
= exact_log2 (UINTVAL (trueop1
))) > 0)
4052 return simplify_gen_binary (LSHIFTRT
, mode
, op0
,
4053 gen_int_shift_amount (mode
, val
));
4057 /* Handle floating point and integers separately. */
4058 if (SCALAR_FLOAT_MODE_P (mode
))
4060 /* Maybe change 0.0 / x to 0.0. This transformation isn't
4061 safe for modes with NaNs, since 0.0 / 0.0 will then be
4062 NaN rather than 0.0. Nor is it safe for modes with signed
4063 zeros, since dividing 0 by a negative number gives -0.0 */
4064 if (trueop0
== CONST0_RTX (mode
)
4065 && !HONOR_NANS (mode
)
4066 && !HONOR_SIGNED_ZEROS (mode
)
4067 && ! side_effects_p (op1
))
4070 if (trueop1
== CONST1_RTX (mode
)
4071 && !HONOR_SNANS (mode
))
4074 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
4075 && trueop1
!= CONST0_RTX (mode
))
4077 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
4080 if (real_equal (d1
, &dconstm1
)
4081 && !HONOR_SNANS (mode
))
4082 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
4084 /* Change FP division by a constant into multiplication.
4085 Only do this with -freciprocal-math. */
4086 if (flag_reciprocal_math
4087 && !real_equal (d1
, &dconst0
))
4090 real_arithmetic (&d
, RDIV_EXPR
, &dconst1
, d1
);
4091 tem
= const_double_from_real_value (d
, mode
);
4092 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
4096 else if (SCALAR_INT_MODE_P (mode
))
4098 /* 0/x is 0 (or x&0 if x has side-effects). */
4099 if (trueop0
== CONST0_RTX (mode
)
4100 && !cfun
->can_throw_non_call_exceptions
)
4102 if (side_effects_p (op1
))
4103 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
4107 if (trueop1
== CONST1_RTX (mode
))
4109 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
4114 if (trueop1
== constm1_rtx
)
4116 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
4118 return simplify_gen_unary (NEG
, mode
, x
, mode
);
4124 /* 0%x is 0 (or x&0 if x has side-effects). */
4125 if (trueop0
== CONST0_RTX (mode
))
4127 if (side_effects_p (op1
))
4128 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
4131 /* x%1 is 0 (of x&0 if x has side-effects). */
4132 if (trueop1
== CONST1_RTX (mode
))
4134 if (side_effects_p (op0
))
4135 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
4136 return CONST0_RTX (mode
);
4138 /* Implement modulus by power of two as AND. */
4139 if (CONST_INT_P (trueop1
)
4140 && exact_log2 (UINTVAL (trueop1
)) > 0)
4141 return simplify_gen_binary (AND
, mode
, op0
,
4142 gen_int_mode (UINTVAL (trueop1
) - 1,
4147 /* 0%x is 0 (or x&0 if x has side-effects). */
4148 if (trueop0
== CONST0_RTX (mode
))
4150 if (side_effects_p (op1
))
4151 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
4154 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
4155 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
4157 if (side_effects_p (op0
))
4158 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
4159 return CONST0_RTX (mode
);
4165 if (trueop1
== CONST0_RTX (mode
))
4167 /* Canonicalize rotates by constant amount. If the condition of
4168 reversing direction is met, then reverse the direction. */
4169 #if defined(HAVE_rotate) && defined(HAVE_rotatert)
4170 if (reverse_rotate_by_imm_p (mode
, (code
== ROTATE
), trueop1
))
4172 int new_amount
= GET_MODE_UNIT_PRECISION (mode
) - INTVAL (trueop1
);
4173 rtx new_amount_rtx
= gen_int_shift_amount (mode
, new_amount
);
4174 return simplify_gen_binary (code
== ROTATE
? ROTATERT
: ROTATE
,
4175 mode
, op0
, new_amount_rtx
);
4180 if (trueop1
== CONST0_RTX (mode
))
4182 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
4184 /* Rotating ~0 always results in ~0. */
4185 if (CONST_INT_P (trueop0
)
4186 && HWI_COMPUTABLE_MODE_P (mode
)
4187 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
4188 && ! side_effects_p (op1
))
4194 scalar constants c1, c2
4195 size (M2) > size (M1)
4196 c1 == size (M2) - size (M1)
4198 ([a|l]shiftrt:M1 (subreg:M1 (lshiftrt:M2 (reg:M2) (const_int <c1>))
4202 (subreg:M1 ([a|l]shiftrt:M2 (reg:M2) (const_int <c1 + c2>))
4204 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
4205 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
4207 && CONST_INT_P (op1
)
4208 && GET_CODE (SUBREG_REG (op0
)) == LSHIFTRT
4209 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
4211 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1))
4212 && GET_MODE_BITSIZE (inner_mode
) > GET_MODE_BITSIZE (int_mode
)
4213 && (INTVAL (XEXP (SUBREG_REG (op0
), 1))
4214 == GET_MODE_BITSIZE (inner_mode
) - GET_MODE_BITSIZE (int_mode
))
4215 && subreg_lowpart_p (op0
))
4217 rtx tmp
= gen_int_shift_amount
4218 (inner_mode
, INTVAL (XEXP (SUBREG_REG (op0
), 1)) + INTVAL (op1
));
4220 /* Combine would usually zero out the value when combining two
4221 local shifts and the range becomes larger or equal to the mode.
4222 However since we fold away one of the shifts here combine won't
4223 see it so we should immediately zero the result if it's out of
4225 if (code
== LSHIFTRT
4226 && INTVAL (tmp
) >= GET_MODE_BITSIZE (inner_mode
))
4229 tmp
= simplify_gen_binary (code
,
4231 XEXP (SUBREG_REG (op0
), 0),
4234 return lowpart_subreg (int_mode
, tmp
, inner_mode
);
4237 if (SHIFT_COUNT_TRUNCATED
&& CONST_INT_P (op1
))
4239 val
= INTVAL (op1
) & (GET_MODE_UNIT_PRECISION (mode
) - 1);
4240 if (val
!= INTVAL (op1
))
4241 return simplify_gen_binary (code
, mode
, op0
,
4242 gen_int_shift_amount (mode
, val
));
4247 if (CONST_INT_P (trueop0
)
4248 && HWI_COMPUTABLE_MODE_P (mode
)
4249 && (UINTVAL (trueop0
) == (GET_MODE_MASK (mode
) >> 1)
4250 || mode_signbit_p (mode
, trueop0
))
4251 && ! side_effects_p (op1
))
4253 goto simplify_ashift
;
4256 if (CONST_INT_P (trueop0
)
4257 && HWI_COMPUTABLE_MODE_P (mode
)
4258 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
4259 && ! side_effects_p (op1
))
4265 if (trueop1
== CONST0_RTX (mode
))
4267 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
4271 && CONST_INT_P (trueop1
)
4272 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
4273 && IN_RANGE (UINTVAL (trueop1
),
4274 1, GET_MODE_PRECISION (int_mode
) - 1))
4276 auto c
= (wi::one (GET_MODE_PRECISION (int_mode
))
4277 << UINTVAL (trueop1
));
4278 rtx new_op1
= immed_wide_int_const (c
, int_mode
);
4279 return simplify_gen_binary (MULT
, int_mode
, op0
, new_op1
);
4281 goto canonicalize_shift
;
4284 if (trueop1
== CONST0_RTX (mode
))
4286 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
4288 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
4289 if (GET_CODE (op0
) == CLZ
4290 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (op0
, 0)), &inner_mode
)
4291 && CONST_INT_P (trueop1
)
4292 && STORE_FLAG_VALUE
== 1
4293 && INTVAL (trueop1
) < GET_MODE_UNIT_PRECISION (mode
))
4295 unsigned HOST_WIDE_INT zero_val
= 0;
4297 if (CLZ_DEFINED_VALUE_AT_ZERO (inner_mode
, zero_val
)
4298 && zero_val
== GET_MODE_PRECISION (inner_mode
)
4299 && INTVAL (trueop1
) == exact_log2 (zero_val
))
4300 return simplify_gen_relational (EQ
, mode
, inner_mode
,
4301 XEXP (op0
, 0), const0_rtx
);
4303 goto canonicalize_shift
;
4306 if (HWI_COMPUTABLE_MODE_P (mode
)
4307 && mode_signbit_p (mode
, trueop1
)
4308 && ! side_effects_p (op0
))
4310 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
4312 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
4318 if (HWI_COMPUTABLE_MODE_P (mode
)
4319 && CONST_INT_P (trueop1
)
4320 && (UINTVAL (trueop1
) == GET_MODE_MASK (mode
) >> 1)
4321 && ! side_effects_p (op0
))
4323 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
4325 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
4331 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
4333 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
4335 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
4341 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
4343 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
4345 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
4354 /* Simplify x +/- 0 to x, if possible. */
4355 if (trueop1
== CONST0_RTX (mode
))
4361 /* Simplify x * 0 to 0, if possible. */
4362 if (trueop1
== CONST0_RTX (mode
)
4363 && !side_effects_p (op0
))
4366 /* Simplify x * 1 to x, if possible. */
4367 if (trueop1
== CONST1_RTX (mode
))
4373 /* Simplify x * 0 to 0, if possible. */
4374 if (trueop1
== CONST0_RTX (mode
)
4375 && !side_effects_p (op0
))
4381 /* Simplify x / 1 to x, if possible. */
4382 if (trueop1
== CONST1_RTX (mode
))
4387 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
4389 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
))
4392 real_convert (&f1
, mode
, CONST_DOUBLE_REAL_VALUE (trueop1
));
4393 rtx tmp
= simplify_gen_unary (ABS
, mode
, op0
, mode
);
4394 if (REAL_VALUE_NEGATIVE (f1
))
4395 tmp
= simplify_gen_unary (NEG
, mode
, op0
, mode
);
4398 if (GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
4399 return simplify_gen_binary (COPYSIGN
, mode
, XEXP (op0
, 0), op1
);
4400 if (GET_CODE (op1
) == ABS
4401 && ! side_effects_p (op1
))
4402 return simplify_gen_unary (ABS
, mode
, op0
, mode
);
4403 if (GET_CODE (op0
) == COPYSIGN
4404 && ! side_effects_p (XEXP (op0
, 1)))
4405 return simplify_gen_binary (COPYSIGN
, mode
, XEXP (op0
, 0), op1
);
4406 if (GET_CODE (op1
) == COPYSIGN
4407 && ! side_effects_p (XEXP (op1
, 0)))
4408 return simplify_gen_binary (COPYSIGN
, mode
, op0
, XEXP (op1
, 1));
4412 if (op1
== CONST0_RTX (GET_MODE_INNER (mode
)))
4413 return gen_vec_duplicate (mode
, op0
);
4414 if (valid_for_const_vector_p (mode
, op0
)
4415 && valid_for_const_vector_p (mode
, op1
))
4416 return gen_const_vec_series (mode
, op0
, op1
);
4420 if (!VECTOR_MODE_P (mode
))
4422 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
4423 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
4424 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
4425 gcc_assert (XVECLEN (trueop1
, 0) == 1);
4427 /* We can't reason about selections made at runtime. */
4428 if (!CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
4431 if (vec_duplicate_p (trueop0
, &elt0
))
4434 if (GET_CODE (trueop0
) == CONST_VECTOR
)
4435 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
4438 /* Extract a scalar element from a nested VEC_SELECT expression
4439 (with optional nested VEC_CONCAT expression). Some targets
4440 (i386) extract scalar element from a vector using chain of
4441 nested VEC_SELECT expressions. When input operand is a memory
4442 operand, this operation can be simplified to a simple scalar
4443 load from an offseted memory address. */
4445 if (GET_CODE (trueop0
) == VEC_SELECT
4446 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
4447 .is_constant (&n_elts
)))
4449 rtx op0
= XEXP (trueop0
, 0);
4450 rtx op1
= XEXP (trueop0
, 1);
4452 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
4458 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4459 gcc_assert (i
< n_elts
);
4461 /* Select element, pointed by nested selector. */
4462 elem
= INTVAL (XVECEXP (op1
, 0, i
));
4464 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
4465 if (GET_CODE (op0
) == VEC_CONCAT
)
4467 rtx op00
= XEXP (op0
, 0);
4468 rtx op01
= XEXP (op0
, 1);
4470 machine_mode mode00
, mode01
;
4471 int n_elts00
, n_elts01
;
4473 mode00
= GET_MODE (op00
);
4474 mode01
= GET_MODE (op01
);
4476 /* Find out the number of elements of each operand.
4477 Since the concatenated result has a constant number
4478 of elements, the operands must too. */
4479 n_elts00
= GET_MODE_NUNITS (mode00
).to_constant ();
4480 n_elts01
= GET_MODE_NUNITS (mode01
).to_constant ();
4482 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
4484 /* Select correct operand of VEC_CONCAT
4485 and adjust selector. */
4486 if (elem
< n_elts01
)
4497 vec
= rtvec_alloc (1);
4498 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
4500 tmp
= gen_rtx_fmt_ee (code
, mode
,
4501 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
4507 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
4508 gcc_assert (GET_MODE_INNER (mode
)
4509 == GET_MODE_INNER (GET_MODE (trueop0
)));
4510 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
4512 if (vec_duplicate_p (trueop0
, &elt0
))
4513 /* It doesn't matter which elements are selected by trueop1,
4514 because they are all the same. */
4515 return gen_vec_duplicate (mode
, elt0
);
4517 if (GET_CODE (trueop0
) == CONST_VECTOR
)
4519 unsigned n_elts
= XVECLEN (trueop1
, 0);
4520 rtvec v
= rtvec_alloc (n_elts
);
4523 gcc_assert (known_eq (n_elts
, GET_MODE_NUNITS (mode
)));
4524 for (i
= 0; i
< n_elts
; i
++)
4526 rtx x
= XVECEXP (trueop1
, 0, i
);
4528 if (!CONST_INT_P (x
))
4531 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
4535 return gen_rtx_CONST_VECTOR (mode
, v
);
4538 /* Recognize the identity. */
4539 if (GET_MODE (trueop0
) == mode
)
4541 bool maybe_ident
= true;
4542 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
4544 rtx j
= XVECEXP (trueop1
, 0, i
);
4545 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
4547 maybe_ident
= false;
4555 /* If we select a low-part subreg, return that. */
4556 if (vec_series_lowpart_p (mode
, GET_MODE (trueop0
), trueop1
))
4558 rtx new_rtx
= lowpart_subreg (mode
, trueop0
,
4559 GET_MODE (trueop0
));
4560 if (new_rtx
!= NULL_RTX
)
4564 /* If we build {a,b} then permute it, build the result directly. */
4565 if (XVECLEN (trueop1
, 0) == 2
4566 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4567 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
4568 && GET_CODE (trueop0
) == VEC_CONCAT
4569 && GET_CODE (XEXP (trueop0
, 0)) == VEC_CONCAT
4570 && GET_MODE (XEXP (trueop0
, 0)) == mode
4571 && GET_CODE (XEXP (trueop0
, 1)) == VEC_CONCAT
4572 && GET_MODE (XEXP (trueop0
, 1)) == mode
)
4574 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4575 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
4578 gcc_assert (i0
< 4 && i1
< 4);
4579 subop0
= XEXP (XEXP (trueop0
, i0
/ 2), i0
% 2);
4580 subop1
= XEXP (XEXP (trueop0
, i1
/ 2), i1
% 2);
4582 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
4585 if (XVECLEN (trueop1
, 0) == 2
4586 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4587 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
4588 && GET_CODE (trueop0
) == VEC_CONCAT
4589 && GET_MODE (trueop0
) == mode
)
4591 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4592 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
4595 gcc_assert (i0
< 2 && i1
< 2);
4596 subop0
= XEXP (trueop0
, i0
);
4597 subop1
= XEXP (trueop0
, i1
);
4599 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
4602 /* If we select one half of a vec_concat, return that. */
4604 if (GET_CODE (trueop0
) == VEC_CONCAT
4605 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 0)))
4607 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0
, 1)))
4609 && CONST_INT_P (XVECEXP (trueop1
, 0, 0)))
4611 rtx subop0
= XEXP (trueop0
, 0);
4612 rtx subop1
= XEXP (trueop0
, 1);
4613 machine_mode mode0
= GET_MODE (subop0
);
4614 machine_mode mode1
= GET_MODE (subop1
);
4615 int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
4616 if (i0
== 0 && !side_effects_p (op1
) && mode
== mode0
)
4618 bool success
= true;
4619 for (int i
= 1; i
< l0
; ++i
)
4621 rtx j
= XVECEXP (trueop1
, 0, i
);
4622 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
4631 if (i0
== l0
&& !side_effects_p (op0
) && mode
== mode1
)
4633 bool success
= true;
4634 for (int i
= 1; i
< l1
; ++i
)
4636 rtx j
= XVECEXP (trueop1
, 0, i
);
4637 if (!CONST_INT_P (j
) || INTVAL (j
) != i0
+ i
)
4648 /* Simplify vec_select of a subreg of X to just a vec_select of X
4649 when X has same component mode as vec_select. */
4650 unsigned HOST_WIDE_INT subreg_offset
= 0;
4651 if (GET_CODE (trueop0
) == SUBREG
4652 && GET_MODE_INNER (mode
)
4653 == GET_MODE_INNER (GET_MODE (SUBREG_REG (trueop0
)))
4654 && GET_MODE_NUNITS (mode
).is_constant (&l1
)
4655 && constant_multiple_p (subreg_memory_offset (trueop0
),
4656 GET_MODE_UNIT_BITSIZE (mode
),
4660 = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0
)));
4661 bool success
= true;
4662 for (int i
= 0; i
!= l1
; i
++)
4664 rtx idx
= XVECEXP (trueop1
, 0, i
);
4665 if (!CONST_INT_P (idx
)
4666 || maybe_ge (UINTVAL (idx
) + subreg_offset
, nunits
))
4678 rtvec vec
= rtvec_alloc (l1
);
4679 for (int i
= 0; i
< l1
; i
++)
4681 = GEN_INT (INTVAL (XVECEXP (trueop1
, 0, i
))
4683 par
= gen_rtx_PARALLEL (VOIDmode
, vec
);
4685 return gen_rtx_VEC_SELECT (mode
, SUBREG_REG (trueop0
), par
);
4690 if (XVECLEN (trueop1
, 0) == 1
4691 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
4692 && GET_CODE (trueop0
) == VEC_CONCAT
)
4695 offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
4697 /* Try to find the element in the VEC_CONCAT. */
4698 while (GET_MODE (vec
) != mode
4699 && GET_CODE (vec
) == VEC_CONCAT
)
4701 poly_int64 vec_size
;
4703 if (CONST_INT_P (XEXP (vec
, 0)))
4705 /* vec_concat of two const_ints doesn't make sense with
4706 respect to modes. */
4707 if (CONST_INT_P (XEXP (vec
, 1)))
4710 vec_size
= GET_MODE_SIZE (GET_MODE (trueop0
))
4711 - GET_MODE_SIZE (GET_MODE (XEXP (vec
, 1)));
4714 vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
4716 if (known_lt (offset
, vec_size
))
4717 vec
= XEXP (vec
, 0);
4718 else if (known_ge (offset
, vec_size
))
4721 vec
= XEXP (vec
, 1);
4725 vec
= avoid_constant_pool_reference (vec
);
4728 if (GET_MODE (vec
) == mode
)
4732 /* If we select elements in a vec_merge that all come from the same
4733 operand, select from that operand directly. */
4734 if (GET_CODE (op0
) == VEC_MERGE
)
4736 rtx trueop02
= avoid_constant_pool_reference (XEXP (op0
, 2));
4737 if (CONST_INT_P (trueop02
))
4739 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop02
);
4740 bool all_operand0
= true;
4741 bool all_operand1
= true;
4742 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
4744 rtx j
= XVECEXP (trueop1
, 0, i
);
4745 if (sel
& (HOST_WIDE_INT_1U
<< UINTVAL (j
)))
4746 all_operand1
= false;
4748 all_operand0
= false;
4750 if (all_operand0
&& !side_effects_p (XEXP (op0
, 1)))
4751 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 0), op1
);
4752 if (all_operand1
&& !side_effects_p (XEXP (op0
, 0)))
4753 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 1), op1
);
4757 /* If we have two nested selects that are inverses of each
4758 other, replace them with the source operand. */
4759 if (GET_CODE (trueop0
) == VEC_SELECT
4760 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
4762 rtx op0_subop1
= XEXP (trueop0
, 1);
4763 gcc_assert (GET_CODE (op0_subop1
) == PARALLEL
);
4764 gcc_assert (known_eq (XVECLEN (trueop1
, 0), GET_MODE_NUNITS (mode
)));
4766 /* Apply the outer ordering vector to the inner one. (The inner
4767 ordering vector is expressly permitted to be of a different
4768 length than the outer one.) If the result is { 0, 1, ..., n-1 }
4769 then the two VEC_SELECTs cancel. */
4770 for (int i
= 0; i
< XVECLEN (trueop1
, 0); ++i
)
4772 rtx x
= XVECEXP (trueop1
, 0, i
);
4773 if (!CONST_INT_P (x
))
4775 rtx y
= XVECEXP (op0_subop1
, 0, INTVAL (x
));
4776 if (!CONST_INT_P (y
) || i
!= INTVAL (y
))
4779 return XEXP (trueop0
, 0);
4785 machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
4786 ? GET_MODE (trueop0
)
4787 : GET_MODE_INNER (mode
));
4788 machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
4789 ? GET_MODE (trueop1
)
4790 : GET_MODE_INNER (mode
));
4792 gcc_assert (VECTOR_MODE_P (mode
));
4793 gcc_assert (known_eq (GET_MODE_SIZE (op0_mode
)
4794 + GET_MODE_SIZE (op1_mode
),
4795 GET_MODE_SIZE (mode
)));
4797 if (VECTOR_MODE_P (op0_mode
))
4798 gcc_assert (GET_MODE_INNER (mode
)
4799 == GET_MODE_INNER (op0_mode
));
4801 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
4803 if (VECTOR_MODE_P (op1_mode
))
4804 gcc_assert (GET_MODE_INNER (mode
)
4805 == GET_MODE_INNER (op1_mode
));
4807 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
4809 unsigned int n_elts
, in_n_elts
;
4810 if ((GET_CODE (trueop0
) == CONST_VECTOR
4811 || CONST_SCALAR_INT_P (trueop0
)
4812 || CONST_DOUBLE_AS_FLOAT_P (trueop0
))
4813 && (GET_CODE (trueop1
) == CONST_VECTOR
4814 || CONST_SCALAR_INT_P (trueop1
)
4815 || CONST_DOUBLE_AS_FLOAT_P (trueop1
))
4816 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
)
4817 && GET_MODE_NUNITS (op0_mode
).is_constant (&in_n_elts
))
4819 rtvec v
= rtvec_alloc (n_elts
);
4821 for (i
= 0; i
< n_elts
; i
++)
4825 if (!VECTOR_MODE_P (op0_mode
))
4826 RTVEC_ELT (v
, i
) = trueop0
;
4828 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
4832 if (!VECTOR_MODE_P (op1_mode
))
4833 RTVEC_ELT (v
, i
) = trueop1
;
4835 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
4840 return gen_rtx_CONST_VECTOR (mode
, v
);
4843 /* Try to merge two VEC_SELECTs from the same vector into a single one.
4844 Restrict the transformation to avoid generating a VEC_SELECT with a
4845 mode unrelated to its operand. */
4846 if (GET_CODE (trueop0
) == VEC_SELECT
4847 && GET_CODE (trueop1
) == VEC_SELECT
4848 && rtx_equal_p (XEXP (trueop0
, 0), XEXP (trueop1
, 0))
4849 && GET_MODE_INNER (GET_MODE (XEXP (trueop0
, 0)))
4850 == GET_MODE_INNER(mode
))
4852 rtx par0
= XEXP (trueop0
, 1);
4853 rtx par1
= XEXP (trueop1
, 1);
4854 int len0
= XVECLEN (par0
, 0);
4855 int len1
= XVECLEN (par1
, 0);
4856 rtvec vec
= rtvec_alloc (len0
+ len1
);
4857 for (int i
= 0; i
< len0
; i
++)
4858 RTVEC_ELT (vec
, i
) = XVECEXP (par0
, 0, i
);
4859 for (int i
= 0; i
< len1
; i
++)
4860 RTVEC_ELT (vec
, len0
+ i
) = XVECEXP (par1
, 0, i
);
4861 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (trueop0
, 0),
4862 gen_rtx_PARALLEL (VOIDmode
, vec
));
4865 (subreg_lowpart:N OP)
4866 (vec_select:N OP P)) --> OP when P selects the high half
4868 if (GET_CODE (trueop0
) == SUBREG
4869 && subreg_lowpart_p (trueop0
)
4870 && GET_CODE (trueop1
) == VEC_SELECT
4871 && SUBREG_REG (trueop0
) == XEXP (trueop1
, 0)
4872 && !side_effects_p (XEXP (trueop1
, 0))
4873 && vec_series_highpart_p (op1_mode
, mode
, XEXP (trueop1
, 1)))
4874 return XEXP (trueop1
, 0);
4882 if (mode
== GET_MODE (op0
)
4883 && mode
== GET_MODE (op1
)
4884 && vec_duplicate_p (op0
, &elt0
)
4885 && vec_duplicate_p (op1
, &elt1
))
4887 /* Try applying the operator to ELT and see if that simplifies.
4888 We can duplicate the result if so.
4890 The reason we don't use simplify_gen_binary is that it isn't
4891 necessarily a win to convert things like:
4893 (plus:V (vec_duplicate:V (reg:S R1))
4894 (vec_duplicate:V (reg:S R2)))
4898 (vec_duplicate:V (plus:S (reg:S R1) (reg:S R2)))
4900 The first might be done entirely in vector registers while the
4901 second might need a move between register files. */
4902 tem
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4905 return gen_vec_duplicate (mode
, tem
);
4911 /* Return true if binary operation OP distributes over addition in operand
4912 OPNO, with the other operand being held constant. OPNO counts from 1. */
4915 distributes_over_addition_p (rtx_code op
, int opno
)
4933 simplify_const_binary_operation (enum rtx_code code
, machine_mode mode
,
4936 if (VECTOR_MODE_P (mode
)
4937 && code
!= VEC_CONCAT
4938 && GET_CODE (op0
) == CONST_VECTOR
4939 && GET_CODE (op1
) == CONST_VECTOR
)
4942 if (CONST_VECTOR_STEPPED_P (op0
)
4943 && CONST_VECTOR_STEPPED_P (op1
))
4944 /* We can operate directly on the encoding if:
4946 a3 - a2 == a2 - a1 && b3 - b2 == b2 - b1
4948 (a3 op b3) - (a2 op b2) == (a2 op b2) - (a1 op b1)
4950 Addition and subtraction are the supported operators
4951 for which this is true. */
4952 step_ok_p
= (code
== PLUS
|| code
== MINUS
);
4953 else if (CONST_VECTOR_STEPPED_P (op0
))
4954 /* We can operate directly on stepped encodings if:
4958 (a3 op c) - (a2 op c) == (a2 op c) - (a1 op c)
4960 which is true if (x -> x op c) distributes over addition. */
4961 step_ok_p
= distributes_over_addition_p (code
, 1);
4963 /* Similarly in reverse. */
4964 step_ok_p
= distributes_over_addition_p (code
, 2);
4965 rtx_vector_builder builder
;
4966 if (!builder
.new_binary_operation (mode
, op0
, op1
, step_ok_p
))
4969 unsigned int count
= builder
.encoded_nelts ();
4970 for (unsigned int i
= 0; i
< count
; i
++)
4972 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
4973 CONST_VECTOR_ELT (op0
, i
),
4974 CONST_VECTOR_ELT (op1
, i
));
4975 if (!x
|| !valid_for_const_vector_p (mode
, x
))
4977 builder
.quick_push (x
);
4979 return builder
.build ();
4982 if (VECTOR_MODE_P (mode
)
4983 && code
== VEC_CONCAT
4984 && (CONST_SCALAR_INT_P (op0
)
4985 || CONST_FIXED_P (op0
)
4986 || CONST_DOUBLE_AS_FLOAT_P (op0
))
4987 && (CONST_SCALAR_INT_P (op1
)
4988 || CONST_DOUBLE_AS_FLOAT_P (op1
)
4989 || CONST_FIXED_P (op1
)))
4991 /* Both inputs have a constant number of elements, so the result
4993 unsigned n_elts
= GET_MODE_NUNITS (mode
).to_constant ();
4994 rtvec v
= rtvec_alloc (n_elts
);
4996 gcc_assert (n_elts
>= 2);
4999 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
5000 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
5002 RTVEC_ELT (v
, 0) = op0
;
5003 RTVEC_ELT (v
, 1) = op1
;
5007 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
)).to_constant ();
5008 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
)).to_constant ();
5011 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
5012 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
5013 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
5015 for (i
= 0; i
< op0_n_elts
; ++i
)
5016 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op0
, i
);
5017 for (i
= 0; i
< op1_n_elts
; ++i
)
5018 RTVEC_ELT (v
, op0_n_elts
+i
) = CONST_VECTOR_ELT (op1
, i
);
5021 return gen_rtx_CONST_VECTOR (mode
, v
);
5024 if (SCALAR_FLOAT_MODE_P (mode
)
5025 && CONST_DOUBLE_AS_FLOAT_P (op0
)
5026 && CONST_DOUBLE_AS_FLOAT_P (op1
)
5027 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
5038 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
5040 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
5042 for (i
= 0; i
< 4; i
++)
5059 real_from_target (&r
, tmp0
, mode
);
5060 return const_double_from_real_value (r
, mode
);
5062 else if (code
== COPYSIGN
)
5064 REAL_VALUE_TYPE f0
, f1
;
5065 real_convert (&f0
, mode
, CONST_DOUBLE_REAL_VALUE (op0
));
5066 real_convert (&f1
, mode
, CONST_DOUBLE_REAL_VALUE (op1
));
5067 real_copysign (&f0
, &f1
);
5068 return const_double_from_real_value (f0
, mode
);
5072 REAL_VALUE_TYPE f0
, f1
, value
, result
;
5073 const REAL_VALUE_TYPE
*opr0
, *opr1
;
5076 opr0
= CONST_DOUBLE_REAL_VALUE (op0
);
5077 opr1
= CONST_DOUBLE_REAL_VALUE (op1
);
5079 if (HONOR_SNANS (mode
)
5080 && (REAL_VALUE_ISSIGNALING_NAN (*opr0
)
5081 || REAL_VALUE_ISSIGNALING_NAN (*opr1
)))
5084 real_convert (&f0
, mode
, opr0
);
5085 real_convert (&f1
, mode
, opr1
);
5088 && real_equal (&f1
, &dconst0
)
5089 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
5092 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
5093 && flag_trapping_math
5094 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
5096 int s0
= REAL_VALUE_NEGATIVE (f0
);
5097 int s1
= REAL_VALUE_NEGATIVE (f1
);
5102 /* Inf + -Inf = NaN plus exception. */
5107 /* Inf - Inf = NaN plus exception. */
5112 /* Inf / Inf = NaN plus exception. */
5119 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
5120 && flag_trapping_math
5121 && ((REAL_VALUE_ISINF (f0
) && real_equal (&f1
, &dconst0
))
5122 || (REAL_VALUE_ISINF (f1
)
5123 && real_equal (&f0
, &dconst0
))))
5124 /* Inf * 0 = NaN plus exception. */
5127 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
5129 real_convert (&result
, mode
, &value
);
5131 /* Don't constant fold this floating point operation if
5132 the result has overflowed and flag_trapping_math. */
5134 if (flag_trapping_math
5135 && MODE_HAS_INFINITIES (mode
)
5136 && REAL_VALUE_ISINF (result
)
5137 && !REAL_VALUE_ISINF (f0
)
5138 && !REAL_VALUE_ISINF (f1
))
5139 /* Overflow plus exception. */
5142 /* Don't constant fold this floating point operation if the
5143 result may dependent upon the run-time rounding mode and
5144 flag_rounding_math is set, or if GCC's software emulation
5145 is unable to accurately represent the result. */
5147 if ((flag_rounding_math
5148 || (MODE_COMPOSITE_P (mode
) && !flag_unsafe_math_optimizations
))
5149 && (inexact
|| !real_identical (&result
, &value
)))
5152 return const_double_from_real_value (result
, mode
);
5156 /* We can fold some multi-word operations. */
5157 scalar_int_mode int_mode
;
5158 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
5159 && CONST_SCALAR_INT_P (op0
)
5160 && CONST_SCALAR_INT_P (op1
)
5161 && GET_MODE_PRECISION (int_mode
) <= MAX_BITSIZE_MODE_ANY_INT
)
5164 wi::overflow_type overflow
;
5165 rtx_mode_t pop0
= rtx_mode_t (op0
, int_mode
);
5166 rtx_mode_t pop1
= rtx_mode_t (op1
, int_mode
);
5168 #if TARGET_SUPPORTS_WIDE_INT == 0
5169 /* This assert keeps the simplification from producing a result
5170 that cannot be represented in a CONST_DOUBLE but a lot of
5171 upstream callers expect that this function never fails to
5172 simplify something and so you if you added this to the test
5173 above the code would die later anyway. If this assert
5174 happens, you just need to make the port support wide int. */
5175 gcc_assert (GET_MODE_PRECISION (int_mode
) <= HOST_BITS_PER_DOUBLE_INT
);
5180 result
= wi::sub (pop0
, pop1
);
5184 result
= wi::add (pop0
, pop1
);
5188 result
= wi::mul (pop0
, pop1
);
5192 result
= wi::div_trunc (pop0
, pop1
, SIGNED
, &overflow
);
5198 result
= wi::mod_trunc (pop0
, pop1
, SIGNED
, &overflow
);
5204 result
= wi::div_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
5210 result
= wi::mod_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
5216 result
= wi::bit_and (pop0
, pop1
);
5220 result
= wi::bit_or (pop0
, pop1
);
5224 result
= wi::bit_xor (pop0
, pop1
);
5228 result
= wi::smin (pop0
, pop1
);
5232 result
= wi::smax (pop0
, pop1
);
5236 result
= wi::umin (pop0
, pop1
);
5240 result
= wi::umax (pop0
, pop1
);
5249 /* The shift count might be in SImode while int_mode might
5250 be narrower. On IA-64 it is even DImode. If the shift
5251 count is too large and doesn't fit into int_mode, we'd
5252 ICE. So, if int_mode is narrower than word, use
5253 word_mode for the shift count. */
5254 if (GET_MODE (op1
) == VOIDmode
5255 && GET_MODE_PRECISION (int_mode
) < BITS_PER_WORD
)
5256 pop1
= rtx_mode_t (op1
, word_mode
);
5258 wide_int wop1
= pop1
;
5259 if (SHIFT_COUNT_TRUNCATED
)
5260 wop1
= wi::umod_trunc (wop1
, GET_MODE_PRECISION (int_mode
));
5261 else if (wi::geu_p (wop1
, GET_MODE_PRECISION (int_mode
)))
5267 result
= wi::lrshift (pop0
, wop1
);
5271 result
= wi::arshift (pop0
, wop1
);
5275 result
= wi::lshift (pop0
, wop1
);
5279 if (wi::leu_p (wop1
, wi::clrsb (pop0
)))
5280 result
= wi::lshift (pop0
, wop1
);
5281 else if (wi::neg_p (pop0
))
5282 result
= wi::min_value (int_mode
, SIGNED
);
5284 result
= wi::max_value (int_mode
, SIGNED
);
5288 if (wi::eq_p (pop0
, 0))
5290 else if (wi::leu_p (wop1
, wi::clz (pop0
)))
5291 result
= wi::lshift (pop0
, wop1
);
5293 result
= wi::max_value (int_mode
, UNSIGNED
);
5304 /* The rotate count might be in SImode while int_mode might
5305 be narrower. On IA-64 it is even DImode. If the shift
5306 count is too large and doesn't fit into int_mode, we'd
5307 ICE. So, if int_mode is narrower than word, use
5308 word_mode for the shift count. */
5309 if (GET_MODE (op1
) == VOIDmode
5310 && GET_MODE_PRECISION (int_mode
) < BITS_PER_WORD
)
5311 pop1
= rtx_mode_t (op1
, word_mode
);
5313 if (wi::neg_p (pop1
))
5319 result
= wi::lrotate (pop0
, pop1
);
5323 result
= wi::rrotate (pop0
, pop1
);
5333 result
= wi::add (pop0
, pop1
, SIGNED
, &overflow
);
5334 clamp_signed_saturation
:
5335 if (overflow
== wi::OVF_OVERFLOW
)
5336 result
= wi::max_value (GET_MODE_PRECISION (int_mode
), SIGNED
);
5337 else if (overflow
== wi::OVF_UNDERFLOW
)
5338 result
= wi::min_value (GET_MODE_PRECISION (int_mode
), SIGNED
);
5339 else if (overflow
!= wi::OVF_NONE
)
5344 result
= wi::add (pop0
, pop1
, UNSIGNED
, &overflow
);
5345 clamp_unsigned_saturation
:
5346 if (overflow
!= wi::OVF_NONE
)
5347 result
= wi::max_value (GET_MODE_PRECISION (int_mode
), UNSIGNED
);
5351 result
= wi::sub (pop0
, pop1
, SIGNED
, &overflow
);
5352 goto clamp_signed_saturation
;
5355 result
= wi::sub (pop0
, pop1
, UNSIGNED
, &overflow
);
5356 if (overflow
!= wi::OVF_NONE
)
5357 result
= wi::min_value (GET_MODE_PRECISION (int_mode
), UNSIGNED
);
5361 result
= wi::mul (pop0
, pop1
, SIGNED
, &overflow
);
5362 goto clamp_signed_saturation
;
5365 result
= wi::mul (pop0
, pop1
, UNSIGNED
, &overflow
);
5366 goto clamp_unsigned_saturation
;
5369 result
= wi::mul_high (pop0
, pop1
, SIGNED
);
5373 result
= wi::mul_high (pop0
, pop1
, UNSIGNED
);
5379 return immed_wide_int_const (result
, int_mode
);
5382 /* Handle polynomial integers. */
5383 if (NUM_POLY_INT_COEFFS
> 1
5384 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5385 && poly_int_rtx_p (op0
)
5386 && poly_int_rtx_p (op1
))
5388 poly_wide_int result
;
5392 result
= wi::to_poly_wide (op0
, mode
) + wi::to_poly_wide (op1
, mode
);
5396 result
= wi::to_poly_wide (op0
, mode
) - wi::to_poly_wide (op1
, mode
);
5400 if (CONST_SCALAR_INT_P (op1
))
5401 result
= wi::to_poly_wide (op0
, mode
) * rtx_mode_t (op1
, mode
);
5407 if (CONST_SCALAR_INT_P (op1
))
5411 GET_MODE (op1
) == VOIDmode
5412 && GET_MODE_PRECISION (int_mode
) < BITS_PER_WORD
5413 ? word_mode
: mode
);
5414 if (SHIFT_COUNT_TRUNCATED
)
5415 shift
= wi::umod_trunc (shift
, GET_MODE_PRECISION (int_mode
));
5416 else if (wi::geu_p (shift
, GET_MODE_PRECISION (int_mode
)))
5418 result
= wi::to_poly_wide (op0
, mode
) << shift
;
5425 if (!CONST_SCALAR_INT_P (op1
)
5426 || !can_ior_p (wi::to_poly_wide (op0
, mode
),
5427 rtx_mode_t (op1
, mode
), &result
))
5434 return immed_wide_int_const (result
, int_mode
);
5442 /* Return a positive integer if X should sort after Y. The value
5443 returned is 1 if and only if X and Y are both regs. */
5446 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
5450 result
= (commutative_operand_precedence (y
)
5451 - commutative_operand_precedence (x
));
5453 return result
+ result
;
5455 /* Group together equal REGs to do more simplification. */
5456 if (REG_P (x
) && REG_P (y
))
5457 return REGNO (x
) > REGNO (y
);
5462 /* Simplify and canonicalize a PLUS or MINUS, at least one of whose
5463 operands may be another PLUS or MINUS.
5465 Rather than test for specific case, we do this by a brute-force method
5466 and do all possible simplifications until no more changes occur. Then
5467 we rebuild the operation.
5469 May return NULL_RTX when no changes were made. */
5472 simplify_context::simplify_plus_minus (rtx_code code
, machine_mode mode
,
5475 struct simplify_plus_minus_op_data
5482 int changed
, n_constants
, canonicalized
= 0;
5485 memset (ops
, 0, sizeof ops
);
5487 /* Set up the two operands and then expand them until nothing has been
5488 changed. If we run out of room in our array, give up; this should
5489 almost never happen. */
5494 ops
[1].neg
= (code
== MINUS
);
5501 for (i
= 0; i
< n_ops
; i
++)
5503 rtx this_op
= ops
[i
].op
;
5504 int this_neg
= ops
[i
].neg
;
5505 enum rtx_code this_code
= GET_CODE (this_op
);
5511 if (n_ops
== ARRAY_SIZE (ops
))
5514 ops
[n_ops
].op
= XEXP (this_op
, 1);
5515 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
5518 ops
[i
].op
= XEXP (this_op
, 0);
5520 /* If this operand was negated then we will potentially
5521 canonicalize the expression. Similarly if we don't
5522 place the operands adjacent we're re-ordering the
5523 expression and thus might be performing a
5524 canonicalization. Ignore register re-ordering.
5525 ??? It might be better to shuffle the ops array here,
5526 but then (plus (plus (A, B), plus (C, D))) wouldn't
5527 be seen as non-canonical. */
5530 && !(REG_P (ops
[i
].op
) && REG_P (ops
[n_ops
- 1].op
))))
5535 ops
[i
].op
= XEXP (this_op
, 0);
5536 ops
[i
].neg
= ! this_neg
;
5542 if (n_ops
!= ARRAY_SIZE (ops
)
5543 && GET_CODE (XEXP (this_op
, 0)) == PLUS
5544 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
5545 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
5547 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
5548 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
5549 ops
[n_ops
].neg
= this_neg
;
5557 /* ~a -> (-a - 1) */
5558 if (n_ops
!= ARRAY_SIZE (ops
))
5560 ops
[n_ops
].op
= CONSTM1_RTX (mode
);
5561 ops
[n_ops
++].neg
= this_neg
;
5562 ops
[i
].op
= XEXP (this_op
, 0);
5563 ops
[i
].neg
= !this_neg
;
5569 CASE_CONST_SCALAR_INT
:
5570 case CONST_POLY_INT
:
5574 ops
[i
].op
= neg_poly_int_rtx (mode
, this_op
);
5588 if (n_constants
> 1)
5591 gcc_assert (n_ops
>= 2);
5593 /* If we only have two operands, we can avoid the loops. */
5596 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
5599 /* Get the two operands. Be careful with the order, especially for
5600 the cases where code == MINUS. */
5601 if (ops
[0].neg
&& ops
[1].neg
)
5603 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
5606 else if (ops
[0].neg
)
5617 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
5620 /* Now simplify each pair of operands until nothing changes. */
5623 /* Insertion sort is good enough for a small array. */
5624 for (i
= 1; i
< n_ops
; i
++)
5626 struct simplify_plus_minus_op_data save
;
5630 cmp
= simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
);
5633 /* Just swapping registers doesn't count as canonicalization. */
5639 ops
[j
+ 1] = ops
[j
];
5641 && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
) > 0);
5646 for (i
= n_ops
- 1; i
> 0; i
--)
5647 for (j
= i
- 1; j
>= 0; j
--)
5649 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
5650 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
5652 if (lhs
!= 0 && rhs
!= 0)
5654 enum rtx_code ncode
= PLUS
;
5660 std::swap (lhs
, rhs
);
5662 else if (swap_commutative_operands_p (lhs
, rhs
))
5663 std::swap (lhs
, rhs
);
5665 if ((GET_CODE (lhs
) == CONST
|| CONST_INT_P (lhs
))
5666 && (GET_CODE (rhs
) == CONST
|| CONST_INT_P (rhs
)))
5668 rtx tem_lhs
, tem_rhs
;
5670 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
5671 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
5672 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
,
5675 if (tem
&& !CONSTANT_P (tem
))
5676 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
5679 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
5683 /* Reject "simplifications" that just wrap the two
5684 arguments in a CONST. Failure to do so can result
5685 in infinite recursion with simplify_binary_operation
5686 when it calls us to simplify CONST operations.
5687 Also, if we find such a simplification, don't try
5688 any more combinations with this rhs: We must have
5689 something like symbol+offset, ie. one of the
5690 trivial CONST expressions we handle later. */
5691 if (GET_CODE (tem
) == CONST
5692 && GET_CODE (XEXP (tem
, 0)) == ncode
5693 && XEXP (XEXP (tem
, 0), 0) == lhs
5694 && XEXP (XEXP (tem
, 0), 1) == rhs
)
5697 if (GET_CODE (tem
) == NEG
)
5698 tem
= XEXP (tem
, 0), lneg
= !lneg
;
5699 if (poly_int_rtx_p (tem
) && lneg
)
5700 tem
= neg_poly_int_rtx (mode
, tem
), lneg
= 0;
5704 ops
[j
].op
= NULL_RTX
;
5714 /* Pack all the operands to the lower-numbered entries. */
5715 for (i
= 0, j
= 0; j
< n_ops
; j
++)
5724 /* If nothing changed, check that rematerialization of rtl instructions
5725 is still required. */
5728 /* Perform rematerialization if only all operands are registers and
5729 all operations are PLUS. */
5730 /* ??? Also disallow (non-global, non-frame) fixed registers to work
5731 around rs6000 and how it uses the CA register. See PR67145. */
5732 for (i
= 0; i
< n_ops
; i
++)
5734 || !REG_P (ops
[i
].op
)
5735 || (REGNO (ops
[i
].op
) < FIRST_PSEUDO_REGISTER
5736 && fixed_regs
[REGNO (ops
[i
].op
)]
5737 && !global_regs
[REGNO (ops
[i
].op
)]
5738 && ops
[i
].op
!= frame_pointer_rtx
5739 && ops
[i
].op
!= arg_pointer_rtx
5740 && ops
[i
].op
!= stack_pointer_rtx
))
5745 /* Create (minus -C X) instead of (neg (const (plus X C))). */
5747 && CONST_INT_P (ops
[1].op
)
5748 && CONSTANT_P (ops
[0].op
)
5750 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
5752 /* We suppressed creation of trivial CONST expressions in the
5753 combination loop to avoid recursion. Create one manually now.
5754 The combination loop should have ensured that there is exactly
5755 one CONST_INT, and the sort will have ensured that it is last
5756 in the array and that any other constant will be next-to-last. */
5759 && poly_int_rtx_p (ops
[n_ops
- 1].op
)
5760 && CONSTANT_P (ops
[n_ops
- 2].op
))
5762 rtx value
= ops
[n_ops
- 1].op
;
5763 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
5764 value
= neg_poly_int_rtx (mode
, value
);
5765 if (CONST_INT_P (value
))
5767 ops
[n_ops
- 2].op
= plus_constant (mode
, ops
[n_ops
- 2].op
,
5773 /* Put a non-negated operand first, if possible. */
5775 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
5778 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
5787 /* Now make the result by performing the requested operations. */
5790 for (i
= 1; i
< n_ops
; i
++)
5791 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
5792 mode
, result
, ops
[i
].op
);
5797 /* Check whether an operand is suitable for calling simplify_plus_minus. */
5799 plus_minus_operand_p (const_rtx x
)
5801 return GET_CODE (x
) == PLUS
5802 || GET_CODE (x
) == MINUS
5803 || (GET_CODE (x
) == CONST
5804 && GET_CODE (XEXP (x
, 0)) == PLUS
5805 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
5806 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
5809 /* Like simplify_binary_operation except used for relational operators.
5810 MODE is the mode of the result. If MODE is VOIDmode, both operands must
5811 not also be VOIDmode.
5813 CMP_MODE specifies in which mode the comparison is done in, so it is
5814 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
5815 the operands or, if both are VOIDmode, the operands are compared in
5816 "infinite precision". */
5818 simplify_context::simplify_relational_operation (rtx_code code
,
5820 machine_mode cmp_mode
,
5823 rtx tem
, trueop0
, trueop1
;
5825 if (cmp_mode
== VOIDmode
)
5826 cmp_mode
= GET_MODE (op0
);
5827 if (cmp_mode
== VOIDmode
)
5828 cmp_mode
= GET_MODE (op1
);
5830 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
5832 return relational_result (mode
, cmp_mode
, tem
);
5834 /* For the following tests, ensure const0_rtx is op1. */
5835 if (swap_commutative_operands_p (op0
, op1
)
5836 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
5837 std::swap (op0
, op1
), code
= swap_condition (code
);
5839 /* If op0 is a compare, extract the comparison arguments from it. */
5840 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
5841 return simplify_gen_relational (code
, mode
, VOIDmode
,
5842 XEXP (op0
, 0), XEXP (op0
, 1));
5844 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
)
5847 trueop0
= avoid_constant_pool_reference (op0
);
5848 trueop1
= avoid_constant_pool_reference (op1
);
5849 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
5853 /* This part of simplify_relational_operation is only used when CMP_MODE
5854 is not in class MODE_CC (i.e. it is a real comparison).
5856 MODE is the mode of the result, while CMP_MODE specifies in which
5857 mode the comparison is done in, so it is the mode of the operands. */
5860 simplify_context::simplify_relational_operation_1 (rtx_code code
,
5862 machine_mode cmp_mode
,
5865 enum rtx_code op0code
= GET_CODE (op0
);
5867 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
5869 /* If op0 is a comparison, extract the comparison arguments
5873 if (GET_MODE (op0
) == mode
)
5874 return simplify_rtx (op0
);
5876 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
5877 XEXP (op0
, 0), XEXP (op0
, 1));
5879 else if (code
== EQ
)
5881 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL
);
5882 if (new_code
!= UNKNOWN
)
5883 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
5884 XEXP (op0
, 0), XEXP (op0
, 1));
5888 /* (LTU/GEU (PLUS a C) C), where C is constant, can be simplified to
5889 (GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
5890 if ((code
== LTU
|| code
== GEU
)
5891 && GET_CODE (op0
) == PLUS
5892 && CONST_INT_P (XEXP (op0
, 1))
5893 && (rtx_equal_p (op1
, XEXP (op0
, 0))
5894 || rtx_equal_p (op1
, XEXP (op0
, 1)))
5895 /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
5896 && XEXP (op0
, 1) != const0_rtx
)
5899 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5900 return simplify_gen_relational ((code
== LTU
? GEU
: LTU
), mode
,
5901 cmp_mode
, XEXP (op0
, 0), new_cmp
);
5904 /* (GTU (PLUS a C) (C - 1)) where C is a non-zero constant can be
5905 transformed into (LTU a -C). */
5906 if (code
== GTU
&& GET_CODE (op0
) == PLUS
&& CONST_INT_P (op1
)
5907 && CONST_INT_P (XEXP (op0
, 1))
5908 && (UINTVAL (op1
) == UINTVAL (XEXP (op0
, 1)) - 1)
5909 && XEXP (op0
, 1) != const0_rtx
)
5912 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
5913 return simplify_gen_relational (LTU
, mode
, cmp_mode
,
5914 XEXP (op0
, 0), new_cmp
);
5917 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
5918 if ((code
== LTU
|| code
== GEU
)
5919 && GET_CODE (op0
) == PLUS
5920 && rtx_equal_p (op1
, XEXP (op0
, 1))
5921 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
5922 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
5923 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
,
5924 copy_rtx (XEXP (op0
, 0)));
5926 if (op1
== const0_rtx
)
5928 /* Canonicalize (GTU x 0) as (NE x 0). */
5930 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
5931 /* Canonicalize (LEU x 0) as (EQ x 0). */
5933 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
5935 else if (op1
== const1_rtx
)
5940 /* Canonicalize (GE x 1) as (GT x 0). */
5941 return simplify_gen_relational (GT
, mode
, cmp_mode
,
5944 /* Canonicalize (GEU x 1) as (NE x 0). */
5945 return simplify_gen_relational (NE
, mode
, cmp_mode
,
5948 /* Canonicalize (LT x 1) as (LE x 0). */
5949 return simplify_gen_relational (LE
, mode
, cmp_mode
,
5952 /* Canonicalize (LTU x 1) as (EQ x 0). */
5953 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
5959 else if (op1
== constm1_rtx
)
5961 /* Canonicalize (LE x -1) as (LT x 0). */
5963 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
5964 /* Canonicalize (GT x -1) as (GE x 0). */
5966 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
5969 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
5970 if ((code
== EQ
|| code
== NE
)
5971 && (op0code
== PLUS
|| op0code
== MINUS
)
5973 && CONSTANT_P (XEXP (op0
, 1))
5974 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
5976 rtx x
= XEXP (op0
, 0);
5977 rtx c
= XEXP (op0
, 1);
5978 enum rtx_code invcode
= op0code
== PLUS
? MINUS
: PLUS
;
5979 rtx tem
= simplify_gen_binary (invcode
, cmp_mode
, op1
, c
);
5981 /* Detect an infinite recursive condition, where we oscillate at this
5982 simplification case between:
5983 A + B == C <---> C - B == A,
5984 where A, B, and C are all constants with non-simplifiable expressions,
5985 usually SYMBOL_REFs. */
5986 if (GET_CODE (tem
) == invcode
5988 && rtx_equal_p (c
, XEXP (tem
, 1)))
5991 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, tem
);
5994 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
5995 the same as (zero_extract:SI FOO (const_int 1) BAR). */
5996 scalar_int_mode int_mode
, int_cmp_mode
;
5998 && op1
== const0_rtx
5999 && is_int_mode (mode
, &int_mode
)
6000 && is_a
<scalar_int_mode
> (cmp_mode
, &int_cmp_mode
)
6001 /* ??? Work-around BImode bugs in the ia64 backend. */
6002 && int_mode
!= BImode
6003 && int_cmp_mode
!= BImode
6004 && nonzero_bits (op0
, int_cmp_mode
) == 1
6005 && STORE_FLAG_VALUE
== 1)
6006 return GET_MODE_SIZE (int_mode
) > GET_MODE_SIZE (int_cmp_mode
)
6007 ? simplify_gen_unary (ZERO_EXTEND
, int_mode
, op0
, int_cmp_mode
)
6008 : lowpart_subreg (int_mode
, op0
, int_cmp_mode
);
6010 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
6011 if ((code
== EQ
|| code
== NE
)
6012 && op1
== const0_rtx
6014 return simplify_gen_relational (code
, mode
, cmp_mode
,
6015 XEXP (op0
, 0), XEXP (op0
, 1));
6017 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
6018 if ((code
== EQ
|| code
== NE
)
6020 && rtx_equal_p (XEXP (op0
, 0), op1
)
6021 && !side_effects_p (XEXP (op0
, 0)))
6022 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 1),
6025 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
6026 if ((code
== EQ
|| code
== NE
)
6028 && rtx_equal_p (XEXP (op0
, 1), op1
)
6029 && !side_effects_p (XEXP (op0
, 1)))
6030 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
6033 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
6034 if ((code
== EQ
|| code
== NE
)
6036 && CONST_SCALAR_INT_P (op1
)
6037 && CONST_SCALAR_INT_P (XEXP (op0
, 1)))
6038 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
6039 simplify_gen_binary (XOR
, cmp_mode
,
6040 XEXP (op0
, 1), op1
));
6042 /* Simplify eq/ne (and/ior x y) x/y) for targets with a BICS instruction or
6043 constant folding if x/y is a constant. */
6044 if ((code
== EQ
|| code
== NE
)
6045 && (op0code
== AND
|| op0code
== IOR
)
6046 && !side_effects_p (op1
)
6047 && op1
!= CONST0_RTX (cmp_mode
))
6049 /* Both (eq/ne (and x y) x) and (eq/ne (ior x y) y) simplify to
6050 (eq/ne (and (not y) x) 0). */
6051 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 0), op1
))
6052 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 1), op1
)))
6054 rtx not_y
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 1),
6056 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_y
, XEXP (op0
, 0));
6058 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
6059 CONST0_RTX (cmp_mode
));
6062 /* Both (eq/ne (and x y) y) and (eq/ne (ior x y) x) simplify to
6063 (eq/ne (and (not x) y) 0). */
6064 if ((op0code
== AND
&& rtx_equal_p (XEXP (op0
, 1), op1
))
6065 || (op0code
== IOR
&& rtx_equal_p (XEXP (op0
, 0), op1
)))
6067 rtx not_x
= simplify_gen_unary (NOT
, cmp_mode
, XEXP (op0
, 0),
6069 rtx lhs
= simplify_gen_binary (AND
, cmp_mode
, not_x
, XEXP (op0
, 1));
6071 return simplify_gen_relational (code
, mode
, cmp_mode
, lhs
,
6072 CONST0_RTX (cmp_mode
));
6076 /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */
6077 if ((code
== EQ
|| code
== NE
)
6078 && GET_CODE (op0
) == BSWAP
6079 && CONST_SCALAR_INT_P (op1
))
6080 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
6081 simplify_gen_unary (BSWAP
, cmp_mode
,
6084 /* (eq/ne (bswap x) (bswap y)) simplifies to (eq/ne x y). */
6085 if ((code
== EQ
|| code
== NE
)
6086 && GET_CODE (op0
) == BSWAP
6087 && GET_CODE (op1
) == BSWAP
)
6088 return simplify_gen_relational (code
, mode
, cmp_mode
,
6089 XEXP (op0
, 0), XEXP (op1
, 0));
6091 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
6097 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
6098 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
6099 XEXP (op0
, 0), const0_rtx
);
6104 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
6105 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
6106 XEXP (op0
, 0), const0_rtx
);
6125 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
6126 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
6127 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
6128 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
6129 For floating-point comparisons, assume that the operands were ordered. */
6132 comparison_result (enum rtx_code code
, int known_results
)
6138 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
6141 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
6145 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
6148 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
6152 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
6155 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
6158 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
6160 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
6163 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
6165 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
6168 return const_true_rtx
;
6176 /* Check if the given comparison (done in the given MODE) is actually
6177 a tautology or a contradiction. If the mode is VOIDmode, the
6178 comparison is done in "infinite precision". If no simplification
6179 is possible, this function returns zero. Otherwise, it returns
6180 either const_true_rtx or const0_rtx. */
6183 simplify_const_relational_operation (enum rtx_code code
,
6191 gcc_assert (mode
!= VOIDmode
6192 || (GET_MODE (op0
) == VOIDmode
6193 && GET_MODE (op1
) == VOIDmode
));
6195 /* We only handle MODE_CC comparisons that are COMPARE against zero. */
6196 if (GET_MODE_CLASS (mode
) == MODE_CC
6197 && (op1
!= const0_rtx
6198 || GET_CODE (op0
) != COMPARE
))
6201 /* If op0 is a compare, extract the comparison arguments from it. */
6202 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6204 op1
= XEXP (op0
, 1);
6205 op0
= XEXP (op0
, 0);
6207 if (GET_MODE (op0
) != VOIDmode
)
6208 mode
= GET_MODE (op0
);
6209 else if (GET_MODE (op1
) != VOIDmode
)
6210 mode
= GET_MODE (op1
);
6215 /* We can't simplify MODE_CC values since we don't know what the
6216 actual comparison is. */
6217 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6220 /* Make sure the constant is second. */
6221 if (swap_commutative_operands_p (op0
, op1
))
6223 std::swap (op0
, op1
);
6224 code
= swap_condition (code
);
6227 trueop0
= avoid_constant_pool_reference (op0
);
6228 trueop1
= avoid_constant_pool_reference (op1
);
6230 /* For integer comparisons of A and B maybe we can simplify A - B and can
6231 then simplify a comparison of that with zero. If A and B are both either
6232 a register or a CONST_INT, this can't help; testing for these cases will
6233 prevent infinite recursion here and speed things up.
6235 We can only do this for EQ and NE comparisons as otherwise we may
6236 lose or introduce overflow which we cannot disregard as undefined as
6237 we do not know the signedness of the operation on either the left or
6238 the right hand side of the comparison. */
6240 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
6241 && (code
== EQ
|| code
== NE
)
6242 && ! ((REG_P (op0
) || CONST_INT_P (trueop0
))
6243 && (REG_P (op1
) || CONST_INT_P (trueop1
)))
6244 && (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
)) != 0
6245 /* We cannot do this if tem is a nonzero address. */
6246 && ! nonzero_address_p (tem
))
6247 return simplify_const_relational_operation (signed_condition (code
),
6248 mode
, tem
, const0_rtx
);
6250 if (! HONOR_NANS (mode
) && code
== ORDERED
)
6251 return const_true_rtx
;
6253 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
6256 /* For modes without NaNs, if the two operands are equal, we know the
6257 result except if they have side-effects. Even with NaNs we know
6258 the result of unordered comparisons and, if signaling NaNs are
6259 irrelevant, also the result of LT/GT/LTGT. */
6260 if ((! HONOR_NANS (trueop0
)
6261 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
6262 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
6263 && ! HONOR_SNANS (trueop0
)))
6264 && rtx_equal_p (trueop0
, trueop1
)
6265 && ! side_effects_p (trueop0
))
6266 return comparison_result (code
, CMP_EQ
);
6268 /* If the operands are floating-point constants, see if we can fold
6270 if (CONST_DOUBLE_AS_FLOAT_P (trueop0
)
6271 && CONST_DOUBLE_AS_FLOAT_P (trueop1
)
6272 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
6274 const REAL_VALUE_TYPE
*d0
= CONST_DOUBLE_REAL_VALUE (trueop0
);
6275 const REAL_VALUE_TYPE
*d1
= CONST_DOUBLE_REAL_VALUE (trueop1
);
6277 /* Comparisons are unordered iff at least one of the values is NaN. */
6278 if (REAL_VALUE_ISNAN (*d0
) || REAL_VALUE_ISNAN (*d1
))
6288 return const_true_rtx
;
6301 return comparison_result (code
,
6302 (real_equal (d0
, d1
) ? CMP_EQ
:
6303 real_less (d0
, d1
) ? CMP_LT
: CMP_GT
));
6306 /* Otherwise, see if the operands are both integers. */
6307 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
6308 && CONST_SCALAR_INT_P (trueop0
) && CONST_SCALAR_INT_P (trueop1
))
6310 /* It would be nice if we really had a mode here. However, the
6311 largest int representable on the target is as good as
6313 machine_mode cmode
= (mode
== VOIDmode
) ? MAX_MODE_INT
: mode
;
6314 rtx_mode_t ptrueop0
= rtx_mode_t (trueop0
, cmode
);
6315 rtx_mode_t ptrueop1
= rtx_mode_t (trueop1
, cmode
);
6317 if (wi::eq_p (ptrueop0
, ptrueop1
))
6318 return comparison_result (code
, CMP_EQ
);
6321 int cr
= wi::lts_p (ptrueop0
, ptrueop1
) ? CMP_LT
: CMP_GT
;
6322 cr
|= wi::ltu_p (ptrueop0
, ptrueop1
) ? CMP_LTU
: CMP_GTU
;
6323 return comparison_result (code
, cr
);
6327 /* Optimize comparisons with upper and lower bounds. */
6328 scalar_int_mode int_mode
;
6329 if (CONST_INT_P (trueop1
)
6330 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6331 && HWI_COMPUTABLE_MODE_P (int_mode
)
6332 && !side_effects_p (trueop0
))
6335 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, int_mode
);
6336 HOST_WIDE_INT val
= INTVAL (trueop1
);
6337 HOST_WIDE_INT mmin
, mmax
;
6347 /* Get a reduced range if the sign bit is zero. */
6348 if (nonzero
<= (GET_MODE_MASK (int_mode
) >> 1))
6355 rtx mmin_rtx
, mmax_rtx
;
6356 get_mode_bounds (int_mode
, sign
, int_mode
, &mmin_rtx
, &mmax_rtx
);
6358 mmin
= INTVAL (mmin_rtx
);
6359 mmax
= INTVAL (mmax_rtx
);
6362 unsigned int sign_copies
6363 = num_sign_bit_copies (trueop0
, int_mode
);
6365 mmin
>>= (sign_copies
- 1);
6366 mmax
>>= (sign_copies
- 1);
6372 /* x >= y is always true for y <= mmin, always false for y > mmax. */
6374 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
6375 return const_true_rtx
;
6376 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
6381 return const_true_rtx
;
6386 /* x <= y is always true for y >= mmax, always false for y < mmin. */
6388 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
6389 return const_true_rtx
;
6390 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
6395 return const_true_rtx
;
6401 /* x == y is always false for y out of range. */
6402 if (val
< mmin
|| val
> mmax
)
6406 /* x > y is always false for y >= mmax, always true for y < mmin. */
6408 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
6410 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
6411 return const_true_rtx
;
6417 return const_true_rtx
;
6420 /* x < y is always false for y <= mmin, always true for y > mmax. */
6422 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
6424 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
6425 return const_true_rtx
;
6431 return const_true_rtx
;
6435 /* x != y is always true for y out of range. */
6436 if (val
< mmin
|| val
> mmax
)
6437 return const_true_rtx
;
6445 /* Optimize integer comparisons with zero. */
6446 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6447 && trueop1
== const0_rtx
6448 && !side_effects_p (trueop0
))
6450 /* Some addresses are known to be nonzero. We don't know
6451 their sign, but equality comparisons are known. */
6452 if (nonzero_address_p (trueop0
))
6454 if (code
== EQ
|| code
== LEU
)
6456 if (code
== NE
|| code
== GTU
)
6457 return const_true_rtx
;
6460 /* See if the first operand is an IOR with a constant. If so, we
6461 may be able to determine the result of this comparison. */
6462 if (GET_CODE (op0
) == IOR
)
6464 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
6465 if (CONST_INT_P (inner_const
) && inner_const
!= const0_rtx
)
6467 int sign_bitnum
= GET_MODE_PRECISION (int_mode
) - 1;
6468 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
6469 && (UINTVAL (inner_const
)
6480 return const_true_rtx
;
6484 return const_true_rtx
;
6498 /* Optimize comparison of ABS with zero. */
6499 if (trueop1
== CONST0_RTX (mode
) && !side_effects_p (trueop0
)
6500 && (GET_CODE (trueop0
) == ABS
6501 || (GET_CODE (trueop0
) == FLOAT_EXTEND
6502 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
6507 /* Optimize abs(x) < 0.0. */
6508 if (!INTEGRAL_MODE_P (mode
) && !HONOR_SNANS (mode
))
6513 /* Optimize abs(x) >= 0.0. */
6514 if (!INTEGRAL_MODE_P (mode
) && !HONOR_NANS (mode
))
6515 return const_true_rtx
;
6519 /* Optimize ! (abs(x) < 0.0). */
6520 return const_true_rtx
;
6530 /* Recognize expressions of the form (X CMP 0) ? VAL : OP (X)
6531 where OP is CLZ or CTZ and VAL is the value from CLZ_DEFINED_VALUE_AT_ZERO
6532 or CTZ_DEFINED_VALUE_AT_ZERO respectively and return OP (X) if the expression
6533 can be simplified to that or NULL_RTX if not.
6534 Assume X is compared against zero with CMP_CODE and the true
6535 arm is TRUE_VAL and the false arm is FALSE_VAL. */
6538 simplify_context::simplify_cond_clz_ctz (rtx x
, rtx_code cmp_code
,
6539 rtx true_val
, rtx false_val
)
6541 if (cmp_code
!= EQ
&& cmp_code
!= NE
)
6544 /* Result on X == 0 and X !=0 respectively. */
6545 rtx on_zero
, on_nonzero
;
6549 on_nonzero
= false_val
;
6553 on_zero
= false_val
;
6554 on_nonzero
= true_val
;
6557 rtx_code op_code
= GET_CODE (on_nonzero
);
6558 if ((op_code
!= CLZ
&& op_code
!= CTZ
)
6559 || !rtx_equal_p (XEXP (on_nonzero
, 0), x
)
6560 || !CONST_INT_P (on_zero
))
6563 HOST_WIDE_INT op_val
;
6564 scalar_int_mode mode ATTRIBUTE_UNUSED
6565 = as_a
<scalar_int_mode
> (GET_MODE (XEXP (on_nonzero
, 0)));
6566 if (((op_code
== CLZ
&& CLZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
))
6567 || (op_code
== CTZ
&& CTZ_DEFINED_VALUE_AT_ZERO (mode
, op_val
)))
6568 && op_val
== INTVAL (on_zero
))
6574 /* Try to simplify X given that it appears within operand OP of a
6575 VEC_MERGE operation whose mask is MASK. X need not use the same
6576 vector mode as the VEC_MERGE, but it must have the same number of
6579 Return the simplified X on success, otherwise return NULL_RTX. */
6582 simplify_context::simplify_merge_mask (rtx x
, rtx mask
, int op
)
6584 gcc_assert (VECTOR_MODE_P (GET_MODE (x
)));
6585 poly_uint64 nunits
= GET_MODE_NUNITS (GET_MODE (x
));
6586 if (GET_CODE (x
) == VEC_MERGE
&& rtx_equal_p (XEXP (x
, 2), mask
))
6588 if (side_effects_p (XEXP (x
, 1 - op
)))
6591 return XEXP (x
, op
);
6594 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6595 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
))
6597 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6599 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), top0
,
6600 GET_MODE (XEXP (x
, 0)));
6603 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6604 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
6605 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
6606 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
))
6608 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6609 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
6612 if (COMPARISON_P (x
))
6613 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
6614 GET_MODE (XEXP (x
, 0)) != VOIDmode
6615 ? GET_MODE (XEXP (x
, 0))
6616 : GET_MODE (XEXP (x
, 1)),
6617 top0
? top0
: XEXP (x
, 0),
6618 top1
? top1
: XEXP (x
, 1));
6620 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
6621 top0
? top0
: XEXP (x
, 0),
6622 top1
? top1
: XEXP (x
, 1));
6625 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_TERNARY
6626 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 0)))
6627 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))), nunits
)
6628 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 1)))
6629 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 1))), nunits
)
6630 && VECTOR_MODE_P (GET_MODE (XEXP (x
, 2)))
6631 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (x
, 2))), nunits
))
6633 rtx top0
= simplify_merge_mask (XEXP (x
, 0), mask
, op
);
6634 rtx top1
= simplify_merge_mask (XEXP (x
, 1), mask
, op
);
6635 rtx top2
= simplify_merge_mask (XEXP (x
, 2), mask
, op
);
6636 if (top0
|| top1
|| top2
)
6637 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
6638 GET_MODE (XEXP (x
, 0)),
6639 top0
? top0
: XEXP (x
, 0),
6640 top1
? top1
: XEXP (x
, 1),
6641 top2
? top2
: XEXP (x
, 2));
6647 /* Simplify CODE, an operation with result mode MODE and three operands,
6648 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
6649 a constant. Return 0 if no simplifications is possible. */
6652 simplify_context::simplify_ternary_operation (rtx_code code
, machine_mode mode
,
6653 machine_mode op0_mode
,
6654 rtx op0
, rtx op1
, rtx op2
)
6656 bool any_change
= false;
6658 scalar_int_mode int_mode
, int_op0_mode
;
6659 unsigned int n_elts
;
6664 /* Simplify negations around the multiplication. */
6665 /* -a * -b + c => a * b + c. */
6666 if (GET_CODE (op0
) == NEG
)
6668 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
6670 op1
= tem
, op0
= XEXP (op0
, 0), any_change
= true;
6672 else if (GET_CODE (op1
) == NEG
)
6674 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
6676 op0
= tem
, op1
= XEXP (op1
, 0), any_change
= true;
6679 /* Canonicalize the two multiplication operands. */
6680 /* a * -b + c => -b * a + c. */
6681 if (swap_commutative_operands_p (op0
, op1
))
6682 std::swap (op0
, op1
), any_change
= true;
6685 return gen_rtx_FMA (mode
, op0
, op1
, op2
);
6690 if (CONST_INT_P (op0
)
6691 && CONST_INT_P (op1
)
6692 && CONST_INT_P (op2
)
6693 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6694 && INTVAL (op1
) + INTVAL (op2
) <= GET_MODE_PRECISION (int_mode
)
6695 && HWI_COMPUTABLE_MODE_P (int_mode
))
6697 /* Extracting a bit-field from a constant */
6698 unsigned HOST_WIDE_INT val
= UINTVAL (op0
);
6699 HOST_WIDE_INT op1val
= INTVAL (op1
);
6700 HOST_WIDE_INT op2val
= INTVAL (op2
);
6701 if (!BITS_BIG_ENDIAN
)
6703 else if (is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
))
6704 val
>>= GET_MODE_PRECISION (int_op0_mode
) - op2val
- op1val
;
6706 /* Not enough information to calculate the bit position. */
6709 if (HOST_BITS_PER_WIDE_INT
!= op1val
)
6711 /* First zero-extend. */
6712 val
&= (HOST_WIDE_INT_1U
<< op1val
) - 1;
6713 /* If desired, propagate sign bit. */
6714 if (code
== SIGN_EXTRACT
6715 && (val
& (HOST_WIDE_INT_1U
<< (op1val
- 1)))
6717 val
|= ~ ((HOST_WIDE_INT_1U
<< op1val
) - 1);
6720 return gen_int_mode (val
, int_mode
);
6725 if (CONST_INT_P (op0
))
6726 return op0
!= const0_rtx
? op1
: op2
;
6728 /* Convert c ? a : a into "a". */
6729 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
6732 /* Convert a != b ? a : b into "a". */
6733 if (GET_CODE (op0
) == NE
6734 && ! side_effects_p (op0
)
6735 && ! HONOR_NANS (mode
)
6736 && ! HONOR_SIGNED_ZEROS (mode
)
6737 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6738 && rtx_equal_p (XEXP (op0
, 1), op2
))
6739 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6740 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6743 /* Convert a == b ? a : b into "b". */
6744 if (GET_CODE (op0
) == EQ
6745 && ! side_effects_p (op0
)
6746 && ! HONOR_NANS (mode
)
6747 && ! HONOR_SIGNED_ZEROS (mode
)
6748 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
6749 && rtx_equal_p (XEXP (op0
, 1), op2
))
6750 || (rtx_equal_p (XEXP (op0
, 0), op2
)
6751 && rtx_equal_p (XEXP (op0
, 1), op1
))))
6754 /* Convert (!c) != {0,...,0} ? a : b into
6755 c != {0,...,0} ? b : a for vector modes. */
6756 if (VECTOR_MODE_P (GET_MODE (op1
))
6757 && GET_CODE (op0
) == NE
6758 && GET_CODE (XEXP (op0
, 0)) == NOT
6759 && GET_CODE (XEXP (op0
, 1)) == CONST_VECTOR
)
6761 rtx cv
= XEXP (op0
, 1);
6764 if (!CONST_VECTOR_NUNITS (cv
).is_constant (&nunits
))
6767 for (int i
= 0; i
< nunits
; ++i
)
6768 if (CONST_VECTOR_ELT (cv
, i
) != const0_rtx
)
6775 rtx new_op0
= gen_rtx_NE (GET_MODE (op0
),
6776 XEXP (XEXP (op0
, 0), 0),
6778 rtx retval
= gen_rtx_IF_THEN_ELSE (mode
, new_op0
, op2
, op1
);
6783 /* Convert x == 0 ? N : clz (x) into clz (x) when
6784 CLZ_DEFINED_VALUE_AT_ZERO is defined to N for the mode of x.
6785 Similarly for ctz (x). */
6786 if (COMPARISON_P (op0
) && !side_effects_p (op0
)
6787 && XEXP (op0
, 1) == const0_rtx
)
6790 = simplify_cond_clz_ctz (XEXP (op0
, 0), GET_CODE (op0
),
6796 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
6798 machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
6799 ? GET_MODE (XEXP (op0
, 1))
6800 : GET_MODE (XEXP (op0
, 0)));
6803 /* Look for happy constants in op1 and op2. */
6804 if (CONST_INT_P (op1
) && CONST_INT_P (op2
))
6806 HOST_WIDE_INT t
= INTVAL (op1
);
6807 HOST_WIDE_INT f
= INTVAL (op2
);
6809 if (t
== STORE_FLAG_VALUE
&& f
== 0)
6810 code
= GET_CODE (op0
);
6811 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
6814 tmp
= reversed_comparison_code (op0
, NULL
);
6822 return simplify_gen_relational (code
, mode
, cmp_mode
,
6823 XEXP (op0
, 0), XEXP (op0
, 1));
6826 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
6827 cmp_mode
, XEXP (op0
, 0),
6830 /* See if any simplifications were possible. */
6833 if (CONST_INT_P (temp
))
6834 return temp
== const0_rtx
? op2
: op1
;
6836 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
6842 gcc_assert (GET_MODE (op0
) == mode
);
6843 gcc_assert (GET_MODE (op1
) == mode
);
6844 gcc_assert (VECTOR_MODE_P (mode
));
6845 trueop2
= avoid_constant_pool_reference (op2
);
6846 if (CONST_INT_P (trueop2
)
6847 && GET_MODE_NUNITS (mode
).is_constant (&n_elts
))
6849 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop2
);
6850 unsigned HOST_WIDE_INT mask
;
6851 if (n_elts
== HOST_BITS_PER_WIDE_INT
)
6854 mask
= (HOST_WIDE_INT_1U
<< n_elts
) - 1;
6856 if (!(sel
& mask
) && !side_effects_p (op0
))
6858 if ((sel
& mask
) == mask
&& !side_effects_p (op1
))
6861 rtx trueop0
= avoid_constant_pool_reference (op0
);
6862 rtx trueop1
= avoid_constant_pool_reference (op1
);
6863 if (GET_CODE (trueop0
) == CONST_VECTOR
6864 && GET_CODE (trueop1
) == CONST_VECTOR
)
6866 rtvec v
= rtvec_alloc (n_elts
);
6869 for (i
= 0; i
< n_elts
; i
++)
6870 RTVEC_ELT (v
, i
) = ((sel
& (HOST_WIDE_INT_1U
<< i
))
6871 ? CONST_VECTOR_ELT (trueop0
, i
)
6872 : CONST_VECTOR_ELT (trueop1
, i
));
6873 return gen_rtx_CONST_VECTOR (mode
, v
);
6876 /* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
6877 if no element from a appears in the result. */
6878 if (GET_CODE (op0
) == VEC_MERGE
)
6880 tem
= avoid_constant_pool_reference (XEXP (op0
, 2));
6881 if (CONST_INT_P (tem
))
6883 unsigned HOST_WIDE_INT sel0
= UINTVAL (tem
);
6884 if (!(sel
& sel0
& mask
) && !side_effects_p (XEXP (op0
, 0)))
6885 return simplify_gen_ternary (code
, mode
, mode
,
6886 XEXP (op0
, 1), op1
, op2
);
6887 if (!(sel
& ~sel0
& mask
) && !side_effects_p (XEXP (op0
, 1)))
6888 return simplify_gen_ternary (code
, mode
, mode
,
6889 XEXP (op0
, 0), op1
, op2
);
6892 if (GET_CODE (op1
) == VEC_MERGE
)
6894 tem
= avoid_constant_pool_reference (XEXP (op1
, 2));
6895 if (CONST_INT_P (tem
))
6897 unsigned HOST_WIDE_INT sel1
= UINTVAL (tem
);
6898 if (!(~sel
& sel1
& mask
) && !side_effects_p (XEXP (op1
, 0)))
6899 return simplify_gen_ternary (code
, mode
, mode
,
6900 op0
, XEXP (op1
, 1), op2
);
6901 if (!(~sel
& ~sel1
& mask
) && !side_effects_p (XEXP (op1
, 1)))
6902 return simplify_gen_ternary (code
, mode
, mode
,
6903 op0
, XEXP (op1
, 0), op2
);
6907 /* Replace (vec_merge (vec_duplicate (vec_select a parallel (i))) a 1 << i)
6909 if (GET_CODE (op0
) == VEC_DUPLICATE
6910 && GET_CODE (XEXP (op0
, 0)) == VEC_SELECT
6911 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == PARALLEL
6912 && known_eq (GET_MODE_NUNITS (GET_MODE (XEXP (op0
, 0))), 1))
6914 tem
= XVECEXP ((XEXP (XEXP (op0
, 0), 1)), 0, 0);
6915 if (CONST_INT_P (tem
) && CONST_INT_P (op2
))
6917 if (XEXP (XEXP (op0
, 0), 0) == op1
6918 && UINTVAL (op2
) == HOST_WIDE_INT_1U
<< UINTVAL (tem
))
6922 /* Replace (vec_merge (vec_duplicate (X)) (const_vector [A, B])
6924 with (vec_concat (X) (B)) if N == 1 or
6925 (vec_concat (A) (X)) if N == 2. */
6926 if (GET_CODE (op0
) == VEC_DUPLICATE
6927 && GET_CODE (op1
) == CONST_VECTOR
6928 && known_eq (CONST_VECTOR_NUNITS (op1
), 2)
6929 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6930 && IN_RANGE (sel
, 1, 2))
6932 rtx newop0
= XEXP (op0
, 0);
6933 rtx newop1
= CONST_VECTOR_ELT (op1
, 2 - sel
);
6935 std::swap (newop0
, newop1
);
6936 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6938 /* Replace (vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
6939 with (vec_concat x z) if N == 1, or (vec_concat y x) if N == 2.
6940 Only applies for vectors of two elements. */
6941 if (GET_CODE (op0
) == VEC_DUPLICATE
6942 && GET_CODE (op1
) == VEC_CONCAT
6943 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6944 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6945 && IN_RANGE (sel
, 1, 2))
6947 rtx newop0
= XEXP (op0
, 0);
6948 rtx newop1
= XEXP (op1
, 2 - sel
);
6949 rtx otherop
= XEXP (op1
, sel
- 1);
6951 std::swap (newop0
, newop1
);
6952 /* Don't want to throw away the other part of the vec_concat if
6953 it has side-effects. */
6954 if (!side_effects_p (otherop
))
6955 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6960 (vec_merge:outer (vec_duplicate:outer x:inner)
6961 (subreg:outer y:inner 0)
6964 with (vec_concat:outer x:inner y:inner) if N == 1,
6965 or (vec_concat:outer y:inner x:inner) if N == 2.
6967 Implicitly, this means we have a paradoxical subreg, but such
6968 a check is cheap, so make it anyway.
6970 Only applies for vectors of two elements. */
6971 if (GET_CODE (op0
) == VEC_DUPLICATE
6972 && GET_CODE (op1
) == SUBREG
6973 && GET_MODE (op1
) == GET_MODE (op0
)
6974 && GET_MODE (SUBREG_REG (op1
)) == GET_MODE (XEXP (op0
, 0))
6975 && paradoxical_subreg_p (op1
)
6976 && subreg_lowpart_p (op1
)
6977 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
6978 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
6979 && IN_RANGE (sel
, 1, 2))
6981 rtx newop0
= XEXP (op0
, 0);
6982 rtx newop1
= SUBREG_REG (op1
);
6984 std::swap (newop0
, newop1
);
6985 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
6988 /* Same as above but with switched operands:
6989 Replace (vec_merge:outer (subreg:outer x:inner 0)
6990 (vec_duplicate:outer y:inner)
6993 with (vec_concat:outer x:inner y:inner) if N == 1,
6994 or (vec_concat:outer y:inner x:inner) if N == 2. */
6995 if (GET_CODE (op1
) == VEC_DUPLICATE
6996 && GET_CODE (op0
) == SUBREG
6997 && GET_MODE (op0
) == GET_MODE (op1
)
6998 && GET_MODE (SUBREG_REG (op0
)) == GET_MODE (XEXP (op1
, 0))
6999 && paradoxical_subreg_p (op0
)
7000 && subreg_lowpart_p (op0
)
7001 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
7002 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
7003 && IN_RANGE (sel
, 1, 2))
7005 rtx newop0
= SUBREG_REG (op0
);
7006 rtx newop1
= XEXP (op1
, 0);
7008 std::swap (newop0
, newop1
);
7009 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
7012 /* Replace (vec_merge (vec_duplicate x) (vec_duplicate y)
7014 with (vec_concat x y) or (vec_concat y x) depending on value
7016 if (GET_CODE (op0
) == VEC_DUPLICATE
7017 && GET_CODE (op1
) == VEC_DUPLICATE
7018 && known_eq (GET_MODE_NUNITS (GET_MODE (op0
)), 2)
7019 && known_eq (GET_MODE_NUNITS (GET_MODE (op1
)), 2)
7020 && IN_RANGE (sel
, 1, 2))
7022 rtx newop0
= XEXP (op0
, 0);
7023 rtx newop1
= XEXP (op1
, 0);
7025 std::swap (newop0
, newop1
);
7027 return simplify_gen_binary (VEC_CONCAT
, mode
, newop0
, newop1
);
7031 if (rtx_equal_p (op0
, op1
)
7032 && !side_effects_p (op2
) && !side_effects_p (op1
))
7035 if (!side_effects_p (op2
))
7038 = may_trap_p (op0
) ? NULL_RTX
: simplify_merge_mask (op0
, op2
, 0);
7040 = may_trap_p (op1
) ? NULL_RTX
: simplify_merge_mask (op1
, op2
, 1);
7042 return simplify_gen_ternary (code
, mode
, mode
,
7044 top1
? top1
: op1
, op2
);
7056 /* Try to calculate NUM_BYTES bytes of the target memory image of X,
7057 starting at byte FIRST_BYTE. Return true on success and add the
7058 bytes to BYTES, such that each byte has BITS_PER_UNIT bits and such
7059 that the bytes follow target memory order. Leave BYTES unmodified
7062 MODE is the mode of X. The caller must reserve NUM_BYTES bytes in
7063 BYTES before calling this function. */
7066 native_encode_rtx (machine_mode mode
, rtx x
, vec
<target_unit
> &bytes
,
7067 unsigned int first_byte
, unsigned int num_bytes
)
7069 /* Check the mode is sensible. */
7070 gcc_assert (GET_MODE (x
) == VOIDmode
7071 ? is_a
<scalar_int_mode
> (mode
)
7072 : mode
== GET_MODE (x
));
7074 if (GET_CODE (x
) == CONST_VECTOR
)
7076 /* CONST_VECTOR_ELT follows target memory order, so no shuffling
7077 is necessary. The only complication is that MODE_VECTOR_BOOL
7078 vectors can have several elements per byte. */
7079 unsigned int elt_bits
= vector_element_size (GET_MODE_PRECISION (mode
),
7080 GET_MODE_NUNITS (mode
));
7081 unsigned int elt
= first_byte
* BITS_PER_UNIT
/ elt_bits
;
7082 if (elt_bits
< BITS_PER_UNIT
)
7084 /* This is the only case in which elements can be smaller than
7086 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
7087 auto mask
= GET_MODE_MASK (GET_MODE_INNER (mode
));
7088 for (unsigned int i
= 0; i
< num_bytes
; ++i
)
7090 target_unit value
= 0;
7091 for (unsigned int j
= 0; j
< BITS_PER_UNIT
; j
+= elt_bits
)
7093 value
|= (INTVAL (CONST_VECTOR_ELT (x
, elt
)) & mask
) << j
;
7096 bytes
.quick_push (value
);
7101 unsigned int start
= bytes
.length ();
7102 unsigned int elt_bytes
= GET_MODE_UNIT_SIZE (mode
);
7103 /* Make FIRST_BYTE relative to ELT. */
7104 first_byte
%= elt_bytes
;
7105 while (num_bytes
> 0)
7107 /* Work out how many bytes we want from element ELT. */
7108 unsigned int chunk_bytes
= MIN (num_bytes
, elt_bytes
- first_byte
);
7109 if (!native_encode_rtx (GET_MODE_INNER (mode
),
7110 CONST_VECTOR_ELT (x
, elt
), bytes
,
7111 first_byte
, chunk_bytes
))
7113 bytes
.truncate (start
);
7118 num_bytes
-= chunk_bytes
;
7123 /* All subsequent cases are limited to scalars. */
7125 if (!is_a
<scalar_mode
> (mode
, &smode
))
7128 /* Make sure that the region is in range. */
7129 unsigned int end_byte
= first_byte
+ num_bytes
;
7130 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
7131 gcc_assert (end_byte
<= mode_bytes
);
7133 if (CONST_SCALAR_INT_P (x
))
7135 /* The target memory layout is affected by both BYTES_BIG_ENDIAN
7136 and WORDS_BIG_ENDIAN. Use the subreg machinery to get the lsb
7137 position of each byte. */
7138 rtx_mode_t
value (x
, smode
);
7139 wide_int_ref
value_wi (value
);
7140 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
7142 /* Always constant because the inputs are. */
7144 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
7145 /* Operate directly on the encoding rather than using
7146 wi::extract_uhwi, so that we preserve the sign or zero
7147 extension for modes that are not a whole number of bits in
7148 size. (Zero extension is only used for the combination of
7149 innermode == BImode && STORE_FLAG_VALUE == 1). */
7150 unsigned int elt
= lsb
/ HOST_BITS_PER_WIDE_INT
;
7151 unsigned int shift
= lsb
% HOST_BITS_PER_WIDE_INT
;
7152 unsigned HOST_WIDE_INT uhwi
= value_wi
.elt (elt
);
7153 bytes
.quick_push (uhwi
>> shift
);
7158 if (CONST_DOUBLE_P (x
))
7160 /* real_to_target produces an array of integers in target memory order.
7161 All integers before the last one have 32 bits; the last one may
7162 have 32 bits or fewer, depending on whether the mode bitsize
7163 is divisible by 32. Each of these integers is then laid out
7164 in target memory as any other integer would be. */
7165 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
7166 real_to_target (el32
, CONST_DOUBLE_REAL_VALUE (x
), smode
);
7168 /* The (maximum) number of target bytes per element of el32. */
7169 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
7170 gcc_assert (bytes_per_el32
!= 0);
7172 /* Build up the integers in a similar way to the CONST_SCALAR_INT_P
7174 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
7176 unsigned int index
= byte
/ bytes_per_el32
;
7177 unsigned int subbyte
= byte
% bytes_per_el32
;
7178 unsigned int int_bytes
= MIN (bytes_per_el32
,
7179 mode_bytes
- index
* bytes_per_el32
);
7180 /* Always constant because the inputs are. */
7182 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
7183 bytes
.quick_push ((unsigned long) el32
[index
] >> lsb
);
7188 if (GET_CODE (x
) == CONST_FIXED
)
7190 for (unsigned int byte
= first_byte
; byte
< end_byte
; ++byte
)
7192 /* Always constant because the inputs are. */
7194 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
7195 unsigned HOST_WIDE_INT piece
= CONST_FIXED_VALUE_LOW (x
);
7196 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
7198 lsb
-= HOST_BITS_PER_WIDE_INT
;
7199 piece
= CONST_FIXED_VALUE_HIGH (x
);
7201 bytes
.quick_push (piece
>> lsb
);
7209 /* Read a vector of mode MODE from the target memory image given by BYTES,
7210 starting at byte FIRST_BYTE. The vector is known to be encodable using
7211 NPATTERNS interleaved patterns with NELTS_PER_PATTERN elements each,
7212 and BYTES is known to have enough bytes to supply NPATTERNS *
7213 NELTS_PER_PATTERN vector elements. Each element of BYTES contains
7214 BITS_PER_UNIT bits and the bytes are in target memory order.
7216 Return the vector on success, otherwise return NULL_RTX. */
7219 native_decode_vector_rtx (machine_mode mode
, const vec
<target_unit
> &bytes
,
7220 unsigned int first_byte
, unsigned int npatterns
,
7221 unsigned int nelts_per_pattern
)
7223 rtx_vector_builder
builder (mode
, npatterns
, nelts_per_pattern
);
7225 unsigned int elt_bits
= vector_element_size (GET_MODE_PRECISION (mode
),
7226 GET_MODE_NUNITS (mode
));
7227 if (elt_bits
< BITS_PER_UNIT
)
7229 /* This is the only case in which elements can be smaller than a byte.
7230 Element 0 is always in the lsb of the containing byte. */
7231 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_BOOL
);
7232 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
7234 unsigned int bit_index
= first_byte
* BITS_PER_UNIT
+ i
* elt_bits
;
7235 unsigned int byte_index
= bit_index
/ BITS_PER_UNIT
;
7236 unsigned int lsb
= bit_index
% BITS_PER_UNIT
;
7237 unsigned int value
= bytes
[byte_index
] >> lsb
;
7238 builder
.quick_push (gen_int_mode (value
, GET_MODE_INNER (mode
)));
7243 for (unsigned int i
= 0; i
< builder
.encoded_nelts (); ++i
)
7245 rtx x
= native_decode_rtx (GET_MODE_INNER (mode
), bytes
, first_byte
);
7248 builder
.quick_push (x
);
7249 first_byte
+= elt_bits
/ BITS_PER_UNIT
;
7252 return builder
.build ();
7255 /* Read an rtx of mode MODE from the target memory image given by BYTES,
7256 starting at byte FIRST_BYTE. Each element of BYTES contains BITS_PER_UNIT
7257 bits and the bytes are in target memory order. The image has enough
7258 values to specify all bytes of MODE.
7260 Return the rtx on success, otherwise return NULL_RTX. */
7263 native_decode_rtx (machine_mode mode
, const vec
<target_unit
> &bytes
,
7264 unsigned int first_byte
)
7266 if (VECTOR_MODE_P (mode
))
7268 /* If we know at compile time how many elements there are,
7269 pull each element directly from BYTES. */
7271 if (GET_MODE_NUNITS (mode
).is_constant (&nelts
))
7272 return native_decode_vector_rtx (mode
, bytes
, first_byte
, nelts
, 1);
7276 scalar_int_mode imode
;
7277 if (is_a
<scalar_int_mode
> (mode
, &imode
)
7278 && GET_MODE_PRECISION (imode
) <= MAX_BITSIZE_MODE_ANY_INT
)
7280 /* Pull the bytes msb first, so that we can use simple
7281 shift-and-insert wide_int operations. */
7282 unsigned int size
= GET_MODE_SIZE (imode
);
7283 wide_int
result (wi::zero (GET_MODE_PRECISION (imode
)));
7284 for (unsigned int i
= 0; i
< size
; ++i
)
7286 unsigned int lsb
= (size
- i
- 1) * BITS_PER_UNIT
;
7287 /* Always constant because the inputs are. */
7288 unsigned int subbyte
7289 = subreg_size_offset_from_lsb (1, size
, lsb
).to_constant ();
7290 result
<<= BITS_PER_UNIT
;
7291 result
|= bytes
[first_byte
+ subbyte
];
7293 return immed_wide_int_const (result
, imode
);
7296 scalar_float_mode fmode
;
7297 if (is_a
<scalar_float_mode
> (mode
, &fmode
))
7299 /* We need to build an array of integers in target memory order.
7300 All integers before the last one have 32 bits; the last one may
7301 have 32 bits or fewer, depending on whether the mode bitsize
7302 is divisible by 32. */
7303 long el32
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
7304 unsigned int num_el32
= CEIL (GET_MODE_BITSIZE (fmode
), 32);
7305 memset (el32
, 0, num_el32
* sizeof (long));
7307 /* The (maximum) number of target bytes per element of el32. */
7308 unsigned int bytes_per_el32
= 32 / BITS_PER_UNIT
;
7309 gcc_assert (bytes_per_el32
!= 0);
7311 unsigned int mode_bytes
= GET_MODE_SIZE (fmode
);
7312 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
7314 unsigned int index
= byte
/ bytes_per_el32
;
7315 unsigned int subbyte
= byte
% bytes_per_el32
;
7316 unsigned int int_bytes
= MIN (bytes_per_el32
,
7317 mode_bytes
- index
* bytes_per_el32
);
7318 /* Always constant because the inputs are. */
7320 = subreg_size_lsb (1, int_bytes
, subbyte
).to_constant ();
7321 el32
[index
] |= (unsigned long) bytes
[first_byte
+ byte
] << lsb
;
7324 real_from_target (&r
, el32
, fmode
);
7325 return const_double_from_real_value (r
, fmode
);
7328 if (ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
7330 scalar_mode smode
= as_a
<scalar_mode
> (mode
);
7336 unsigned int mode_bytes
= GET_MODE_SIZE (smode
);
7337 for (unsigned int byte
= 0; byte
< mode_bytes
; ++byte
)
7339 /* Always constant because the inputs are. */
7341 = subreg_size_lsb (1, mode_bytes
, byte
).to_constant ();
7342 unsigned HOST_WIDE_INT unit
= bytes
[first_byte
+ byte
];
7343 if (lsb
>= HOST_BITS_PER_WIDE_INT
)
7344 f
.data
.high
|= unit
<< (lsb
- HOST_BITS_PER_WIDE_INT
);
7346 f
.data
.low
|= unit
<< lsb
;
7348 return CONST_FIXED_FROM_FIXED_VALUE (f
, mode
);
7354 /* Simplify a byte offset BYTE into CONST_VECTOR X. The main purpose
7355 is to convert a runtime BYTE value into a constant one. */
7358 simplify_const_vector_byte_offset (rtx x
, poly_uint64 byte
)
7360 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
7361 machine_mode mode
= GET_MODE (x
);
7362 unsigned int elt_bits
= vector_element_size (GET_MODE_PRECISION (mode
),
7363 GET_MODE_NUNITS (mode
));
7364 /* The number of bits needed to encode one element from each pattern. */
7365 unsigned int sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * elt_bits
;
7367 /* Identify the start point in terms of a sequence number and a byte offset
7368 within that sequence. */
7369 poly_uint64 first_sequence
;
7370 unsigned HOST_WIDE_INT subbit
;
7371 if (can_div_trunc_p (byte
* BITS_PER_UNIT
, sequence_bits
,
7372 &first_sequence
, &subbit
))
7374 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
7375 if (nelts_per_pattern
== 1)
7376 /* This is a duplicated vector, so the value of FIRST_SEQUENCE
7378 byte
= subbit
/ BITS_PER_UNIT
;
7379 else if (nelts_per_pattern
== 2 && known_gt (first_sequence
, 0U))
7381 /* The subreg drops the first element from each pattern and
7382 only uses the second element. Find the first sequence
7383 that starts on a byte boundary. */
7384 subbit
+= least_common_multiple (sequence_bits
, BITS_PER_UNIT
);
7385 byte
= subbit
/ BITS_PER_UNIT
;
7391 /* Subroutine of simplify_subreg in which:
7393 - X is known to be a CONST_VECTOR
7394 - OUTERMODE is known to be a vector mode
7396 Try to handle the subreg by operating on the CONST_VECTOR encoding
7397 rather than on each individual element of the CONST_VECTOR.
7399 Return the simplified subreg on success, otherwise return NULL_RTX. */
7402 simplify_const_vector_subreg (machine_mode outermode
, rtx x
,
7403 machine_mode innermode
, unsigned int first_byte
)
7405 /* Paradoxical subregs of vectors have dubious semantics. */
7406 if (paradoxical_subreg_p (outermode
, innermode
))
7409 /* We can only preserve the semantics of a stepped pattern if the new
7410 vector element is the same as the original one. */
7411 if (CONST_VECTOR_STEPPED_P (x
)
7412 && GET_MODE_INNER (outermode
) != GET_MODE_INNER (innermode
))
7415 /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */
7416 unsigned int x_elt_bits
7417 = vector_element_size (GET_MODE_PRECISION (innermode
),
7418 GET_MODE_NUNITS (innermode
));
7419 unsigned int out_elt_bits
7420 = vector_element_size (GET_MODE_PRECISION (outermode
),
7421 GET_MODE_NUNITS (outermode
));
7423 /* The number of bits needed to encode one element from every pattern
7424 of the original vector. */
7425 unsigned int x_sequence_bits
= CONST_VECTOR_NPATTERNS (x
) * x_elt_bits
;
7427 /* The number of bits needed to encode one element from every pattern
7429 unsigned int out_sequence_bits
7430 = least_common_multiple (x_sequence_bits
, out_elt_bits
);
7432 /* Work out the number of interleaved patterns in the output vector
7433 and the number of encoded elements per pattern. */
7434 unsigned int out_npatterns
= out_sequence_bits
/ out_elt_bits
;
7435 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
7437 /* The encoding scheme requires the number of elements to be a multiple
7438 of the number of patterns, so that each pattern appears at least once
7439 and so that the same number of elements appear from each pattern. */
7440 bool ok_p
= multiple_p (GET_MODE_NUNITS (outermode
), out_npatterns
);
7441 unsigned int const_nunits
;
7442 if (GET_MODE_NUNITS (outermode
).is_constant (&const_nunits
)
7443 && (!ok_p
|| out_npatterns
* nelts_per_pattern
> const_nunits
))
7445 /* Either the encoding is invalid, or applying it would give us
7446 more elements than we need. Just encode each element directly. */
7447 out_npatterns
= const_nunits
;
7448 nelts_per_pattern
= 1;
7453 /* Get enough bytes of X to form the new encoding. */
7454 unsigned int buffer_bits
= out_npatterns
* nelts_per_pattern
* out_elt_bits
;
7455 unsigned int buffer_bytes
= CEIL (buffer_bits
, BITS_PER_UNIT
);
7456 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
7457 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, buffer_bytes
))
7460 /* Reencode the bytes as OUTERMODE. */
7461 return native_decode_vector_rtx (outermode
, buffer
, 0, out_npatterns
,
7465 /* Try to simplify a subreg of a constant by encoding the subreg region
7466 as a sequence of target bytes and reading them back in the new mode.
7467 Return the new value on success, otherwise return null.
7469 The subreg has outer mode OUTERMODE, inner mode INNERMODE, inner value X
7470 and byte offset FIRST_BYTE. */
7473 simplify_immed_subreg (fixed_size_mode outermode
, rtx x
,
7474 machine_mode innermode
, unsigned int first_byte
)
7476 unsigned int buffer_bytes
= GET_MODE_SIZE (outermode
);
7477 auto_vec
<target_unit
, 128> buffer (buffer_bytes
);
7479 /* Some ports misuse CCmode. */
7480 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& CONST_INT_P (x
))
7483 /* Paradoxical subregs read undefined values for bytes outside of the
7484 inner value. However, we have traditionally always sign-extended
7485 integer constants and zero-extended others. */
7486 unsigned int inner_bytes
= buffer_bytes
;
7487 if (paradoxical_subreg_p (outermode
, innermode
))
7489 if (!GET_MODE_SIZE (innermode
).is_constant (&inner_bytes
))
7492 target_unit filler
= 0;
7493 if (CONST_SCALAR_INT_P (x
) && wi::neg_p (rtx_mode_t (x
, innermode
)))
7496 /* Add any leading bytes due to big-endian layout. The number of
7497 bytes must be constant because both modes have constant size. */
7498 unsigned int leading_bytes
7499 = -byte_lowpart_offset (outermode
, innermode
).to_constant ();
7500 for (unsigned int i
= 0; i
< leading_bytes
; ++i
)
7501 buffer
.quick_push (filler
);
7503 if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
7506 /* Add any trailing bytes due to little-endian layout. */
7507 while (buffer
.length () < buffer_bytes
)
7508 buffer
.quick_push (filler
);
7510 else if (!native_encode_rtx (innermode
, x
, buffer
, first_byte
, inner_bytes
))
7512 rtx ret
= native_decode_rtx (outermode
, buffer
, 0);
7513 if (ret
&& FLOAT_MODE_P (outermode
))
7515 auto_vec
<target_unit
, 128> buffer2 (buffer_bytes
);
7516 if (!native_encode_rtx (outermode
, ret
, buffer2
, 0, buffer_bytes
))
7518 for (unsigned int i
= 0; i
< buffer_bytes
; ++i
)
7519 if (buffer
[i
] != buffer2
[i
])
7525 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
7526 Return 0 if no simplifications are possible. */
7528 simplify_context::simplify_subreg (machine_mode outermode
, rtx op
,
7529 machine_mode innermode
, poly_uint64 byte
)
7531 /* Little bit of sanity checking. */
7532 gcc_assert (innermode
!= VOIDmode
);
7533 gcc_assert (outermode
!= VOIDmode
);
7534 gcc_assert (innermode
!= BLKmode
);
7535 gcc_assert (outermode
!= BLKmode
);
7537 gcc_assert (GET_MODE (op
) == innermode
7538 || GET_MODE (op
) == VOIDmode
);
7540 poly_uint64 outersize
= GET_MODE_SIZE (outermode
);
7541 if (!multiple_p (byte
, outersize
))
7544 poly_uint64 innersize
= GET_MODE_SIZE (innermode
);
7545 if (maybe_ge (byte
, innersize
))
7548 if (outermode
== innermode
&& known_eq (byte
, 0U))
7551 if (GET_CODE (op
) == CONST_VECTOR
)
7552 byte
= simplify_const_vector_byte_offset (op
, byte
);
7554 if (multiple_p (byte
, GET_MODE_UNIT_SIZE (innermode
)))
7558 if (VECTOR_MODE_P (outermode
)
7559 && GET_MODE_INNER (outermode
) == GET_MODE_INNER (innermode
)
7560 && vec_duplicate_p (op
, &elt
))
7561 return gen_vec_duplicate (outermode
, elt
);
7563 if (outermode
== GET_MODE_INNER (innermode
)
7564 && vec_duplicate_p (op
, &elt
))
7568 if (CONST_SCALAR_INT_P (op
)
7569 || CONST_DOUBLE_AS_FLOAT_P (op
)
7570 || CONST_FIXED_P (op
)
7571 || GET_CODE (op
) == CONST_VECTOR
)
7573 unsigned HOST_WIDE_INT cbyte
;
7574 if (byte
.is_constant (&cbyte
))
7576 if (GET_CODE (op
) == CONST_VECTOR
&& VECTOR_MODE_P (outermode
))
7578 rtx tmp
= simplify_const_vector_subreg (outermode
, op
,
7584 fixed_size_mode fs_outermode
;
7585 if (is_a
<fixed_size_mode
> (outermode
, &fs_outermode
))
7586 return simplify_immed_subreg (fs_outermode
, op
, innermode
, cbyte
);
7590 /* Changing mode twice with SUBREG => just change it once,
7591 or not at all if changing back op starting mode. */
7592 if (GET_CODE (op
) == SUBREG
)
7594 machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
7595 poly_uint64 innermostsize
= GET_MODE_SIZE (innermostmode
);
7598 if (outermode
== innermostmode
7599 && known_eq (byte
, 0U)
7600 && known_eq (SUBREG_BYTE (op
), 0))
7601 return SUBREG_REG (op
);
7603 /* Work out the memory offset of the final OUTERMODE value relative
7604 to the inner value of OP. */
7605 poly_int64 mem_offset
= subreg_memory_offset (outermode
,
7607 poly_int64 op_mem_offset
= subreg_memory_offset (op
);
7608 poly_int64 final_offset
= mem_offset
+ op_mem_offset
;
7610 /* See whether resulting subreg will be paradoxical. */
7611 if (!paradoxical_subreg_p (outermode
, innermostmode
))
7613 /* Bail out in case resulting subreg would be incorrect. */
7614 if (maybe_lt (final_offset
, 0)
7615 || maybe_ge (poly_uint64 (final_offset
), innermostsize
)
7616 || !multiple_p (final_offset
, outersize
))
7621 poly_int64 required_offset
= subreg_memory_offset (outermode
,
7623 if (maybe_ne (final_offset
, required_offset
))
7625 /* Paradoxical subregs always have byte offset 0. */
7629 /* Recurse for further possible simplifications. */
7630 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
7634 if (validate_subreg (outermode
, innermostmode
,
7635 SUBREG_REG (op
), final_offset
))
7637 newx
= gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
7638 if (SUBREG_PROMOTED_VAR_P (op
)
7639 && SUBREG_PROMOTED_SIGN (op
) >= 0
7640 && GET_MODE_CLASS (outermode
) == MODE_INT
7641 && known_ge (outersize
, innersize
)
7642 && known_le (outersize
, innermostsize
)
7643 && subreg_lowpart_p (newx
))
7645 SUBREG_PROMOTED_VAR_P (newx
) = 1;
7646 SUBREG_PROMOTED_SET (newx
, SUBREG_PROMOTED_GET (op
));
7653 /* SUBREG of a hard register => just change the register number
7654 and/or mode. If the hard register is not valid in that mode,
7655 suppress this simplification. If the hard register is the stack,
7656 frame, or argument pointer, leave this as a SUBREG. */
7658 if (REG_P (op
) && HARD_REGISTER_P (op
))
7660 unsigned int regno
, final_regno
;
7663 final_regno
= simplify_subreg_regno (regno
, innermode
, byte
, outermode
);
7664 if (HARD_REGISTER_NUM_P (final_regno
))
7666 rtx x
= gen_rtx_REG_offset (op
, outermode
, final_regno
,
7667 subreg_memory_offset (outermode
,
7670 /* Propagate original regno. We don't have any way to specify
7671 the offset inside original regno, so do so only for lowpart.
7672 The information is used only by alias analysis that cannot
7673 grog partial register anyway. */
7675 if (known_eq (subreg_lowpart_offset (outermode
, innermode
), byte
))
7676 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
7681 /* If we have a SUBREG of a register that we are replacing and we are
7682 replacing it with a MEM, make a new MEM and try replacing the
7683 SUBREG with it. Don't do this if the MEM has a mode-dependent address
7684 or if we would be widening it. */
7687 && ! mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
))
7688 /* Allow splitting of volatile memory references in case we don't
7689 have instruction to move the whole thing. */
7690 && (! MEM_VOLATILE_P (op
)
7691 || ! have_insn_for (SET
, innermode
))
7692 && !(STRICT_ALIGNMENT
&& MEM_ALIGN (op
) < GET_MODE_ALIGNMENT (outermode
))
7693 && known_le (outersize
, innersize
))
7694 return adjust_address_nv (op
, outermode
, byte
);
7696 /* Handle complex or vector values represented as CONCAT or VEC_CONCAT
7698 if (GET_CODE (op
) == CONCAT
7699 || GET_CODE (op
) == VEC_CONCAT
)
7701 poly_uint64 final_offset
;
7704 machine_mode part_mode
= GET_MODE (XEXP (op
, 0));
7705 if (part_mode
== VOIDmode
)
7706 part_mode
= GET_MODE_INNER (GET_MODE (op
));
7707 poly_uint64 part_size
= GET_MODE_SIZE (part_mode
);
7708 if (known_lt (byte
, part_size
))
7710 part
= XEXP (op
, 0);
7711 final_offset
= byte
;
7713 else if (known_ge (byte
, part_size
))
7715 part
= XEXP (op
, 1);
7716 final_offset
= byte
- part_size
;
7721 if (maybe_gt (final_offset
+ outersize
, part_size
))
7724 part_mode
= GET_MODE (part
);
7725 if (part_mode
== VOIDmode
)
7726 part_mode
= GET_MODE_INNER (GET_MODE (op
));
7727 res
= simplify_subreg (outermode
, part
, part_mode
, final_offset
);
7730 if (validate_subreg (outermode
, part_mode
, part
, final_offset
))
7731 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
7736 (subreg (vec_merge (X)
7738 (const_int ((1 << N) | M)))
7739 (N * sizeof (outermode)))
7741 (subreg (X) (N * sizeof (outermode)))
7744 if (constant_multiple_p (byte
, GET_MODE_SIZE (outermode
), &idx
)
7745 && idx
< HOST_BITS_PER_WIDE_INT
7746 && GET_CODE (op
) == VEC_MERGE
7747 && GET_MODE_INNER (innermode
) == outermode
7748 && CONST_INT_P (XEXP (op
, 2))
7749 && (UINTVAL (XEXP (op
, 2)) & (HOST_WIDE_INT_1U
<< idx
)) != 0)
7750 return simplify_gen_subreg (outermode
, XEXP (op
, 0), innermode
, byte
);
7752 /* A SUBREG resulting from a zero extension may fold to zero if
7753 it extracts higher bits that the ZERO_EXTEND's source bits. */
7754 if (GET_CODE (op
) == ZERO_EXTEND
&& SCALAR_INT_MODE_P (innermode
))
7756 poly_uint64 bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
7757 if (known_ge (bitpos
, GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))))
7758 return CONST0_RTX (outermode
);
7761 /* Optimize SUBREGS of scalar integral ASHIFT by a valid constant. */
7762 if (GET_CODE (op
) == ASHIFT
7763 && SCALAR_INT_MODE_P (innermode
)
7764 && CONST_INT_P (XEXP (op
, 1))
7765 && INTVAL (XEXP (op
, 1)) > 0
7766 && known_gt (GET_MODE_BITSIZE (innermode
), INTVAL (XEXP (op
, 1))))
7768 HOST_WIDE_INT val
= INTVAL (XEXP (op
, 1));
7769 /* A lowpart SUBREG of a ASHIFT by a constant may fold to zero. */
7770 if (known_eq (subreg_lowpart_offset (outermode
, innermode
), byte
)
7771 && known_le (GET_MODE_BITSIZE (outermode
), val
))
7772 return CONST0_RTX (outermode
);
7773 /* Optimize the highpart SUBREG of a suitable ASHIFT (ZERO_EXTEND). */
7774 if (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
7775 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == outermode
7776 && known_eq (GET_MODE_BITSIZE (outermode
), val
)
7777 && known_eq (GET_MODE_BITSIZE (innermode
), 2 * val
)
7778 && known_eq (subreg_highpart_offset (outermode
, innermode
), byte
))
7779 return XEXP (XEXP (op
, 0), 0);
7782 /* Attempt to simplify WORD_MODE SUBREGs of bitwise expressions. */
7783 if (outermode
== word_mode
7784 && (GET_CODE (op
) == IOR
|| GET_CODE (op
) == XOR
|| GET_CODE (op
) == AND
)
7785 && SCALAR_INT_MODE_P (innermode
))
7787 rtx op0
= simplify_subreg (outermode
, XEXP (op
, 0), innermode
, byte
);
7788 rtx op1
= simplify_subreg (outermode
, XEXP (op
, 1), innermode
, byte
);
7790 return simplify_gen_binary (GET_CODE (op
), outermode
, op0
, op1
);
7793 scalar_int_mode int_outermode
, int_innermode
;
7794 if (is_a
<scalar_int_mode
> (outermode
, &int_outermode
)
7795 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
7796 && known_eq (byte
, subreg_lowpart_offset (int_outermode
, int_innermode
)))
7798 /* Handle polynomial integers. The upper bits of a paradoxical
7799 subreg are undefined, so this is safe regardless of whether
7800 we're truncating or extending. */
7801 if (CONST_POLY_INT_P (op
))
7804 = poly_wide_int::from (const_poly_int_value (op
),
7805 GET_MODE_PRECISION (int_outermode
),
7807 return immed_wide_int_const (val
, int_outermode
);
7810 if (GET_MODE_PRECISION (int_outermode
)
7811 < GET_MODE_PRECISION (int_innermode
))
7813 rtx tem
= simplify_truncation (int_outermode
, op
, int_innermode
);
7819 /* If the outer mode is not integral, try taking a subreg with the equivalent
7820 integer outer mode and then bitcasting the result.
7821 Other simplifications rely on integer to integer subregs and we'd
7822 potentially miss out on optimizations otherwise. */
7823 if (known_gt (GET_MODE_SIZE (innermode
),
7824 GET_MODE_SIZE (outermode
))
7825 && SCALAR_INT_MODE_P (innermode
)
7826 && !SCALAR_INT_MODE_P (outermode
)
7827 && int_mode_for_size (GET_MODE_BITSIZE (outermode
),
7828 0).exists (&int_outermode
))
7830 rtx tem
= simplify_subreg (int_outermode
, op
, innermode
, byte
);
7832 return simplify_gen_subreg (outermode
, tem
, int_outermode
, byte
);
7835 /* If OP is a vector comparison and the subreg is not changing the
7836 number of elements or the size of the elements, change the result
7837 of the comparison to the new mode. */
7838 if (COMPARISON_P (op
)
7839 && VECTOR_MODE_P (outermode
)
7840 && VECTOR_MODE_P (innermode
)
7841 && known_eq (GET_MODE_NUNITS (outermode
), GET_MODE_NUNITS (innermode
))
7842 && known_eq (GET_MODE_UNIT_SIZE (outermode
),
7843 GET_MODE_UNIT_SIZE (innermode
)))
7844 return simplify_gen_relational (GET_CODE (op
), outermode
, innermode
,
7845 XEXP (op
, 0), XEXP (op
, 1));
7849 /* Make a SUBREG operation or equivalent if it folds. */
7852 simplify_context::simplify_gen_subreg (machine_mode outermode
, rtx op
,
7853 machine_mode innermode
,
7858 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
7862 if (GET_CODE (op
) == SUBREG
7863 || GET_CODE (op
) == CONCAT
7864 || GET_MODE (op
) == VOIDmode
)
7867 if (MODE_COMPOSITE_P (outermode
)
7868 && (CONST_SCALAR_INT_P (op
)
7869 || CONST_DOUBLE_AS_FLOAT_P (op
)
7870 || CONST_FIXED_P (op
)
7871 || GET_CODE (op
) == CONST_VECTOR
))
7874 if (validate_subreg (outermode
, innermode
, op
, byte
))
7875 return gen_rtx_SUBREG (outermode
, op
, byte
);
7880 /* Generates a subreg to get the least significant part of EXPR (in mode
7881 INNER_MODE) to OUTER_MODE. */
7884 simplify_context::lowpart_subreg (machine_mode outer_mode
, rtx expr
,
7885 machine_mode inner_mode
)
7887 return simplify_gen_subreg (outer_mode
, expr
, inner_mode
,
7888 subreg_lowpart_offset (outer_mode
, inner_mode
));
7891 /* Generate RTX to select element at INDEX out of vector OP. */
7894 simplify_context::simplify_gen_vec_select (rtx op
, unsigned int index
)
7896 gcc_assert (VECTOR_MODE_P (GET_MODE (op
)));
7898 scalar_mode imode
= GET_MODE_INNER (GET_MODE (op
));
7900 if (known_eq (index
* GET_MODE_SIZE (imode
),
7901 subreg_lowpart_offset (imode
, GET_MODE (op
))))
7903 rtx res
= lowpart_subreg (imode
, op
, GET_MODE (op
));
7908 rtx tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, GEN_INT (index
)));
7909 return gen_rtx_VEC_SELECT (imode
, op
, tmp
);
7913 /* Simplify X, an rtx expression.
7915 Return the simplified expression or NULL if no simplifications
7918 This is the preferred entry point into the simplification routines;
7919 however, we still allow passes to call the more specific routines.
7921 Right now GCC has three (yes, three) major bodies of RTL simplification
7922 code that need to be unified.
7924 1. fold_rtx in cse.cc. This code uses various CSE specific
7925 information to aid in RTL simplification.
7927 2. simplify_rtx in combine.cc. Similar to fold_rtx, except that
7928 it uses combine specific information to aid in RTL
7931 3. The routines in this file.
7934 Long term we want to only have one body of simplification code; to
7935 get to that state I recommend the following steps:
7937 1. Pour over fold_rtx & simplify_rtx and move any simplifications
7938 which are not pass dependent state into these routines.
7940 2. As code is moved by #1, change fold_rtx & simplify_rtx to
7941 use this routine whenever possible.
7943 3. Allow for pass dependent state to be provided to these
7944 routines and add simplifications based on the pass dependent
7945 state. Remove code from cse.cc & combine.cc that becomes
7948 It will take time, but ultimately the compiler will be easier to
7949 maintain and improve. It's totally silly that when we add a
7950 simplification that it needs to be added to 4 places (3 for RTL
7951 simplification and 1 for tree simplification. */
7954 simplify_rtx (const_rtx x
)
7956 const enum rtx_code code
= GET_CODE (x
);
7957 const machine_mode mode
= GET_MODE (x
);
7959 switch (GET_RTX_CLASS (code
))
7962 return simplify_unary_operation (code
, mode
,
7963 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
7964 case RTX_COMM_ARITH
:
7965 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7966 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
7971 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
7974 case RTX_BITFIELD_OPS
:
7975 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
7976 XEXP (x
, 0), XEXP (x
, 1),
7980 case RTX_COMM_COMPARE
:
7981 return simplify_relational_operation (code
, mode
,
7982 ((GET_MODE (XEXP (x
, 0))
7984 ? GET_MODE (XEXP (x
, 0))
7985 : GET_MODE (XEXP (x
, 1))),
7991 return simplify_subreg (mode
, SUBREG_REG (x
),
7992 GET_MODE (SUBREG_REG (x
)),
7999 /* Convert (lo_sum (high FOO) FOO) to FOO. */
8000 if (GET_CODE (XEXP (x
, 0)) == HIGH
8001 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
8014 namespace selftest
{
8016 /* Make a unique pseudo REG of mode MODE for use by selftests. */
8019 make_test_reg (machine_mode mode
)
8021 static int test_reg_num
= LAST_VIRTUAL_REGISTER
+ 1;
8023 return gen_rtx_REG (mode
, test_reg_num
++);
8027 test_scalar_int_ops (machine_mode mode
)
8029 rtx op0
= make_test_reg (mode
);
8030 rtx op1
= make_test_reg (mode
);
8031 rtx six
= GEN_INT (6);
8033 rtx neg_op0
= simplify_gen_unary (NEG
, mode
, op0
, mode
);
8034 rtx not_op0
= simplify_gen_unary (NOT
, mode
, op0
, mode
);
8035 rtx bswap_op0
= simplify_gen_unary (BSWAP
, mode
, op0
, mode
);
8037 rtx and_op0_op1
= simplify_gen_binary (AND
, mode
, op0
, op1
);
8038 rtx ior_op0_op1
= simplify_gen_binary (IOR
, mode
, op0
, op1
);
8039 rtx xor_op0_op1
= simplify_gen_binary (XOR
, mode
, op0
, op1
);
8041 rtx and_op0_6
= simplify_gen_binary (AND
, mode
, op0
, six
);
8042 rtx and_op1_6
= simplify_gen_binary (AND
, mode
, op1
, six
);
8044 /* Test some binary identities. */
8045 ASSERT_RTX_EQ (op0
, simplify_gen_binary (PLUS
, mode
, op0
, const0_rtx
));
8046 ASSERT_RTX_EQ (op0
, simplify_gen_binary (PLUS
, mode
, const0_rtx
, op0
));
8047 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MINUS
, mode
, op0
, const0_rtx
));
8048 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MULT
, mode
, op0
, const1_rtx
));
8049 ASSERT_RTX_EQ (op0
, simplify_gen_binary (MULT
, mode
, const1_rtx
, op0
));
8050 ASSERT_RTX_EQ (op0
, simplify_gen_binary (DIV
, mode
, op0
, const1_rtx
));
8051 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, op0
, constm1_rtx
));
8052 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, constm1_rtx
, op0
));
8053 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, op0
, const0_rtx
));
8054 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, const0_rtx
, op0
));
8055 ASSERT_RTX_EQ (op0
, simplify_gen_binary (XOR
, mode
, op0
, const0_rtx
));
8056 ASSERT_RTX_EQ (op0
, simplify_gen_binary (XOR
, mode
, const0_rtx
, op0
));
8057 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ASHIFT
, mode
, op0
, const0_rtx
));
8058 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ROTATE
, mode
, op0
, const0_rtx
));
8059 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ASHIFTRT
, mode
, op0
, const0_rtx
));
8060 ASSERT_RTX_EQ (op0
, simplify_gen_binary (LSHIFTRT
, mode
, op0
, const0_rtx
));
8061 ASSERT_RTX_EQ (op0
, simplify_gen_binary (ROTATERT
, mode
, op0
, const0_rtx
));
8063 /* Test some self-inverse operations. */
8064 ASSERT_RTX_EQ (op0
, simplify_gen_unary (NEG
, mode
, neg_op0
, mode
));
8065 ASSERT_RTX_EQ (op0
, simplify_gen_unary (NOT
, mode
, not_op0
, mode
));
8066 ASSERT_RTX_EQ (op0
, simplify_gen_unary (BSWAP
, mode
, bswap_op0
, mode
));
8068 /* Test some reflexive operations. */
8069 ASSERT_RTX_EQ (op0
, simplify_gen_binary (AND
, mode
, op0
, op0
));
8070 ASSERT_RTX_EQ (op0
, simplify_gen_binary (IOR
, mode
, op0
, op0
));
8071 ASSERT_RTX_EQ (op0
, simplify_gen_binary (SMIN
, mode
, op0
, op0
));
8072 ASSERT_RTX_EQ (op0
, simplify_gen_binary (SMAX
, mode
, op0
, op0
));
8073 ASSERT_RTX_EQ (op0
, simplify_gen_binary (UMIN
, mode
, op0
, op0
));
8074 ASSERT_RTX_EQ (op0
, simplify_gen_binary (UMAX
, mode
, op0
, op0
));
8076 ASSERT_RTX_EQ (const0_rtx
, simplify_gen_binary (MINUS
, mode
, op0
, op0
));
8077 ASSERT_RTX_EQ (const0_rtx
, simplify_gen_binary (XOR
, mode
, op0
, op0
));
8079 /* Test simplify_distributive_operation. */
8080 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, xor_op0_op1
, six
),
8081 simplify_gen_binary (XOR
, mode
, and_op0_6
, and_op1_6
));
8082 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, ior_op0_op1
, six
),
8083 simplify_gen_binary (IOR
, mode
, and_op0_6
, and_op1_6
));
8084 ASSERT_RTX_EQ (simplify_gen_binary (AND
, mode
, and_op0_op1
, six
),
8085 simplify_gen_binary (AND
, mode
, and_op0_6
, and_op1_6
));
8087 /* Test useless extensions are eliminated. */
8088 ASSERT_RTX_EQ (op0
, simplify_gen_unary (TRUNCATE
, mode
, op0
, mode
));
8089 ASSERT_RTX_EQ (op0
, simplify_gen_unary (ZERO_EXTEND
, mode
, op0
, mode
));
8090 ASSERT_RTX_EQ (op0
, simplify_gen_unary (SIGN_EXTEND
, mode
, op0
, mode
));
8091 ASSERT_RTX_EQ (op0
, lowpart_subreg (mode
, op0
, mode
));
8094 /* Verify some simplifications of integer extension/truncation.
8095 Machine mode BMODE is the guaranteed wider than SMODE. */
8098 test_scalar_int_ext_ops (machine_mode bmode
, machine_mode smode
)
8100 rtx sreg
= make_test_reg (smode
);
8102 /* Check truncation of extension. */
8103 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8104 simplify_gen_unary (ZERO_EXTEND
, bmode
,
8108 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8109 simplify_gen_unary (SIGN_EXTEND
, bmode
,
8113 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8114 lowpart_subreg (bmode
, sreg
, smode
),
8119 /* Verify more simplifications of integer extension/truncation.
8120 BMODE is wider than MMODE which is wider than SMODE. */
8123 test_scalar_int_ext_ops2 (machine_mode bmode
, machine_mode mmode
,
8126 rtx breg
= make_test_reg (bmode
);
8127 rtx mreg
= make_test_reg (mmode
);
8128 rtx sreg
= make_test_reg (smode
);
8130 /* Check truncate of truncate. */
8131 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8132 simplify_gen_unary (TRUNCATE
, mmode
,
8135 simplify_gen_unary (TRUNCATE
, smode
, breg
, bmode
));
8137 /* Check extension of extension. */
8138 ASSERT_RTX_EQ (simplify_gen_unary (ZERO_EXTEND
, bmode
,
8139 simplify_gen_unary (ZERO_EXTEND
, mmode
,
8142 simplify_gen_unary (ZERO_EXTEND
, bmode
, sreg
, smode
));
8143 ASSERT_RTX_EQ (simplify_gen_unary (SIGN_EXTEND
, bmode
,
8144 simplify_gen_unary (SIGN_EXTEND
, mmode
,
8147 simplify_gen_unary (SIGN_EXTEND
, bmode
, sreg
, smode
));
8148 ASSERT_RTX_EQ (simplify_gen_unary (SIGN_EXTEND
, bmode
,
8149 simplify_gen_unary (ZERO_EXTEND
, mmode
,
8152 simplify_gen_unary (ZERO_EXTEND
, bmode
, sreg
, smode
));
8154 /* Check truncation of extension. */
8155 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8156 simplify_gen_unary (ZERO_EXTEND
, bmode
,
8159 simplify_gen_unary (TRUNCATE
, smode
, mreg
, mmode
));
8160 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8161 simplify_gen_unary (SIGN_EXTEND
, bmode
,
8164 simplify_gen_unary (TRUNCATE
, smode
, mreg
, mmode
));
8165 ASSERT_RTX_EQ (simplify_gen_unary (TRUNCATE
, smode
,
8166 lowpart_subreg (bmode
, mreg
, mmode
),
8168 simplify_gen_unary (TRUNCATE
, smode
, mreg
, mmode
));
8172 /* Verify some simplifications involving scalar expressions. */
8177 for (unsigned int i
= 0; i
< NUM_MACHINE_MODES
; ++i
)
8179 machine_mode mode
= (machine_mode
) i
;
8180 if (SCALAR_INT_MODE_P (mode
) && mode
!= BImode
)
8181 test_scalar_int_ops (mode
);
8184 test_scalar_int_ext_ops (HImode
, QImode
);
8185 test_scalar_int_ext_ops (SImode
, QImode
);
8186 test_scalar_int_ext_ops (SImode
, HImode
);
8187 test_scalar_int_ext_ops (DImode
, QImode
);
8188 test_scalar_int_ext_ops (DImode
, HImode
);
8189 test_scalar_int_ext_ops (DImode
, SImode
);
8191 test_scalar_int_ext_ops2 (SImode
, HImode
, QImode
);
8192 test_scalar_int_ext_ops2 (DImode
, HImode
, QImode
);
8193 test_scalar_int_ext_ops2 (DImode
, SImode
, QImode
);
8194 test_scalar_int_ext_ops2 (DImode
, SImode
, HImode
);
8197 /* Test vector simplifications involving VEC_DUPLICATE in which the
8198 operands and result have vector mode MODE. SCALAR_REG is a pseudo
8199 register that holds one element of MODE. */
8202 test_vector_ops_duplicate (machine_mode mode
, rtx scalar_reg
)
8204 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
8205 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
8206 poly_uint64 nunits
= GET_MODE_NUNITS (mode
);
8207 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
8209 /* Test some simple unary cases with VEC_DUPLICATE arguments. */
8210 rtx not_scalar_reg
= gen_rtx_NOT (inner_mode
, scalar_reg
);
8211 rtx duplicate_not
= gen_rtx_VEC_DUPLICATE (mode
, not_scalar_reg
);
8212 ASSERT_RTX_EQ (duplicate
,
8213 simplify_unary_operation (NOT
, mode
,
8214 duplicate_not
, mode
));
8216 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
8217 rtx duplicate_neg
= gen_rtx_VEC_DUPLICATE (mode
, neg_scalar_reg
);
8218 ASSERT_RTX_EQ (duplicate
,
8219 simplify_unary_operation (NEG
, mode
,
8220 duplicate_neg
, mode
));
8222 /* Test some simple binary cases with VEC_DUPLICATE arguments. */
8223 ASSERT_RTX_EQ (duplicate
,
8224 simplify_binary_operation (PLUS
, mode
, duplicate
,
8225 CONST0_RTX (mode
)));
8227 ASSERT_RTX_EQ (duplicate
,
8228 simplify_binary_operation (MINUS
, mode
, duplicate
,
8229 CONST0_RTX (mode
)));
8231 ASSERT_RTX_PTR_EQ (CONST0_RTX (mode
),
8232 simplify_binary_operation (MINUS
, mode
, duplicate
,
8236 /* Test a scalar VEC_SELECT of a VEC_DUPLICATE. */
8237 rtx zero_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, const0_rtx
));
8238 ASSERT_RTX_PTR_EQ (scalar_reg
,
8239 simplify_binary_operation (VEC_SELECT
, inner_mode
,
8240 duplicate
, zero_par
));
8242 unsigned HOST_WIDE_INT const_nunits
;
8243 if (nunits
.is_constant (&const_nunits
))
8245 /* And again with the final element. */
8246 rtx last_index
= gen_int_mode (const_nunits
- 1, word_mode
);
8247 rtx last_par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, last_index
));
8248 ASSERT_RTX_PTR_EQ (scalar_reg
,
8249 simplify_binary_operation (VEC_SELECT
, inner_mode
,
8250 duplicate
, last_par
));
8252 /* Test a scalar subreg of a VEC_MERGE of a VEC_DUPLICATE. */
8253 /* Skip this test for vectors of booleans, because offset is in bytes,
8254 while vec_merge indices are in elements (usually bits). */
8255 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_BOOL
)
8257 rtx vector_reg
= make_test_reg (mode
);
8258 for (unsigned HOST_WIDE_INT i
= 0; i
< const_nunits
; i
++)
8260 if (i
>= HOST_BITS_PER_WIDE_INT
)
8262 rtx mask
= GEN_INT ((HOST_WIDE_INT_1U
<< i
) | (i
+ 1));
8263 rtx vm
= gen_rtx_VEC_MERGE (mode
, duplicate
, vector_reg
, mask
);
8264 poly_uint64 offset
= i
* GET_MODE_SIZE (inner_mode
);
8266 ASSERT_RTX_EQ (scalar_reg
,
8267 simplify_gen_subreg (inner_mode
, vm
,
8273 /* Test a scalar subreg of a VEC_DUPLICATE. */
8274 poly_uint64 offset
= subreg_lowpart_offset (inner_mode
, mode
);
8275 ASSERT_RTX_EQ (scalar_reg
,
8276 simplify_gen_subreg (inner_mode
, duplicate
,
8279 machine_mode narrower_mode
;
8280 if (maybe_ne (nunits
, 2U)
8281 && multiple_p (nunits
, 2)
8282 && mode_for_vector (inner_mode
, 2).exists (&narrower_mode
)
8283 && VECTOR_MODE_P (narrower_mode
))
8285 /* Test VEC_DUPLICATE of a vector. */
8286 rtx_vector_builder
nbuilder (narrower_mode
, 2, 1);
8287 nbuilder
.quick_push (const0_rtx
);
8288 nbuilder
.quick_push (const1_rtx
);
8289 rtx_vector_builder
builder (mode
, 2, 1);
8290 builder
.quick_push (const0_rtx
);
8291 builder
.quick_push (const1_rtx
);
8292 ASSERT_RTX_EQ (builder
.build (),
8293 simplify_unary_operation (VEC_DUPLICATE
, mode
,
8297 /* Test VEC_SELECT of a vector. */
8299 = gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, const1_rtx
, const0_rtx
));
8300 rtx narrower_duplicate
8301 = gen_rtx_VEC_DUPLICATE (narrower_mode
, scalar_reg
);
8302 ASSERT_RTX_EQ (narrower_duplicate
,
8303 simplify_binary_operation (VEC_SELECT
, narrower_mode
,
8304 duplicate
, vec_par
));
8306 /* Test a vector subreg of a VEC_DUPLICATE. */
8307 poly_uint64 offset
= subreg_lowpart_offset (narrower_mode
, mode
);
8308 ASSERT_RTX_EQ (narrower_duplicate
,
8309 simplify_gen_subreg (narrower_mode
, duplicate
,
8314 /* Test vector simplifications involving VEC_SERIES in which the
8315 operands and result have vector mode MODE. SCALAR_REG is a pseudo
8316 register that holds one element of MODE. */
8319 test_vector_ops_series (machine_mode mode
, rtx scalar_reg
)
8321 /* Test unary cases with VEC_SERIES arguments. */
8322 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
8323 rtx duplicate
= gen_rtx_VEC_DUPLICATE (mode
, scalar_reg
);
8324 rtx neg_scalar_reg
= gen_rtx_NEG (inner_mode
, scalar_reg
);
8325 rtx series_0_r
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, scalar_reg
);
8326 rtx series_0_nr
= gen_rtx_VEC_SERIES (mode
, const0_rtx
, neg_scalar_reg
);
8327 rtx series_nr_1
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
, const1_rtx
);
8328 rtx series_r_m1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, constm1_rtx
);
8329 rtx series_r_r
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, scalar_reg
);
8330 rtx series_nr_nr
= gen_rtx_VEC_SERIES (mode
, neg_scalar_reg
,
8332 ASSERT_RTX_EQ (series_0_r
,
8333 simplify_unary_operation (NEG
, mode
, series_0_nr
, mode
));
8334 ASSERT_RTX_EQ (series_r_m1
,
8335 simplify_unary_operation (NEG
, mode
, series_nr_1
, mode
));
8336 ASSERT_RTX_EQ (series_r_r
,
8337 simplify_unary_operation (NEG
, mode
, series_nr_nr
, mode
));
8339 /* Test that a VEC_SERIES with a zero step is simplified away. */
8340 ASSERT_RTX_EQ (duplicate
,
8341 simplify_binary_operation (VEC_SERIES
, mode
,
8342 scalar_reg
, const0_rtx
));
8344 /* Test PLUS and MINUS with VEC_SERIES. */
8345 rtx series_0_1
= gen_const_vec_series (mode
, const0_rtx
, const1_rtx
);
8346 rtx series_0_m1
= gen_const_vec_series (mode
, const0_rtx
, constm1_rtx
);
8347 rtx series_r_1
= gen_rtx_VEC_SERIES (mode
, scalar_reg
, const1_rtx
);
8348 ASSERT_RTX_EQ (series_r_r
,
8349 simplify_binary_operation (PLUS
, mode
, series_0_r
,
8351 ASSERT_RTX_EQ (series_r_1
,
8352 simplify_binary_operation (PLUS
, mode
, duplicate
,
8354 ASSERT_RTX_EQ (series_r_m1
,
8355 simplify_binary_operation (PLUS
, mode
, duplicate
,
8357 ASSERT_RTX_EQ (series_0_r
,
8358 simplify_binary_operation (MINUS
, mode
, series_r_r
,
8360 ASSERT_RTX_EQ (series_r_m1
,
8361 simplify_binary_operation (MINUS
, mode
, duplicate
,
8363 ASSERT_RTX_EQ (series_r_1
,
8364 simplify_binary_operation (MINUS
, mode
, duplicate
,
8366 ASSERT_RTX_EQ (series_0_m1
,
8367 simplify_binary_operation (VEC_SERIES
, mode
, const0_rtx
,
8370 /* Test NEG on constant vector series. */
8371 ASSERT_RTX_EQ (series_0_m1
,
8372 simplify_unary_operation (NEG
, mode
, series_0_1
, mode
));
8373 ASSERT_RTX_EQ (series_0_1
,
8374 simplify_unary_operation (NEG
, mode
, series_0_m1
, mode
));
8376 /* Test PLUS and MINUS on constant vector series. */
8377 rtx scalar2
= gen_int_mode (2, inner_mode
);
8378 rtx scalar3
= gen_int_mode (3, inner_mode
);
8379 rtx series_1_1
= gen_const_vec_series (mode
, const1_rtx
, const1_rtx
);
8380 rtx series_0_2
= gen_const_vec_series (mode
, const0_rtx
, scalar2
);
8381 rtx series_1_3
= gen_const_vec_series (mode
, const1_rtx
, scalar3
);
8382 ASSERT_RTX_EQ (series_1_1
,
8383 simplify_binary_operation (PLUS
, mode
, series_0_1
,
8384 CONST1_RTX (mode
)));
8385 ASSERT_RTX_EQ (series_0_m1
,
8386 simplify_binary_operation (PLUS
, mode
, CONST0_RTX (mode
),
8388 ASSERT_RTX_EQ (series_1_3
,
8389 simplify_binary_operation (PLUS
, mode
, series_1_1
,
8391 ASSERT_RTX_EQ (series_0_1
,
8392 simplify_binary_operation (MINUS
, mode
, series_1_1
,
8393 CONST1_RTX (mode
)));
8394 ASSERT_RTX_EQ (series_1_1
,
8395 simplify_binary_operation (MINUS
, mode
, CONST1_RTX (mode
),
8397 ASSERT_RTX_EQ (series_1_1
,
8398 simplify_binary_operation (MINUS
, mode
, series_1_3
,
8401 /* Test MULT between constant vectors. */
8402 rtx vec2
= gen_const_vec_duplicate (mode
, scalar2
);
8403 rtx vec3
= gen_const_vec_duplicate (mode
, scalar3
);
8404 rtx scalar9
= gen_int_mode (9, inner_mode
);
8405 rtx series_3_9
= gen_const_vec_series (mode
, scalar3
, scalar9
);
8406 ASSERT_RTX_EQ (series_0_2
,
8407 simplify_binary_operation (MULT
, mode
, series_0_1
, vec2
));
8408 ASSERT_RTX_EQ (series_3_9
,
8409 simplify_binary_operation (MULT
, mode
, vec3
, series_1_3
));
8410 if (!GET_MODE_NUNITS (mode
).is_constant ())
8411 ASSERT_FALSE (simplify_binary_operation (MULT
, mode
, series_0_1
,
8414 /* Test ASHIFT between constant vectors. */
8415 ASSERT_RTX_EQ (series_0_2
,
8416 simplify_binary_operation (ASHIFT
, mode
, series_0_1
,
8417 CONST1_RTX (mode
)));
8418 if (!GET_MODE_NUNITS (mode
).is_constant ())
8419 ASSERT_FALSE (simplify_binary_operation (ASHIFT
, mode
, CONST1_RTX (mode
),
8424 simplify_merge_mask (rtx x
, rtx mask
, int op
)
8426 return simplify_context ().simplify_merge_mask (x
, mask
, op
);
8429 /* Verify simplify_merge_mask works correctly. */
8432 test_vec_merge (machine_mode mode
)
8434 rtx op0
= make_test_reg (mode
);
8435 rtx op1
= make_test_reg (mode
);
8436 rtx op2
= make_test_reg (mode
);
8437 rtx op3
= make_test_reg (mode
);
8438 rtx op4
= make_test_reg (mode
);
8439 rtx op5
= make_test_reg (mode
);
8440 rtx mask1
= make_test_reg (SImode
);
8441 rtx mask2
= make_test_reg (SImode
);
8442 rtx vm1
= gen_rtx_VEC_MERGE (mode
, op0
, op1
, mask1
);
8443 rtx vm2
= gen_rtx_VEC_MERGE (mode
, op2
, op3
, mask1
);
8444 rtx vm3
= gen_rtx_VEC_MERGE (mode
, op4
, op5
, mask1
);
8446 /* Simple vec_merge. */
8447 ASSERT_EQ (op0
, simplify_merge_mask (vm1
, mask1
, 0));
8448 ASSERT_EQ (op1
, simplify_merge_mask (vm1
, mask1
, 1));
8449 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 0));
8450 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (vm1
, mask2
, 1));
8452 /* Nested vec_merge.
8453 It's tempting to make this simplify right down to opN, but we don't
8454 because all the simplify_* functions assume that the operands have
8455 already been simplified. */
8456 rtx nvm
= gen_rtx_VEC_MERGE (mode
, vm1
, vm2
, mask1
);
8457 ASSERT_EQ (vm1
, simplify_merge_mask (nvm
, mask1
, 0));
8458 ASSERT_EQ (vm2
, simplify_merge_mask (nvm
, mask1
, 1));
8460 /* Intermediate unary op. */
8461 rtx unop
= gen_rtx_NOT (mode
, vm1
);
8462 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op0
),
8463 simplify_merge_mask (unop
, mask1
, 0));
8464 ASSERT_RTX_EQ (gen_rtx_NOT (mode
, op1
),
8465 simplify_merge_mask (unop
, mask1
, 1));
8467 /* Intermediate binary op. */
8468 rtx binop
= gen_rtx_PLUS (mode
, vm1
, vm2
);
8469 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op0
, op2
),
8470 simplify_merge_mask (binop
, mask1
, 0));
8471 ASSERT_RTX_EQ (gen_rtx_PLUS (mode
, op1
, op3
),
8472 simplify_merge_mask (binop
, mask1
, 1));
8474 /* Intermediate ternary op. */
8475 rtx tenop
= gen_rtx_FMA (mode
, vm1
, vm2
, vm3
);
8476 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op0
, op2
, op4
),
8477 simplify_merge_mask (tenop
, mask1
, 0));
8478 ASSERT_RTX_EQ (gen_rtx_FMA (mode
, op1
, op3
, op5
),
8479 simplify_merge_mask (tenop
, mask1
, 1));
8482 rtx badop0
= gen_rtx_PRE_INC (mode
, op0
);
8483 rtx badvm
= gen_rtx_VEC_MERGE (mode
, badop0
, op1
, mask1
);
8484 ASSERT_EQ (badop0
, simplify_merge_mask (badvm
, mask1
, 0));
8485 ASSERT_EQ (NULL_RTX
, simplify_merge_mask (badvm
, mask1
, 1));
8487 /* Called indirectly. */
8488 ASSERT_RTX_EQ (gen_rtx_VEC_MERGE (mode
, op0
, op3
, mask1
),
8489 simplify_rtx (nvm
));
8492 /* Test subregs of integer vector constant X, trying elements in
8493 the range [ELT_BIAS, ELT_BIAS + constant_lower_bound (NELTS)),
8494 where NELTS is the number of elements in X. Subregs involving
8495 elements [ELT_BIAS, ELT_BIAS + FIRST_VALID) are expected to fail. */
8498 test_vector_subregs_modes (rtx x
, poly_uint64 elt_bias
= 0,
8499 unsigned int first_valid
= 0)
8501 machine_mode inner_mode
= GET_MODE (x
);
8502 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
8504 for (unsigned int modei
= 0; modei
< NUM_MACHINE_MODES
; ++modei
)
8506 machine_mode outer_mode
= (machine_mode
) modei
;
8507 if (!VECTOR_MODE_P (outer_mode
))
8510 unsigned int outer_nunits
;
8511 if (GET_MODE_INNER (outer_mode
) == int_mode
8512 && GET_MODE_NUNITS (outer_mode
).is_constant (&outer_nunits
)
8513 && multiple_p (GET_MODE_NUNITS (inner_mode
), outer_nunits
))
8515 /* Test subregs in which the outer mode is a smaller,
8516 constant-sized vector of the same element type. */
8518 = constant_lower_bound (GET_MODE_NUNITS (inner_mode
));
8519 for (unsigned int elt
= 0; elt
< limit
; elt
+= outer_nunits
)
8521 rtx expected
= NULL_RTX
;
8522 if (elt
>= first_valid
)
8524 rtx_vector_builder
builder (outer_mode
, outer_nunits
, 1);
8525 for (unsigned int i
= 0; i
< outer_nunits
; ++i
)
8526 builder
.quick_push (CONST_VECTOR_ELT (x
, elt
+ i
));
8527 expected
= builder
.build ();
8529 poly_uint64 byte
= (elt_bias
+ elt
) * GET_MODE_SIZE (int_mode
);
8530 ASSERT_RTX_EQ (expected
,
8531 simplify_subreg (outer_mode
, x
,
8535 else if (known_eq (GET_MODE_SIZE (outer_mode
),
8536 GET_MODE_SIZE (inner_mode
))
8537 && known_eq (elt_bias
, 0U)
8538 && (GET_MODE_CLASS (outer_mode
) != MODE_VECTOR_BOOL
8539 || known_eq (GET_MODE_BITSIZE (outer_mode
),
8540 GET_MODE_NUNITS (outer_mode
)))
8541 && (!FLOAT_MODE_P (outer_mode
)
8542 || (FLOAT_MODE_FORMAT (outer_mode
)->ieee_bits
8543 == GET_MODE_UNIT_PRECISION (outer_mode
)))
8544 && (GET_MODE_SIZE (inner_mode
).is_constant ()
8545 || !CONST_VECTOR_STEPPED_P (x
)))
8547 /* Try converting to OUTER_MODE and back. */
8548 rtx outer_x
= simplify_subreg (outer_mode
, x
, inner_mode
, 0);
8549 ASSERT_TRUE (outer_x
!= NULL_RTX
);
8550 ASSERT_RTX_EQ (x
, simplify_subreg (inner_mode
, outer_x
,
8555 if (BYTES_BIG_ENDIAN
== WORDS_BIG_ENDIAN
)
8557 /* Test each byte in the element range. */
8559 = constant_lower_bound (GET_MODE_SIZE (inner_mode
));
8560 for (unsigned int i
= 0; i
< limit
; ++i
)
8562 unsigned int elt
= i
/ GET_MODE_SIZE (int_mode
);
8563 rtx expected
= NULL_RTX
;
8564 if (elt
>= first_valid
)
8566 unsigned int byte_shift
= i
% GET_MODE_SIZE (int_mode
);
8567 if (BYTES_BIG_ENDIAN
)
8568 byte_shift
= GET_MODE_SIZE (int_mode
) - byte_shift
- 1;
8569 rtx_mode_t
vec_elt (CONST_VECTOR_ELT (x
, elt
), int_mode
);
8570 wide_int shifted_elt
8571 = wi::lrshift (vec_elt
, byte_shift
* BITS_PER_UNIT
);
8572 expected
= immed_wide_int_const (shifted_elt
, QImode
);
8574 poly_uint64 byte
= elt_bias
* GET_MODE_SIZE (int_mode
) + i
;
8575 ASSERT_RTX_EQ (expected
,
8576 simplify_subreg (QImode
, x
, inner_mode
, byte
));
8581 /* Test constant subregs of integer vector mode INNER_MODE, using 1
8582 element per pattern. */
8585 test_vector_subregs_repeating (machine_mode inner_mode
)
8587 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
8588 unsigned int min_nunits
= constant_lower_bound (nunits
);
8589 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
8590 unsigned int count
= gcd (min_nunits
, 8);
8592 rtx_vector_builder
builder (inner_mode
, count
, 1);
8593 for (unsigned int i
= 0; i
< count
; ++i
)
8594 builder
.quick_push (gen_int_mode (8 - i
, int_mode
));
8595 rtx x
= builder
.build ();
8597 test_vector_subregs_modes (x
);
8598 if (!nunits
.is_constant ())
8599 test_vector_subregs_modes (x
, nunits
- min_nunits
);
8602 /* Test constant subregs of integer vector mode INNER_MODE, using 2
8603 elements per pattern. */
8606 test_vector_subregs_fore_back (machine_mode inner_mode
)
8608 poly_uint64 nunits
= GET_MODE_NUNITS (inner_mode
);
8609 unsigned int min_nunits
= constant_lower_bound (nunits
);
8610 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
8611 unsigned int count
= gcd (min_nunits
, 4);
8613 rtx_vector_builder
builder (inner_mode
, count
, 2);
8614 for (unsigned int i
= 0; i
< count
; ++i
)
8615 builder
.quick_push (gen_int_mode (i
, int_mode
));
8616 for (unsigned int i
= 0; i
< count
; ++i
)
8617 builder
.quick_push (gen_int_mode (-1 - (int) i
, int_mode
));
8618 rtx x
= builder
.build ();
8620 test_vector_subregs_modes (x
);
8621 if (!nunits
.is_constant ())
8622 test_vector_subregs_modes (x
, nunits
- min_nunits
, count
);
8625 /* Test constant subregs of integer vector mode INNER_MODE, using 3
8626 elements per pattern. */
8629 test_vector_subregs_stepped (machine_mode inner_mode
)
8631 /* Build { 0, 1, 2, 3, ... }. */
8632 scalar_mode int_mode
= GET_MODE_INNER (inner_mode
);
8633 rtx_vector_builder
builder (inner_mode
, 1, 3);
8634 for (unsigned int i
= 0; i
< 3; ++i
)
8635 builder
.quick_push (gen_int_mode (i
, int_mode
));
8636 rtx x
= builder
.build ();
8638 test_vector_subregs_modes (x
);
8641 /* Test constant subregs of integer vector mode INNER_MODE. */
8644 test_vector_subregs (machine_mode inner_mode
)
8646 test_vector_subregs_repeating (inner_mode
);
8647 test_vector_subregs_fore_back (inner_mode
);
8648 test_vector_subregs_stepped (inner_mode
);
8651 /* Verify some simplifications involving vectors. */
8656 for (unsigned int i
= 0; i
< NUM_MACHINE_MODES
; ++i
)
8658 machine_mode mode
= (machine_mode
) i
;
8659 if (VECTOR_MODE_P (mode
))
8661 rtx scalar_reg
= make_test_reg (GET_MODE_INNER (mode
));
8662 test_vector_ops_duplicate (mode
, scalar_reg
);
8663 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
8664 && maybe_gt (GET_MODE_NUNITS (mode
), 2))
8666 test_vector_ops_series (mode
, scalar_reg
);
8667 test_vector_subregs (mode
);
8669 test_vec_merge (mode
);
8674 template<unsigned int N
>
8675 struct simplify_const_poly_int_tests
8681 struct simplify_const_poly_int_tests
<1>
8683 static void run () {}
8686 /* Test various CONST_POLY_INT properties. */
8688 template<unsigned int N
>
8690 simplify_const_poly_int_tests
<N
>::run ()
8692 rtx x1
= gen_int_mode (poly_int64 (1, 1), QImode
);
8693 rtx x2
= gen_int_mode (poly_int64 (-80, 127), QImode
);
8694 rtx x3
= gen_int_mode (poly_int64 (-79, -128), QImode
);
8695 rtx x4
= gen_int_mode (poly_int64 (5, 4), QImode
);
8696 rtx x5
= gen_int_mode (poly_int64 (30, 24), QImode
);
8697 rtx x6
= gen_int_mode (poly_int64 (20, 16), QImode
);
8698 rtx x7
= gen_int_mode (poly_int64 (7, 4), QImode
);
8699 rtx x8
= gen_int_mode (poly_int64 (30, 24), HImode
);
8700 rtx x9
= gen_int_mode (poly_int64 (-30, -24), HImode
);
8701 rtx x10
= gen_int_mode (poly_int64 (-31, -24), HImode
);
8702 rtx two
= GEN_INT (2);
8703 rtx six
= GEN_INT (6);
8704 poly_uint64 offset
= subreg_lowpart_offset (QImode
, HImode
);
8706 /* These tests only try limited operation combinations. Fuller arithmetic
8707 testing is done directly on poly_ints. */
8708 ASSERT_EQ (simplify_unary_operation (NEG
, HImode
, x8
, HImode
), x9
);
8709 ASSERT_EQ (simplify_unary_operation (NOT
, HImode
, x8
, HImode
), x10
);
8710 ASSERT_EQ (simplify_unary_operation (TRUNCATE
, QImode
, x8
, HImode
), x5
);
8711 ASSERT_EQ (simplify_binary_operation (PLUS
, QImode
, x1
, x2
), x3
);
8712 ASSERT_EQ (simplify_binary_operation (MINUS
, QImode
, x3
, x1
), x2
);
8713 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, x4
, six
), x5
);
8714 ASSERT_EQ (simplify_binary_operation (MULT
, QImode
, six
, x4
), x5
);
8715 ASSERT_EQ (simplify_binary_operation (ASHIFT
, QImode
, x4
, two
), x6
);
8716 ASSERT_EQ (simplify_binary_operation (IOR
, QImode
, x4
, two
), x7
);
8717 ASSERT_EQ (simplify_subreg (HImode
, x5
, QImode
, 0), x8
);
8718 ASSERT_EQ (simplify_subreg (QImode
, x8
, HImode
, offset
), x5
);
8721 /* Run all of the selftests within this file. */
8724 simplify_rtx_cc_tests ()
8728 simplify_const_poly_int_tests
<NUM_POLY_INT_COEFFS
>::run ();
8731 } // namespace selftest
8733 #endif /* CHECKING_P */