1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
38 #include "hard-reg-set.h"
40 /* Forward declarations */
41 static void set_of_1 (rtx
, const_rtx
, void *);
42 static bool covers_regno_p (const_rtx
, unsigned int);
43 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
44 static int computed_jump_p_1 (const_rtx
);
45 static void parms_set (rtx
, const_rtx
, void *);
47 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
48 const_rtx
, machine_mode
,
49 unsigned HOST_WIDE_INT
);
50 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
51 const_rtx
, machine_mode
,
52 unsigned HOST_WIDE_INT
);
53 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
54 const_rtx
, machine_mode
,
56 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
57 const_rtx
, machine_mode
,
60 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
61 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
63 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
64 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
65 SIGN_EXTEND then while narrowing we also have to enforce the
66 representation and sign-extend the value to mode DESTINATION_REP.
68 If the value is already sign-extended to DESTINATION_REP mode we
69 can just switch to DESTINATION mode on it. For each pair of
70 integral modes SOURCE and DESTINATION, when truncating from SOURCE
71 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
72 contains the number of high-order bits in SOURCE that have to be
73 copies of the sign-bit so that we can do this mode-switch to
77 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
79 /* Store X into index I of ARRAY. ARRAY is known to have at least I
80 elements. Return the new base of ARRAY. */
83 typename
T::value_type
*
84 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
86 size_t i
, value_type x
)
88 if (base
== array
.stack
)
95 gcc_checking_assert (i
== LOCAL_ELEMS
);
96 /* A previous iteration might also have moved from the stack to the
97 heap, in which case the heap array will already be big enough. */
98 if (vec_safe_length (array
.heap
) <= i
)
99 vec_safe_grow (array
.heap
, i
+ 1);
100 base
= array
.heap
->address ();
101 memcpy (base
, array
.stack
, sizeof (array
.stack
));
102 base
[LOCAL_ELEMS
] = x
;
105 unsigned int length
= array
.heap
->length ();
108 gcc_checking_assert (base
== array
.heap
->address ());
114 gcc_checking_assert (i
== length
);
115 vec_safe_push (array
.heap
, x
);
116 return array
.heap
->address ();
120 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
121 number of elements added to the worklist. */
123 template <typename T
>
125 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
127 size_t end
, rtx_type x
)
129 enum rtx_code code
= GET_CODE (x
);
130 const char *format
= GET_RTX_FORMAT (code
);
131 size_t orig_end
= end
;
132 if (__builtin_expect (INSN_P (x
), false))
134 /* Put the pattern at the top of the queue, since that's what
135 we're likely to want most. It also allows for the SEQUENCE
137 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
138 if (format
[i
] == 'e')
140 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
141 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
144 base
= add_single_to_queue (array
, base
, end
++, subx
);
148 for (int i
= 0; format
[i
]; ++i
)
149 if (format
[i
] == 'e')
151 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
152 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
155 base
= add_single_to_queue (array
, base
, end
++, subx
);
157 else if (format
[i
] == 'E')
159 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
160 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
161 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
[end
++] = T::get_value (vec
[j
]);
165 for (unsigned int j
= 0; j
< length
; j
++)
166 base
= add_single_to_queue (array
, base
, end
++,
167 T::get_value (vec
[j
]));
168 if (code
== SEQUENCE
&& end
== length
)
169 /* If the subrtxes of the sequence fill the entire array then
170 we know that no other parts of a containing insn are queued.
171 The caller is therefore iterating over the sequence as a
172 PATTERN (...), so we also want the patterns of the
174 for (unsigned int j
= 0; j
< length
; j
++)
176 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
178 base
[j
] = T::get_value (PATTERN (x
));
181 return end
- orig_end
;
184 template <typename T
>
186 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
188 vec_free (array
.heap
);
191 template <typename T
>
192 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
194 template class generic_subrtx_iterator
<const_rtx_accessor
>;
195 template class generic_subrtx_iterator
<rtx_var_accessor
>;
196 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
198 /* Return 1 if the value of X is unstable
199 (would be different at a different point in the program).
200 The frame pointer, arg pointer, etc. are considered stable
201 (within one function) and so is anything marked `unchanging'. */
204 rtx_unstable_p (const_rtx x
)
206 const RTX_CODE code
= GET_CODE (x
);
213 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
222 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
223 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
224 /* The arg pointer varies if it is not a fixed register. */
225 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
227 /* ??? When call-clobbered, the value is stable modulo the restore
228 that must happen after a call. This currently screws up local-alloc
229 into believing that the restore is not needed. */
230 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
235 if (MEM_VOLATILE_P (x
))
244 fmt
= GET_RTX_FORMAT (code
);
245 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
248 if (rtx_unstable_p (XEXP (x
, i
)))
251 else if (fmt
[i
] == 'E')
254 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
255 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
262 /* Return 1 if X has a value that can vary even between two
263 executions of the program. 0 means X can be compared reliably
264 against certain constants or near-constants.
265 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
266 zero, we are slightly more conservative.
267 The frame pointer and the arg pointer are considered constant. */
270 rtx_varies_p (const_rtx x
, bool for_alias
)
283 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
292 /* Note that we have to test for the actual rtx used for the frame
293 and arg pointers and not just the register number in case we have
294 eliminated the frame and/or arg pointer and are using it
296 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
297 /* The arg pointer varies if it is not a fixed register. */
298 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
300 if (x
== pic_offset_table_rtx
301 /* ??? When call-clobbered, the value is stable modulo the restore
302 that must happen after a call. This currently screws up
303 local-alloc into believing that the restore is not needed, so we
304 must return 0 only if we are called from alias analysis. */
305 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
310 /* The operand 0 of a LO_SUM is considered constant
311 (in fact it is related specifically to operand 1)
312 during alias analysis. */
313 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
314 || rtx_varies_p (XEXP (x
, 1), for_alias
);
317 if (MEM_VOLATILE_P (x
))
326 fmt
= GET_RTX_FORMAT (code
);
327 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
330 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
333 else if (fmt
[i
] == 'E')
336 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
337 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
344 /* Compute an approximation for the offset between the register
345 FROM and TO for the current function, as it was at the start
349 get_initial_register_offset (int from
, int to
)
351 static const struct elim_table_t
355 } table
[] = ELIMINABLE_REGS
;
356 poly_int64 offset1
, offset2
;
362 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
363 is completed, but we need to give at least an estimate for the stack
364 pointer based on the frame size. */
365 if (!epilogue_completed
)
367 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
368 #if !STACK_GROWS_DOWNWARD
371 if (to
== STACK_POINTER_REGNUM
)
373 else if (from
== STACK_POINTER_REGNUM
)
379 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
380 if (table
[i
].from
== from
)
382 if (table
[i
].to
== to
)
384 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
388 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
390 if (table
[j
].to
== to
391 && table
[j
].from
== table
[i
].to
)
393 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
395 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
397 return offset1
+ offset2
;
399 if (table
[j
].from
== to
400 && table
[j
].to
== table
[i
].to
)
402 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
404 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
406 return offset1
- offset2
;
410 else if (table
[i
].to
== from
)
412 if (table
[i
].from
== to
)
414 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
418 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
420 if (table
[j
].to
== to
421 && table
[j
].from
== table
[i
].from
)
423 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
425 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
427 return - offset1
+ offset2
;
429 if (table
[j
].from
== to
430 && table
[j
].to
== table
[i
].from
)
432 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
434 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
436 return - offset1
- offset2
;
441 /* If the requested register combination was not found,
442 try a different more simple combination. */
443 if (from
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
445 else if (to
== ARG_POINTER_REGNUM
)
446 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
447 else if (from
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
449 else if (to
== HARD_FRAME_POINTER_REGNUM
)
450 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
455 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
456 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
457 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
458 references on strict alignment machines. */
461 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
462 machine_mode mode
, bool unaligned_mems
)
464 enum rtx_code code
= GET_CODE (x
);
465 gcc_checking_assert (mode
== BLKmode
|| known_size_p (size
));
468 /* The offset must be a multiple of the mode size if we are considering
469 unaligned memory references on strict alignment machines. */
470 if (STRICT_ALIGNMENT
&& unaligned_mems
&& mode
!= BLKmode
)
472 poly_int64 actual_offset
= offset
;
474 #ifdef SPARC_STACK_BOUNDARY_HACK
475 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
476 the real alignment of %sp. However, when it does this, the
477 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
478 if (SPARC_STACK_BOUNDARY_HACK
479 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
480 actual_offset
-= STACK_POINTER_OFFSET
;
483 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
490 if (SYMBOL_REF_WEAK (x
))
492 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
495 poly_int64 decl_size
;
497 if (maybe_lt (offset
, 0))
499 if (!known_size_p (size
))
500 return maybe_ne (offset
, 0);
502 /* If the size of the access or of the symbol is unknown,
504 decl
= SYMBOL_REF_DECL (x
);
506 /* Else check that the access is in bounds. TODO: restructure
507 expr_size/tree_expr_size/int_expr_size and just use the latter. */
510 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
512 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
515 else if (TREE_CODE (decl
) == STRING_CST
)
516 decl_size
= TREE_STRING_LENGTH (decl
);
517 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
518 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
522 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
523 ? maybe_ne (offset
, 0)
524 : !known_subrange_p (offset
, size
, 0, decl_size
));
533 /* Stack references are assumed not to trap, but we need to deal with
534 nonsensical offsets. */
535 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
536 || x
== stack_pointer_rtx
537 /* The arg pointer varies if it is not a fixed register. */
538 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
541 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
543 poly_int64 red_zone_size
= 0;
545 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
546 poly_int64 low_bound
, high_bound
;
548 if (!known_size_p (size
))
551 if (x
== frame_pointer_rtx
)
553 if (FRAME_GROWS_DOWNWARD
)
555 high_bound
= targetm
.starting_frame_offset ();
556 low_bound
= high_bound
- get_frame_size ();
560 low_bound
= targetm
.starting_frame_offset ();
561 high_bound
= low_bound
+ get_frame_size ();
564 else if (x
== hard_frame_pointer_rtx
)
567 = get_initial_register_offset (STACK_POINTER_REGNUM
,
568 HARD_FRAME_POINTER_REGNUM
);
570 = get_initial_register_offset (ARG_POINTER_REGNUM
,
571 HARD_FRAME_POINTER_REGNUM
);
573 #if STACK_GROWS_DOWNWARD
574 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
575 high_bound
= ap_offset
576 + FIRST_PARM_OFFSET (current_function_decl
)
577 #if !ARGS_GROW_DOWNWARD
582 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
583 low_bound
= ap_offset
584 + FIRST_PARM_OFFSET (current_function_decl
)
585 #if ARGS_GROW_DOWNWARD
591 else if (x
== stack_pointer_rtx
)
594 = get_initial_register_offset (ARG_POINTER_REGNUM
,
595 STACK_POINTER_REGNUM
);
597 #if STACK_GROWS_DOWNWARD
598 low_bound
= - red_zone_size
- stack_boundary
;
599 high_bound
= ap_offset
600 + FIRST_PARM_OFFSET (current_function_decl
)
601 #if !ARGS_GROW_DOWNWARD
606 high_bound
= red_zone_size
+ stack_boundary
;
607 low_bound
= ap_offset
608 + FIRST_PARM_OFFSET (current_function_decl
)
609 #if ARGS_GROW_DOWNWARD
617 /* We assume that accesses are safe to at least the
619 Examples are varargs and __builtin_return_address. */
620 #if ARGS_GROW_DOWNWARD
621 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
623 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 - crtl
->args
.size
- stack_boundary
;
626 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
628 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
629 + crtl
->args
.size
+ stack_boundary
;
633 if (known_ge (offset
, low_bound
)
634 && known_le (offset
, high_bound
- size
))
638 /* All of the virtual frame registers are stack references. */
639 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
640 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
645 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
646 mode
, unaligned_mems
);
649 /* An address is assumed not to trap if:
650 - it is the pic register plus a const unspec without offset. */
651 if (XEXP (x
, 0) == pic_offset_table_rtx
652 && GET_CODE (XEXP (x
, 1)) == CONST
653 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
654 && known_eq (offset
, 0))
657 /* - or it is an address that can't trap plus a constant integer. */
658 if (poly_int_rtx_p (XEXP (x
, 1), &const_x1
)
659 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ const_x1
,
660 size
, mode
, unaligned_mems
))
667 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
668 mode
, unaligned_mems
);
675 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
676 mode
, unaligned_mems
);
682 /* If it isn't one of the case above, it can cause a trap. */
686 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
689 rtx_addr_can_trap_p (const_rtx x
)
691 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
694 /* Return true if X contains a MEM subrtx. */
697 contains_mem_rtx_p (rtx x
)
699 subrtx_iterator::array_type array
;
700 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
707 /* Return true if X is an address that is known to not be zero. */
710 nonzero_address_p (const_rtx x
)
712 const enum rtx_code code
= GET_CODE (x
);
717 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
723 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
724 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
725 || x
== stack_pointer_rtx
726 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
728 /* All of the virtual frame registers are stack references. */
729 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
730 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
735 return nonzero_address_p (XEXP (x
, 0));
738 /* Handle PIC references. */
739 if (XEXP (x
, 0) == pic_offset_table_rtx
740 && CONSTANT_P (XEXP (x
, 1)))
745 /* Similar to the above; allow positive offsets. Further, since
746 auto-inc is only allowed in memories, the register must be a
748 if (CONST_INT_P (XEXP (x
, 1))
749 && INTVAL (XEXP (x
, 1)) > 0)
751 return nonzero_address_p (XEXP (x
, 0));
754 /* Similarly. Further, the offset is always positive. */
761 return nonzero_address_p (XEXP (x
, 0));
764 return nonzero_address_p (XEXP (x
, 1));
770 /* If it isn't one of the case above, might be zero. */
774 /* Return 1 if X refers to a memory location whose address
775 cannot be compared reliably with constant addresses,
776 or if X refers to a BLKmode memory object.
777 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
778 zero, we are slightly more conservative. */
781 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
792 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
794 fmt
= GET_RTX_FORMAT (code
);
795 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
798 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
801 else if (fmt
[i
] == 'E')
804 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
805 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
811 /* Return the CALL in X if there is one. */
814 get_call_rtx_from (rtx x
)
818 if (GET_CODE (x
) == PARALLEL
)
819 x
= XVECEXP (x
, 0, 0);
820 if (GET_CODE (x
) == SET
)
822 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
827 /* Return the value of the integer term in X, if one is apparent;
829 Only obvious integer terms are detected.
830 This is used in cse.c with the `related_value' field. */
833 get_integer_term (const_rtx x
)
835 if (GET_CODE (x
) == CONST
)
838 if (GET_CODE (x
) == MINUS
839 && CONST_INT_P (XEXP (x
, 1)))
840 return - INTVAL (XEXP (x
, 1));
841 if (GET_CODE (x
) == PLUS
842 && CONST_INT_P (XEXP (x
, 1)))
843 return INTVAL (XEXP (x
, 1));
847 /* If X is a constant, return the value sans apparent integer term;
849 Only obvious integer terms are detected. */
852 get_related_value (const_rtx x
)
854 if (GET_CODE (x
) != CONST
)
857 if (GET_CODE (x
) == PLUS
858 && CONST_INT_P (XEXP (x
, 1)))
860 else if (GET_CODE (x
) == MINUS
861 && CONST_INT_P (XEXP (x
, 1)))
866 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
867 to somewhere in the same object or object_block as SYMBOL. */
870 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
874 if (GET_CODE (symbol
) != SYMBOL_REF
)
882 if (CONSTANT_POOL_ADDRESS_P (symbol
)
883 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
886 decl
= SYMBOL_REF_DECL (symbol
);
887 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
891 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
892 && SYMBOL_REF_BLOCK (symbol
)
893 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
894 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
895 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
901 /* Split X into a base and a constant offset, storing them in *BASE_OUT
902 and *OFFSET_OUT respectively. */
905 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
907 if (GET_CODE (x
) == CONST
)
910 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
912 *base_out
= XEXP (x
, 0);
913 *offset_out
= XEXP (x
, 1);
918 *offset_out
= const0_rtx
;
921 /* Express integer value X as some value Y plus a polynomial offset,
922 where Y is either const0_rtx, X or something within X (as opposed
923 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
926 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
928 rtx base
= const0_rtx
;
930 if (GET_CODE (test
) == CONST
)
931 test
= XEXP (test
, 0);
932 if (GET_CODE (test
) == PLUS
)
934 base
= XEXP (test
, 0);
935 test
= XEXP (test
, 1);
937 if (poly_int_rtx_p (test
, offset_out
))
943 /* Return the argument size in REG_ARGS_SIZE note X. */
946 get_args_size (const_rtx x
)
948 gcc_checking_assert (REG_NOTE_KIND (x
) == REG_ARGS_SIZE
);
949 return rtx_to_poly_int64 (XEXP (x
, 0));
952 /* Return the number of places FIND appears within X. If COUNT_DEST is
953 zero, we do not count occurrences inside the destination of a SET. */
956 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
960 const char *format_ptr
;
979 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
981 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
985 if (MEM_P (find
) && rtx_equal_p (x
, find
))
990 if (SET_DEST (x
) == find
&& ! count_dest
)
991 return count_occurrences (SET_SRC (x
), find
, count_dest
);
998 format_ptr
= GET_RTX_FORMAT (code
);
1001 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
1003 switch (*format_ptr
++)
1006 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
1010 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1011 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1019 /* Return TRUE if OP is a register or subreg of a register that
1020 holds an unsigned quantity. Otherwise, return FALSE. */
1023 unsigned_reg_p (rtx op
)
1027 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1030 if (GET_CODE (op
) == SUBREG
1031 && SUBREG_PROMOTED_SIGN (op
))
1038 /* Nonzero if register REG appears somewhere within IN.
1039 Also works if REG is not a register; in this case it checks
1040 for a subexpression of IN that is Lisp "equal" to REG. */
1043 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1055 if (GET_CODE (in
) == LABEL_REF
)
1056 return reg
== label_ref_label (in
);
1058 code
= GET_CODE (in
);
1062 /* Compare registers by number. */
1064 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1066 /* These codes have no constituent expressions
1074 /* These are kept unique for a given value. */
1081 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1084 fmt
= GET_RTX_FORMAT (code
);
1086 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1091 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1092 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1095 else if (fmt
[i
] == 'e'
1096 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1102 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1103 no CODE_LABEL insn. */
1106 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1111 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1117 /* Nonzero if register REG is used in an insn between
1118 FROM_INSN and TO_INSN (exclusive of those two). */
1121 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1122 const rtx_insn
*to_insn
)
1126 if (from_insn
== to_insn
)
1129 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1130 if (NONDEBUG_INSN_P (insn
)
1131 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1132 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1137 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1138 is entirely replaced by a new value and the only use is as a SET_DEST,
1139 we do not consider it a reference. */
1142 reg_referenced_p (const_rtx x
, const_rtx body
)
1146 switch (GET_CODE (body
))
1149 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1152 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1153 of a REG that occupies all of the REG, the insn references X if
1154 it is mentioned in the destination. */
1155 if (GET_CODE (SET_DEST (body
)) != CC0
1156 && GET_CODE (SET_DEST (body
)) != PC
1157 && !REG_P (SET_DEST (body
))
1158 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1159 && REG_P (SUBREG_REG (SET_DEST (body
)))
1160 && !read_modify_subreg_p (SET_DEST (body
)))
1161 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1166 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1167 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1174 return reg_overlap_mentioned_p (x
, body
);
1177 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1180 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1183 case UNSPEC_VOLATILE
:
1184 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1185 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1190 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1191 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1196 if (MEM_P (XEXP (body
, 0)))
1197 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1202 gcc_assert (REG_P (XEXP (body
, 0)));
1206 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1208 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1215 /* Nonzero if register REG is set or clobbered in an insn between
1216 FROM_INSN and TO_INSN (exclusive of those two). */
1219 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1220 const rtx_insn
*to_insn
)
1222 const rtx_insn
*insn
;
1224 if (from_insn
== to_insn
)
1227 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1228 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1233 /* Return true if REG is set or clobbered inside INSN. */
1236 reg_set_p (const_rtx reg
, const_rtx insn
)
1238 /* After delay slot handling, call and branch insns might be in a
1239 sequence. Check all the elements there. */
1240 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1242 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1243 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1249 /* We can be passed an insn or part of one. If we are passed an insn,
1250 check if a side-effect of the insn clobbers REG. */
1252 && (FIND_REG_INC_NOTE (insn
, reg
)
1255 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1256 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1257 GET_MODE (reg
), REGNO (reg
)))
1259 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1262 /* There are no REG_INC notes for SP autoinc. */
1263 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1265 subrtx_var_iterator::array_type array
;
1266 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1271 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1273 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1275 iter
.skip_subrtxes ();
1280 return set_of (reg
, insn
) != NULL_RTX
;
1283 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1284 only if none of them are modified between START and END. Return 1 if
1285 X contains a MEM; this routine does use memory aliasing. */
1288 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1290 const enum rtx_code code
= GET_CODE (x
);
1311 if (modified_between_p (XEXP (x
, 0), start
, end
))
1313 if (MEM_READONLY_P (x
))
1315 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1316 if (memory_modified_in_insn_p (x
, insn
))
1321 return reg_set_between_p (x
, start
, end
);
1327 fmt
= GET_RTX_FORMAT (code
);
1328 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1330 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1333 else if (fmt
[i
] == 'E')
1334 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1335 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1342 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1343 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1344 does use memory aliasing. */
1347 modified_in_p (const_rtx x
, const_rtx insn
)
1349 const enum rtx_code code
= GET_CODE (x
);
1366 if (modified_in_p (XEXP (x
, 0), insn
))
1368 if (MEM_READONLY_P (x
))
1370 if (memory_modified_in_insn_p (x
, insn
))
1375 return reg_set_p (x
, insn
);
1381 fmt
= GET_RTX_FORMAT (code
);
1382 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1384 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1387 else if (fmt
[i
] == 'E')
1388 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1389 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1396 /* Return true if X is a SUBREG and if storing a value to X would
1397 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1398 target, using a SUBREG to store to one half of a DImode REG would
1399 preserve the other half. */
1402 read_modify_subreg_p (const_rtx x
)
1404 if (GET_CODE (x
) != SUBREG
)
1406 poly_uint64 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1407 poly_uint64 osize
= GET_MODE_SIZE (GET_MODE (x
));
1408 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1409 /* The inner and outer modes of a subreg must be ordered, so that we
1410 can tell whether they're paradoxical or partial. */
1411 gcc_checking_assert (ordered_p (isize
, osize
));
1412 return (maybe_gt (isize
, osize
) && maybe_gt (isize
, regsize
));
1415 /* Helper function for set_of. */
1423 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1425 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1426 if (rtx_equal_p (x
, data
->pat
)
1427 || (GET_CODE (pat
) == CLOBBER_HIGH
1428 && REGNO(data
->pat
) == REGNO(XEXP (pat
, 0))
1429 && reg_is_clobbered_by_clobber_high (data
->pat
, XEXP (pat
, 0)))
1430 || (GET_CODE (pat
) != CLOBBER_HIGH
&& !MEM_P (x
)
1431 && reg_overlap_mentioned_p (data
->pat
, x
)))
1435 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1436 (either directly or via STRICT_LOW_PART and similar modifiers). */
1438 set_of (const_rtx pat
, const_rtx insn
)
1440 struct set_of_data data
;
1441 data
.found
= NULL_RTX
;
1443 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1447 /* Add all hard register in X to *PSET. */
1449 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1451 subrtx_iterator::array_type array
;
1452 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1454 const_rtx x
= *iter
;
1455 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1456 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1460 /* This function, called through note_stores, collects sets and
1461 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1464 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1466 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1467 if (REG_P (x
) && HARD_REGISTER_P (x
))
1468 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1471 /* Examine INSN, and compute the set of hard registers written by it.
1472 Store it in *PSET. Should only be called after reload. */
1474 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1478 CLEAR_HARD_REG_SET (*pset
);
1479 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1483 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1485 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1486 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1488 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1489 if (REG_NOTE_KIND (link
) == REG_INC
)
1490 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1493 /* Like record_hard_reg_sets, but called through note_uses. */
1495 record_hard_reg_uses (rtx
*px
, void *data
)
1497 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1500 /* Given an INSN, return a SET expression if this insn has only a single SET.
1501 It may also have CLOBBERs, USEs, or SET whose output
1502 will not be used, which we ignore. */
1505 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1508 int set_verified
= 1;
1511 if (GET_CODE (pat
) == PARALLEL
)
1513 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1515 rtx sub
= XVECEXP (pat
, 0, i
);
1516 switch (GET_CODE (sub
))
1524 /* We can consider insns having multiple sets, where all
1525 but one are dead as single set insns. In common case
1526 only single set is present in the pattern so we want
1527 to avoid checking for REG_UNUSED notes unless necessary.
1529 When we reach set first time, we just expect this is
1530 the single set we are looking for and only when more
1531 sets are found in the insn, we check them. */
1534 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1535 && !side_effects_p (set
))
1541 set
= sub
, set_verified
= 0;
1542 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1543 || side_effects_p (sub
))
1555 /* Given an INSN, return nonzero if it has more than one SET, else return
1559 multiple_sets (const_rtx insn
)
1564 /* INSN must be an insn. */
1565 if (! INSN_P (insn
))
1568 /* Only a PARALLEL can have multiple SETs. */
1569 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1571 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1572 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1574 /* If we have already found a SET, then return now. */
1582 /* Either zero or one SET. */
1586 /* Return nonzero if the destination of SET equals the source
1587 and there are no side effects. */
1590 set_noop_p (const_rtx set
)
1592 rtx src
= SET_SRC (set
);
1593 rtx dst
= SET_DEST (set
);
1595 if (dst
== pc_rtx
&& src
== pc_rtx
)
1598 if (MEM_P (dst
) && MEM_P (src
))
1599 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1601 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1602 return rtx_equal_p (XEXP (dst
, 0), src
)
1603 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1604 && !side_effects_p (src
);
1606 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1607 dst
= XEXP (dst
, 0);
1609 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1611 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1613 src
= SUBREG_REG (src
);
1614 dst
= SUBREG_REG (dst
);
1617 /* It is a NOOP if destination overlaps with selected src vector
1619 if (GET_CODE (src
) == VEC_SELECT
1620 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1621 && HARD_REGISTER_P (XEXP (src
, 0))
1622 && HARD_REGISTER_P (dst
))
1625 rtx par
= XEXP (src
, 1);
1626 rtx src0
= XEXP (src
, 0);
1627 poly_int64 c0
= rtx_to_poly_int64 (XVECEXP (par
, 0, 0));
1628 poly_int64 offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1630 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1631 if (maybe_ne (rtx_to_poly_int64 (XVECEXP (par
, 0, i
)), c0
+ i
))
1634 REG_CAN_CHANGE_MODE_P (REGNO (dst
), GET_MODE (src0
), GET_MODE (dst
))
1635 && simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1636 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1639 return (REG_P (src
) && REG_P (dst
)
1640 && REGNO (src
) == REGNO (dst
));
1643 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1647 noop_move_p (const rtx_insn
*insn
)
1649 rtx pat
= PATTERN (insn
);
1651 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1654 /* Insns carrying these notes are useful later on. */
1655 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1658 /* Check the code to be executed for COND_EXEC. */
1659 if (GET_CODE (pat
) == COND_EXEC
)
1660 pat
= COND_EXEC_CODE (pat
);
1662 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1665 if (GET_CODE (pat
) == PARALLEL
)
1668 /* If nothing but SETs of registers to themselves,
1669 this insn can also be deleted. */
1670 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1672 rtx tem
= XVECEXP (pat
, 0, i
);
1674 if (GET_CODE (tem
) == USE
1675 || GET_CODE (tem
) == CLOBBER
1676 || GET_CODE (tem
) == CLOBBER_HIGH
)
1679 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1689 /* Return nonzero if register in range [REGNO, ENDREGNO)
1690 appears either explicitly or implicitly in X
1691 other than being stored into.
1693 References contained within the substructure at LOC do not count.
1694 LOC may be zero, meaning don't ignore anything. */
1697 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1701 unsigned int x_regno
;
1706 /* The contents of a REG_NONNEG note is always zero, so we must come here
1707 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1711 code
= GET_CODE (x
);
1716 x_regno
= REGNO (x
);
1718 /* If we modifying the stack, frame, or argument pointer, it will
1719 clobber a virtual register. In fact, we could be more precise,
1720 but it isn't worth it. */
1721 if ((x_regno
== STACK_POINTER_REGNUM
1722 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1723 && x_regno
== ARG_POINTER_REGNUM
)
1724 || x_regno
== FRAME_POINTER_REGNUM
)
1725 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1728 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1731 /* If this is a SUBREG of a hard reg, we can see exactly which
1732 registers are being modified. Otherwise, handle normally. */
1733 if (REG_P (SUBREG_REG (x
))
1734 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1736 unsigned int inner_regno
= subreg_regno (x
);
1737 unsigned int inner_endregno
1738 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1739 ? subreg_nregs (x
) : 1);
1741 return endregno
> inner_regno
&& regno
< inner_endregno
;
1747 if (&SET_DEST (x
) != loc
1748 /* Note setting a SUBREG counts as referring to the REG it is in for
1749 a pseudo but not for hard registers since we can
1750 treat each word individually. */
1751 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1752 && loc
!= &SUBREG_REG (SET_DEST (x
))
1753 && REG_P (SUBREG_REG (SET_DEST (x
)))
1754 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1755 && refers_to_regno_p (regno
, endregno
,
1756 SUBREG_REG (SET_DEST (x
)), loc
))
1757 || (!REG_P (SET_DEST (x
))
1758 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1761 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1770 /* X does not match, so try its subexpressions. */
1772 fmt
= GET_RTX_FORMAT (code
);
1773 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1775 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1783 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1786 else if (fmt
[i
] == 'E')
1789 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1790 if (loc
!= &XVECEXP (x
, i
, j
)
1791 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1798 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1799 we check if any register number in X conflicts with the relevant register
1800 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1801 contains a MEM (we don't bother checking for memory addresses that can't
1802 conflict because we expect this to be a rare case. */
1805 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1807 unsigned int regno
, endregno
;
1809 /* If either argument is a constant, then modifying X cannot
1810 affect IN. Here we look at IN, we can profitably combine
1811 CONSTANT_P (x) with the switch statement below. */
1812 if (CONSTANT_P (in
))
1816 switch (GET_CODE (x
))
1819 case STRICT_LOW_PART
:
1822 /* Overly conservative. */
1827 regno
= REGNO (SUBREG_REG (x
));
1828 if (regno
< FIRST_PSEUDO_REGISTER
)
1829 regno
= subreg_regno (x
);
1830 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1831 ? subreg_nregs (x
) : 1);
1836 endregno
= END_REGNO (x
);
1838 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1848 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1849 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1852 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1855 else if (fmt
[i
] == 'E')
1858 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1859 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1869 return reg_mentioned_p (x
, in
);
1875 /* If any register in here refers to it we return true. */
1876 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1877 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1878 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1884 gcc_assert (CONSTANT_P (x
));
1889 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1890 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1891 ignored by note_stores, but passed to FUN.
1893 FUN receives three arguments:
1894 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1895 2. the SET or CLOBBER rtx that does the store,
1896 3. the pointer DATA provided to note_stores.
1898 If the item being stored in or clobbered is a SUBREG of a hard register,
1899 the SUBREG will be passed. */
1902 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1906 if (GET_CODE (x
) == COND_EXEC
)
1907 x
= COND_EXEC_CODE (x
);
1909 if (GET_CODE (x
) == SET
1910 || GET_CODE (x
) == CLOBBER
1911 || GET_CODE (x
) == CLOBBER_HIGH
)
1913 rtx dest
= SET_DEST (x
);
1915 while ((GET_CODE (dest
) == SUBREG
1916 && (!REG_P (SUBREG_REG (dest
))
1917 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1918 || GET_CODE (dest
) == ZERO_EXTRACT
1919 || GET_CODE (dest
) == STRICT_LOW_PART
)
1920 dest
= XEXP (dest
, 0);
1922 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1923 each of whose first operand is a register. */
1924 if (GET_CODE (dest
) == PARALLEL
)
1926 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1927 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1928 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1931 (*fun
) (dest
, x
, data
);
1934 else if (GET_CODE (x
) == PARALLEL
)
1935 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1936 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1939 /* Like notes_stores, but call FUN for each expression that is being
1940 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1941 FUN for each expression, not any interior subexpressions. FUN receives a
1942 pointer to the expression and the DATA passed to this function.
1944 Note that this is not quite the same test as that done in reg_referenced_p
1945 since that considers something as being referenced if it is being
1946 partially set, while we do not. */
1949 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1954 switch (GET_CODE (body
))
1957 (*fun
) (&COND_EXEC_TEST (body
), data
);
1958 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1962 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1963 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1967 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1968 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1972 (*fun
) (&XEXP (body
, 0), data
);
1976 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1977 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1981 (*fun
) (&TRAP_CONDITION (body
), data
);
1985 (*fun
) (&XEXP (body
, 0), data
);
1989 case UNSPEC_VOLATILE
:
1990 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1991 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1995 if (MEM_P (XEXP (body
, 0)))
1996 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
2001 rtx dest
= SET_DEST (body
);
2003 /* For sets we replace everything in source plus registers in memory
2004 expression in store and operands of a ZERO_EXTRACT. */
2005 (*fun
) (&SET_SRC (body
), data
);
2007 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2009 (*fun
) (&XEXP (dest
, 1), data
);
2010 (*fun
) (&XEXP (dest
, 2), data
);
2013 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
2014 dest
= XEXP (dest
, 0);
2017 (*fun
) (&XEXP (dest
, 0), data
);
2022 /* All the other possibilities never store. */
2023 (*fun
) (pbody
, data
);
2028 /* Return nonzero if X's old contents don't survive after INSN.
2029 This will be true if X is (cc0) or if X is a register and
2030 X dies in INSN or because INSN entirely sets X.
2032 "Entirely set" means set directly and not through a SUBREG, or
2033 ZERO_EXTRACT, so no trace of the old contents remains.
2034 Likewise, REG_INC does not count.
2036 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2037 but for this use that makes no difference, since regs don't overlap
2038 during their lifetimes. Therefore, this function may be used
2039 at any time after deaths have been computed.
2041 If REG is a hard reg that occupies multiple machine registers, this
2042 function will only return 1 if each of those registers will be replaced
2046 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2048 unsigned int regno
, end_regno
;
2051 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2052 if (GET_CODE (x
) == CC0
)
2055 gcc_assert (REG_P (x
));
2058 end_regno
= END_REGNO (x
);
2059 for (i
= regno
; i
< end_regno
; i
++)
2060 if (! dead_or_set_regno_p (insn
, i
))
2066 /* Return TRUE iff DEST is a register or subreg of a register, is a
2067 complete rather than read-modify-write destination, and contains
2068 register TEST_REGNO. */
2071 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2073 unsigned int regno
, endregno
;
2075 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2076 dest
= SUBREG_REG (dest
);
2081 regno
= REGNO (dest
);
2082 endregno
= END_REGNO (dest
);
2083 return (test_regno
>= regno
&& test_regno
< endregno
);
2086 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2087 any member matches the covers_regno_no_parallel_p criteria. */
2090 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2092 if (GET_CODE (dest
) == PARALLEL
)
2094 /* Some targets place small structures in registers for return
2095 values of functions, and those registers are wrapped in
2096 PARALLELs that we may see as the destination of a SET. */
2099 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2101 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2102 if (inner
!= NULL_RTX
2103 && covers_regno_no_parallel_p (inner
, test_regno
))
2110 return covers_regno_no_parallel_p (dest
, test_regno
);
2113 /* Utility function for dead_or_set_p to check an individual register. */
2116 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2120 /* See if there is a death note for something that includes TEST_REGNO. */
2121 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2125 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2128 pattern
= PATTERN (insn
);
2130 /* If a COND_EXEC is not executed, the value survives. */
2131 if (GET_CODE (pattern
) == COND_EXEC
)
2134 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2135 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2136 else if (GET_CODE (pattern
) == PARALLEL
)
2140 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2142 rtx body
= XVECEXP (pattern
, 0, i
);
2144 if (GET_CODE (body
) == COND_EXEC
)
2145 body
= COND_EXEC_CODE (body
);
2147 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2148 && covers_regno_p (SET_DEST (body
), test_regno
))
2156 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2157 If DATUM is nonzero, look for one whose datum is DATUM. */
2160 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2164 gcc_checking_assert (insn
);
2166 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2167 if (! INSN_P (insn
))
2171 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2172 if (REG_NOTE_KIND (link
) == kind
)
2177 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2178 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2183 /* Return the reg-note of kind KIND in insn INSN which applies to register
2184 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2185 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2186 it might be the case that the note overlaps REGNO. */
2189 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2193 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2194 if (! INSN_P (insn
))
2197 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2198 if (REG_NOTE_KIND (link
) == kind
2199 /* Verify that it is a register, so that scratch and MEM won't cause a
2201 && REG_P (XEXP (link
, 0))
2202 && REGNO (XEXP (link
, 0)) <= regno
2203 && END_REGNO (XEXP (link
, 0)) > regno
)
2208 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2212 find_reg_equal_equiv_note (const_rtx insn
)
2219 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2220 if (REG_NOTE_KIND (link
) == REG_EQUAL
2221 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2223 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2224 insns that have multiple sets. Checking single_set to
2225 make sure of this is not the proper check, as explained
2226 in the comment in set_unique_reg_note.
2228 This should be changed into an assert. */
2229 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2236 /* Check whether INSN is a single_set whose source is known to be
2237 equivalent to a constant. Return that constant if so, otherwise
2241 find_constant_src (const rtx_insn
*insn
)
2245 set
= single_set (insn
);
2248 x
= avoid_constant_pool_reference (SET_SRC (set
));
2253 note
= find_reg_equal_equiv_note (insn
);
2254 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2255 return XEXP (note
, 0);
2260 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2261 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2264 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2266 /* If it's not a CALL_INSN, it can't possibly have a
2267 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2277 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2279 link
= XEXP (link
, 1))
2280 if (GET_CODE (XEXP (link
, 0)) == code
2281 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2286 unsigned int regno
= REGNO (datum
);
2288 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2289 to pseudo registers, so don't bother checking. */
2291 if (regno
< FIRST_PSEUDO_REGISTER
)
2293 unsigned int end_regno
= END_REGNO (datum
);
2296 for (i
= regno
; i
< end_regno
; i
++)
2297 if (find_regno_fusage (insn
, code
, i
))
2305 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2306 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2309 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2313 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2314 to pseudo registers, so don't bother checking. */
2316 if (regno
>= FIRST_PSEUDO_REGISTER
2320 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2324 if (GET_CODE (op
= XEXP (link
, 0)) == code
2325 && REG_P (reg
= XEXP (op
, 0))
2326 && REGNO (reg
) <= regno
2327 && END_REGNO (reg
) > regno
)
2335 /* Return true if KIND is an integer REG_NOTE. */
2338 int_reg_note_p (enum reg_note kind
)
2340 return kind
== REG_BR_PROB
;
2343 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2344 stored as the pointer to the next register note. */
2347 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2351 gcc_checking_assert (!int_reg_note_p (kind
));
2356 case REG_LABEL_TARGET
:
2357 case REG_LABEL_OPERAND
:
2359 /* These types of register notes use an INSN_LIST rather than an
2360 EXPR_LIST, so that copying is done right and dumps look
2362 note
= alloc_INSN_LIST (datum
, list
);
2363 PUT_REG_NOTE_KIND (note
, kind
);
2367 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2374 /* Add register note with kind KIND and datum DATUM to INSN. */
2377 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2379 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2382 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2385 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2387 gcc_checking_assert (int_reg_note_p (kind
));
2388 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2389 datum
, REG_NOTES (insn
));
2392 /* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2395 add_args_size_note (rtx_insn
*insn
, poly_int64 value
)
2397 gcc_checking_assert (!find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
));
2398 add_reg_note (insn
, REG_ARGS_SIZE
, gen_int_mode (value
, Pmode
));
2401 /* Add a register note like NOTE to INSN. */
2404 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2406 if (GET_CODE (note
) == INT_LIST
)
2407 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2409 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2412 /* Duplicate NOTE and return the copy. */
2414 duplicate_reg_note (rtx note
)
2416 reg_note kind
= REG_NOTE_KIND (note
);
2418 if (GET_CODE (note
) == INT_LIST
)
2419 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2420 else if (GET_CODE (note
) == EXPR_LIST
)
2421 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2423 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2426 /* Remove register note NOTE from the REG_NOTES of INSN. */
2429 remove_note (rtx_insn
*insn
, const_rtx note
)
2433 if (note
== NULL_RTX
)
2436 if (REG_NOTES (insn
) == note
)
2437 REG_NOTES (insn
) = XEXP (note
, 1);
2439 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2440 if (XEXP (link
, 1) == note
)
2442 XEXP (link
, 1) = XEXP (note
, 1);
2446 switch (REG_NOTE_KIND (note
))
2450 df_notes_rescan (insn
);
2457 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2458 Return true if any note has been removed. */
2461 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2466 loc
= ®_NOTES (insn
);
2469 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2470 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2472 *loc
= XEXP (*loc
, 1);
2476 loc
= &XEXP (*loc
, 1);
2481 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2484 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2491 /* This loop is a little tricky. We cannot just go down the chain because
2492 it is being modified by some actions in the loop. So we just iterate
2493 over the head. We plan to drain the list anyway. */
2494 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2496 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2497 rtx note
= find_reg_equal_equiv_note (insn
);
2499 /* This assert is generally triggered when someone deletes a REG_EQUAL
2500 or REG_EQUIV note by hacking the list manually rather than calling
2504 remove_note (insn
, note
);
2508 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2509 return 1 if it is found. A simple equality test is used to determine if
2513 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2517 for (x
= listp
; x
; x
= XEXP (x
, 1))
2518 if (node
== XEXP (x
, 0))
2524 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2525 remove that entry from the list if it is found.
2527 A simple equality test is used to determine if NODE matches. */
2530 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2532 rtx_expr_list
*temp
= *listp
;
2533 rtx_expr_list
*prev
= NULL
;
2537 if (node
== temp
->element ())
2539 /* Splice the node out of the list. */
2541 XEXP (prev
, 1) = temp
->next ();
2543 *listp
= temp
->next ();
2549 temp
= temp
->next ();
2553 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2554 remove that entry from the list if it is found.
2556 A simple equality test is used to determine if NODE matches. */
2559 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2561 rtx_insn_list
*temp
= *listp
;
2562 rtx_insn_list
*prev
= NULL
;
2566 if (node
== temp
->insn ())
2568 /* Splice the node out of the list. */
2570 XEXP (prev
, 1) = temp
->next ();
2572 *listp
= temp
->next ();
2578 temp
= temp
->next ();
2582 /* Nonzero if X contains any volatile instructions. These are instructions
2583 which may cause unpredictable machine state instructions, and thus no
2584 instructions or register uses should be moved or combined across them.
2585 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2588 volatile_insn_p (const_rtx x
)
2590 const RTX_CODE code
= GET_CODE (x
);
2608 case UNSPEC_VOLATILE
:
2613 if (MEM_VOLATILE_P (x
))
2620 /* Recursively scan the operands of this expression. */
2623 const char *const fmt
= GET_RTX_FORMAT (code
);
2626 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2630 if (volatile_insn_p (XEXP (x
, i
)))
2633 else if (fmt
[i
] == 'E')
2636 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2637 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2645 /* Nonzero if X contains any volatile memory references
2646 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2649 volatile_refs_p (const_rtx x
)
2651 const RTX_CODE code
= GET_CODE (x
);
2667 case UNSPEC_VOLATILE
:
2673 if (MEM_VOLATILE_P (x
))
2680 /* Recursively scan the operands of this expression. */
2683 const char *const fmt
= GET_RTX_FORMAT (code
);
2686 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2690 if (volatile_refs_p (XEXP (x
, i
)))
2693 else if (fmt
[i
] == 'E')
2696 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2697 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2705 /* Similar to above, except that it also rejects register pre- and post-
2709 side_effects_p (const_rtx x
)
2711 const RTX_CODE code
= GET_CODE (x
);
2728 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2729 when some combination can't be done. If we see one, don't think
2730 that we can simplify the expression. */
2731 return (GET_MODE (x
) != VOIDmode
);
2740 case UNSPEC_VOLATILE
:
2746 if (MEM_VOLATILE_P (x
))
2753 /* Recursively scan the operands of this expression. */
2756 const char *fmt
= GET_RTX_FORMAT (code
);
2759 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2763 if (side_effects_p (XEXP (x
, i
)))
2766 else if (fmt
[i
] == 'E')
2769 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2770 if (side_effects_p (XVECEXP (x
, i
, j
)))
2778 /* Return nonzero if evaluating rtx X might cause a trap.
2779 FLAGS controls how to consider MEMs. A nonzero means the context
2780 of the access may have changed from the original, such that the
2781 address may have become invalid. */
2784 may_trap_p_1 (const_rtx x
, unsigned flags
)
2790 /* We make no distinction currently, but this function is part of
2791 the internal target-hooks ABI so we keep the parameter as
2792 "unsigned flags". */
2793 bool code_changed
= flags
!= 0;
2797 code
= GET_CODE (x
);
2800 /* Handle these cases quickly. */
2812 return targetm
.unspec_may_trap_p (x
, flags
);
2814 case UNSPEC_VOLATILE
:
2820 return MEM_VOLATILE_P (x
);
2822 /* Memory ref can trap unless it's a static var or a stack slot. */
2824 /* Recognize specific pattern of stack checking probes. */
2825 if (flag_stack_check
2826 && MEM_VOLATILE_P (x
)
2827 && XEXP (x
, 0) == stack_pointer_rtx
)
2829 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2830 reference; moving it out of context such as when moving code
2831 when optimizing, might cause its address to become invalid. */
2833 || !MEM_NOTRAP_P (x
))
2835 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
2836 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2837 GET_MODE (x
), code_changed
);
2842 /* Division by a non-constant might trap. */
2847 if (HONOR_SNANS (x
))
2849 if (FLOAT_MODE_P (GET_MODE (x
)))
2850 return flag_trapping_math
;
2851 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2853 if (GET_CODE (XEXP (x
, 1)) == CONST_VECTOR
)
2855 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
2856 unsigned int n_elts
;
2857 rtx op
= XEXP (x
, 1);
2858 if (!GET_MODE_NUNITS (GET_MODE (op
)).is_constant (&n_elts
))
2860 if (!CONST_VECTOR_DUPLICATE_P (op
))
2862 for (unsigned i
= 0; i
< (unsigned int) XVECLEN (op
, 0); i
++)
2863 if (CONST_VECTOR_ENCODED_ELT (op
, i
) == const0_rtx
)
2867 for (unsigned i
= 0; i
< n_elts
; i
++)
2868 if (CONST_VECTOR_ELT (op
, i
) == const0_rtx
)
2874 /* An EXPR_LIST is used to represent a function call. This
2875 certainly may trap. */
2884 /* Some floating point comparisons may trap. */
2885 if (!flag_trapping_math
)
2887 /* ??? There is no machine independent way to check for tests that trap
2888 when COMPARE is used, though many targets do make this distinction.
2889 For instance, sparc uses CCFPE for compares which generate exceptions
2890 and CCFP for compares which do not generate exceptions. */
2893 /* But often the compare has some CC mode, so check operand
2895 if (HONOR_NANS (XEXP (x
, 0))
2896 || HONOR_NANS (XEXP (x
, 1)))
2902 if (HONOR_SNANS (x
))
2904 /* Often comparison is CC mode, so check operand modes. */
2905 if (HONOR_SNANS (XEXP (x
, 0))
2906 || HONOR_SNANS (XEXP (x
, 1)))
2911 /* Conversion of floating point might trap. */
2912 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2923 /* These operations don't trap even with floating point. */
2927 /* Any floating arithmetic may trap. */
2928 if (FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2932 fmt
= GET_RTX_FORMAT (code
);
2933 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2937 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2940 else if (fmt
[i
] == 'E')
2943 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2944 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2951 /* Return nonzero if evaluating rtx X might cause a trap. */
2954 may_trap_p (const_rtx x
)
2956 return may_trap_p_1 (x
, 0);
2959 /* Same as above, but additionally return nonzero if evaluating rtx X might
2960 cause a fault. We define a fault for the purpose of this function as a
2961 erroneous execution condition that cannot be encountered during the normal
2962 execution of a valid program; the typical example is an unaligned memory
2963 access on a strict alignment machine. The compiler guarantees that it
2964 doesn't generate code that will fault from a valid program, but this
2965 guarantee doesn't mean anything for individual instructions. Consider
2966 the following example:
2968 struct S { int d; union { char *cp; int *ip; }; };
2970 int foo(struct S *s)
2978 on a strict alignment machine. In a valid program, foo will never be
2979 invoked on a structure for which d is equal to 1 and the underlying
2980 unique field of the union not aligned on a 4-byte boundary, but the
2981 expression *s->ip might cause a fault if considered individually.
2983 At the RTL level, potentially problematic expressions will almost always
2984 verify may_trap_p; for example, the above dereference can be emitted as
2985 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2986 However, suppose that foo is inlined in a caller that causes s->cp to
2987 point to a local character variable and guarantees that s->d is not set
2988 to 1; foo may have been effectively translated into pseudo-RTL as:
2991 (set (reg:SI) (mem:SI (%fp - 7)))
2993 (set (reg:QI) (mem:QI (%fp - 7)))
2995 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2996 memory reference to a stack slot, but it will certainly cause a fault
2997 on a strict alignment machine. */
3000 may_trap_or_fault_p (const_rtx x
)
3002 return may_trap_p_1 (x
, 1);
3005 /* Return nonzero if X contains a comparison that is not either EQ or NE,
3006 i.e., an inequality. */
3009 inequality_comparisons_p (const_rtx x
)
3013 const enum rtx_code code
= GET_CODE (x
);
3041 len
= GET_RTX_LENGTH (code
);
3042 fmt
= GET_RTX_FORMAT (code
);
3044 for (i
= 0; i
< len
; i
++)
3048 if (inequality_comparisons_p (XEXP (x
, i
)))
3051 else if (fmt
[i
] == 'E')
3054 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3055 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
3063 /* Replace any occurrence of FROM in X with TO. The function does
3064 not enter into CONST_DOUBLE for the replace.
3066 Note that copying is not done so X must not be shared unless all copies
3069 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3070 those pointer-equal ones. */
3073 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3081 /* Allow this function to make replacements in EXPR_LISTs. */
3088 && REGNO (x
) == REGNO (from
))
3090 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3093 else if (GET_CODE (x
) == SUBREG
)
3095 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3097 if (CONST_INT_P (new_rtx
))
3099 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3100 GET_MODE (SUBREG_REG (x
)),
3105 SUBREG_REG (x
) = new_rtx
;
3109 else if (GET_CODE (x
) == ZERO_EXTEND
)
3111 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3113 if (CONST_INT_P (new_rtx
))
3115 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3116 new_rtx
, GET_MODE (XEXP (x
, 0)));
3120 XEXP (x
, 0) = new_rtx
;
3125 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3126 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3129 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3130 else if (fmt
[i
] == 'E')
3131 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3132 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3133 from
, to
, all_regs
);
3139 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3140 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3143 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3145 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3147 if (JUMP_TABLE_DATA_P (x
))
3150 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3151 int len
= GET_NUM_ELEM (vec
);
3152 for (int i
= 0; i
< len
; ++i
)
3154 rtx ref
= RTVEC_ELT (vec
, i
);
3155 if (XEXP (ref
, 0) == old_label
)
3157 XEXP (ref
, 0) = new_label
;
3158 if (update_label_nuses
)
3160 ++LABEL_NUSES (new_label
);
3161 --LABEL_NUSES (old_label
);
3168 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3169 field. This is not handled by the iterator because it doesn't
3170 handle unprinted ('0') fields. */
3171 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3172 JUMP_LABEL (x
) = new_label
;
3174 subrtx_ptr_iterator::array_type array
;
3175 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3180 if (GET_CODE (x
) == SYMBOL_REF
3181 && CONSTANT_POOL_ADDRESS_P (x
))
3183 rtx c
= get_pool_constant (x
);
3184 if (rtx_referenced_p (old_label
, c
))
3186 /* Create a copy of constant C; replace the label inside
3187 but do not update LABEL_NUSES because uses in constant pool
3189 rtx new_c
= copy_rtx (c
);
3190 replace_label (&new_c
, old_label
, new_label
, false);
3192 /* Add the new constant NEW_C to constant pool and replace
3193 the old reference to constant by new reference. */
3194 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3195 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3199 if ((GET_CODE (x
) == LABEL_REF
3200 || GET_CODE (x
) == INSN_LIST
)
3201 && XEXP (x
, 0) == old_label
)
3203 XEXP (x
, 0) = new_label
;
3204 if (update_label_nuses
)
3206 ++LABEL_NUSES (new_label
);
3207 --LABEL_NUSES (old_label
);
3215 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3216 rtx_insn
*new_label
, bool update_label_nuses
)
3218 rtx insn_as_rtx
= insn
;
3219 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3220 gcc_checking_assert (insn_as_rtx
== insn
);
3223 /* Return true if X is referenced in BODY. */
3226 rtx_referenced_p (const_rtx x
, const_rtx body
)
3228 subrtx_iterator::array_type array
;
3229 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3230 if (const_rtx y
= *iter
)
3232 /* Check if a label_ref Y refers to label X. */
3233 if (GET_CODE (y
) == LABEL_REF
3235 && label_ref_label (y
) == x
)
3238 if (rtx_equal_p (x
, y
))
3241 /* If Y is a reference to pool constant traverse the constant. */
3242 if (GET_CODE (y
) == SYMBOL_REF
3243 && CONSTANT_POOL_ADDRESS_P (y
))
3244 iter
.substitute (get_pool_constant (y
));
3249 /* If INSN is a tablejump return true and store the label (before jump table) to
3250 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3253 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3254 rtx_jump_table_data
**tablep
)
3259 rtx target
= JUMP_LABEL (insn
);
3260 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3263 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3264 rtx_insn
*table
= next_insn (label
);
3265 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3271 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3275 /* For INSN known to satisfy tablejump_p, determine if it actually is a
3276 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3279 tablejump_casesi_pattern (const rtx_insn
*insn
)
3283 if ((tmp
= single_set (insn
)) != NULL
3284 && SET_DEST (tmp
) == pc_rtx
3285 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3286 && GET_CODE (XEXP (SET_SRC (tmp
), 2)) == LABEL_REF
)
3292 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3293 constant that is not in the constant pool and not in the condition
3294 of an IF_THEN_ELSE. */
3297 computed_jump_p_1 (const_rtx x
)
3299 const enum rtx_code code
= GET_CODE (x
);
3316 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3317 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3320 return (computed_jump_p_1 (XEXP (x
, 1))
3321 || computed_jump_p_1 (XEXP (x
, 2)));
3327 fmt
= GET_RTX_FORMAT (code
);
3328 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3331 && computed_jump_p_1 (XEXP (x
, i
)))
3334 else if (fmt
[i
] == 'E')
3335 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3336 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3343 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3345 Tablejumps and casesi insns are not considered indirect jumps;
3346 we can recognize them by a (use (label_ref)). */
3349 computed_jump_p (const rtx_insn
*insn
)
3354 rtx pat
= PATTERN (insn
);
3356 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3357 if (JUMP_LABEL (insn
) != NULL
)
3360 if (GET_CODE (pat
) == PARALLEL
)
3362 int len
= XVECLEN (pat
, 0);
3363 int has_use_labelref
= 0;
3365 for (i
= len
- 1; i
>= 0; i
--)
3366 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3367 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3370 has_use_labelref
= 1;
3374 if (! has_use_labelref
)
3375 for (i
= len
- 1; i
>= 0; i
--)
3376 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3377 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3378 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3381 else if (GET_CODE (pat
) == SET
3382 && SET_DEST (pat
) == pc_rtx
3383 && computed_jump_p_1 (SET_SRC (pat
)))
3391 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3392 the equivalent add insn and pass the result to FN, using DATA as the
3396 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3398 rtx x
= XEXP (mem
, 0);
3399 switch (GET_CODE (x
))
3404 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3405 rtx r1
= XEXP (x
, 0);
3406 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3407 return fn (mem
, x
, r1
, r1
, c
, data
);
3413 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3414 rtx r1
= XEXP (x
, 0);
3415 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3416 return fn (mem
, x
, r1
, r1
, c
, data
);
3422 rtx r1
= XEXP (x
, 0);
3423 rtx add
= XEXP (x
, 1);
3424 return fn (mem
, x
, r1
, add
, NULL
, data
);
3432 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3433 For each such autoinc operation found, call FN, passing it
3434 the innermost enclosing MEM, the operation itself, the RTX modified
3435 by the operation, two RTXs (the second may be NULL) that, once
3436 added, represent the value to be held by the modified RTX
3437 afterwards, and DATA. FN is to return 0 to continue the
3438 traversal or any other value to have it returned to the caller of
3439 for_each_inc_dec. */
3442 for_each_inc_dec (rtx x
,
3443 for_each_inc_dec_fn fn
,
3446 subrtx_var_iterator::array_type array
;
3447 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3452 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3454 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3457 iter
.skip_subrtxes ();
3464 /* Searches X for any reference to REGNO, returning the rtx of the
3465 reference found if any. Otherwise, returns NULL_RTX. */
3468 regno_use_in (unsigned int regno
, rtx x
)
3474 if (REG_P (x
) && REGNO (x
) == regno
)
3477 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3478 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3482 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3485 else if (fmt
[i
] == 'E')
3486 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3487 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3494 /* Return a value indicating whether OP, an operand of a commutative
3495 operation, is preferred as the first or second operand. The more
3496 positive the value, the stronger the preference for being the first
3500 commutative_operand_precedence (rtx op
)
3502 enum rtx_code code
= GET_CODE (op
);
3504 /* Constants always become the second operand. Prefer "nice" constants. */
3505 if (code
== CONST_INT
)
3507 if (code
== CONST_WIDE_INT
)
3509 if (code
== CONST_POLY_INT
)
3511 if (code
== CONST_DOUBLE
)
3513 if (code
== CONST_FIXED
)
3515 op
= avoid_constant_pool_reference (op
);
3516 code
= GET_CODE (op
);
3518 switch (GET_RTX_CLASS (code
))
3521 if (code
== CONST_INT
)
3523 if (code
== CONST_WIDE_INT
)
3525 if (code
== CONST_POLY_INT
)
3527 if (code
== CONST_DOUBLE
)
3529 if (code
== CONST_FIXED
)
3534 /* SUBREGs of objects should come second. */
3535 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3540 /* Complex expressions should be the first, so decrease priority
3541 of objects. Prefer pointer objects over non pointer objects. */
3542 if ((REG_P (op
) && REG_POINTER (op
))
3543 || (MEM_P (op
) && MEM_POINTER (op
)))
3547 case RTX_COMM_ARITH
:
3548 /* Prefer operands that are themselves commutative to be first.
3549 This helps to make things linear. In particular,
3550 (and (and (reg) (reg)) (not (reg))) is canonical. */
3554 /* If only one operand is a binary expression, it will be the first
3555 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3556 is canonical, although it will usually be further simplified. */
3560 /* Then prefer NEG and NOT. */
3561 if (code
== NEG
|| code
== NOT
)
3570 /* Return 1 iff it is necessary to swap operands of commutative operation
3571 in order to canonicalize expression. */
3574 swap_commutative_operands_p (rtx x
, rtx y
)
3576 return (commutative_operand_precedence (x
)
3577 < commutative_operand_precedence (y
));
3580 /* Return 1 if X is an autoincrement side effect and the register is
3581 not the stack pointer. */
3583 auto_inc_p (const_rtx x
)
3585 switch (GET_CODE (x
))
3593 /* There are no REG_INC notes for SP. */
3594 if (XEXP (x
, 0) != stack_pointer_rtx
)
3602 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3604 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3613 code
= GET_CODE (in
);
3614 fmt
= GET_RTX_FORMAT (code
);
3615 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3619 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3622 else if (fmt
[i
] == 'E')
3623 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3624 if (loc
== &XVECEXP (in
, i
, j
)
3625 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3631 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3632 and SUBREG_BYTE, return the bit offset where the subreg begins
3633 (counting from the least significant bit of the operand). */
3636 subreg_lsb_1 (machine_mode outer_mode
,
3637 machine_mode inner_mode
,
3638 poly_uint64 subreg_byte
)
3640 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3642 /* A paradoxical subreg begins at bit position 0. */
3643 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
3646 subreg_end
= subreg_byte
+ GET_MODE_SIZE (outer_mode
);
3647 trailing_bytes
= GET_MODE_SIZE (inner_mode
) - subreg_end
;
3648 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3649 byte_pos
= trailing_bytes
;
3650 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3651 byte_pos
= subreg_byte
;
3654 /* When bytes and words have opposite endianness, we must be able
3655 to split offsets into words and bytes at compile time. */
3656 poly_uint64 leading_word_part
3657 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3658 poly_uint64 trailing_word_part
3659 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3660 /* If the subreg crosses a word boundary ensure that
3661 it also begins and ends on a word boundary. */
3662 gcc_assert (known_le (subreg_end
- leading_word_part
,
3663 (unsigned int) UNITS_PER_WORD
)
3664 || (known_eq (leading_word_part
, subreg_byte
)
3665 && known_eq (trailing_word_part
, trailing_bytes
)));
3666 if (WORDS_BIG_ENDIAN
)
3667 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3669 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3672 return byte_pos
* BITS_PER_UNIT
;
3675 /* Given a subreg X, return the bit offset where the subreg begins
3676 (counting from the least significant bit of the reg). */
3679 subreg_lsb (const_rtx x
)
3681 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3685 /* Return the subreg byte offset for a subreg whose outer value has
3686 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3687 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3688 lsb of the inner value. This is the inverse of the calculation
3689 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3692 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3693 poly_uint64 lsb_shift
)
3695 /* A paradoxical subreg begins at bit position 0. */
3696 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3697 if (maybe_gt (outer_bytes
, inner_bytes
))
3699 gcc_checking_assert (known_eq (lsb_shift
, 0U));
3703 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
3704 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3705 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3707 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3711 /* When bytes and words have opposite endianness, we must be able
3712 to split offsets into words and bytes at compile time. */
3713 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
3715 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
3717 if (WORDS_BIG_ENDIAN
)
3718 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3720 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3724 /* Fill in information about a subreg of a hard register.
3725 xregno - A regno of an inner hard subreg_reg (or what will become one).
3726 xmode - The mode of xregno.
3727 offset - The byte offset.
3728 ymode - The mode of a top level SUBREG (or what may become one).
3729 info - Pointer to structure to fill in.
3731 Rather than considering one particular inner register (and thus one
3732 particular "outer" register) in isolation, this function really uses
3733 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3734 function does not check whether adding INFO->offset to XREGNO gives
3735 a valid hard register; even if INFO->offset + XREGNO is out of range,
3736 there might be another register of the same type that is in range.
3737 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
3738 the new register, since that can depend on things like whether the final
3739 register number is even or odd. Callers that want to check whether
3740 this particular subreg can be replaced by a simple (reg ...) should
3741 use simplify_subreg_regno. */
3744 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3745 poly_uint64 offset
, machine_mode ymode
,
3746 struct subreg_info
*info
)
3748 unsigned int nregs_xmode
, nregs_ymode
;
3750 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3752 poly_uint64 xsize
= GET_MODE_SIZE (xmode
);
3753 poly_uint64 ysize
= GET_MODE_SIZE (ymode
);
3755 bool rknown
= false;
3757 /* If the register representation of a non-scalar mode has holes in it,
3758 we expect the scalar units to be concatenated together, with the holes
3759 distributed evenly among the scalar units. Each scalar unit must occupy
3760 at least one register. */
3761 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3763 /* As a consequence, we must be dealing with a constant number of
3764 scalars, and thus a constant offset and number of units. */
3765 HOST_WIDE_INT coffset
= offset
.to_constant ();
3766 HOST_WIDE_INT cysize
= ysize
.to_constant ();
3767 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3768 unsigned int nunits
= GET_MODE_NUNITS (xmode
).to_constant ();
3769 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
3770 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3771 gcc_assert (nregs_xmode
3773 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3774 gcc_assert (hard_regno_nregs (xregno
, xmode
)
3775 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
3777 /* You can only ask for a SUBREG of a value with holes in the middle
3778 if you don't cross the holes. (Such a SUBREG should be done by
3779 picking a different register class, or doing it in memory if
3780 necessary.) An example of a value with holes is XCmode on 32-bit
3781 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3782 3 for each part, but in memory it's two 128-bit parts.
3783 Padding is assumed to be at the end (not necessarily the 'high part')
3785 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3786 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
3787 != ((coffset
+ cysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3789 info
->representable_p
= false;
3794 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
3796 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
3798 /* Subreg sizes must be ordered, so that we can tell whether they are
3799 partial, paradoxical or complete. */
3800 gcc_checking_assert (ordered_p (xsize
, ysize
));
3802 /* Paradoxical subregs are otherwise valid. */
3803 if (!rknown
&& known_eq (offset
, 0U) && maybe_gt (ysize
, xsize
))
3805 info
->representable_p
= true;
3806 /* If this is a big endian paradoxical subreg, which uses more
3807 actual hard registers than the original register, we must
3808 return a negative offset so that we find the proper highpart
3811 We assume that the ordering of registers within a multi-register
3812 value has a consistent endianness: if bytes and register words
3813 have different endianness, the hard registers that make up a
3814 multi-register value must be at least word-sized. */
3815 if (REG_WORDS_BIG_ENDIAN
)
3816 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3819 info
->nregs
= nregs_ymode
;
3823 /* If registers store different numbers of bits in the different
3824 modes, we cannot generally form this subreg. */
3825 poly_uint64 regsize_xmode
, regsize_ymode
;
3826 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3827 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3828 && multiple_p (xsize
, nregs_xmode
, ®size_xmode
)
3829 && multiple_p (ysize
, nregs_ymode
, ®size_ymode
))
3832 && ((nregs_ymode
> 1 && maybe_gt (regsize_xmode
, regsize_ymode
))
3833 || (nregs_xmode
> 1 && maybe_gt (regsize_ymode
, regsize_xmode
))))
3835 info
->representable_p
= false;
3836 if (!can_div_away_from_zero_p (ysize
, regsize_xmode
, &info
->nregs
)
3837 || !can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3838 /* Checked by validate_subreg. We must know at compile time
3839 which inner registers are being accessed. */
3843 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3844 would go outside of XMODE. */
3845 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
3847 info
->representable_p
= false;
3848 info
->nregs
= nregs_ymode
;
3849 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
3850 /* Checked by validate_subreg. We must know at compile time
3851 which inner registers are being accessed. */
3855 /* Quick exit for the simple and common case of extracting whole
3856 subregisters from a multiregister value. */
3857 /* ??? It would be better to integrate this into the code below,
3858 if we can generalize the concept enough and figure out how
3859 odd-sized modes can coexist with the other weird cases we support. */
3860 HOST_WIDE_INT count
;
3862 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3863 && known_eq (regsize_xmode
, regsize_ymode
)
3864 && constant_multiple_p (offset
, regsize_ymode
, &count
))
3866 info
->representable_p
= true;
3867 info
->nregs
= nregs_ymode
;
3868 info
->offset
= count
;
3869 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3874 /* Lowpart subregs are otherwise valid. */
3875 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
3877 info
->representable_p
= true;
3880 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
3883 info
->nregs
= nregs_ymode
;
3888 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3889 values there are in (reg:XMODE XREGNO). We can view the register
3890 as consisting of this number of independent "blocks", where each
3891 block occupies NREGS_YMODE registers and contains exactly one
3892 representable YMODE value. */
3893 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3894 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3896 /* Calculate the number of bytes in each block. This must always
3897 be exact, otherwise we don't know how to verify the constraint.
3898 These conditions may be relaxed but subreg_regno_offset would
3899 need to be redesigned. */
3900 poly_uint64 bytes_per_block
= exact_div (xsize
, num_blocks
);
3902 /* Get the number of the first block that contains the subreg and the byte
3903 offset of the subreg from the start of that block. */
3904 unsigned int block_number
;
3905 poly_uint64 subblock_offset
;
3906 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
3908 /* Checked by validate_subreg. We must know at compile time which
3909 inner registers are being accessed. */
3914 /* Only the lowpart of each block is representable. */
3915 info
->representable_p
3916 = known_eq (subblock_offset
,
3917 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3921 /* We assume that the ordering of registers within a multi-register
3922 value has a consistent endianness: if bytes and register words
3923 have different endianness, the hard registers that make up a
3924 multi-register value must be at least word-sized. */
3925 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3926 /* The block number we calculated above followed memory endianness.
3927 Convert it to register endianness by counting back from the end.
3928 (Note that, because of the assumption above, each block must be
3929 at least word-sized.) */
3930 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3932 info
->offset
= block_number
* nregs_ymode
;
3933 info
->nregs
= nregs_ymode
;
3936 /* This function returns the regno offset of a subreg expression.
3937 xregno - A regno of an inner hard subreg_reg (or what will become one).
3938 xmode - The mode of xregno.
3939 offset - The byte offset.
3940 ymode - The mode of a top level SUBREG (or what may become one).
3941 RETURN - The regno offset which would be used. */
3943 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3944 poly_uint64 offset
, machine_mode ymode
)
3946 struct subreg_info info
;
3947 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3951 /* This function returns true when the offset is representable via
3952 subreg_offset in the given regno.
3953 xregno - A regno of an inner hard subreg_reg (or what will become one).
3954 xmode - The mode of xregno.
3955 offset - The byte offset.
3956 ymode - The mode of a top level SUBREG (or what may become one).
3957 RETURN - Whether the offset is representable. */
3959 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3960 poly_uint64 offset
, machine_mode ymode
)
3962 struct subreg_info info
;
3963 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3964 return info
.representable_p
;
3967 /* Return the number of a YMODE register to which
3969 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3971 can be simplified. Return -1 if the subreg can't be simplified.
3973 XREGNO is a hard register number. */
3976 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3977 poly_uint64 offset
, machine_mode ymode
)
3979 struct subreg_info info
;
3980 unsigned int yregno
;
3982 /* Give the backend a chance to disallow the mode change. */
3983 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3984 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3985 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3986 /* We can use mode change in LRA for some transformations. */
3987 && ! lra_in_progress
)
3990 /* We shouldn't simplify stack-related registers. */
3991 if ((!reload_completed
|| frame_pointer_needed
)
3992 && xregno
== FRAME_POINTER_REGNUM
)
3995 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3996 && xregno
== ARG_POINTER_REGNUM
)
3999 if (xregno
== STACK_POINTER_REGNUM
4000 /* We should convert hard stack register in LRA if it is
4002 && ! lra_in_progress
)
4005 /* Try to get the register offset. */
4006 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
4007 if (!info
.representable_p
)
4010 /* Make sure that the offsetted register value is in range. */
4011 yregno
= xregno
+ info
.offset
;
4012 if (!HARD_REGISTER_NUM_P (yregno
))
4015 /* See whether (reg:YMODE YREGNO) is valid.
4017 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
4018 This is a kludge to work around how complex FP arguments are passed
4019 on IA-64 and should be fixed. See PR target/49226. */
4020 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
4021 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
4024 return (int) yregno
;
4027 /* Return the final regno that a subreg expression refers to. */
4029 subreg_regno (const_rtx x
)
4032 rtx subreg
= SUBREG_REG (x
);
4033 int regno
= REGNO (subreg
);
4035 ret
= regno
+ subreg_regno_offset (regno
,
4043 /* Return the number of registers that a subreg expression refers
4046 subreg_nregs (const_rtx x
)
4048 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
4051 /* Return the number of registers that a subreg REG with REGNO
4052 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
4053 changed so that the regno can be passed in. */
4056 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
4058 struct subreg_info info
;
4059 rtx subreg
= SUBREG_REG (x
);
4061 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
4066 struct parms_set_data
4072 /* Helper function for noticing stores to parameter registers. */
4074 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
4076 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
4077 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
4078 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4080 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4085 /* Look backward for first parameter to be loaded.
4086 Note that loads of all parameters will not necessarily be
4087 found if CSE has eliminated some of them (e.g., an argument
4088 to the outer function is passed down as a parameter).
4089 Do not skip BOUNDARY. */
4091 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4093 struct parms_set_data parm
;
4095 rtx_insn
*before
, *first_set
;
4097 /* Since different machines initialize their parameter registers
4098 in different orders, assume nothing. Collect the set of all
4099 parameter registers. */
4100 CLEAR_HARD_REG_SET (parm
.regs
);
4102 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4103 if (GET_CODE (XEXP (p
, 0)) == USE
4104 && REG_P (XEXP (XEXP (p
, 0), 0))
4105 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4107 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4109 /* We only care about registers which can hold function
4111 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4114 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4118 first_set
= call_insn
;
4120 /* Search backward for the first set of a register in this set. */
4121 while (parm
.nregs
&& before
!= boundary
)
4123 before
= PREV_INSN (before
);
4125 /* It is possible that some loads got CSEed from one call to
4126 another. Stop in that case. */
4127 if (CALL_P (before
))
4130 /* Our caller needs either ensure that we will find all sets
4131 (in case code has not been optimized yet), or take care
4132 for possible labels in a way by setting boundary to preceding
4134 if (LABEL_P (before
))
4136 gcc_assert (before
== boundary
);
4140 if (INSN_P (before
))
4142 int nregs_old
= parm
.nregs
;
4143 note_stores (PATTERN (before
), parms_set
, &parm
);
4144 /* If we found something that did not set a parameter reg,
4145 we're done. Do not keep going, as that might result
4146 in hoisting an insn before the setting of a pseudo
4147 that is used by the hoisted insn. */
4148 if (nregs_old
!= parm
.nregs
)
4157 /* Return true if we should avoid inserting code between INSN and preceding
4158 call instruction. */
4161 keep_with_call_p (const rtx_insn
*insn
)
4165 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4167 if (REG_P (SET_DEST (set
))
4168 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4169 && fixed_regs
[REGNO (SET_DEST (set
))]
4170 && general_operand (SET_SRC (set
), VOIDmode
))
4172 if (REG_P (SET_SRC (set
))
4173 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4174 && REG_P (SET_DEST (set
))
4175 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4177 /* There may be a stack pop just after the call and before the store
4178 of the return register. Search for the actual store when deciding
4179 if we can break or not. */
4180 if (SET_DEST (set
) == stack_pointer_rtx
)
4182 /* This CONST_CAST is okay because next_nonnote_insn just
4183 returns its argument and we assign it to a const_rtx
4186 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4187 if (i2
&& keep_with_call_p (i2
))
4194 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4195 to non-complex jumps. That is, direct unconditional, conditional,
4196 and tablejumps, but not computed jumps or returns. It also does
4197 not apply to the fallthru case of a conditional jump. */
4200 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4202 rtx tmp
= JUMP_LABEL (jump_insn
);
4203 rtx_jump_table_data
*table
;
4208 if (tablejump_p (jump_insn
, NULL
, &table
))
4210 rtvec vec
= table
->get_labels ();
4211 int i
, veclen
= GET_NUM_ELEM (vec
);
4213 for (i
= 0; i
< veclen
; ++i
)
4214 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4218 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4225 /* Return an estimate of the cost of computing rtx X.
4226 One use is in cse, to decide which expression to keep in the hash table.
4227 Another is in rtl generation, to pick the cheapest way to multiply.
4228 Other uses like the latter are expected in the future.
4230 X appears as operand OPNO in an expression with code OUTER_CODE.
4231 SPEED specifies whether costs optimized for speed or size should
4235 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4236 int opno
, bool speed
)
4247 if (GET_MODE (x
) != VOIDmode
)
4248 mode
= GET_MODE (x
);
4250 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4251 many insns, taking N times as long. */
4252 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4256 /* Compute the default costs of certain things.
4257 Note that targetm.rtx_costs can override the defaults. */
4259 code
= GET_CODE (x
);
4263 /* Multiplication has time-complexity O(N*N), where N is the
4264 number of units (translated from digits) when using
4265 schoolbook long multiplication. */
4266 total
= factor
* factor
* COSTS_N_INSNS (5);
4272 /* Similarly, complexity for schoolbook long division. */
4273 total
= factor
* factor
* COSTS_N_INSNS (7);
4276 /* Used in combine.c as a marker. */
4280 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4281 the mode for the factor. */
4282 mode
= GET_MODE (SET_DEST (x
));
4283 factor
= estimated_poly_value (GET_MODE_SIZE (mode
)) / UNITS_PER_WORD
;
4288 total
= factor
* COSTS_N_INSNS (1);
4298 /* If we can't tie these modes, make this expensive. The larger
4299 the mode, the more expensive it is. */
4300 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4301 return COSTS_N_INSNS (2 + factor
);
4305 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4312 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4317 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4318 which is already in total. */
4320 fmt
= GET_RTX_FORMAT (code
);
4321 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4323 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4324 else if (fmt
[i
] == 'E')
4325 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4326 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4331 /* Fill in the structure C with information about both speed and size rtx
4332 costs for X, which is operand OPNO in an expression with code OUTER. */
4335 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4336 struct full_rtx_costs
*c
)
4338 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4339 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4343 /* Return cost of address expression X.
4344 Expect that X is properly formed address reference.
4346 SPEED parameter specify whether costs optimized for speed or size should
4350 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4352 /* We may be asked for cost of various unusual addresses, such as operands
4353 of push instruction. It is not worthwhile to complicate writing
4354 of the target hook by such cases. */
4356 if (!memory_address_addr_space_p (mode
, x
, as
))
4359 return targetm
.address_cost (x
, mode
, as
, speed
);
4362 /* If the target doesn't override, compute the cost as with arithmetic. */
4365 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4367 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4371 unsigned HOST_WIDE_INT
4372 nonzero_bits (const_rtx x
, machine_mode mode
)
4374 if (mode
== VOIDmode
)
4375 mode
= GET_MODE (x
);
4376 scalar_int_mode int_mode
;
4377 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4378 return GET_MODE_MASK (mode
);
4379 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4383 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4385 if (mode
== VOIDmode
)
4386 mode
= GET_MODE (x
);
4387 scalar_int_mode int_mode
;
4388 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4390 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4393 /* Return true if nonzero_bits1 might recurse into both operands
4397 nonzero_bits_binary_arith_p (const_rtx x
)
4399 if (!ARITHMETIC_P (x
))
4401 switch (GET_CODE (x
))
4423 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4424 It avoids exponential behavior in nonzero_bits1 when X has
4425 identical subexpressions on the first or the second level. */
4427 static unsigned HOST_WIDE_INT
4428 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4429 machine_mode known_mode
,
4430 unsigned HOST_WIDE_INT known_ret
)
4432 if (x
== known_x
&& mode
== known_mode
)
4435 /* Try to find identical subexpressions. If found call
4436 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4437 precomputed value for the subexpression as KNOWN_RET. */
4439 if (nonzero_bits_binary_arith_p (x
))
4441 rtx x0
= XEXP (x
, 0);
4442 rtx x1
= XEXP (x
, 1);
4444 /* Check the first level. */
4446 return nonzero_bits1 (x
, mode
, x0
, mode
,
4447 cached_nonzero_bits (x0
, mode
, known_x
,
4448 known_mode
, known_ret
));
4450 /* Check the second level. */
4451 if (nonzero_bits_binary_arith_p (x0
)
4452 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4453 return nonzero_bits1 (x
, mode
, x1
, mode
,
4454 cached_nonzero_bits (x1
, mode
, known_x
,
4455 known_mode
, known_ret
));
4457 if (nonzero_bits_binary_arith_p (x1
)
4458 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4459 return nonzero_bits1 (x
, mode
, x0
, mode
,
4460 cached_nonzero_bits (x0
, mode
, known_x
,
4461 known_mode
, known_ret
));
4464 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4467 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4468 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4469 is less useful. We can't allow both, because that results in exponential
4470 run time recursion. There is a nullstone testcase that triggered
4471 this. This macro avoids accidental uses of num_sign_bit_copies. */
4472 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4474 /* Given an expression, X, compute which bits in X can be nonzero.
4475 We don't care about bits outside of those defined in MODE.
4477 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4478 an arithmetic operation, we can do better. */
4480 static unsigned HOST_WIDE_INT
4481 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4482 machine_mode known_mode
,
4483 unsigned HOST_WIDE_INT known_ret
)
4485 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4486 unsigned HOST_WIDE_INT inner_nz
;
4487 enum rtx_code code
= GET_CODE (x
);
4488 machine_mode inner_mode
;
4489 unsigned int inner_width
;
4490 scalar_int_mode xmode
;
4492 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4494 if (CONST_INT_P (x
))
4496 if (SHORT_IMMEDIATES_SIGN_EXTEND
4498 && mode_width
< BITS_PER_WORD
4499 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4500 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4505 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4507 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4509 /* If X is wider than MODE, use its mode instead. */
4510 if (xmode_width
> mode_width
)
4513 nonzero
= GET_MODE_MASK (mode
);
4514 mode_width
= xmode_width
;
4517 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4518 /* Our only callers in this case look for single bit values. So
4519 just return the mode mask. Those tests will then be false. */
4522 /* If MODE is wider than X, but both are a single word for both the host
4523 and target machines, we can compute this from which bits of the object
4524 might be nonzero in its own mode, taking into account the fact that, on
4525 CISC machines, accessing an object in a wider mode generally causes the
4526 high-order bits to become undefined, so they are not known to be zero.
4527 We extend this reasoning to RISC machines for operations that might not
4528 operate on the full registers. */
4529 if (mode_width
> xmode_width
4530 && xmode_width
<= BITS_PER_WORD
4531 && xmode_width
<= HOST_BITS_PER_WIDE_INT
4532 && !(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
4534 nonzero
&= cached_nonzero_bits (x
, xmode
,
4535 known_x
, known_mode
, known_ret
);
4536 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4540 /* Please keep nonzero_bits_binary_arith_p above in sync with
4541 the code in the switch below. */
4545 #if defined(POINTERS_EXTEND_UNSIGNED)
4546 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4547 all the bits above ptr_mode are known to be zero. */
4548 /* As we do not know which address space the pointer is referring to,
4549 we can do this only if the target does not support different pointer
4550 or address modes depending on the address space. */
4551 if (target_default_pointer_address_modes_p ()
4552 && POINTERS_EXTEND_UNSIGNED
4555 && !targetm
.have_ptr_extend ())
4556 nonzero
&= GET_MODE_MASK (ptr_mode
);
4559 /* Include declared information about alignment of pointers. */
4560 /* ??? We don't properly preserve REG_POINTER changes across
4561 pointer-to-integer casts, so we can't trust it except for
4562 things that we know must be pointers. See execute/960116-1.c. */
4563 if ((x
== stack_pointer_rtx
4564 || x
== frame_pointer_rtx
4565 || x
== arg_pointer_rtx
)
4566 && REGNO_POINTER_ALIGN (REGNO (x
)))
4568 unsigned HOST_WIDE_INT alignment
4569 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4571 #ifdef PUSH_ROUNDING
4572 /* If PUSH_ROUNDING is defined, it is possible for the
4573 stack to be momentarily aligned only to that amount,
4574 so we pick the least alignment. */
4575 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4577 poly_uint64 rounded_1
= PUSH_ROUNDING (poly_int64 (1));
4578 alignment
= MIN (known_alignment (rounded_1
), alignment
);
4582 nonzero
&= ~(alignment
- 1);
4586 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4587 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4591 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4592 known_mode
, known_ret
);
4594 return nonzero_for_hook
;
4598 /* In many, if not most, RISC machines, reading a byte from memory
4599 zeros the rest of the register. Noticing that fact saves a lot
4600 of extra zero-extends. */
4601 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4602 nonzero
&= GET_MODE_MASK (xmode
);
4606 case UNEQ
: case LTGT
:
4607 case GT
: case GTU
: case UNGT
:
4608 case LT
: case LTU
: case UNLT
:
4609 case GE
: case GEU
: case UNGE
:
4610 case LE
: case LEU
: case UNLE
:
4611 case UNORDERED
: case ORDERED
:
4612 /* If this produces an integer result, we know which bits are set.
4613 Code here used to clear bits outside the mode of X, but that is
4615 /* Mind that MODE is the mode the caller wants to look at this
4616 operation in, and not the actual operation mode. We can wind
4617 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4618 that describes the results of a vector compare. */
4619 if (GET_MODE_CLASS (xmode
) == MODE_INT
4620 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4621 nonzero
= STORE_FLAG_VALUE
;
4626 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4627 and num_sign_bit_copies. */
4628 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4632 if (xmode_width
< mode_width
)
4633 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4638 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4639 and num_sign_bit_copies. */
4640 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4646 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4647 known_x
, known_mode
, known_ret
)
4648 & GET_MODE_MASK (mode
));
4652 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4653 known_x
, known_mode
, known_ret
);
4654 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4655 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4659 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4660 Otherwise, show all the bits in the outer mode but not the inner
4662 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4663 known_x
, known_mode
, known_ret
);
4664 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4666 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4667 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4668 inner_nz
|= (GET_MODE_MASK (mode
)
4669 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4672 nonzero
&= inner_nz
;
4676 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4677 known_x
, known_mode
, known_ret
)
4678 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4679 known_x
, known_mode
, known_ret
);
4683 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4685 unsigned HOST_WIDE_INT nonzero0
4686 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4687 known_x
, known_mode
, known_ret
);
4689 /* Don't call nonzero_bits for the second time if it cannot change
4691 if ((nonzero
& nonzero0
) != nonzero
)
4693 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4694 known_x
, known_mode
, known_ret
);
4698 case PLUS
: case MINUS
:
4700 case DIV
: case UDIV
:
4701 case MOD
: case UMOD
:
4702 /* We can apply the rules of arithmetic to compute the number of
4703 high- and low-order zero bits of these operations. We start by
4704 computing the width (position of the highest-order nonzero bit)
4705 and the number of low-order zero bits for each value. */
4707 unsigned HOST_WIDE_INT nz0
4708 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4709 known_x
, known_mode
, known_ret
);
4710 unsigned HOST_WIDE_INT nz1
4711 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4712 known_x
, known_mode
, known_ret
);
4713 int sign_index
= xmode_width
- 1;
4714 int width0
= floor_log2 (nz0
) + 1;
4715 int width1
= floor_log2 (nz1
) + 1;
4716 int low0
= ctz_or_zero (nz0
);
4717 int low1
= ctz_or_zero (nz1
);
4718 unsigned HOST_WIDE_INT op0_maybe_minusp
4719 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4720 unsigned HOST_WIDE_INT op1_maybe_minusp
4721 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4722 unsigned int result_width
= mode_width
;
4728 result_width
= MAX (width0
, width1
) + 1;
4729 result_low
= MIN (low0
, low1
);
4732 result_low
= MIN (low0
, low1
);
4735 result_width
= width0
+ width1
;
4736 result_low
= low0
+ low1
;
4741 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4742 result_width
= width0
;
4747 result_width
= width0
;
4752 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4753 result_width
= MIN (width0
, width1
);
4754 result_low
= MIN (low0
, low1
);
4759 result_width
= MIN (width0
, width1
);
4760 result_low
= MIN (low0
, low1
);
4766 if (result_width
< mode_width
)
4767 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4770 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4775 if (CONST_INT_P (XEXP (x
, 1))
4776 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4777 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4781 /* If this is a SUBREG formed for a promoted variable that has
4782 been zero-extended, we know that at least the high-order bits
4783 are zero, though others might be too. */
4784 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4785 nonzero
= GET_MODE_MASK (xmode
)
4786 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
4787 known_x
, known_mode
, known_ret
);
4789 /* If the inner mode is a single word for both the host and target
4790 machines, we can compute this from which bits of the inner
4791 object might be nonzero. */
4792 inner_mode
= GET_MODE (SUBREG_REG (x
));
4793 if (GET_MODE_PRECISION (inner_mode
).is_constant (&inner_width
)
4794 && inner_width
<= BITS_PER_WORD
4795 && inner_width
<= HOST_BITS_PER_WIDE_INT
)
4797 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4798 known_x
, known_mode
, known_ret
);
4800 /* On a typical CISC machine, accessing an object in a wider mode
4801 causes the high-order bits to become undefined. So they are
4802 not known to be zero.
4804 On a typical RISC machine, we only have to worry about the way
4805 loads are extended. Otherwise, if we get a reload for the inner
4806 part, it may be loaded from the stack, and then we may lose all
4807 the zero bits that existed before the store to the stack. */
4809 if ((!WORD_REGISTER_OPERATIONS
4810 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4811 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4812 : extend_op
!= ZERO_EXTEND
)
4813 || (!MEM_P (SUBREG_REG (x
)) && !REG_P (SUBREG_REG (x
))))
4814 && xmode_width
> inner_width
)
4816 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4825 /* The nonzero bits are in two classes: any bits within MODE
4826 that aren't in xmode are always significant. The rest of the
4827 nonzero bits are those that are significant in the operand of
4828 the shift when shifted the appropriate number of bits. This
4829 shows that high-order bits are cleared by the right shift and
4830 low-order bits by left shifts. */
4831 if (CONST_INT_P (XEXP (x
, 1))
4832 && INTVAL (XEXP (x
, 1)) >= 0
4833 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4834 && INTVAL (XEXP (x
, 1)) < xmode_width
)
4836 int count
= INTVAL (XEXP (x
, 1));
4837 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
4838 unsigned HOST_WIDE_INT op_nonzero
4839 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4840 known_x
, known_mode
, known_ret
);
4841 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4842 unsigned HOST_WIDE_INT outer
= 0;
4844 if (mode_width
> xmode_width
)
4845 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4860 /* If the sign bit may have been nonzero before the shift, we
4861 need to mark all the places it could have been copied to
4862 by the shift as possibly nonzero. */
4863 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
4864 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
4865 << (xmode_width
- count
));
4869 inner
= (inner
<< (count
% xmode_width
)
4870 | (inner
>> (xmode_width
- (count
% xmode_width
))))
4875 inner
= (inner
>> (count
% xmode_width
)
4876 | (inner
<< (xmode_width
- (count
% xmode_width
))))
4884 nonzero
&= (outer
| inner
);
4890 /* This is at most the number of bits in the mode. */
4891 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4895 /* If CLZ has a known value at zero, then the nonzero bits are
4896 that value, plus the number of bits in the mode minus one. */
4897 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4899 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4905 /* If CTZ has a known value at zero, then the nonzero bits are
4906 that value, plus the number of bits in the mode minus one. */
4907 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4909 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4915 /* This is at most the number of bits in the mode minus 1. */
4916 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4925 unsigned HOST_WIDE_INT nonzero_true
4926 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4927 known_x
, known_mode
, known_ret
);
4929 /* Don't call nonzero_bits for the second time if it cannot change
4931 if ((nonzero
& nonzero_true
) != nonzero
)
4932 nonzero
&= nonzero_true
4933 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4934 known_x
, known_mode
, known_ret
);
4945 /* See the macro definition above. */
4946 #undef cached_num_sign_bit_copies
4949 /* Return true if num_sign_bit_copies1 might recurse into both operands
4953 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4955 if (!ARITHMETIC_P (x
))
4957 switch (GET_CODE (x
))
4975 /* The function cached_num_sign_bit_copies is a wrapper around
4976 num_sign_bit_copies1. It avoids exponential behavior in
4977 num_sign_bit_copies1 when X has identical subexpressions on the
4978 first or the second level. */
4981 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
4982 const_rtx known_x
, machine_mode known_mode
,
4983 unsigned int known_ret
)
4985 if (x
== known_x
&& mode
== known_mode
)
4988 /* Try to find identical subexpressions. If found call
4989 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4990 the precomputed value for the subexpression as KNOWN_RET. */
4992 if (num_sign_bit_copies_binary_arith_p (x
))
4994 rtx x0
= XEXP (x
, 0);
4995 rtx x1
= XEXP (x
, 1);
4997 /* Check the first level. */
5000 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5001 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5005 /* Check the second level. */
5006 if (num_sign_bit_copies_binary_arith_p (x0
)
5007 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
5009 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
5010 cached_num_sign_bit_copies (x1
, mode
, known_x
,
5014 if (num_sign_bit_copies_binary_arith_p (x1
)
5015 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
5017 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5018 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5023 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
5026 /* Return the number of bits at the high-order end of X that are known to
5027 be equal to the sign bit. X will be used in mode MODE. The returned
5028 value will always be between 1 and the number of bits in MODE. */
5031 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
5032 machine_mode known_mode
,
5033 unsigned int known_ret
)
5035 enum rtx_code code
= GET_CODE (x
);
5036 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
5037 int num0
, num1
, result
;
5038 unsigned HOST_WIDE_INT nonzero
;
5040 if (CONST_INT_P (x
))
5042 /* If the constant is negative, take its 1's complement and remask.
5043 Then see how many zero bits we have. */
5044 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
5045 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5046 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5047 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5049 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5052 scalar_int_mode xmode
, inner_mode
;
5053 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
5056 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
5058 /* For a smaller mode, just ignore the high bits. */
5059 if (bitwidth
< xmode_width
)
5061 num0
= cached_num_sign_bit_copies (x
, xmode
,
5062 known_x
, known_mode
, known_ret
);
5063 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
5066 if (bitwidth
> xmode_width
)
5068 /* If this machine does not do all register operations on the entire
5069 register and MODE is wider than the mode of X, we can say nothing
5070 at all about the high-order bits. We extend this reasoning to RISC
5071 machines for operations that might not operate on full registers. */
5072 if (!(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
5075 /* Likewise on machines that do, if the mode of the object is smaller
5076 than a word and loads of that size don't sign extend, we can say
5077 nothing about the high order bits. */
5078 if (xmode_width
< BITS_PER_WORD
5079 && load_extend_op (xmode
) != SIGN_EXTEND
)
5083 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5084 the code in the switch below. */
5089 #if defined(POINTERS_EXTEND_UNSIGNED)
5090 /* If pointers extend signed and this is a pointer in Pmode, say that
5091 all the bits above ptr_mode are known to be sign bit copies. */
5092 /* As we do not know which address space the pointer is referring to,
5093 we can do this only if the target does not support different pointer
5094 or address modes depending on the address space. */
5095 if (target_default_pointer_address_modes_p ()
5096 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
5097 && mode
== Pmode
&& REG_POINTER (x
)
5098 && !targetm
.have_ptr_extend ())
5099 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
5103 unsigned int copies_for_hook
= 1, copies
= 1;
5104 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5108 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5109 known_mode
, known_ret
);
5111 if (copies
> 1 || copies_for_hook
> 1)
5112 return MAX (copies
, copies_for_hook
);
5114 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5119 /* Some RISC machines sign-extend all loads of smaller than a word. */
5120 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5121 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5125 /* If this is a SUBREG for a promoted object that is sign-extended
5126 and we are looking at it in a wider mode, we know that at least the
5127 high-order bits are known to be sign bit copies. */
5129 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5131 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5132 known_x
, known_mode
, known_ret
);
5133 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5136 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5138 /* For a smaller object, just ignore the high bits. */
5139 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5141 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5142 known_x
, known_mode
,
5144 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5148 /* For paradoxical SUBREGs on machines where all register operations
5149 affect the entire register, just look inside. Note that we are
5150 passing MODE to the recursive call, so the number of sign bit
5151 copies will remain relative to that mode, not the inner mode.
5153 This works only if loads sign extend. Otherwise, if we get a
5154 reload for the inner part, it may be loaded from the stack, and
5155 then we lose all sign bit copies that existed before the store
5157 if (WORD_REGISTER_OPERATIONS
5158 && load_extend_op (inner_mode
) == SIGN_EXTEND
5159 && paradoxical_subreg_p (x
)
5160 && MEM_P (SUBREG_REG (x
)))
5161 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5162 known_x
, known_mode
, known_ret
);
5167 if (CONST_INT_P (XEXP (x
, 1)))
5168 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5172 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5173 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5174 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5175 known_x
, known_mode
, known_ret
));
5179 /* For a smaller object, just ignore the high bits. */
5180 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5181 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5182 known_x
, known_mode
, known_ret
);
5183 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5187 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5188 known_x
, known_mode
, known_ret
);
5190 case ROTATE
: case ROTATERT
:
5191 /* If we are rotating left by a number of bits less than the number
5192 of sign bit copies, we can just subtract that amount from the
5194 if (CONST_INT_P (XEXP (x
, 1))
5195 && INTVAL (XEXP (x
, 1)) >= 0
5196 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5198 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5199 known_x
, known_mode
, known_ret
);
5200 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5201 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5206 /* In general, this subtracts one sign bit copy. But if the value
5207 is known to be positive, the number of sign bit copies is the
5208 same as that of the input. Finally, if the input has just one bit
5209 that might be nonzero, all the bits are copies of the sign bit. */
5210 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5211 known_x
, known_mode
, known_ret
);
5212 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5213 return num0
> 1 ? num0
- 1 : 1;
5215 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5220 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5225 case IOR
: case AND
: case XOR
:
5226 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5227 /* Logical operations will preserve the number of sign-bit copies.
5228 MIN and MAX operations always return one of the operands. */
5229 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5230 known_x
, known_mode
, known_ret
);
5231 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5232 known_x
, known_mode
, known_ret
);
5234 /* If num1 is clearing some of the top bits then regardless of
5235 the other term, we are guaranteed to have at least that many
5236 high-order zero bits. */
5239 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5240 && CONST_INT_P (XEXP (x
, 1))
5241 && (UINTVAL (XEXP (x
, 1))
5242 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5245 /* Similarly for IOR when setting high-order bits. */
5248 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5249 && CONST_INT_P (XEXP (x
, 1))
5250 && (UINTVAL (XEXP (x
, 1))
5251 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5254 return MIN (num0
, num1
);
5256 case PLUS
: case MINUS
:
5257 /* For addition and subtraction, we can have a 1-bit carry. However,
5258 if we are subtracting 1 from a positive number, there will not
5259 be such a carry. Furthermore, if the positive number is known to
5260 be 0 or 1, we know the result is either -1 or 0. */
5262 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5263 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5265 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5266 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5267 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5268 : bitwidth
- floor_log2 (nonzero
) - 1);
5271 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5272 known_x
, known_mode
, known_ret
);
5273 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5274 known_x
, known_mode
, known_ret
);
5275 result
= MAX (1, MIN (num0
, num1
) - 1);
5280 /* The number of bits of the product is the sum of the number of
5281 bits of both terms. However, unless one of the terms if known
5282 to be positive, we must allow for an additional bit since negating
5283 a negative number can remove one sign bit copy. */
5285 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5286 known_x
, known_mode
, known_ret
);
5287 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5288 known_x
, known_mode
, known_ret
);
5290 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5292 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5293 || (((nonzero_bits (XEXP (x
, 0), mode
)
5294 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5295 && ((nonzero_bits (XEXP (x
, 1), mode
)
5296 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5300 return MAX (1, result
);
5303 /* The result must be <= the first operand. If the first operand
5304 has the high bit set, we know nothing about the number of sign
5306 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5308 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5309 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5312 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5313 known_x
, known_mode
, known_ret
);
5316 /* The result must be <= the second operand. If the second operand
5317 has (or just might have) the high bit set, we know nothing about
5318 the number of sign bit copies. */
5319 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5321 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5322 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5325 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5326 known_x
, known_mode
, known_ret
);
5329 /* Similar to unsigned division, except that we have to worry about
5330 the case where the divisor is negative, in which case we have
5332 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5333 known_x
, known_mode
, known_ret
);
5335 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5336 || (nonzero_bits (XEXP (x
, 1), mode
)
5337 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5343 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5344 known_x
, known_mode
, known_ret
);
5346 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5347 || (nonzero_bits (XEXP (x
, 1), mode
)
5348 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5354 /* Shifts by a constant add to the number of bits equal to the
5356 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5357 known_x
, known_mode
, known_ret
);
5358 if (CONST_INT_P (XEXP (x
, 1))
5359 && INTVAL (XEXP (x
, 1)) > 0
5360 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5361 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5366 /* Left shifts destroy copies. */
5367 if (!CONST_INT_P (XEXP (x
, 1))
5368 || INTVAL (XEXP (x
, 1)) < 0
5369 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5370 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5373 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5374 known_x
, known_mode
, known_ret
);
5375 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5378 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5379 known_x
, known_mode
, known_ret
);
5380 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5381 known_x
, known_mode
, known_ret
);
5382 return MIN (num0
, num1
);
5384 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5385 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5386 case GEU
: case GTU
: case LEU
: case LTU
:
5387 case UNORDERED
: case ORDERED
:
5388 /* If the constant is negative, take its 1's complement and remask.
5389 Then see how many zero bits we have. */
5390 nonzero
= STORE_FLAG_VALUE
;
5391 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5392 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5393 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5395 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5401 /* If we haven't been able to figure it out by one of the above rules,
5402 see if some of the high-order bits are known to be zero. If so,
5403 count those bits and return one less than that amount. If we can't
5404 safely compute the mask for this mode, always return BITWIDTH. */
5406 bitwidth
= GET_MODE_PRECISION (mode
);
5407 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5410 nonzero
= nonzero_bits (x
, mode
);
5411 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5412 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5415 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5416 zero indicates an instruction pattern without a known cost. */
5419 pattern_cost (rtx pat
, bool speed
)
5424 /* Extract the single set rtx from the instruction pattern. We
5425 can't use single_set since we only have the pattern. We also
5426 consider PARALLELs of a normal set and a single comparison. In
5427 that case we use the cost of the non-comparison SET operation,
5428 which is most-likely to be the real cost of this operation. */
5429 if (GET_CODE (pat
) == SET
)
5431 else if (GET_CODE (pat
) == PARALLEL
)
5434 rtx comparison
= NULL_RTX
;
5436 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5438 rtx x
= XVECEXP (pat
, 0, i
);
5439 if (GET_CODE (x
) == SET
)
5441 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5456 if (!set
&& comparison
)
5465 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5466 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5469 /* Calculate the cost of a single instruction. A return value of zero
5470 indicates an instruction pattern without a known cost. */
5473 insn_cost (rtx_insn
*insn
, bool speed
)
5475 if (targetm
.insn_cost
)
5476 return targetm
.insn_cost (insn
, speed
);
5478 return pattern_cost (PATTERN (insn
), speed
);
5481 /* Returns estimate on cost of computing SEQ. */
5484 seq_cost (const rtx_insn
*seq
, bool speed
)
5489 for (; seq
; seq
= NEXT_INSN (seq
))
5491 set
= single_set (seq
);
5493 cost
+= set_rtx_cost (set
, speed
);
5494 else if (NONDEBUG_INSN_P (seq
))
5496 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5507 /* Given an insn INSN and condition COND, return the condition in a
5508 canonical form to simplify testing by callers. Specifically:
5510 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5511 (2) Both operands will be machine operands; (cc0) will have been replaced.
5512 (3) If an operand is a constant, it will be the second operand.
5513 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5514 for GE, GEU, and LEU.
5516 If the condition cannot be understood, or is an inequality floating-point
5517 comparison which needs to be reversed, 0 will be returned.
5519 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5521 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5522 insn used in locating the condition was found. If a replacement test
5523 of the condition is desired, it should be placed in front of that
5524 insn and we will be sure that the inputs are still valid.
5526 If WANT_REG is nonzero, we wish the condition to be relative to that
5527 register, if possible. Therefore, do not canonicalize the condition
5528 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5529 to be a compare to a CC mode register.
5531 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5535 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5536 rtx_insn
**earliest
,
5537 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5540 rtx_insn
*prev
= insn
;
5544 int reverse_code
= 0;
5546 basic_block bb
= BLOCK_FOR_INSN (insn
);
5548 code
= GET_CODE (cond
);
5549 mode
= GET_MODE (cond
);
5550 op0
= XEXP (cond
, 0);
5551 op1
= XEXP (cond
, 1);
5554 code
= reversed_comparison_code (cond
, insn
);
5555 if (code
== UNKNOWN
)
5561 /* If we are comparing a register with zero, see if the register is set
5562 in the previous insn to a COMPARE or a comparison operation. Perform
5563 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5566 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5567 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5568 && op1
== CONST0_RTX (GET_MODE (op0
))
5571 /* Set nonzero when we find something of interest. */
5574 /* If comparison with cc0, import actual comparison from compare
5578 if ((prev
= prev_nonnote_insn (prev
)) == 0
5579 || !NONJUMP_INSN_P (prev
)
5580 || (set
= single_set (prev
)) == 0
5581 || SET_DEST (set
) != cc0_rtx
)
5584 op0
= SET_SRC (set
);
5585 op1
= CONST0_RTX (GET_MODE (op0
));
5590 /* If this is a COMPARE, pick up the two things being compared. */
5591 if (GET_CODE (op0
) == COMPARE
)
5593 op1
= XEXP (op0
, 1);
5594 op0
= XEXP (op0
, 0);
5597 else if (!REG_P (op0
))
5600 /* Go back to the previous insn. Stop if it is not an INSN. We also
5601 stop if it isn't a single set or if it has a REG_INC note because
5602 we don't want to bother dealing with it. */
5604 prev
= prev_nonnote_nondebug_insn (prev
);
5607 || !NONJUMP_INSN_P (prev
)
5608 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5609 /* In cfglayout mode, there do not have to be labels at the
5610 beginning of a block, or jumps at the end, so the previous
5611 conditions would not stop us when we reach bb boundary. */
5612 || BLOCK_FOR_INSN (prev
) != bb
)
5615 set
= set_of (op0
, prev
);
5618 && (GET_CODE (set
) != SET
5619 || !rtx_equal_p (SET_DEST (set
), op0
)))
5622 /* If this is setting OP0, get what it sets it to if it looks
5626 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5627 #ifdef FLOAT_STORE_FLAG_VALUE
5628 REAL_VALUE_TYPE fsfv
;
5631 /* ??? We may not combine comparisons done in a CCmode with
5632 comparisons not done in a CCmode. This is to aid targets
5633 like Alpha that have an IEEE compliant EQ instruction, and
5634 a non-IEEE compliant BEQ instruction. The use of CCmode is
5635 actually artificial, simply to prevent the combination, but
5636 should not affect other platforms.
5638 However, we must allow VOIDmode comparisons to match either
5639 CCmode or non-CCmode comparison, because some ports have
5640 modeless comparisons inside branch patterns.
5642 ??? This mode check should perhaps look more like the mode check
5643 in simplify_comparison in combine. */
5644 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5645 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5647 && inner_mode
!= VOIDmode
)
5649 if (GET_CODE (SET_SRC (set
)) == COMPARE
5652 && val_signbit_known_set_p (inner_mode
,
5654 #ifdef FLOAT_STORE_FLAG_VALUE
5656 && SCALAR_FLOAT_MODE_P (inner_mode
)
5657 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5658 REAL_VALUE_NEGATIVE (fsfv
)))
5661 && COMPARISON_P (SET_SRC (set
))))
5663 else if (((code
== EQ
5665 && val_signbit_known_set_p (inner_mode
,
5667 #ifdef FLOAT_STORE_FLAG_VALUE
5669 && SCALAR_FLOAT_MODE_P (inner_mode
)
5670 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5671 REAL_VALUE_NEGATIVE (fsfv
)))
5674 && COMPARISON_P (SET_SRC (set
)))
5679 else if ((code
== EQ
|| code
== NE
)
5680 && GET_CODE (SET_SRC (set
)) == XOR
)
5681 /* Handle sequences like:
5684 ...(eq|ne op0 (const_int 0))...
5688 (eq op0 (const_int 0)) reduces to (eq X Y)
5689 (ne op0 (const_int 0)) reduces to (ne X Y)
5691 This is the form used by MIPS16, for example. */
5697 else if (reg_set_p (op0
, prev
))
5698 /* If this sets OP0, but not directly, we have to give up. */
5703 /* If the caller is expecting the condition to be valid at INSN,
5704 make sure X doesn't change before INSN. */
5705 if (valid_at_insn_p
)
5706 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5708 if (COMPARISON_P (x
))
5709 code
= GET_CODE (x
);
5712 code
= reversed_comparison_code (x
, prev
);
5713 if (code
== UNKNOWN
)
5718 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5724 /* If constant is first, put it last. */
5725 if (CONSTANT_P (op0
))
5726 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5728 /* If OP0 is the result of a comparison, we weren't able to find what
5729 was really being compared, so fail. */
5731 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5734 /* Canonicalize any ordered comparison with integers involving equality
5735 if we can do computations in the relevant mode and we do not
5738 scalar_int_mode op0_mode
;
5739 if (CONST_INT_P (op1
)
5740 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
5741 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
5743 HOST_WIDE_INT const_val
= INTVAL (op1
);
5744 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5745 unsigned HOST_WIDE_INT max_val
5746 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
5751 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5752 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
5755 /* When cross-compiling, const_val might be sign-extended from
5756 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5758 if ((const_val
& max_val
)
5759 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
5760 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
5764 if (uconst_val
< max_val
)
5765 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
5769 if (uconst_val
!= 0)
5770 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
5778 /* Never return CC0; return zero instead. */
5782 /* We promised to return a comparison. */
5783 rtx ret
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5784 if (COMPARISON_P (ret
))
5789 /* Given a jump insn JUMP, return the condition that will cause it to branch
5790 to its JUMP_LABEL. If the condition cannot be understood, or is an
5791 inequality floating-point comparison which needs to be reversed, 0 will
5794 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5795 insn used in locating the condition was found. If a replacement test
5796 of the condition is desired, it should be placed in front of that
5797 insn and we will be sure that the inputs are still valid. If EARLIEST
5798 is null, the returned condition will be valid at INSN.
5800 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5801 compare CC mode register.
5803 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5806 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5807 int valid_at_insn_p
)
5813 /* If this is not a standard conditional jump, we can't parse it. */
5815 || ! any_condjump_p (jump
))
5817 set
= pc_set (jump
);
5819 cond
= XEXP (SET_SRC (set
), 0);
5821 /* If this branches to JUMP_LABEL when the condition is false, reverse
5824 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5825 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5827 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5828 allow_cc_mode
, valid_at_insn_p
);
5831 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5832 TARGET_MODE_REP_EXTENDED.
5834 Note that we assume that the property of
5835 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5836 narrower than mode B. I.e., if A is a mode narrower than B then in
5837 order to be able to operate on it in mode B, mode A needs to
5838 satisfy the requirements set by the representation of mode B. */
5841 init_num_sign_bit_copies_in_rep (void)
5843 opt_scalar_int_mode in_mode_iter
;
5844 scalar_int_mode mode
;
5846 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
5847 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
5849 scalar_int_mode in_mode
= in_mode_iter
.require ();
5852 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5853 extends to the next widest mode. */
5854 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5855 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
5857 /* We are in in_mode. Count how many bits outside of mode
5858 have to be copies of the sign-bit. */
5859 FOR_EACH_MODE (i
, mode
, in_mode
)
5861 /* This must always exist (for the last iteration it will be
5863 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
5865 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5866 /* We can only check sign-bit copies starting from the
5867 top-bit. In order to be able to check the bits we
5868 have already seen we pretend that subsequent bits
5869 have to be sign-bit copies too. */
5870 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5871 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5872 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5877 /* Suppose that truncation from the machine mode of X to MODE is not a
5878 no-op. See if there is anything special about X so that we can
5879 assume it already contains a truncated value of MODE. */
5882 truncated_to_mode (machine_mode mode
, const_rtx x
)
5884 /* This register has already been used in MODE without explicit
5886 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5889 /* See if we already satisfy the requirements of MODE. If yes we
5890 can just switch to MODE. */
5891 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5892 && (num_sign_bit_copies (x
, GET_MODE (x
))
5893 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5899 /* Return true if RTX code CODE has a single sequence of zero or more
5900 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5901 entry in that case. */
5904 setup_reg_subrtx_bounds (unsigned int code
)
5906 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5908 for (; format
[i
] != 'e'; ++i
)
5911 /* No subrtxes. Leave start and count as 0. */
5913 if (format
[i
] == 'E' || format
[i
] == 'V')
5917 /* Record the sequence of 'e's. */
5918 rtx_all_subrtx_bounds
[code
].start
= i
;
5921 while (format
[i
] == 'e');
5922 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5923 /* rtl-iter.h relies on this. */
5924 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5926 for (; format
[i
]; ++i
)
5927 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5933 /* Initialize rtx_all_subrtx_bounds. */
5938 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5940 if (!setup_reg_subrtx_bounds (i
))
5941 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5942 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5943 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5946 init_num_sign_bit_copies_in_rep ();
5949 /* Check whether this is a constant pool constant. */
5951 constant_pool_constant_p (rtx x
)
5953 x
= avoid_constant_pool_reference (x
);
5954 return CONST_DOUBLE_P (x
);
5957 /* If M is a bitmask that selects a field of low-order bits within an item but
5958 not the entire word, return the length of the field. Return -1 otherwise.
5959 M is used in machine mode MODE. */
5962 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5964 if (mode
!= VOIDmode
)
5966 if (!HWI_COMPUTABLE_MODE_P (mode
))
5968 m
&= GET_MODE_MASK (mode
);
5971 return exact_log2 (m
+ 1);
5974 /* Return the mode of MEM's address. */
5977 get_address_mode (rtx mem
)
5981 gcc_assert (MEM_P (mem
));
5982 mode
= GET_MODE (XEXP (mem
, 0));
5983 if (mode
!= VOIDmode
)
5984 return as_a
<scalar_int_mode
> (mode
);
5985 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5988 /* Split up a CONST_DOUBLE or integer constant rtx
5989 into two rtx's for single words,
5990 storing in *FIRST the word that comes first in memory in the target
5991 and in *SECOND the other.
5993 TODO: This function needs to be rewritten to work on any size
5997 split_double (rtx value
, rtx
*first
, rtx
*second
)
5999 if (CONST_INT_P (value
))
6001 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
6003 /* In this case the CONST_INT holds both target words.
6004 Extract the bits from it into two word-sized pieces.
6005 Sign extend each half to HOST_WIDE_INT. */
6006 unsigned HOST_WIDE_INT low
, high
;
6007 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
6008 unsigned bits_per_word
= BITS_PER_WORD
;
6010 /* Set sign_bit to the most significant bit of a word. */
6012 sign_bit
<<= bits_per_word
- 1;
6014 /* Set mask so that all bits of the word are set. We could
6015 have used 1 << BITS_PER_WORD instead of basing the
6016 calculation on sign_bit. However, on machines where
6017 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
6018 compiler warning, even though the code would never be
6020 mask
= sign_bit
<< 1;
6023 /* Set sign_extend as any remaining bits. */
6024 sign_extend
= ~mask
;
6026 /* Pick the lower word and sign-extend it. */
6027 low
= INTVAL (value
);
6032 /* Pick the higher word, shifted to the least significant
6033 bits, and sign-extend it. */
6034 high
= INTVAL (value
);
6035 high
>>= bits_per_word
- 1;
6038 if (high
& sign_bit
)
6039 high
|= sign_extend
;
6041 /* Store the words in the target machine order. */
6042 if (WORDS_BIG_ENDIAN
)
6044 *first
= GEN_INT (high
);
6045 *second
= GEN_INT (low
);
6049 *first
= GEN_INT (low
);
6050 *second
= GEN_INT (high
);
6055 /* The rule for using CONST_INT for a wider mode
6056 is that we regard the value as signed.
6057 So sign-extend it. */
6058 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
6059 if (WORDS_BIG_ENDIAN
)
6071 else if (GET_CODE (value
) == CONST_WIDE_INT
)
6073 /* All of this is scary code and needs to be converted to
6074 properly work with any size integer. */
6075 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
6076 if (WORDS_BIG_ENDIAN
)
6078 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6079 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6083 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6084 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6087 else if (!CONST_DOUBLE_P (value
))
6089 if (WORDS_BIG_ENDIAN
)
6091 *first
= const0_rtx
;
6097 *second
= const0_rtx
;
6100 else if (GET_MODE (value
) == VOIDmode
6101 /* This is the old way we did CONST_DOUBLE integers. */
6102 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
6104 /* In an integer, the words are defined as most and least significant.
6105 So order them by the target's convention. */
6106 if (WORDS_BIG_ENDIAN
)
6108 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6109 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6113 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6114 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6121 /* Note, this converts the REAL_VALUE_TYPE to the target's
6122 format, splits up the floating point double and outputs
6123 exactly 32 bits of it into each of l[0] and l[1] --
6124 not necessarily BITS_PER_WORD bits. */
6125 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6127 /* If 32 bits is an entire word for the target, but not for the host,
6128 then sign-extend on the host so that the number will look the same
6129 way on the host that it would on the target. See for instance
6130 simplify_unary_operation. The #if is needed to avoid compiler
6133 #if HOST_BITS_PER_LONG > 32
6134 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6136 if (l
[0] & ((long) 1 << 31))
6137 l
[0] |= ((unsigned long) (-1) << 32);
6138 if (l
[1] & ((long) 1 << 31))
6139 l
[1] |= ((unsigned long) (-1) << 32);
6143 *first
= GEN_INT (l
[0]);
6144 *second
= GEN_INT (l
[1]);
6148 /* Return true if X is a sign_extract or zero_extract from the least
6152 lsb_bitfield_op_p (rtx x
)
6154 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6156 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6157 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6158 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6159 poly_int64 remaining_bits
= GET_MODE_PRECISION (mode
) - len
;
6161 return known_eq (pos
, BITS_BIG_ENDIAN
? remaining_bits
: 0);
6166 /* Strip outer address "mutations" from LOC and return a pointer to the
6167 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6168 stripped expression there.
6170 "Mutations" either convert between modes or apply some kind of
6171 extension, truncation or alignment. */
6174 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6178 enum rtx_code code
= GET_CODE (*loc
);
6179 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6180 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6181 used to convert between pointer sizes. */
6182 loc
= &XEXP (*loc
, 0);
6183 else if (lsb_bitfield_op_p (*loc
))
6184 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6185 acts as a combined truncation and extension. */
6186 loc
= &XEXP (*loc
, 0);
6187 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6188 /* (and ... (const_int -X)) is used to align to X bytes. */
6189 loc
= &XEXP (*loc
, 0);
6190 else if (code
== SUBREG
6191 && !OBJECT_P (SUBREG_REG (*loc
))
6192 && subreg_lowpart_p (*loc
))
6193 /* (subreg (operator ...) ...) inside and is used for mode
6195 loc
= &SUBREG_REG (*loc
);
6203 /* Return true if CODE applies some kind of scale. The scaled value is
6204 is the first operand and the scale is the second. */
6207 binary_scale_code_p (enum rtx_code code
)
6209 return (code
== MULT
6211 /* Needed by ARM targets. */
6215 || code
== ROTATERT
);
6218 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6219 (see address_info). Return null otherwise. */
6222 get_base_term (rtx
*inner
)
6224 if (GET_CODE (*inner
) == LO_SUM
)
6225 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6228 || GET_CODE (*inner
) == SUBREG
6229 || GET_CODE (*inner
) == SCRATCH
)
6234 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6235 (see address_info). Return null otherwise. */
6238 get_index_term (rtx
*inner
)
6240 /* At present, only constant scales are allowed. */
6241 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6242 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6245 || GET_CODE (*inner
) == SUBREG
6246 || GET_CODE (*inner
) == SCRATCH
)
6251 /* Set the segment part of address INFO to LOC, given that INNER is the
6255 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6257 gcc_assert (!info
->segment
);
6258 info
->segment
= loc
;
6259 info
->segment_term
= inner
;
6262 /* Set the base part of address INFO to LOC, given that INNER is the
6266 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6268 gcc_assert (!info
->base
);
6270 info
->base_term
= inner
;
6273 /* Set the index part of address INFO to LOC, given that INNER is the
6277 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6279 gcc_assert (!info
->index
);
6281 info
->index_term
= inner
;
6284 /* Set the displacement part of address INFO to LOC, given that INNER
6285 is the constant term. */
6288 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6290 gcc_assert (!info
->disp
);
6292 info
->disp_term
= inner
;
6295 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6296 rest of INFO accordingly. */
6299 decompose_incdec_address (struct address_info
*info
)
6301 info
->autoinc_p
= true;
6303 rtx
*base
= &XEXP (*info
->inner
, 0);
6304 set_address_base (info
, base
, base
);
6305 gcc_checking_assert (info
->base
== info
->base_term
);
6307 /* These addresses are only valid when the size of the addressed
6309 gcc_checking_assert (info
->mode
!= VOIDmode
);
6312 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6313 of INFO accordingly. */
6316 decompose_automod_address (struct address_info
*info
)
6318 info
->autoinc_p
= true;
6320 rtx
*base
= &XEXP (*info
->inner
, 0);
6321 set_address_base (info
, base
, base
);
6322 gcc_checking_assert (info
->base
== info
->base_term
);
6324 rtx plus
= XEXP (*info
->inner
, 1);
6325 gcc_assert (GET_CODE (plus
) == PLUS
);
6327 info
->base_term2
= &XEXP (plus
, 0);
6328 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6330 rtx
*step
= &XEXP (plus
, 1);
6331 rtx
*inner_step
= strip_address_mutations (step
);
6332 if (CONSTANT_P (*inner_step
))
6333 set_address_disp (info
, step
, inner_step
);
6335 set_address_index (info
, step
, inner_step
);
6338 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6339 values in [PTR, END). Return a pointer to the end of the used array. */
6342 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6345 if (GET_CODE (x
) == PLUS
)
6347 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6348 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6352 gcc_assert (ptr
!= end
);
6358 /* Evaluate the likelihood of X being a base or index value, returning
6359 positive if it is likely to be a base, negative if it is likely to be
6360 an index, and 0 if we can't tell. Make the magnitude of the return
6361 value reflect the amount of confidence we have in the answer.
6363 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6366 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6367 enum rtx_code outer_code
, enum rtx_code index_code
)
6369 /* Believe *_POINTER unless the address shape requires otherwise. */
6370 if (REG_P (x
) && REG_POINTER (x
))
6372 if (MEM_P (x
) && MEM_POINTER (x
))
6375 if (REG_P (x
) && HARD_REGISTER_P (x
))
6377 /* X is a hard register. If it only fits one of the base
6378 or index classes, choose that interpretation. */
6379 int regno
= REGNO (x
);
6380 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6381 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6382 if (base_p
!= index_p
)
6383 return base_p
? 1 : -1;
6388 /* INFO->INNER describes a normal, non-automodified address.
6389 Fill in the rest of INFO accordingly. */
6392 decompose_normal_address (struct address_info
*info
)
6394 /* Treat the address as the sum of up to four values. */
6396 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6397 ops
+ ARRAY_SIZE (ops
)) - ops
;
6399 /* If there is more than one component, any base component is in a PLUS. */
6401 info
->base_outer_code
= PLUS
;
6403 /* Try to classify each sum operand now. Leave those that could be
6404 either a base or an index in OPS. */
6407 for (size_t in
= 0; in
< n_ops
; ++in
)
6410 rtx
*inner
= strip_address_mutations (loc
);
6411 if (CONSTANT_P (*inner
))
6412 set_address_disp (info
, loc
, inner
);
6413 else if (GET_CODE (*inner
) == UNSPEC
)
6414 set_address_segment (info
, loc
, inner
);
6417 /* The only other possibilities are a base or an index. */
6418 rtx
*base_term
= get_base_term (inner
);
6419 rtx
*index_term
= get_index_term (inner
);
6420 gcc_assert (base_term
|| index_term
);
6422 set_address_index (info
, loc
, index_term
);
6423 else if (!index_term
)
6424 set_address_base (info
, loc
, base_term
);
6427 gcc_assert (base_term
== index_term
);
6429 inner_ops
[out
] = base_term
;
6435 /* Classify the remaining OPS members as bases and indexes. */
6438 /* If we haven't seen a base or an index yet, assume that this is
6439 the base. If we were confident that another term was the base
6440 or index, treat the remaining operand as the other kind. */
6442 set_address_base (info
, ops
[0], inner_ops
[0]);
6444 set_address_index (info
, ops
[0], inner_ops
[0]);
6448 /* In the event of a tie, assume the base comes first. */
6449 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6451 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6452 GET_CODE (*ops
[0])))
6454 set_address_base (info
, ops
[0], inner_ops
[0]);
6455 set_address_index (info
, ops
[1], inner_ops
[1]);
6459 set_address_base (info
, ops
[1], inner_ops
[1]);
6460 set_address_index (info
, ops
[0], inner_ops
[0]);
6464 gcc_assert (out
== 0);
6467 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6468 or VOIDmode if not known. AS is the address space associated with LOC.
6469 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6472 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6473 addr_space_t as
, enum rtx_code outer_code
)
6475 memset (info
, 0, sizeof (*info
));
6478 info
->addr_outer_code
= outer_code
;
6480 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6481 info
->base_outer_code
= outer_code
;
6482 switch (GET_CODE (*info
->inner
))
6488 decompose_incdec_address (info
);
6493 decompose_automod_address (info
);
6497 decompose_normal_address (info
);
6502 /* Describe address operand LOC in INFO. */
6505 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6507 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6510 /* Describe the address of MEM X in INFO. */
6513 decompose_mem_address (struct address_info
*info
, rtx x
)
6515 gcc_assert (MEM_P (x
));
6516 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6517 MEM_ADDR_SPACE (x
), MEM
);
6520 /* Update INFO after a change to the address it describes. */
6523 update_address (struct address_info
*info
)
6525 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6526 info
->addr_outer_code
);
6529 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6530 more complicated than that. */
6533 get_index_scale (const struct address_info
*info
)
6535 rtx index
= *info
->index
;
6536 if (GET_CODE (index
) == MULT
6537 && CONST_INT_P (XEXP (index
, 1))
6538 && info
->index_term
== &XEXP (index
, 0))
6539 return INTVAL (XEXP (index
, 1));
6541 if (GET_CODE (index
) == ASHIFT
6542 && CONST_INT_P (XEXP (index
, 1))
6543 && info
->index_term
== &XEXP (index
, 0))
6544 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6546 if (info
->index
== info
->index_term
)
6552 /* Return the "index code" of INFO, in the form required by
6556 get_index_code (const struct address_info
*info
)
6559 return GET_CODE (*info
->index
);
6562 return GET_CODE (*info
->disp
);
6567 /* Return true if RTL X contains a SYMBOL_REF. */
6570 contains_symbol_ref_p (const_rtx x
)
6572 subrtx_iterator::array_type array
;
6573 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6574 if (SYMBOL_REF_P (*iter
))
6580 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6583 contains_symbolic_reference_p (const_rtx x
)
6585 subrtx_iterator::array_type array
;
6586 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6587 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6593 /* Return true if RTL X contains a constant pool address. */
6596 contains_constant_pool_address_p (const_rtx x
)
6598 subrtx_iterator::array_type array
;
6599 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6600 if (SYMBOL_REF_P (*iter
) && CONSTANT_POOL_ADDRESS_P (*iter
))
6607 /* Return true if X contains a thread-local symbol. */
6610 tls_referenced_p (const_rtx x
)
6612 if (!targetm
.have_tls
)
6615 subrtx_iterator::array_type array
;
6616 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6617 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)
6622 /* Return true if reg REGNO with mode REG_MODE would be clobbered by the
6623 clobber_high operand in CLOBBER_HIGH_OP. */
6626 reg_is_clobbered_by_clobber_high (unsigned int regno
, machine_mode reg_mode
,
6627 const_rtx clobber_high_op
)
6629 unsigned int clobber_regno
= REGNO (clobber_high_op
);
6630 machine_mode clobber_mode
= GET_MODE (clobber_high_op
);
6631 unsigned char regno_nregs
= hard_regno_nregs (regno
, reg_mode
);
6633 /* Clobber high should always span exactly one register. */
6634 gcc_assert (REG_NREGS (clobber_high_op
) == 1);
6636 /* Clobber high needs to match with one of the registers in X. */
6637 if (clobber_regno
< regno
|| clobber_regno
>= regno
+ regno_nregs
)
6640 gcc_assert (reg_mode
!= BLKmode
&& clobber_mode
!= BLKmode
);
6642 if (reg_mode
== VOIDmode
)
6643 return clobber_mode
!= VOIDmode
;
6645 /* Clobber high will clobber if its size might be greater than the size of
6647 return maybe_gt (exact_div (GET_MODE_SIZE (reg_mode
), regno_nregs
),
6648 GET_MODE_SIZE (clobber_mode
));