1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "diagnostic-core.h"
29 /* Include insn-config.h before expr.h so that HAVE_conditional_move
30 is properly defined. */
31 #include "insn-config.h"
44 #include "basic-block.h"
47 struct target_optabs default_target_optabs
;
48 struct target_libfuncs default_target_libfuncs
;
50 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
51 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
54 #define libfunc_hash \
55 (this_target_libfuncs->x_libfunc_hash)
57 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
59 static rtx
expand_unop_direct (enum machine_mode
, optab
, rtx
, rtx
, int);
60 static void emit_libcall_block_1 (rtx
, rtx
, rtx
, rtx
, bool);
62 /* Debug facility for use in GDB. */
63 void debug_optab_libfuncs (void);
65 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
66 #if ENABLE_DECIMAL_BID_FORMAT
67 #define DECIMAL_PREFIX "bid_"
69 #define DECIMAL_PREFIX "dpd_"
72 /* Used for libfunc_hash. */
75 hash_libfunc (const void *p
)
77 const struct libfunc_entry
*const e
= (const struct libfunc_entry
*) p
;
78 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
81 /* Used for libfunc_hash. */
84 eq_libfunc (const void *p
, const void *q
)
86 const struct libfunc_entry
*const e1
= (const struct libfunc_entry
*) p
;
87 const struct libfunc_entry
*const e2
= (const struct libfunc_entry
*) q
;
88 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
91 /* Return libfunc corresponding operation defined by OPTAB converting
92 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
93 if no libfunc is available. */
95 convert_optab_libfunc (convert_optab optab
, enum machine_mode mode1
,
96 enum machine_mode mode2
)
98 struct libfunc_entry e
;
99 struct libfunc_entry
**slot
;
101 /* ??? This ought to be an assert, but not all of the places
102 that we expand optabs know about the optabs that got moved
104 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
110 slot
= (struct libfunc_entry
**)
111 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
114 const struct convert_optab_libcall_d
*d
115 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
117 if (d
->libcall_gen
== NULL
)
120 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
121 slot
= (struct libfunc_entry
**)
122 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
126 return (*slot
)->libfunc
;
129 /* Return libfunc corresponding operation defined by OPTAB in MODE.
130 Trigger lazy initialization if needed, return NULL if no libfunc is
133 optab_libfunc (optab optab
, enum machine_mode mode
)
135 struct libfunc_entry e
;
136 struct libfunc_entry
**slot
;
138 /* ??? This ought to be an assert, but not all of the places
139 that we expand optabs know about the optabs that got moved
141 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
147 slot
= (struct libfunc_entry
**)
148 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
151 const struct optab_libcall_d
*d
152 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
154 if (d
->libcall_gen
== NULL
)
157 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
158 slot
= (struct libfunc_entry
**)
159 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
163 return (*slot
)->libfunc
;
167 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
168 the result of operation CODE applied to OP0 (and OP1 if it is a binary
171 If the last insn does not set TARGET, don't do anything, but return 1.
173 If a previous insn sets TARGET and TARGET is one of OP0 or OP1,
174 don't add the REG_EQUAL note but return 0. Our caller can then try
175 again, ensuring that TARGET is not one of the operands. */
178 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
180 rtx last_insn
, insn
, set
;
183 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
185 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
186 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
187 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
188 && GET_RTX_CLASS (code
) != RTX_COMPARE
189 && GET_RTX_CLASS (code
) != RTX_UNARY
)
192 if (GET_CODE (target
) == ZERO_EXTRACT
)
195 for (last_insn
= insns
;
196 NEXT_INSN (last_insn
) != NULL_RTX
;
197 last_insn
= NEXT_INSN (last_insn
))
200 set
= single_set (last_insn
);
204 if (! rtx_equal_p (SET_DEST (set
), target
)
205 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
206 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
207 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
210 /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET
211 besides the last insn. */
212 if (reg_overlap_mentioned_p (target
, op0
)
213 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
215 insn
= PREV_INSN (last_insn
);
216 while (insn
!= NULL_RTX
)
218 if (reg_set_p (target
, insn
))
221 insn
= PREV_INSN (insn
);
225 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
235 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
237 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
238 if (GET_MODE_SIZE (GET_MODE (op0
))
239 > GET_MODE_SIZE (GET_MODE (target
)))
240 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
241 note
, GET_MODE (op0
));
243 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
244 note
, GET_MODE (op0
));
249 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
253 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
255 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
260 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
261 for a widening operation would be. In most cases this would be OP0, but if
262 that's a constant it'll be VOIDmode, which isn't useful. */
264 static enum machine_mode
265 widened_mode (enum machine_mode to_mode
, rtx op0
, rtx op1
)
267 enum machine_mode m0
= GET_MODE (op0
);
268 enum machine_mode m1
= GET_MODE (op1
);
269 enum machine_mode result
;
271 if (m0
== VOIDmode
&& m1
== VOIDmode
)
273 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
278 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
284 /* Find a widening optab even if it doesn't widen as much as we want.
285 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
286 direct HI->SI insn, then return SI->DI, if that exists.
287 If PERMIT_NON_WIDENING is non-zero then this can be used with
288 non-widening optabs also. */
291 find_widening_optab_handler_and_mode (optab op
, enum machine_mode to_mode
,
292 enum machine_mode from_mode
,
293 int permit_non_widening
,
294 enum machine_mode
*found_mode
)
296 for (; (permit_non_widening
|| from_mode
!= to_mode
)
297 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
298 && from_mode
!= VOIDmode
;
299 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
301 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
304 if (handler
!= CODE_FOR_nothing
)
307 *found_mode
= from_mode
;
312 return CODE_FOR_nothing
;
315 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
316 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
317 not actually do a sign-extend or zero-extend, but can leave the
318 higher-order bits of the result rtx undefined, for example, in the case
319 of logical operations, but not right shifts. */
322 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
323 int unsignedp
, int no_extend
)
327 /* If we don't have to extend and this is a constant, return it. */
328 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
331 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
332 extend since it will be more efficient to do so unless the signedness of
333 a promoted object differs from our extension. */
335 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
336 && SUBREG_PROMOTED_UNSIGNED_P (op
) == unsignedp
))
337 return convert_modes (mode
, oldmode
, op
, unsignedp
);
339 /* If MODE is no wider than a single word, we return a paradoxical
341 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
342 return gen_rtx_SUBREG (mode
, force_reg (GET_MODE (op
), op
), 0);
344 /* Otherwise, get an object of MODE, clobber it, and set the low-order
347 result
= gen_reg_rtx (mode
);
348 emit_clobber (result
);
349 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
353 /* Return the optab used for computing the operation given by the tree code,
354 CODE and the tree EXP. This function is not always usable (for example, it
355 cannot give complete results for multiplication or division) but probably
356 ought to be relied on more widely throughout the expander. */
358 optab_for_tree_code (enum tree_code code
, const_tree type
,
359 enum optab_subtype subtype
)
371 return one_cmpl_optab
;
376 case MULT_HIGHPART_EXPR
:
377 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
383 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
391 if (TYPE_SATURATING(type
))
392 return TYPE_UNSIGNED(type
) ? usdiv_optab
: ssdiv_optab
;
393 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
396 if (TREE_CODE (type
) == VECTOR_TYPE
)
398 if (subtype
== optab_vector
)
399 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
401 gcc_assert (subtype
== optab_scalar
);
403 if (TYPE_SATURATING(type
))
404 return TYPE_UNSIGNED(type
) ? usashl_optab
: ssashl_optab
;
408 if (TREE_CODE (type
) == VECTOR_TYPE
)
410 if (subtype
== optab_vector
)
411 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
413 gcc_assert (subtype
== optab_scalar
);
415 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
418 if (TREE_CODE (type
) == VECTOR_TYPE
)
420 if (subtype
== optab_vector
)
423 gcc_assert (subtype
== optab_scalar
);
428 if (TREE_CODE (type
) == VECTOR_TYPE
)
430 if (subtype
== optab_vector
)
433 gcc_assert (subtype
== optab_scalar
);
438 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
441 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
443 case REALIGN_LOAD_EXPR
:
444 return vec_realign_load_optab
;
447 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
450 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
452 case WIDEN_MULT_PLUS_EXPR
:
453 return (TYPE_UNSIGNED (type
)
454 ? (TYPE_SATURATING (type
)
455 ? usmadd_widen_optab
: umadd_widen_optab
)
456 : (TYPE_SATURATING (type
)
457 ? ssmadd_widen_optab
: smadd_widen_optab
));
459 case WIDEN_MULT_MINUS_EXPR
:
460 return (TYPE_UNSIGNED (type
)
461 ? (TYPE_SATURATING (type
)
462 ? usmsub_widen_optab
: umsub_widen_optab
)
463 : (TYPE_SATURATING (type
)
464 ? ssmsub_widen_optab
: smsub_widen_optab
));
470 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
473 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
475 case REDUC_PLUS_EXPR
:
476 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
478 case VEC_LSHIFT_EXPR
:
479 return vec_shl_optab
;
481 case VEC_RSHIFT_EXPR
:
482 return vec_shr_optab
;
484 case VEC_WIDEN_MULT_HI_EXPR
:
485 return TYPE_UNSIGNED (type
) ?
486 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
488 case VEC_WIDEN_MULT_LO_EXPR
:
489 return TYPE_UNSIGNED (type
) ?
490 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
492 case VEC_WIDEN_MULT_EVEN_EXPR
:
493 return TYPE_UNSIGNED (type
) ?
494 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
496 case VEC_WIDEN_MULT_ODD_EXPR
:
497 return TYPE_UNSIGNED (type
) ?
498 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
500 case VEC_WIDEN_LSHIFT_HI_EXPR
:
501 return TYPE_UNSIGNED (type
) ?
502 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
504 case VEC_WIDEN_LSHIFT_LO_EXPR
:
505 return TYPE_UNSIGNED (type
) ?
506 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
508 case VEC_UNPACK_HI_EXPR
:
509 return TYPE_UNSIGNED (type
) ?
510 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
512 case VEC_UNPACK_LO_EXPR
:
513 return TYPE_UNSIGNED (type
) ?
514 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
516 case VEC_UNPACK_FLOAT_HI_EXPR
:
517 /* The signedness is determined from input operand. */
518 return TYPE_UNSIGNED (type
) ?
519 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
521 case VEC_UNPACK_FLOAT_LO_EXPR
:
522 /* The signedness is determined from input operand. */
523 return TYPE_UNSIGNED (type
) ?
524 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
526 case VEC_PACK_TRUNC_EXPR
:
527 return vec_pack_trunc_optab
;
529 case VEC_PACK_SAT_EXPR
:
530 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
532 case VEC_PACK_FIX_TRUNC_EXPR
:
533 /* The signedness is determined from output operand. */
534 return TYPE_UNSIGNED (type
) ?
535 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
541 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
544 case POINTER_PLUS_EXPR
:
546 if (TYPE_SATURATING(type
))
547 return TYPE_UNSIGNED(type
) ? usadd_optab
: ssadd_optab
;
548 return trapv
? addv_optab
: add_optab
;
551 if (TYPE_SATURATING(type
))
552 return TYPE_UNSIGNED(type
) ? ussub_optab
: sssub_optab
;
553 return trapv
? subv_optab
: sub_optab
;
556 if (TYPE_SATURATING(type
))
557 return TYPE_UNSIGNED(type
) ? usmul_optab
: ssmul_optab
;
558 return trapv
? smulv_optab
: smul_optab
;
561 if (TYPE_SATURATING(type
))
562 return TYPE_UNSIGNED(type
) ? usneg_optab
: ssneg_optab
;
563 return trapv
? negv_optab
: neg_optab
;
566 return trapv
? absv_optab
: abs_optab
;
569 return unknown_optab
;
574 /* Expand vector widening operations.
576 There are two different classes of operations handled here:
577 1) Operations whose result is wider than all the arguments to the operation.
578 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
579 In this case OP0 and optionally OP1 would be initialized,
580 but WIDE_OP wouldn't (not relevant for this case).
581 2) Operations whose result is of the same size as the last argument to the
582 operation, but wider than all the other arguments to the operation.
583 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
584 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
586 E.g, when called to expand the following operations, this is how
587 the arguments will be initialized:
589 widening-sum 2 oprnd0 - oprnd1
590 widening-dot-product 3 oprnd0 oprnd1 oprnd2
591 widening-mult 2 oprnd0 oprnd1 -
592 type-promotion (vec-unpack) 1 oprnd0 - - */
595 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
596 rtx target
, int unsignedp
)
598 struct expand_operand eops
[4];
599 tree oprnd0
, oprnd1
, oprnd2
;
600 enum machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
601 optab widen_pattern_optab
;
602 enum insn_code icode
;
603 int nops
= TREE_CODE_LENGTH (ops
->code
);
607 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
608 widen_pattern_optab
=
609 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
610 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
611 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
612 icode
= find_widening_optab_handler (widen_pattern_optab
,
613 TYPE_MODE (TREE_TYPE (ops
->op2
)),
616 icode
= optab_handler (widen_pattern_optab
, tmode0
);
617 gcc_assert (icode
!= CODE_FOR_nothing
);
622 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
625 /* The last operand is of a wider mode than the rest of the operands. */
630 gcc_assert (tmode1
== tmode0
);
633 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
637 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
638 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
640 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
642 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
643 expand_insn (icode
, op
, eops
);
644 return eops
[0].value
;
647 /* Generate code to perform an operation specified by TERNARY_OPTAB
648 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
650 UNSIGNEDP is for the case where we have to widen the operands
651 to perform the operation. It says to use zero-extension.
653 If TARGET is nonzero, the value
654 is generated there, if it is convenient to do so.
655 In all cases an rtx is returned for the locus of the value;
656 this may or may not be TARGET. */
659 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
660 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
662 struct expand_operand ops
[4];
663 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
665 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
667 create_output_operand (&ops
[0], target
, mode
);
668 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
669 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
670 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
671 expand_insn (icode
, 4, ops
);
676 /* Like expand_binop, but return a constant rtx if the result can be
677 calculated at compile time. The arguments and return value are
678 otherwise the same as for expand_binop. */
681 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
682 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
683 enum optab_methods methods
)
685 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
687 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
693 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
696 /* Like simplify_expand_binop, but always put the result in TARGET.
697 Return true if the expansion succeeded. */
700 force_expand_binop (enum machine_mode mode
, optab binoptab
,
701 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
702 enum optab_methods methods
)
704 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
705 target
, unsignedp
, methods
);
709 emit_move_insn (target
, x
);
713 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
716 expand_vec_shift_expr (sepops ops
, rtx target
)
718 struct expand_operand eops
[3];
719 enum insn_code icode
;
720 rtx rtx_op1
, rtx_op2
;
721 enum machine_mode mode
= TYPE_MODE (ops
->type
);
722 tree vec_oprnd
= ops
->op0
;
723 tree shift_oprnd
= ops
->op1
;
728 case VEC_RSHIFT_EXPR
:
729 shift_optab
= vec_shr_optab
;
731 case VEC_LSHIFT_EXPR
:
732 shift_optab
= vec_shl_optab
;
738 icode
= optab_handler (shift_optab
, mode
);
739 gcc_assert (icode
!= CODE_FOR_nothing
);
741 rtx_op1
= expand_normal (vec_oprnd
);
742 rtx_op2
= expand_normal (shift_oprnd
);
744 create_output_operand (&eops
[0], target
, mode
);
745 create_input_operand (&eops
[1], rtx_op1
, GET_MODE (rtx_op1
));
746 create_convert_operand_from_type (&eops
[2], rtx_op2
, TREE_TYPE (shift_oprnd
));
747 expand_insn (icode
, 3, eops
);
749 return eops
[0].value
;
752 /* Create a new vector value in VMODE with all elements set to OP. The
753 mode of OP must be the element mode of VMODE. If OP is a constant,
754 then the return value will be a constant. */
757 expand_vector_broadcast (enum machine_mode vmode
, rtx op
)
759 enum insn_code icode
;
764 gcc_checking_assert (VECTOR_MODE_P (vmode
));
766 n
= GET_MODE_NUNITS (vmode
);
767 vec
= rtvec_alloc (n
);
768 for (i
= 0; i
< n
; ++i
)
769 RTVEC_ELT (vec
, i
) = op
;
772 return gen_rtx_CONST_VECTOR (vmode
, vec
);
774 /* ??? If the target doesn't have a vec_init, then we have no easy way
775 of performing this operation. Most of this sort of generic support
776 is hidden away in the vector lowering support in gimple. */
777 icode
= optab_handler (vec_init_optab
, vmode
);
778 if (icode
== CODE_FOR_nothing
)
781 ret
= gen_reg_rtx (vmode
);
782 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
787 /* This subroutine of expand_doubleword_shift handles the cases in which
788 the effective shift value is >= BITS_PER_WORD. The arguments and return
789 value are the same as for the parent routine, except that SUPERWORD_OP1
790 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
791 INTO_TARGET may be null if the caller has decided to calculate it. */
794 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
795 rtx outof_target
, rtx into_target
,
796 int unsignedp
, enum optab_methods methods
)
798 if (into_target
!= 0)
799 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
800 into_target
, unsignedp
, methods
))
803 if (outof_target
!= 0)
805 /* For a signed right shift, we must fill OUTOF_TARGET with copies
806 of the sign bit, otherwise we must fill it with zeros. */
807 if (binoptab
!= ashr_optab
)
808 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
810 if (!force_expand_binop (word_mode
, binoptab
,
811 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
812 outof_target
, unsignedp
, methods
))
818 /* This subroutine of expand_doubleword_shift handles the cases in which
819 the effective shift value is < BITS_PER_WORD. The arguments and return
820 value are the same as for the parent routine. */
823 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
824 rtx outof_input
, rtx into_input
, rtx op1
,
825 rtx outof_target
, rtx into_target
,
826 int unsignedp
, enum optab_methods methods
,
827 unsigned HOST_WIDE_INT shift_mask
)
829 optab reverse_unsigned_shift
, unsigned_shift
;
832 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
833 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
835 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
836 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
837 the opposite direction to BINOPTAB. */
838 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
840 carries
= outof_input
;
841 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
842 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
847 /* We must avoid shifting by BITS_PER_WORD bits since that is either
848 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
849 has unknown behavior. Do a single shift first, then shift by the
850 remainder. It's OK to use ~OP1 as the remainder if shift counts
851 are truncated to the mode size. */
852 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
853 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
854 if (shift_mask
== BITS_PER_WORD
- 1)
856 tmp
= immed_double_const (-1, -1, op1_mode
);
857 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
862 tmp
= immed_double_const (BITS_PER_WORD
- 1, 0, op1_mode
);
863 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
867 if (tmp
== 0 || carries
== 0)
869 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
870 carries
, tmp
, 0, unsignedp
, methods
);
874 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
875 so the result can go directly into INTO_TARGET if convenient. */
876 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
877 into_target
, unsignedp
, methods
);
881 /* Now OR in the bits carried over from OUTOF_INPUT. */
882 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
883 into_target
, unsignedp
, methods
))
886 /* Use a standard word_mode shift for the out-of half. */
887 if (outof_target
!= 0)
888 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
889 outof_target
, unsignedp
, methods
))
896 #ifdef HAVE_conditional_move
897 /* Try implementing expand_doubleword_shift using conditional moves.
898 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
899 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
900 are the shift counts to use in the former and latter case. All other
901 arguments are the same as the parent routine. */
904 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
905 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
906 rtx outof_input
, rtx into_input
,
907 rtx subword_op1
, rtx superword_op1
,
908 rtx outof_target
, rtx into_target
,
909 int unsignedp
, enum optab_methods methods
,
910 unsigned HOST_WIDE_INT shift_mask
)
912 rtx outof_superword
, into_superword
;
914 /* Put the superword version of the output into OUTOF_SUPERWORD and
916 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
917 if (outof_target
!= 0 && subword_op1
== superword_op1
)
919 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
920 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
921 into_superword
= outof_target
;
922 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
923 outof_superword
, 0, unsignedp
, methods
))
928 into_superword
= gen_reg_rtx (word_mode
);
929 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
930 outof_superword
, into_superword
,
935 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
936 if (!expand_subword_shift (op1_mode
, binoptab
,
937 outof_input
, into_input
, subword_op1
,
938 outof_target
, into_target
,
939 unsignedp
, methods
, shift_mask
))
942 /* Select between them. Do the INTO half first because INTO_SUPERWORD
943 might be the current value of OUTOF_TARGET. */
944 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
945 into_target
, into_superword
, word_mode
, false))
948 if (outof_target
!= 0)
949 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
950 outof_target
, outof_superword
,
958 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
959 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
960 input operand; the shift moves bits in the direction OUTOF_INPUT->
961 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
962 of the target. OP1 is the shift count and OP1_MODE is its mode.
963 If OP1 is constant, it will have been truncated as appropriate
964 and is known to be nonzero.
966 If SHIFT_MASK is zero, the result of word shifts is undefined when the
967 shift count is outside the range [0, BITS_PER_WORD). This routine must
968 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
970 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
971 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
972 fill with zeros or sign bits as appropriate.
974 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
975 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
976 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
977 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
980 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
981 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
982 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
983 function wants to calculate it itself.
985 Return true if the shift could be successfully synthesized. */
988 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
989 rtx outof_input
, rtx into_input
, rtx op1
,
990 rtx outof_target
, rtx into_target
,
991 int unsignedp
, enum optab_methods methods
,
992 unsigned HOST_WIDE_INT shift_mask
)
994 rtx superword_op1
, tmp
, cmp1
, cmp2
;
995 rtx subword_label
, done_label
;
996 enum rtx_code cmp_code
;
998 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
999 fill the result with sign or zero bits as appropriate. If so, the value
1000 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1001 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1002 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1004 This isn't worthwhile for constant shifts since the optimizers will
1005 cope better with in-range shift counts. */
1006 if (shift_mask
>= BITS_PER_WORD
1007 && outof_target
!= 0
1008 && !CONSTANT_P (op1
))
1010 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1011 outof_input
, into_input
, op1
,
1013 unsignedp
, methods
, shift_mask
))
1015 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1016 outof_target
, unsignedp
, methods
))
1021 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1022 is true when the effective shift value is less than BITS_PER_WORD.
1023 Set SUPERWORD_OP1 to the shift count that should be used to shift
1024 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1025 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
1026 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1028 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1029 is a subword shift count. */
1030 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1032 cmp2
= CONST0_RTX (op1_mode
);
1034 superword_op1
= op1
;
1038 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1039 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1041 cmp2
= CONST0_RTX (op1_mode
);
1043 superword_op1
= cmp1
;
1048 /* If we can compute the condition at compile time, pick the
1049 appropriate subroutine. */
1050 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1051 if (tmp
!= 0 && CONST_INT_P (tmp
))
1053 if (tmp
== const0_rtx
)
1054 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1055 outof_target
, into_target
,
1056 unsignedp
, methods
);
1058 return expand_subword_shift (op1_mode
, binoptab
,
1059 outof_input
, into_input
, op1
,
1060 outof_target
, into_target
,
1061 unsignedp
, methods
, shift_mask
);
1064 #ifdef HAVE_conditional_move
1065 /* Try using conditional moves to generate straight-line code. */
1067 rtx start
= get_last_insn ();
1068 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1069 cmp_code
, cmp1
, cmp2
,
1070 outof_input
, into_input
,
1072 outof_target
, into_target
,
1073 unsignedp
, methods
, shift_mask
))
1075 delete_insns_since (start
);
1079 /* As a last resort, use branches to select the correct alternative. */
1080 subword_label
= gen_label_rtx ();
1081 done_label
= gen_label_rtx ();
1084 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1085 0, 0, subword_label
, -1);
1088 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1089 outof_target
, into_target
,
1090 unsignedp
, methods
))
1093 emit_jump_insn (gen_jump (done_label
));
1095 emit_label (subword_label
);
1097 if (!expand_subword_shift (op1_mode
, binoptab
,
1098 outof_input
, into_input
, op1
,
1099 outof_target
, into_target
,
1100 unsignedp
, methods
, shift_mask
))
1103 emit_label (done_label
);
1107 /* Subroutine of expand_binop. Perform a double word multiplication of
1108 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1109 as the target's word_mode. This function return NULL_RTX if anything
1110 goes wrong, in which case it may have already emitted instructions
1111 which need to be deleted.
1113 If we want to multiply two two-word values and have normal and widening
1114 multiplies of single-word values, we can do this with three smaller
1117 The multiplication proceeds as follows:
1118 _______________________
1119 [__op0_high_|__op0_low__]
1120 _______________________
1121 * [__op1_high_|__op1_low__]
1122 _______________________________________________
1123 _______________________
1124 (1) [__op0_low__*__op1_low__]
1125 _______________________
1126 (2a) [__op0_low__*__op1_high_]
1127 _______________________
1128 (2b) [__op0_high_*__op1_low__]
1129 _______________________
1130 (3) [__op0_high_*__op1_high_]
1133 This gives a 4-word result. Since we are only interested in the
1134 lower 2 words, partial result (3) and the upper words of (2a) and
1135 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1136 calculated using non-widening multiplication.
1138 (1), however, needs to be calculated with an unsigned widening
1139 multiplication. If this operation is not directly supported we
1140 try using a signed widening multiplication and adjust the result.
1141 This adjustment works as follows:
1143 If both operands are positive then no adjustment is needed.
1145 If the operands have different signs, for example op0_low < 0 and
1146 op1_low >= 0, the instruction treats the most significant bit of
1147 op0_low as a sign bit instead of a bit with significance
1148 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1149 with 2**BITS_PER_WORD - op0_low, and two's complements the
1150 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1153 Similarly, if both operands are negative, we need to add
1154 (op0_low + op1_low) * 2**BITS_PER_WORD.
1156 We use a trick to adjust quickly. We logically shift op0_low right
1157 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1158 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1159 logical shift exists, we do an arithmetic right shift and subtract
1163 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1164 bool umulp
, enum optab_methods methods
)
1166 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1167 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1168 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1169 rtx product
, adjust
, product_high
, temp
;
1171 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1172 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1173 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1174 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1176 /* If we're using an unsigned multiply to directly compute the product
1177 of the low-order words of the operands and perform any required
1178 adjustments of the operands, we begin by trying two more multiplications
1179 and then computing the appropriate sum.
1181 We have checked above that the required addition is provided.
1182 Full-word addition will normally always succeed, especially if
1183 it is provided at all, so we don't worry about its failure. The
1184 multiplication may well fail, however, so we do handle that. */
1188 /* ??? This could be done with emit_store_flag where available. */
1189 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1190 NULL_RTX
, 1, methods
);
1192 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1193 NULL_RTX
, 0, OPTAB_DIRECT
);
1196 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1197 NULL_RTX
, 0, methods
);
1200 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1201 NULL_RTX
, 0, OPTAB_DIRECT
);
1208 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1209 NULL_RTX
, 0, OPTAB_DIRECT
);
1213 /* OP0_HIGH should now be dead. */
1217 /* ??? This could be done with emit_store_flag where available. */
1218 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1219 NULL_RTX
, 1, methods
);
1221 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1222 NULL_RTX
, 0, OPTAB_DIRECT
);
1225 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1226 NULL_RTX
, 0, methods
);
1229 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1230 NULL_RTX
, 0, OPTAB_DIRECT
);
1237 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1238 NULL_RTX
, 0, OPTAB_DIRECT
);
1242 /* OP1_HIGH should now be dead. */
1244 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1245 NULL_RTX
, 0, OPTAB_DIRECT
);
1247 if (target
&& !REG_P (target
))
1251 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1252 target
, 1, OPTAB_DIRECT
);
1254 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1255 target
, 1, OPTAB_DIRECT
);
1260 product_high
= operand_subword (product
, high
, 1, mode
);
1261 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1262 NULL_RTX
, 0, OPTAB_DIRECT
);
1263 emit_move_insn (product_high
, adjust
);
1267 /* Wrapper around expand_binop which takes an rtx code to specify
1268 the operation to perform, not an optab pointer. All other
1269 arguments are the same. */
1271 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1272 rtx op1
, rtx target
, int unsignedp
,
1273 enum optab_methods methods
)
1275 optab binop
= code_to_optab (code
);
1278 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1281 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1282 binop. Order them according to commutative_operand_precedence and, if
1283 possible, try to put TARGET or a pseudo first. */
1285 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1287 int op0_prec
= commutative_operand_precedence (op0
);
1288 int op1_prec
= commutative_operand_precedence (op1
);
1290 if (op0_prec
< op1_prec
)
1293 if (op0_prec
> op1_prec
)
1296 /* With equal precedence, both orders are ok, but it is better if the
1297 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1298 if (target
== 0 || REG_P (target
))
1299 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1301 return rtx_equal_p (op1
, target
);
1304 /* Return true if BINOPTAB implements a shift operation. */
1307 shift_optab_p (optab binoptab
)
1309 switch (optab_to_code (binoptab
))
1325 /* Return true if BINOPTAB implements a commutative binary operation. */
1328 commutative_optab_p (optab binoptab
)
1330 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1331 || binoptab
== smul_widen_optab
1332 || binoptab
== umul_widen_optab
1333 || binoptab
== smul_highpart_optab
1334 || binoptab
== umul_highpart_optab
);
1337 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1338 optimizing, and if the operand is a constant that costs more than
1339 1 instruction, force the constant into a register and return that
1340 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1343 avoid_expensive_constant (enum machine_mode mode
, optab binoptab
,
1344 int opn
, rtx x
, bool unsignedp
)
1346 bool speed
= optimize_insn_for_speed_p ();
1348 if (mode
!= VOIDmode
1351 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1352 > set_src_cost (x
, speed
)))
1354 if (CONST_INT_P (x
))
1356 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1357 if (intval
!= INTVAL (x
))
1358 x
= GEN_INT (intval
);
1361 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1362 x
= force_reg (mode
, x
);
1367 /* Helper function for expand_binop: handle the case where there
1368 is an insn that directly implements the indicated operation.
1369 Returns null if this is not possible. */
1371 expand_binop_directly (enum machine_mode mode
, optab binoptab
,
1373 rtx target
, int unsignedp
, enum optab_methods methods
,
1376 enum machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1377 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1379 enum machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1380 enum machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1381 enum machine_mode mode0
, mode1
, tmp_mode
;
1382 struct expand_operand ops
[3];
1385 rtx xop0
= op0
, xop1
= op1
;
1388 /* If it is a commutative operator and the modes would match
1389 if we would swap the operands, we can save the conversions. */
1390 commutative_p
= commutative_optab_p (binoptab
);
1392 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1393 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1400 /* If we are optimizing, force expensive constants into a register. */
1401 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1402 if (!shift_optab_p (binoptab
))
1403 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1405 /* In case the insn wants input operands in modes different from
1406 those of the actual operands, convert the operands. It would
1407 seem that we don't need to convert CONST_INTs, but we do, so
1408 that they're properly zero-extended, sign-extended or truncated
1411 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1412 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1414 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1418 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1419 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1421 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1425 /* If operation is commutative,
1426 try to make the first operand a register.
1427 Even better, try to make it the same as the target.
1428 Also try to make the last operand a constant. */
1430 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1437 /* Now, if insn's predicates don't allow our operands, put them into
1440 if (binoptab
== vec_pack_trunc_optab
1441 || binoptab
== vec_pack_usat_optab
1442 || binoptab
== vec_pack_ssat_optab
1443 || binoptab
== vec_pack_ufix_trunc_optab
1444 || binoptab
== vec_pack_sfix_trunc_optab
)
1446 /* The mode of the result is different then the mode of the
1448 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1449 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1451 delete_insns_since (last
);
1458 create_output_operand (&ops
[0], target
, tmp_mode
);
1459 create_input_operand (&ops
[1], xop0
, mode0
);
1460 create_input_operand (&ops
[2], xop1
, mode1
);
1461 pat
= maybe_gen_insn (icode
, 3, ops
);
1464 /* If PAT is composed of more than one insn, try to add an appropriate
1465 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1466 operand, call expand_binop again, this time without a target. */
1467 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1468 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (binoptab
),
1469 ops
[1].value
, ops
[2].value
))
1471 delete_insns_since (last
);
1472 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1473 unsignedp
, methods
);
1477 return ops
[0].value
;
1479 delete_insns_since (last
);
1483 /* Generate code to perform an operation specified by BINOPTAB
1484 on operands OP0 and OP1, with result having machine-mode MODE.
1486 UNSIGNEDP is for the case where we have to widen the operands
1487 to perform the operation. It says to use zero-extension.
1489 If TARGET is nonzero, the value
1490 is generated there, if it is convenient to do so.
1491 In all cases an rtx is returned for the locus of the value;
1492 this may or may not be TARGET. */
1495 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1496 rtx target
, int unsignedp
, enum optab_methods methods
)
1498 enum optab_methods next_methods
1499 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1500 ? OPTAB_WIDEN
: methods
);
1501 enum mode_class mclass
;
1502 enum machine_mode wider_mode
;
1505 rtx entry_last
= get_last_insn ();
1508 mclass
= GET_MODE_CLASS (mode
);
1510 /* If subtracting an integer constant, convert this into an addition of
1511 the negated constant. */
1513 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1515 op1
= negate_rtx (mode
, op1
);
1516 binoptab
= add_optab
;
1519 /* Record where to delete back to if we backtrack. */
1520 last
= get_last_insn ();
1522 /* If we can do it with a three-operand insn, do so. */
1524 if (methods
!= OPTAB_MUST_WIDEN
1525 && find_widening_optab_handler (binoptab
, mode
,
1526 widened_mode (mode
, op0
, op1
), 1)
1527 != CODE_FOR_nothing
)
1529 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1530 unsignedp
, methods
, last
);
1535 /* If we were trying to rotate, and that didn't work, try rotating
1536 the other direction before falling back to shifts and bitwise-or. */
1537 if (((binoptab
== rotl_optab
1538 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1539 || (binoptab
== rotr_optab
1540 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1541 && mclass
== MODE_INT
)
1543 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1545 unsigned int bits
= GET_MODE_PRECISION (mode
);
1547 if (CONST_INT_P (op1
))
1548 newop1
= GEN_INT (bits
- INTVAL (op1
));
1549 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1550 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1552 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1553 GEN_INT (bits
), op1
,
1554 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1556 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1557 target
, unsignedp
, methods
, last
);
1562 /* If this is a multiply, see if we can do a widening operation that
1563 takes operands of this mode and makes a wider mode. */
1565 if (binoptab
== smul_optab
1566 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1567 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1568 : smul_widen_optab
),
1569 GET_MODE_2XWIDER_MODE (mode
), mode
)
1570 != CODE_FOR_nothing
))
1572 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1573 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1574 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1578 if (GET_MODE_CLASS (mode
) == MODE_INT
1579 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1580 return gen_lowpart (mode
, temp
);
1582 return convert_to_mode (mode
, temp
, unsignedp
);
1586 /* If this is a vector shift by a scalar, see if we can do a vector
1587 shift by a vector. If so, broadcast the scalar into a vector. */
1588 if (mclass
== MODE_VECTOR_INT
)
1590 optab otheroptab
= unknown_optab
;
1592 if (binoptab
== ashl_optab
)
1593 otheroptab
= vashl_optab
;
1594 else if (binoptab
== ashr_optab
)
1595 otheroptab
= vashr_optab
;
1596 else if (binoptab
== lshr_optab
)
1597 otheroptab
= vlshr_optab
;
1598 else if (binoptab
== rotl_optab
)
1599 otheroptab
= vrotl_optab
;
1600 else if (binoptab
== rotr_optab
)
1601 otheroptab
= vrotr_optab
;
1603 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1605 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1608 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1609 target
, unsignedp
, methods
, last
);
1616 /* Look for a wider mode of the same class for which we think we
1617 can open-code the operation. Check for a widening multiply at the
1618 wider mode as well. */
1620 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1621 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1622 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1623 wider_mode
!= VOIDmode
;
1624 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1626 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1627 || (binoptab
== smul_optab
1628 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1629 && (find_widening_optab_handler ((unsignedp
1631 : smul_widen_optab
),
1632 GET_MODE_WIDER_MODE (wider_mode
),
1634 != CODE_FOR_nothing
)))
1636 rtx xop0
= op0
, xop1
= op1
;
1639 /* For certain integer operations, we need not actually extend
1640 the narrow operands, as long as we will truncate
1641 the results to the same narrowness. */
1643 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1644 || binoptab
== xor_optab
1645 || binoptab
== add_optab
|| binoptab
== sub_optab
1646 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1647 && mclass
== MODE_INT
)
1650 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1652 if (binoptab
!= ashl_optab
)
1653 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1657 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1659 /* The second operand of a shift must always be extended. */
1660 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1661 no_extend
&& binoptab
!= ashl_optab
);
1663 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1664 unsignedp
, OPTAB_DIRECT
);
1667 if (mclass
!= MODE_INT
1668 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1671 target
= gen_reg_rtx (mode
);
1672 convert_move (target
, temp
, 0);
1676 return gen_lowpart (mode
, temp
);
1679 delete_insns_since (last
);
1683 /* If operation is commutative,
1684 try to make the first operand a register.
1685 Even better, try to make it the same as the target.
1686 Also try to make the last operand a constant. */
1687 if (commutative_optab_p (binoptab
)
1688 && swap_commutative_operands_with_target (target
, op0
, op1
))
1695 /* These can be done a word at a time. */
1696 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1697 && mclass
== MODE_INT
1698 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1699 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1704 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1705 won't be accurate, so use a new target. */
1709 || !valid_multiword_target_p (target
))
1710 target
= gen_reg_rtx (mode
);
1714 /* Do the actual arithmetic. */
1715 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1717 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1718 rtx x
= expand_binop (word_mode
, binoptab
,
1719 operand_subword_force (op0
, i
, mode
),
1720 operand_subword_force (op1
, i
, mode
),
1721 target_piece
, unsignedp
, next_methods
);
1726 if (target_piece
!= x
)
1727 emit_move_insn (target_piece
, x
);
1730 insns
= get_insns ();
1733 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1740 /* Synthesize double word shifts from single word shifts. */
1741 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1742 || binoptab
== ashr_optab
)
1743 && mclass
== MODE_INT
1744 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1745 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1746 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1747 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1748 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1749 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1751 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1752 enum machine_mode op1_mode
;
1754 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1755 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1756 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1758 /* Apply the truncation to constant shifts. */
1759 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1760 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1762 if (op1
== CONST0_RTX (op1_mode
))
1765 /* Make sure that this is a combination that expand_doubleword_shift
1766 can handle. See the comments there for details. */
1767 if (double_shift_mask
== 0
1768 || (shift_mask
== BITS_PER_WORD
- 1
1769 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1772 rtx into_target
, outof_target
;
1773 rtx into_input
, outof_input
;
1774 int left_shift
, outof_word
;
1776 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1777 won't be accurate, so use a new target. */
1781 || !valid_multiword_target_p (target
))
1782 target
= gen_reg_rtx (mode
);
1786 /* OUTOF_* is the word we are shifting bits away from, and
1787 INTO_* is the word that we are shifting bits towards, thus
1788 they differ depending on the direction of the shift and
1789 WORDS_BIG_ENDIAN. */
1791 left_shift
= binoptab
== ashl_optab
;
1792 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1794 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1795 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1797 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1798 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1800 if (expand_doubleword_shift (op1_mode
, binoptab
,
1801 outof_input
, into_input
, op1
,
1802 outof_target
, into_target
,
1803 unsignedp
, next_methods
, shift_mask
))
1805 insns
= get_insns ();
1815 /* Synthesize double word rotates from single word shifts. */
1816 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1817 && mclass
== MODE_INT
1818 && CONST_INT_P (op1
)
1819 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1820 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1821 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1824 rtx into_target
, outof_target
;
1825 rtx into_input
, outof_input
;
1827 int shift_count
, left_shift
, outof_word
;
1829 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1830 won't be accurate, so use a new target. Do this also if target is not
1831 a REG, first because having a register instead may open optimization
1832 opportunities, and second because if target and op0 happen to be MEMs
1833 designating the same location, we would risk clobbering it too early
1834 in the code sequence we generate below. */
1839 || !valid_multiword_target_p (target
))
1840 target
= gen_reg_rtx (mode
);
1844 shift_count
= INTVAL (op1
);
1846 /* OUTOF_* is the word we are shifting bits away from, and
1847 INTO_* is the word that we are shifting bits towards, thus
1848 they differ depending on the direction of the shift and
1849 WORDS_BIG_ENDIAN. */
1851 left_shift
= (binoptab
== rotl_optab
);
1852 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1854 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1855 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1857 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1858 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1860 if (shift_count
== BITS_PER_WORD
)
1862 /* This is just a word swap. */
1863 emit_move_insn (outof_target
, into_input
);
1864 emit_move_insn (into_target
, outof_input
);
1869 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1870 rtx first_shift_count
, second_shift_count
;
1871 optab reverse_unsigned_shift
, unsigned_shift
;
1873 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1874 ? lshr_optab
: ashl_optab
);
1876 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1877 ? ashl_optab
: lshr_optab
);
1879 if (shift_count
> BITS_PER_WORD
)
1881 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1882 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1886 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1887 second_shift_count
= GEN_INT (shift_count
);
1890 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1891 outof_input
, first_shift_count
,
1892 NULL_RTX
, unsignedp
, next_methods
);
1893 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1894 into_input
, second_shift_count
,
1895 NULL_RTX
, unsignedp
, next_methods
);
1897 if (into_temp1
!= 0 && into_temp2
!= 0)
1898 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1899 into_target
, unsignedp
, next_methods
);
1903 if (inter
!= 0 && inter
!= into_target
)
1904 emit_move_insn (into_target
, inter
);
1906 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1907 into_input
, first_shift_count
,
1908 NULL_RTX
, unsignedp
, next_methods
);
1909 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1910 outof_input
, second_shift_count
,
1911 NULL_RTX
, unsignedp
, next_methods
);
1913 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1914 inter
= expand_binop (word_mode
, ior_optab
,
1915 outof_temp1
, outof_temp2
,
1916 outof_target
, unsignedp
, next_methods
);
1918 if (inter
!= 0 && inter
!= outof_target
)
1919 emit_move_insn (outof_target
, inter
);
1922 insns
= get_insns ();
1932 /* These can be done a word at a time by propagating carries. */
1933 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1934 && mclass
== MODE_INT
1935 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1936 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1939 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1940 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1941 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1942 rtx xop0
, xop1
, xtarget
;
1944 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1945 value is one of those, use it. Otherwise, use 1 since it is the
1946 one easiest to get. */
1947 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1948 int normalizep
= STORE_FLAG_VALUE
;
1953 /* Prepare the operands. */
1954 xop0
= force_reg (mode
, op0
);
1955 xop1
= force_reg (mode
, op1
);
1957 xtarget
= gen_reg_rtx (mode
);
1959 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1962 /* Indicate for flow that the entire target reg is being set. */
1964 emit_clobber (xtarget
);
1966 /* Do the actual arithmetic. */
1967 for (i
= 0; i
< nwords
; i
++)
1969 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1970 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1971 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1972 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1975 /* Main add/subtract of the input operands. */
1976 x
= expand_binop (word_mode
, binoptab
,
1977 op0_piece
, op1_piece
,
1978 target_piece
, unsignedp
, next_methods
);
1984 /* Store carry from main add/subtract. */
1985 carry_out
= gen_reg_rtx (word_mode
);
1986 carry_out
= emit_store_flag_force (carry_out
,
1987 (binoptab
== add_optab
1990 word_mode
, 1, normalizep
);
1997 /* Add/subtract previous carry to main result. */
1998 newx
= expand_binop (word_mode
,
1999 normalizep
== 1 ? binoptab
: otheroptab
,
2001 NULL_RTX
, 1, next_methods
);
2005 /* Get out carry from adding/subtracting carry in. */
2006 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2007 carry_tmp
= emit_store_flag_force (carry_tmp
,
2008 (binoptab
== add_optab
2011 word_mode
, 1, normalizep
);
2013 /* Logical-ior the two poss. carry together. */
2014 carry_out
= expand_binop (word_mode
, ior_optab
,
2015 carry_out
, carry_tmp
,
2016 carry_out
, 0, next_methods
);
2020 emit_move_insn (target_piece
, newx
);
2024 if (x
!= target_piece
)
2025 emit_move_insn (target_piece
, x
);
2028 carry_in
= carry_out
;
2031 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2033 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2034 || ! rtx_equal_p (target
, xtarget
))
2036 rtx temp
= emit_move_insn (target
, xtarget
);
2038 set_dst_reg_note (temp
, REG_EQUAL
,
2039 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2040 mode
, copy_rtx (xop0
),
2051 delete_insns_since (last
);
2054 /* Attempt to synthesize double word multiplies using a sequence of word
2055 mode multiplications. We first attempt to generate a sequence using a
2056 more efficient unsigned widening multiply, and if that fails we then
2057 try using a signed widening multiply. */
2059 if (binoptab
== smul_optab
2060 && mclass
== MODE_INT
2061 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2062 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2063 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2065 rtx product
= NULL_RTX
;
2066 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2067 != CODE_FOR_nothing
)
2069 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2072 delete_insns_since (last
);
2075 if (product
== NULL_RTX
2076 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2077 != CODE_FOR_nothing
)
2079 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2082 delete_insns_since (last
);
2085 if (product
!= NULL_RTX
)
2087 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2089 temp
= emit_move_insn (target
? target
: product
, product
);
2090 set_dst_reg_note (temp
,
2092 gen_rtx_fmt_ee (MULT
, mode
,
2095 target
? target
: product
);
2101 /* It can't be open-coded in this mode.
2102 Use a library call if one is available and caller says that's ok. */
2104 libfunc
= optab_libfunc (binoptab
, mode
);
2106 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2110 enum machine_mode op1_mode
= mode
;
2115 if (shift_optab_p (binoptab
))
2117 op1_mode
= targetm
.libgcc_shift_count_mode ();
2118 /* Specify unsigned here,
2119 since negative shift counts are meaningless. */
2120 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2123 if (GET_MODE (op0
) != VOIDmode
2124 && GET_MODE (op0
) != mode
)
2125 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2127 /* Pass 1 for NO_QUEUE so we don't lose any increments
2128 if the libcall is cse'd or moved. */
2129 value
= emit_library_call_value (libfunc
,
2130 NULL_RTX
, LCT_CONST
, mode
, 2,
2131 op0
, mode
, op1x
, op1_mode
);
2133 insns
= get_insns ();
2136 target
= gen_reg_rtx (mode
);
2137 emit_libcall_block_1 (insns
, target
, value
,
2138 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2140 trapv_binoptab_p (binoptab
));
2145 delete_insns_since (last
);
2147 /* It can't be done in this mode. Can we do it in a wider mode? */
2149 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2150 || methods
== OPTAB_MUST_WIDEN
))
2152 /* Caller says, don't even try. */
2153 delete_insns_since (entry_last
);
2157 /* Compute the value of METHODS to pass to recursive calls.
2158 Don't allow widening to be tried recursively. */
2160 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2162 /* Look for a wider mode of the same class for which it appears we can do
2165 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2167 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2168 wider_mode
!= VOIDmode
;
2169 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2171 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2173 || (methods
== OPTAB_LIB
2174 && optab_libfunc (binoptab
, wider_mode
)))
2176 rtx xop0
= op0
, xop1
= op1
;
2179 /* For certain integer operations, we need not actually extend
2180 the narrow operands, as long as we will truncate
2181 the results to the same narrowness. */
2183 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2184 || binoptab
== xor_optab
2185 || binoptab
== add_optab
|| binoptab
== sub_optab
2186 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2187 && mclass
== MODE_INT
)
2190 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2191 unsignedp
, no_extend
);
2193 /* The second operand of a shift must always be extended. */
2194 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2195 no_extend
&& binoptab
!= ashl_optab
);
2197 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2198 unsignedp
, methods
);
2201 if (mclass
!= MODE_INT
2202 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2205 target
= gen_reg_rtx (mode
);
2206 convert_move (target
, temp
, 0);
2210 return gen_lowpart (mode
, temp
);
2213 delete_insns_since (last
);
2218 delete_insns_since (entry_last
);
2222 /* Expand a binary operator which has both signed and unsigned forms.
2223 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2226 If we widen unsigned operands, we may use a signed wider operation instead
2227 of an unsigned wider operation, since the result would be the same. */
2230 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2231 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2232 enum optab_methods methods
)
2235 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2238 /* Do it without widening, if possible. */
2239 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2240 unsignedp
, OPTAB_DIRECT
);
2241 if (temp
|| methods
== OPTAB_DIRECT
)
2244 /* Try widening to a signed int. Disable any direct use of any
2245 signed insn in the current mode. */
2246 save_enable
= swap_optab_enable (soptab
, mode
, false);
2248 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2249 unsignedp
, OPTAB_WIDEN
);
2251 /* For unsigned operands, try widening to an unsigned int. */
2252 if (!temp
&& unsignedp
)
2253 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2254 unsignedp
, OPTAB_WIDEN
);
2255 if (temp
|| methods
== OPTAB_WIDEN
)
2258 /* Use the right width libcall if that exists. */
2259 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2260 unsignedp
, OPTAB_LIB
);
2261 if (temp
|| methods
== OPTAB_LIB
)
2264 /* Must widen and use a libcall, use either signed or unsigned. */
2265 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2266 unsignedp
, methods
);
2267 if (!temp
&& unsignedp
)
2268 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2269 unsignedp
, methods
);
2272 /* Undo the fiddling above. */
2274 swap_optab_enable (soptab
, mode
, true);
2278 /* Generate code to perform an operation specified by UNOPPTAB
2279 on operand OP0, with two results to TARG0 and TARG1.
2280 We assume that the order of the operands for the instruction
2281 is TARG0, TARG1, OP0.
2283 Either TARG0 or TARG1 may be zero, but what that means is that
2284 the result is not actually wanted. We will generate it into
2285 a dummy pseudo-reg and discard it. They may not both be zero.
2287 Returns 1 if this operation can be performed; 0 if not. */
2290 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2293 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2294 enum mode_class mclass
;
2295 enum machine_mode wider_mode
;
2296 rtx entry_last
= get_last_insn ();
2299 mclass
= GET_MODE_CLASS (mode
);
2302 targ0
= gen_reg_rtx (mode
);
2304 targ1
= gen_reg_rtx (mode
);
2306 /* Record where to go back to if we fail. */
2307 last
= get_last_insn ();
2309 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2311 struct expand_operand ops
[3];
2312 enum insn_code icode
= optab_handler (unoptab
, mode
);
2314 create_fixed_operand (&ops
[0], targ0
);
2315 create_fixed_operand (&ops
[1], targ1
);
2316 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2317 if (maybe_expand_insn (icode
, 3, ops
))
2321 /* It can't be done in this mode. Can we do it in a wider mode? */
2323 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2325 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2326 wider_mode
!= VOIDmode
;
2327 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2329 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2331 rtx t0
= gen_reg_rtx (wider_mode
);
2332 rtx t1
= gen_reg_rtx (wider_mode
);
2333 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2335 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2337 convert_move (targ0
, t0
, unsignedp
);
2338 convert_move (targ1
, t1
, unsignedp
);
2342 delete_insns_since (last
);
2347 delete_insns_since (entry_last
);
2351 /* Generate code to perform an operation specified by BINOPTAB
2352 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2353 We assume that the order of the operands for the instruction
2354 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2355 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2357 Either TARG0 or TARG1 may be zero, but what that means is that
2358 the result is not actually wanted. We will generate it into
2359 a dummy pseudo-reg and discard it. They may not both be zero.
2361 Returns 1 if this operation can be performed; 0 if not. */
2364 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2367 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2368 enum mode_class mclass
;
2369 enum machine_mode wider_mode
;
2370 rtx entry_last
= get_last_insn ();
2373 mclass
= GET_MODE_CLASS (mode
);
2376 targ0
= gen_reg_rtx (mode
);
2378 targ1
= gen_reg_rtx (mode
);
2380 /* Record where to go back to if we fail. */
2381 last
= get_last_insn ();
2383 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2385 struct expand_operand ops
[4];
2386 enum insn_code icode
= optab_handler (binoptab
, mode
);
2387 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2388 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2389 rtx xop0
= op0
, xop1
= op1
;
2391 /* If we are optimizing, force expensive constants into a register. */
2392 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2393 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2395 create_fixed_operand (&ops
[0], targ0
);
2396 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2397 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2398 create_fixed_operand (&ops
[3], targ1
);
2399 if (maybe_expand_insn (icode
, 4, ops
))
2401 delete_insns_since (last
);
2404 /* It can't be done in this mode. Can we do it in a wider mode? */
2406 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2408 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2409 wider_mode
!= VOIDmode
;
2410 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2412 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2414 rtx t0
= gen_reg_rtx (wider_mode
);
2415 rtx t1
= gen_reg_rtx (wider_mode
);
2416 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2417 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2419 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2422 convert_move (targ0
, t0
, unsignedp
);
2423 convert_move (targ1
, t1
, unsignedp
);
2427 delete_insns_since (last
);
2432 delete_insns_since (entry_last
);
2436 /* Expand the two-valued library call indicated by BINOPTAB, but
2437 preserve only one of the values. If TARG0 is non-NULL, the first
2438 value is placed into TARG0; otherwise the second value is placed
2439 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2440 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2441 This routine assumes that the value returned by the library call is
2442 as if the return value was of an integral mode twice as wide as the
2443 mode of OP0. Returns 1 if the call was successful. */
2446 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2447 rtx targ0
, rtx targ1
, enum rtx_code code
)
2449 enum machine_mode mode
;
2450 enum machine_mode libval_mode
;
2455 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2456 gcc_assert (!targ0
!= !targ1
);
2458 mode
= GET_MODE (op0
);
2459 libfunc
= optab_libfunc (binoptab
, mode
);
2463 /* The value returned by the library function will have twice as
2464 many bits as the nominal MODE. */
2465 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2468 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2472 /* Get the part of VAL containing the value that we want. */
2473 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2474 targ0
? 0 : GET_MODE_SIZE (mode
));
2475 insns
= get_insns ();
2477 /* Move the into the desired location. */
2478 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2479 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2485 /* Wrapper around expand_unop which takes an rtx code to specify
2486 the operation to perform, not an optab pointer. All other
2487 arguments are the same. */
2489 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2490 rtx target
, int unsignedp
)
2492 optab unop
= code_to_optab (code
);
2495 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2501 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2503 A similar operation can be used for clrsb. UNOPTAB says which operation
2504 we are trying to expand. */
2506 widen_leading (enum machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2508 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2509 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2511 enum machine_mode wider_mode
;
2512 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2513 wider_mode
!= VOIDmode
;
2514 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2516 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2518 rtx xop0
, temp
, last
;
2520 last
= get_last_insn ();
2523 target
= gen_reg_rtx (mode
);
2524 xop0
= widen_operand (op0
, wider_mode
, mode
,
2525 unoptab
!= clrsb_optab
, false);
2526 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2527 unoptab
!= clrsb_optab
);
2529 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2530 GEN_INT (GET_MODE_PRECISION (wider_mode
)
2531 - GET_MODE_PRECISION (mode
)),
2532 target
, true, OPTAB_DIRECT
);
2534 delete_insns_since (last
);
2543 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2544 quantities, choosing which based on whether the high word is nonzero. */
2546 expand_doubleword_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2548 rtx xop0
= force_reg (mode
, op0
);
2549 rtx subhi
= gen_highpart (word_mode
, xop0
);
2550 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2551 rtx hi0_label
= gen_label_rtx ();
2552 rtx after_label
= gen_label_rtx ();
2553 rtx seq
, temp
, result
;
2555 /* If we were not given a target, use a word_mode register, not a
2556 'mode' register. The result will fit, and nobody is expecting
2557 anything bigger (the return type of __builtin_clz* is int). */
2559 target
= gen_reg_rtx (word_mode
);
2561 /* In any case, write to a word_mode scratch in both branches of the
2562 conditional, so we can ensure there is a single move insn setting
2563 'target' to tag a REG_EQUAL note on. */
2564 result
= gen_reg_rtx (word_mode
);
2568 /* If the high word is not equal to zero,
2569 then clz of the full value is clz of the high word. */
2570 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2571 word_mode
, true, hi0_label
);
2573 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2578 convert_move (result
, temp
, true);
2580 emit_jump_insn (gen_jump (after_label
));
2583 /* Else clz of the full value is clz of the low word plus the number
2584 of bits in the high word. */
2585 emit_label (hi0_label
);
2587 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2590 temp
= expand_binop (word_mode
, add_optab
, temp
,
2591 GEN_INT (GET_MODE_BITSIZE (word_mode
)),
2592 result
, true, OPTAB_DIRECT
);
2596 convert_move (result
, temp
, true);
2598 emit_label (after_label
);
2599 convert_move (target
, result
, true);
2604 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2616 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2618 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2620 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2621 enum machine_mode wider_mode
;
2624 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2627 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2628 wider_mode
!= VOIDmode
;
2629 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2630 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2635 last
= get_last_insn ();
2637 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2638 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2640 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2641 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2643 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2644 GET_MODE_BITSIZE (wider_mode
)
2645 - GET_MODE_BITSIZE (mode
),
2651 target
= gen_reg_rtx (mode
);
2652 emit_move_insn (target
, gen_lowpart (mode
, x
));
2655 delete_insns_since (last
);
2660 /* Try calculating bswap as two bswaps of two word-sized operands. */
2663 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2667 t1
= expand_unop (word_mode
, bswap_optab
,
2668 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2669 t0
= expand_unop (word_mode
, bswap_optab
,
2670 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2672 if (target
== 0 || !valid_multiword_target_p (target
))
2673 target
= gen_reg_rtx (mode
);
2675 emit_clobber (target
);
2676 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2677 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2682 /* Try calculating (parity x) as (and (popcount x) 1), where
2683 popcount can also be done in a wider mode. */
2685 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2687 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2688 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2690 enum machine_mode wider_mode
;
2691 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2692 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2694 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2696 rtx xop0
, temp
, last
;
2698 last
= get_last_insn ();
2701 target
= gen_reg_rtx (mode
);
2702 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2703 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2706 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2707 target
, true, OPTAB_DIRECT
);
2709 delete_insns_since (last
);
2718 /* Try calculating ctz(x) as K - clz(x & -x) ,
2719 where K is GET_MODE_PRECISION(mode) - 1.
2721 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2722 don't have to worry about what the hardware does in that case. (If
2723 the clz instruction produces the usual value at 0, which is K, the
2724 result of this code sequence will be -1; expand_ffs, below, relies
2725 on this. It might be nice to have it be K instead, for consistency
2726 with the (very few) processors that provide a ctz with a defined
2727 value, but that would take one more instruction, and it would be
2728 less convenient for expand_ffs anyway. */
2731 expand_ctz (enum machine_mode mode
, rtx op0
, rtx target
)
2735 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2740 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2742 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2743 true, OPTAB_DIRECT
);
2745 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2747 temp
= expand_binop (mode
, sub_optab
, GEN_INT (GET_MODE_PRECISION (mode
) - 1),
2749 true, OPTAB_DIRECT
);
2759 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2765 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2766 else with the sequence used by expand_clz.
2768 The ffs builtin promises to return zero for a zero value and ctz/clz
2769 may have an undefined value in that case. If they do not give us a
2770 convenient value, we have to generate a test and branch. */
2772 expand_ffs (enum machine_mode mode
, rtx op0
, rtx target
)
2774 HOST_WIDE_INT val
= 0;
2775 bool defined_at_zero
= false;
2778 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2782 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2786 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2788 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2791 temp
= expand_ctz (mode
, op0
, 0);
2795 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2797 defined_at_zero
= true;
2798 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2804 if (defined_at_zero
&& val
== -1)
2805 /* No correction needed at zero. */;
2808 /* We don't try to do anything clever with the situation found
2809 on some processors (eg Alpha) where ctz(0:mode) ==
2810 bitsize(mode). If someone can think of a way to send N to -1
2811 and leave alone all values in the range 0..N-1 (where N is a
2812 power of two), cheaper than this test-and-branch, please add it.
2814 The test-and-branch is done after the operation itself, in case
2815 the operation sets condition codes that can be recycled for this.
2816 (This is true on i386, for instance.) */
2818 rtx nonzero_label
= gen_label_rtx ();
2819 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2820 mode
, true, nonzero_label
);
2822 convert_move (temp
, GEN_INT (-1), false);
2823 emit_label (nonzero_label
);
2826 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2827 to produce a value in the range 0..bitsize. */
2828 temp
= expand_binop (mode
, add_optab
, temp
, GEN_INT (1),
2829 target
, false, OPTAB_DIRECT
);
2836 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2845 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2846 conditions, VAL may already be a SUBREG against which we cannot generate
2847 a further SUBREG. In this case, we expect forcing the value into a
2848 register will work around the situation. */
2851 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2852 enum machine_mode imode
)
2855 ret
= lowpart_subreg (omode
, val
, imode
);
2858 val
= force_reg (imode
, val
);
2859 ret
= lowpart_subreg (omode
, val
, imode
);
2860 gcc_assert (ret
!= NULL
);
2865 /* Expand a floating point absolute value or negation operation via a
2866 logical operation on the sign bit. */
2869 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2870 rtx op0
, rtx target
)
2872 const struct real_format
*fmt
;
2873 int bitpos
, word
, nwords
, i
;
2874 enum machine_mode imode
;
2878 /* The format has to have a simple sign bit. */
2879 fmt
= REAL_MODE_FORMAT (mode
);
2883 bitpos
= fmt
->signbit_rw
;
2887 /* Don't create negative zeros if the format doesn't support them. */
2888 if (code
== NEG
&& !fmt
->has_signed_zero
)
2891 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2893 imode
= int_mode_for_mode (mode
);
2894 if (imode
== BLKmode
)
2903 if (FLOAT_WORDS_BIG_ENDIAN
)
2904 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2906 word
= bitpos
/ BITS_PER_WORD
;
2907 bitpos
= bitpos
% BITS_PER_WORD
;
2908 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2911 mask
= double_int_zero
.set_bit (bitpos
);
2917 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2918 target
= gen_reg_rtx (mode
);
2924 for (i
= 0; i
< nwords
; ++i
)
2926 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2927 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2931 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2933 immed_double_int_const (mask
, imode
),
2934 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2935 if (temp
!= targ_piece
)
2936 emit_move_insn (targ_piece
, temp
);
2939 emit_move_insn (targ_piece
, op0_piece
);
2942 insns
= get_insns ();
2949 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2950 gen_lowpart (imode
, op0
),
2951 immed_double_int_const (mask
, imode
),
2952 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2953 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2955 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2956 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2963 /* As expand_unop, but will fail rather than attempt the operation in a
2964 different mode or with a libcall. */
2966 expand_unop_direct (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2969 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2971 struct expand_operand ops
[2];
2972 enum insn_code icode
= optab_handler (unoptab
, mode
);
2973 rtx last
= get_last_insn ();
2976 create_output_operand (&ops
[0], target
, mode
);
2977 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2978 pat
= maybe_gen_insn (icode
, 2, ops
);
2981 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2982 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (unoptab
),
2983 ops
[1].value
, NULL_RTX
))
2985 delete_insns_since (last
);
2986 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
2991 return ops
[0].value
;
2997 /* Generate code to perform an operation specified by UNOPTAB
2998 on operand OP0, with result having machine-mode MODE.
3000 UNSIGNEDP is for the case where we have to widen the operands
3001 to perform the operation. It says to use zero-extension.
3003 If TARGET is nonzero, the value
3004 is generated there, if it is convenient to do so.
3005 In all cases an rtx is returned for the locus of the value;
3006 this may or may not be TARGET. */
3009 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3012 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3013 enum machine_mode wider_mode
;
3017 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3021 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3023 /* Widening (or narrowing) clz needs special treatment. */
3024 if (unoptab
== clz_optab
)
3026 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3030 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3031 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3033 temp
= expand_doubleword_clz (mode
, op0
, target
);
3041 if (unoptab
== clrsb_optab
)
3043 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3049 /* Widening (or narrowing) bswap needs special treatment. */
3050 if (unoptab
== bswap_optab
)
3052 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3053 or ROTATERT. First try these directly; if this fails, then try the
3054 obvious pair of shifts with allowed widening, as this will probably
3055 be always more efficient than the other fallback methods. */
3058 rtx last
, temp1
, temp2
;
3060 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3062 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3063 unsignedp
, OPTAB_DIRECT
);
3068 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3070 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3071 unsignedp
, OPTAB_DIRECT
);
3076 last
= get_last_insn ();
3078 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3079 unsignedp
, OPTAB_WIDEN
);
3080 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3081 unsignedp
, OPTAB_WIDEN
);
3084 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3085 unsignedp
, OPTAB_WIDEN
);
3090 delete_insns_since (last
);
3093 temp
= widen_bswap (mode
, op0
, target
);
3097 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3098 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3100 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3108 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3109 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3110 wider_mode
!= VOIDmode
;
3111 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3113 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3116 rtx last
= get_last_insn ();
3118 /* For certain operations, we need not actually extend
3119 the narrow operand, as long as we will truncate the
3120 results to the same narrowness. */
3122 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3123 (unoptab
== neg_optab
3124 || unoptab
== one_cmpl_optab
)
3125 && mclass
== MODE_INT
);
3127 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3132 if (mclass
!= MODE_INT
3133 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3136 target
= gen_reg_rtx (mode
);
3137 convert_move (target
, temp
, 0);
3141 return gen_lowpart (mode
, temp
);
3144 delete_insns_since (last
);
3148 /* These can be done a word at a time. */
3149 if (unoptab
== one_cmpl_optab
3150 && mclass
== MODE_INT
3151 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3152 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3157 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3158 target
= gen_reg_rtx (mode
);
3162 /* Do the actual arithmetic. */
3163 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3165 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3166 rtx x
= expand_unop (word_mode
, unoptab
,
3167 operand_subword_force (op0
, i
, mode
),
3168 target_piece
, unsignedp
);
3170 if (target_piece
!= x
)
3171 emit_move_insn (target_piece
, x
);
3174 insns
= get_insns ();
3181 if (optab_to_code (unoptab
) == NEG
)
3183 /* Try negating floating point values by flipping the sign bit. */
3184 if (SCALAR_FLOAT_MODE_P (mode
))
3186 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3191 /* If there is no negation pattern, and we have no negative zero,
3192 try subtracting from zero. */
3193 if (!HONOR_SIGNED_ZEROS (mode
))
3195 temp
= expand_binop (mode
, (unoptab
== negv_optab
3196 ? subv_optab
: sub_optab
),
3197 CONST0_RTX (mode
), op0
, target
,
3198 unsignedp
, OPTAB_DIRECT
);
3204 /* Try calculating parity (x) as popcount (x) % 2. */
3205 if (unoptab
== parity_optab
)
3207 temp
= expand_parity (mode
, op0
, target
);
3212 /* Try implementing ffs (x) in terms of clz (x). */
3213 if (unoptab
== ffs_optab
)
3215 temp
= expand_ffs (mode
, op0
, target
);
3220 /* Try implementing ctz (x) in terms of clz (x). */
3221 if (unoptab
== ctz_optab
)
3223 temp
= expand_ctz (mode
, op0
, target
);
3229 /* Now try a library call in this mode. */
3230 libfunc
= optab_libfunc (unoptab
, mode
);
3236 enum machine_mode outmode
= mode
;
3238 /* All of these functions return small values. Thus we choose to
3239 have them return something that isn't a double-word. */
3240 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3241 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3242 || unoptab
== parity_optab
)
3244 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3245 optab_libfunc (unoptab
, mode
)));
3249 /* Pass 1 for NO_QUEUE so we don't lose any increments
3250 if the libcall is cse'd or moved. */
3251 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3253 insns
= get_insns ();
3256 target
= gen_reg_rtx (outmode
);
3257 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3258 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3259 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3260 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3261 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3262 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3263 trapv_unoptab_p (unoptab
));
3268 /* It can't be done in this mode. Can we do it in a wider mode? */
3270 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3272 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3273 wider_mode
!= VOIDmode
;
3274 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3276 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3277 || optab_libfunc (unoptab
, wider_mode
))
3280 rtx last
= get_last_insn ();
3282 /* For certain operations, we need not actually extend
3283 the narrow operand, as long as we will truncate the
3284 results to the same narrowness. */
3285 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3286 (unoptab
== neg_optab
3287 || unoptab
== one_cmpl_optab
3288 || unoptab
== bswap_optab
)
3289 && mclass
== MODE_INT
);
3291 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3294 /* If we are generating clz using wider mode, adjust the
3295 result. Similarly for clrsb. */
3296 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3298 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
3299 GEN_INT (GET_MODE_PRECISION (wider_mode
)
3300 - GET_MODE_PRECISION (mode
)),
3301 target
, true, OPTAB_DIRECT
);
3303 /* Likewise for bswap. */
3304 if (unoptab
== bswap_optab
&& temp
!= 0)
3306 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3307 == GET_MODE_BITSIZE (wider_mode
)
3308 && GET_MODE_PRECISION (mode
)
3309 == GET_MODE_BITSIZE (mode
));
3311 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3312 GET_MODE_BITSIZE (wider_mode
)
3313 - GET_MODE_BITSIZE (mode
),
3319 if (mclass
!= MODE_INT
)
3322 target
= gen_reg_rtx (mode
);
3323 convert_move (target
, temp
, 0);
3327 return gen_lowpart (mode
, temp
);
3330 delete_insns_since (last
);
3335 /* One final attempt at implementing negation via subtraction,
3336 this time allowing widening of the operand. */
3337 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3340 temp
= expand_binop (mode
,
3341 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3342 CONST0_RTX (mode
), op0
,
3343 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3351 /* Emit code to compute the absolute value of OP0, with result to
3352 TARGET if convenient. (TARGET may be 0.) The return value says
3353 where the result actually is to be found.
3355 MODE is the mode of the operand; the mode of the result is
3356 different but can be deduced from MODE.
3361 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
3362 int result_unsignedp
)
3367 result_unsignedp
= 1;
3369 /* First try to do it with a special abs instruction. */
3370 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3375 /* For floating point modes, try clearing the sign bit. */
3376 if (SCALAR_FLOAT_MODE_P (mode
))
3378 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3383 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3384 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3385 && !HONOR_SIGNED_ZEROS (mode
))
3387 rtx last
= get_last_insn ();
3389 temp
= expand_unop (mode
, neg_optab
, op0
, NULL_RTX
, 0);
3391 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3397 delete_insns_since (last
);
3400 /* If this machine has expensive jumps, we can do integer absolute
3401 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3402 where W is the width of MODE. */
3404 if (GET_MODE_CLASS (mode
) == MODE_INT
3405 && BRANCH_COST (optimize_insn_for_speed_p (),
3408 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3409 GET_MODE_PRECISION (mode
) - 1,
3412 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3415 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3416 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3426 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3427 int result_unsignedp
, int safe
)
3432 result_unsignedp
= 1;
3434 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3438 /* If that does not win, use conditional jump and negate. */
3440 /* It is safe to use the target if it is the same
3441 as the source if this is also a pseudo register */
3442 if (op0
== target
&& REG_P (op0
)
3443 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3446 op1
= gen_label_rtx ();
3447 if (target
== 0 || ! safe
3448 || GET_MODE (target
) != mode
3449 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3451 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3452 target
= gen_reg_rtx (mode
);
3454 emit_move_insn (target
, op0
);
3457 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3458 NULL_RTX
, NULL_RTX
, op1
, -1);
3460 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3463 emit_move_insn (target
, op0
);
3469 /* Emit code to compute the one's complement absolute value of OP0
3470 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3471 (TARGET may be NULL_RTX.) The return value says where the result
3472 actually is to be found.
3474 MODE is the mode of the operand; the mode of the result is
3475 different but can be deduced from MODE. */
3478 expand_one_cmpl_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
)
3482 /* Not applicable for floating point modes. */
3483 if (FLOAT_MODE_P (mode
))
3486 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3487 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3489 rtx last
= get_last_insn ();
3491 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3493 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3499 delete_insns_since (last
);
3502 /* If this machine has expensive jumps, we can do one's complement
3503 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3505 if (GET_MODE_CLASS (mode
) == MODE_INT
3506 && BRANCH_COST (optimize_insn_for_speed_p (),
3509 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3510 GET_MODE_PRECISION (mode
) - 1,
3513 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3523 /* A subroutine of expand_copysign, perform the copysign operation using the
3524 abs and neg primitives advertised to exist on the target. The assumption
3525 is that we have a split register file, and leaving op0 in fp registers,
3526 and not playing with subregs so much, will help the register allocator. */
3529 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3530 int bitpos
, bool op0_is_abs
)
3532 enum machine_mode imode
;
3533 enum insn_code icode
;
3539 /* Check if the back end provides an insn that handles signbit for the
3541 icode
= optab_handler (signbit_optab
, mode
);
3542 if (icode
!= CODE_FOR_nothing
)
3544 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3545 sign
= gen_reg_rtx (imode
);
3546 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3552 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3554 imode
= int_mode_for_mode (mode
);
3555 if (imode
== BLKmode
)
3557 op1
= gen_lowpart (imode
, op1
);
3564 if (FLOAT_WORDS_BIG_ENDIAN
)
3565 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3567 word
= bitpos
/ BITS_PER_WORD
;
3568 bitpos
= bitpos
% BITS_PER_WORD
;
3569 op1
= operand_subword_force (op1
, word
, mode
);
3572 mask
= double_int_zero
.set_bit (bitpos
);
3574 sign
= expand_binop (imode
, and_optab
, op1
,
3575 immed_double_int_const (mask
, imode
),
3576 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3581 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3588 if (target
== NULL_RTX
)
3589 target
= copy_to_reg (op0
);
3591 emit_move_insn (target
, op0
);
3594 label
= gen_label_rtx ();
3595 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3597 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3598 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3600 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3602 emit_move_insn (target
, op0
);
3610 /* A subroutine of expand_copysign, perform the entire copysign operation
3611 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3612 is true if op0 is known to have its sign bit clear. */
3615 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3616 int bitpos
, bool op0_is_abs
)
3618 enum machine_mode imode
;
3620 int word
, nwords
, i
;
3623 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3625 imode
= int_mode_for_mode (mode
);
3626 if (imode
== BLKmode
)
3635 if (FLOAT_WORDS_BIG_ENDIAN
)
3636 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3638 word
= bitpos
/ BITS_PER_WORD
;
3639 bitpos
= bitpos
% BITS_PER_WORD
;
3640 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3643 mask
= double_int_zero
.set_bit (bitpos
);
3648 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3649 target
= gen_reg_rtx (mode
);
3655 for (i
= 0; i
< nwords
; ++i
)
3657 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3658 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3664 = expand_binop (imode
, and_optab
, op0_piece
,
3665 immed_double_int_const (~mask
, imode
),
3666 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3668 op1
= expand_binop (imode
, and_optab
,
3669 operand_subword_force (op1
, i
, mode
),
3670 immed_double_int_const (mask
, imode
),
3671 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3673 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3674 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3675 if (temp
!= targ_piece
)
3676 emit_move_insn (targ_piece
, temp
);
3679 emit_move_insn (targ_piece
, op0_piece
);
3682 insns
= get_insns ();
3689 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3690 immed_double_int_const (mask
, imode
),
3691 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3693 op0
= gen_lowpart (imode
, op0
);
3695 op0
= expand_binop (imode
, and_optab
, op0
,
3696 immed_double_int_const (~mask
, imode
),
3697 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3699 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3700 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3701 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3707 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3708 scalar floating point mode. Return NULL if we do not know how to
3709 expand the operation inline. */
3712 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3714 enum machine_mode mode
= GET_MODE (op0
);
3715 const struct real_format
*fmt
;
3719 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3720 gcc_assert (GET_MODE (op1
) == mode
);
3722 /* First try to do it with a special instruction. */
3723 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3724 target
, 0, OPTAB_DIRECT
);
3728 fmt
= REAL_MODE_FORMAT (mode
);
3729 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3733 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3735 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3736 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3740 if (fmt
->signbit_ro
>= 0
3741 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3742 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3743 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3745 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3746 fmt
->signbit_ro
, op0_is_abs
);
3751 if (fmt
->signbit_rw
< 0)
3753 return expand_copysign_bit (mode
, op0
, op1
, target
,
3754 fmt
->signbit_rw
, op0_is_abs
);
3757 /* Generate an instruction whose insn-code is INSN_CODE,
3758 with two operands: an output TARGET and an input OP0.
3759 TARGET *must* be nonzero, and the output is always stored there.
3760 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3761 the value that is stored into TARGET.
3763 Return false if expansion failed. */
3766 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3769 struct expand_operand ops
[2];
3772 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3773 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3774 pat
= maybe_gen_insn (icode
, 2, ops
);
3778 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
3779 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3783 if (ops
[0].value
!= target
)
3784 emit_move_insn (target
, ops
[0].value
);
3787 /* Generate an instruction whose insn-code is INSN_CODE,
3788 with two operands: an output TARGET and an input OP0.
3789 TARGET *must* be nonzero, and the output is always stored there.
3790 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3791 the value that is stored into TARGET. */
3794 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3796 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3800 struct no_conflict_data
3802 rtx target
, first
, insn
;
3806 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3807 the currently examined clobber / store has to stay in the list of
3808 insns that constitute the actual libcall block. */
3810 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3812 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3814 /* If this inns directly contributes to setting the target, it must stay. */
3815 if (reg_overlap_mentioned_p (p
->target
, dest
))
3816 p
->must_stay
= true;
3817 /* If we haven't committed to keeping any other insns in the list yet,
3818 there is nothing more to check. */
3819 else if (p
->insn
== p
->first
)
3821 /* If this insn sets / clobbers a register that feeds one of the insns
3822 already in the list, this insn has to stay too. */
3823 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3824 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3825 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3826 /* Likewise if this insn depends on a register set by a previous
3827 insn in the list, or if it sets a result (presumably a hard
3828 register) that is set or clobbered by a previous insn.
3829 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3830 SET_DEST perform the former check on the address, and the latter
3831 check on the MEM. */
3832 || (GET_CODE (set
) == SET
3833 && (modified_in_p (SET_SRC (set
), p
->first
)
3834 || modified_in_p (SET_DEST (set
), p
->first
)
3835 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3836 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3837 p
->must_stay
= true;
3841 /* Emit code to make a call to a constant function or a library call.
3843 INSNS is a list containing all insns emitted in the call.
3844 These insns leave the result in RESULT. Our block is to copy RESULT
3845 to TARGET, which is logically equivalent to EQUIV.
3847 We first emit any insns that set a pseudo on the assumption that these are
3848 loading constants into registers; doing so allows them to be safely cse'ed
3849 between blocks. Then we emit all the other insns in the block, followed by
3850 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3851 note with an operand of EQUIV. */
3854 emit_libcall_block_1 (rtx insns
, rtx target
, rtx result
, rtx equiv
,
3855 bool equiv_may_trap
)
3857 rtx final_dest
= target
;
3858 rtx next
, last
, insn
;
3860 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3861 into a MEM later. Protect the libcall block from this change. */
3862 if (! REG_P (target
) || REG_USERVAR_P (target
))
3863 target
= gen_reg_rtx (GET_MODE (target
));
3865 /* If we're using non-call exceptions, a libcall corresponding to an
3866 operation that may trap may also trap. */
3867 /* ??? See the comment in front of make_reg_eh_region_note. */
3868 if (cfun
->can_throw_non_call_exceptions
3869 && (equiv_may_trap
|| may_trap_p (equiv
)))
3871 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3874 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3877 int lp_nr
= INTVAL (XEXP (note
, 0));
3878 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3879 remove_note (insn
, note
);
3885 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3886 reg note to indicate that this call cannot throw or execute a nonlocal
3887 goto (unless there is already a REG_EH_REGION note, in which case
3889 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3891 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3894 /* First emit all insns that set pseudos. Remove them from the list as
3895 we go. Avoid insns that set pseudos which were referenced in previous
3896 insns. These can be generated by move_by_pieces, for example,
3897 to update an address. Similarly, avoid insns that reference things
3898 set in previous insns. */
3900 for (insn
= insns
; insn
; insn
= next
)
3902 rtx set
= single_set (insn
);
3904 next
= NEXT_INSN (insn
);
3906 if (set
!= 0 && REG_P (SET_DEST (set
))
3907 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3909 struct no_conflict_data data
;
3911 data
.target
= const0_rtx
;
3915 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3916 if (! data
.must_stay
)
3918 if (PREV_INSN (insn
))
3919 NEXT_INSN (PREV_INSN (insn
)) = next
;
3924 PREV_INSN (next
) = PREV_INSN (insn
);
3930 /* Some ports use a loop to copy large arguments onto the stack.
3931 Don't move anything outside such a loop. */
3936 /* Write the remaining insns followed by the final copy. */
3937 for (insn
= insns
; insn
; insn
= next
)
3939 next
= NEXT_INSN (insn
);
3944 last
= emit_move_insn (target
, result
);
3945 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3947 if (final_dest
!= target
)
3948 emit_move_insn (final_dest
, target
);
3952 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3954 emit_libcall_block_1 (insns
, target
, result
, equiv
, false);
3957 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3958 PURPOSE describes how this comparison will be used. CODE is the rtx
3959 comparison code we will be using.
3961 ??? Actually, CODE is slightly weaker than that. A target is still
3962 required to implement all of the normal bcc operations, but not
3963 required to implement all (or any) of the unordered bcc operations. */
3966 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
3967 enum can_compare_purpose purpose
)
3970 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3973 enum insn_code icode
;
3975 if (purpose
== ccp_jump
3976 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
3977 && insn_operand_matches (icode
, 0, test
))
3979 if (purpose
== ccp_store_flag
3980 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
3981 && insn_operand_matches (icode
, 1, test
))
3983 if (purpose
== ccp_cmov
3984 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
3987 mode
= GET_MODE_WIDER_MODE (mode
);
3988 PUT_MODE (test
, mode
);
3990 while (mode
!= VOIDmode
);
3995 /* This function is called when we are going to emit a compare instruction that
3996 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
3998 *PMODE is the mode of the inputs (in case they are const_int).
3999 *PUNSIGNEDP nonzero says that the operands are unsigned;
4000 this matters if they need to be widened (as given by METHODS).
4002 If they have mode BLKmode, then SIZE specifies the size of both operands.
4004 This function performs all the setup necessary so that the caller only has
4005 to emit a single comparison insn. This setup can involve doing a BLKmode
4006 comparison or emitting a library call to perform the comparison if no insn
4007 is available to handle it.
4008 The values which are passed in through pointers can be modified; the caller
4009 should perform the comparison on the modified values. Constant
4010 comparisons must have already been folded. */
4013 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4014 int unsignedp
, enum optab_methods methods
,
4015 rtx
*ptest
, enum machine_mode
*pmode
)
4017 enum machine_mode mode
= *pmode
;
4019 enum machine_mode cmp_mode
;
4020 enum mode_class mclass
;
4022 /* The other methods are not needed. */
4023 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4024 || methods
== OPTAB_LIB_WIDEN
);
4026 /* If we are optimizing, force expensive constants into a register. */
4027 if (CONSTANT_P (x
) && optimize
4028 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4029 > COSTS_N_INSNS (1)))
4030 x
= force_reg (mode
, x
);
4032 if (CONSTANT_P (y
) && optimize
4033 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4034 > COSTS_N_INSNS (1)))
4035 y
= force_reg (mode
, y
);
4038 /* Make sure if we have a canonical comparison. The RTL
4039 documentation states that canonical comparisons are required only
4040 for targets which have cc0. */
4041 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4044 /* Don't let both operands fail to indicate the mode. */
4045 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4046 x
= force_reg (mode
, x
);
4047 if (mode
== VOIDmode
)
4048 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4050 /* Handle all BLKmode compares. */
4052 if (mode
== BLKmode
)
4054 enum machine_mode result_mode
;
4055 enum insn_code cmp_code
;
4060 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4064 /* Try to use a memory block compare insn - either cmpstr
4065 or cmpmem will do. */
4066 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4067 cmp_mode
!= VOIDmode
;
4068 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4070 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4071 if (cmp_code
== CODE_FOR_nothing
)
4072 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4073 if (cmp_code
== CODE_FOR_nothing
)
4074 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4075 if (cmp_code
== CODE_FOR_nothing
)
4078 /* Must make sure the size fits the insn's mode. */
4079 if ((CONST_INT_P (size
)
4080 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4081 || (GET_MODE_BITSIZE (GET_MODE (size
))
4082 > GET_MODE_BITSIZE (cmp_mode
)))
4085 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4086 result
= gen_reg_rtx (result_mode
);
4087 size
= convert_to_mode (cmp_mode
, size
, 1);
4088 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4090 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4091 *pmode
= result_mode
;
4095 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4098 /* Otherwise call a library function, memcmp. */
4099 libfunc
= memcmp_libfunc
;
4100 length_type
= sizetype
;
4101 result_mode
= TYPE_MODE (integer_type_node
);
4102 cmp_mode
= TYPE_MODE (length_type
);
4103 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4104 TYPE_UNSIGNED (length_type
));
4106 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4112 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4113 *pmode
= result_mode
;
4117 /* Don't allow operands to the compare to trap, as that can put the
4118 compare and branch in different basic blocks. */
4119 if (cfun
->can_throw_non_call_exceptions
)
4122 x
= force_reg (mode
, x
);
4124 y
= force_reg (mode
, y
);
4127 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4129 gcc_assert (can_compare_p (comparison
, CCmode
, ccp_jump
));
4130 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4134 mclass
= GET_MODE_CLASS (mode
);
4135 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4139 enum insn_code icode
;
4140 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4141 if (icode
!= CODE_FOR_nothing
4142 && insn_operand_matches (icode
, 0, test
))
4144 rtx last
= get_last_insn ();
4145 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4146 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4148 && insn_operand_matches (icode
, 1, op0
)
4149 && insn_operand_matches (icode
, 2, op1
))
4151 XEXP (test
, 0) = op0
;
4152 XEXP (test
, 1) = op1
;
4157 delete_insns_since (last
);
4160 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4162 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4164 while (cmp_mode
!= VOIDmode
);
4166 if (methods
!= OPTAB_LIB_WIDEN
)
4169 if (!SCALAR_FLOAT_MODE_P (mode
))
4172 enum machine_mode ret_mode
;
4174 /* Handle a libcall just for the mode we are using. */
4175 libfunc
= optab_libfunc (cmp_optab
, mode
);
4176 gcc_assert (libfunc
);
4178 /* If we want unsigned, and this mode has a distinct unsigned
4179 comparison routine, use that. */
4182 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4187 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4188 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4189 ret_mode
, 2, x
, mode
, y
, mode
);
4191 /* There are two kinds of comparison routines. Biased routines
4192 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4193 of gcc expect that the comparison operation is equivalent
4194 to the modified comparison. For signed comparisons compare the
4195 result against 1 in the biased case, and zero in the unbiased
4196 case. For unsigned comparisons always compare against 1 after
4197 biasing the unbiased result by adding 1. This gives us a way to
4199 The comparisons in the fixed-point helper library are always
4204 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4207 x
= plus_constant (ret_mode
, result
, 1);
4213 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4217 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4225 /* Before emitting an insn with code ICODE, make sure that X, which is going
4226 to be used for operand OPNUM of the insn, is converted from mode MODE to
4227 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4228 that it is accepted by the operand predicate. Return the new value. */
4231 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, enum machine_mode mode
,
4232 enum machine_mode wider_mode
, int unsignedp
)
4234 if (mode
!= wider_mode
)
4235 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4237 if (!insn_operand_matches (icode
, opnum
, x
))
4239 if (reload_completed
)
4241 x
= copy_to_mode_reg (insn_data
[(int) icode
].operand
[opnum
].mode
, x
);
4247 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4248 we can do the branch. */
4251 emit_cmp_and_jump_insn_1 (rtx test
, enum machine_mode mode
, rtx label
)
4253 enum machine_mode optab_mode
;
4254 enum mode_class mclass
;
4255 enum insn_code icode
;
4257 mclass
= GET_MODE_CLASS (mode
);
4258 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4259 icode
= optab_handler (cbranch_optab
, optab_mode
);
4261 gcc_assert (icode
!= CODE_FOR_nothing
);
4262 gcc_assert (insn_operand_matches (icode
, 0, test
));
4263 emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0), XEXP (test
, 1), label
));
4266 /* Generate code to compare X with Y so that the condition codes are
4267 set and to jump to LABEL if the condition is true. If X is a
4268 constant and Y is not a constant, then the comparison is swapped to
4269 ensure that the comparison RTL has the canonical form.
4271 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4272 need to be widened. UNSIGNEDP is also used to select the proper
4273 branch condition code.
4275 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4277 MODE is the mode of the inputs (in case they are const_int).
4279 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4280 It will be potentially converted into an unsigned variant based on
4281 UNSIGNEDP to select a proper jump instruction. */
4284 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4285 enum machine_mode mode
, int unsignedp
, rtx label
)
4287 rtx op0
= x
, op1
= y
;
4290 /* Swap operands and condition to ensure canonical RTL. */
4291 if (swap_commutative_operands_p (x
, y
)
4292 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4295 comparison
= swap_condition (comparison
);
4298 /* If OP0 is still a constant, then both X and Y must be constants
4299 or the opposite comparison is not supported. Force X into a register
4300 to create canonical RTL. */
4301 if (CONSTANT_P (op0
))
4302 op0
= force_reg (mode
, op0
);
4305 comparison
= unsigned_condition (comparison
);
4307 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4309 emit_cmp_and_jump_insn_1 (test
, mode
, label
);
4313 /* Emit a library call comparison between floating point X and Y.
4314 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4317 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4318 rtx
*ptest
, enum machine_mode
*pmode
)
4320 enum rtx_code swapped
= swap_condition (comparison
);
4321 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4322 enum machine_mode orig_mode
= GET_MODE (x
);
4323 enum machine_mode mode
, cmp_mode
;
4324 rtx true_rtx
, false_rtx
;
4325 rtx value
, target
, insns
, equiv
;
4327 bool reversed_p
= false;
4328 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4330 for (mode
= orig_mode
;
4332 mode
= GET_MODE_WIDER_MODE (mode
))
4334 if (code_to_optab (comparison
)
4335 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4338 if (code_to_optab (swapped
)
4339 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4342 tmp
= x
; x
= y
; y
= tmp
;
4343 comparison
= swapped
;
4347 if (code_to_optab (reversed
)
4348 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4350 comparison
= reversed
;
4356 gcc_assert (mode
!= VOIDmode
);
4358 if (mode
!= orig_mode
)
4360 x
= convert_to_mode (mode
, x
, 0);
4361 y
= convert_to_mode (mode
, y
, 0);
4364 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4365 the RTL. The allows the RTL optimizers to delete the libcall if the
4366 condition can be determined at compile-time. */
4367 if (comparison
== UNORDERED
4368 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4370 true_rtx
= const_true_rtx
;
4371 false_rtx
= const0_rtx
;
4378 true_rtx
= const0_rtx
;
4379 false_rtx
= const_true_rtx
;
4383 true_rtx
= const_true_rtx
;
4384 false_rtx
= const0_rtx
;
4388 true_rtx
= const1_rtx
;
4389 false_rtx
= const0_rtx
;
4393 true_rtx
= const0_rtx
;
4394 false_rtx
= constm1_rtx
;
4398 true_rtx
= constm1_rtx
;
4399 false_rtx
= const0_rtx
;
4403 true_rtx
= const0_rtx
;
4404 false_rtx
= const1_rtx
;
4412 if (comparison
== UNORDERED
)
4414 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4415 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4416 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4417 temp
, const_true_rtx
, equiv
);
4421 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4422 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4423 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4424 equiv
, true_rtx
, false_rtx
);
4428 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4429 cmp_mode
, 2, x
, mode
, y
, mode
);
4430 insns
= get_insns ();
4433 target
= gen_reg_rtx (cmp_mode
);
4434 emit_libcall_block (insns
, target
, value
, equiv
);
4436 if (comparison
== UNORDERED
4437 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4439 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4441 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4446 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4449 emit_indirect_jump (rtx loc
)
4451 struct expand_operand ops
[1];
4453 create_address_operand (&ops
[0], loc
);
4454 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4458 #ifdef HAVE_conditional_move
4460 /* Emit a conditional move instruction if the machine supports one for that
4461 condition and machine mode.
4463 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4464 the mode to use should they be constants. If it is VOIDmode, they cannot
4467 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4468 should be stored there. MODE is the mode to use should they be constants.
4469 If it is VOIDmode, they cannot both be constants.
4471 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4472 is not supported. */
4475 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4476 enum machine_mode cmode
, rtx op2
, rtx op3
,
4477 enum machine_mode mode
, int unsignedp
)
4479 rtx tem
, comparison
, last
;
4480 enum insn_code icode
;
4481 enum rtx_code reversed
;
4483 /* If one operand is constant, make it the second one. Only do this
4484 if the other operand is not constant as well. */
4486 if (swap_commutative_operands_p (op0
, op1
))
4491 code
= swap_condition (code
);
4494 /* get_condition will prefer to generate LT and GT even if the old
4495 comparison was against zero, so undo that canonicalization here since
4496 comparisons against zero are cheaper. */
4497 if (code
== LT
&& op1
== const1_rtx
)
4498 code
= LE
, op1
= const0_rtx
;
4499 else if (code
== GT
&& op1
== constm1_rtx
)
4500 code
= GE
, op1
= const0_rtx
;
4502 if (cmode
== VOIDmode
)
4503 cmode
= GET_MODE (op0
);
4505 if (swap_commutative_operands_p (op2
, op3
)
4506 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4515 if (mode
== VOIDmode
)
4516 mode
= GET_MODE (op2
);
4518 icode
= direct_optab_handler (movcc_optab
, mode
);
4520 if (icode
== CODE_FOR_nothing
)
4524 target
= gen_reg_rtx (mode
);
4526 code
= unsignedp
? unsigned_condition (code
) : code
;
4527 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4529 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4530 return NULL and let the caller figure out how best to deal with this
4532 if (!COMPARISON_P (comparison
))
4535 do_pending_stack_adjust ();
4536 last
= get_last_insn ();
4537 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4538 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4539 &comparison
, &cmode
);
4542 struct expand_operand ops
[4];
4544 create_output_operand (&ops
[0], target
, mode
);
4545 create_fixed_operand (&ops
[1], comparison
);
4546 create_input_operand (&ops
[2], op2
, mode
);
4547 create_input_operand (&ops
[3], op3
, mode
);
4548 if (maybe_expand_insn (icode
, 4, ops
))
4550 if (ops
[0].value
!= target
)
4551 convert_move (target
, ops
[0].value
, false);
4555 delete_insns_since (last
);
4559 /* Return nonzero if a conditional move of mode MODE is supported.
4561 This function is for combine so it can tell whether an insn that looks
4562 like a conditional move is actually supported by the hardware. If we
4563 guess wrong we lose a bit on optimization, but that's it. */
4564 /* ??? sparc64 supports conditionally moving integers values based on fp
4565 comparisons, and vice versa. How do we handle them? */
4568 can_conditionally_move_p (enum machine_mode mode
)
4570 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4576 #endif /* HAVE_conditional_move */
4578 /* Emit a conditional addition instruction if the machine supports one for that
4579 condition and machine mode.
4581 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4582 the mode to use should they be constants. If it is VOIDmode, they cannot
4585 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4586 should be stored there. MODE is the mode to use should they be constants.
4587 If it is VOIDmode, they cannot both be constants.
4589 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4590 is not supported. */
4593 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4594 enum machine_mode cmode
, rtx op2
, rtx op3
,
4595 enum machine_mode mode
, int unsignedp
)
4597 rtx tem
, comparison
, last
;
4598 enum insn_code icode
;
4600 /* If one operand is constant, make it the second one. Only do this
4601 if the other operand is not constant as well. */
4603 if (swap_commutative_operands_p (op0
, op1
))
4608 code
= swap_condition (code
);
4611 /* get_condition will prefer to generate LT and GT even if the old
4612 comparison was against zero, so undo that canonicalization here since
4613 comparisons against zero are cheaper. */
4614 if (code
== LT
&& op1
== const1_rtx
)
4615 code
= LE
, op1
= const0_rtx
;
4616 else if (code
== GT
&& op1
== constm1_rtx
)
4617 code
= GE
, op1
= const0_rtx
;
4619 if (cmode
== VOIDmode
)
4620 cmode
= GET_MODE (op0
);
4622 if (mode
== VOIDmode
)
4623 mode
= GET_MODE (op2
);
4625 icode
= optab_handler (addcc_optab
, mode
);
4627 if (icode
== CODE_FOR_nothing
)
4631 target
= gen_reg_rtx (mode
);
4633 code
= unsignedp
? unsigned_condition (code
) : code
;
4634 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4636 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4637 return NULL and let the caller figure out how best to deal with this
4639 if (!COMPARISON_P (comparison
))
4642 do_pending_stack_adjust ();
4643 last
= get_last_insn ();
4644 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4645 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4646 &comparison
, &cmode
);
4649 struct expand_operand ops
[4];
4651 create_output_operand (&ops
[0], target
, mode
);
4652 create_fixed_operand (&ops
[1], comparison
);
4653 create_input_operand (&ops
[2], op2
, mode
);
4654 create_input_operand (&ops
[3], op3
, mode
);
4655 if (maybe_expand_insn (icode
, 4, ops
))
4657 if (ops
[0].value
!= target
)
4658 convert_move (target
, ops
[0].value
, false);
4662 delete_insns_since (last
);
4666 /* These functions attempt to generate an insn body, rather than
4667 emitting the insn, but if the gen function already emits them, we
4668 make no attempt to turn them back into naked patterns. */
4670 /* Generate and return an insn body to add Y to X. */
4673 gen_add2_insn (rtx x
, rtx y
)
4675 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4677 gcc_assert (insn_operand_matches (icode
, 0, x
));
4678 gcc_assert (insn_operand_matches (icode
, 1, x
));
4679 gcc_assert (insn_operand_matches (icode
, 2, y
));
4681 return GEN_FCN (icode
) (x
, x
, y
);
4684 /* Generate and return an insn body to add r1 and c,
4685 storing the result in r0. */
4688 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4690 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4692 if (icode
== CODE_FOR_nothing
4693 || !insn_operand_matches (icode
, 0, r0
)
4694 || !insn_operand_matches (icode
, 1, r1
)
4695 || !insn_operand_matches (icode
, 2, c
))
4698 return GEN_FCN (icode
) (r0
, r1
, c
);
4702 have_add2_insn (rtx x
, rtx y
)
4704 enum insn_code icode
;
4706 gcc_assert (GET_MODE (x
) != VOIDmode
);
4708 icode
= optab_handler (add_optab
, GET_MODE (x
));
4710 if (icode
== CODE_FOR_nothing
)
4713 if (!insn_operand_matches (icode
, 0, x
)
4714 || !insn_operand_matches (icode
, 1, x
)
4715 || !insn_operand_matches (icode
, 2, y
))
4721 /* Generate and return an insn body to subtract Y from X. */
4724 gen_sub2_insn (rtx x
, rtx y
)
4726 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4728 gcc_assert (insn_operand_matches (icode
, 0, x
));
4729 gcc_assert (insn_operand_matches (icode
, 1, x
));
4730 gcc_assert (insn_operand_matches (icode
, 2, y
));
4732 return GEN_FCN (icode
) (x
, x
, y
);
4735 /* Generate and return an insn body to subtract r1 and c,
4736 storing the result in r0. */
4739 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4741 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4743 if (icode
== CODE_FOR_nothing
4744 || !insn_operand_matches (icode
, 0, r0
)
4745 || !insn_operand_matches (icode
, 1, r1
)
4746 || !insn_operand_matches (icode
, 2, c
))
4749 return GEN_FCN (icode
) (r0
, r1
, c
);
4753 have_sub2_insn (rtx x
, rtx y
)
4755 enum insn_code icode
;
4757 gcc_assert (GET_MODE (x
) != VOIDmode
);
4759 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4761 if (icode
== CODE_FOR_nothing
)
4764 if (!insn_operand_matches (icode
, 0, x
)
4765 || !insn_operand_matches (icode
, 1, x
)
4766 || !insn_operand_matches (icode
, 2, y
))
4772 /* Generate the body of an instruction to copy Y into X.
4773 It may be a list of insns, if one insn isn't enough. */
4776 gen_move_insn (rtx x
, rtx y
)
4781 emit_move_insn_1 (x
, y
);
4787 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4788 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4789 no such operation exists, CODE_FOR_nothing will be returned. */
4792 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4796 #ifdef HAVE_ptr_extend
4798 return CODE_FOR_ptr_extend
;
4801 tab
= unsignedp
? zext_optab
: sext_optab
;
4802 return convert_optab_handler (tab
, to_mode
, from_mode
);
4805 /* Generate the body of an insn to extend Y (with mode MFROM)
4806 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4809 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4810 enum machine_mode mfrom
, int unsignedp
)
4812 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4813 return GEN_FCN (icode
) (x
, y
);
4816 /* can_fix_p and can_float_p say whether the target machine
4817 can directly convert a given fixed point type to
4818 a given floating point type, or vice versa.
4819 The returned value is the CODE_FOR_... value to use,
4820 or CODE_FOR_nothing if these modes cannot be directly converted.
4822 *TRUNCP_PTR is set to 1 if it is necessary to output
4823 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4825 static enum insn_code
4826 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4827 int unsignedp
, int *truncp_ptr
)
4830 enum insn_code icode
;
4832 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4833 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4834 if (icode
!= CODE_FOR_nothing
)
4840 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4841 for this to work. We need to rework the fix* and ftrunc* patterns
4842 and documentation. */
4843 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4844 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4845 if (icode
!= CODE_FOR_nothing
4846 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4853 return CODE_FOR_nothing
;
4857 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4862 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4863 return convert_optab_handler (tab
, fltmode
, fixmode
);
4866 /* Function supportable_convert_operation
4868 Check whether an operation represented by the code CODE is a
4869 convert operation that is supported by the target platform in
4870 vector form (i.e., when operating on arguments of type VECTYPE_IN
4871 producing a result of type VECTYPE_OUT).
4873 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4874 This function checks if these operations are supported
4875 by the target platform either directly (via vector tree-codes), or via
4879 - CODE1 is code of vector operation to be used when
4880 vectorizing the operation, if available.
4881 - DECL is decl of target builtin functions to be used
4882 when vectorizing the operation, if available. In this case,
4883 CODE1 is CALL_EXPR. */
4886 supportable_convert_operation (enum tree_code code
,
4887 tree vectype_out
, tree vectype_in
,
4888 tree
*decl
, enum tree_code
*code1
)
4890 enum machine_mode m1
,m2
;
4893 m1
= TYPE_MODE (vectype_out
);
4894 m2
= TYPE_MODE (vectype_in
);
4896 /* First check if we can done conversion directly. */
4897 if ((code
== FIX_TRUNC_EXPR
4898 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
4899 != CODE_FOR_nothing
)
4900 || (code
== FLOAT_EXPR
4901 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
4902 != CODE_FOR_nothing
))
4908 /* Now check for builtin. */
4909 if (targetm
.vectorize
.builtin_conversion
4910 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
4913 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
4920 /* Generate code to convert FROM to floating point
4921 and store in TO. FROM must be fixed point and not VOIDmode.
4922 UNSIGNEDP nonzero means regard FROM as unsigned.
4923 Normally this is done by correcting the final value
4924 if it is negative. */
4927 expand_float (rtx to
, rtx from
, int unsignedp
)
4929 enum insn_code icode
;
4931 enum machine_mode fmode
, imode
;
4932 bool can_do_signed
= false;
4934 /* Crash now, because we won't be able to decide which mode to use. */
4935 gcc_assert (GET_MODE (from
) != VOIDmode
);
4937 /* Look for an insn to do the conversion. Do it in the specified
4938 modes if possible; otherwise convert either input, output or both to
4939 wider mode. If the integer mode is wider than the mode of FROM,
4940 we can do the conversion signed even if the input is unsigned. */
4942 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4943 fmode
= GET_MODE_WIDER_MODE (fmode
))
4944 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
4945 imode
= GET_MODE_WIDER_MODE (imode
))
4947 int doing_unsigned
= unsignedp
;
4949 if (fmode
!= GET_MODE (to
)
4950 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
4953 icode
= can_float_p (fmode
, imode
, unsignedp
);
4954 if (icode
== CODE_FOR_nothing
&& unsignedp
)
4956 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
4957 if (scode
!= CODE_FOR_nothing
)
4958 can_do_signed
= true;
4959 if (imode
!= GET_MODE (from
))
4960 icode
= scode
, doing_unsigned
= 0;
4963 if (icode
!= CODE_FOR_nothing
)
4965 if (imode
!= GET_MODE (from
))
4966 from
= convert_to_mode (imode
, from
, unsignedp
);
4968 if (fmode
!= GET_MODE (to
))
4969 target
= gen_reg_rtx (fmode
);
4971 emit_unop_insn (icode
, target
, from
,
4972 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
4975 convert_move (to
, target
, 0);
4980 /* Unsigned integer, and no way to convert directly. Convert as signed,
4981 then unconditionally adjust the result. */
4982 if (unsignedp
&& can_do_signed
)
4984 rtx label
= gen_label_rtx ();
4986 REAL_VALUE_TYPE offset
;
4988 /* Look for a usable floating mode FMODE wider than the source and at
4989 least as wide as the target. Using FMODE will avoid rounding woes
4990 with unsigned values greater than the signed maximum value. */
4992 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4993 fmode
= GET_MODE_WIDER_MODE (fmode
))
4994 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
4995 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
4998 if (fmode
== VOIDmode
)
5000 /* There is no such mode. Pretend the target is wide enough. */
5001 fmode
= GET_MODE (to
);
5003 /* Avoid double-rounding when TO is narrower than FROM. */
5004 if ((significand_size (fmode
) + 1)
5005 < GET_MODE_PRECISION (GET_MODE (from
)))
5008 rtx neglabel
= gen_label_rtx ();
5010 /* Don't use TARGET if it isn't a register, is a hard register,
5011 or is the wrong mode. */
5013 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5014 || GET_MODE (target
) != fmode
)
5015 target
= gen_reg_rtx (fmode
);
5017 imode
= GET_MODE (from
);
5018 do_pending_stack_adjust ();
5020 /* Test whether the sign bit is set. */
5021 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5024 /* The sign bit is not set. Convert as signed. */
5025 expand_float (target
, from
, 0);
5026 emit_jump_insn (gen_jump (label
));
5029 /* The sign bit is set.
5030 Convert to a usable (positive signed) value by shifting right
5031 one bit, while remembering if a nonzero bit was shifted
5032 out; i.e., compute (from & 1) | (from >> 1). */
5034 emit_label (neglabel
);
5035 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5036 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5037 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5038 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5040 expand_float (target
, temp
, 0);
5042 /* Multiply by 2 to undo the shift above. */
5043 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5044 target
, 0, OPTAB_LIB_WIDEN
);
5046 emit_move_insn (target
, temp
);
5048 do_pending_stack_adjust ();
5054 /* If we are about to do some arithmetic to correct for an
5055 unsigned operand, do it in a pseudo-register. */
5057 if (GET_MODE (to
) != fmode
5058 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5059 target
= gen_reg_rtx (fmode
);
5061 /* Convert as signed integer to floating. */
5062 expand_float (target
, from
, 0);
5064 /* If FROM is negative (and therefore TO is negative),
5065 correct its value by 2**bitwidth. */
5067 do_pending_stack_adjust ();
5068 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5072 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5073 temp
= expand_binop (fmode
, add_optab
, target
,
5074 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5075 target
, 0, OPTAB_LIB_WIDEN
);
5077 emit_move_insn (target
, temp
);
5079 do_pending_stack_adjust ();
5084 /* No hardware instruction available; call a library routine. */
5089 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5091 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
5092 from
= convert_to_mode (SImode
, from
, unsignedp
);
5094 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5095 gcc_assert (libfunc
);
5099 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5100 GET_MODE (to
), 1, from
,
5102 insns
= get_insns ();
5105 emit_libcall_block (insns
, target
, value
,
5106 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5107 GET_MODE (to
), from
));
5112 /* Copy result to requested destination
5113 if we have been computing in a temp location. */
5117 if (GET_MODE (target
) == GET_MODE (to
))
5118 emit_move_insn (to
, target
);
5120 convert_move (to
, target
, 0);
5124 /* Generate code to convert FROM to fixed point and store in TO. FROM
5125 must be floating point. */
5128 expand_fix (rtx to
, rtx from
, int unsignedp
)
5130 enum insn_code icode
;
5132 enum machine_mode fmode
, imode
;
5135 /* We first try to find a pair of modes, one real and one integer, at
5136 least as wide as FROM and TO, respectively, in which we can open-code
5137 this conversion. If the integer mode is wider than the mode of TO,
5138 we can do the conversion either signed or unsigned. */
5140 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5141 fmode
= GET_MODE_WIDER_MODE (fmode
))
5142 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5143 imode
= GET_MODE_WIDER_MODE (imode
))
5145 int doing_unsigned
= unsignedp
;
5147 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5148 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5149 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5151 if (icode
!= CODE_FOR_nothing
)
5153 rtx last
= get_last_insn ();
5154 if (fmode
!= GET_MODE (from
))
5155 from
= convert_to_mode (fmode
, from
, 0);
5159 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5160 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5164 if (imode
!= GET_MODE (to
))
5165 target
= gen_reg_rtx (imode
);
5167 if (maybe_emit_unop_insn (icode
, target
, from
,
5168 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5171 convert_move (to
, target
, unsignedp
);
5174 delete_insns_since (last
);
5178 /* For an unsigned conversion, there is one more way to do it.
5179 If we have a signed conversion, we generate code that compares
5180 the real value to the largest representable positive number. If if
5181 is smaller, the conversion is done normally. Otherwise, subtract
5182 one plus the highest signed number, convert, and add it back.
5184 We only need to check all real modes, since we know we didn't find
5185 anything with a wider integer mode.
5187 This code used to extend FP value into mode wider than the destination.
5188 This is needed for decimal float modes which cannot accurately
5189 represent one plus the highest signed number of the same size, but
5190 not for binary modes. Consider, for instance conversion from SFmode
5193 The hot path through the code is dealing with inputs smaller than 2^63
5194 and doing just the conversion, so there is no bits to lose.
5196 In the other path we know the value is positive in the range 2^63..2^64-1
5197 inclusive. (as for other input overflow happens and result is undefined)
5198 So we know that the most important bit set in mantissa corresponds to
5199 2^63. The subtraction of 2^63 should not generate any rounding as it
5200 simply clears out that bit. The rest is trivial. */
5202 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5203 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5204 fmode
= GET_MODE_WIDER_MODE (fmode
))
5205 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5206 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5207 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5210 REAL_VALUE_TYPE offset
;
5211 rtx limit
, lab1
, lab2
, insn
;
5213 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5214 real_2expN (&offset
, bitsize
- 1, fmode
);
5215 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5216 lab1
= gen_label_rtx ();
5217 lab2
= gen_label_rtx ();
5219 if (fmode
!= GET_MODE (from
))
5220 from
= convert_to_mode (fmode
, from
, 0);
5222 /* See if we need to do the subtraction. */
5223 do_pending_stack_adjust ();
5224 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5227 /* If not, do the signed "fix" and branch around fixup code. */
5228 expand_fix (to
, from
, 0);
5229 emit_jump_insn (gen_jump (lab2
));
5232 /* Otherwise, subtract 2**(N-1), convert to signed number,
5233 then add 2**(N-1). Do the addition using XOR since this
5234 will often generate better code. */
5236 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5237 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5238 expand_fix (to
, target
, 0);
5239 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5241 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5243 to
, 1, OPTAB_LIB_WIDEN
);
5246 emit_move_insn (to
, target
);
5250 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5252 /* Make a place for a REG_NOTE and add it. */
5253 insn
= emit_move_insn (to
, to
);
5254 set_dst_reg_note (insn
, REG_EQUAL
,
5255 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5263 /* We can't do it with an insn, so use a library call. But first ensure
5264 that the mode of TO is at least as wide as SImode, since those are the
5265 only library calls we know about. */
5267 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
5269 target
= gen_reg_rtx (SImode
);
5271 expand_fix (target
, from
, unsignedp
);
5279 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5280 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5281 gcc_assert (libfunc
);
5285 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5286 GET_MODE (to
), 1, from
,
5288 insns
= get_insns ();
5291 emit_libcall_block (insns
, target
, value
,
5292 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5293 GET_MODE (to
), from
));
5298 if (GET_MODE (to
) == GET_MODE (target
))
5299 emit_move_insn (to
, target
);
5301 convert_move (to
, target
, 0);
5305 /* Generate code to convert FROM or TO a fixed-point.
5306 If UINTP is true, either TO or FROM is an unsigned integer.
5307 If SATP is true, we need to saturate the result. */
5310 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5312 enum machine_mode to_mode
= GET_MODE (to
);
5313 enum machine_mode from_mode
= GET_MODE (from
);
5315 enum rtx_code this_code
;
5316 enum insn_code code
;
5320 if (to_mode
== from_mode
)
5322 emit_move_insn (to
, from
);
5328 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5329 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5333 tab
= satp
? satfract_optab
: fract_optab
;
5334 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5336 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5337 if (code
!= CODE_FOR_nothing
)
5339 emit_unop_insn (code
, to
, from
, this_code
);
5343 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5344 gcc_assert (libfunc
);
5347 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5348 1, from
, from_mode
);
5349 insns
= get_insns ();
5352 emit_libcall_block (insns
, to
, value
,
5353 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5356 /* Generate code to convert FROM to fixed point and store in TO. FROM
5357 must be floating point, TO must be signed. Use the conversion optab
5358 TAB to do the conversion. */
5361 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5363 enum insn_code icode
;
5365 enum machine_mode fmode
, imode
;
5367 /* We first try to find a pair of modes, one real and one integer, at
5368 least as wide as FROM and TO, respectively, in which we can open-code
5369 this conversion. If the integer mode is wider than the mode of TO,
5370 we can do the conversion either signed or unsigned. */
5372 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5373 fmode
= GET_MODE_WIDER_MODE (fmode
))
5374 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5375 imode
= GET_MODE_WIDER_MODE (imode
))
5377 icode
= convert_optab_handler (tab
, imode
, fmode
);
5378 if (icode
!= CODE_FOR_nothing
)
5380 rtx last
= get_last_insn ();
5381 if (fmode
!= GET_MODE (from
))
5382 from
= convert_to_mode (fmode
, from
, 0);
5384 if (imode
!= GET_MODE (to
))
5385 target
= gen_reg_rtx (imode
);
5387 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5389 delete_insns_since (last
);
5393 convert_move (to
, target
, 0);
5401 /* Report whether we have an instruction to perform the operation
5402 specified by CODE on operands of mode MODE. */
5404 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5406 return (code_to_optab (code
)
5407 && (optab_handler (code_to_optab (code
), mode
)
5408 != CODE_FOR_nothing
));
5411 /* Initialize the libfunc fields of an entire group of entries in some
5412 optab. Each entry is set equal to a string consisting of a leading
5413 pair of underscores followed by a generic operation name followed by
5414 a mode name (downshifted to lowercase) followed by a single character
5415 representing the number of operands for the given operation (which is
5416 usually one of the characters '2', '3', or '4').
5418 OPTABLE is the table in which libfunc fields are to be initialized.
5419 OPNAME is the generic (string) name of the operation.
5420 SUFFIX is the character which specifies the number of operands for
5421 the given generic operation.
5422 MODE is the mode to generate for.
5426 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5427 enum machine_mode mode
)
5429 unsigned opname_len
= strlen (opname
);
5430 const char *mname
= GET_MODE_NAME (mode
);
5431 unsigned mname_len
= strlen (mname
);
5432 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5433 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5434 char *libfunc_name
= XALLOCAVEC (char, len
);
5441 if (targetm
.libfunc_gnu_prefix
)
5448 for (q
= opname
; *q
; )
5450 for (q
= mname
; *q
; q
++)
5451 *p
++ = TOLOWER (*q
);
5455 set_optab_libfunc (optable
, mode
,
5456 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5459 /* Like gen_libfunc, but verify that integer operation is involved. */
5462 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5463 enum machine_mode mode
)
5465 int maxsize
= 2 * BITS_PER_WORD
;
5467 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5469 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5470 maxsize
= LONG_LONG_TYPE_SIZE
;
5471 if (GET_MODE_CLASS (mode
) != MODE_INT
5472 || mode
< word_mode
|| GET_MODE_BITSIZE (mode
) > maxsize
)
5474 gen_libfunc (optable
, opname
, suffix
, mode
);
5477 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5480 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5481 enum machine_mode mode
)
5485 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5486 gen_libfunc (optable
, opname
, suffix
, mode
);
5487 if (DECIMAL_FLOAT_MODE_P (mode
))
5489 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5490 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5491 depending on the low level floating format used. */
5492 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5493 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5494 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5498 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5501 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5502 enum machine_mode mode
)
5504 if (!ALL_FIXED_POINT_MODE_P (mode
))
5506 gen_libfunc (optable
, opname
, suffix
, mode
);
5509 /* Like gen_libfunc, but verify that signed fixed-point operation is
5513 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5514 enum machine_mode mode
)
5516 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5518 gen_libfunc (optable
, opname
, suffix
, mode
);
5521 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5525 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5526 enum machine_mode mode
)
5528 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5530 gen_libfunc (optable
, opname
, suffix
, mode
);
5533 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5536 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5537 enum machine_mode mode
)
5539 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5540 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5541 if (INTEGRAL_MODE_P (mode
))
5542 gen_int_libfunc (optable
, name
, suffix
, mode
);
5545 /* Like gen_libfunc, but verify that FP or INT operation is involved
5546 and add 'v' suffix for integer operation. */
5549 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5550 enum machine_mode mode
)
5552 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5553 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5554 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5556 int len
= strlen (name
);
5557 char *v_name
= XALLOCAVEC (char, len
+ 2);
5558 strcpy (v_name
, name
);
5560 v_name
[len
+ 1] = 0;
5561 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5565 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5569 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5570 enum machine_mode mode
)
5572 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5573 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5574 if (INTEGRAL_MODE_P (mode
))
5575 gen_int_libfunc (optable
, name
, suffix
, mode
);
5576 if (ALL_FIXED_POINT_MODE_P (mode
))
5577 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5580 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5584 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5585 enum machine_mode mode
)
5587 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5588 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5589 if (INTEGRAL_MODE_P (mode
))
5590 gen_int_libfunc (optable
, name
, suffix
, mode
);
5591 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5592 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5595 /* Like gen_libfunc, but verify that INT or FIXED operation is
5599 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5600 enum machine_mode mode
)
5602 if (INTEGRAL_MODE_P (mode
))
5603 gen_int_libfunc (optable
, name
, suffix
, mode
);
5604 if (ALL_FIXED_POINT_MODE_P (mode
))
5605 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5608 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5612 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5613 enum machine_mode mode
)
5615 if (INTEGRAL_MODE_P (mode
))
5616 gen_int_libfunc (optable
, name
, suffix
, mode
);
5617 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5618 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5621 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5625 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5626 enum machine_mode mode
)
5628 if (INTEGRAL_MODE_P (mode
))
5629 gen_int_libfunc (optable
, name
, suffix
, mode
);
5630 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5631 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5634 /* Initialize the libfunc fields of an entire group of entries of an
5635 inter-mode-class conversion optab. The string formation rules are
5636 similar to the ones for init_libfuncs, above, but instead of having
5637 a mode name and an operand count these functions have two mode names
5638 and no operand count. */
5641 gen_interclass_conv_libfunc (convert_optab tab
,
5643 enum machine_mode tmode
,
5644 enum machine_mode fmode
)
5646 size_t opname_len
= strlen (opname
);
5647 size_t mname_len
= 0;
5649 const char *fname
, *tname
;
5651 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5652 char *libfunc_name
, *suffix
;
5653 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5656 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5657 depends on which underlying decimal floating point format is used. */
5658 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5660 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5662 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5663 nondec_name
[0] = '_';
5664 nondec_name
[1] = '_';
5665 if (targetm
.libfunc_gnu_prefix
)
5667 nondec_name
[2] = 'g';
5668 nondec_name
[3] = 'n';
5669 nondec_name
[4] = 'u';
5670 nondec_name
[5] = '_';
5673 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5674 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5676 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5679 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5680 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5681 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5683 fname
= GET_MODE_NAME (fmode
);
5684 tname
= GET_MODE_NAME (tmode
);
5686 if (DECIMAL_FLOAT_MODE_P(fmode
) || DECIMAL_FLOAT_MODE_P(tmode
))
5688 libfunc_name
= dec_name
;
5689 suffix
= dec_suffix
;
5693 libfunc_name
= nondec_name
;
5694 suffix
= nondec_suffix
;
5698 for (q
= fname
; *q
; p
++, q
++)
5700 for (q
= tname
; *q
; p
++, q
++)
5705 set_conv_libfunc (tab
, tmode
, fmode
,
5706 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5709 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5710 int->fp conversion. */
5713 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5715 enum machine_mode tmode
,
5716 enum machine_mode fmode
)
5718 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5720 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5722 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5725 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5729 gen_ufloat_conv_libfunc (convert_optab tab
,
5730 const char *opname ATTRIBUTE_UNUSED
,
5731 enum machine_mode tmode
,
5732 enum machine_mode fmode
)
5734 if (DECIMAL_FLOAT_MODE_P (tmode
))
5735 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5737 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5740 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5741 fp->int conversion. */
5744 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5746 enum machine_mode tmode
,
5747 enum machine_mode fmode
)
5749 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5751 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5753 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5756 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5757 fp->int conversion with no decimal floating point involved. */
5760 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5762 enum machine_mode tmode
,
5763 enum machine_mode fmode
)
5765 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5767 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5769 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5772 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5773 The string formation rules are
5774 similar to the ones for init_libfunc, above. */
5777 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5778 enum machine_mode tmode
, enum machine_mode fmode
)
5780 size_t opname_len
= strlen (opname
);
5781 size_t mname_len
= 0;
5783 const char *fname
, *tname
;
5785 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5786 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5787 char *libfunc_name
, *suffix
;
5790 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5791 depends on which underlying decimal floating point format is used. */
5792 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5794 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5796 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5797 nondec_name
[0] = '_';
5798 nondec_name
[1] = '_';
5799 if (targetm
.libfunc_gnu_prefix
)
5801 nondec_name
[2] = 'g';
5802 nondec_name
[3] = 'n';
5803 nondec_name
[4] = 'u';
5804 nondec_name
[5] = '_';
5806 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5807 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5809 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5812 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5813 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5814 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5816 fname
= GET_MODE_NAME (fmode
);
5817 tname
= GET_MODE_NAME (tmode
);
5819 if (DECIMAL_FLOAT_MODE_P(fmode
) || DECIMAL_FLOAT_MODE_P(tmode
))
5821 libfunc_name
= dec_name
;
5822 suffix
= dec_suffix
;
5826 libfunc_name
= nondec_name
;
5827 suffix
= nondec_suffix
;
5831 for (q
= fname
; *q
; p
++, q
++)
5833 for (q
= tname
; *q
; p
++, q
++)
5839 set_conv_libfunc (tab
, tmode
, fmode
,
5840 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5843 /* Pick proper libcall for trunc_optab. We need to chose if we do
5844 truncation or extension and interclass or intraclass. */
5847 gen_trunc_conv_libfunc (convert_optab tab
,
5849 enum machine_mode tmode
,
5850 enum machine_mode fmode
)
5852 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5854 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5859 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5860 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5861 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5863 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5866 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5867 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5868 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5869 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5872 /* Pick proper libcall for extend_optab. We need to chose if we do
5873 truncation or extension and interclass or intraclass. */
5876 gen_extend_conv_libfunc (convert_optab tab
,
5877 const char *opname ATTRIBUTE_UNUSED
,
5878 enum machine_mode tmode
,
5879 enum machine_mode fmode
)
5881 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5883 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5888 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5889 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5890 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5892 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
5895 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5896 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5897 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5898 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5901 /* Pick proper libcall for fract_optab. We need to chose if we do
5902 interclass or intraclass. */
5905 gen_fract_conv_libfunc (convert_optab tab
,
5907 enum machine_mode tmode
,
5908 enum machine_mode fmode
)
5912 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
5915 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5916 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5918 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5921 /* Pick proper libcall for fractuns_optab. */
5924 gen_fractuns_conv_libfunc (convert_optab tab
,
5926 enum machine_mode tmode
,
5927 enum machine_mode fmode
)
5931 /* One mode must be a fixed-point mode, and the other must be an integer
5933 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
5934 || (ALL_FIXED_POINT_MODE_P (fmode
)
5935 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
5938 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5941 /* Pick proper libcall for satfract_optab. We need to chose if we do
5942 interclass or intraclass. */
5945 gen_satfract_conv_libfunc (convert_optab tab
,
5947 enum machine_mode tmode
,
5948 enum machine_mode fmode
)
5952 /* TMODE must be a fixed-point mode. */
5953 if (!ALL_FIXED_POINT_MODE_P (tmode
))
5956 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5957 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5959 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5962 /* Pick proper libcall for satfractuns_optab. */
5965 gen_satfractuns_conv_libfunc (convert_optab tab
,
5967 enum machine_mode tmode
,
5968 enum machine_mode fmode
)
5972 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
5973 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
5976 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5979 /* A table of previously-created libfuncs, hashed by name. */
5980 static GTY ((param_is (union tree_node
))) htab_t libfunc_decls
;
5982 /* Hashtable callbacks for libfunc_decls. */
5985 libfunc_decl_hash (const void *entry
)
5987 return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree
) entry
));
5991 libfunc_decl_eq (const void *entry1
, const void *entry2
)
5993 return DECL_NAME ((const_tree
) entry1
) == (const_tree
) entry2
;
5996 /* Build a decl for a libfunc named NAME. */
5999 build_libfunc_function (const char *name
)
6001 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6002 get_identifier (name
),
6003 build_function_type (integer_type_node
, NULL_TREE
));
6004 /* ??? We don't have any type information except for this is
6005 a function. Pretend this is "int foo()". */
6006 DECL_ARTIFICIAL (decl
) = 1;
6007 DECL_EXTERNAL (decl
) = 1;
6008 TREE_PUBLIC (decl
) = 1;
6009 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6011 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6012 are the flags assigned by targetm.encode_section_info. */
6013 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6019 init_one_libfunc (const char *name
)
6025 if (libfunc_decls
== NULL
)
6026 libfunc_decls
= htab_create_ggc (37, libfunc_decl_hash
,
6027 libfunc_decl_eq
, NULL
);
6029 /* See if we have already created a libfunc decl for this function. */
6030 id
= get_identifier (name
);
6031 hash
= IDENTIFIER_HASH_VALUE (id
);
6032 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, INSERT
);
6033 decl
= (tree
) *slot
;
6036 /* Create a new decl, so that it can be passed to
6037 targetm.encode_section_info. */
6038 decl
= build_libfunc_function (name
);
6041 return XEXP (DECL_RTL (decl
), 0);
6044 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6047 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6053 id
= get_identifier (name
);
6054 hash
= IDENTIFIER_HASH_VALUE (id
);
6055 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, NO_INSERT
);
6057 decl
= (tree
) *slot
;
6058 set_user_assembler_name (decl
, asmspec
);
6059 return XEXP (DECL_RTL (decl
), 0);
6062 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6063 MODE to NAME, which should be either 0 or a string constant. */
6065 set_optab_libfunc (optab op
, enum machine_mode mode
, const char *name
)
6068 struct libfunc_entry e
;
6069 struct libfunc_entry
**slot
;
6076 val
= init_one_libfunc (name
);
6079 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6081 *slot
= ggc_alloc_libfunc_entry ();
6083 (*slot
)->mode1
= mode
;
6084 (*slot
)->mode2
= VOIDmode
;
6085 (*slot
)->libfunc
= val
;
6088 /* Call this to reset the function entry for one conversion optab
6089 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6090 either 0 or a string constant. */
6092 set_conv_libfunc (convert_optab optab
, enum machine_mode tmode
,
6093 enum machine_mode fmode
, const char *name
)
6096 struct libfunc_entry e
;
6097 struct libfunc_entry
**slot
;
6104 val
= init_one_libfunc (name
);
6107 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6109 *slot
= ggc_alloc_libfunc_entry ();
6110 (*slot
)->op
= optab
;
6111 (*slot
)->mode1
= tmode
;
6112 (*slot
)->mode2
= fmode
;
6113 (*slot
)->libfunc
= val
;
6116 /* Call this to initialize the contents of the optabs
6117 appropriately for the current target machine. */
6123 htab_empty (libfunc_hash
);
6125 libfunc_hash
= htab_create_ggc (10, hash_libfunc
, eq_libfunc
, NULL
);
6127 /* Fill in the optabs with the insns we support. */
6130 /* The ffs function operates on `int'. Fall back on it if we do not
6131 have a libgcc2 function for that width. */
6132 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6133 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6136 /* Explicitly initialize the bswap libfuncs since we need them to be
6137 valid for things other than word_mode. */
6138 if (targetm
.libfunc_gnu_prefix
)
6140 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6141 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6145 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6146 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6149 /* Use cabs for double complex abs, since systems generally have cabs.
6150 Don't define any libcall for float complex, so that cabs will be used. */
6151 if (complex_double_type_node
)
6152 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6155 abort_libfunc
= init_one_libfunc ("abort");
6156 memcpy_libfunc
= init_one_libfunc ("memcpy");
6157 memmove_libfunc
= init_one_libfunc ("memmove");
6158 memcmp_libfunc
= init_one_libfunc ("memcmp");
6159 memset_libfunc
= init_one_libfunc ("memset");
6160 setbits_libfunc
= init_one_libfunc ("__setbits");
6162 #ifndef DONT_USE_BUILTIN_SETJMP
6163 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6164 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6166 setjmp_libfunc
= init_one_libfunc ("setjmp");
6167 longjmp_libfunc
= init_one_libfunc ("longjmp");
6169 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6170 unwind_sjlj_unregister_libfunc
6171 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6173 /* For function entry/exit instrumentation. */
6174 profile_function_entry_libfunc
6175 = init_one_libfunc ("__cyg_profile_func_enter");
6176 profile_function_exit_libfunc
6177 = init_one_libfunc ("__cyg_profile_func_exit");
6179 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6181 /* Allow the target to add more libcalls or rename some, etc. */
6182 targetm
.init_libfuncs ();
6185 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6186 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6189 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6191 enum machine_mode mode
;
6193 size_t len
= strlen (base
);
6196 gcc_assert (max
<= 8);
6197 gcc_assert (len
+ 3 < sizeof (buf
));
6199 memcpy (buf
, base
, len
);
6202 buf
[len
+ 2] = '\0';
6205 for (i
= 1; i
<= max
; i
*= 2)
6207 buf
[len
+ 1] = '0' + i
;
6208 set_optab_libfunc (tab
, mode
, buf
);
6209 mode
= GET_MODE_2XWIDER_MODE (mode
);
6214 init_sync_libfuncs (int max
)
6216 if (!flag_sync_libcalls
)
6219 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6220 "__sync_val_compare_and_swap", max
);
6221 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6222 "__sync_lock_test_and_set", max
);
6224 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6225 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6226 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6227 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6228 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6229 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6231 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6232 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6233 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6234 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6235 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6236 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6239 /* Print information about the current contents of the optabs on
6243 debug_optab_libfuncs (void)
6247 /* Dump the arithmetic optabs. */
6248 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6249 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6251 rtx l
= optab_libfunc ((optab
) i
, (enum machine_mode
) j
);
6254 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6255 fprintf (stderr
, "%s\t%s:\t%s\n",
6256 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6262 /* Dump the conversion optabs. */
6263 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6264 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6265 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6267 rtx l
= convert_optab_libfunc ((optab
) i
, (enum machine_mode
) j
,
6268 (enum machine_mode
) k
);
6271 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6272 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6273 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6282 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6283 CODE. Return 0 on failure. */
6286 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6288 enum machine_mode mode
= GET_MODE (op1
);
6289 enum insn_code icode
;
6293 if (mode
== VOIDmode
)
6296 icode
= optab_handler (ctrap_optab
, mode
);
6297 if (icode
== CODE_FOR_nothing
)
6300 /* Some targets only accept a zero trap code. */
6301 if (!insn_operand_matches (icode
, 3, tcode
))
6304 do_pending_stack_adjust ();
6306 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6311 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6314 /* If that failed, then give up. */
6322 insn
= get_insns ();
6327 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6328 or unsigned operation code. */
6330 static enum rtx_code
6331 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6343 code
= unsignedp
? LTU
: LT
;
6346 code
= unsignedp
? LEU
: LE
;
6349 code
= unsignedp
? GTU
: GT
;
6352 code
= unsignedp
? GEU
: GE
;
6355 case UNORDERED_EXPR
:
6386 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6387 unsigned operators. Do not generate compare instruction. */
6390 vector_compare_rtx (tree cond
, bool unsignedp
, enum insn_code icode
)
6392 struct expand_operand ops
[2];
6393 enum rtx_code rcode
;
6395 rtx rtx_op0
, rtx_op1
;
6397 /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer
6398 ensures that condition is a relational operation. */
6399 gcc_assert (COMPARISON_CLASS_P (cond
));
6401 rcode
= get_rtx_code (TREE_CODE (cond
), unsignedp
);
6402 t_op0
= TREE_OPERAND (cond
, 0);
6403 t_op1
= TREE_OPERAND (cond
, 1);
6405 /* Expand operands. */
6406 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6408 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6411 create_input_operand (&ops
[0], rtx_op0
, GET_MODE (rtx_op0
));
6412 create_input_operand (&ops
[1], rtx_op1
, GET_MODE (rtx_op1
));
6413 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6415 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6418 /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions
6419 of the CPU. SEL may be NULL, which stands for an unknown constant. */
6422 can_vec_perm_p (enum machine_mode mode
, bool variable
,
6423 const unsigned char *sel
)
6425 enum machine_mode qimode
;
6427 /* If the target doesn't implement a vector mode for the vector type,
6428 then no operations are supported. */
6429 if (!VECTOR_MODE_P (mode
))
6434 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6436 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6437 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6441 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6444 /* We allow fallback to a QI vector mode, and adjust the mask. */
6445 if (GET_MODE_INNER (mode
) == QImode
)
6447 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6448 if (!VECTOR_MODE_P (qimode
))
6451 /* ??? For completeness, we ought to check the QImode version of
6452 vec_perm_const_optab. But all users of this implicit lowering
6453 feature implement the variable vec_perm_optab. */
6454 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6457 /* In order to support the lowering of variable permutations,
6458 we need to support shifts and adds. */
6461 if (GET_MODE_UNIT_SIZE (mode
) > 2
6462 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6463 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6465 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6472 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6475 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6476 rtx v0
, rtx v1
, rtx sel
)
6478 enum machine_mode tmode
= GET_MODE (target
);
6479 enum machine_mode smode
= GET_MODE (sel
);
6480 struct expand_operand ops
[4];
6482 create_output_operand (&ops
[0], target
, tmode
);
6483 create_input_operand (&ops
[3], sel
, smode
);
6485 /* Make an effort to preserve v0 == v1. The target expander is able to
6486 rely on this to determine if we're permuting a single input operand. */
6487 if (rtx_equal_p (v0
, v1
))
6489 if (!insn_operand_matches (icode
, 1, v0
))
6490 v0
= force_reg (tmode
, v0
);
6491 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6492 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6494 create_fixed_operand (&ops
[1], v0
);
6495 create_fixed_operand (&ops
[2], v0
);
6499 create_input_operand (&ops
[1], v0
, tmode
);
6500 create_input_operand (&ops
[2], v1
, tmode
);
6503 if (maybe_expand_insn (icode
, 4, ops
))
6504 return ops
[0].value
;
6508 /* Generate instructions for vec_perm optab given its mode
6509 and three operands. */
6512 expand_vec_perm (enum machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6514 enum insn_code icode
;
6515 enum machine_mode qimode
;
6516 unsigned int i
, w
, e
, u
;
6517 rtx tmp
, sel_qi
= NULL
;
6520 if (!target
|| GET_MODE (target
) != mode
)
6521 target
= gen_reg_rtx (mode
);
6523 w
= GET_MODE_SIZE (mode
);
6524 e
= GET_MODE_NUNITS (mode
);
6525 u
= GET_MODE_UNIT_SIZE (mode
);
6527 /* Set QIMODE to a different vector mode with byte elements.
6528 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6530 if (GET_MODE_INNER (mode
) != QImode
)
6532 qimode
= mode_for_vector (QImode
, w
);
6533 if (!VECTOR_MODE_P (qimode
))
6537 /* If the input is a constant, expand it specially. */
6538 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6539 if (GET_CODE (sel
) == CONST_VECTOR
)
6541 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6542 if (icode
!= CODE_FOR_nothing
)
6544 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6549 /* Fall back to a constant byte-based permutation. */
6550 if (qimode
!= VOIDmode
)
6552 vec
= rtvec_alloc (w
);
6553 for (i
= 0; i
< e
; ++i
)
6555 unsigned int j
, this_e
;
6557 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6558 this_e
&= 2 * e
- 1;
6561 for (j
= 0; j
< u
; ++j
)
6562 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6564 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6566 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6567 if (icode
!= CODE_FOR_nothing
)
6569 tmp
= expand_vec_perm_1 (icode
, gen_lowpart (qimode
, target
),
6570 gen_lowpart (qimode
, v0
),
6571 gen_lowpart (qimode
, v1
), sel_qi
);
6573 return gen_lowpart (mode
, tmp
);
6578 /* Otherwise expand as a fully variable permuation. */
6579 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6580 if (icode
!= CODE_FOR_nothing
)
6582 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6587 /* As a special case to aid several targets, lower the element-based
6588 permutation to a byte-based permutation and try again. */
6589 if (qimode
== VOIDmode
)
6591 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6592 if (icode
== CODE_FOR_nothing
)
6597 /* Multiply each element by its byte size. */
6598 enum machine_mode selmode
= GET_MODE (sel
);
6600 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6601 sel
, 0, OPTAB_DIRECT
);
6603 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6604 GEN_INT (exact_log2 (u
)),
6605 sel
, 0, OPTAB_DIRECT
);
6606 gcc_assert (sel
!= NULL
);
6608 /* Broadcast the low byte each element into each of its bytes. */
6609 vec
= rtvec_alloc (w
);
6610 for (i
= 0; i
< w
; ++i
)
6612 int this_e
= i
/ u
* u
;
6613 if (BYTES_BIG_ENDIAN
)
6615 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6617 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6618 sel
= gen_lowpart (qimode
, sel
);
6619 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6620 gcc_assert (sel
!= NULL
);
6622 /* Add the byte offset to each byte element. */
6623 /* Note that the definition of the indicies here is memory ordering,
6624 so there should be no difference between big and little endian. */
6625 vec
= rtvec_alloc (w
);
6626 for (i
= 0; i
< w
; ++i
)
6627 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6628 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6629 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6630 sel
, 0, OPTAB_DIRECT
);
6631 gcc_assert (sel_qi
!= NULL
);
6634 tmp
= expand_vec_perm_1 (icode
, gen_lowpart (qimode
, target
),
6635 gen_lowpart (qimode
, v0
),
6636 gen_lowpart (qimode
, v1
), sel_qi
);
6638 tmp
= gen_lowpart (mode
, tmp
);
6642 /* Return insn code for a conditional operator with a comparison in
6643 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6645 static inline enum insn_code
6646 get_vcond_icode (enum machine_mode vmode
, enum machine_mode cmode
, bool uns
)
6648 enum insn_code icode
= CODE_FOR_nothing
;
6650 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6652 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6656 /* Return TRUE iff, appropriate vector insns are available
6657 for vector cond expr with vector type VALUE_TYPE and a comparison
6658 with operand vector types in CMP_OP_TYPE. */
6661 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6663 enum machine_mode value_mode
= TYPE_MODE (value_type
);
6664 enum machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6665 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6666 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6667 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6668 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6673 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6677 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6680 struct expand_operand ops
[6];
6681 enum insn_code icode
;
6682 rtx comparison
, rtx_op1
, rtx_op2
;
6683 enum machine_mode mode
= TYPE_MODE (vec_cond_type
);
6684 enum machine_mode cmp_op_mode
;
6687 gcc_assert (COMPARISON_CLASS_P (op0
));
6689 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (op0
, 0)));
6690 cmp_op_mode
= TYPE_MODE (TREE_TYPE (TREE_OPERAND (op0
, 0)));
6692 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6693 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6695 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6696 if (icode
== CODE_FOR_nothing
)
6699 comparison
= vector_compare_rtx (op0
, unsignedp
, icode
);
6700 rtx_op1
= expand_normal (op1
);
6701 rtx_op2
= expand_normal (op2
);
6703 create_output_operand (&ops
[0], target
, mode
);
6704 create_input_operand (&ops
[1], rtx_op1
, mode
);
6705 create_input_operand (&ops
[2], rtx_op2
, mode
);
6706 create_fixed_operand (&ops
[3], comparison
);
6707 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6708 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6709 expand_insn (icode
, 6, ops
);
6710 return ops
[0].value
;
6713 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6714 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6715 2 for even/odd widening, and 3 for hi/lo widening. */
6718 can_mult_highpart_p (enum machine_mode mode
, bool uns_p
)
6724 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6725 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6728 /* If the mode is an integral vector, synth from widening operations. */
6729 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6732 nunits
= GET_MODE_NUNITS (mode
);
6733 sel
= XALLOCAVEC (unsigned char, nunits
);
6735 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6736 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6738 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6739 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6741 for (i
= 0; i
< nunits
; ++i
)
6742 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6743 if (can_vec_perm_p (mode
, false, sel
))
6748 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6749 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6751 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6752 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6754 for (i
= 0; i
< nunits
; ++i
)
6755 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6756 if (can_vec_perm_p (mode
, false, sel
))
6764 /* Expand a highpart multiply. */
6767 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
6768 rtx target
, bool uns_p
)
6770 struct expand_operand eops
[3];
6771 enum insn_code icode
;
6772 int method
, i
, nunits
;
6773 enum machine_mode wmode
;
6778 method
= can_mult_highpart_p (mode
, uns_p
);
6784 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6785 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6788 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6789 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6792 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6793 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6794 if (BYTES_BIG_ENDIAN
)
6805 icode
= optab_handler (tab1
, mode
);
6806 nunits
= GET_MODE_NUNITS (mode
);
6807 wmode
= insn_data
[icode
].operand
[0].mode
;
6808 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6809 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6811 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6812 create_input_operand (&eops
[1], op0
, mode
);
6813 create_input_operand (&eops
[2], op1
, mode
);
6814 expand_insn (icode
, 3, eops
);
6815 m1
= gen_lowpart (mode
, eops
[0].value
);
6817 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6818 create_input_operand (&eops
[1], op0
, mode
);
6819 create_input_operand (&eops
[2], op1
, mode
);
6820 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6821 m2
= gen_lowpart (mode
, eops
[0].value
);
6823 v
= rtvec_alloc (nunits
);
6826 for (i
= 0; i
< nunits
; ++i
)
6827 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6828 + ((i
& 1) ? nunits
: 0));
6832 for (i
= 0; i
< nunits
; ++i
)
6833 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
6835 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
6837 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
6840 /* Return true if there is a compare_and_swap pattern. */
6843 can_compare_and_swap_p (enum machine_mode mode
, bool allow_libcall
)
6845 enum insn_code icode
;
6847 /* Check for __atomic_compare_and_swap. */
6848 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
6849 if (icode
!= CODE_FOR_nothing
)
6852 /* Check for __sync_compare_and_swap. */
6853 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
6854 if (icode
!= CODE_FOR_nothing
)
6856 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
6859 /* No inline compare and swap. */
6863 /* Return true if an atomic exchange can be performed. */
6866 can_atomic_exchange_p (enum machine_mode mode
, bool allow_libcall
)
6868 enum insn_code icode
;
6870 /* Check for __atomic_exchange. */
6871 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
6872 if (icode
!= CODE_FOR_nothing
)
6875 /* Don't check __sync_test_and_set, as on some platforms that
6876 has reduced functionality. Targets that really do support
6877 a proper exchange should simply be updated to the __atomics. */
6879 return can_compare_and_swap_p (mode
, allow_libcall
);
6883 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6887 find_cc_set (rtx x
, const_rtx pat
, void *data
)
6889 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
6890 && GET_CODE (pat
) == SET
)
6892 rtx
*p_cc_reg
= (rtx
*) data
;
6893 gcc_assert (!*p_cc_reg
);
6898 /* This is a helper function for the other atomic operations. This function
6899 emits a loop that contains SEQ that iterates until a compare-and-swap
6900 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6901 a set of instructions that takes a value from OLD_REG as an input and
6902 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6903 set to the current contents of MEM. After SEQ, a compare-and-swap will
6904 attempt to update MEM with NEW_REG. The function returns true when the
6905 loop was generated successfully. */
6908 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
6910 enum machine_mode mode
= GET_MODE (mem
);
6911 rtx label
, cmp_reg
, success
, oldval
;
6913 /* The loop we want to generate looks like
6919 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6923 Note that we only do the plain load from memory once. Subsequent
6924 iterations use the value loaded by the compare-and-swap pattern. */
6926 label
= gen_label_rtx ();
6927 cmp_reg
= gen_reg_rtx (mode
);
6929 emit_move_insn (cmp_reg
, mem
);
6931 emit_move_insn (old_reg
, cmp_reg
);
6937 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
6938 new_reg
, false, MEMMODEL_SEQ_CST
,
6942 if (oldval
!= cmp_reg
)
6943 emit_move_insn (cmp_reg
, oldval
);
6945 /* ??? Mark this jump predicted not taken? */
6946 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
6947 GET_MODE (success
), 1, label
);
6952 /* This function tries to emit an atomic_exchange intruction. VAL is written
6953 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6954 using TARGET if possible. */
6957 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
6959 enum machine_mode mode
= GET_MODE (mem
);
6960 enum insn_code icode
;
6962 /* If the target supports the exchange directly, great. */
6963 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
6964 if (icode
!= CODE_FOR_nothing
)
6966 struct expand_operand ops
[4];
6968 create_output_operand (&ops
[0], target
, mode
);
6969 create_fixed_operand (&ops
[1], mem
);
6970 /* VAL may have been promoted to a wider mode. Shrink it if so. */
6971 create_convert_operand_to (&ops
[2], val
, mode
, true);
6972 create_integer_operand (&ops
[3], model
);
6973 if (maybe_expand_insn (icode
, 4, ops
))
6974 return ops
[0].value
;
6980 /* This function tries to implement an atomic exchange operation using
6981 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6982 The previous contents of *MEM are returned, using TARGET if possible.
6983 Since this instructionn is an acquire barrier only, stronger memory
6984 models may require additional barriers to be emitted. */
6987 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
6988 enum memmodel model
)
6990 enum machine_mode mode
= GET_MODE (mem
);
6991 enum insn_code icode
;
6992 rtx last_insn
= get_last_insn ();
6994 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
6996 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6997 exists, and the memory model is stronger than acquire, add a release
6998 barrier before the instruction. */
7000 if (model
== MEMMODEL_SEQ_CST
7001 || model
== MEMMODEL_RELEASE
7002 || model
== MEMMODEL_ACQ_REL
)
7003 expand_mem_thread_fence (model
);
7005 if (icode
!= CODE_FOR_nothing
)
7007 struct expand_operand ops
[3];
7008 create_output_operand (&ops
[0], target
, mode
);
7009 create_fixed_operand (&ops
[1], mem
);
7010 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7011 create_convert_operand_to (&ops
[2], val
, mode
, true);
7012 if (maybe_expand_insn (icode
, 3, ops
))
7013 return ops
[0].value
;
7016 /* If an external test-and-set libcall is provided, use that instead of
7017 any external compare-and-swap that we might get from the compare-and-
7018 swap-loop expansion later. */
7019 if (!can_compare_and_swap_p (mode
, false))
7021 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7022 if (libfunc
!= NULL
)
7026 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7027 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7028 mode
, 2, addr
, ptr_mode
,
7033 /* If the test_and_set can't be emitted, eliminate any barrier that might
7034 have been emitted. */
7035 delete_insns_since (last_insn
);
7039 /* This function tries to implement an atomic exchange operation using a
7040 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7041 *MEM are returned, using TARGET if possible. No memory model is required
7042 since a compare_and_swap loop is seq-cst. */
7045 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7047 enum machine_mode mode
= GET_MODE (mem
);
7049 if (can_compare_and_swap_p (mode
, true))
7051 if (!target
|| !register_operand (target
, mode
))
7052 target
= gen_reg_rtx (mode
);
7053 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
7054 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
7055 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7062 /* This function tries to implement an atomic test-and-set operation
7063 using the atomic_test_and_set instruction pattern. A boolean value
7064 is returned from the operation, using TARGET if possible. */
7066 #ifndef HAVE_atomic_test_and_set
7067 #define HAVE_atomic_test_and_set 0
7068 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7072 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7074 enum machine_mode pat_bool_mode
;
7075 struct expand_operand ops
[3];
7077 if (!HAVE_atomic_test_and_set
)
7080 /* While we always get QImode from __atomic_test_and_set, we get
7081 other memory modes from __sync_lock_test_and_set. Note that we
7082 use no endian adjustment here. This matches the 4.6 behavior
7083 in the Sparc backend. */
7085 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7086 if (GET_MODE (mem
) != QImode
)
7087 mem
= adjust_address_nv (mem
, QImode
, 0);
7089 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7090 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7091 create_fixed_operand (&ops
[1], mem
);
7092 create_integer_operand (&ops
[2], model
);
7094 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7095 return ops
[0].value
;
7099 /* This function expands the legacy _sync_lock test_and_set operation which is
7100 generally an atomic exchange. Some limited targets only allow the
7101 constant 1 to be stored. This is an ACQUIRE operation.
7103 TARGET is an optional place to stick the return value.
7104 MEM is where VAL is stored. */
7107 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7111 /* Try an atomic_exchange first. */
7112 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7116 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7120 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7124 /* If there are no other options, try atomic_test_and_set if the value
7125 being stored is 1. */
7126 if (val
== const1_rtx
)
7127 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_ACQUIRE
);
7132 /* This function expands the atomic test_and_set operation:
7133 atomically store a boolean TRUE into MEM and return the previous value.
7135 MEMMODEL is the memory model variant to use.
7136 TARGET is an optional place to stick the return value. */
7139 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7141 enum machine_mode mode
= GET_MODE (mem
);
7142 rtx ret
, trueval
, subtarget
;
7144 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7148 /* Be binary compatible with non-default settings of trueval, and different
7149 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7150 another only has atomic-exchange. */
7151 if (targetm
.atomic_test_and_set_trueval
== 1)
7153 trueval
= const1_rtx
;
7154 subtarget
= target
? target
: gen_reg_rtx (mode
);
7158 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7159 subtarget
= gen_reg_rtx (mode
);
7162 /* Try the atomic-exchange optab... */
7163 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7165 /* ... then an atomic-compare-and-swap loop ... */
7167 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7169 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7171 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7173 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7174 things with the value 1. Thus we try again without trueval. */
7175 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7176 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7178 /* Failing all else, assume a single threaded environment and simply
7179 perform the operation. */
7182 emit_move_insn (subtarget
, mem
);
7183 emit_move_insn (mem
, trueval
);
7187 /* Recall that have to return a boolean value; rectify if trueval
7188 is not exactly one. */
7189 if (targetm
.atomic_test_and_set_trueval
!= 1)
7190 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7195 /* This function expands the atomic exchange operation:
7196 atomically store VAL in MEM and return the previous value in MEM.
7198 MEMMODEL is the memory model variant to use.
7199 TARGET is an optional place to stick the return value. */
7202 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7206 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7208 /* Next try a compare-and-swap loop for the exchange. */
7210 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7215 /* This function expands the atomic compare exchange operation:
7217 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7218 *PTARGET_OVAL is an optional place to store the old value from memory.
7219 Both target parameters may be NULL to indicate that we do not care about
7220 that return value. Both target parameters are updated on success to
7221 the actual location of the corresponding result.
7223 MEMMODEL is the memory model variant to use.
7225 The return value of the function is true for success. */
7228 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7229 rtx mem
, rtx expected
, rtx desired
,
7230 bool is_weak
, enum memmodel succ_model
,
7231 enum memmodel fail_model
)
7233 enum machine_mode mode
= GET_MODE (mem
);
7234 struct expand_operand ops
[8];
7235 enum insn_code icode
;
7236 rtx target_oval
, target_bool
= NULL_RTX
;
7239 /* Load expected into a register for the compare and swap. */
7240 if (MEM_P (expected
))
7241 expected
= copy_to_reg (expected
);
7243 /* Make sure we always have some place to put the return oldval.
7244 Further, make sure that place is distinct from the input expected,
7245 just in case we need that path down below. */
7246 if (ptarget_oval
== NULL
7247 || (target_oval
= *ptarget_oval
) == NULL
7248 || reg_overlap_mentioned_p (expected
, target_oval
))
7249 target_oval
= gen_reg_rtx (mode
);
7251 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7252 if (icode
!= CODE_FOR_nothing
)
7254 enum machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7256 /* Make sure we always have a place for the bool operand. */
7257 if (ptarget_bool
== NULL
7258 || (target_bool
= *ptarget_bool
) == NULL
7259 || GET_MODE (target_bool
) != bool_mode
)
7260 target_bool
= gen_reg_rtx (bool_mode
);
7262 /* Emit the compare_and_swap. */
7263 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7264 create_output_operand (&ops
[1], target_oval
, mode
);
7265 create_fixed_operand (&ops
[2], mem
);
7266 create_convert_operand_to (&ops
[3], expected
, mode
, true);
7267 create_convert_operand_to (&ops
[4], desired
, mode
, true);
7268 create_integer_operand (&ops
[5], is_weak
);
7269 create_integer_operand (&ops
[6], succ_model
);
7270 create_integer_operand (&ops
[7], fail_model
);
7271 expand_insn (icode
, 8, ops
);
7273 /* Return success/failure. */
7274 target_bool
= ops
[0].value
;
7275 target_oval
= ops
[1].value
;
7279 /* Otherwise fall back to the original __sync_val_compare_and_swap
7280 which is always seq-cst. */
7281 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7282 if (icode
!= CODE_FOR_nothing
)
7286 create_output_operand (&ops
[0], target_oval
, mode
);
7287 create_fixed_operand (&ops
[1], mem
);
7288 create_convert_operand_to (&ops
[2], expected
, mode
, true);
7289 create_convert_operand_to (&ops
[3], desired
, mode
, true);
7290 if (!maybe_expand_insn (icode
, 4, ops
))
7293 target_oval
= ops
[0].value
;
7295 /* If the caller isn't interested in the boolean return value,
7296 skip the computation of it. */
7297 if (ptarget_bool
== NULL
)
7300 /* Otherwise, work out if the compare-and-swap succeeded. */
7302 if (have_insn_for (COMPARE
, CCmode
))
7303 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7306 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7307 const0_rtx
, VOIDmode
, 0, 1);
7310 goto success_bool_from_val
;
7313 /* Also check for library support for __sync_val_compare_and_swap. */
7314 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7315 if (libfunc
!= NULL
)
7317 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7318 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7319 mode
, 3, addr
, ptr_mode
,
7320 expected
, mode
, desired
, mode
);
7322 /* Compute the boolean return value only if requested. */
7324 goto success_bool_from_val
;
7332 success_bool_from_val
:
7333 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7334 expected
, VOIDmode
, 1, 1);
7336 /* Make sure that the oval output winds up where the caller asked. */
7338 *ptarget_oval
= target_oval
;
7340 *ptarget_bool
= target_bool
;
7344 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7347 expand_asm_memory_barrier (void)
7351 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7352 rtvec_alloc (0), rtvec_alloc (0),
7353 rtvec_alloc (0), UNKNOWN_LOCATION
);
7354 MEM_VOLATILE_P (asm_op
) = 1;
7356 clob
= gen_rtx_SCRATCH (VOIDmode
);
7357 clob
= gen_rtx_MEM (BLKmode
, clob
);
7358 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7360 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7363 /* This routine will either emit the mem_thread_fence pattern or issue a
7364 sync_synchronize to generate a fence for memory model MEMMODEL. */
7366 #ifndef HAVE_mem_thread_fence
7367 # define HAVE_mem_thread_fence 0
7368 # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
7370 #ifndef HAVE_memory_barrier
7371 # define HAVE_memory_barrier 0
7372 # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
7376 expand_mem_thread_fence (enum memmodel model
)
7378 if (HAVE_mem_thread_fence
)
7379 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7380 else if (model
!= MEMMODEL_RELAXED
)
7382 if (HAVE_memory_barrier
)
7383 emit_insn (gen_memory_barrier ());
7384 else if (synchronize_libfunc
!= NULL_RTX
)
7385 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7387 expand_asm_memory_barrier ();
7391 /* This routine will either emit the mem_signal_fence pattern or issue a
7392 sync_synchronize to generate a fence for memory model MEMMODEL. */
7394 #ifndef HAVE_mem_signal_fence
7395 # define HAVE_mem_signal_fence 0
7396 # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
7400 expand_mem_signal_fence (enum memmodel model
)
7402 if (HAVE_mem_signal_fence
)
7403 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7404 else if (model
!= MEMMODEL_RELAXED
)
7406 /* By default targets are coherent between a thread and the signal
7407 handler running on the same thread. Thus this really becomes a
7408 compiler barrier, in that stores must not be sunk past
7409 (or raised above) a given point. */
7410 expand_asm_memory_barrier ();
7414 /* This function expands the atomic load operation:
7415 return the atomically loaded value in MEM.
7417 MEMMODEL is the memory model variant to use.
7418 TARGET is an option place to stick the return value. */
7421 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7423 enum machine_mode mode
= GET_MODE (mem
);
7424 enum insn_code icode
;
7426 /* If the target supports the load directly, great. */
7427 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7428 if (icode
!= CODE_FOR_nothing
)
7430 struct expand_operand ops
[3];
7432 create_output_operand (&ops
[0], target
, mode
);
7433 create_fixed_operand (&ops
[1], mem
);
7434 create_integer_operand (&ops
[2], model
);
7435 if (maybe_expand_insn (icode
, 3, ops
))
7436 return ops
[0].value
;
7439 /* If the size of the object is greater than word size on this target,
7440 then we assume that a load will not be atomic. */
7441 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7443 /* Issue val = compare_and_swap (mem, 0, 0).
7444 This may cause the occasional harmless store of 0 when the value is
7445 already 0, but it seems to be OK according to the standards guys. */
7446 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7447 const0_rtx
, false, model
, model
))
7450 /* Otherwise there is no atomic load, leave the library call. */
7454 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7455 if (!target
|| target
== const0_rtx
)
7456 target
= gen_reg_rtx (mode
);
7458 /* Emit the appropriate barrier before the load. */
7459 expand_mem_thread_fence (model
);
7461 emit_move_insn (target
, mem
);
7463 /* For SEQ_CST, also emit a barrier after the load. */
7464 if (model
== MEMMODEL_SEQ_CST
)
7465 expand_mem_thread_fence (model
);
7470 /* This function expands the atomic store operation:
7471 Atomically store VAL in MEM.
7472 MEMMODEL is the memory model variant to use.
7473 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7474 function returns const0_rtx if a pattern was emitted. */
7477 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7479 enum machine_mode mode
= GET_MODE (mem
);
7480 enum insn_code icode
;
7481 struct expand_operand ops
[3];
7483 /* If the target supports the store directly, great. */
7484 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7485 if (icode
!= CODE_FOR_nothing
)
7487 create_fixed_operand (&ops
[0], mem
);
7488 create_input_operand (&ops
[1], val
, mode
);
7489 create_integer_operand (&ops
[2], model
);
7490 if (maybe_expand_insn (icode
, 3, ops
))
7494 /* If using __sync_lock_release is a viable alternative, try it. */
7497 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7498 if (icode
!= CODE_FOR_nothing
)
7500 create_fixed_operand (&ops
[0], mem
);
7501 create_input_operand (&ops
[1], const0_rtx
, mode
);
7502 if (maybe_expand_insn (icode
, 2, ops
))
7504 /* lock_release is only a release barrier. */
7505 if (model
== MEMMODEL_SEQ_CST
)
7506 expand_mem_thread_fence (model
);
7512 /* If the size of the object is greater than word size on this target,
7513 a default store will not be atomic, Try a mem_exchange and throw away
7514 the result. If that doesn't work, don't do anything. */
7515 if (GET_MODE_PRECISION(mode
) > BITS_PER_WORD
)
7517 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7519 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7526 /* If there is no mem_store, default to a move with barriers */
7527 if (model
== MEMMODEL_SEQ_CST
|| model
== MEMMODEL_RELEASE
)
7528 expand_mem_thread_fence (model
);
7530 emit_move_insn (mem
, val
);
7532 /* For SEQ_CST, also emit a barrier after the load. */
7533 if (model
== MEMMODEL_SEQ_CST
)
7534 expand_mem_thread_fence (model
);
7540 /* Structure containing the pointers and values required to process the
7541 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7543 struct atomic_op_functions
7545 direct_optab mem_fetch_before
;
7546 direct_optab mem_fetch_after
;
7547 direct_optab mem_no_result
;
7550 direct_optab no_result
;
7551 enum rtx_code reverse_code
;
7555 /* Fill in structure pointed to by OP with the various optab entries for an
7556 operation of type CODE. */
7559 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7561 gcc_assert (op
!= NULL
);
7563 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7564 in the source code during compilation, and the optab entries are not
7565 computable until runtime. Fill in the values at runtime. */
7569 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7570 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7571 op
->mem_no_result
= atomic_add_optab
;
7572 op
->fetch_before
= sync_old_add_optab
;
7573 op
->fetch_after
= sync_new_add_optab
;
7574 op
->no_result
= sync_add_optab
;
7575 op
->reverse_code
= MINUS
;
7578 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7579 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7580 op
->mem_no_result
= atomic_sub_optab
;
7581 op
->fetch_before
= sync_old_sub_optab
;
7582 op
->fetch_after
= sync_new_sub_optab
;
7583 op
->no_result
= sync_sub_optab
;
7584 op
->reverse_code
= PLUS
;
7587 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7588 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7589 op
->mem_no_result
= atomic_xor_optab
;
7590 op
->fetch_before
= sync_old_xor_optab
;
7591 op
->fetch_after
= sync_new_xor_optab
;
7592 op
->no_result
= sync_xor_optab
;
7593 op
->reverse_code
= XOR
;
7596 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7597 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7598 op
->mem_no_result
= atomic_and_optab
;
7599 op
->fetch_before
= sync_old_and_optab
;
7600 op
->fetch_after
= sync_new_and_optab
;
7601 op
->no_result
= sync_and_optab
;
7602 op
->reverse_code
= UNKNOWN
;
7605 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7606 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7607 op
->mem_no_result
= atomic_or_optab
;
7608 op
->fetch_before
= sync_old_ior_optab
;
7609 op
->fetch_after
= sync_new_ior_optab
;
7610 op
->no_result
= sync_ior_optab
;
7611 op
->reverse_code
= UNKNOWN
;
7614 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7615 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7616 op
->mem_no_result
= atomic_nand_optab
;
7617 op
->fetch_before
= sync_old_nand_optab
;
7618 op
->fetch_after
= sync_new_nand_optab
;
7619 op
->no_result
= sync_nand_optab
;
7620 op
->reverse_code
= UNKNOWN
;
7627 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7628 using memory order MODEL. If AFTER is true the operation needs to return
7629 the value of *MEM after the operation, otherwise the previous value.
7630 TARGET is an optional place to place the result. The result is unused if
7632 Return the result if there is a better sequence, otherwise NULL_RTX. */
7635 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7636 enum memmodel model
, bool after
)
7638 /* If the value is prefetched, or not used, it may be possible to replace
7639 the sequence with a native exchange operation. */
7640 if (!after
|| target
== const0_rtx
)
7642 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7643 if (code
== AND
&& val
== const0_rtx
)
7645 if (target
== const0_rtx
)
7646 target
= gen_reg_rtx (GET_MODE (mem
));
7647 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7650 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7651 if (code
== IOR
&& val
== constm1_rtx
)
7653 if (target
== const0_rtx
)
7654 target
= gen_reg_rtx (GET_MODE (mem
));
7655 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7662 /* Try to emit an instruction for a specific operation varaition.
7663 OPTAB contains the OP functions.
7664 TARGET is an optional place to return the result. const0_rtx means unused.
7665 MEM is the memory location to operate on.
7666 VAL is the value to use in the operation.
7667 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7668 MODEL is the memory model, if used.
7669 AFTER is true if the returned result is the value after the operation. */
7672 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7673 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7675 enum machine_mode mode
= GET_MODE (mem
);
7676 struct expand_operand ops
[4];
7677 enum insn_code icode
;
7681 /* Check to see if there is a result returned. */
7682 if (target
== const0_rtx
)
7686 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7687 create_integer_operand (&ops
[2], model
);
7692 icode
= direct_optab_handler (optab
->no_result
, mode
);
7696 /* Otherwise, we need to generate a result. */
7701 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7702 : optab
->mem_fetch_before
, mode
);
7703 create_integer_operand (&ops
[3], model
);
7708 icode
= optab_handler (after
? optab
->fetch_after
7709 : optab
->fetch_before
, mode
);
7712 create_output_operand (&ops
[op_counter
++], target
, mode
);
7714 if (icode
== CODE_FOR_nothing
)
7717 create_fixed_operand (&ops
[op_counter
++], mem
);
7718 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7719 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7721 if (maybe_expand_insn (icode
, num_ops
, ops
))
7722 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7728 /* This function expands an atomic fetch_OP or OP_fetch operation:
7729 TARGET is an option place to stick the return value. const0_rtx indicates
7730 the result is unused.
7731 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7732 CODE is the operation being performed (OP)
7733 MEMMODEL is the memory model variant to use.
7734 AFTER is true to return the result of the operation (OP_fetch).
7735 AFTER is false to return the value before the operation (fetch_OP). */
7737 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7738 enum memmodel model
, bool after
)
7740 enum machine_mode mode
= GET_MODE (mem
);
7741 struct atomic_op_functions optab
;
7743 bool unused_result
= (target
== const0_rtx
);
7745 get_atomic_op_for_code (&optab
, code
);
7747 /* Check to see if there are any better instructions. */
7748 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7752 /* Check for the case where the result isn't used and try those patterns. */
7755 /* Try the memory model variant first. */
7756 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7760 /* Next try the old style withuot a memory model. */
7761 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7765 /* There is no no-result pattern, so try patterns with a result. */
7769 /* Try the __atomic version. */
7770 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7774 /* Try the older __sync version. */
7775 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7779 /* If the fetch value can be calculated from the other variation of fetch,
7780 try that operation. */
7781 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7783 /* Try the __atomic version, then the older __sync version. */
7784 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7786 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7790 /* If the result isn't used, no need to do compensation code. */
7794 /* Issue compensation code. Fetch_after == fetch_before OP val.
7795 Fetch_before == after REVERSE_OP val. */
7797 code
= optab
.reverse_code
;
7800 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
7801 true, OPTAB_LIB_WIDEN
);
7802 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
7805 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7806 true, OPTAB_LIB_WIDEN
);
7811 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7812 if (!can_compare_and_swap_p (mode
, false))
7816 enum rtx_code orig_code
= code
;
7818 libfunc
= optab_libfunc (after
? optab
.fetch_after
7819 : optab
.fetch_before
, mode
);
7821 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
7825 code
= optab
.reverse_code
;
7826 libfunc
= optab_libfunc (after
? optab
.fetch_before
7827 : optab
.fetch_after
, mode
);
7829 if (libfunc
!= NULL
)
7831 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7832 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
7833 2, addr
, ptr_mode
, val
, mode
);
7835 if (!unused_result
&& fixup
)
7836 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7837 true, OPTAB_LIB_WIDEN
);
7841 /* We need the original code for any further attempts. */
7845 /* If nothing else has succeeded, default to a compare and swap loop. */
7846 if (can_compare_and_swap_p (mode
, true))
7849 rtx t0
= gen_reg_rtx (mode
), t1
;
7853 /* If the result is used, get a register for it. */
7856 if (!target
|| !register_operand (target
, mode
))
7857 target
= gen_reg_rtx (mode
);
7858 /* If fetch_before, copy the value now. */
7860 emit_move_insn (target
, t0
);
7863 target
= const0_rtx
;
7868 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
7869 true, OPTAB_LIB_WIDEN
);
7870 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
7873 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
7876 /* For after, copy the value now. */
7877 if (!unused_result
&& after
)
7878 emit_move_insn (target
, t1
);
7879 insn
= get_insns ();
7882 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
7889 /* Return true if OPERAND is suitable for operand number OPNO of
7890 instruction ICODE. */
7893 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
7895 return (!insn_data
[(int) icode
].operand
[opno
].predicate
7896 || (insn_data
[(int) icode
].operand
[opno
].predicate
7897 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
7900 /* TARGET is a target of a multiword operation that we are going to
7901 implement as a series of word-mode operations. Return true if
7902 TARGET is suitable for this purpose. */
7905 valid_multiword_target_p (rtx target
)
7907 enum machine_mode mode
;
7910 mode
= GET_MODE (target
);
7911 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
7912 if (!validate_subreg (word_mode
, mode
, target
, i
))
7917 /* Like maybe_legitimize_operand, but do not change the code of the
7918 current rtx value. */
7921 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
7922 struct expand_operand
*op
)
7924 /* See if the operand matches in its current form. */
7925 if (insn_operand_matches (icode
, opno
, op
->value
))
7928 /* If the operand is a memory whose address has no side effects,
7929 try forcing the address into a non-virtual pseudo register.
7930 The check for side effects is important because copy_to_mode_reg
7931 cannot handle things like auto-modified addresses. */
7932 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
7937 addr
= XEXP (mem
, 0);
7938 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
7939 && !side_effects_p (addr
))
7942 enum machine_mode mode
;
7944 last
= get_last_insn ();
7945 mode
= get_address_mode (mem
);
7946 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
7947 if (insn_operand_matches (icode
, opno
, mem
))
7952 delete_insns_since (last
);
7959 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7960 on success, storing the new operand value back in OP. */
7963 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
7964 struct expand_operand
*op
)
7966 enum machine_mode mode
, imode
;
7967 bool old_volatile_ok
, result
;
7973 old_volatile_ok
= volatile_ok
;
7975 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
7976 volatile_ok
= old_volatile_ok
;
7980 gcc_assert (mode
!= VOIDmode
);
7982 && op
->value
!= const0_rtx
7983 && GET_MODE (op
->value
) == mode
7984 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
7987 op
->value
= gen_reg_rtx (mode
);
7992 gcc_assert (mode
!= VOIDmode
);
7993 gcc_assert (GET_MODE (op
->value
) == VOIDmode
7994 || GET_MODE (op
->value
) == mode
);
7995 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
7998 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8001 case EXPAND_CONVERT_TO
:
8002 gcc_assert (mode
!= VOIDmode
);
8003 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8006 case EXPAND_CONVERT_FROM
:
8007 if (GET_MODE (op
->value
) != VOIDmode
)
8008 mode
= GET_MODE (op
->value
);
8010 /* The caller must tell us what mode this value has. */
8011 gcc_assert (mode
!= VOIDmode
);
8013 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8014 if (imode
!= VOIDmode
&& imode
!= mode
)
8016 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8021 case EXPAND_ADDRESS
:
8022 gcc_assert (mode
!= VOIDmode
);
8023 op
->value
= convert_memory_address (mode
, op
->value
);
8026 case EXPAND_INTEGER
:
8027 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8028 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8032 return insn_operand_matches (icode
, opno
, op
->value
);
8035 /* Make OP describe an input operand that should have the same value
8036 as VALUE, after any mode conversion that the target might request.
8037 TYPE is the type of VALUE. */
8040 create_convert_operand_from_type (struct expand_operand
*op
,
8041 rtx value
, tree type
)
8043 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8044 TYPE_UNSIGNED (type
));
8047 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8048 of instruction ICODE. Return true on success, leaving the new operand
8049 values in the OPS themselves. Emit no code on failure. */
8052 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8053 unsigned int nops
, struct expand_operand
*ops
)
8058 last
= get_last_insn ();
8059 for (i
= 0; i
< nops
; i
++)
8060 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8062 delete_insns_since (last
);
8068 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8069 as its operands. Return the instruction pattern on success,
8070 and emit any necessary set-up code. Return null and emit no
8074 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8075 struct expand_operand
*ops
)
8077 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8078 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8084 return GEN_FCN (icode
) (ops
[0].value
);
8086 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8088 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8090 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8093 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8094 ops
[3].value
, ops
[4].value
);
8096 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8097 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8099 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8100 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8103 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8104 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8105 ops
[6].value
, ops
[7].value
);
8110 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8111 as its operands. Return true on success and emit no code on failure. */
8114 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8115 struct expand_operand
*ops
)
8117 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8126 /* Like maybe_expand_insn, but for jumps. */
8129 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8130 struct expand_operand
*ops
)
8132 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8135 emit_jump_insn (pat
);
8141 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8145 expand_insn (enum insn_code icode
, unsigned int nops
,
8146 struct expand_operand
*ops
)
8148 if (!maybe_expand_insn (icode
, nops
, ops
))
8152 /* Like expand_insn, but for jumps. */
8155 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8156 struct expand_operand
*ops
)
8158 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8162 #include "gt-optabs.h"