| blob | 77d54e5bcb72363c12f752caec064aebdcdfadeb |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
93 #ifndef CHECK_STACK_LIMIT
94 #define CHECK_STACK_LIMIT (-1)
95 #endif
97 /* Return index of given mode in mult and division cost tables. */
98 #define MODE_INDEX(mode) \
99 ((mode) == QImode ? 0 \
100 : (mode) == HImode ? 1 \
101 : (mode) == SImode ? 2 \
102 : (mode) == DImode ? 3 \
103 : 4)
105 /* Processor costs (relative to an add) */
106 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
107 #define COSTS_N_BYTES(N) ((N) * 2)
109 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
118 const
141 in QImode, HImode and SImode.
142 Relative to reg-reg move (2). */
146 in SFmode, DFmode and XFmode */
148 in SFmode, DFmode and XFmode */
151 in SImode and DImode */
153 in SImode and DImode */
156 in SImode, DImode and TImode */
158 in SImode, DImode and TImode */
171 ix86_size_memcpy,
172 ix86_size_memset,
184 };
186 /* Processor costs (relative to an add) */
189 DUMMY_STRINGOP_ALGS};
192 DUMMY_STRINGOP_ALGS};
194 static const
217 in QImode, HImode and SImode.
218 Relative to reg-reg move (2). */
222 in SFmode, DFmode and XFmode */
224 in SFmode, DFmode and XFmode */
227 in SImode and DImode */
229 in SImode and DImode */
232 in SImode, DImode and TImode */
234 in SImode, DImode and TImode */
247 i386_memcpy,
248 i386_memset,
260 };
264 DUMMY_STRINGOP_ALGS};
267 DUMMY_STRINGOP_ALGS};
269 static const
292 in QImode, HImode and SImode.
293 Relative to reg-reg move (2). */
297 in SFmode, DFmode and XFmode */
299 in SFmode, DFmode and XFmode */
302 in SImode and DImode */
304 in SImode and DImode */
307 in SImode, DImode and TImode */
309 in SImode, DImode and TImode */
312 shared for code and data, so 4kB is
313 not really precise. */
324 i486_memcpy,
325 i486_memset,
337 };
341 DUMMY_STRINGOP_ALGS};
344 DUMMY_STRINGOP_ALGS};
346 static const
369 in QImode, HImode and SImode.
370 Relative to reg-reg move (2). */
374 in SFmode, DFmode and XFmode */
376 in SFmode, DFmode and XFmode */
379 in SImode and DImode */
381 in SImode and DImode */
384 in SImode, DImode and TImode */
386 in SImode, DImode and TImode */
399 pentium_memcpy,
400 pentium_memset,
412 };
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
415 (we ensure the alignment). For small blocks inline loop is still a
416 noticeable win, for bigger blocks either rep movsl or rep movsb is
417 way to go. Rep movsb has apparently more expensive startup time in CPU,
418 but after 4K the difference is down in the noise. */
423 DUMMY_STRINGOP_ALGS};
428 DUMMY_STRINGOP_ALGS};
429 static const
452 in QImode, HImode and SImode.
453 Relative to reg-reg move (2). */
457 in SFmode, DFmode and XFmode */
459 in SFmode, DFmode and XFmode */
462 in SImode and DImode */
464 in SImode and DImode */
467 in SImode, DImode and TImode */
469 in SImode, DImode and TImode */
482 pentiumpro_memcpy,
483 pentiumpro_memset,
495 };
499 DUMMY_STRINGOP_ALGS};
502 DUMMY_STRINGOP_ALGS};
503 static const
526 in QImode, HImode and SImode.
527 Relative to reg-reg move (2). */
531 in SFmode, DFmode and XFmode */
533 in SFmode, DFmode and XFmode */
537 in SImode and DImode */
539 in SImode and DImode */
542 in SImode, DImode and TImode */
544 in SImode, DImode and TImode */
557 geode_memcpy,
558 geode_memset,
570 };
574 DUMMY_STRINGOP_ALGS};
577 DUMMY_STRINGOP_ALGS};
578 static const
601 in QImode, HImode and SImode.
602 Relative to reg-reg move (2). */
606 in SFmode, DFmode and XFmode */
608 in SFmode, DFmode and XFmode */
611 in SImode and DImode */
613 in SImode and DImode */
616 in SImode, DImode and TImode */
618 in SImode, DImode and TImode */
622 have integrated l2 cache, but
623 optimizing for k6 is not important
624 enough to worry about that. */
634 k6_memcpy,
635 k6_memset,
647 };
649 /* For some reason, Athlon deals better with REP prefix (relative to loops)
650 compared to K8. Alignment becomes important after 8 bytes for memcpy and
651 128 bytes for memset. */
654 DUMMY_STRINGOP_ALGS};
657 DUMMY_STRINGOP_ALGS};
658 static const
681 in QImode, HImode and SImode.
682 Relative to reg-reg move (2). */
686 in SFmode, DFmode and XFmode */
688 in SFmode, DFmode and XFmode */
691 in SImode and DImode */
693 in SImode and DImode */
696 in SImode, DImode and TImode */
698 in SImode, DImode and TImode */
711 athlon_memcpy,
712 athlon_memset,
724 };
726 /* K8 has optimized REP instruction for medium sized blocks, but for very
727 small blocks it is better to use loop. For large blocks, libcall can
728 do nontemporary accesses and beat inline considerably. */
739 static const
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
767 in SFmode, DFmode and XFmode */
769 in SFmode, DFmode and XFmode */
772 in SImode and DImode */
774 in SImode and DImode */
777 in SImode, DImode and TImode */
779 in SImode, DImode and TImode */
784 /* New AMD processors never drop prefetches; if they cannot be performed
785 immediately, they are queued. We set number of simultaneous prefetches
786 to a large constant to reflect this (it probably is not a good idea not
787 to limit number of prefetches at all, as their execution also takes some
788 time). */
798 k8_memcpy,
799 k8_memset,
811 };
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
848 in QImode, HImode and SImode.
849 Relative to reg-reg move (2). */
853 in SFmode, DFmode and XFmode */
855 in SFmode, DFmode and XFmode */
858 in SImode and DImode */
860 in SImode and DImode */
863 in SImode, DImode and TImode */
865 in SImode, DImode and TImode */
867 /* On K8:
868 MOVD reg64, xmmreg Double FSTORE 4
869 MOVD reg32, xmmreg Double FSTORE 4
870 On AMDFAM10:
871 MOVD reg64, xmmreg Double FADD 3
872 1/1 1/1
873 MOVD reg32, xmmreg Double FADD 3
874 1/1 1/1 */
878 /* New AMD processors never drop prefetches; if they cannot be performed
879 immediately, they are queued. We set number of simultaneous prefetches
880 to a large constant to reflect this (it probably is not a good idea not
881 to limit number of prefetches at all, as their execution also takes some
882 time). */
892 amdfam10_memcpy,
893 amdfam10_memset,
905 };
907 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
908 very small blocks it is better to use loop. For large blocks, libcall
909 can do nontemporary accesses and beat inline considerably. */
943 in QImode, HImode and SImode.
944 Relative to reg-reg move (2). */
948 in SFmode, DFmode and XFmode */
950 in SFmode, DFmode and XFmode */
953 in SImode and DImode */
955 in SImode and DImode */
958 in SImode, DImode and TImode */
960 in SImode, DImode and TImode */
962 /* On K8:
963 MOVD reg64, xmmreg Double FSTORE 4
964 MOVD reg32, xmmreg Double FSTORE 4
965 On AMDFAM10:
966 MOVD reg64, xmmreg Double FADD 3
967 1/1 1/1
968 MOVD reg32, xmmreg Double FADD 3
969 1/1 1/1 */
973 /* New AMD processors never drop prefetches; if they cannot be performed
974 immediately, they are queued. We set number of simultaneous prefetches
975 to a large constant to reflect this (it probably is not a good idea not
976 to limit number of prefetches at all, as their execution also takes some
977 time). */
987 bdver1_memcpy,
988 bdver1_memset,
1000 };
1002 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1003 very small blocks it is better to use loop. For large blocks, libcall
1004 can do nontemporary accesses and beat inline considerably. */
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1058 /* On K8:
1059 MOVD reg64, xmmreg Double FSTORE 4
1060 MOVD reg32, xmmreg Double FSTORE 4
1061 On AMDFAM10:
1062 MOVD reg64, xmmreg Double FADD 3
1063 1/1 1/1
1064 MOVD reg32, xmmreg Double FADD 3
1065 1/1 1/1 */
1069 /* New AMD processors never drop prefetches; if they cannot be performed
1070 immediately, they are queued. We set number of simultaneous prefetches
1071 to a large constant to reflect this (it probably is not a good idea not
1072 to limit number of prefetches at all, as their execution also takes some
1073 time). */
1083 bdver2_memcpy,
1084 bdver2_memset,
1096 };
1099 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1100 very small blocks it is better to use loop. For large blocks, libcall
1101 can do nontemporary accesses and beat inline considerably. */
1134 in QImode, HImode and SImode.
1135 Relative to reg-reg move (2). */
1139 in SFmode, DFmode and XFmode */
1141 in SFmode, DFmode and XFmode */
1144 in SImode and DImode */
1146 in SImode and DImode */
1149 in SImode, DImode and TImode */
1151 in SImode, DImode and TImode */
1156 /* New AMD processors never drop prefetches; if they cannot be performed
1157 immediately, they are queued. We set number of simultaneous prefetches
1158 to a large constant to reflect this (it probably is not a good idea not
1159 to limit number of prefetches at all, as their execution also takes some
1160 time). */
1170 bdver3_memcpy,
1171 bdver3_memset,
1183 };
1185 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1186 very small blocks it is better to use loop. For large blocks, libcall
1187 can do nontemporary accesses and beat inline considerably. */
1220 in QImode, HImode and SImode.
1221 Relative to reg-reg move (2). */
1225 in SFmode, DFmode and XFmode */
1227 in SFmode, DFmode and XFmode */
1230 in SImode and DImode */
1232 in SImode and DImode */
1235 in SImode, DImode and TImode */
1237 in SImode, DImode and TImode */
1242 /* New AMD processors never drop prefetches; if they cannot be performed
1243 immediately, they are queued. We set number of simultaneous prefetches
1244 to a large constant to reflect this (it probably is not a good idea not
1245 to limit number of prefetches at all, as their execution also takes some
1246 time). */
1256 bdver4_memcpy,
1257 bdver4_memset,
1269 };
1271 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1272 very small blocks it is better to use loop. For large blocks, libcall can
1273 do nontemporary accesses and beat inline considerably. */
1306 in QImode, HImode and SImode.
1307 Relative to reg-reg move (2). */
1311 in SFmode, DFmode and XFmode */
1313 in SFmode, DFmode and XFmode */
1316 in SImode and DImode */
1318 in SImode and DImode */
1321 in SImode, DImode and TImode */
1323 in SImode, DImode and TImode */
1325 /* On K8:
1326 MOVD reg64, xmmreg Double FSTORE 4
1327 MOVD reg32, xmmreg Double FSTORE 4
1328 On AMDFAM10:
1329 MOVD reg64, xmmreg Double FADD 3
1330 1/1 1/1
1331 MOVD reg32, xmmreg Double FADD 3
1332 1/1 1/1 */
1345 btver1_memcpy,
1346 btver1_memset,
1358 };
1392 in QImode, HImode and SImode.
1393 Relative to reg-reg move (2). */
1397 in SFmode, DFmode and XFmode */
1399 in SFmode, DFmode and XFmode */
1402 in SImode and DImode */
1404 in SImode and DImode */
1407 in SImode, DImode and TImode */
1409 in SImode, DImode and TImode */
1411 /* On K8:
1412 MOVD reg64, xmmreg Double FSTORE 4
1413 MOVD reg32, xmmreg Double FSTORE 4
1414 On AMDFAM10:
1415 MOVD reg64, xmmreg Double FADD 3
1416 1/1 1/1
1417 MOVD reg32, xmmreg Double FADD 3
1418 1/1 1/1 */
1430 btver2_memcpy,
1431 btver2_memset,
1443 };
1447 DUMMY_STRINGOP_ALGS};
1451 DUMMY_STRINGOP_ALGS};
1453 static const
1476 in QImode, HImode and SImode.
1477 Relative to reg-reg move (2). */
1481 in SFmode, DFmode and XFmode */
1483 in SFmode, DFmode and XFmode */
1486 in SImode and DImode */
1488 in SImode and DImode */
1491 in SImode, DImode and TImode */
1493 in SImode, DImode and TImode */
1506 pentium4_memcpy,
1507 pentium4_memset,
1519 };
1532 static const
1555 in QImode, HImode and SImode.
1556 Relative to reg-reg move (2). */
1560 in SFmode, DFmode and XFmode */
1562 in SFmode, DFmode and XFmode */
1565 in SImode and DImode */
1567 in SImode and DImode */
1570 in SImode, DImode and TImode */
1572 in SImode, DImode and TImode */
1585 nocona_memcpy,
1586 nocona_memset,
1598 };
1609 static const
1632 in QImode, HImode and SImode.
1633 Relative to reg-reg move (2). */
1637 in SFmode, DFmode and XFmode */
1639 in SFmode, DFmode and XFmode */
1642 in SImode and DImode */
1644 in SImode and DImode */
1647 in SImode, DImode and TImode */
1649 in SImode, DImode and TImode */
1662 atom_memcpy,
1663 atom_memset,
1675 };
1686 static const
1709 in QImode, HImode and SImode.
1710 Relative to reg-reg move (2). */
1714 in SFmode, DFmode and XFmode */
1716 in SFmode, DFmode and XFmode */
1719 in SImode and DImode */
1721 in SImode and DImode */
1724 in SImode, DImode and TImode */
1726 in SImode, DImode and TImode */
1739 slm_memcpy,
1740 slm_memset,
1752 };
1763 static const
1786 in QImode, HImode and SImode.
1787 Relative to reg-reg move (2). */
1791 in SFmode, DFmode and XFmode */
1793 in SFmode, DFmode and XFmode */
1796 in SImode and DImode */
1798 in SImode and DImode */
1801 in SImode, DImode and TImode */
1803 in SImode, DImode and TImode */
1816 intel_memcpy,
1817 intel_memset,
1829 };
1831 /* Generic should produce code tuned for Core-i7 (and newer chips)
1832 and btver1 (and newer chips). */
1844 static const
1847 /* On all chips taken into consideration lea is 2 cycles and more. With
1848 this cost however our current implementation of synth_mult results in
1849 use of unnecessary temporary registers causing regression on several
1850 SPECfp benchmarks. */
1871 in QImode, HImode and SImode.
1872 Relative to reg-reg move (2). */
1876 in SFmode, DFmode and XFmode */
1878 in SFmode, DFmode and XFmode */
1881 in SImode and DImode */
1883 in SImode and DImode */
1886 in SImode, DImode and TImode */
1888 in SImode, DImode and TImode */
1894 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1895 value is increased to perhaps more appropriate value of 5. */
1903 generic_memcpy,
1904 generic_memset,
1916 };
1918 /* core_cost should produce code tuned for Core familly of CPUs. */
1931 static const
1934 /* On all chips taken into consideration lea is 2 cycles and more. With
1935 this cost however our current implementation of synth_mult results in
1936 use of unnecessary temporary registers causing regression on several
1937 SPECfp benchmarks. */
1958 in QImode, HImode and SImode.
1959 Relative to reg-reg move (2). */
1963 in SFmode, DFmode and XFmode */
1965 in SFmode, DFmode and XFmode */
1968 in SImode and DImode */
1970 in SImode and DImode */
1973 in SImode, DImode and TImode */
1975 in SImode, DImode and TImode */
1981 /* FIXME perhaps more appropriate value is 5. */
1989 core_memcpy,
1990 core_memset,
2002 };
2005 /* Set by -mtune. */
2008 /* Set by -mtune or -Os. */
2011 /* Processor feature/optimization bitmasks. */
2012 #define m_386 (1<<PROCESSOR_I386)
2013 #define m_486 (1<<PROCESSOR_I486)
2014 #define m_PENT (1<<PROCESSOR_PENTIUM)
2015 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2016 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2017 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2018 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2019 #define m_CORE2 (1<<PROCESSOR_CORE2)
2020 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2021 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2022 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2023 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2024 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2025 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2026 #define m_INTEL (1<<PROCESSOR_INTEL)
2028 #define m_GEODE (1<<PROCESSOR_GEODE)
2029 #define m_K6 (1<<PROCESSOR_K6)
2030 #define m_K6_GEODE (m_K6 | m_GEODE)
2031 #define m_K8 (1<<PROCESSOR_K8)
2032 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2033 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2034 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2035 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2036 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2037 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2038 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2039 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2040 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2041 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2042 #define m_BTVER (m_BTVER1 | m_BTVER2)
2043 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2045 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2048 #undef DEF_TUNE
2049 #define DEF_TUNE(tune, name, selector) name,
2051 #undef DEF_TUNE
2052 };
2054 /* Feature tests against the various tunings. */
2057 /* Feature tests against the various tunings used to create ix86_tune_features
2058 based on the processor mask. */
2060 #undef DEF_TUNE
2061 #define DEF_TUNE(tune, name, selector) selector,
2063 #undef DEF_TUNE
2064 };
2066 /* Feature tests against the various architecture variations. */
2069 /* Feature tests against the various architecture variations, used to create
2070 ix86_arch_features based on the processor mask. */
2072 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2075 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2078 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2081 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2084 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2086 };
2088 /* In case the average insn count for single function invocation is
2089 lower than this constant, emit fast (but longer) prologue and
2090 epilogue code. */
2091 #define FAST_PROLOGUE_INSN_COUNT 20
2093 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2098 /* Array of the smallest class containing reg number REGNO, indexed by
2099 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2102 {
2103 /* ax, dx, cx, bx */
2105 /* si, di, bp, sp */
2107 /* FP registers */
2110 /* arg pointer */
2111 NON_Q_REGS,
2112 /* flags, fpsr, fpcr, frame */
2114 /* SSE registers */
2117 /* MMX registers */
2120 /* REX registers */
2123 /* SSE REX registers */
2126 /* AVX-512 SSE registers */
2131 /* Mask registers. */
2134 };
2136 /* The "default" register map used in 32bit mode. */
2139 {
2150 };
2152 /* The "default" register map used in 64bit mode. */
2155 {
2166 };
2168 /* Define the register numbers to be used in Dwarf debugging information.
2169 The SVR4 reference port C compiler uses the following register numbers
2170 in its Dwarf output code:
2171 0 for %eax (gcc regno = 0)
2172 1 for %ecx (gcc regno = 2)
2173 2 for %edx (gcc regno = 1)
2174 3 for %ebx (gcc regno = 3)
2175 4 for %esp (gcc regno = 7)
2176 5 for %ebp (gcc regno = 6)
2177 6 for %esi (gcc regno = 4)
2178 7 for %edi (gcc regno = 5)
2179 The following three DWARF register numbers are never generated by
2180 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2181 believes these numbers have these meanings.
2182 8 for %eip (no gcc equivalent)
2183 9 for %eflags (gcc regno = 17)
2184 10 for %trapno (no gcc equivalent)
2185 It is not at all clear how we should number the FP stack registers
2186 for the x86 architecture. If the version of SDB on x86/svr4 were
2187 a bit less brain dead with respect to floating-point then we would
2188 have a precedent to follow with respect to DWARF register numbers
2189 for x86 FP registers, but the SDB on x86/svr4 is so completely
2190 broken with respect to FP registers that it is hardly worth thinking
2191 of it as something to strive for compatibility with.
2192 The version of x86/svr4 SDB I have at the moment does (partially)
2193 seem to believe that DWARF register number 11 is associated with
2194 the x86 register %st(0), but that's about all. Higher DWARF
2195 register numbers don't seem to be associated with anything in
2196 particular, and even for DWARF regno 11, SDB only seems to under-
2197 stand that it should say that a variable lives in %st(0) (when
2198 asked via an `=' command) if we said it was in DWARF regno 11,
2199 but SDB still prints garbage when asked for the value of the
2200 variable in question (via a `/' command).
2201 (Also note that the labels SDB prints for various FP stack regs
2202 when doing an `x' command are all wrong.)
2203 Note that these problems generally don't affect the native SVR4
2204 C compiler because it doesn't allow the use of -O with -g and
2205 because when it is *not* optimizing, it allocates a memory
2206 location for each floating-point variable, and the memory
2207 location is what gets described in the DWARF AT_location
2208 attribute for the variable in question.
2209 Regardless of the severe mental illness of the x86/svr4 SDB, we
2210 do something sensible here and we use the following DWARF
2211 register numbers. Note that these are all stack-top-relative
2212 numbers.
2213 11 for %st(0) (gcc regno = 8)
2214 12 for %st(1) (gcc regno = 9)
2215 13 for %st(2) (gcc regno = 10)
2216 14 for %st(3) (gcc regno = 11)
2217 15 for %st(4) (gcc regno = 12)
2218 16 for %st(5) (gcc regno = 13)
2219 17 for %st(6) (gcc regno = 14)
2220 18 for %st(7) (gcc regno = 15)
2221 */
2223 {
2234 };
2236 /* Define parameter passing and return registers. */
2239 {
2241 };
2244 {
2246 };
2249 {
2251 };
2253 /* Additional registers that are clobbered by SYSV calls. */
2256 {
2261 };
2263 /* Define the structure for the machine field in struct function. */
2268 rtx rtl;
2270 };
2272 /* Structure describing stack frame layout.
2273 Stack grows downward:
2275 [arguments]
2276 <- ARG_POINTER
2277 saved pc
2279 saved static chain if ix86_static_chain_on_stack
2281 saved frame pointer if frame_pointer_needed
2282 <- HARD_FRAME_POINTER
2283 [saved regs]
2284 <- regs_save_offset
2285 [padding0]
2287 [saved SSE regs]
2288 <- sse_regs_save_offset
2289 [padding1] |
2290 | <- FRAME_POINTER
2291 [va_arg registers] |
2292 |
2293 [frame] |
2294 |
2295 [padding2] | = to_allocate
2296 <- STACK_POINTER
2297 */
2298 struct ix86_frame
2299 {
2306 /* The offsets relative to ARG_POINTER. */
2307 HOST_WIDE_INT frame_pointer_offset;
2308 HOST_WIDE_INT hard_frame_pointer_offset;
2309 HOST_WIDE_INT stack_pointer_offset;
2310 HOST_WIDE_INT hfp_save_offset;
2311 HOST_WIDE_INT reg_save_offset;
2312 HOST_WIDE_INT sse_reg_save_offset;
2314 /* When save_regs_using_mov is set, emit prologue using
2315 move instead of push instructions. */
2317 };
2319 /* Which cpu are we scheduling for. */
2322 /* Which cpu are we optimizing for. */
2325 /* Which instruction set architecture to use. */
2328 /* True if processor has SSE prefetch instruction. */
2331 /* -mstackrealign option */
2348 /* Preferred alignment for stack boundary in bits. */
2351 /* Alignment for incoming stack boundary in bits specified at
2352 command line. */
2355 /* Default alignment for incoming stack boundary in bits. */
2358 /* Alignment for incoming stack boundary in bits. */
2361 /* Calling abi specific va_list type nodes. */
2365 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2369 /* Fence to use after loop using movnt. */
2370 tree x86_mfence;
2372 /* Register class used for passing given 64bit part of the argument.
2373 These represent classes as documented by the PS ABI, with the exception
2374 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2375 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2377 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2378 whenever possible (upper half does contain padding). */
2379 enum x86_64_reg_class
2380 {
2381 X86_64_NO_CLASS,
2382 X86_64_INTEGER_CLASS,
2383 X86_64_INTEGERSI_CLASS,
2384 X86_64_SSE_CLASS,
2385 X86_64_SSESF_CLASS,
2386 X86_64_SSEDF_CLASS,
2387 X86_64_SSEUP_CLASS,
2388 X86_64_X87_CLASS,
2389 X86_64_X87UP_CLASS,
2390 X86_64_COMPLEX_X87_CLASS,
2391 X86_64_MEMORY_CLASS
2392 };
2394 #define MAX_CLASSES 8
2396 /* Table of constants used by fldpi, fldln2, etc.... */
2400 \f
2405 const_tree);
2417 enum ix86_function_specific_strings
2418 {
2419 IX86_FUNCTION_SPECIFIC_ARCH,
2420 IX86_FUNCTION_SPECIFIC_TUNE,
2421 IX86_FUNCTION_SPECIFIC_MAX
2422 };
2443 \f
2444 #ifndef SUBTARGET32_DEFAULT_CPU
2446 #endif
2448 /* Whether -mtune= or -march= were specified */
2452 /* Vectorization library interface and handlers. */
2458 /* Processor target table, indexed by processor number */
2459 struct ptt
2460 {
2468 };
2470 /* This table must be in sync with enum processor_type in i386.h. */
2472 {
2498 };
2499 \f
2500 static unsigned int
2502 {
2505 /* vzeroupper instructions are inserted immediately after reload to
2506 account for possible spills from 256bit registers. The pass
2507 reuses mode switching infrastructure by re-running mode insertion
2508 pass, so disable entities that have already been processed. */
2514 /* Call optimize_mode_switching. */
2517 }
2522 {
2533 };
2536 {
2540 {}
2542 /* opt_pass methods: */
2544 {
2546 }
2549 {
2551 }
2557 rtl_opt_pass *
2559 {
2561 }
2563 /* Return true if a red-zone is in use. */
2567 {
2569 }
2570 \f
2571 /* Return a string that documents the current -m options. The caller is
2572 responsible for freeing the string. */
2578 {
2579 struct ix86_target_opts
2580 {
2583 };
2585 /* This table is ordered so that options like -msse4.2 that imply
2586 preceding options while match those first. */
2588 {
2633 };
2635 /* Flag options. */
2637 {
2666 };
2683 /* Add -march= option. */
2685 {
2688 }
2690 /* Add -mtune= option. */
2692 {
2695 }
2697 /* Add -m32/-m64/-mx32. */
2699 {
2702 else
2704 isa &= ~ (OPTION_MASK_ISA_64BIT
2705 | OPTION_MASK_ABI_64
2707 }
2708 else
2712 /* Pick out the options in isa options. */
2714 {
2716 {
2719 }
2720 }
2723 {
2726 isa);
2727 }
2729 /* Add flag options. */
2731 {
2733 {
2736 }
2737 }
2740 {
2743 }
2745 /* Add -fpmath= option. */
2747 {
2750 {
2765 }
2766 }
2768 /* Any options? */
2774 /* Size the string. */
2778 {
2783 }
2785 /* Build the string. */
2790 {
2797 {
2799 line_len++;
2802 {
2806 }
2807 }
2811 {
2815 }
2816 }
2822 }
2824 /* Return true, if profiling code should be emitted before
2825 prologue. Otherwise it returns false.
2826 Note: For x86 with "hotfix" it is sorried. */
2827 static bool
2829 {
2831 }
2833 /* Function that is callable from the debugger to print the current
2834 options. */
2835 void ATTRIBUTE_UNUSED
2837 {
2843 {
2846 }
2847 else
2851 }
2854 #define DEF_ENUM
2855 #define DEF_ALG(alg, name) #name,
2857 #undef DEF_ENUM
2858 #undef DEF_ALG
2859 };
2861 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2862 The string is of the following form (or comma separated list of it):
2864 strategy_alg:max_size:[align|noalign]
2866 where the full size range for the strategy is either [0, max_size] or
2867 [min_size, max_size], in which min_size is the max_size + 1 of the
2868 preceding range. The last size range must have max_size == -1.
2870 Examples:
2872 1.
2873 -mmemcpy-strategy=libcall:-1:noalign
2875 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2878 2.
2879 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2881 This is to tell the compiler to use the following strategy for memset
2882 1) when the expected size is between [1, 16], use rep_8byte strategy;
2883 2) when the size is between [17, 2048], use vector_loop;
2884 3) when the size is > 2048, use libcall. */
2886 struct stringop_size_range
2887 {
2889 stringop_alg alg;
2891 };
2893 static void
2895 {
2903 else
2908 do
2909 {
2919 {
2923 }
2926 {
2930 }
2937 {
2939 alg_name,
2942 }
2950 else
2951 {
2955 }
2956 n++;
2958 }
2962 {
2967 }
2970 {
2974 }
2976 /* Now override the default algs array. */
2978 {
2984 }
2985 }
2987 \f
2988 /* parse -mtune-ctrl= option. When DUMP is true,
2989 print the features that are explicitly set. */
2991 static void
2993 {
3001 do
3002 {
3009 {
3010 curr_feature_string++;
3012 }
3014 {
3016 {
3022 }
3023 }
3028 }
3031 }
3033 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3034 processor type. */
3036 static void
3038 {
3043 {
3046 else
3048 }
3051 {
3056 }
3059 }
3062 /* Override various settings based on options. If MAIN_ARGS_P, the
3063 options are from the command line, otherwise they are from
3064 attributes. */
3066 static void
3070 {
3078 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3079 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3080 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3081 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3082 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3083 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3084 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3085 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3086 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3087 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3088 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3089 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3090 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3091 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3092 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3093 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3094 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3095 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3096 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3097 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3098 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3099 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3100 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3101 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3102 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3103 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3104 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3105 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3106 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3107 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3108 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3109 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3110 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3111 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3112 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3113 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3114 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3115 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3116 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3117 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3118 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3119 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3120 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3121 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3122 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3123 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3124 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3125 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3126 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3128 #define PTA_CORE2 \
3129 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3130 | PTA_CX16 | PTA_FXSR)
3131 #define PTA_NEHALEM \
3132 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3133 #define PTA_WESTMERE \
3134 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3135 #define PTA_SANDYBRIDGE \
3136 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3137 #define PTA_IVYBRIDGE \
3138 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3139 #define PTA_HASWELL \
3140 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3141 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3142 #define PTA_BROADWELL \
3143 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3144 #define PTA_BONNELL \
3145 (PTA_CORE2 | PTA_MOVBE)
3146 #define PTA_SILVERMONT \
3147 (PTA_WESTMERE | PTA_MOVBE)
3149 /* if this reaches 64, need to widen struct pta flags below */
3151 static struct pta
3152 {
3157 }
3159 {
3193 PTA_SANDYBRIDGE},
3195 PTA_SANDYBRIDGE},
3197 PTA_IVYBRIDGE},
3199 PTA_IVYBRIDGE},
3289 PTA_64BIT
3291 };
3293 /* -mrecip options. */
3294 static struct
3295 {
3298 }
3300 {
3307 };
3311 /* Set up prefix/suffix so the error messages refer to either the command
3312 line argument, or the attribute(target). */
3314 {
3318 }
3319 else
3320 {
3324 }
3326 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3327 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3330 #ifdef TARGET_BI_ARCH
3331 else
3332 {
3333 #if TARGET_BI_ARCH == 1
3334 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3335 is on and OPTION_MASK_ABI_X32 is off. We turn off
3336 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3337 -mx32. */
3340 #else
3341 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3342 on and OPTION_MASK_ABI_64 is off. We turn off
3343 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3344 -m64. */
3347 #endif
3348 }
3349 #endif
3352 {
3353 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3354 OPTION_MASK_ABI_64 for TARGET_X32. */
3357 }
3360 | OPTION_MASK_ABI_X32
3363 {
3364 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3365 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3368 }
3370 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3371 SUBTARGET_OVERRIDE_OPTIONS;
3372 #endif
3374 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3375 SUBSUBTARGET_OVERRIDE_OPTIONS;
3376 #endif
3378 /* -fPIC is the default for x86_64. */
3382 /* Need to check -mtune=generic first. */
3384 {
3385 /* As special support for cross compilers we read -mtune=native
3386 as -mtune=generic. With native compilers we won't see the
3387 -mtune=native, as it was changed by the driver. */
3389 {
3391 }
3396 }
3397 else
3398 {
3402 {
3403 opts->x_ix86_tune_string
3406 }
3408 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3409 or defaulted. We need to use a sensible tune option. */
3411 {
3413 }
3414 }
3418 {
3419 /* rep; movq isn't available in 32-bit code. */
3422 }
3425 opts->x_ix86_arch_string
3428 else
3432 {
3440 }
3441 else
3448 /* For targets using ms ABI enable ms-extensions, if not
3449 explicit turned off. For non-ms ABI we turn off this
3450 option. */
3455 {
3457 {
3501 {
3504 }
3512 }
3513 }
3514 else
3515 {
3516 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3517 use of rip-relative addressing. This eliminates fixups that
3518 would otherwise be needed if this object is to be placed in a
3519 DLL, and is essentially just as efficient as direct addressing. */
3525 else
3527 }
3529 {
3532 }
3540 {
3543 /* Default cpu tuning to the architecture. */
3697 }
3715 {
3719 {
3721 {
3723 {
3731 }
3732 else
3735 }
3736 }
3737 /* Intel CPUs have always interpreted SSE prefetch instructions as
3738 NOPs; so, we can enable SSE prefetch instructions even when
3739 -mtune (rather than -march) points us to a processor that has them.
3740 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3741 higher processors. */
3746 }
3754 #ifndef USE_IX86_FRAME_POINTER
3755 #define USE_IX86_FRAME_POINTER 0
3756 #endif
3758 #ifndef USE_X86_64_FRAME_POINTER
3759 #define USE_X86_64_FRAME_POINTER 0
3760 #endif
3762 /* Set the default values for switches whose default depends on TARGET_64BIT
3763 in case they weren't overwritten by command line options. */
3765 {
3773 opts->x_flag_unwind_tables
3777 }
3778 else
3779 {
3781 opts->x_flag_omit_frame_pointer
3787 }
3792 else
3795 /* Arrange to set up i386_stack_locals for all functions. */
3798 /* Validate -mregparm= value. */
3800 {
3804 {
3808 }
3809 }
3813 /* Default align_* from the processor table. */
3815 {
3818 }
3820 {
3823 }
3825 {
3827 }
3829 /* Provide default for -mbranch-cost= value. */
3834 {
3835 opts->x_target_flags
3838 /* Enable by default the SSE and MMX builtins. Do allow the user to
3839 explicitly disable any of these. In particular, disabling SSE and
3840 MMX for kernel code is extremely useful. */
3842 opts->x_ix86_isa_flags
3849 }
3850 else
3851 {
3852 opts->x_target_flags
3856 opts->x_ix86_isa_flags
3859 /* i386 ABI does not specify red zone. It still makes sense to use it
3860 when programmer takes care to stack from being destroyed. */
3863 }
3865 /* Keep nonleaf frame pointers. */
3871 /* If we're doing fast math, we don't care about comparison order
3872 wrt NaNs. This lets us use a shorter comparison sequence. */
3876 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3877 since the insns won't need emulation. */
3881 /* Likewise, if the target doesn't have a 387, or we've specified
3882 software floating point, don't use 387 inline intrinsics. */
3886 /* Turn on MMX builtins for -msse. */
3888 opts->x_ix86_isa_flags
3891 /* Enable SSE prefetch. */
3896 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3899 opts->x_ix86_isa_flags
3902 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3905 opts->x_ix86_isa_flags
3908 /* Enable lzcnt instruction for -mabm. */
3910 opts->x_ix86_isa_flags
3913 /* Validate -mpreferred-stack-boundary= value or default it to
3914 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3917 {
3924 {
3928 else
3931 }
3932 else
3933 ix86_preferred_stack_boundary
3935 }
3937 /* Set the default value for -mstackrealign. */
3943 /* Validate -mincoming-stack-boundary= value or default it to
3944 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3947 {
3954 else
3955 {
3956 ix86_user_incoming_stack_boundary
3958 ix86_incoming_stack_boundary
3960 }
3961 }
3963 /* Accept -msseregparm only if at least SSE support is enabled. */
3969 {
3971 {
3973 {
3976 }
3979 {
3982 }
3983 }
3984 }
3985 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3986 fpmath=387. The second is however default at many targets since the
3987 extra 80bit precision of temporaries is considered to be part of ABI.
3988 Overwrite the default at least for -ffast-math.
3989 TODO: -mfpmath=both seems to produce same performing code with bit
3990 smaller binaries. It is however not clear if register allocation is
3991 ready for this setting.
3992 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3993 codegen. We may switch to 387 with -ffast-math for size optimized
3994 functions. */
3998 else
4001 /* If the i387 is disabled, then do not return values in it. */
4005 /* Use external vectorized library in vectorizing intrinsics. */
4008 {
4019 }
4026 /* If stack probes are required, the space used for large function
4027 arguments on the stack must also be probed, so enable
4028 -maccumulate-outgoing-args so this happens in the prologue. */
4031 {
4036 }
4038 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4039 {
4045 }
4047 /* When scheduling description is not available, disable scheduler pass
4048 so it won't slow down the compilation and make x87 code slower. */
4069 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4071 && HAVE_prefetch
4076 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4077 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4082 {
4085 {
4087 ix86_gen_tls_local_dynamic_base_64
4089 }
4090 else
4091 {
4093 ix86_gen_tls_local_dynamic_base_64
4095 }
4096 }
4097 else
4101 {
4111 }
4112 else
4113 {
4123 }
4125 #ifdef USE_IX86_CLD
4126 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4129 #endif
4132 {
4137 }
4139 {
4143 }
4145 {
4146 #if defined(PROFILE_BEFORE_PROLOGUE)
4148 #else
4150 #endif
4151 }
4153 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4154 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4155 AVX unaligned load/store. */
4157 {
4167 /* Enable 128-bit AVX instruction generation
4168 for the auto-vectorizer. */
4172 }
4175 {
4182 {
4185 {
4187 q++;
4188 }
4189 else
4194 else
4195 {
4198 {
4201 }
4204 {
4208 }
4209 }
4214 else
4216 }
4217 }
4224 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4225 for 64-bit Bionic. */
4230 ? MASK_LONG_DOUBLE_128
4233 /* Only one of them can be active. */
4237 /* Save the initial options in case the user does function specific
4238 options. */
4240 target_option_default_node = target_option_current_node
4243 /* Handle stack protector */
4245 opts->x_ix86_stack_protector_guard
4248 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4250 {
4254 }
4257 {
4261 }
4262 }
4264 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4266 static void
4268 {
4270 static struct register_pass_info insert_vzeroupper_info
4273 };
4278 /* This needs to be done at start up. It's convenient to do it here. */
4280 }
4282 /* Update register usage after having seen the compiler flags. */
4284 static void
4286 {
4290 /* The PIC register, if it exists, is fixed. */
4295 /* For 32-bit targets, squash the REX registers. */
4297 {
4304 }
4306 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4314 {
4315 /* Set/reset conditionally defined registers from
4316 CALL_USED_REGISTERS initializer. */
4320 /* Calculate registers of CLOBBERED_REGS register set
4321 as call used registers from GENERAL_REGS register set. */
4325 }
4327 /* If MMX is disabled, squash the registers. */
4333 /* If SSE is disabled, squash the registers. */
4339 /* If the FPU is disabled, squash the registers. */
4345 /* If AVX512F is disabled, squash the registers. */
4347 {
4353 }
4354 }
4356 \f
4357 /* Save the current options */
4359 static void
4362 {
4397 /* The fields are char but the variables are not; make sure the
4398 values fit in the fields. */
4403 }
4405 /* Restore the current options */
4407 static void
4410 {
4416 /* We don't change -fPIC. */
4453 /* Recreate the arch feature tests if the arch changed */
4455 {
4460 }
4462 /* Recreate the tune optimization tests */
4465 }
4467 /* Print the current options */
4469 static void
4472 {
4490 {
4493 }
4494 }
4496 \f
4497 /* Inner function to process the attribute((target(...))), take an argument and
4498 set the current options from the argument. If we have a list, recursively go
4499 over the list. */
4501 static bool
4506 {
4510 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4511 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4512 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4513 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4514 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4516 enum ix86_opt_type
4517 {
4518 ix86_opt_unknown,
4519 ix86_opt_yes,
4520 ix86_opt_no,
4521 ix86_opt_str,
4522 ix86_opt_enum,
4523 ix86_opt_isa
4524 };
4526 static const struct
4527 {
4534 /* isa options */
4580 /* enum options */
4583 /* string options */
4587 /* flag options */
4589 OPT_mcld,
4590 MASK_CLD),
4593 OPT_mfancy_math_387,
4594 MASK_NO_FANCY_MATH_387),
4597 OPT_mieee_fp,
4598 MASK_IEEE_FP),
4601 OPT_minline_all_stringops,
4602 MASK_INLINE_ALL_STRINGOPS),
4605 OPT_minline_stringops_dynamically,
4606 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4609 OPT_mno_align_stringops,
4610 MASK_NO_ALIGN_STRINGOPS),
4613 OPT_mrecip,
4614 MASK_RECIP),
4616 };
4618 /* If this is a list, recurse to get the options. */
4620 {
4627 enum_opts_set))
4631 }
4634 {
4637 }
4639 /* Handle multiple arguments separated by commas. */
4643 {
4657 {
4661 }
4662 else
4663 {
4666 }
4668 /* Recognize no-xxx. */
4670 {
4674 }
4675 else
4678 /* Find the option. */
4682 {
4690 {
4695 }
4696 }
4698 /* Process the option. */
4700 {
4703 }
4706 {
4712 }
4715 {
4721 else
4723 }
4726 {
4728 {
4731 }
4732 else
4734 }
4737 {
4745 global_dc);
4746 else
4747 {
4750 }
4751 }
4753 else
4755 }
4758 }
4760 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4762 tree
4766 {
4781 /* Process each of the options on the chain. */
4786 /* If the changed options are different from the default, rerun
4787 ix86_option_override_internal, and then save the options away.
4788 The string options are are attribute options, and will be undone
4789 when we copy the save structure. */
4795 {
4796 /* If we are using the default tune= or arch=, undo the string assigned,
4797 and use the default. */
4808 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4813 {
4816 }
4818 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4821 /* Add any builtin functions with the new isa if any. */
4824 /* Save the current options unless we are validating options for
4825 #pragma. */
4832 /* Free up memory allocated to hold the strings */
4835 }
4838 }
4840 /* Hook to validate attribute((target("string"))). */
4842 static bool
4845 tree args,
4847 {
4852 /* attribute((target("default"))) does nothing, beyond
4853 affecting multi-versioning. */
4862 /* Get the optimization options of the current function. */
4868 /* Init func_options. */
4876 /* Initialize func_options to the default before its target options can
4877 be set. */
4890 {
4895 }
4898 }
4900 \f
4901 /* Hook to determine if one function can safely inline another. */
4903 static bool
4905 {
4910 /* If callee has no option attributes, then it is ok to inline. */
4914 /* If caller has no option attributes, but callee does then it is not ok to
4915 inline. */
4919 else
4920 {
4924 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4925 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4926 function. */
4931 /* See if we have the same non-isa options. */
4935 /* See if arch, tune, etc. are the same. */
4948 else
4950 }
4953 }
4955 \f
4956 /* Remember the last target of ix86_set_current_function. */
4959 /* Invalidate ix86_previous_fndecl cache. */
4960 void
4962 {
4964 }
4966 /* Establish appropriate back-end context for processing the function
4967 FNDECL. The argument might be NULL to indicate processing at top
4968 level, outside of any function scope. */
4969 static void
4971 {
4972 /* Only change the context if the function changes. This hook is called
4973 several times in the course of compiling a function, and we don't want to
4974 slow things down too much or call target_reinit when it isn't safe. */
4976 {
4977 tree old_tree = (ix86_previous_fndecl
4981 tree new_tree = (fndecl
4987 ;
4990 {
4995 else
4998 }
5001 {
5009 else
5012 }
5013 }
5014 }
5016 \f
5017 /* Return true if this goes in large data/bss. */
5019 static bool
5021 {
5025 /* Functions are never large data. */
5030 {
5036 }
5037 else
5038 {
5041 /* If this is an incomplete type with size 0, then we can't put it
5042 in data because it might be too big when completed. */
5045 }
5048 }
5050 /* Switch to the appropriate section for output of DECL.
5051 DECL is either a `VAR_DECL' node or a constant of some sort.
5052 RELOC indicates whether forming the initial value of DECL requires
5053 link-time relocations. */
5058 {
5061 {
5065 {
5099 /* We don't split these for medium model. Place them into
5100 default sections and hope for best. */
5102 }
5104 {
5105 /* We might get called with string constants, but get_named_section
5106 doesn't like them as they are not DECLs. Also, we need to set
5107 flags in that case. */
5111 }
5112 }
5114 }
5116 /* Select a set of attributes for section NAME based on the properties
5117 of DECL and whether or not RELOC indicates that DECL's initializer
5118 might contain runtime relocations. */
5120 static unsigned int ATTRIBUTE_UNUSED
5122 {
5136 }
5138 /* Build up a unique section name, expressed as a
5139 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5140 RELOC indicates whether the initial value of EXP requires
5141 link-time relocations. */
5143 static void ATTRIBUTE_UNUSED
5145 {
5148 {
5150 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5154 {
5178 /* We don't split these for medium model. Place them into
5179 default sections and hope for best. */
5181 }
5183 {
5190 /* If we're using one_only, then there needs to be a .gnu.linkonce
5191 prefix to the section name. */
5198 }
5199 }
5201 }
5203 #ifdef COMMON_ASM_OP
5204 /* This says how to output assembler code to declare an
5205 uninitialized external linkage data object.
5207 For medium model x86-64 we need to use .largecomm opcode for
5208 large objects. */
5209 void
5213 {
5217 else
5222 }
5223 #endif
5225 /* Utility function for targets to use in implementing
5226 ASM_OUTPUT_ALIGNED_BSS. */
5228 void
5232 {
5236 else
5239 #ifdef ASM_DECLARE_OBJECT_NAME
5242 #else
5243 /* Standard thing is just output label for the object. */
5247 }
5248 \f
5249 /* Decide whether we must probe the stack before any space allocation
5250 on this target. It's essentially TARGET_STACK_PROBE except when
5251 -fstack-check causes the stack to be already probed differently. */
5253 bool
5255 {
5256 /* Do not probe the stack twice if static stack checking is enabled. */
5261 }
5262 \f
5263 /* Decide whether we can make a sibling call to a function. DECL is the
5264 declaration of the function being targeted by the call and EXP is the
5265 CALL_EXPR representing the call. */
5267 static bool
5269 {
5273 /* If we are generating position-independent code, we cannot sibcall
5274 optimize any indirect call, or a direct call to a global function,
5275 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5277 && !TARGET_64BIT
5278 && flag_pic
5282 /* If we need to align the outgoing stack, then sibcalling would
5283 unalign the stack, which may break the called function. */
5289 {
5292 }
5293 else
5294 {
5295 /* We're looking at the CALL_EXPR, we need the type of the function. */
5300 }
5302 /* Check that the return value locations are the same. Like
5303 if we are returning floats on the 80387 register stack, we cannot
5304 make a sibcall from a function that doesn't return a float to a
5305 function that does or, conversely, from a function that does return
5306 a float to a function that doesn't; the necessary stack adjustment
5307 would not be executed. This is also the place we notice
5308 differences in the return value ABI. Note that it is ok for one
5309 of the functions to have void return type as long as the return
5310 value of the other is passed in a register. */
5315 {
5318 }
5320 ;
5325 {
5326 /* The SYSV ABI has more call-clobbered registers;
5327 disallow sibcalls from MS to SYSV. */
5331 }
5332 else
5333 {
5334 /* If this call is indirect, we'll need to be able to use a
5335 call-clobbered register for the address of the target function.
5336 Make sure that all such registers are not used for passing
5337 parameters. Note that DLLIMPORT functions are indirect. */
5340 {
5342 {
5343 /* ??? Need to count the actual number of registers to be used,
5344 not the possible number of registers. Fix later. */
5346 }
5347 }
5348 }
5350 /* Otherwise okay. That also includes certain types of indirect calls. */
5352 }
5354 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5355 and "sseregparm" calling convention attributes;
5356 arguments as in struct attribute_spec.handler. */
5358 static tree
5360 tree args,
5363 {
5368 {
5370 name);
5373 }
5375 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5377 {
5378 tree cst;
5381 {
5383 }
5386 {
5388 }
5392 {
5395 name);
5397 }
5399 {
5403 }
5406 }
5409 {
5410 /* Do not warn when emulating the MS ABI. */
5415 name);
5418 }
5420 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5422 {
5424 {
5426 }
5428 {
5430 }
5432 {
5434 }
5436 {
5438 }
5439 }
5441 /* Can combine stdcall with fastcall (redundant), regparm and
5442 sseregparm. */
5444 {
5446 {
5448 }
5450 {
5452 }
5454 {
5456 }
5457 }
5459 /* Can combine cdecl with regparm and sseregparm. */
5461 {
5463 {
5465 }
5467 {
5469 }
5471 {
5473 }
5474 }
5476 {
5479 name);
5481 {
5483 }
5485 {
5487 }
5489 {
5491 }
5492 }
5494 /* Can combine sseregparm with all attributes. */
5497 }
5499 /* The transactional memory builtins are implicitly regparm or fastcall
5500 depending on the ABI. Override the generic do-nothing attribute that
5501 these builtins were declared with, and replace it with one of the two
5502 attributes that we expect elsewhere. */
5504 static tree
5506 tree args ATTRIBUTE_UNUSED,
5508 {
5509 tree alt;
5511 /* In no case do we want to add the placeholder attribute. */
5514 /* The 64-bit ABI is unchanged for transactional memory. */
5518 /* ??? Is there a better way to validate 32-bit windows? We have
5519 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5522 else
5523 {
5526 }
5530 }
5532 /* This function determines from TYPE the calling-convention. */
5534 unsigned int
5536 {
5539 tree attrs;
5546 {
5556 /* Regparam isn't allowed for thiscall and fastcall. */
5558 {
5563 }
5567 }
5574 || is_stdarg
5580 }
5582 /* Return 0 if the attributes for two types are incompatible, 1 if they
5583 are compatible, and 2 if they are nearly compatible (which causes a
5584 warning to be generated). */
5586 static int
5588 {
5604 }
5605 \f
5606 /* Return the regparm value for a function with the indicated TYPE and DECL.
5607 DECL may be NULL when calling function indirectly
5608 or considering a libcall. */
5610 static int
5612 {
5613 tree attr;
5624 {
5627 {
5630 }
5631 }
5637 /* Use register calling convention for local functions when possible. */
5640 /* Caller and callee must agree on the calling convention, so
5641 checking here just optimize means that with
5642 __attribute__((optimize (...))) caller could use regparm convention
5643 and callee not, or vice versa. Instead look at whether the callee
5644 is optimized or not. */
5647 {
5648 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5651 {
5654 /* Make sure no regparm register is taken by a
5655 fixed register variable. */
5660 /* We don't want to use regparm(3) for nested functions as
5661 these use a static chain pointer in the third argument. */
5665 /* In 32-bit mode save a register for the split stack. */
5669 /* Each fixed register usage increases register pressure,
5670 so less registers should be used for argument passing.
5671 This functionality can be overriden by an explicit
5672 regparm value. */
5675 globals++;
5677 local_regparm
5682 }
5683 }
5686 }
5688 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5689 DFmode (2) arguments in SSE registers for a function with the
5690 indicated TYPE and DECL. DECL may be NULL when calling function
5691 indirectly or considering a libcall. Otherwise return 0. */
5693 static int
5695 {
5698 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5699 by the sseregparm attribute. */
5702 {
5704 {
5706 {
5710 else
5713 }
5715 }
5718 }
5720 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5721 (and DFmode for SSE2) arguments in SSE registers. */
5724 {
5725 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5729 }
5732 }
5734 /* Return true if EAX is live at the start of the function. Used by
5735 ix86_expand_prologue to determine if we need special help before
5736 calling allocate_stack_worker. */
5738 static bool
5740 {
5741 /* Cheat. Don't bother working forward from ix86_function_regparm
5742 to the function type to whether an actual argument is located in
5743 eax. Instead just look at cfg info, which is still close enough
5744 to correct at this point. This gives false positives for broken
5745 functions that might use uninitialized data that happens to be
5746 allocated in eax, but who cares? */
5748 }
5750 static bool
5752 {
5753 tree attr;
5756 {
5762 /* For 32-bit MS-ABI the default is to keep aggregate
5763 return pointer. */
5766 }
5768 }
5770 /* Value is the number of bytes of arguments automatically
5771 popped when returning from a subroutine call.
5772 FUNDECL is the declaration node of the function (as a tree),
5773 FUNTYPE is the data type of the function (as a tree),
5774 or for a library call it is an identifier node for the subroutine name.
5775 SIZE is the number of bytes of arguments passed on the stack.
5777 On the 80386, the RTD insn may be used to pop them if the number
5778 of args is fixed, but if the number is variable then the caller
5779 must pop them all. RTD can't be used for library calls now
5780 because the library is compiled with the Unix compiler.
5781 Use of RTD is a selectable option, since it is incompatible with
5782 standard Unix calling sequences. If the option is not selected,
5783 the caller must always pop the args.
5785 The attribute stdcall is equivalent to RTD on a per module basis. */
5787 static int
5789 {
5792 /* None of the 64-bit ABIs pop arguments. */
5803 /* Lose any fake structure return argument if it is passed on the stack. */
5806 {
5810 }
5813 }
5815 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5817 static bool
5819 {
5820 /* Check operand constraints in case hard registers were propagated
5821 into insn pattern. This check prevents combine pass from
5822 generating insn patterns with invalid hard register operands.
5823 These invalid insns can eventually confuse reload to error out
5824 with a spill failure. See also PRs 46829 and 46843. */
5826 {
5835 {
5843 /* For pre-AVX disallow unaligned loads/stores where the
5844 instructions don't support it. */
5848 {
5852 }
5854 /* A unary operator may be accepted by the predicate, but it
5855 is irrelevant for matching constraints. */
5860 {
5868 }
5875 /* Operand has no constraints, anything is OK. */
5880 {
5885 && operands_match_p
5889 {
5892 }
5893 }
5897 }
5898 }
5901 }
5902 \f
5903 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5905 static unsigned HOST_WIDE_INT
5907 {
5911 }
5912 \f
5913 /* Argument support functions. */
5915 /* Return true when register may be used to pass function parameters. */
5916 bool
5918 {
5923 {
5927 else
5933 }
5939 /* TODO: The function should depend on current function ABI but
5940 builtins.c would need updating then. Therefore we use the
5941 default ABI. */
5943 /* RAX is used as hidden argument to va_arg functions. */
5949 else
5956 }
5958 /* Return if we do not know how to pass TYPE solely in registers. */
5960 static bool
5962 {
5966 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5967 The layout_type routine is crafty and tries to trick us into passing
5968 currently unsupported vector types on the stack by using TImode. */
5971 }
5973 /* It returns the size, in bytes, of the area reserved for arguments passed
5974 in registers for the function represented by fndecl dependent to the used
5975 abi format. */
5976 int
5978 {
5982 else
5987 }
5989 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5990 call abi used. */
5991 enum calling_abi
5993 {
5995 {
5998 {
6001 }
6005 }
6007 }
6009 /* We add this as a workaround in order to use libc_has_function
6010 hook in i386.md. */
6011 bool
6013 {
6015 }
6017 static bool
6019 {
6021 {
6025 else
6027 }
6029 }
6031 static enum calling_abi
6033 {
6037 }
6039 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6040 call abi used. */
6041 enum calling_abi
6043 {
6047 }
6049 /* Write the extra assembler code needed to declare a function properly. */
6051 void
6053 tree decl)
6054 {
6058 {
6064 }
6066 #ifdef SUBTARGET_ASM_UNWIND_INIT
6068 #endif
6072 /* Output magic byte marker, if hot-patch attribute is set. */
6074 {
6076 {
6077 /* leaq [%rsp + 0], %rsp */
6080 }
6081 else
6082 {
6083 /* movl.s %edi, %edi
6084 push %ebp
6085 movl.s %esp, %ebp */
6088 }
6089 }
6090 }
6092 /* regclass.c */
6095 /* Implementation of call abi switching target hook. Specific to FNDECL
6096 the specific call register sets are set. See also
6097 ix86_conditional_register_usage for more details. */
6098 void
6100 {
6103 else
6105 }
6107 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6108 expensive re-initialization of init_regs each time we switch function context
6109 since this is needed only during RTL expansion. */
6110 static void
6112 {
6116 }
6118 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6119 for a call to a function whose data type is FNTYPE.
6120 For a library call, FNTYPE is 0. */
6122 void
6126 tree fndecl,
6128 {
6134 {
6137 }
6138 else
6139 {
6142 }
6146 /* Set up the number of registers to use for passing arguments. */
6149 {
6151 ? X86_64_REGPARM_MAX
6153 }
6155 {
6158 {
6160 ? X86_64_SSE_REGPARM_MAX
6162 }
6163 }
6171 /* Because type might mismatch in between caller and callee, we need to
6172 use actual type of function for local calls.
6173 FIXME: cgraph_analyze can be told to actually record if function uses
6174 va_start so for local functions maybe_vaarg can be made aggressive
6175 helping K&R code.
6176 FIXME: once typesytem is fixed, we won't need this code anymore. */
6184 {
6185 /* If there are variable arguments, then we won't pass anything
6186 in registers in 32-bit mode. */
6188 {
6197 }
6199 /* Use ecx and edx registers if function has fastcall attribute,
6200 else look for regparm information. */
6202 {
6205 {
6208 }
6210 {
6213 }
6214 else
6216 }
6218 /* Set up the number of SSE registers used for passing SFmode
6219 and DFmode arguments. Warn for mismatching ABI. */
6221 }
6222 }
6224 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6225 But in the case of vector types, it is some vector mode.
6227 When we have only some of our vector isa extensions enabled, then there
6228 are some modes for which vector_mode_supported_p is false. For these
6229 modes, the generic vector support in gcc will choose some non-vector mode
6230 in order to implement the type. By computing the natural mode, we'll
6231 select the proper ABI location for the operand and not depend on whatever
6232 the middle-end decides to do with these vector types.
6234 The midde-end can't deal with the vector types > 16 bytes. In this
6235 case, we return the original mode and warn ABI change if CUM isn't
6236 NULL.
6238 If INT_RETURN is true, warn ABI change if the vector mode isn't
6239 available for function return value. */
6241 static enum machine_mode
6244 {
6248 {
6251 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6253 {
6258 else
6261 /* Get the mode which has this inner mode and number of units. */
6265 {
6267 {
6272 {
6276 }
6278 {
6282 }
6285 }
6287 {
6292 {
6296 }
6298 {
6302 }
6305 }
6308 {
6313 {
6317 }
6319 {
6323 }
6324 }
6326 {
6331 {
6335 }
6337 {
6341 }
6342 }
6344 }
6347 }
6348 }
6351 }
6353 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6354 this may not agree with the mode that the type system has chosen for the
6355 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6356 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6358 static rtx
6361 {
6362 rtx tmp;
6366 else
6367 {
6371 }
6374 }
6376 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6377 of this code is to classify each 8bytes of incoming argument by the register
6378 class and assign registers accordingly. */
6380 /* Return the union class of CLASS1 and CLASS2.
6381 See the x86-64 PS ABI for details. */
6383 static enum x86_64_reg_class
6385 {
6386 /* Rule #1: If both classes are equal, this is the resulting class. */
6390 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6391 the other class. */
6397 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6401 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6409 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6410 MEMORY is used. */
6419 /* Rule #6: Otherwise class SSE is used. */
6421 }
6423 /* Classify the argument of type TYPE and mode MODE.
6424 CLASSES will be filled by the register class used to pass each word
6425 of the operand. The number of words is returned. In case the parameter
6426 should be passed in memory, 0 is returned. As a special case for zero
6427 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6429 BIT_OFFSET is used internally for handling records and specifies offset
6430 of the offset in bits modulo 512 to avoid overflow cases.
6432 See the x86-64 PS ABI for details.
6433 */
6435 static int
6438 {
6439 HOST_WIDE_INT bytes =
6441 int words
6444 /* Variable sized entities are always passed/returned in memory. */
6453 {
6455 tree field;
6458 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6465 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6466 signalize memory class, so handle it as special case. */
6468 {
6471 }
6473 /* Classify each field of record and merge classes. */
6475 {
6477 /* And now merge the fields of structure. */
6479 {
6481 {
6487 /* Bitfields are always classified as integer. Handle them
6488 early, since later code would consider them to be
6489 misaligned integers. */
6491 {
6500 }
6501 else
6502 {
6507 /* Flexible array member is ignored. */
6514 {
6518 {
6521 "the ABI of passing struct with"
6522 " a flexible array member has"
6524 }
6526 }
6528 subclasses,
6538 }
6539 }
6540 }
6544 /* Arrays are handled as small records. */
6545 {
6552 /* The partial classes are now full classes. */
6563 }
6566 /* Unions are similar to RECORD_TYPE but offset is always 0.
6567 */
6569 {
6571 {
6579 bit_offset);
6584 }
6585 }
6590 }
6593 {
6594 /* When size > 16 bytes, if the first one isn't
6595 X86_64_SSE_CLASS or any other ones aren't
6596 X86_64_SSEUP_CLASS, everything should be passed in
6597 memory. */
6604 }
6606 /* Final merger cleanup. */
6608 {
6609 /* If one class is MEMORY, everything should be passed in
6610 memory. */
6614 /* The X86_64_SSEUP_CLASS should be always preceded by
6615 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6619 {
6620 /* The first one should never be X86_64_SSEUP_CLASS. */
6623 }
6625 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6626 everything should be passed in memory. */
6629 {
6632 /* The first one should never be X86_64_X87UP_CLASS. */
6635 {
6638 "the ABI of passing union with long double"
6640 }
6642 }
6643 }
6645 }
6647 /* Compute alignment needed. We align all types to natural boundaries with
6648 exception of XFmode that is aligned to 64bits. */
6650 {
6659 /* Misaligned fields are always returned in memory. */
6662 }
6664 /* for V1xx modes, just use the base mode */
6669 /* Classification of atomic types. */
6671 {
6687 {
6690 /* Analyze last 128 bits only. */
6694 {
6697 }
6699 {
6702 }
6704 {
6708 }
6710 {
6713 }
6714 else
6716 }
6723 /* OImode shouldn't be used directly. */
6730 else
6748 else
6749 {
6753 {
6756 "the ABI of passing structure with complex float"
6758 }
6761 }
6770 /* This modes is larger than 16 bytes. */
6828 else
6832 }
6833 }
6835 /* Examine the argument and return set number of register required in each
6836 class. Return true iff parameter should be passed in memory. */
6838 static bool
6841 {
6852 {
6873 }
6876 }
6878 /* Construct container for the argument used by GCC interface. See
6879 FUNCTION_ARG for the detailed description. */
6881 static rtx
6885 {
6886 /* The following variables hold the static issued_error state. */
6900 rtx ret;
6911 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6912 some less clueful developer tries to use floating-point anyway. */
6914 {
6916 {
6918 {
6921 }
6922 }
6924 {
6927 }
6929 }
6931 /* Likewise, error if the ABI requires us to return values in the
6932 x87 registers and the user specified -mno-80387. */
6938 {
6940 {
6943 }
6945 }
6947 /* First construct simple cases. Avoid SCmode, since we want to use
6948 single register to pass this type. */
6951 {
6966 /* Zero sized array, struct or class. */
6970 }
7009 /* Otherwise figure out the entries of the PARALLEL. */
7011 {
7015 {
7020 /* Merge TImodes on aligned occasions here too. */
7022 tmpmode
7026 else
7028 /* We've requested 24 bytes we
7029 don't have mode for. Use DImode. */
7036 intreg++;
7044 sse_regno++;
7052 sse_regno++;
7057 {
7063 {
7065 i++;
7066 }
7067 else
7092 }
7098 sse_regno++;
7102 }
7103 }
7105 /* Empty aligned struct, union or class. */
7113 }
7115 /* Update the data in CUM to advance over an argument of mode MODE
7116 and data type TYPE. (TYPE is null for libcalls where that information
7117 may not be available.) */
7119 static void
7122 HOST_WIDE_INT words)
7123 {
7125 {
7132 /* FALLTHRU */
7143 {
7146 }
7150 /* OImode shouldn't be used directly. */
7159 /* FALLTHRU */
7181 {
7186 {
7189 }
7190 }
7200 {
7205 {
7208 }
7209 }
7211 }
7212 }
7214 static void
7217 {
7220 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7227 {
7232 }
7233 else
7234 {
7238 }
7239 }
7241 static void
7243 HOST_WIDE_INT words)
7244 {
7245 /* Otherwise, this should be passed indirect. */
7250 {
7253 }
7254 }
7256 /* Update the data in CUM to advance over an argument of mode MODE and
7257 data type TYPE. (TYPE is null for libcalls where that information
7258 may not be available.) */
7260 static void
7263 {
7269 else
7280 else
7282 }
7284 /* Define where to put the arguments to a function.
7285 Value is zero to push the argument on the stack,
7286 or a hard register in which to store the argument.
7288 MODE is the argument's machine mode.
7289 TYPE is the data type of the argument (as a tree).
7290 This is null for libcalls where that information may
7291 not be available.
7292 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7293 the preceding args and about the function being called.
7294 NAMED is nonzero if this argument is a named parameter
7295 (otherwise it is an extra parameter matching an ellipsis). */
7297 static rtx
7301 {
7302 /* Avoid the AL settings for the Unix64 ABI. */
7307 {
7314 /* FALLTHRU */
7320 {
7323 /* Fastcall allocates the first two DWORD (SImode) or
7324 smaller arguments to ECX and EDX if it isn't an
7325 aggregate type . */
7327 {
7333 /* ECX not EAX is the first allocated register. */
7336 }
7338 }
7347 /* FALLTHRU */
7349 /* In 32bit, we pass TImode in xmm registers. */
7357 {
7361 }
7366 /* OImode and XImode shouldn't be used directly. */
7382 {
7386 }
7396 {
7400 }
7402 }
7405 }
7407 static rtx
7410 {
7411 /* Handle a hidden AL argument containing number of registers
7412 for varargs x86-64 functions. */
7416 ? X86_64_SSE_REGPARM_MAX
7421 {
7437 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7441 }
7447 }
7449 static rtx
7452 HOST_WIDE_INT bytes)
7453 {
7456 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7457 We use value of -2 to specify that current function call is MSABI. */
7461 /* If we've run out of registers, it goes on the stack. */
7467 /* Only floating point modes are passed in anything but integer regs. */
7469 {
7472 else
7473 {
7476 /* Unnamed floating parameters are passed in both the
7477 SSE and integer registers. */
7483 }
7484 }
7485 /* Handle aggregated types passed in register. */
7487 {
7492 }
7495 }
7497 /* Return where to put the arguments to a function.
7498 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7500 MODE is the argument's machine mode. TYPE is the data type of the
7501 argument. It is null for libcalls where that information may not be
7502 available. CUM gives information about the preceding args and about
7503 the function being called. NAMED is nonzero if this argument is a
7504 named parameter (otherwise it is an extra parameter matching an
7505 ellipsis). */
7507 static rtx
7510 {
7514 rtx arg;
7518 else
7522 /* To simplify the code below, represent vector types with a vector mode
7523 even if MMX/SSE are not active. */
7531 else
7535 }
7537 /* A C expression that indicates when an argument must be passed by
7538 reference. If nonzero for an argument, a copy of that argument is
7539 made in memory and a pointer to the argument is passed instead of
7540 the argument itself. The pointer is passed in whatever way is
7541 appropriate for passing a pointer to that type. */
7543 static bool
7546 {
7549 /* See Windows x64 Software Convention. */
7551 {
7554 {
7555 /* Arrays are passed by reference. */
7560 {
7561 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7562 are passed by reference. */
7564 }
7565 }
7567 /* __m128 is passed by reference. */
7573 }
7574 }
7579 }
7581 /* Return true when TYPE should be 128bit aligned for 32bit argument
7582 passing ABI. XXX: This function is obsolete and is only used for
7583 checking psABI compatibility with previous versions of GCC. */
7585 static bool
7587 {
7599 {
7600 /* Walk the aggregates recursively. */
7602 {
7606 {
7607 tree field;
7609 /* Walk all the structure fields. */
7611 {
7615 }
7617 }
7620 /* Just for use if some languages passes arrays by value. */
7627 }
7628 }
7630 }
7632 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7633 XXX: This function is obsolete and is only used for checking psABI
7634 compatibility with previous versions of GCC. */
7636 static unsigned int
7639 {
7640 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7641 natural boundaries. */
7643 {
7644 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7645 make an exception for SSE modes since these require 128bit
7646 alignment.
7648 The handling here differs from field_alignment. ICC aligns MMX
7649 arguments to 4 byte boundaries, while structure fields are aligned
7650 to 8 byte boundaries. */
7652 {
7655 }
7656 else
7657 {
7660 }
7661 }
7665 }
7667 /* Return true when TYPE should be 128bit aligned for 32bit argument
7668 passing ABI. */
7670 static bool
7672 {
7682 {
7683 /* Walk the aggregates recursively. */
7685 {
7689 {
7690 tree field;
7692 /* Walk all the structure fields. */
7694 field;
7696 {
7700 }
7702 }
7705 /* Just for use if some languages passes arrays by value. */
7712 }
7713 }
7714 else
7718 }
7720 /* Gives the alignment boundary, in bits, of an argument with the
7721 specified mode and type. */
7723 static unsigned int
7725 {
7728 {
7729 /* Since the main variant type is used for call, we convert it to
7730 the main variant type. */
7733 }
7734 else
7738 else
7739 {
7744 {
7745 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7747 {
7750 }
7756 }
7759 && !warned
7761 saved_align))
7762 {
7765 "The ABI for passing parameters with %d-byte"
7768 }
7769 }
7772 }
7774 /* Return true if N is a possible register number of function value. */
7776 static bool
7778 {
7780 {
7789 /* Complex values are returned in %st(0)/%st(1) pair. */
7792 /* TODO: The function should depend on current function ABI but
7793 builtins.c would need updating then. Therefore we use the
7794 default ABI. */
7799 /* Complex values are returned in %xmm0/%xmm1 pair. */
7808 }
7811 }
7813 /* Define how to find the value returned by a function.
7814 VALTYPE is the data type of the value (as a tree).
7815 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7816 otherwise, FUNC is 0. */
7818 static rtx
7821 {
7824 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7825 we normally prevent this case when mmx is not available. However
7826 some ABIs may require the result to be returned like DImode. */
7830 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7831 we prevent this case when sse is not available. However some ABIs
7832 may require the result to be returned like integer TImode. */
7837 /* 32-byte vector modes in %ymm0. */
7841 /* 64-byte vector modes in %zmm0. */
7845 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7848 else
7849 /* Most things go in %eax. */
7852 /* Override FP return register with %xmm0 for local functions when
7853 SSE math is enabled or for functions with sseregparm attribute. */
7855 {
7860 }
7862 /* OImode shouldn't be used directly. */
7866 }
7868 static rtx
7870 const_tree valtype)
7871 {
7872 rtx ret;
7874 /* Handle libcalls, which don't provide a type node. */
7876 {
7880 {
7899 }
7902 }
7904 {
7905 /* Pointers are always returned in word_mode. */
7907 }
7913 /* For zero sized structures, construct_container returns NULL, but we
7914 need to keep rest of compiler happy by returning meaningful value. */
7919 }
7921 static rtx
7923 const_tree valtype)
7924 {
7928 {
7930 {
7949 }
7950 }
7952 }
7954 static rtx
7957 {
7969 else
7971 }
7973 static rtx
7976 {
7982 }
7984 /* Pointer function arguments and return values are promoted to
7985 word_mode. */
7987 static enum machine_mode
7991 {
7993 {
7996 }
7998 for_return);
7999 }
8001 /* Return true if a structure, union or array with MODE containing FIELD
8002 should be accessed using BLKmode. */
8004 static bool
8006 {
8007 /* Union with XFmode must be in BLKmode. */
8011 }
8013 rtx
8015 {
8017 }
8019 /* Return true iff type is returned in memory. */
8021 static bool
8023 {
8024 #ifdef SUBTARGET_RETURN_IN_MEMORY
8026 #else
8028 HOST_WIDE_INT size;
8031 {
8033 {
8036 /* __m128 is returned in xmm0. */
8045 /* Otherwise, the size must be exactly in [1248]. */
8047 }
8048 else
8049 {
8054 }
8055 }
8056 else
8057 {
8067 {
8068 /* User-created vectors small enough to fit in EAX. */
8072 /* Unless ABI prescibes otherwise,
8073 MMX/3dNow values are returned in MM0 if available. */
8078 /* SSE values are returned in XMM0 if available. */
8082 /* AVX values are returned in YMM0 if available. */
8086 /* AVX512F values are returned in ZMM0 if available. */
8089 }
8097 /* OImode shouldn't be used directly. */
8101 }
8102 #endif
8103 }
8105 \f
8106 /* Create the va_list data type. */
8108 /* Returns the calling convention specific va_list date type.
8109 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8111 static tree
8113 {
8116 /* For i386 we use plain pointer to argument area. */
8126 unsigned_type_node);
8129 unsigned_type_node);
8132 ptr_type_node);
8135 ptr_type_node);
8154 /* The correct type is an array type of one element. */
8156 }
8158 /* Setup the builtin va_list data type and for 64-bit the additional
8159 calling convention specific va_list data types. */
8161 static tree
8163 {
8166 /* Initialize abi specific va_list builtin types. */
8168 {
8169 tree t;
8171 {
8176 }
8177 else
8178 {
8183 }
8185 {
8190 }
8191 else
8192 {
8197 }
8198 }
8201 }
8203 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8205 static void
8207 {
8209 alias_set_type set;
8212 /* GPR size of varargs save area. */
8215 else
8218 /* FPR size of varargs save area. We don't need it if we don't pass
8219 anything in SSE registers. */
8222 else
8236 {
8244 }
8247 {
8251 /* Now emit code to save SSE registers. The AX parameter contains number
8252 of SSE parameter registers used to call this function, though all we
8253 actually check here is the zero/non-zero status. */
8258 label));
8260 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8261 we used movdqa (i.e. TImode) instead? Perhaps even better would
8262 be if we could determine the real mode of the data, via a hook
8263 into pass_stdarg. Ignore all that for now. */
8273 {
8282 }
8285 }
8286 }
8288 static void
8290 {
8294 /* Reset to zero, as there might be a sysv vaarg used
8295 before. */
8300 {
8311 }
8312 }
8314 static void
8318 {
8320 CUMULATIVE_ARGS next_cum;
8321 tree fntype;
8323 /* This argument doesn't appear to be used anymore. Which is good,
8324 because the old code here didn't suppress rtl generation. */
8332 /* For varargs, we do not want to skip the dummy va_dcl argument.
8333 For stdargs, we do want to skip the last named argument. */
8341 else
8343 }
8345 /* Checks if TYPE is of kind va_list char *. */
8347 static bool
8349 {
8350 tree canonic;
8352 /* For 32-bit it is always true. */
8358 }
8360 /* Implement va_start. */
8362 static void
8364 {
8368 tree type;
8369 rtx ovf_rtx;
8373 {
8376 /* When we are splitting the stack, we can't refer to the stack
8377 arguments using internal_arg_pointer, because they may be on
8378 the old stack. The split stack prologue will arrange to
8379 leave a pointer to the old stack arguments in a scratch
8380 register, which we here copy to a pseudo-register. The split
8381 stack prologue can't set the pseudo-register directly because
8382 it (the prologue) runs before any registers have been saved. */
8386 {
8400 }
8401 }
8403 /* Only 64bit target needs something special. */
8405 {
8408 else
8409 {
8418 }
8420 }
8429 /* The following should be folded into the MEM_REF offset. */
8439 /* Count number of gp and fp argument registers used. */
8445 {
8451 }
8454 {
8460 }
8462 /* Find the overflow area. */
8466 else
8476 {
8477 /* Find the register save area.
8478 Prologue of the function save it right above stack frame. */
8486 }
8487 }
8489 /* Implement va_arg. */
8491 static tree
8494 {
8501 rtx container;
8503 tree ptrtype;
8507 /* Only 64bit target needs something special. */
8531 {
8544 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8546 {
8549 }
8557 }
8559 /* Pull the value out of the saved registers. */
8564 {
8578 /* In case we are passing structure, verify that it is consecutive block
8579 on the register save area. If not we need to do moves. */
8581 {
8582 /* Verify that all registers are strictly consecutive */
8584 {
8588 {
8593 }
8594 }
8595 else
8596 {
8600 {
8605 }
8606 }
8607 }
8609 {
8612 }
8613 else
8614 {
8617 }
8619 /* First ensure that we fit completely in registers. */
8621 {
8628 }
8630 {
8638 }
8640 /* Compute index to start of area used for integer regs. */
8642 {
8643 /* int_addr = gpr + sav; */
8646 }
8648 {
8649 /* sse_addr = fpr + sav; */
8652 }
8654 {
8658 /* addr = &temp; */
8663 {
8667 tree piece_type;
8668 tree addr_type;
8669 tree daddr_type;
8678 {
8683 }
8687 else
8694 {
8697 }
8698 else
8699 {
8702 }
8709 {
8714 }
8715 else
8716 {
8717 tree copy
8722 }
8724 }
8725 }
8728 {
8732 }
8735 {
8739 }
8744 }
8746 /* ... otherwise out of the overflow area. */
8748 /* When we align parameter on stack for caller, if the parameter
8749 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8750 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8751 here with caller. */
8756 /* Care for on-stack alignment if needed. */
8759 else
8760 {
8765 }
8782 }
8783 \f
8784 /* Return true if OPNUM's MEM should be matched
8785 in movabs* patterns. */
8787 bool
8789 {
8801 }
8802 \f
8803 /* Initialize the table of extra 80387 mathematical constants. */
8805 static void
8807 {
8809 {
8815 };
8819 {
8821 /* Ensure each constant is rounded to XFmode precision. */
8824 }
8827 }
8829 /* Return non-zero if the constant is something that
8830 can be loaded with a special instruction. */
8832 int
8834 {
8837 REAL_VALUE_TYPE r;
8849 /* For XFmode constants, try to find a special 80387 instruction when
8850 optimizing for size or on those CPUs that benefit from them. */
8853 {
8862 }
8864 /* Load of the constant -0.0 or -1.0 will be split as
8865 fldz;fchs or fld1;fchs sequence. */
8872 }
8874 /* Return the opcode of the special instruction to be used to load
8875 the constant X. */
8879 {
8881 {
8901 }
8902 }
8904 /* Return the CONST_DOUBLE representing the 80387 constant that is
8905 loaded by the specified special instruction. The argument IDX
8906 matches the return value from standard_80387_constant_p. */
8908 rtx
8910 {
8917 {
8928 }
8931 XFmode);
8932 }
8934 /* Return 1 if X is all 0s and 2 if x is all 1s
8935 in supported SSE/AVX vector mode. */
8937 int
8939 {
8946 {
8967 }
8970 }
8972 /* Return the opcode of the special instruction to be used to load
8973 the constant X. */
8977 {
8979 {
8982 {
9004 }
9013 else
9018 }
9020 }
9022 /* Returns true if OP contains a symbol reference */
9024 bool
9026 {
9035 {
9037 {
9043 }
9047 }
9050 }
9052 /* Return true if it is appropriate to emit `ret' instructions in the
9053 body of a function. Do this only if the epilogue is simple, needing a
9054 couple of insns. Prior to reloading, we can't tell how many registers
9055 must be saved, so return false then. Return false if there is no frame
9056 marker to de-allocate. */
9058 bool
9060 {
9066 /* Don't allow more than 32k pop, since that's all we can do
9067 with one instruction. */
9074 }
9075 \f
9076 /* Value should be nonzero if functions must have frame pointers.
9077 Zero means the frame pointer need not be set up (and parms may
9078 be accessed via the stack pointer) in functions that seem suitable. */
9080 static bool
9082 {
9083 /* If we accessed previous frames, then the generated code expects
9084 to be able to access the saved ebp value in our frame. */
9088 /* Several x86 os'es need a frame pointer for other reasons,
9089 usually pertaining to setjmp. */
9093 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9097 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9098 allocation is 4GB. */
9102 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9103 turns off the frame pointer by default. Turn it back on now if
9104 we've not got a leaf function. */
9114 }
9116 /* Record that the current function accesses previous call frames. */
9118 void
9120 {
9122 }
9123 \f
9124 #ifndef USE_HIDDEN_LINKONCE
9125 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9126 # define USE_HIDDEN_LINKONCE 1
9127 # else
9128 # define USE_HIDDEN_LINKONCE 0
9129 # endif
9130 #endif
9134 /* Fills in the label name that should be used for a pc thunk for
9135 the given register. */
9137 static void
9139 {
9144 else
9146 }
9149 /* This function generates code for -fpic that loads %ebx with
9150 the return address of the caller and then returns. */
9152 static void
9154 {
9159 {
9161 tree decl;
9177 #if TARGET_MACHO
9179 {
9188 }
9189 else
9190 #endif
9192 {
9203 }
9204 else
9205 {
9208 }
9214 /* Make sure unwind info is emitted for the thunk if needed. */
9217 /* Pad stack IP move with 4 instructions (two NOPs count
9218 as one instruction). */
9220 {
9225 }
9236 }
9240 }
9242 /* Emit code for the SET_GOT patterns. */
9246 {
9252 {
9253 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9258 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9259 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9260 an unadorned address. */
9265 }
9270 {
9272 /* We don't need a pic base, we're not producing pic. */
9279 }
9280 else
9281 {
9290 #if TARGET_MACHO
9291 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9292 This is what will be referenced by the Mach-O PIC subsystem. */
9296 /* When we are restoring the pic base at the site of a nonlocal label,
9297 and we decided to emit the pic base above, we will still output a
9298 local label used for calculating the correction offset (even though
9299 the offset will be 0 in that case). */
9303 #endif
9304 }
9310 }
9312 /* Generate an "push" pattern for input ARG. */
9314 static rtx
9316 {
9329 stack_pointer_rtx)),
9330 arg);
9331 }
9333 /* Generate an "pop" pattern for input ARG. */
9335 static rtx
9337 {
9342 arg,
9345 stack_pointer_rtx)));
9346 }
9348 /* Return >= 0 if there is an unused call-clobbered register available
9349 for the entire function. */
9351 static unsigned int
9353 {
9357 {
9359 /* Can't use the same register for both PIC and DRAP. */
9362 else
9367 }
9370 }
9372 /* Return TRUE if we need to save REGNO. */
9374 static bool
9376 {
9387 {
9390 {
9396 }
9397 }
9408 }
9410 /* Return number of saved general prupose registers. */
9412 static int
9414 {
9420 nregs ++;
9422 }
9424 /* Return number of saved SSE registrers. */
9426 static int
9428 {
9436 nregs ++;
9438 }
9440 /* Given FROM and TO register numbers, say whether this elimination is
9441 allowed. If stack alignment is needed, we can only replace argument
9442 pointer with hard frame pointer, or replace frame pointer with stack
9443 pointer. Otherwise, frame pointer elimination is automatically
9444 handled and all other eliminations are valid. */
9446 static bool
9448 {
9454 else
9456 }
9458 /* Return the offset between two registers, one to be eliminated, and the other
9459 its replacement, at the start of a routine. */
9461 HOST_WIDE_INT
9463 {
9472 else
9473 {
9481 }
9482 }
9484 /* In a dynamically-aligned function, we can't know the offset from
9485 stack pointer to frame pointer, so we must ensure that setjmp
9486 eliminates fp against the hard fp (%ebp) rather than trying to
9487 index from %esp up to the top of the frame across a gap that is
9488 of unknown (at compile-time) size. */
9489 static rtx
9491 {
9493 }
9495 /* When using -fsplit-stack, the allocation routines set a field in
9496 the TCB to the bottom of the stack plus this much space, measured
9497 in bytes. */
9499 #define SPLIT_STACK_AVAILABLE 256
9501 /* Fill structure ix86_frame about frame of currently computed function. */
9503 static void
9505 {
9507 HOST_WIDE_INT offset;
9510 HOST_WIDE_INT to_allocate;
9515 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9516 function prologues and leaf. */
9520 {
9523 }
9524 /* preferred_stack_boundary is never updated for call
9525 expanded from tls descriptor. Update it here. We don't update it in
9526 expand stage because according to the comments before
9527 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9528 away. */
9531 {
9535 }
9544 /* For SEH we have to limit the amount of code movement into the prologue.
9545 At present we do this via a BLOCKAGE, at which point there's very little
9546 scheduling that can be done, which means that there's very little point
9547 in doing anything except PUSHs. */
9551 /* During reload iteration the amount of registers saved can change.
9552 Recompute the value as needed. Do not recompute when amount of registers
9553 didn't change as reload does multiple calls to the function and does not
9554 expect the decision to change within single iteration. */
9557 {
9563 /* The fast prologue uses move instead of push to save registers. This
9564 is significantly longer, but also executes faster as modern hardware
9565 can execute the moves in parallel, but can't do that for push/pop.
9567 Be careful about choosing what prologue to emit: When function takes
9568 many instructions to execute we may use slow version as well as in
9569 case function is known to be outside hot spot (this is known with
9570 feedback only). Weight the size of function by number of registers
9571 to save as it is cheap to use one or two push instructions but very
9572 slow to use many of them. */
9576 || (flag_branch_probabilities
9579 else
9582 }
9584 frame->save_regs_using_mov
9586 /* If static stack checking is enabled and done with probes,
9587 the registers need to be saved before allocating the frame. */
9590 /* Skip return address. */
9593 /* Skip pushed static chain. */
9597 /* Skip saved base pointer. */
9602 /* The traditional frame pointer location is at the top of the frame. */
9605 /* Register save area */
9609 /* On SEH target, registers are pushed just before the frame pointer
9610 location. */
9614 /* Align and set SSE register save area. */
9616 {
9617 /* The only ABI that has saved SSE registers (Win64) also has a
9618 16-byte aligned default stack, and thus we don't need to be
9619 within the re-aligned local stack frame to save them. */
9623 }
9626 /* The re-aligned stack starts here. Values before this point are not
9627 directly comparable with values below this point. In order to make
9628 sure that no value happens to be the same before and after, force
9629 the alignment computation below to add a non-zero value. */
9633 /* Va-arg area */
9637 /* Align start of frame for local function. */
9646 /* Frame pointer points here. */
9651 /* Add outgoing arguments area. Can be skipped if we eliminated
9652 all the function calls as dead code.
9653 Skipping is however impossible when function calls alloca. Alloca
9654 expander assumes that last crtl->outgoing_args_size
9655 of stack frame are unused. */
9659 {
9662 }
9663 else
9666 /* Align stack boundary. Only needed if we're calling another function
9667 or using alloca. */
9672 /* We've reached end of stack frame. */
9675 /* Size prologue needs to allocate. */
9686 {
9692 }
9693 else
9697 /* The SEH frame pointer location is near the bottom of the frame.
9698 This is enforced by the fact that the difference between the
9699 stack pointer and the frame pointer is limited to 240 bytes in
9700 the unwind data structure. */
9702 {
9703 HOST_WIDE_INT diff;
9705 /* If we can leave the frame pointer where it is, do so. Also, returns
9706 the establisher frame for __builtin_frame_address (0). */
9711 {
9712 /* Ideally we'd determine what portion of the local stack frame
9713 (within the constraint of the lowest 240) is most heavily used.
9714 But without that complication, simply bias the frame pointer
9715 by 128 bytes so as to maximize the amount of the local stack
9716 frame that is addressable with 8-bit offsets. */
9718 }
9719 }
9720 }
9722 /* This is semi-inlined memory_address_length, but simplified
9723 since we know that we're always dealing with reg+offset, and
9724 to avoid having to create and discard all that rtl. */
9728 {
9732 {
9733 /* EBP and R13 cannot be encoded without an offset. */
9735 }
9739 /* ESP and R12 must be encoded with a SIB byte. */
9741 len++;
9744 }
9746 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9747 The valid base registers are taken from CFUN->MACHINE->FS. */
9749 static rtx
9751 {
9757 {
9758 /* Choose the base register most likely to allow the most scheduling
9759 opportunities. Generally FP is valid throughout the function,
9760 while DRAP must be reloaded within the epilogue. But choose either
9761 over the SP due to increased encoding size. */
9764 {
9767 }
9769 {
9772 }
9774 {
9777 }
9778 }
9779 else
9780 {
9781 HOST_WIDE_INT toffset;
9784 /* Choose the base register with the smallest address encoding.
9785 With a tie, choose FP > DRAP > SP. */
9787 {
9791 }
9793 {
9797 {
9801 }
9802 }
9804 {
9808 {
9812 }
9813 }
9814 }
9818 }
9820 /* Emit code to save registers in the prologue. */
9822 static void
9824 {
9826 rtx insn;
9830 {
9833 }
9834 }
9836 /* Emit a single register save at CFA - CFA_OFFSET. */
9838 static void
9840 HOST_WIDE_INT cfa_offset)
9841 {
9849 /* For SSE saves, we need to indicate the 128-bit alignment. */
9860 /* When saving registers into a re-aligned local stack frame, avoid
9861 any tricky guessing by dwarf2out. */
9863 {
9867 {
9868 /* A bit of a hack. We force the DRAP register to be saved in
9869 the re-aligned stack frame, which provides us with a copy
9870 of the CFA that will last past the prologue. Install it. */
9876 }
9877 else
9878 {
9879 /* The frame pointer is a stable reference within the
9880 aligned frame. Use it. */
9887 }
9888 }
9890 /* The memory may not be relative to the current CFA register,
9891 which means that we may need to generate a new pattern for
9892 use by the unwind info. */
9894 {
9899 }
9900 }
9902 /* Emit code to save registers using MOV insns.
9903 First register is stored at CFA - CFA_OFFSET. */
9904 static void
9906 {
9911 {
9914 }
9915 }
9917 /* Emit code to save SSE registers using MOV insns.
9918 First register is stored at CFA - CFA_OFFSET. */
9919 static void
9921 {
9926 {
9929 }
9930 }
9934 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9935 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9936 Don't add the note if the previously saved value will be left untouched
9937 within stack red-zone till return, as unwinders can find the same value
9938 in the register and on the stack. */
9940 static void
9942 {
9948 {
9951 }
9952 else
9953 queued_cfa_restores
9955 }
9957 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9959 static void
9961 {
9962 rtx last;
9966 ;
9971 }
9973 /* Expand prologue or epilogue stack adjustment.
9974 The pattern exist to put a dependency on all ebp-based memory accesses.
9975 STYLE should be negative if instructions should be marked as frame related,
9976 zero if %r11 register is live and cannot be freely used and positive
9977 otherwise. */
9979 static void
9982 {
9984 rtx insn;
9991 else
9992 {
9993 rtx tmp;
9994 /* r11 is used by indirect sibcall return as well, set before the
9995 epilogue and used after the epilogue. */
9998 else
9999 {
10003 }
10009 }
10016 {
10017 rtx r;
10027 }
10029 {
10032 {
10036 }
10037 }
10040 {
10045 {
10048 }
10050 {
10053 }
10054 else
10055 {
10056 /* Else there are two possibilities: SP itself, which we set
10057 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10058 taken care of this by hand along the eh_return path. */
10061 }
10065 }
10066 }
10068 /* Find an available register to be used as dynamic realign argument
10069 pointer regsiter. Such a register will be written in prologue and
10070 used in begin of body, so it must not be
10071 1. parameter passing register.
10072 2. GOT pointer.
10073 We reuse static-chain register if it is available. Otherwise, we
10074 use DI for i386 and R13 for x86-64. We chose R13 since it has
10075 shorter encoding.
10077 Return: the regno of chosen register. */
10079 static unsigned int
10081 {
10085 {
10086 /* Use R13 for nested function or function need static chain.
10087 Since function with tail call may use any caller-saved
10088 registers in epilogue, DRAP must not use caller-saved
10089 register in such case. */
10094 }
10095 else
10096 {
10097 /* Use DI for nested function or function need static chain.
10098 Since function with tail call may use any caller-saved
10099 registers in epilogue, DRAP must not use caller-saved
10100 register in such case. */
10104 /* Reuse static chain register if it isn't used for parameter
10105 passing. */
10107 {
10111 }
10113 }
10114 }
10116 /* Return minimum incoming stack alignment. */
10118 static unsigned int
10120 {
10123 /* Prefer the one specified at command line. */
10126 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10127 if -mstackrealign is used, it isn't used for sibcall check and
10128 estimated stack alignment is 128bit. */
10130 && !TARGET_64BIT
10131 && ix86_force_align_arg_pointer
10134 else
10137 /* Incoming stack alignment can be changed on individual functions
10138 via force_align_arg_pointer attribute. We use the smallest
10139 incoming stack boundary. */
10145 /* The incoming stack frame has to be aligned at least at
10146 parm_stack_boundary. */
10150 /* Stack at entrance of main is aligned by runtime. We use the
10151 smallest incoming stack boundary. */
10159 }
10161 /* Update incoming stack boundary and estimated stack alignment. */
10163 static void
10165 {
10166 ix86_incoming_stack_boundary
10169 /* x86_64 vararg needs 16byte stack alignment for register save
10170 area. */
10175 }
10177 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10178 needed or an rtx for DRAP otherwise. */
10180 static rtx
10182 {
10187 {
10188 /* Assign DRAP to vDRAP and returns vDRAP */
10190 rtx drap_vreg;
10191 rtx arg_ptr;
10204 {
10207 }
10209 }
10210 else
10212 }
10214 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10216 static rtx
10218 {
10220 }
10223 rtx reg;
10225 };
10227 /* Return a short-lived scratch register for use on function entry.
10228 In 32-bit mode, it is valid only after the registers are saved
10229 in the prologue. This register must be released by means of
10230 release_scratch_register_on_entry once it is dead. */
10232 static void
10234 {
10240 {
10241 /* We always use R11 in 64-bit mode. */
10243 }
10244 else
10245 {
10247 bool fastcall_p
10249 bool thiscall_p
10253 int drap_regno
10256 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10257 for the static chain register. */
10261 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10262 for the static chain register. */
10267 /* ecx is the static chain register. */
10269 && !static_chain_p
10274 /* esi is the static chain register. */
10280 else
10281 {
10284 }
10285 }
10289 {
10292 }
10293 }
10295 /* Release a scratch register obtained from the preceding function. */
10297 static void
10299 {
10301 {
10305 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10311 }
10312 }
10314 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10316 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10318 static void
10320 {
10321 /* We skip the probe for the first interval + a small dope of 4 words and
10322 probe that many bytes past the specified size to maintain a protection
10323 area at the botton of the stack. */
10327 /* See if we have a constant small number of probes to generate. If so,
10328 that's the easy case. The run-time loop is made up of 11 insns in the
10329 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10330 for n # of intervals. */
10332 {
10336 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10337 values of N from 1 until it exceeds SIZE. If only one probe is
10338 needed, this will not generate any code. Then adjust and probe
10339 to PROBE_INTERVAL + SIZE. */
10341 {
10343 {
10346 }
10347 else
10354 }
10358 else
10366 /* Adjust back to account for the additional first interval. */
10370 }
10372 /* Otherwise, do the same as above, but in a loop. Note that we must be
10373 extra careful with variables wrapping around because we might be at
10374 the very top (or the very bottom) of the address space and we have
10375 to be able to handle this case properly; in particular, we use an
10376 equality test for the loop condition. */
10377 else
10378 {
10379 HOST_WIDE_INT rounded_size;
10385 /* Step 1: round SIZE to the previous multiple of the interval. */
10390 /* Step 2: compute initial and final value of the loop counter. */
10392 /* SP = SP_0 + PROBE_INTERVAL. */
10397 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10401 stack_pointer_rtx)));
10404 /* Step 3: the loop
10406 while (SP != LAST_ADDR)
10407 {
10408 SP = SP + PROBE_INTERVAL
10409 probe at SP
10410 }
10412 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10413 values of N from 1 until it is equal to ROUNDED_SIZE. */
10418 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10419 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10422 {
10427 }
10429 /* Adjust back to account for the additional first interval. */
10435 }
10439 /* Even if the stack pointer isn't the CFA register, we need to correctly
10440 describe the adjustments made to it, in particular differentiate the
10441 frame-related ones from the frame-unrelated ones. */
10443 {
10456 }
10458 /* Make sure nothing is scheduled before we are done. */
10460 }
10462 /* Adjust the stack pointer up to REG while probing it. */
10466 {
10476 /* Jump to END_LAB if SP == LAST_ADDR. */
10484 /* SP = SP + PROBE_INTERVAL. */
10488 /* Probe at SP. */
10499 }
10501 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10502 inclusive. These are offsets from the current stack pointer. */
10504 static void
10506 {
10507 /* See if we have a constant small number of probes to generate. If so,
10508 that's the easy case. The run-time loop is made up of 7 insns in the
10509 generic case while the compile-time loop is made up of n insns for n #
10510 of intervals. */
10512 {
10513 HOST_WIDE_INT i;
10515 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10516 it exceeds SIZE. If only one probe is needed, this will not
10517 generate any code. Then probe at FIRST + SIZE. */
10524 }
10526 /* Otherwise, do the same as above, but in a loop. Note that we must be
10527 extra careful with variables wrapping around because we might be at
10528 the very top (or the very bottom) of the address space and we have
10529 to be able to handle this case properly; in particular, we use an
10530 equality test for the loop condition. */
10531 else
10532 {
10539 /* Step 1: round SIZE to the previous multiple of the interval. */
10544 /* Step 2: compute initial and final value of the loop counter. */
10546 /* TEST_OFFSET = FIRST. */
10549 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10553 /* Step 3: the loop
10555 while (TEST_ADDR != LAST_ADDR)
10556 {
10557 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10558 probe at TEST_ADDR
10559 }
10561 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10562 until it is equal to ROUNDED_SIZE. */
10567 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10568 that SIZE is equal to ROUNDED_SIZE. */
10573 stack_pointer_rtx,
10578 }
10580 /* Make sure nothing is scheduled before we are done. */
10582 }
10584 /* Probe a range of stack addresses from REG to END, inclusive. These are
10585 offsets from the current stack pointer. */
10589 {
10599 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10607 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10611 /* Probe at TEST_ADDR. */
10624 }
10626 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10627 to be generated in correct form. */
10628 static void
10630 {
10631 /* Check if stack realign is really needed after reload, and
10632 stores result in cfun */
10633 unsigned int incoming_stack_boundary
10642 {
10643 /* After stack_realign_needed is finalized, we can't no longer
10644 change it. */
10647 }
10649 /* If the only reason for frame_pointer_needed is that we conservatively
10650 assumed stack realignment might be needed, but in the end nothing that
10651 needed the stack alignment had been spilled, clear frame_pointer_needed
10652 and say we don't need stack realignment. */
10654 && frame_pointer_needed
10656 && flag_omit_frame_pointer
10658 && !ix86_current_function_calls_tls_descriptor
10667 {
10669 basic_block bb;
10676 HARD_FRAME_POINTER_REGNUM);
10678 {
10679 rtx insn;
10683 set_up_by_prologue))
10684 {
10688 }
10689 }
10691 /* If drap has been set, but it actually isn't live at the start
10692 of the function, there is no reason to set it up. */
10694 {
10697 {
10700 }
10701 }
10702 else
10717 }
10721 }
10723 /* Expand the prologue into a bunch of separate insns. */
10725 void
10727 {
10732 HOST_WIDE_INT allocate;
10738 /* DRAP should not coexist with stack_realign_fp */
10743 /* Initialize CFA state for before the prologue. */
10747 /* Track SP offset to the CFA. We continue tracking this after we've
10748 swapped the CFA register away from SP. In the case of re-alignment
10749 this is fudged; we're interested to offsets within the local frame. */
10756 {
10757 /* We should have already generated an error for any use of
10758 ms_hook on a nested function. */
10761 /* Check if profiling is active and we shall use profiling before
10762 prologue variant. If so sorry. */
10767 /* In ix86_asm_output_function_label we emitted:
10768 8b ff movl.s %edi,%edi
10769 55 push %ebp
10770 8b ec movl.s %esp,%ebp
10772 This matches the hookable function prologue in Win32 API
10773 functions in Microsoft Windows XP Service Pack 2 and newer.
10774 Wine uses this to enable Windows apps to hook the Win32 API
10775 functions provided by Wine.
10777 What that means is that we've already set up the frame pointer. */
10781 {
10784 /* We've decided to use the frame pointer already set up.
10785 Describe this to the unwinder by pretending that both
10786 push and mov insns happen right here.
10788 Putting the unwind info here at the end of the ms_hook
10789 is done so that we can make absolutely certain we get
10790 the required byte sequence at the start of the function,
10791 rather than relying on an assembler that can produce
10792 the exact encoding required.
10794 However it does mean (in the unpatched case) that we have
10795 a 1 insn window where the asynchronous unwind info is
10796 incorrect. However, if we placed the unwind info at
10797 its correct location we would have incorrect unwind info
10798 in the patched case. Which is probably all moot since
10799 I don't expect Wine generates dwarf2 unwind info for the
10800 system libraries that use this feature. */
10806 stack_pointer_rtx);
10814 /* Note that gen_push incremented m->fs.cfa_offset, even
10815 though we didn't emit the push insn here. */
10819 }
10820 else
10821 {
10822 /* The frame pointer is not needed so pop %ebp again.
10823 This leaves us with a pristine state. */
10825 }
10826 }
10828 /* The first insn of a function that accepts its static chain on the
10829 stack is to push the register that would be filled in by a direct
10830 call. This insn will be skipped by the trampoline. */
10832 {
10836 /* We don't want to interpret this push insn as a register save,
10837 only as a stack adjustment. The real copy of the register as
10838 a save will be done later, if needed. */
10843 }
10845 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10846 of DRAP is needed and stack realignment is really needed after reload */
10848 {
10851 /* Only need to push parameter pointer reg if it is caller saved. */
10853 {
10854 /* Push arg pointer reg */
10857 }
10859 /* Grab the argument pointer. */
10866 /* Align the stack. */
10868 stack_pointer_rtx,
10872 /* Replicate the return address on the stack so that return
10873 address can be reached via (argp - 1) slot. This is needed
10874 to implement macro RETURN_ADDR_RTX and intrinsic function
10875 expand_builtin_return_addr etc. */
10881 /* For the purposes of frame and register save area addressing,
10882 we've started over with a new frame. */
10885 }
10891 {
10892 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10893 slower on all targets. Also sdb doesn't like it. */
10897 /* Push registers now, before setting the frame pointer
10898 on SEH target. */
10900 && TARGET_SEH
10902 {
10906 }
10909 {
10917 }
10918 }
10921 {
10922 /* If saving registers via PUSH, do so now. */
10924 {
10928 }
10930 /* When using red zone we may start register saving before allocating
10931 the stack frame saving one cycle of the prologue. However, avoid
10932 doing this if we have to probe the stack; at least on x86_64 the
10933 stack probe can turn into a call that clobbers a red zone location. */
10935 && (! TARGET_STACK_PROBE
10937 {
10940 }
10941 }
10944 {
10948 /* The computation of the size of the re-aligned stack frame means
10949 that we must allocate the size of the register save area before
10950 performing the actual alignment. Otherwise we cannot guarantee
10951 that there's enough storage above the realignment point. */
10958 /* Align the stack. */
10960 stack_pointer_rtx,
10963 /* For the purposes of register save area addressing, the stack
10964 pointer is no longer valid. As for the value of sp_offset,
10965 see ix86_compute_frame_layout, which we need to match in order
10966 to pass verification of stack_pointer_offset at the end. */
10969 }
10974 {
10975 /* We start to count from ARG_POINTER. */
10978 /* If it was realigned, take into account the fake frame. */
10980 {
10987 /* This over-estimates by 1 minimal-stack-alignment-unit but
10988 mitigates that by counting in the new return address slot. */
10989 current_function_dynamic_stack_size
10991 }
10994 }
10996 /* On SEH target with very large frame size, allocate an area to save
10997 SSE registers (as the very large allocation won't be described). */
11001 {
11002 HOST_WIDE_INT sse_size =
11007 /* No need to do stack checking as the area will be immediately
11008 written. */
11015 }
11017 /* The stack has already been decremented by the instruction calling us
11018 so probe if the size is non-negative to preserve the protection area. */
11020 {
11021 /* We expect the registers to be saved when probes are used. */
11025 {
11028 {
11031 }
11032 }
11033 else
11034 {
11041 {
11043 {
11046 }
11047 else
11049 }
11050 else
11051 {
11053 {
11057 }
11058 else
11060 }
11061 }
11062 }
11065 ;
11068 {
11072 }
11073 else
11074 {
11086 {
11089 /* Note that SEH directives need to continue tracking the stack
11090 pointer even after the frame pointer has been set up. */
11092 {
11096 }
11097 }
11100 {
11105 {
11109 }
11110 }
11115 /* Use the fact that AX still contains ALLOCATE. */
11117 ? gen_pro_epilogue_adjust_stack_di_sub
11124 {
11132 }
11135 /* Use stack_pointer_rtx for relative addressing so that code
11136 works for realigned stack, too. */
11138 {
11145 }
11147 {
11152 }
11153 }
11156 /* If we havn't already set up the frame pointer, do so now. */
11158 {
11170 }
11178 /* We don't use pic-register for pe-coff target. */
11180 && !TARGET_PECOFF
11183 {
11190 }
11193 {
11195 {
11197 {
11207 label));
11211 }
11212 else
11214 }
11215 else
11216 {
11220 }
11221 }
11223 /* In the pic_reg_used case, make sure that the got load isn't deleted
11224 when mcount needs it. Blockage to avoid call movement across mcount
11225 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11226 note. */
11231 {
11232 /* vDRAP is setup but after reload it turns out stack realign
11233 isn't necessary, here we will emit prologue to setup DRAP
11234 without stack realign adjustment */
11237 }
11239 /* Prevent instructions from being scheduled into register save push
11240 sequence when access to the redzone area is done through frame pointer.
11241 The offset between the frame pointer and the stack pointer is calculated
11242 relative to the value of the stack pointer at the end of the function
11243 prologue, and moving instructions that access redzone area via frame
11244 pointer inside push sequence violates this assumption. */
11248 /* Emit cld instruction if stringops are used in the function. */
11252 /* SEH requires that the prologue end within 256 bytes of the start of
11253 the function. Prevent instruction schedules that would extend that.
11254 Further, prevent alloca modifications to the stack pointer from being
11255 combined with prologue modifications. */
11258 }
11260 /* Emit code to restore REG using a POP insn. */
11262 static void
11264 {
11273 {
11274 /* Previously we'd represented the CFA as an expression
11275 like *(%ebp - 8). We've just popped that value from
11276 the stack, which means we need to reset the CFA to
11277 the drap register. This will remain until we restore
11278 the stack pointer. */
11282 /* This means that the DRAP register is valid for addressing too. */
11285 }
11288 {
11295 }
11297 /* When the frame pointer is the CFA, and we pop it, we are
11298 swapping back to the stack pointer as the CFA. This happens
11299 for stack frames that don't allocate other data, so we assume
11300 the stack pointer is now pointing at the return address, i.e.
11301 the function entry state, which makes the offset be 1 word. */
11303 {
11306 {
11314 }
11315 }
11316 }
11318 /* Emit code to restore saved registers using POP insns. */
11320 static void
11322 {
11328 }
11330 /* Emit code and notes for the LEAVE instruction. */
11332 static void
11334 {
11346 {
11354 }
11357 }
11359 /* Emit code to restore saved registers using MOV insns.
11360 First register is restored from CFA - CFA_OFFSET. */
11361 static void
11364 {
11370 {
11379 {
11380 /* Previously we'd represented the CFA as an expression
11381 like *(%ebp - 8). We've just popped that value from
11382 the stack, which means we need to reset the CFA to
11383 the drap register. This will remain until we restore
11384 the stack pointer. */
11388 /* This means that the DRAP register is valid for addressing. */
11390 }
11391 else
11395 }
11396 }
11398 /* Emit code to restore saved registers using MOV insns.
11399 First register is restored from CFA - CFA_OFFSET. */
11400 static void
11403 {
11408 {
11410 rtx mem;
11420 }
11421 }
11423 /* Restore function stack, frame, and registers. */
11425 void
11427 {
11443 /* The FP must be valid if the frame pointer is present. */
11448 /* We must have *some* valid pointer to the stack frame. */
11451 /* The DRAP is never valid at this point. */
11454 /* See the comment about red zone and frame
11455 pointer usage in ix86_expand_prologue. */
11462 /* Determine the CFA offset of the end of the red-zone. */
11465 {
11466 /* The red-zone begins below the return address. */
11469 /* When the register save area is in the aligned portion of
11470 the stack, determine the maximum runtime displacement that
11471 matches up with the aligned frame. */
11475 }
11477 /* Special care must be taken for the normal return case of a function
11478 using eh_return: the eax and edx registers are marked as saved, but
11479 not restored along this path. Adjust the save location to match. */
11483 /* EH_RETURN requires the use of moves to function properly. */
11486 /* SEH requires the use of pops to identify the epilogue. */
11489 /* If we're only restoring one register and sp is not valid then
11490 using a move instruction to restore the register since it's
11491 less work than reloading sp and popping the register. */
11504 && TARGET_USE_LEAVE
11508 else
11512 {
11513 /* Ensure that the entire register save area is addressable via
11514 the stack pointer, if we will restore via sp. */
11519 {
11523 style,
11525 }
11526 }
11528 /* If there are any SSE registers to restore, then we have to do it
11529 via moves, since there's obviously no pop for SSE regs. */
11535 {
11536 rtx t;
11541 /* eh_return epilogues need %ecx added to the stack pointer. */
11543 {
11546 /* Stack align doesn't work with eh_return. */
11548 /* Neither does regparm nested functions. */
11552 {
11560 /* Note that we use SA as a temporary CFA, as the return
11561 address is at the proper place relative to it. We
11562 pretend this happens at the FP restore insn because
11563 prior to this insn the FP would be stored at the wrong
11564 offset relative to SA, and after this insn we have no
11565 other reasonable register to use for the CFA. We don't
11566 bother resetting the CFA to the SP for the duration of
11567 the return insn. */
11580 }
11581 else
11582 {
11590 {
11594 UNITS_PER_WORD));
11596 }
11597 }
11600 }
11601 }
11602 else
11603 {
11604 /* SEH requires that the function end with (1) a stack adjustment
11605 if necessary, (2) a sequence of pops, and (3) a return or
11606 jump instruction. Prevent insns from the function body from
11607 being scheduled into this sequence. */
11609 {
11610 /* Prevent a catch region from being adjacent to the standard
11611 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11612 several other flags that would be interesting to test are
11613 not yet set up. */
11616 else
11618 }
11620 /* First step is to deallocate the stack frame so that we can
11621 pop the registers. Also do it on SEH target for very large
11622 frame as the emitted instructions aren't allowed by the ABI in
11623 epilogues. */
11625 || (TARGET_SEH
11628 {
11633 }
11635 {
11639 style,
11641 }
11644 }
11646 /* If we used a stack pointer and haven't already got rid of it,
11647 then do so now. */
11649 {
11650 /* If the stack pointer is valid and pointing at the frame
11651 pointer store address, then we only need a pop. */
11654 /* Leave results in shorter dependency chains on CPUs that are
11655 able to grok it fast. */
11660 else
11661 {
11663 hard_frame_pointer_rtx,
11666 }
11667 }
11670 {
11672 rtx insn;
11698 }
11700 /* At this point the stack pointer must be valid, and we must have
11701 restored all of the registers. We may not have deallocated the
11702 entire stack frame. We've delayed this until now because it may
11703 be possible to merge the local stack deallocation with the
11704 deallocation forced by ix86_static_chain_on_stack. */
11709 {
11713 }
11714 else
11717 /* Sibcall epilogues don't want a return instruction. */
11719 {
11722 }
11725 {
11728 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11729 address, do explicit add, and jump indirectly to the caller. */
11732 {
11734 rtx insn;
11736 /* There is no "pascal" calling convention in any 64bit ABI. */
11753 }
11754 else
11756 }
11757 else
11760 /* Restore the state back to the state from the prologue,
11761 so that it's correct for the next epilogue. */
11763 }
11765 /* Reset from the function's potential modifications. */
11767 static void
11769 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11770 {
11773 #if TARGET_MACHO
11774 /* Mach-O doesn't support labels at the end of objects, so if
11775 it looks like we might want one, insert a NOP. */
11776 {
11782 {
11783 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11784 notes only, instead set their CODE_LABEL_NUMBER to -1,
11785 otherwise there would be code generation differences
11786 in between -g and -g0. */
11790 }
11800 }
11801 #endif
11803 }
11805 /* Return a scratch register to use in the split stack prologue. The
11806 split stack prologue is used for -fsplit-stack. It is the first
11807 instructions in the function, even before the regular prologue.
11808 The scratch register can be any caller-saved register which is not
11809 used for parameters or for the static chain. */
11811 static unsigned int
11813 {
11816 else
11817 {
11830 {
11832 {
11836 }
11838 }
11840 {
11844 }
11846 {
11849 else
11850 {
11852 {
11856 }
11858 }
11859 }
11860 else
11861 {
11862 /* FIXME: We could make this work by pushing a register
11863 around the addition and comparison. */
11866 }
11867 }
11868 }
11870 /* A SYMBOL_REF for the function which allocates new stackspace for
11871 -fsplit-stack. */
11875 /* A SYMBOL_REF for the more stack function when using the large
11876 model. */
11880 /* Handle -fsplit-stack. These are the first instructions in the
11881 function, even before the regular prologue. */
11883 void
11885 {
11887 HOST_WIDE_INT allocate;
11892 rtx fn;
11900 /* This is the label we will branch to if we have enough stack
11901 space. We expect the basic block reordering pass to reverse this
11902 branch if optimizing, so that we branch in the unlikely case. */
11905 /* We need to compare the stack pointer minus the frame size with
11906 the stack boundary in the TCB. The stack boundary always gives
11907 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11908 can compare directly. Otherwise we need to do an addition. */
11911 UNSPEC_STACK_CHECK);
11916 else
11917 {
11919 rtx offset;
11921 /* We need a scratch register to hold the stack pointer minus
11922 the required frame size. Since this is the very start of the
11923 function, the scratch register can be any caller-saved
11924 register which is not used for parameters. */
11931 {
11932 /* We don't use ix86_gen_add3 in this case because it will
11933 want to split to lea, but when not optimizing the insn
11934 will not be split after this point. */
11937 offset)));
11938 }
11939 else
11940 {
11943 stack_pointer_rtx));
11944 }
11946 }
11952 /* Mark the jump as very likely to be taken. */
11960 /* Get more stack space. We pass in the desired stack space and the
11961 size of the arguments to copy to the new stack. In 32-bit mode
11962 we push the parameters; __morestack will return on a new stack
11963 anyhow. In 64-bit mode we pass the parameters in r10 and
11964 r11. */
11969 {
11975 /* If this function uses a static chain, it will be in %r10.
11976 Preserve it across the call to __morestack. */
11978 {
11979 rtx rax;
11984 }
11988 {
11989 HOST_WIDE_INT argval;
11992 /* When using the large model we need to load the address
11993 into a register, and we've run out of registers. So we
11994 switch to a different calling convention, and we call a
11995 different function: __morestack_large. We pass the
11996 argument size in the upper 32 bits of r10 and pass the
11997 frame size in the lower 32 bits. */
12002 split_stack_fn_large =
12006 {
12016 UNSPEC_GOT);
12022 }
12023 else
12030 }
12031 else
12032 {
12036 }
12039 }
12040 else
12041 {
12044 }
12050 /* In order to make call/return prediction work right, we now need
12051 to execute a return instruction. See
12052 libgcc/config/i386/morestack.S for the details on how this works.
12054 For flow purposes gcc must not see this as a return
12055 instruction--we need control flow to continue at the subsequent
12056 label. Therefore, we use an unspec. */
12060 /* If we are in 64-bit mode and this function uses a static chain,
12061 we saved %r10 in %rax before calling _morestack. */
12066 /* If this function calls va_start, we need to store a pointer to
12067 the arguments on the old stack, because they may not have been
12068 all copied to the new stack. At this point the old stack can be
12069 found at the frame pointer value used by __morestack, because
12070 __morestack has set that up before calling back to us. Here we
12071 store that pointer in a scratch register, and in
12072 ix86_expand_prologue we store the scratch register in a stack
12073 slot. */
12075 {
12077 rtx frame_reg;
12084 /* 64-bit:
12085 fp -> old fp value
12086 return address within this function
12087 return address of caller of this function
12088 stack arguments
12089 So we add three words to get to the stack arguments.
12091 32-bit:
12092 fp -> old fp value
12093 return address within this function
12094 first argument to __morestack
12095 second argument to __morestack
12096 return address of caller of this function
12097 stack arguments
12098 So we add five words to get to the stack arguments.
12099 */
12110 }
12115 /* If this function calls va_start, we now have to set the scratch
12116 register for the case where we do not call __morestack. In this
12117 case we need to set it based on the stack pointer. */
12119 {
12126 }
12127 }
12129 /* We may have to tell the dataflow pass that the split stack prologue
12130 is initializing a scratch register. */
12132 static void
12134 {
12136 {
12139 }
12140 }
12141 \f
12142 /* Extract the parts of an RTL expression that is a valid memory address
12143 for an instruction. Return 0 if the structure of the address is
12144 grossly off. Return -1 if the address contains ASHIFT, so it is not
12145 strictly valid, but still used for computing length of lea instruction. */
12147 int
12149 {
12154 rtx tmp;
12158 /* Allow zero-extended SImode addresses,
12159 they will be emitted with addr32 prefix. */
12161 {
12164 {
12168 }
12171 {
12178 }
12179 }
12181 /* Allow SImode subregs of DImode addresses,
12182 they will be emitted with addr32 prefix. */
12184 {
12187 {
12191 }
12192 }
12197 {
12200 else
12202 }
12204 {
12209 do
12210 {
12215 }
12222 {
12225 {
12250 /* FALLTHRU */
12254 && TARGET_TLS_DIRECT_SEG_REFS
12257 else
12264 /* FALLTHRU */
12271 else
12286 }
12287 }
12288 }
12290 {
12293 }
12295 {
12296 /* We're called for lea too, which implements ashift on occasion. */
12306 }
12307 else
12311 {
12313 ;
12316 ;
12317 else
12319 }
12321 /* Extract the integral value of scale. */
12323 {
12327 }
12332 /* Avoid useless 0 displacement. */
12336 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12341 {
12342 rtx tmp;
12345 }
12347 /* Special case: %ebp cannot be encoded as a base without a displacement.
12348 Similarly %r13. */
12350 && base_reg
12359 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12360 Avoid this by transforming to [%esi+0].
12361 Reload calls address legitimization without cfun defined, so we need
12362 to test cfun for being non-NULL. */
12368 /* Special case: encode reg+reg instead of reg*2. */
12372 /* Special case: scaling cannot be encoded without base or displacement. */
12383 }
12384 \f
12385 /* Return cost of the memory address x.
12386 For i386, it is better to use a complex address than let gcc copy
12387 the address into a reg and make a new pseudo. But not if the address
12388 requires to two regs - that would mean more pseudos with longer
12389 lifetimes. */
12390 static int
12392 addr_space_t as ATTRIBUTE_UNUSED,
12394 {
12406 /* Attempt to minimize number of registers in the address. */
12412 cost++;
12419 cost++;
12421 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12422 since it's predecode logic can't detect the length of instructions
12423 and it degenerates to vector decoded. Increase cost of such
12424 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12425 to split such addresses or even refuse such addresses at all.
12427 Following addressing modes are affected:
12428 [base+scale*index]
12429 [scale*index+disp]
12430 [base+index]
12432 The first and last case may be avoidable by explicitly coding the zero in
12433 memory address, but I don't have AMD-K6 machine handy to check this
12434 theory. */
12443 }
12444 \f
12445 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12446 this is used for to form addresses to local data when -fPIC is in
12447 use. */
12449 static bool
12451 {
12454 }
12456 /* Determine if a given RTX is a valid constant. We already know this
12457 satisfies CONSTANT_P. */
12459 static bool
12461 {
12463 {
12468 {
12472 }
12477 /* Only some unspecs are valid as "constants". */
12480 {
12496 }
12498 /* We must have drilled down to a symbol. */
12503 /* FALLTHRU */
12506 /* TLS symbols are never valid. */
12510 /* DLLIMPORT symbols are never valid. */
12515 #if TARGET_MACHO
12516 /* mdynamic-no-pic */
12519 #endif
12535 }
12537 /* Otherwise we handle everything else in the move patterns. */
12539 }
12541 /* Determine if it's legal to put X into the constant pool. This
12542 is not possible for the address of thread-local symbols, which
12543 is checked above. */
12545 static bool
12547 {
12548 /* We can always put integral constants and vectors in memory. */
12550 {
12558 }
12560 }
12562 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12563 otherwise zero. */
12565 static bool
12567 {
12573 }
12576 /* Nonzero if the constant value X is a legitimate general operand
12577 when generating PIC code. It is given that flag_pic is on and
12578 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12580 bool
12582 {
12583 rtx inner;
12586 {
12593 /* Only some unspecs are valid as "constants". */
12596 {
12609 }
12610 /* FALLTHRU */
12618 }
12619 }
12621 /* Determine if a given CONST RTX is a valid memory displacement
12622 in PIC mode. */
12624 bool
12626 {
12629 /* In 64bit mode we can allow direct addresses of symbols and labels
12630 when they are not dynamic symbols. */
12632 {
12636 {
12660 /* FALLTHRU */
12663 /* TLS references should always be enclosed in UNSPEC.
12664 The dllimported symbol needs always to be resolved. */
12670 {
12678 /* Function-symbols need to be resolved only for
12679 large-model.
12680 For the small-model we don't need to resolve anything
12681 here. */
12686 /* Non-external symbols don't need to be resolved for
12687 large, and medium-model. */
12692 }
12701 }
12702 }
12708 {
12709 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12710 of GOT tables. We should not need these anyway. */
12722 }
12726 {
12731 }
12740 {
12744 /* We need to check for both symbols and labels because VxWorks loads
12745 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12746 details. */
12750 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12751 While ABI specify also 32bit relocation but we don't produce it in
12752 small PIC model at all. */
12774 }
12777 }
12779 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12780 replace the input X, or the original X if no replacement is called for.
12781 The output parameter *WIN is 1 if the calling macro should goto WIN,
12782 0 if it should not. */
12784 bool
12789 {
12790 /* Reload can generate:
12792 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12793 (reg:DI 97))
12794 (reg:DI 2 cx))
12796 This RTX is rejected from ix86_legitimate_address_p due to
12797 non-strictness of base register 97. Following this rejection,
12798 reload pushes all three components into separate registers,
12799 creating invalid memory address RTX.
12801 Following code reloads only the invalid part of the
12802 memory address RTX. */
12808 {
12814 {
12819 }
12823 {
12828 }
12832 }
12835 }
12837 /* Determine if op is suitable RTX for an address register.
12838 Return naked register if a register or a register subreg is
12839 found, otherwise return NULL_RTX. */
12841 static rtx
12843 {
12846 /* Only SImode or DImode registers can form the address. */
12853 {
12861 /* Don't allow SUBREGs that span more than a word. It can
12862 lead to spill failures when the register is one word out
12863 of a two word structure. */
12867 /* Allow only SUBREGs of non-eliminable hard registers. */
12870 }
12872 /* Op is not a register. */
12874 }
12876 /* Recognizes RTL expressions that are valid memory addresses for an
12877 instruction. The MODE argument is the machine mode for the MEM
12878 expression that wants to use this address.
12880 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12881 convert common non-canonical forms to canonical form so that they will
12882 be recognized. */
12884 static bool
12887 {
12890 HOST_WIDE_INT scale;
12894 /* Decomposition failed. */
12903 /* Validate base register. */
12905 {
12913 /* Base is not valid. */
12915 }
12917 /* Validate index register. */
12919 {
12927 /* Index is not valid. */
12929 }
12931 /* Index and base should have the same mode. */
12936 /* Address override works only on the (%reg) part of %fs:(%reg). */
12942 /* Validate scale factor. */
12944 {
12946 /* Scale without index. */
12950 /* Scale is not a valid multiplier. */
12952 }
12954 /* Validate displacement. */
12956 {
12961 {
12962 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12963 used. While ABI specify also 32bit relocations, we don't produce
12964 them at all and use IP relative instead. */
12971 /* 64bit address unspec. */
12991 /* Invalid address unspec. */
12993 }
12996 && (flag_pic
12997 || (TARGET_MACHO
12998 #if TARGET_MACHO
12999 && MACHOPIC_INDIRECT
13001 #endif
13002 )))
13003 {
13005 is_legitimate_pic:
13007 {
13008 /* foo@dtpoff(%rX) is ok. */
13015 /* Non-constant pic memory reference. */
13017 }
13020 /* Displacement is an invalid pic construct. */
13022 #if TARGET_MACHO
13025 /* displacment must be referenced via non_lazy_pointer */
13027 #endif
13029 /* This code used to verify that a symbolic pic displacement
13030 includes the pic_offset_table_rtx register.
13032 While this is good idea, unfortunately these constructs may
13033 be created by "adds using lea" optimization for incorrect
13034 code like:
13036 int a;
13037 int foo(int i)
13038 {
13039 return *(&a+i);
13040 }
13042 This code is nonsensical, but results in addressing
13043 GOT table with pic_offset_table_rtx base. We can't
13044 just refuse it easily, since it gets matched by
13045 "addsi3" pattern, that later gets split to lea in the
13046 case output register differs from input. While this
13047 can be handled by separate addsi pattern for this case
13048 that never results in lea, this seems to be easier and
13049 correct fix for crash to disable this test. */
13050 }
13057 /* Displacement is not constant. */
13061 /* Displacement is out of range. */
13063 /* In x32 mode, constant addresses are sign extended to 64bit, so
13064 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13069 }
13071 /* Everything looks valid. */
13073 }
13075 /* Determine if a given RTX is a valid constant address. */
13077 bool
13079 {
13081 }
13082 \f
13083 /* Return a unique alias set for the GOT. */
13085 static alias_set_type
13087 {
13092 }
13094 /* Return a legitimate reference for ORIG (an address) using the
13095 register REG. If REG is 0, a new pseudo is generated.
13097 There are two types of references that must be handled:
13099 1. Global data references must load the address from the GOT, via
13100 the PIC reg. An insn is emitted to do this load, and the reg is
13101 returned.
13103 2. Static data references, constant pool addresses, and code labels
13104 compute the address as an offset from the GOT, whose base is in
13105 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13106 differentiate them from global data objects. The returned
13107 address is the PIC reg + an unspec constant.
13109 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13110 reg also appears in the address. */
13112 static rtx
13114 {
13118 #if TARGET_MACHO
13120 {
13123 /* Use the generic Mach-O PIC machinery. */
13125 }
13126 #endif
13129 {
13133 }
13139 {
13140 rtx tmpreg;
13141 /* This symbol may be referenced via a displacement from the PIC
13142 base address (@GOTOFF). */
13149 {
13151 UNSPEC_GOTOFF);
13153 }
13154 else
13159 else
13164 {
13168 }
13169 else
13171 }
13173 {
13174 /* This symbol may be referenced via a displacement from the PIC
13175 base address (@GOTOFF). */
13182 {
13184 UNSPEC_GOTOFF);
13186 }
13187 else
13193 {
13196 }
13197 }
13199 /* We can't use @GOTOFF for text labels on VxWorks;
13200 see gotoff_operand. */
13202 {
13207 /* For x64 PE-COFF there is no GOT table. So we use address
13208 directly. */
13210 {
13218 }
13220 {
13228 /* Use directly gen_movsi, otherwise the address is loaded
13229 into register for CSE. We don't want to CSE this addresses,
13230 instead we CSE addresses from the GOT table, so skip this. */
13233 }
13234 else
13235 {
13236 /* This symbol must be referenced via a load from the
13237 Global Offset Table (@GOT). */
13253 }
13254 }
13255 else
13256 {
13259 {
13261 {
13264 }
13265 else
13267 }
13269 {
13272 /* We must match stuff we generate before. Assume the only
13273 unspecs that can get here are ours. Not that we could do
13274 anything with them anyway.... */
13280 }
13282 {
13285 /* Check first to see if this is a constant offset from a @GOTOFF
13286 symbol reference. */
13289 {
13291 {
13295 UNSPEC_GOTOFF);
13301 {
13304 }
13305 }
13306 else
13307 {
13310 {
13314 }
13315 }
13316 }
13317 else
13318 {
13321 new_rtx
13325 {
13328 {
13331 new_rtx
13333 }
13334 else
13336 }
13337 else
13338 {
13341 {
13344 }
13346 }
13347 }
13348 }
13349 }
13351 }
13352 \f
13353 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13355 static rtx
13357 {
13361 {
13366 }
13372 }
13374 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13378 static rtx
13380 {
13382 {
13388 }
13391 {
13393 UNSPEC_PLTOFF);
13396 }
13399 }
13401 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13405 rtx
13407 {
13409 {
13410 ix86_tls_module_base_symbol
13415 }
13418 }
13420 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13421 false if we expect this to be used for a memory address and true if
13422 we expect to load the address into a register. */
13424 static rtx
13426 {
13432 /* Fall back to global dynamic model if tool chain cannot support local
13433 dynamic. */
13440 {
13445 {
13448 else
13449 {
13452 }
13453 }
13456 {
13459 else
13469 }
13470 else
13471 {
13475 {
13477 rtx insns;
13480 emit_call_insn
13490 }
13491 else
13493 }
13500 {
13503 else
13504 {
13507 }
13508 }
13511 {
13516 else
13522 }
13523 else
13524 {
13528 {
13533 emit_call_insn
13538 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13539 share the LD_BASE result with other LD model accesses. */
13541 UNSPEC_TLS_LD_BASE);
13545 }
13546 else
13548 }
13556 {
13563 }
13568 {
13570 {
13571 /* The Sun linker took the AMD64 TLS spec literally
13572 and can only handle %rax as destination of the
13573 initial executable code sequence. */
13578 }
13580 /* Generate DImode references to avoid %fs:(%reg32)
13581 problems and linker IE->LE relaxation bug. */
13585 }
13587 {
13592 }
13594 {
13598 }
13599 else
13600 {
13603 }
13613 {
13618 }
13619 else
13620 {
13624 }
13634 {
13638 }
13639 else
13640 {
13644 }
13649 }
13652 }
13654 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13655 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13656 unique refptr-DECL symbol corresponding to symbol DECL. */
13659 htab_t dllimport_map;
13661 static tree
13663 {
13670 tree to;
13671 rtx rtl;
13698 else
13711 {
13713 #ifdef SUB_TARGET_RECORD_STUB
13715 #endif
13716 }
13725 }
13727 /* Expand SYMBOL into its corresponding far-addresse symbol.
13728 WANT_REG is true if we require the result be a register. */
13730 static rtx
13732 {
13733 tree imp_decl;
13734 rtx x;
13743 }
13745 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13746 true if we require the result be a register. */
13748 static rtx
13750 {
13751 tree imp_decl;
13752 rtx x;
13761 }
13763 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13764 is true if we require the result be a register. */
13766 static rtx
13768 {
13773 {
13780 {
13783 }
13784 }
13800 {
13803 }
13805 }
13807 /* Try machine-dependent ways of modifying an illegitimate address
13808 to be legitimate. If we find one, return the new, valid address.
13809 This macro is used in only one place: `memory_address' in explow.c.
13811 OLDX is the address as it was before break_out_memory_refs was called.
13812 In some cases it is useful to look at this to decide what needs to be done.
13814 It is always safe for this macro to do nothing. It exists to recognize
13815 opportunities to optimize the output.
13817 For the 80386, we handle X+REG by loading X into a register R and
13818 using R+REG. R will go in a general reg and indexing will be used.
13819 However, if REG is a broken-out memory address or multiplication,
13820 nothing needs to be done because REG can certainly go in a general reg.
13822 When -fpic is used, special handling is needed for symbolic references.
13823 See comments by legitimize_pic_address in i386.c for details. */
13825 static rtx
13828 {
13839 {
13843 }
13846 {
13850 }
13855 #if TARGET_MACHO
13858 #endif
13860 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13864 {
13869 }
13872 {
13873 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13878 {
13884 }
13889 {
13895 }
13897 /* Put multiply first if it isn't already. */
13899 {
13904 }
13906 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13907 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13908 created by virtual register instantiation, register elimination, and
13909 similar optimizations. */
13911 {
13917 }
13919 /* Canonicalize
13920 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13921 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13926 {
13927 rtx constant;
13931 {
13934 }
13936 {
13939 }
13940 else
13944 {
13951 }
13952 }
13958 {
13961 }
13964 {
13967 }
13975 {
13978 }
13984 {
13988 {
13991 }
13995 }
13998 {
14002 {
14005 }
14009 }
14010 }
14013 }
14014 \f
14015 /* Print an integer constant expression in assembler syntax. Addition
14016 and subtraction are the only arithmetic that may appear in these
14017 expressions. FILE is the stdio stream to write to, X is the rtx, and
14018 CODE is the operand print code from the output string. */
14020 static void
14022 {
14026 {
14035 else
14036 {
14039 /* Mark the decl as referenced so that cgraph will
14040 output the function. */
14044 #if TARGET_MACHO
14048 #endif
14050 }
14058 /* FALLTHRU */
14069 /* This used to output parentheses around the expression,
14070 but that does not work on the 386 (either ATT or BSD assembler). */
14076 {
14077 /* We can use %d if the number is <32 bits and positive. */
14082 else
14084 }
14085 else
14086 /* We can't handle floating point constants;
14087 TARGET_PRINT_OPERAND must handle them. */
14092 /* Some assemblers need integer constants to appear first. */
14094 {
14098 }
14099 else
14100 {
14105 }
14120 {
14124 }
14129 {
14148 /* FIXME: This might be @TPOFF in Sun ld too. */
14157 else
14167 else
14173 #if TARGET_MACHO
14178 #endif
14182 }
14187 }
14188 }
14190 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14191 We need to emit DTP-relative relocations. */
14193 static void ATTRIBUTE_UNUSED
14195 {
14200 {
14208 }
14209 }
14211 /* Return true if X is a representation of the PIC register. This copes
14212 with calls from ix86_find_base_term, where the register might have
14213 been replaced by a cselib value. */
14215 static bool
14217 {
14221 else
14223 }
14225 /* Helper function for ix86_delegitimize_address.
14226 Attempt to delegitimize TLS local-exec accesses. */
14228 static rtx
14230 {
14255 {
14260 }
14266 }
14268 /* In the name of slightly smaller debug output, and to cater to
14269 general assembler lossage, recognize PIC+GOTOFF and turn it back
14270 into a direct symbol reference.
14272 On Darwin, this is necessary to avoid a crash, because Darwin
14273 has a different PIC label for each routine but the DWARF debugging
14274 information is not associated with any particular routine, so it's
14275 necessary to remove references to the PIC label from RTL stored by
14276 the DWARF output code. */
14278 static rtx
14280 {
14282 /* addend is NULL or some rtx if x is something+GOTOFF where
14283 something doesn't include the PIC register. */
14285 /* reg_addend is NULL or a multiple of some register. */
14287 /* const_addend is NULL or a const_int. */
14289 /* This is the result, or NULL. */
14298 {
14305 {
14311 }
14318 {
14321 {
14326 }
14328 }
14333 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14334 and -mcmodel=medium -fpic. */
14335 }
14342 /* %ebx + GOT/GOTOFF */
14343 ;
14345 {
14346 /* %ebx + %reg * scale + GOT/GOTOFF */
14352 else
14353 {
14356 }
14357 }
14358 else
14364 {
14367 }
14388 {
14389 /* If the rest of original X doesn't involve the PIC register, add
14390 addend and subtract pic_offset_table_rtx. This can happen e.g.
14391 for code like:
14392 leal (%ebx, %ecx, 4), %ecx
14393 ...
14394 movl foo@GOTOFF(%ecx), %edx
14395 in which case we return (%ecx - %ebx) + foo. */
14398 pic_offset_table_rtx),
14399 result);
14400 else
14402 }
14404 {
14408 }
14410 }
14412 /* If X is a machine specific address (i.e. a symbol or label being
14413 referenced as a displacement from the GOT implemented using an
14414 UNSPEC), then return the base term. Otherwise return X. */
14416 rtx
14418 {
14419 rtx term;
14422 {
14436 }
14439 }
14440 \f
14441 static void
14444 {
14448 {
14451 }
14456 {
14459 {
14478 }
14482 {
14501 }
14508 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14509 Those same assemblers have the same but opposite lossage on cmov. */
14512 else
14517 {
14530 }
14537 else
14542 {
14555 }
14562 else
14572 else
14583 }
14585 }
14587 /* Print the name of register X to FILE based on its machine mode and number.
14588 If CODE is 'w', pretend the mode is HImode.
14589 If CODE is 'b', pretend the mode is QImode.
14590 If CODE is 'k', pretend the mode is SImode.
14591 If CODE is 'q', pretend the mode is DImode.
14592 If CODE is 'x', pretend the mode is V4SFmode.
14593 If CODE is 't', pretend the mode is V8SFmode.
14594 If CODE is 'g', pretend the mode is V16SFmode.
14595 If CODE is 'h', pretend the reg is the 'high' byte register.
14596 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14597 If CODE is 'd', duplicate the operand for AVX instruction.
14598 */
14600 void
14602 {
14611 {
14615 }
14642 else
14645 /* Irritatingly, AMD extended registers use different naming convention
14646 from the normal registers: "r%d[bwd]" */
14648 {
14653 {
14667 /* no suffix */
14672 }
14674 }
14678 {
14681 {
14684 }
14685 /* FALLTHRU */
14691 /* FALLTHRU */
14694 normal:
14709 {
14714 }
14717 {
14722 }
14726 }
14730 {
14733 else
14735 }
14736 }
14738 /* Locate some local-dynamic symbol still in use by this function
14739 so that we can print its name in some tls_local_dynamic_base
14740 pattern. */
14742 static int
14744 {
14749 {
14752 }
14755 }
14759 {
14760 rtx insn;
14771 }
14773 /* Meaning of CODE:
14774 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14775 C -- print opcode suffix for set/cmov insn.
14776 c -- like C, but print reversed condition
14777 F,f -- likewise, but for floating-point.
14778 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14779 otherwise nothing
14780 R -- print embeded rounding and sae.
14781 r -- print only sae.
14782 z -- print the opcode suffix for the size of the current operand.
14783 Z -- likewise, with special suffixes for x87 instructions.
14784 * -- print a star (in certain assembler syntax)
14785 A -- print an absolute memory reference.
14786 E -- print address with DImode register names if TARGET_64BIT.
14787 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14788 s -- print a shift double count, followed by the assemblers argument
14789 delimiter.
14790 b -- print the QImode name of the register for the indicated operand.
14791 %b0 would print %al if operands[0] is reg 0.
14792 w -- likewise, print the HImode name of the register.
14793 k -- likewise, print the SImode name of the register.
14794 q -- likewise, print the DImode name of the register.
14795 x -- likewise, print the V4SFmode name of the register.
14796 t -- likewise, print the V8SFmode name of the register.
14797 g -- likewise, print the V16SFmode name of the register.
14798 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14799 y -- print "st(0)" instead of "st" as a register.
14800 d -- print duplicated register operand for AVX instruction.
14801 D -- print condition for SSE cmp instruction.
14802 P -- if PIC, print an @PLT suffix.
14803 p -- print raw symbol name.
14804 X -- don't print any sort of PIC '@' suffix for a symbol.
14805 & -- print some in-use local-dynamic symbol name.
14806 H -- print a memory address offset by 8; used for sse high-parts
14807 Y -- print condition for XOP pcom* instruction.
14808 + -- print a branch hint as 'cs' or 'ds' prefix
14809 ; -- print a semicolon (after prefixes due to bug in older gas).
14810 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14811 @ -- print a segment register of thread base pointer load
14812 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14813 */
14815 void
14817 {
14819 {
14821 {
14824 {
14830 /* Intel syntax. For absolute addresses, registers should not
14831 be surrounded by braces. */
14833 {
14838 }
14843 }
14849 /* Wrap address in an UNSPEC to declare special handling. */
14887 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14892 {
14906 output_operand_lossage
14909 }
14912 #endif
14917 {
14918 /* Opcodes don't get size suffixes if using Intel opcodes. */
14923 {
14941 output_operand_lossage
14944 }
14945 }
14948 warning
14950 /* FALLTHRU */
14953 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14958 {
14960 {
14962 #ifdef HAVE_AS_IX86_FILDS
14964 #endif
14972 #ifdef HAVE_AS_IX86_FILDQ
14974 #else
14976 #endif
14981 }
14982 }
14984 {
14985 /* 387 opcodes don't get size suffixes
14986 if the operands are registers. */
14991 {
15007 }
15008 }
15009 else
15010 {
15011 output_operand_lossage
15014 }
15016 output_operand_lossage
15037 {
15040 }
15045 {
15096 }
15100 /* Little bit of braindamage here. The SSE compare instructions
15101 does use completely different names for the comparisons that the
15102 fp conditional moves. */
15104 {
15107 {
15110 }
15116 {
15119 }
15125 {
15128 }
15137 {
15140 }
15146 {
15149 }
15155 {
15158 }
15169 }
15174 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15177 #endif
15182 {
15186 }
15190 file);
15195 {
15199 }
15200 /* It doesn't actually matter what mode we use here, as we're
15201 only going to use this for printing. */
15203 /* Output 'qword ptr' for intel assembler dialect. */
15212 #ifdef HAVE_AS_IX86_HLE
15214 #else
15216 #endif
15218 #ifdef HAVE_AS_IX86_HLE
15220 #else
15222 #endif
15223 /* We do not want to print value of the operand. */
15252 {
15267 }
15280 {
15285 else
15288 }
15291 {
15292 rtx x;
15301 {
15306 {
15308 bool cputaken
15311 /* Emit hints only in the case default branch prediction
15312 heuristics would fail. */
15314 {
15315 /* We use 3e (DS) prefix for taken branches and
15316 2e (CS) prefix for not taken branches. */
15319 else
15321 }
15322 }
15323 }
15325 }
15328 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15330 #endif
15337 /* The kernel uses a different segment register for performance
15338 reasons; a system call would not have to trash the userspace
15339 segment register, which would be expensive. */
15342 else
15357 }
15358 }
15364 {
15365 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15368 {
15371 {
15380 else
15387 }
15389 /* Check for explicit size override (codes 'b', 'w', 'k',
15390 'q' and 'x') */
15404 }
15407 /* Avoid (%rip) for call operands. */
15413 else
15415 }
15418 {
15419 REAL_VALUE_TYPE r;
15427 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15431 else
15433 }
15436 {
15437 REAL_VALUE_TYPE r;
15446 }
15448 /* These float cases don't actually occur as immediate operands. */
15450 {
15455 }
15457 else
15458 {
15459 /* We have patterns that allow zero sets of memory, for instance.
15460 In 64-bit mode, we should probably support all 8-byte vectors,
15461 since we can in fact encode that into an immediate. */
15463 {
15466 }
15469 {
15471 {
15474 }
15477 {
15480 else
15482 }
15483 }
15488 else
15490 }
15491 }
15493 static bool
15495 {
15498 }
15499 \f
15500 /* Print a memory operand whose address is ADDR. */
15502 static void
15504 {
15513 {
15520 }
15522 {
15526 }
15527 else
15538 {
15549 }
15551 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15553 {
15565 }
15567 {
15568 /* Displacement only requires special attention. */
15571 {
15575 }
15578 else
15580 }
15581 else
15582 {
15583 /* Print SImode register names to force addr32 prefix. */
15585 {
15586 #ifdef ENABLE_CHECKING
15589 {
15600 }
15601 #endif
15604 }
15606 && TARGET_X32
15607 && disp
15610 {
15611 /* X32 runs in 64-bit mode, where displacement, DISP, in
15612 address DISP(%r64), is encoded as 32-bit immediate sign-
15613 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15614 address is %r64 + 0xffffffffbffffd00. When %r64 <
15615 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15616 which is invalid for x32. The correct address is %r64
15617 - 0x40000300 == 0xf7ffdd64. To properly encode
15618 -0x40000300(%r64) for x32, we zero-extend negative
15619 displacement by forcing addr32 prefix which truncates
15620 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15621 zero-extend all negative displacements, including -1(%rsp).
15622 However, for small negative displacements, sign-extension
15623 won't cause overflow. We only zero-extend negative
15624 displacements if they < -16*1024*1024, which is also used
15625 to check legitimate address displacements for PIC. */
15627 }
15630 {
15632 {
15637 else
15639 }
15645 {
15650 }
15652 }
15653 else
15654 {
15658 {
15659 /* Pull out the offset of a symbol; print any symbol itself. */
15663 {
15667 }
15675 else
15677 }
15681 {
15684 {
15688 }
15689 }
15692 else
15696 {
15701 }
15703 }
15704 }
15705 }
15707 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15709 static bool
15711 {
15712 rtx op;
15719 {
15722 /* FIXME: This might be @TPOFF in Sun ld. */
15733 else
15745 else
15752 #if TARGET_MACHO
15758 #endif
15761 {
15766 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15768 #else
15770 #endif
15773 }
15778 }
15781 }
15782 \f
15783 /* Split one or more double-mode RTL references into pairs of half-mode
15784 references. The RTL can be REG, offsettable MEM, integer constant, or
15785 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15786 split and "num" is its length. lo_half and hi_half are output arrays
15787 that parallel "operands". */
15789 void
15792 {
15797 {
15806 }
15811 {
15814 /* simplify_subreg refuse to split volatile memory addresses,
15815 but we still have to handle it. */
15817 {
15820 }
15821 else
15822 {
15829 }
15830 }
15831 }
15832 \f
15833 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15834 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15835 is the expression of the binary operation. The output may either be
15836 emitted here, or returned to the caller, like all output_* functions.
15838 There is no guarantee that the operands are the same mode, as they
15839 might be within FLOAT or FLOAT_EXTEND expressions. */
15841 #ifndef SYSV386_COMPAT
15842 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15843 wants to fix the assemblers because that causes incompatibility
15844 with gcc. No-one wants to fix gcc because that causes
15845 incompatibility with assemblers... You can use the option of
15846 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15847 #define SYSV386_COMPAT 1
15848 #endif
15852 {
15858 #ifdef ENABLE_CHECKING
15859 /* Even if we do not want to check the inputs, this documents input
15860 constraints. Which helps in understanding the following code. */
15870 else
15872 #endif
15875 {
15880 else
15889 else
15898 else
15907 else
15914 }
15917 {
15919 {
15923 else
15925 }
15926 else
15927 {
15931 else
15933 }
15935 }
15939 {
15943 {
15947 }
15949 /* know operands[0] == operands[1]. */
15952 {
15955 }
15958 {
15960 /* How is it that we are storing to a dead operand[2]?
15961 Well, presumably operands[1] is dead too. We can't
15962 store the result to st(0) as st(0) gets popped on this
15963 instruction. Instead store to operands[2] (which I
15964 think has to be st(1)). st(1) will be popped later.
15965 gcc <= 2.8.1 didn't have this check and generated
15966 assembly code that the Unixware assembler rejected. */
15968 else
15971 }
15975 else
15982 {
15985 }
15988 {
15991 }
15994 {
15995 #if SYSV386_COMPAT
15996 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15997 derived assemblers, confusingly reverse the direction of
15998 the operation for fsub{r} and fdiv{r} when the
15999 destination register is not st(0). The Intel assembler
16000 doesn't have this brain damage. Read !SYSV386_COMPAT to
16001 figure out what the hardware really does. */
16004 else
16006 #else
16008 /* As above for fmul/fadd, we can't store to st(0). */
16010 else
16012 #endif
16014 }
16017 {
16018 #if SYSV386_COMPAT
16021 else
16023 #else
16026 else
16028 #endif
16030 }
16033 {
16036 else
16039 }
16041 {
16042 #if SYSV386_COMPAT
16044 #else
16046 #endif
16047 }
16048 else
16049 {
16050 #if SYSV386_COMPAT
16052 #else
16054 #endif
16055 }
16060 }
16064 }
16066 /* Check if a 256bit AVX register is referenced inside of EXP. */
16068 static int
16070 {
16081 }
16083 /* Return needed mode for entity in optimize_mode_switching pass. */
16085 static int
16087 {
16089 {
16090 rtx link;
16092 /* Needed mode is set to AVX_U128_CLEAN if there are
16093 no 256bit modes used in function arguments. */
16095 link;
16097 {
16099 {
16104 }
16105 }
16108 }
16110 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16111 changes state only when a 256bit register is written to, but we need
16112 to prevent the compiler from moving optimal insertion point above
16113 eventual read from 256bit register. */
16118 }
16120 /* Return mode that i387 must be switched into
16121 prior to the execution of insn. */
16123 static int
16125 {
16128 /* The mode UNINITIALIZED is used to store control word after a
16129 function call or ASM pattern. The mode ANY specify that function
16130 has no requirements on the control word and make no changes in the
16131 bits we are interested in. */
16145 {
16168 }
16171 }
16173 /* Return mode that entity must be switched into
16174 prior to the execution of insn. */
16176 static int
16178 {
16180 {
16190 }
16192 }
16194 /* Check if a 256bit AVX register is referenced in stores. */
16196 static void
16198 {
16200 {
16203 }
16204 }
16206 /* Calculate mode of upper 128bit AVX registers after the insn. */
16208 static int
16210 {
16217 /* We know that state is clean after CALL insn if there are no
16218 256bit registers used in the function return register. */
16220 {
16225 }
16227 /* Otherwise, return current mode. Remember that if insn
16228 references AVX 256bit registers, the mode was already changed
16229 to DIRTY from MODE_NEEDED. */
16231 }
16233 /* Return the mode that an insn results in. */
16235 int
16237 {
16239 {
16249 }
16250 }
16252 static int
16254 {
16255 tree arg;
16257 /* Entry mode is set to AVX_U128_DIRTY if there are
16258 256bit modes used in function arguments. */
16261 {
16266 }
16269 }
16271 /* Return a mode that ENTITY is assumed to be
16272 switched to at function entry. */
16274 static int
16276 {
16278 {
16288 }
16289 }
16291 static int
16293 {
16296 /* Exit mode is set to AVX_U128_DIRTY if there are
16297 256bit modes used in the function return register. */
16302 }
16304 /* Return a mode that ENTITY is assumed to be
16305 switched to at function exit. */
16307 static int
16309 {
16311 {
16321 }
16322 }
16324 static int
16326 {
16328 }
16330 /* Output code to initialize control word copies used by trunc?f?i and
16331 rounding patterns. CURRENT_MODE is set to current control word,
16332 while NEW_MODE is set to new control word. */
16334 static void
16336 {
16338 rtx new_mode;
16349 {
16351 {
16353 /* round toward zero (truncate) */
16359 /* round down toward -oo */
16366 /* round up toward +oo */
16373 /* mask precision exception for nearbyint() */
16380 }
16381 }
16382 else
16383 {
16385 {
16387 /* round toward zero (truncate) */
16393 /* round down toward -oo */
16399 /* round up toward +oo */
16405 /* mask precision exception for nearbyint() */
16412 }
16413 }
16419 }
16421 /* Emit vzeroupper. */
16423 void
16425 {
16428 /* Cancel automatic vzeroupper insertion if there are
16429 live call-saved SSE registers at the insertion point. */
16441 }
16443 /* Generate one or more insns to set ENTITY to MODE. */
16445 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16446 is the set of hard registers live at the point where the insn(s)
16447 are to be inserted. */
16449 static void
16451 {
16453 {
16468 }
16469 }
16471 /* Output code for INSN to convert a float to a signed int. OPERANDS
16472 are the insn operands. The output may be [HSD]Imode and the input
16473 operand may be [SDX]Fmode. */
16477 {
16482 /* Jump through a hoop or two for DImode, since the hardware has no
16483 non-popping instruction. We used to do this a different way, but
16484 that was somewhat fragile and broke with post-reload splitters. */
16494 else
16495 {
16500 else
16504 }
16507 }
16509 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16510 have the values zero or one, indicates the ffreep insn's operand
16511 from the OPERANDS array. */
16515 {
16517 #ifdef HAVE_AS_IX86_FFREEP
16519 #else
16520 {
16530 }
16531 #endif
16534 }
16537 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16538 should be used. UNORDERED_P is true when fucom should be used. */
16542 {
16548 {
16551 }
16552 else
16553 {
16556 }
16559 {
16563 else
16565 else
16568 else
16570 }
16577 {
16579 {
16582 }
16583 else
16585 }
16588 && stack_top_dies
16591 {
16592 /* If both the top of the 387 stack dies, and the other operand
16593 is also a stack register that dies, then this must be a
16594 `fcompp' float compare */
16597 {
16598 /* There is no double popping fcomi variant. Fortunately,
16599 eflags is immune from the fstp's cc clobbering. */
16602 else
16605 }
16606 else
16607 {
16610 else
16612 }
16613 }
16614 else
16615 {
16616 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16619 {
16627 NULL,
16628 NULL,
16635 NULL,
16636 NULL,
16637 NULL,
16638 NULL
16639 };
16654 }
16655 }
16657 void
16659 {
16662 #ifdef ASM_QUAD
16665 #else
16667 #endif
16670 }
16672 void
16674 {
16677 #ifdef ASM_QUAD
16680 #else
16682 #endif
16683 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16689 #if TARGET_MACHO
16691 {
16695 }
16696 #endif
16697 else
16700 }
16701 \f
16702 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16703 for the target. */
16705 void
16707 {
16708 rtx tmp;
16710 /* We play register width games, which are only valid after reload. */
16713 /* Avoid HImode and its attendant prefix byte. */
16719 {
16722 }
16725 }
16727 /* X is an unchanging MEM. If it is a constant pool reference, return
16728 the constant pool rtx, else NULL. */
16730 rtx
16732 {
16739 }
16741 void
16743 {
16751 {
16752 rtx tmp;
16756 {
16762 }
16765 }
16769 {
16772 rtx tmp;
16777 else
16781 {
16788 }
16789 }
16793 {
16795 {
16796 #if TARGET_MACHO
16797 /* dynamic-no-pic */
16799 {
16800 rtx temp = ((reload_in_progress
16808 }
16810 {
16814 }
16817 else
16818 {
16826 }
16827 /* dynamic-no-pic */
16828 #endif
16829 }
16830 else
16831 {
16835 {
16841 }
16842 }
16843 }
16844 else
16845 {
16856 /* Force large constants in 64bit compilation into register
16857 to get them CSEed. */
16869 {
16870 /* If we are loading a floating point constant to a register,
16871 force the value to memory now, since we'll get better code
16872 out the back end. */
16876 {
16881 }
16882 }
16883 }
16886 }
16888 void
16890 {
16897 /* Force constants other than zero into memory. We do not know how
16898 the instructions used to build constants modify the upper 64 bits
16899 of the register, once we have that information we may be able
16900 to handle some of them more efficiently. */
16909 /* We need to check memory alignment for SSE mode since attribute
16910 can make operands unaligned. */
16915 {
16918 /* ix86_expand_vector_move_misalign() does not like constants ... */
16924 /* ... nor both arguments in memory. */
16932 }
16934 /* Make operand1 a register if it isn't already. */
16938 {
16941 }
16944 }
16946 /* Split 32-byte AVX unaligned load and store if needed. */
16948 static void
16950 {
16951 rtx m;
16958 {
16979 }
16982 {
16984 {
16991 }
16992 /* Normal *mov<mode>_internal pattern will handle
16993 unaligned loads just fine if misaligned_operand
16994 is true, and without the UNSPEC it can be combined
16995 with arithmetic instructions. */
16998 else
17000 }
17002 {
17004 {
17009 }
17010 else
17012 }
17013 else
17015 }
17017 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17018 straight to ix86_expand_vector_move. */
17019 /* Code generation for scalar reg-reg moves of single and double precision data:
17020 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17021 movaps reg, reg
17022 else
17023 movss reg, reg
17024 if (x86_sse_partial_reg_dependency == true)
17025 movapd reg, reg
17026 else
17027 movsd reg, reg
17029 Code generation for scalar loads of double precision data:
17030 if (x86_sse_split_regs == true)
17031 movlpd mem, reg (gas syntax)
17032 else
17033 movsd mem, reg
17035 Code generation for unaligned packed loads of single precision data
17036 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17037 if (x86_sse_unaligned_move_optimal)
17038 movups mem, reg
17040 if (x86_sse_partial_reg_dependency == true)
17041 {
17042 xorps reg, reg
17043 movlps mem, reg
17044 movhps mem+8, reg
17045 }
17046 else
17047 {
17048 movlps mem, reg
17049 movhps mem+8, reg
17050 }
17052 Code generation for unaligned packed loads of double precision data
17053 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17054 if (x86_sse_unaligned_move_optimal)
17055 movupd mem, reg
17057 if (x86_sse_split_regs == true)
17058 {
17059 movlpd mem, reg
17060 movhpd mem+8, reg
17061 }
17062 else
17063 {
17064 movsd mem, reg
17065 movhpd mem+8, reg
17066 }
17067 */
17069 void
17071 {
17080 {
17082 {
17086 {
17088 {
17091 }
17092 else
17094 }
17096 /* FALLTHRU */
17100 {
17115 }
17121 else
17129 }
17132 }
17136 {
17138 {
17142 {
17144 {
17147 }
17148 else
17150 }
17152 /* FALLTHRU */
17162 }
17165 }
17168 {
17169 /* Normal *mov<mode>_internal pattern will handle
17170 unaligned loads just fine if misaligned_operand
17171 is true, and without the UNSPEC it can be combined
17172 with arithmetic instructions. */
17178 /* ??? If we have typed data, then it would appear that using
17179 movdqu is the only way to get unaligned data loaded with
17180 integer type. */
17182 {
17184 {
17187 }
17189 /* We will eventually emit movups based on insn attributes. */
17193 }
17195 {
17196 rtx zero;
17199 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17200 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17202 {
17203 /* We will eventually emit movups based on insn attributes. */
17206 }
17208 /* When SSE registers are split into halves, we can avoid
17209 writing to the top half twice. */
17211 {
17214 }
17215 else
17216 {
17217 /* ??? Not sure about the best option for the Intel chips.
17218 The following would seem to satisfy; the register is
17219 entirely cleared, breaking the dependency chain. We
17220 then store to the upper half, with a dependency depth
17221 of one. A rumor has it that Intel recommends two movsd
17222 followed by an unpacklpd, but this is unconfirmed. And
17223 given that the dependency depth of the unpacklpd would
17224 still be one, I'm not sure why this would be better. */
17226 }
17232 }
17233 else
17234 {
17235 rtx t;
17238 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17239 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17241 {
17243 {
17246 }
17253 }
17257 else
17262 else
17271 }
17272 }
17274 {
17276 {
17279 /* We will eventually emit movups based on insn attributes. */
17281 }
17283 {
17285 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17286 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17288 /* We will eventually emit movups based on insn attributes. */
17290 else
17291 {
17296 }
17297 }
17298 else
17299 {
17304 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17305 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17307 {
17310 }
17311 else
17312 {
17317 }
17318 }
17319 }
17320 else
17322 }
17324 /* Helper function of ix86_fixup_binary_operands to canonicalize
17325 operand order. Returns true if the operands should be swapped. */
17327 static bool
17329 rtx operands[])
17330 {
17335 /* If the operation is not commutative, we can't do anything. */
17339 /* Highest priority is that src1 should match dst. */
17345 /* Next highest priority is that immediate constants come second. */
17351 /* Lowest priority is that memory references should come second. */
17358 }
17361 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17362 destination to use for the operation. If different from the true
17363 destination in operands[0], a copy operation will be required. */
17365 rtx
17367 rtx operands[])
17368 {
17373 /* Canonicalize operand order. */
17375 {
17376 rtx temp;
17378 /* It is invalid to swap operands of different modes. */
17384 }
17386 /* Both source operands cannot be in memory. */
17388 {
17389 /* Optimization: Only read from memory once. */
17391 {
17394 }
17397 else
17399 }
17401 /* If the destination is memory, and we do not have matching source
17402 operands, do things in registers. */
17406 /* Source 1 cannot be a constant. */
17410 /* Source 1 cannot be a non-matching memory. */
17414 /* Improve address combine. */
17423 }
17425 /* Similarly, but assume that the destination has already been
17426 set up properly. */
17428 void
17431 {
17434 }
17436 /* Attempt to expand a binary operator. Make the expansion closer to the
17437 actual machine, then just general_operand, which will allow 3 separate
17438 memory references (one output, two input) in a single insn. */
17440 void
17442 rtx operands[])
17443 {
17450 /* Emit the instruction. */
17454 {
17455 /* Reload doesn't know about the flags register, and doesn't know that
17456 it doesn't want to clobber it. We can only do this with PLUS. */
17459 }
17463 {
17464 /* This is going to be an LEA; avoid splitting it later. */
17466 }
17467 else
17468 {
17471 }
17473 /* Fix up the destination if needed. */
17476 }
17478 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17479 the given OPERANDS. */
17481 void
17483 rtx operands[])
17484 {
17487 {
17490 }
17492 {
17495 }
17496 /* Optimize (__m128i) d | (__m128i) e and similar code
17497 when d and e are float vectors into float vector logical
17498 insn. In C/C++ without using intrinsics there is no other way
17499 to express vector logical operation on float vectors than
17500 to cast them temporarily to integer vectors. */
17502 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17511 {
17512 rtx dst;
17514 {
17521 {
17524 }
17525 else
17526 {
17531 }
17542 }
17543 }
17552 }
17554 /* Return TRUE or FALSE depending on whether the binary operator meets the
17555 appropriate constraints. */
17557 bool
17560 {
17565 /* Both source operands cannot be in memory. */
17569 /* Canonicalize operand order for commutative operators. */
17571 {
17575 }
17577 /* If the destination is memory, we must have a matching source operand. */
17581 /* Source 1 cannot be a constant. */
17585 /* Source 1 cannot be a non-matching memory. */
17587 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17595 }
17597 /* Attempt to expand a unary operator. Make the expansion closer to the
17598 actual machine, then just general_operand, which will allow 2 separate
17599 memory references (one output, one input) in a single insn. */
17601 void
17603 rtx operands[])
17604 {
17611 /* If the destination is memory, and we do not have matching source
17612 operands, do things in registers. */
17615 {
17618 else
17620 }
17622 /* When source operand is memory, destination must match. */
17626 /* Emit the instruction. */
17630 {
17631 /* Reload doesn't know about the flags register, and doesn't know that
17632 it doesn't want to clobber it. */
17635 }
17636 else
17637 {
17640 }
17642 /* Fix up the destination if needed. */
17645 }
17647 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17648 divisor are within the range [0-255]. */
17650 void
17653 {
17662 {
17675 }
17682 /* Use 8bit unsigned divimod if dividend and divisor are within
17683 the range [0-255]. */
17692 pc_rtx);
17697 /* Generate original signed/unsigned divimod. */
17702 /* Branch to the end. */
17706 /* Generate 8bit unsigned divide. */
17708 /* Don't use operands[0] for result of 8bit divide since not all
17709 registers support QImode ZERO_EXTRACT. */
17716 {
17719 }
17720 else
17721 {
17724 }
17726 /* Extract remainder from AH. */
17730 else
17731 {
17732 /* Need a new scratch register since the old one has result
17733 of 8bit divide. */
17737 }
17740 /* Zero extend quotient from AL. */
17746 }
17748 /* Whether it is OK to emit CFI directives when emitting asm code. */
17750 bool
17752 {
17754 }
17756 #define LEA_MAX_STALL (3)
17757 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17759 /* Increase given DISTANCE in half-cycles according to
17760 dependencies between PREV and NEXT instructions.
17761 Add 1 half-cycle if there is no dependency and
17762 go to next cycle if there is some dependecy. */
17764 static unsigned int
17766 {
17782 }
17784 /* Function checks if instruction INSN defines register number
17785 REGNO1 or REGNO2. */
17787 static bool
17789 rtx insn)
17790 {
17791 df_ref def;
17801 }
17803 /* Function checks if instruction INSN uses register number
17804 REGNO as a part of address expression. */
17806 static bool
17808 {
17809 df_ref use;
17816 }
17818 /* Search backward for non-agu definition of register number REGNO1
17819 or register number REGNO2 in basic block starting from instruction
17820 START up to head of basic block or instruction INSN.
17822 Function puts true value into *FOUND var if definition was found
17823 and false otherwise.
17825 Distance in half-cycles between START and found instruction or head
17826 of BB is added to DISTANCE and returned. */
17828 static int
17832 {
17842 {
17844 {
17847 {
17850 {
17853 }
17854 }
17857 }
17862 }
17865 }
17867 /* Search backward for non-agu definition of register number REGNO1
17868 or register number REGNO2 in INSN's basic block until
17869 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17870 2. Reach neighbour BBs boundary, or
17871 3. Reach agu definition.
17872 Returns the distance between the non-agu definition point and INSN.
17873 If no definition point, returns -1. */
17875 static int
17877 rtx insn)
17878 {
17889 {
17890 edge e;
17891 edge_iterator ei;
17896 {
17899 }
17905 else
17906 {
17911 {
17912 int bb_dist
17918 {
17925 }
17926 }
17929 }
17930 }
17932 /* get_attr_type may modify recog data. We want to make sure
17933 that recog data is valid for instruction INSN, on which
17934 distance_non_agu_define is called. INSN is unchanged here. */
17941 }
17943 /* Return the distance in half-cycles between INSN and the next
17944 insn that uses register number REGNO in memory address added
17945 to DISTANCE. Return -1 if REGNO0 is set.
17947 Put true value into *FOUND if register usage was found and
17948 false otherwise.
17949 Put true value into *REDEFINED if register redefinition was
17950 found and false otherwise. */
17952 static int
17956 {
17965 {
17968 /* If insn and start belong to the same bb, set prev to insn,
17969 so the call to increase_distance will increase the distance
17970 between insns by 1. */
17972 }
17977 {
17979 {
17982 {
17983 /* Return DISTANCE if OP0 is used in memory
17984 address in NEXT. */
17987 }
17990 {
17991 /* Return -1 if OP0 is set in NEXT. */
17994 }
17997 }
18003 }
18006 }
18008 /* Return the distance between INSN and the next insn that uses
18009 register number REGNO0 in memory address. Return -1 if no such
18010 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18012 static int
18014 {
18026 {
18027 edge e;
18028 edge_iterator ei;
18033 {
18036 }
18042 else
18043 {
18049 {
18050 int bb_dist
18055 {
18062 }
18063 }
18066 }
18067 }
18073 }
18075 /* Define this macro to tune LEA priority vs ADD, it take effect when
18076 there is a dilemma of choicing LEA or ADD
18077 Negative value: ADD is more preferred than LEA
18078 Zero: Netrual
18079 Positive value: LEA is more preferred than ADD*/
18080 #define IX86_LEA_PRIORITY 0
18082 /* Return true if usage of lea INSN has performance advantage
18083 over a sequence of instructions. Instructions sequence has
18084 SPLIT_COST cycles higher latency than lea latency. */
18086 static bool
18089 {
18092 /* For Silvermont if using a 2-source or 3-source LEA for
18093 non-destructive destination purposes, or due to wanting
18094 ability to use SCALE, the use of LEA is justified. */
18096 {
18104 }
18110 {
18111 /* If there is no non AGU operand definition, no AGU
18112 operand usage and split cost is 0 then both lea
18113 and non lea variants have same priority. Currently
18114 we prefer lea for 64 bit code and non lea on 32 bit
18115 code. */
18118 else
18120 }
18122 /* With longer definitions distance lea is more preferable.
18123 Here we change it to take into account splitting cost and
18124 lea priority. */
18127 /* If there is no use in memory addess then we just check
18128 that split cost exceeds AGU stall. */
18132 /* If this insn has both backward non-agu dependence and forward
18133 agu dependence, the one with short distance takes effect. */
18135 }
18137 /* Return true if it is legal to clobber flags by INSN and
18138 false otherwise. */
18140 static bool
18142 {
18144 df_ref use;
18145 bitmap live;
18148 {
18150 {
18157 }
18163 }
18167 }
18169 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18170 move and add to avoid AGU stalls. */
18172 bool
18174 {
18177 /* Check if we need to optimize. */
18181 /* Check it is correct to split here. */
18189 /* We need to split only adds with non destructive
18190 destination operand. */
18193 else
18195 }
18197 /* Return true if we should emit lea instruction instead of mov
18198 instruction. */
18200 bool
18202 {
18205 /* Check if we need to optimize. */
18209 /* Use lea for reg to reg moves only. */
18217 }
18219 /* Return true if we need to split lea into a sequence of
18220 instructions to avoid AGU stalls. */
18222 bool
18224 {
18230 /* Check we need to optimize. */
18234 /* The "at least two components" test below might not catch simple
18235 move or zero extension insns if parts.base is non-NULL and parts.disp
18236 is const0_rtx as the only components in the address, e.g. if the
18237 register is %rbp or %r13. As this test is much cheaper and moves or
18238 zero extensions are the common case, do this check first. */
18244 /* Check if it is OK to split here. */
18251 /* There should be at least two components in the address. */
18256 /* We should not split into add if non legitimate pic
18257 operand is used as displacement. */
18272 /* Compute how many cycles we will add to execution time
18273 if split lea into a sequence of instructions. */
18275 {
18276 /* Have to use mov instruction if non desctructive
18277 destination form is used. */
18281 /* Have to add index to base if both exist. */
18285 /* Have to use shift and adds if scale is 2 or greater. */
18287 {
18292 else
18294 }
18296 /* Have to use add instruction with immediate if
18297 disp is non zero. */
18301 /* Subtract the price of lea. */
18303 }
18307 }
18309 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18310 matches destination. RTX includes clobber of FLAGS_REG. */
18312 static void
18315 {
18322 }
18324 /* Return true if regno1 def is nearest to the insn. */
18326 static bool
18328 {
18335 {
18337 {
18340 }
18346 }
18348 /* None of the regs is defined in the bb. */
18350 }
18352 /* Split lea instructions into a sequence of instructions
18353 which are executed on ALU to avoid AGU stalls.
18354 It is assumed that it is allowed to clobber flags register
18355 at lea position. */
18357 void
18359 {
18375 {
18378 }
18381 {
18384 }
18390 {
18391 /* Case r1 = r1 + ... */
18393 {
18394 /* If we have a case r1 = r1 + C * r2 then we
18395 should use multiplication which is very
18396 expensive. Assume cost model is wrong if we
18397 have such case here. */
18402 }
18403 else
18404 {
18405 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18409 /* Use shift for scaling. */
18418 }
18419 }
18421 {
18424 }
18425 else
18426 {
18428 {
18431 }
18433 {
18436 }
18437 else
18438 {
18443 else
18444 {
18445 rtx tmp1;
18447 /* Find better operand for SET instruction, depending
18448 on which definition is farther from the insn. */
18451 else
18461 }
18464 }
18468 }
18469 }
18471 /* Return true if it is ok to optimize an ADD operation to LEA
18472 operation to avoid flag register consumation. For most processors,
18473 ADD is faster than LEA. For the processors like BONNELL, if the
18474 destination register of LEA holds an actual address which will be
18475 used soon, LEA is better and otherwise ADD is better. */
18477 bool
18479 {
18484 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18492 }
18494 /* Return true if destination reg of SET_BODY is shift count of
18495 USE_BODY. */
18497 static bool
18499 {
18500 rtx set_dest;
18501 rtx shift_rtx;
18504 /* Retrieve destination of SET_BODY. */
18506 {
18515 use_body))
18520 }
18522 /* Retrieve shift count of USE_BODY. */
18524 {
18536 }
18544 {
18547 /* Return true if shift count is dest of SET_BODY. */
18549 {
18550 /* Add check since it can be invoked before register
18551 allocation in pre-reload schedule. */
18557 }
18558 }
18561 }
18563 /* Return true if destination reg of SET_INSN is shift count of
18564 USE_INSN. */
18566 bool
18568 {
18571 }
18573 /* Return TRUE or FALSE depending on whether the unary operator meets the
18574 appropriate constraints. */
18576 bool
18580 {
18581 /* If one of operands is memory, source and destination must match. */
18587 }
18589 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18590 are ok, keeping in mind the possible movddup alternative. */
18592 bool
18594 {
18600 }
18602 /* Post-reload splitter for converting an SF or DFmode value in an
18603 SSE register into an unsigned SImode. */
18605 void
18607 {
18618 /* Load up the value into the low element. We must ensure that the other
18619 elements are valid floats -- zero is the easiest such value. */
18621 {
18624 else
18626 }
18627 else
18628 {
18633 else
18635 }
18655 else
18660 }
18662 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18663 Expects the 64-bit DImode to be supplied in a pair of integral
18664 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18665 -mfpmath=sse, !optimize_size only. */
18667 void
18669 {
18673 rtx x;
18679 {
18682 }
18683 else
18684 {
18688 }
18696 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18699 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18700 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18701 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18702 (0x1.0p84 + double(fp_value_hi_xmm)).
18703 Note these exponents differ by 32. */
18707 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18708 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18717 /* Add the upper and lower DFmode values together. */
18720 else
18721 {
18725 }
18728 }
18730 /* Not used, but eases macroization of patterns. */
18731 void
18733 rtx input ATTRIBUTE_UNUSED)
18734 {
18736 }
18738 /* Convert an unsigned SImode value into a DFmode. Only currently used
18739 for SSE, but applicable anywhere. */
18741 void
18743 {
18744 REAL_VALUE_TYPE TWO31r;
18759 }
18761 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18762 32-bit mode; otherwise we have a direct convert instruction. */
18764 void
18766 {
18767 REAL_VALUE_TYPE TWO32r;
18785 }
18787 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18788 For x86_32, -mfpmath=sse, !optimize_size only. */
18789 void
18791 {
18792 REAL_VALUE_TYPE ONE16r;
18811 }
18813 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18814 a vector of unsigned ints VAL to vector of floats TARGET. */
18816 void
18818 {
18820 REAL_VALUE_TYPE TWO16r;
18827 else
18832 OPTAB_DIRECT);
18843 OPTAB_DIRECT);
18845 OPTAB_DIRECT);
18848 }
18850 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18851 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18852 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18853 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18855 rtx
18857 {
18858 REAL_VALUE_TYPE TWO31r;
18873 {
18879 }
18888 OPTAB_DIRECT);
18889 else
18890 {
18896 OPTAB_DIRECT);
18897 }
18900 }
18902 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18903 then replicate the value for all elements of the vector
18904 register. */
18906 rtx
18908 {
18910 rtvec v;
18914 {
18947 }
18948 }
18950 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18951 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18952 for an SSE register. If VECT is true, then replicate the mask for
18953 all elements of the vector register. If INVERT is true, then create
18954 a mask excluding the sign bit. */
18956 rtx
18958 {
18962 rtx v;
18963 rtx mask;
18965 /* Find the sign bit, sign extended to 2*HWI. */
18967 {
18991 else
18999 {
19002 }
19003 else
19004 {
19005 rtvec vec;
19011 {
19014 }
19015 else
19025 }
19030 }
19035 /* Force this value into the low part of a fp vector constant. */
19044 }
19046 /* Generate code for floating point ABS or NEG. */
19048 void
19050 rtx operands[])
19051 {
19062 {
19068 }
19070 /* NEG and ABS performed with SSE use bitwise mask operations.
19071 Create the appropriate mask now. */
19074 else
19084 {
19086 rtvec par;
19091 else
19092 {
19095 }
19097 }
19098 else
19100 }
19102 /* Expand a copysign operation. Special case operand 0 being a constant. */
19104 void
19106 {
19120 else
19124 {
19131 {
19134 else
19135 {
19139 }
19140 }
19150 else
19154 }
19155 else
19156 {
19166 else
19170 }
19171 }
19173 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19174 be a constant, and so has already been expanded into a vector constant. */
19176 void
19178 {
19194 {
19197 }
19198 }
19200 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19201 so we have to do two masks. */
19203 void
19205 {
19220 {
19221 /* Shouldn't happen often (it's useless, obviously), but when it does
19222 we'd generate incorrect code if we continue below. */
19225 }
19228 {
19239 }
19240 else
19241 {
19243 {
19245 }
19247 {
19251 }
19255 {
19258 }
19260 {
19265 }
19267 }
19271 }
19273 /* Return TRUE or FALSE depending on whether the first SET in INSN
19274 has source and destination with matching CC modes, and that the
19275 CC mode is at least as constrained as REQ_MODE. */
19277 bool
19279 {
19280 rtx set;
19291 {
19301 /* FALLTHRU */
19305 /* FALLTHRU */
19309 /* FALLTHRU */
19323 }
19326 }
19328 /* Generate insn patterns to do an integer compare of OPERANDS. */
19330 static rtx
19332 {
19339 /* This is very simple, but making the interface the same as in the
19340 FP case makes the rest of the code easier. */
19344 /* Return the test that should be put into the flags user, i.e.
19345 the bcc, scc, or cmov instruction. */
19347 }
19349 /* Figure out whether to use ordered or unordered fp comparisons.
19350 Return the appropriate mode to use. */
19352 enum machine_mode
19354 {
19355 /* ??? In order to make all comparisons reversible, we do all comparisons
19356 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19357 all forms trapping and nontrapping comparisons, we can make inequality
19358 comparisons trapping again, since it results in better code when using
19359 FCOM based compares. */
19361 }
19363 enum machine_mode
19365 {
19369 {
19372 }
19375 {
19376 /* Only zero flag is needed. */
19380 /* Codes needing carry flag. */
19383 /* Detect overflow checks. They need just the carry flag. */
19387 else
19392 /* Codes possibly doable only with sign flag when
19393 comparing against zero. */
19398 else
19399 /* For other cases Carry flag is not required. */
19401 /* Codes doable only with sign flag when comparing
19402 against zero, but we miss jump instruction for it
19403 so we need to use relational tests against overflow
19404 that thus needs to be zero. */
19409 else
19411 /* strcmp pattern do (use flags) and combine may ask us for proper
19412 mode. */
19417 }
19418 }
19420 /* Return the fixed registers used for condition codes. */
19422 static bool
19424 {
19428 }
19430 /* If two condition code modes are compatible, return a condition code
19431 mode which is compatible with both. Otherwise, return
19432 VOIDmode. */
19434 static enum machine_mode
19436 {
19453 {
19467 {
19481 }
19485 /* These are only compatible with themselves, which we already
19486 checked above. */
19488 }
19489 }
19492 /* Return a comparison we can do and that it is equivalent to
19493 swap_condition (code) apart possibly from orderedness.
19494 But, never change orderedness if TARGET_IEEE_FP, returning
19495 UNKNOWN in that case if necessary. */
19497 static enum rtx_code
19499 {
19501 {
19512 }
19513 }
19515 /* Return cost of comparison CODE using the best strategy for performance.
19516 All following functions do use number of instructions as a cost metrics.
19517 In future this should be tweaked to compute bytes for optimize_size and
19518 take into account performance of various instructions on various CPUs. */
19520 static int
19522 {
19525 /* The cost of code using bit-twiddling on %ah. */
19527 {
19550 }
19553 {
19560 }
19561 }
19563 /* Return strategy to use for floating-point. We assume that fcomi is always
19564 preferrable where available, since that is also true when looking at size
19565 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19567 enum ix86_fpcmp_strategy
19569 {
19570 /* Do fcomi/sahf based test when profitable. */
19579 }
19581 /* Swap, force into registers, or otherwise massage the two operands
19582 to a fp comparison. The operands are updated in place; the new
19583 comparison code is returned. */
19585 static enum rtx_code
19587 {
19593 /* All of the unordered compare instructions only work on registers.
19594 The same is true of the fcomi compare instructions. The XFmode
19595 compare instructions require registers except when comparing
19596 against zero or when converting operand 1 from fixed point to
19597 floating point. */
19606 {
19609 }
19610 else
19611 {
19612 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19613 things around if they appear profitable, otherwise force op0
19614 into a register. */
19620 {
19623 {
19624 rtx tmp;
19627 }
19628 }
19634 {
19639 {
19642 }
19643 else
19645 }
19646 }
19648 /* Try to rearrange the comparison to make it cheaper. */
19652 {
19653 rtx tmp;
19658 }
19663 }
19665 /* Convert comparison codes we use to represent FP comparison to integer
19666 code that will result in proper branch. Return UNKNOWN if no such code
19667 is available. */
19669 enum rtx_code
19671 {
19673 {
19696 }
19697 }
19699 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19701 static rtx
19703 {
19710 /* Do fcomi/sahf based test when profitable. */
19712 {
19717 tmp);
19725 tmp);
19734 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19741 /* In the unordered case, we have to check C2 for NaN's, which
19742 doesn't happen to work out to anything nice combination-wise.
19743 So do some bit twiddling on the value we've got in AH to come
19744 up with an appropriate set of condition codes. */
19748 {
19752 {
19755 }
19756 else
19757 {
19763 }
19768 {
19773 }
19774 else
19775 {
19778 }
19783 {
19786 }
19787 else
19788 {
19792 }
19797 {
19803 }
19804 else
19805 {
19808 }
19813 {
19818 }
19819 else
19820 {
19823 }
19828 {
19833 }
19834 else
19835 {
19838 }
19852 }
19857 }
19859 /* Return the test that should be put into the flags user, i.e.
19860 the bcc, scc, or cmov instruction. */
19863 const0_rtx);
19864 }
19866 static rtx
19868 {
19869 rtx ret;
19875 {
19878 }
19879 else
19883 }
19885 void
19887 {
19889 rtx tmp;
19892 {
19899 simple:
19903 pc_rtx);
19911 /* Expand DImode branch into multiple compare+branch. */
19912 {
19918 {
19921 }
19928 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19929 avoid two branches. This costs one extra insn, so disable when
19930 optimizing for size. */
19935 {
19953 }
19955 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19956 op1 is a constant and the low word is zero, then we can just
19957 examine the high word. Similarly for low word -1 and
19958 less-or-equal-than or greater-than. */
19962 {
19965 {
19968 }
19972 {
19975 }
19979 }
19981 /* Otherwise, we need two or three jumps. */
19990 {
20004 }
20006 /*
20007 * a < b =>
20008 * if (hi(a) < hi(b)) goto true;
20009 * if (hi(a) > hi(b)) goto false;
20010 * if (lo(a) < lo(b)) goto true;
20011 * false:
20012 */
20024 }
20029 }
20030 }
20032 /* Split branch based on floating point condition. */
20033 void
20036 {
20037 rtx condition;
20038 rtx i;
20041 {
20046 }
20049 tmp);
20057 }
20059 void
20061 {
20062 rtx ret;
20069 }
20071 /* Expand comparison setting or clearing carry flag. Return true when
20072 successful and set pop for the operation. */
20073 static bool
20075 {
20079 /* Do not handle double-mode compares that go through special path. */
20084 {
20089 /* Shortcut: following common codes never translate
20090 into carry flag compares. */
20095 /* These comparisons require zero flag; swap operands so they won't. */
20098 {
20103 }
20105 /* Try to expand the comparison and verify that we end up with
20106 carry flag based comparison. This fails to be true only when
20107 we decide to expand comparison using arithmetic that is not
20108 too common scenario. */
20117 else
20126 }
20132 {
20137 /* Convert a==0 into (unsigned)a<1. */
20146 /* Convert a>b into b<a or a>=b-1. */
20150 {
20152 /* Bail out on overflow. We still can swap operands but that
20153 would force loading of the constant into register. */
20158 }
20159 else
20160 {
20165 }
20168 /* Convert a>=0 into (unsigned)a<0x80000000. */
20186 }
20187 /* Swapping operands may cause constant to appear as first operand. */
20189 {
20193 }
20197 }
20199 bool
20201 {
20225 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20226 HImode insns, we'd be swallowed in word prefix ops. */
20232 {
20236 HOST_WIDE_INT diff;
20239 /* Sign bit compares are better done using shifts than we do by using
20240 sbb. */
20243 {
20244 /* Detect overlap between destination and compare sources. */
20248 {
20249 rtx flags;
20258 {
20260 compare_code
20262 }
20264 /* To simplify rest of code, restrict to the GEU case. */
20266 {
20272 }
20273 else
20274 {
20277 reverse_condition_maybe_unordered
20279 else
20282 }
20291 else
20294 }
20295 else
20296 {
20299 else
20300 {
20305 }
20307 }
20310 {
20311 /*
20312 * cmpl op0,op1
20313 * sbbl dest,dest
20314 * [addl dest, ct]
20315 *
20316 * Size 5 - 8.
20317 */
20322 }
20324 {
20325 /*
20326 * cmpl op0,op1
20327 * sbbl dest,dest
20328 * orl $ct, dest
20329 *
20330 * Size 8.
20331 */
20335 }
20337 {
20338 /*
20339 * cmpl op0,op1
20340 * sbbl dest,dest
20341 * notl dest
20342 * [addl dest, cf]
20343 *
20344 * Size 8 - 11.
20345 */
20351 }
20352 else
20353 {
20354 /*
20355 * cmpl op0,op1
20356 * sbbl dest,dest
20357 * [notl dest]
20358 * andl cf - ct, dest
20359 * [addl dest, ct]
20360 *
20361 * Size 8 - 11.
20362 */
20365 {
20369 }
20379 }
20385 }
20388 {
20391 HOST_WIDE_INT tmp;
20396 {
20399 /* We may be reversing unordered compare to normal compare, that
20400 is not valid in general (we may convert non-trapping condition
20401 to trapping one), however on i386 we currently emit all
20402 comparisons unordered. */
20405 }
20406 else
20407 {
20410 }
20411 }
20416 {
20421 {
20426 }
20427 }
20429 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20433 {
20434 /* If lea code below could be used, only optimize
20435 if it results in a 2 insn sequence. */
20441 {
20442 /*
20443 * notl op1 (if necessary)
20444 * sarl $31, op1
20445 * orl cf, op1
20446 */
20448 {
20452 }
20463 }
20464 }
20472 {
20473 /*
20474 * xorl dest,dest
20475 * cmpl op1,op2
20476 * setcc dest
20477 * lea cf(dest*(ct-cf)),dest
20478 *
20479 * Size 14.
20480 *
20481 * This also catches the degenerate setcc-only case.
20482 */
20484 rtx tmp;
20490 /* On x86_64 the lea instruction operates on Pmode, so we need
20491 to get arithmetics done in proper mode to match. */
20494 else
20495 {
20496 rtx out1;
20499 nops++;
20501 {
20503 nops++;
20504 }
20505 }
20507 {
20509 nops++;
20510 }
20512 {
20515 else
20517 }
20522 }
20524 /*
20525 * General case: Jumpful:
20526 * xorl dest,dest cmpl op1, op2
20527 * cmpl op1, op2 movl ct, dest
20528 * setcc dest jcc 1f
20529 * decl dest movl cf, dest
20530 * andl (cf-ct),dest 1:
20531 * addl ct,dest
20532 *
20533 * Size 20. Size 14.
20534 *
20535 * This is reasonably steep, but branch mispredict costs are
20536 * high on modern cpus, so consider failing only if optimizing
20537 * for space.
20538 */
20543 {
20545 {
20552 {
20555 /* We may be reversing unordered compare to normal compare,
20556 that is not valid in general (we may convert non-trapping
20557 condition to trapping one), however on i386 we currently
20558 emit all comparisons unordered. */
20560 }
20561 else
20562 {
20566 }
20567 }
20570 {
20571 /* notl op1 (if needed)
20572 sarl $31, op1
20573 andl (cf-ct), op1
20574 addl ct, op1
20576 For x < 0 (resp. x <= -1) there will be no notl,
20577 so if possible swap the constants to get rid of the
20578 complement.
20579 True/false will be -1/0 while code below (store flag
20580 followed by decrement) is 0/-1, so the constants need
20581 to be exchanged once more. */
20584 {
20587 }
20588 else
20589 {
20593 }
20596 }
20597 else
20598 {
20602 constm1_rtx,
20604 }
20616 }
20617 }
20620 {
20621 /* Try a few things more with specific constants and a variable. */
20623 optab op;
20629 /* If one of the two operands is an interesting constant, load a
20630 constant with the above and mask it in with a logical operation. */
20633 {
20639 else
20641 }
20643 {
20649 else
20651 }
20652 else
20659 /* Recurse to get the constant loaded. */
20663 /* Mask in the interesting variable. */
20665 OPTAB_WIDEN);
20670 }
20672 /*
20673 * For comparison with above,
20674 *
20675 * movl cf,dest
20676 * movl ct,tmp
20677 * cmpl op1,op2
20678 * cmovcc tmp,dest
20679 *
20680 * Size 15.
20681 */
20703 }
20705 /* Swap, force into registers, or otherwise massage the two operands
20706 to an sse comparison with a mask result. Thus we differ a bit from
20707 ix86_prepare_fp_compare_args which expects to produce a flags result.
20709 The DEST operand exists to help determine whether to commute commutative
20710 operators. The POP0/POP1 operands are updated in place. The new
20711 comparison code is returned, or UNKNOWN if not implementable. */
20713 static enum rtx_code
20716 {
20717 rtx tmp;
20720 {
20723 /* AVX supports all the needed comparisons. */
20726 /* We have no LTGT as an operator. We could implement it with
20727 NE & ORDERED, but this requires an extra temporary. It's
20728 not clear that it's worth it. */
20735 /* These are supported directly. */
20742 /* AVX has 3 operand comparisons, no need to swap anything. */
20745 /* For commutative operators, try to canonicalize the destination
20746 operand to be first in the comparison - this helps reload to
20747 avoid extra moves. */
20750 /* FALLTHRU */
20756 /* These are not supported directly before AVX, and furthermore
20757 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20758 comparison operands to transform into something that is
20759 supported. */
20768 }
20771 }
20773 /* Detect conditional moves that exactly match min/max operational
20774 semantics. Note that this is IEEE safe, as long as we don't
20775 interchange the operands.
20777 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20778 and TRUE if the operation is successful and instructions are emitted. */
20780 static bool
20783 {
20786 rtx tmp;
20789 ;
20791 {
20795 }
20796 else
20803 else
20808 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20809 but MODE may be a vector mode and thus not appropriate. */
20811 {
20813 rtvec v;
20818 }
20819 else
20820 {
20823 }
20827 }
20829 /* Expand an sse vector comparison. Return the register with the result. */
20831 static rtx
20834 {
20838 /* In general case result of comparison can differ from operands' type. */
20841 /* In AVX512F the result of comparison is an integer mask. */
20843 rtx x;
20846 {
20851 }
20852 else
20865 /* Compare patterns for int modes are unspec in AVX512F only. */
20867 {
20871 {
20880 }
20883 {
20886 }
20887 }
20891 {
20894 }
20895 else
20899 }
20901 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20902 operations. This is used for both scalar and vector conditional moves. */
20904 static void
20906 {
20910 /* In AVX512F the result of comparison is an integer mask. */
20918 {
20920 }
20923 {
20927 }
20930 {
20935 }
20938 {
20942 }
20945 {
20953 op_true,
20954 op_false)));
20955 }
20956 else
20957 {
20967 {
20981 {
20988 }
21003 {
21010 }
21028 }
21031 {
21035 }
21036 else
21037 {
21043 else
21055 }
21056 }
21057 }
21059 /* Expand a floating-point conditional move. Return true if successful. */
21061 bool
21063 {
21071 {
21074 /* Since we've no cmove for sse registers, don't force bad register
21075 allocation just to gain access to it. Deny movcc when the
21076 comparison mode doesn't match the move mode. */
21095 }
21102 /* The floating point conditional move instructions don't directly
21103 support conditions resulting from a signed integer comparison. */
21107 {
21112 }
21119 }
21121 /* Expand a floating-point vector conditional move; a vcond operation
21122 rather than a movcc operation. */
21124 bool
21126 {
21128 rtx cmp;
21133 {
21134 rtx temp;
21136 {
21153 }
21155 OPTAB_DIRECT);
21158 }
21168 }
21170 /* Expand a signed/unsigned integral vector conditional move. */
21172 bool
21174 {
21184 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21185 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21194 {
21198 {
21204 }
21207 {
21213 }
21214 }
21223 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21227 ;
21228 else
21229 {
21230 /* Canonicalize the comparison to EQ, GT, GTU. */
21232 {
21249 /* FALLTHRU */
21259 }
21261 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21263 {
21265 {
21267 /* SSE4.1 supports EQ. */
21274 /* SSE4.2 supports GT/GTU. */
21281 }
21282 }
21284 /* Unsigned parallel compare is not supported by the hardware.
21285 Play some tricks to turn this into a signed comparison
21286 against 0. */
21288 {
21292 {
21299 {
21304 {
21313 }
21314 /* Subtract (-(INT MAX) - 1) from both operands to make
21315 them signed. */
21326 }
21333 /* Perform a parallel unsigned saturating subtraction. */
21346 }
21347 }
21348 }
21350 /* Allow the comparison to be done in one mode, but the movcc to
21351 happen in another mode. */
21353 {
21356 }
21357 else
21358 {
21364 }
21369 }
21371 static bool
21373 {
21376 {
21380 op1));
21385 op1));
21397 }
21398 }
21400 /* Expand a variable vector permutation. */
21402 void
21404 {
21415 /* Number of elements in the vector. */
21424 {
21426 {
21427 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21428 an constant shuffle operand. With a tiny bit of effort we can
21429 use VPERMD instead. A re-interpretation stall for V4DFmode is
21430 unfortunate but there's no avoiding it.
21431 Similarly for V16HImode we don't have instructions for variable
21432 shuffling, while for V32QImode we can use after preparing suitable
21433 masks vpshufb; vpshufb; vpermq; vpor. */
21436 {
21440 }
21441 else
21442 {
21446 }
21449 /* Replicate the low bits of the V4DImode mask into V8SImode:
21450 mask = { A B C D }
21451 t1 = { A A B B C C D D }. */
21459 else
21462 /* Multiply the shuffle indicies by two. */
21464 OPTAB_DIRECT);
21466 /* Add one to the odd shuffle indicies:
21467 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21469 {
21472 }
21476 OPTAB_DIRECT);
21478 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21483 }
21486 {
21488 /* The VPERMD and VPERMPS instructions already properly ignore
21489 the high bits of the shuffle elements. No need for us to
21490 perform an AND ourselves. */
21492 {
21497 }
21498 else
21499 {
21505 }
21512 else
21513 {
21519 }
21523 /* By combining the two 128-bit input vectors into one 256-bit
21524 input vector, we can use VPERMD and VPERMPS for the full
21525 two-operand shuffle. */
21557 /* From mask create two adjusted masks, which contain the same
21558 bits as mask in the low 7 bits of each vector element.
21559 The first mask will have the most significant bit clear
21560 if it requests element from the same 128-bit lane
21561 and MSB set if it requests element from the other 128-bit lane.
21562 The second mask will have the opposite values of the MSB,
21563 and additionally will have its 128-bit lanes swapped.
21564 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21565 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21566 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21567 stands for other 12 bytes. */
21568 /* The bit whether element is from the same lane or the other
21569 lane is bit 4, so shift it up by 3 to the MSB position. */
21573 /* Clear MSB bits from the mask just in case it had them set. */
21575 /* After this t1 will have MSB set for elements from other lane. */
21577 /* Clear bits other than MSB. */
21579 /* Or in the lower bits from mask into t3. */
21581 /* And invert MSB bits in t1, so MSB is set for elements from the same
21582 lane. */
21584 /* Swap 128-bit lanes in t3. */
21589 /* And or in the lower bits from mask into t1. */
21592 {
21593 /* Each of these shuffles will put 0s in places where
21594 element from the other 128-bit lane is needed, otherwise
21595 will shuffle in the requested value. */
21599 /* For t3 the 128-bit lanes are swapped again. */
21604 /* And oring both together leads to the result. */
21611 }
21614 /* Similarly to the above one_operand_shuffle code,
21615 just for repeated twice for each operand. merge_two:
21616 code will merge the two results together. */
21640 }
21641 }
21644 {
21645 /* The XOP VPPERM insn supports three inputs. By ignoring the
21646 one_operand_shuffle special case, we avoid creating another
21647 set of constant vectors in memory. */
21650 /* mask = mask & {2*w-1, ...} */
21652 }
21653 else
21654 {
21655 /* mask = mask & {w-1, ...} */
21657 }
21665 /* For non-QImode operations, convert the word permutation control
21666 into a byte permutation control. */
21668 {
21673 /* Convert mask to vector of chars. */
21676 /* Replicate each of the input bytes into byte positions:
21677 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21678 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21679 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21686 else
21689 /* Convert it into the byte positions by doing
21690 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21696 }
21698 /* The actual shuffle operations all operate on V16QImode. */
21703 {
21710 }
21712 {
21719 }
21720 else
21721 {
21725 /* Shuffle the two input vectors independently. */
21731 merge_two:
21732 /* Then merge them together. The key is whether any given control
21733 element contained a bit set that indicates the second word. */
21737 {
21738 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21739 more shuffle to convert the V2DI input mask into a V4SI
21740 input mask. At which point the masking that expand_int_vcond
21741 will work as desired. */
21749 }
21771 }
21772 }
21774 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21775 true if we should do zero extension, else sign extension. HIGH_P is
21776 true if we want the N/2 high elements, else the low elements. */
21778 void
21780 {
21782 rtx tmp;
21785 {
21791 {
21795 else
21798 extract
21804 else
21807 extract
21813 else
21816 extract
21822 else
21825 extract
21831 else
21834 extract
21840 else
21846 else
21852 else
21857 }
21860 {
21863 }
21865 {
21866 /* Shift higher 8 bytes to lower 8 bytes. */
21871 }
21872 else
21876 }
21877 else
21878 {
21882 {
21886 else
21892 else
21898 else
21903 }
21907 else
21914 }
21915 }
21917 /* Expand conditional increment or decrement using adb/sbb instructions.
21918 The default case using setcc followed by the conditional move can be
21919 done by generic code. */
21920 bool
21922 {
21924 rtx flags;
21926 rtx compare_op;
21944 {
21947 }
21950 {
21954 reverse_condition_maybe_unordered
21956 else
21958 }
21962 /* Construct either adc or sbb insn. */
21964 {
21966 {
21981 }
21982 }
21983 else
21984 {
21986 {
22001 }
22002 }
22006 }
22009 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22010 but works for floating pointer parameters and nonoffsetable memories.
22011 For pushes, it returns just stack offsets; the values will be saved
22012 in the right order. Maximally three parts are generated. */
22014 static int
22016 {
22021 else
22027 /* Optimize constant pool reference to immediates. This is used by fp
22028 moves, that force all constants to memory to allow combining. */
22030 {
22034 }
22037 {
22038 /* The only non-offsetable memories we handle are pushes. */
22047 }
22050 {
22052 /* Caution: if we looked through a constant pool memory above,
22053 the operand may actually have a different mode now. That's
22054 ok, since we want to pun this all the way back to an integer. */
22058 }
22061 {
22064 else
22065 {
22069 {
22073 }
22075 {
22080 }
22082 {
22083 REAL_VALUE_TYPE r;
22088 {
22095 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22096 long double may not be 80-bit. */
22105 }
22108 }
22109 else
22111 }
22112 }
22113 else
22114 {
22118 {
22121 {
22125 }
22127 {
22131 }
22133 {
22134 REAL_VALUE_TYPE r;
22140 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22143 = gen_int_mode
22146 DImode);
22147 else
22154 = gen_int_mode
22157 DImode);
22158 else
22160 }
22161 else
22163 }
22164 }
22167 }
22169 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22170 Return false when normal moves are needed; true when all required
22171 insns have been emitted. Operands 2-4 contain the input values
22172 int the correct order; operands 5-7 contain the output values. */
22174 void
22176 {
22184 /* The DFmode expanders may ask us to move double.
22185 For 64bit target this is single move. By hiding the fact
22186 here we simplify i386.md splitters. */
22188 {
22189 /* Optimize constant pool reference to immediates. This is used by
22190 fp moves, that force all constants to memory to allow combining. */
22197 {
22200 }
22201 else
22206 }
22208 /* The only non-offsettable memory we handle is push. */
22211 else
22218 /* When emitting push, take care for source operands on the stack. */
22221 {
22224 /* Compensate for the stack decrement by 4. */
22229 /* src_base refers to the stack pointer and is
22230 automatically decreased by emitted push. */
22234 }
22236 /* We need to do copy in the right order in case an address register
22237 of the source overlaps the destination. */
22239 {
22240 rtx tmp;
22243 {
22247 collisions++;
22248 }
22250 /* Collision in the middle part can be handled by reordering. */
22252 {
22255 }
22259 {
22261 {
22264 }
22265 else
22266 {
22269 }
22270 }
22272 /* If there are more collisions, we can't handle it by reordering.
22273 Do an lea to the last part and use only one colliding move. */
22275 {
22276 rtx base;
22282 /* Handle the case when the last part isn't valid for lea.
22283 Happens in 64-bit mode storing the 12-byte XFmode. */
22290 {
22293 }
22294 }
22295 }
22298 {
22300 {
22302 {
22307 }
22309 {
22312 }
22313 }
22314 else
22315 {
22316 /* In 64bit mode we don't have 32bit push available. In case this is
22317 register, it is OK - we will just use larger counterpart. We also
22318 retype memory - these comes from attempt to avoid REX prefix on
22319 moving of second half of TFmode value. */
22321 {
22323 {
22334 }
22338 }
22339 }
22343 }
22345 /* Choose correct order to not overwrite the source before it is copied. */
22355 {
22357 {
22360 }
22361 }
22362 else
22363 {
22365 {
22368 }
22369 }
22371 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22373 {
22382 }
22388 }
22390 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22391 left shift by a constant, either using a single shift or
22392 a sequence of add instructions. */
22394 static void
22396 {
22402 {
22406 }
22407 else
22408 {
22411 }
22412 }
22414 void
22416 {
22425 {
22430 {
22436 }
22437 else
22438 {
22446 }
22448 }
22455 {
22456 /* Assuming we've chosen a QImode capable registers, then 1 << N
22457 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22459 {
22475 }
22477 /* Otherwise, we can get the same results by manually performing
22478 a bit extract operation on bit 5/6, and then performing the two
22479 shifts. The two methods of getting 0/1 into low/high are exactly
22480 the same size. Avoiding the shift in the bit extract case helps
22481 pentium4 a bit; no one else seems to care much either way. */
22482 else
22483 {
22488 HOST_WIDE_INT bits;
22489 rtx x;
22492 {
22498 }
22499 else
22500 {
22506 }
22510 else
22518 }
22523 }
22526 {
22527 /* For -1 << N, we can avoid the shld instruction, because we
22528 know that we're shifting 0...31/63 ones into a -1. */
22532 else
22534 }
22535 else
22536 {
22544 }
22549 {
22555 }
22556 else
22557 {
22562 }
22563 }
22565 void
22567 {
22577 {
22582 {
22588 }
22590 {
22599 }
22600 else
22601 {
22609 }
22610 }
22611 else
22612 {
22624 {
22632 scratch));
22633 }
22634 else
22635 {
22640 }
22641 }
22642 }
22644 void
22646 {
22656 {
22661 {
22668 }
22669 else
22670 {
22678 }
22679 }
22680 else
22681 {
22693 {
22699 scratch));
22700 }
22701 else
22702 {
22707 }
22708 }
22709 }
22711 /* Predict just emitted jump instruction to be taken with probability PROB. */
22712 static void
22714 {
22718 }
22720 /* Helper function for the string operations below. Dest VARIABLE whether
22721 it is aligned to VALUE bytes. If true, jump to the label. */
22722 static rtx
22724 {
22729 else
22735 else
22738 }
22740 /* Adjust COUNTER by the VALUE. */
22741 static void
22743 {
22748 }
22750 /* Zero extend possibly SImode EXP to Pmode register. */
22751 rtx
22753 {
22755 }
22757 /* Divide COUNTREG by SCALE. */
22758 static rtx
22760 {
22761 rtx sc;
22773 }
22775 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22776 DImode for constant loop counts. */
22778 static enum machine_mode
22780 {
22788 }
22790 /* Copy the address to a Pmode register. This is used for x32 to
22791 truncate DImode TLS address to a SImode register. */
22793 static rtx
22795 {
22798 else
22799 {
22802 }
22803 }
22805 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22806 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22807 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22808 memory by VALUE (supposed to be in MODE).
22810 The size is rounded down to whole number of chunk size moved at once.
22811 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22814 static void
22819 {
22825 rtx size;
22834 /* Those two should combine. */
22836 {
22840 }
22847 /* This assert could be relaxed - in this case we'll need to compute
22848 smallest power of two, containing in PIECE_SIZE_N and pass it to
22849 offset_address. */
22855 {
22859 /* When unrolling for chips that reorder memory reads and writes,
22860 we can save registers by using single temporary.
22861 Also using 4 temporaries is overkill in 32bit mode. */
22863 {
22865 {
22867 {
22868 destmem =
22870 srcmem =
22872 }
22874 }
22875 }
22876 else
22877 {
22881 {
22884 {
22885 srcmem =
22887 }
22889 }
22891 {
22893 {
22894 destmem =
22896 }
22898 }
22899 }
22900 }
22901 else
22903 {
22905 destmem =
22908 }
22918 {
22924 else
22926 }
22927 else
22935 {
22940 }
22942 }
22944 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
22945 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
22946 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
22947 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
22948 ORIG_VALUE is the original value passed to memset to fill the memory with.
22949 Other arguments have same meaning as for previous function. */
22951 static void
22954 rtx count,
22956 {
22957 rtx destexp;
22958 rtx srcexp;
22959 rtx countreg;
22960 HOST_WIDE_INT rounded_count;
22962 /* If possible, it is shorter to use rep movs.
22963 TODO: Maybe it is better to move this logic to decide_alg. */
22974 {
22978 }
22979 else
22982 {
22987 }
22992 {
22995 }
22996 else
22997 {
23001 {
23005 }
23006 else
23009 {
23014 }
23015 else
23016 {
23019 }
23022 }
23023 }
23025 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23026 DESTMEM.
23027 SRC is passed by pointer to be updated on return.
23028 Return value is updated DST. */
23029 static rtx
23031 HOST_WIDE_INT size_to_move)
23032 {
23038 /* Find the widest mode in which we could perform moves.
23039 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23040 it until move of such size is supported. */
23045 {
23049 }
23051 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23052 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23054 {
23059 {
23063 }
23064 }
23070 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23074 {
23075 /* We move from memory to memory, so we'll need to do it via
23076 a temporary register. */
23087 piece_size);
23089 piece_size);
23090 }
23092 /* Update DST and SRC rtx. */
23095 }
23097 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23098 static void
23101 {
23104 {
23109 /* For now MAX_SIZE should be a power of 2. This assert could be
23110 relaxed, but it'll require a bit more complicated epilogue
23111 expanding. */
23114 {
23117 }
23119 }
23121 {
23127 }
23129 /* When there are stringops, we can cheaply increase dest and src pointers.
23130 Otherwise we save code size by maintaining offset (zero is readily
23131 available from preceding rep operation) and using x86 addressing modes.
23132 */
23134 {
23136 {
23143 }
23145 {
23152 }
23154 {
23161 }
23162 }
23163 else
23164 {
23166 rtx tmp;
23169 {
23180 }
23182 {
23195 }
23197 {
23206 }
23207 }
23208 }
23210 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23211 with value PROMOTED_VAL.
23212 SRC is passed by pointer to be updated on return.
23213 Return value is updated DST. */
23214 static rtx
23216 HOST_WIDE_INT size_to_move)
23217 {
23223 /* Find the widest mode in which we could perform moves.
23224 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23225 it until move of such size is supported. */
23230 {
23233 }
23240 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23244 {
23246 {
23249 piece_size);
23251 }
23259 piece_size);
23260 }
23262 /* Update DST rtx. */
23264 }
23265 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23266 static void
23269 {
23270 count =
23276 }
23278 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23279 static void
23282 {
23283 rtx dest;
23286 {
23291 /* For now MAX_SIZE should be a power of 2. This assert could be
23292 relaxed, but it'll require a bit more complicated epilogue
23293 expanding. */
23296 {
23298 {
23301 else
23303 }
23304 }
23306 }
23308 {
23311 }
23313 {
23316 {
23321 }
23322 else
23323 {
23332 }
23335 }
23337 {
23340 {
23343 }
23344 else
23345 {
23350 }
23353 }
23355 {
23361 }
23363 {
23369 }
23371 {
23377 }
23378 }
23380 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23381 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23382 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23383 ignored.
23384 Return value is updated DESTMEM. */
23385 static rtx
23390 {
23393 {
23395 {
23398 {
23401 else
23403 }
23404 else
23410 }
23411 }
23413 }
23415 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23416 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23417 and jump to DONE_LABEL. */
23418 static void
23424 {
23427 rtx modesize;
23430 /* If we do not have vector value to copy, we must reduce size. */
23432 {
23434 {
23439 }
23440 else
23442 }
23443 else
23444 {
23445 /* Choose appropriate vector mode. */
23451 }
23456 {
23459 else
23460 {
23463 }
23465 }
23471 {
23475 }
23477 {
23480 else
23481 {
23484 }
23486 }
23492 }
23494 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23495 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23496 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23497 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23498 DONE_LABEL is a label after the whole copying sequence. The label is created
23499 on demand if *DONE_LABEL is NULL.
23500 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23501 bounds after the initial copies.
23503 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23504 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23505 we will dispatch to a library call for large blocks.
23507 In pseudocode we do:
23509 if (COUNT < SIZE)
23510 {
23511 Assume that SIZE is 4. Bigger sizes are handled analogously
23512 if (COUNT & 4)
23513 {
23514 copy 4 bytes from SRCPTR to DESTPTR
23515 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23516 goto done_label
23517 }
23518 if (!COUNT)
23519 goto done_label;
23520 copy 1 byte from SRCPTR to DESTPTR
23521 if (COUNT & 2)
23522 {
23523 copy 2 bytes from SRCPTR to DESTPTR
23524 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23525 }
23526 }
23527 else
23528 {
23529 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23530 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23532 OLD_DESPTR = DESTPTR;
23533 Align DESTPTR up to DESIRED_ALIGN
23534 SRCPTR += DESTPTR - OLD_DESTPTR
23535 COUNT -= DEST_PTR - OLD_DESTPTR
23536 if (DYNAMIC_CHECK)
23537 Round COUNT down to multiple of SIZE
23538 << optional caller supplied zero size guard is here >>
23539 << optional caller suppplied dynamic check is here >>
23540 << caller supplied main copy loop is here >>
23541 }
23542 done_label:
23543 */
23544 static void
23557 {
23560 rtx modesize;
23562 rtx mode_value;
23564 /* Chose proper value to copy. */
23567 else
23571 /* See if block is big or small, handle small blocks. */
23573 {
23584 /* Handle sizes > 3. */
23591 /* Nothing to copy? Jump to DONE_LABEL if so */
23595 /* Do a byte copy. */
23599 else
23600 {
23603 }
23605 /* Handle sizes 2 and 3. */
23612 else
23613 {
23618 }
23624 }
23625 else
23629 /* Start memcpy for COUNT >= SIZE. */
23631 {
23634 }
23636 /* Copy first desired_align bytes. */
23642 {
23645 else
23646 {
23649 }
23652 }
23655 /* Copy last SIZE bytes. */
23662 else
23663 {
23669 }
23671 {
23675 else
23676 {
23679 }
23680 }
23682 /* Align destination. */
23684 {
23688 /* Align destptr up, place it to new register. */
23695 /* See how many bytes we skipped. */
23699 /* Adjust srcptr and count. */
23705 /* We copied at most size + prolog_size. */
23708 else
23711 /* Our loops always round down the bock size, but for dispatch to library
23712 we need precise value. */
23716 }
23717 else
23718 {
23720 /* Decrease count, so we won't end up copying last word twice. */
23724 else
23728 }
23729 }
23732 /* This function is like the previous one, except here we know how many bytes
23733 need to be copied. That allows us to update alignment not only of DST, which
23734 is returned, but also of SRC, which is passed as a pointer for that
23735 reason. */
23736 static rtx
23741 {
23749 {
23753 }
23758 {
23760 {
23762 {
23765 else
23767 }
23768 else
23771 }
23772 }
23779 {
23785 {
23788 {
23792 }
23797 }
23801 }
23804 }
23806 /* Return true if ALG can be used in current context.
23807 Assume we expand memset if MEMSET is true. */
23808 static bool
23810 {
23815 /* Algorithms using the rep prefix want at least edi and ecx;
23816 additionally, memset wants eax and memcpy wants esi. Don't
23817 consider such algorithms if the user has appropriated those
23818 registers for their own purposes. */
23825 }
23827 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23828 static enum stringop_alg
23832 {
23843 /* Even if the string operation call is cold, we still might spend a lot
23844 of time processing large blocks. */
23850 else
23856 else
23859 /* See maximal size for user defined algorithm. */
23861 {
23868 }
23870 /* If expected size is not known but max size is small enough
23871 so inline version is a win, set expected size into
23872 the range. */
23877 /* If user specified the algorithm, honnor it if possible. */
23881 /* rep; movq or rep; movl is the smallest variant. */
23883 {
23888 else
23891 }
23892 /* Very tiny blocks are best handled via the loop, REP is expensive to
23893 setup. */
23897 {
23901 {
23902 /* We get here if the algorithms that were not libcall-based
23903 were rep-prefix based and we are unable to use rep prefixes
23904 based on global register usage. Break out of the loop and
23905 use the heuristic below. */
23909 {
23913 {
23916 }
23917 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
23918 last non-libcall inline algorithm. */
23920 {
23921 /* When the current size is best to be copied by a libcall,
23922 but we are still forced to inline, run the heuristic below
23923 that will pick code for medium sized blocks. */
23925 {
23928 }
23930 }
23932 {
23935 }
23936 }
23937 }
23938 }
23939 /* When asked to inline the call anyway, try to pick meaningful choice.
23940 We look for maximal size of block that is faster to copy by hand and
23941 take blocks of at most of that size guessing that average size will
23942 be roughly half of the block.
23944 If this turns out to be bad, we might simply specify the preferred
23945 choice in ix86_costs. */
23949 {
23952 /* If there aren't any usable algorithms, then recursing on
23953 smaller sizes isn't going to find anything. Just return the
23954 simple byte-at-a-time copy loop. */
23956 {
23957 /* Pick something reasonable. */
23961 }
23971 }
23974 }
23976 /* Decide on alignment. We know that the operand is already aligned to ALIGN
23977 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
23978 static int
23983 {
23994 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
23995 copying whole cacheline at once. */
24008 }
24011 /* Helper function for memcpy. For QImode value 0xXY produce
24012 0xXYXYXYXY of wide specified by MODE. This is essentially
24013 a * 0x10101010, but we can do slightly better than
24014 synth_mult by unwinding the sequence by hand on CPUs with
24015 slow multiply. */
24016 static rtx
24018 {
24020 rtx tmp;
24027 {
24035 }
24044 nops--;
24049 {
24053 OPTAB_DIRECT);
24054 }
24055 else
24056 {
24062 else
24064 else
24065 {
24068 reg =
24070 }
24080 }
24081 }
24083 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24084 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24085 alignment from ALIGN to DESIRED_ALIGN. */
24086 static rtx
24089 {
24090 rtx promoted_val;
24099 else
24103 }
24105 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24106 operations when profitable. The code depends upon architecture, block size
24107 and alignment, but always has one of the following overall structures:
24109 Aligned move sequence:
24111 1) Prologue guard: Conditional that jumps up to epilogues for small
24112 blocks that can be handled by epilogue alone. This is faster
24113 but also needed for correctness, since prologue assume the block
24114 is larger than the desired alignment.
24116 Optional dynamic check for size and libcall for large
24117 blocks is emitted here too, with -minline-stringops-dynamically.
24119 2) Prologue: copy first few bytes in order to get destination
24120 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24121 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24122 copied. We emit either a jump tree on power of two sized
24123 blocks, or a byte loop.
24125 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24126 with specified algorithm.
24128 4) Epilogue: code copying tail of the block that is too small to be
24129 handled by main body (or up to size guarded by prologue guard).
24131 Misaligned move sequence
24133 1) missaligned move prologue/epilogue containing:
24134 a) Prologue handling small memory blocks and jumping to done_label
24135 (skipped if blocks are known to be large enough)
24136 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24137 needed by single possibly misaligned move
24138 (skipped if alignment is not needed)
24139 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24141 2) Zero size guard dispatching to done_label, if needed
24143 3) dispatch to library call, if needed,
24145 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24146 with specified algorithm. */
24147 bool
24153 {
24154 rtx destreg;
24157 rtx tmp;
24173 /* TODO: Once value ranges are available, fill in proper data. */
24181 /* i386 can do misaligned access on reasonably increased cost. */
24185 /* ALIGN is the minimum of destination and source alignment, but we care here
24186 just about destination alignment. */
24192 {
24195 /* When COUNT is 0, there is nothing to do. */
24198 }
24199 else
24200 {
24209 }
24211 /* Make sure we don't need to care about overflow later on. */
24215 /* Step 0: Decide on preferred algorithm, desired alignment and
24216 size of chunks to be copied by main loop. */
24218 issetmem,
24225 /* For now vector-version of memset is generated only for memory zeroing, as
24226 creating of promoted vector value is very cheap in this case. */
24239 {
24258 /* Find the widest supported mode. */
24264 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24265 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24267 {
24272 }
24284 }
24292 /* Step 1: Prologue guard. */
24294 /* Alignment code needs count to be in register. */
24296 {
24299 {
24300 align_bytes
24304 else
24306 }
24309 }
24312 /* Misaligned move sequences handle both prologue and epilogue at once.
24313 Default code generation results in a smaller code for large alignments
24314 and also avoids redundant job when sizes are known precisely. */
24315 misaligned_prologue_used
24316 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24322 /* Do the cheap promotion to allow better CSE across the
24323 main loop and epilogue (ie one load of the big constant in the
24324 front of all code.
24325 For now the misaligned move sequences do not have fast path
24326 without broadcasting. */
24328 {
24330 {
24336 }
24337 else
24338 {
24341 }
24342 }
24343 /* Misaligned move sequences handles both prologues and epilogues at once.
24344 Default code generation results in smaller code for large alignments and
24345 also avoids redundant job when sizes are known precisely. */
24347 {
24348 /* Misaligned move prologue handled small blocks by itself. */
24349 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24354 desired_align < align
24363 {
24364 /* It is possible that we copied enough so the main loop will not
24365 execute. */
24375 else
24377 }
24378 }
24379 /* Ensure that alignment prologue won't copy past end of block. */
24381 {
24383 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24384 Make sure it is power of 2. */
24387 /* To improve performance of small blocks, we jump around the VAL
24388 promoting mode. This mean that if the promoted VAL is not constant,
24389 we might not use it in the epilogue and have to use byte
24390 loop variant. */
24395 {
24396 /* If main algorithm works on QImode, no epilogue is needed.
24397 For small sizes just don't align anything. */
24400 else
24402 }
24405 {
24412 else
24414 }
24415 }
24417 /* Emit code to decide on runtime whether library call or inline should be
24418 used. */
24420 {
24422 {
24424 {
24428 }
24429 }
24430 else
24431 {
24441 else
24445 }
24446 }
24448 /* Step 2: Alignment prologue. */
24449 /* Do the expensive promotion once we branched off the small blocks. */
24455 {
24457 {
24458 /* Except for the first move in prologue, we no longer know
24459 constant offset in aliasing info. It don't seems to worth
24460 the pain to maintain it for the first move, so throw away
24461 the info early. */
24468 issetmem);
24469 /* At most desired_align - align bytes are copied. */
24472 else
24474 }
24475 else
24476 {
24477 /* If we know how many bytes need to be stored before dst is
24478 sufficiently aligned, maintain aliasing info accurately. */
24480 srcreg,
24481 promoted_val,
24482 vec_promoted_val,
24483 desired_align,
24484 align_bytes,
24485 issetmem);
24492 }
24494 && !min_size
24499 {
24500 /* It is possible that we copied enough so the main loop will not
24501 execute. */
24511 else
24513 }
24514 }
24516 {
24523 }
24527 /* Step 3: Main loop. */
24530 {
24553 }
24554 /* Adjust properly the offset of src and dest memory for aliasing. */
24556 {
24562 }
24563 else
24564 {
24568 }
24570 /* Step 4: Epilogue to copy the remaining bytes. */
24571 epilogue:
24573 {
24574 /* When the main loop is done, COUNT_EXP might hold original count,
24575 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24576 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24577 bytes. Compensate if needed. */
24580 {
24581 tmp =
24584 OPTAB_DIRECT);
24587 }
24590 }
24593 {
24596 epilogue_size_needed);
24597 else
24598 {
24602 epilogue_size_needed);
24603 else
24605 epilogue_size_needed);
24606 }
24607 }
24611 }
24614 /* Expand the appropriate insns for doing strlen if not just doing
24615 repnz; scasb
24617 out = result, initialized with the start address
24618 align_rtx = alignment of the address.
24619 scratch = scratch register, initialized with the startaddress when
24620 not aligned, otherwise undefined
24622 This is just the body. It needs the initializations mentioned above and
24623 some address computing at the end. These things are done in i386.md. */
24625 static void
24627 {
24629 rtx tmp;
24634 rtx mem;
24637 rtx cmp;
24643 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24645 /* Is there a known alignment and is it less than 4? */
24647 {
24650 /* Is there a known alignment and is it not 2? */
24652 {
24656 /* Leave just the 3 lower bits. */
24666 }
24667 else
24668 {
24669 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24670 check if is aligned to 4 - byte. */
24677 }
24681 /* Now compare the bytes. */
24683 /* Compare the first n unaligned byte on a byte per byte basis. */
24687 /* Increment the address. */
24690 /* Not needed with an alignment of 2 */
24692 {
24696 end_0_label);
24701 }
24704 end_0_label);
24707 }
24709 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24710 align this loop. It gives only huge programs, but does not help to
24711 speed up. */
24718 /* This formula yields a nonzero result iff one of the bytes is zero.
24719 This saves three branches inside loop and many cycles. */
24727 align_4_label);
24730 {
24736 /* If zero is not in the first two bytes, move two bytes forward. */
24742 reg,
24743 tmpreg)));
24744 /* Emit lea manually to avoid clobbering of flags. */
24752 reg2,
24753 out)));
24754 }
24755 else
24756 {
24758 /* Is zero in the first two bytes? */
24765 pc_rtx);
24769 /* Not in the first two. Move two bytes forward. */
24775 }
24777 /* Avoid branch in fixing the byte. */
24785 }
24787 /* Expand strlen. */
24789 bool
24791 {
24794 /* The generic case of strlen expander is long. Avoid it's
24795 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24798 && !TARGET_INLINE_ALL_STRINGOPS
24808 {
24809 /* Well it seems that some optimizer does not combine a call like
24810 foo(strlen(bar), strlen(bar));
24811 when the move and the subtraction is done here. It does calculate
24812 the length just once when these instructions are done inside of
24813 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24814 often used and I use one fewer register for the lifetime of
24815 output_strlen_unroll() this is better. */
24821 /* strlensi_unroll_1 returns the address of the zero at the end of
24822 the string, like memchr(), so compute the length by subtracting
24823 the start address. */
24825 }
24826 else
24827 {
24828 rtx unspec;
24830 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24843 /* If .md starts supporting :P, this can be done in .md. */
24849 }
24851 }
24853 /* For given symbol (function) construct code to compute address of it's PLT
24854 entry in large x86-64 PIC model. */
24855 static rtx
24857 {
24870 }
24872 rtx
24874 rtx callarg2,
24876 {
24877 unsigned int const cregs_size
24888 {
24889 #if TARGET_MACHO
24892 #endif
24893 }
24894 else
24895 {
24896 /* Static functions and indirect calls don't need the pic register. */
24898 && (!TARGET_64BIT
24904 }
24907 {
24911 }
24914 && !TARGET_PECOFF
24922 {
24925 }
24933 {
24937 }
24941 {
24945 UNSPEC_MS_TO_SYSV_CALL);
24948 {
24954 }
24955 }
24964 }
24966 /* Output the assembly for a call instruction. */
24970 {
24976 {
24979 /* SEH epilogue detection requires the indirect branch case
24980 to include REX.W. */
24983 else
24988 }
24990 /* SEH unwinding can require an extra nop to be emitted in several
24991 circumstances. Determine if we have one of those. */
24993 {
24994 rtx i;
24997 {
24998 /* If we get to another real insn, we don't need the nop. */
25002 /* If we get to the epilogue note, prevent a catch region from
25003 being adjacent to the standard epilogue sequence. If non-
25004 call-exceptions, we'll have done this during epilogue emission. */
25006 && !flag_non_call_exceptions
25008 {
25011 }
25012 }
25014 /* If we didn't find a real insn following the call, prevent the
25015 unwinder from looking into the next function. */
25018 }
25022 else
25031 }
25032 \f
25033 /* Clear stack slot assignments remembered from previous functions.
25034 This is called from INIT_EXPANDERS once before RTL is emitted for each
25035 function. */
25039 {
25047 }
25049 /* Return a MEM corresponding to a stack slot with mode MODE.
25050 Allocate a new slot if necessary.
25052 The RTL for a function can have several slots available: N is
25053 which slot to use. */
25055 rtx
25057 {
25074 }
25076 static void
25078 {
25084 }
25085 \f
25086 /* Check whether x86 address PARTS is a pc-relative address. */
25088 static bool
25090 {
25098 {
25100 {
25117 }
25118 }
25120 }
25122 /* Calculate the length of the memory address in the instruction encoding.
25123 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25124 or other prefixes. We never generate addr32 prefix for LEA insn. */
25126 int
25128 {
25145 /* If this is not LEA instruction, add the length of addr32 prefix. */
25150 len++;
25164 /* Rule of thumb:
25165 - esp as the base always wants an index,
25166 - ebp as the base always wants a displacement,
25167 - r12 as the base always wants an index,
25168 - r13 as the base always wants a displacement. */
25170 /* Register Indirect. */
25172 {
25173 /* esp (for its index) and ebp (for its displacement) need
25174 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25175 code. */
25182 len++;
25183 }
25185 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25186 is not disp32, but disp32(%rip), so for disp32
25187 SIB byte is needed, unless print_operand_address
25188 optimizes it into disp32(%rip) or (%rip) is implied
25189 by UNSPEC. */
25191 {
25194 len++;
25195 }
25196 else
25197 {
25198 /* Find the length of the displacement constant. */
25200 {
25203 else
25205 }
25206 /* ebp always wants a displacement. Similarly r13. */
25208 len++;
25210 /* An index requires the two-byte modrm form.... */
25212 /* ...like esp (or r12), which always wants an index. */
25216 len++;
25217 }
25220 }
25222 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25223 is set, expect that insn have 8bit immediate alternative. */
25224 int
25226 {
25232 {
25237 {
25240 {
25252 }
25254 {
25257 }
25258 }
25260 {
25270 /* Immediates for DImode instructions are encoded
25271 as 32bit sign extended values. */
25277 }
25278 }
25280 }
25282 /* Compute default value for "length_address" attribute. */
25283 int
25285 {
25289 {
25300 }
25305 {
25308 {
25313 constraints++;
25316 ;
25317 /* Skip ignored operands. */
25320 }
25322 }
25324 }
25326 /* Compute default value for "length_vex" attribute. It includes
25327 2 or 3 byte VEX prefix and 1 opcode byte. */
25329 int
25331 {
25334 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25335 byte VEX prefix. */
25339 /* We can always use 2 byte VEX prefix in 32bit. */
25347 {
25348 /* REX.W bit uses 3 byte VEX prefix. */
25352 }
25353 else
25354 {
25355 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25359 }
25362 }
25363 \f
25364 /* Return the maximum number of instructions a cpu can issue. */
25366 static int
25368 {
25370 {
25401 }
25402 }
25404 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25405 by DEP_INSN and nothing set by DEP_INSN. */
25407 static bool
25409 {
25412 /* Simplify the test for uninteresting insns. */
25420 {
25423 }
25428 {
25431 }
25432 else
25438 /* This test is true if the dependent insn reads the flags but
25439 not any other potentially set register. */
25447 }
25449 /* Return true iff USE_INSN has a memory address with operands set by
25450 SET_INSN. */
25452 bool
25454 {
25459 {
25462 }
25464 }
25466 /* Helper function for exact_store_load_dependency.
25467 Return true if addr is found in insn. */
25468 static bool
25470 {
25477 {
25483 CASE_CONST_ANY:
25492 }
25496 {
25498 {
25508 }
25509 }
25511 }
25513 /* Return true if there exists exact dependency for store & load, i.e.
25514 the same memory address is used in them. */
25515 static bool
25517 {
25531 }
25533 static int
25535 {
25541 /* Anti and output dependencies have zero cost on all CPUs. */
25547 /* If we can't recognize the insns, we can't really do anything. */
25555 {
25557 /* Address Generation Interlock adds a cycle of latency. */
25559 {
25570 }
25574 /* ??? Compares pair with jump/setcc. */
25578 /* Floating point stores require value to be ready one cycle earlier. */
25586 /* INT->FP conversion is expensive. */
25590 /* There is one cycle extra latency between an FP op and a store. */
25600 /* Show ability of reorder buffer to hide latency of load by executing
25601 in parallel with previous instruction in case
25602 previous instruction is not needed to compute the address. */
25605 {
25606 /* Claim moves to take one cycle, as core can issue one load
25607 at time and the next load can start cycle later. */
25612 cost--;
25613 }
25617 /* The esp dependency is resolved before
25618 the instruction is really finished. */
25623 /* INT->FP conversion is expensive. */
25629 /* Show ability of reorder buffer to hide latency of load by executing
25630 in parallel with previous instruction in case
25631 previous instruction is not needed to compute the address. */
25634 {
25635 /* Claim moves to take one cycle, as core can issue one load
25636 at time and the next load can start cycle later. */
25642 else
25644 }
25655 /* Stack engine allows to execute push&pop instructions in parall. */
25659 /* FALLTHRU */
25665 /* Show ability of reorder buffer to hide latency of load by executing
25666 in parallel with previous instruction in case
25667 previous instruction is not needed to compute the address. */
25670 {
25674 /* Because of the difference between the length of integer and
25675 floating unit pipeline preparation stages, the memory operands
25676 for floating point are cheaper.
25678 ??? For Athlon it the difference is most probably 2. */
25681 else
25686 else
25688 }
25695 /* Stack engine allows to execute push&pop instructions in parall. */
25702 /* Show ability of reorder buffer to hide latency of load by executing
25703 in parallel with previous instruction in case
25704 previous instruction is not needed to compute the address. */
25707 {
25710 else
25712 }
25720 /* Increase cost of integer loads. */
25723 {
25726 {
25729 else
25730 {
25731 /* Increase cost of ld/st for short int types only
25732 because of store forwarding issue. */
25736 {
25737 /* Increase cost of store/load insn if exact
25738 dependence exists and it is load insn. */
25743 }
25744 }
25745 }
25746 }
25750 }
25753 }
25755 /* How many alternative schedules to try. This should be as wide as the
25756 scheduling freedom in the DFA, but no wider. Making this value too
25757 large results extra work for the scheduler. */
25759 static int
25761 {
25763 {
25775 /* We use lookahead value 4 for BD both before and after reload
25776 schedules. Plan is to have value 8 included for O3. */
25786 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25787 as many instructions can be executed on a cycle, i.e.,
25788 issue_rate. I wonder why tuning for many CPUs does not do this. */
25791 /* Don't use lookahead for pre-reload schedule to save compile time. */
25796 }
25797 }
25799 /* Return true if target platform supports macro-fusion. */
25801 static bool
25803 {
25805 }
25807 /* Check whether current microarchitecture support macro fusion
25808 for insn pair "CONDGEN + CONDJMP". Refer to
25809 "Intel Architectures Optimization Reference Manual". */
25811 static bool
25813 {
25832 else
25833 {
25838 {
25842 else
25844 }
25845 }
25852 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
25853 supported. */
25860 /* No fusion for RIP-relative address. */
25867 ix86_address parts;
25873 }
25878 /* Check whether conditional jump use Sign or Overflow Flags. */
25886 /* Return true for TYPE_TEST and TYPE_ICMP. */
25891 /* The following is the case that macro-fusion for alu + jmp. */
25895 /* No fusion for alu op with memory destination operand. */
25900 /* Macro-fusion for inc/dec + unsigned conditional jump is not
25901 supported. */
25910 }
25912 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
25913 execution. It is applied if
25914 (1) IMUL instruction is on the top of list;
25915 (2) There exists the only producer of independent IMUL instruction in
25916 ready list.
25917 Return index of IMUL producer if it was found and -1 otherwise. */
25918 static int
25920 {
25922 sd_iterator_def sd_it;
25923 dep_t dep;
25930 /* Check that IMUL instruction is on the top of ready list. */
25939 /* Search for producer of independent IMUL instruction. */
25941 {
25945 /* Skip IMUL instruction. */
25955 {
25956 rtx con;
25967 {
25968 sd_iterator_def sd_it1;
25969 dep_t dep1;
25970 /* Check if there is no other dependee for IMUL. */
25973 {
25974 rtx pro;
25980 }
25983 }
25984 }
25987 }
25989 }
25991 /* Try to find the best candidate on the top of ready list if two insns
25992 have the same priority - candidate is best if its dependees were
25993 scheduled earlier. Applied for Silvermont only.
25994 Return true if top 2 insns must be interchanged. */
25995 static bool
25997 {
26000 rtx set;
26001 sd_iterator_def sd_it;
26002 dep_t dep;
26005 #define INSN_TICK(INSN) (HID (INSN)->tick)
26026 {
26029 /* Determine winner more precise. */
26031 {
26032 rtx pro;
26038 }
26040 {
26041 rtx pro;
26047 }
26050 {
26051 /* Determine winner - load must win. */
26057 }
26059 }
26061 #undef INSN_TICK
26062 }
26064 /* Perform possible reodering of ready list for Atom/Silvermont only.
26065 Return issue rate. */
26066 static int
26069 {
26073 rtx insn;
26076 /* Set up issue rate. */
26079 /* Do reodering for BONNELL/SILVERMONT only. */
26083 /* Nothing to do if ready list contains only 1 instruction. */
26087 /* Do reodering for post-reload scheduler only. */
26092 {
26097 /* Put IMUL producer (ready[index]) at the top of ready list. */
26103 }
26105 {
26109 /* Swap 2 top elements of ready list. */
26113 }
26115 }
26117 static bool
26120 /* Returns true if lhs of insn is HW function argument register and set up
26121 is_spilled to true if it is likely spilled HW register. */
26122 static bool
26124 {
26125 rtx dst;
26129 /* Call instructions are not movable, ignore it. */
26140 {
26141 /* Is it likely spilled HW register? */
26146 }
26148 }
26150 /* Add output dependencies for chain of function adjacent arguments if only
26151 there is a move to likely spilled HW register. Return first argument
26152 if at least one dependence was added or NULL otherwise. */
26153 static rtx
26155 {
26156 rtx insn;
26163 /* Find nearest to call argument passing instruction. */
26165 {
26174 }
26178 {
26185 {
26188 }
26190 {
26191 /* Add output depdendence between two function arguments if chain
26192 of output arguments contains likely spilled HW registers. */
26196 }
26197 else
26199 }
26203 }
26205 /* Add output or anti dependency from insn to first_arg to restrict its code
26206 motion. */
26207 static void
26209 {
26210 rtx set;
26211 rtx tmp;
26218 {
26219 /* Add output dependency to the first function argument. */
26222 }
26223 /* Add anti dependency. */
26225 }
26227 /* Avoid cross block motion of function argument through adding dependency
26228 from the first non-jump instruction in bb. */
26229 static void
26231 {
26235 {
26237 {
26240 {
26243 }
26244 }
26248 }
26249 }
26251 /* Hook for pre-reload schedule - avoid motion of function arguments
26252 passed in likely spilled HW registers. */
26253 static void
26255 {
26256 rtx insn;
26264 {
26267 {
26268 /* Add dependee for first argument to predecessors if only
26269 region contains more than one block. */
26273 /* Skip trivial regions and region head blocks that can have
26274 predecessors outside of region. */
26276 {
26277 edge e;
26278 edge_iterator ei;
26280 /* Regions are SCCs with the exception of selective
26281 scheduling with pipelining of outer blocks enabled.
26282 So also check that immediate predecessors of a non-head
26283 block are in the same region. */
26285 {
26286 /* Avoid creating of loop-carried dependencies through
26287 using topological ordering in the region. */
26291 }
26292 }
26296 }
26297 }
26300 }
26302 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26303 HW registers to maximum, to schedule them at soon as possible. These are
26304 moves from function argument registers at the top of the function entry
26305 and moves from function return value registers after call. */
26306 static int
26308 {
26309 rtx set;
26319 {
26326 }
26329 }
26331 /* Model decoder of Core 2/i7.
26332 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26333 track the instruction fetch block boundaries and make sure that long
26334 (9+ bytes) instructions are assigned to D0. */
26336 /* Maximum length of an insn that can be handled by
26337 a secondary decoder unit. '8' for Core 2/i7. */
26340 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26341 '16' for Core 2/i7. */
26344 /* Maximum number of instructions decoder can handle per cycle.
26345 '6' for Core 2/i7. */
26349 ix86_first_cycle_multipass_data_t;
26351 const_ix86_first_cycle_multipass_data_t;
26353 /* A variable to store target state across calls to max_issue within
26354 one cycle. */
26358 /* Initialize DATA. */
26359 static void
26361 {
26362 ix86_first_cycle_multipass_data_t data
26369 }
26371 /* Advancing the cycle; reset ifetch block counts. */
26372 static void
26374 {
26381 }
26385 /* Filter out insns from ready_try that the core will not be able to issue
26386 on current cycle due to decoder. */
26387 static void
26388 core2i7_first_cycle_multipass_filter_ready_try
26391 {
26393 {
26394 rtx insn;
26404 (!first_cycle_insn_p
26406 /* ... or it would not fit into the ifetch block ... */
26408 /* ... or the decoder is full already ... */
26410 /* ... mask the insn out. */
26411 {
26416 }
26417 }
26418 }
26420 /* Prepare for a new round of multipass lookahead scheduling. */
26421 static void
26425 {
26426 ix86_first_cycle_multipass_data_t data
26428 const_ix86_first_cycle_multipass_data_t prev_data
26431 /* Restore the state from the end of the previous round. */
26435 /* Filter instructions that cannot be issued on current cycle due to
26436 decoder restrictions. */
26438 first_cycle_insn_p);
26439 }
26441 /* INSN is being issued in current solution. Account for its impact on
26442 the decoder model. */
26443 static void
26447 {
26448 ix86_first_cycle_multipass_data_t data
26450 const_ix86_first_cycle_multipass_data_t prev_data
26460 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26462 {
26465 }
26467 {
26471 }
26474 /* Filter out insns from ready_try that the core will not be able to issue
26475 on current cycle due to decoder. */
26478 }
26480 /* Revert the effect on ready_try. */
26481 static void
26485 {
26486 const_ix86_first_cycle_multipass_data_t data
26489 sbitmap_iterator sbi;
26493 {
26495 }
26496 }
26498 /* Save the result of multipass lookahead scheduling for the next round. */
26499 static void
26501 {
26502 const_ix86_first_cycle_multipass_data_t data
26504 ix86_first_cycle_multipass_data_t next_data
26508 {
26511 }
26512 }
26514 /* Deallocate target data. */
26515 static void
26517 {
26518 ix86_first_cycle_multipass_data_t data
26522 {
26526 }
26527 }
26529 /* Prepare for scheduling pass. */
26530 static void
26534 {
26535 /* Install scheduling hooks for current CPU. Some of these hooks are used
26536 in time-critical parts of the scheduler, so we only set them up when
26537 they are actually used. */
26539 {
26544 /* Do not perform multipass scheduling for pre-reload schedule
26545 to save compile time. */
26547 {
26563 /* Set decoder parameters. */
26568 }
26569 /* ... Fall through ... */
26579 }
26580 }
26582 \f
26583 /* Compute the alignment given to a constant that is being placed in memory.
26584 EXP is the constant and ALIGN is the alignment that the object would
26585 ordinarily have.
26586 The value of this function is used instead of that alignment to align
26587 the object. */
26589 int
26591 {
26594 {
26599 }
26605 }
26607 /* Compute the alignment for a static variable.
26608 TYPE is the data type, and ALIGN is the alignment that
26609 the object would ordinarily have. The value of this function is used
26610 instead of that alignment to align the object. */
26612 int
26614 {
26615 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26616 for symbols from other compilation units or symbols that don't need
26617 to bind locally. In order to preserve some ABI compatibility with
26618 those compilers, ensure we don't decrease alignment from what we
26619 used to assume. */
26621 int max_align_compat
26624 /* A data structure, equal or greater than the size of a cache line
26625 (64 bytes in the Pentium 4 and other recent Intel processors, including
26626 processors based on Intel Core microarchitecture) should be aligned
26627 so that its base address is a multiple of a cache line size. */
26629 int max_align
26639 {
26646 }
26648 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26649 to 16byte boundary. */
26651 {
26658 }
26664 {
26669 }
26671 {
26678 }
26683 {
26688 }
26691 {
26696 }
26699 }
26701 /* Compute the alignment for a local variable or a stack slot. EXP is
26702 the data type or decl itself, MODE is the widest mode available and
26703 ALIGN is the alignment that the object would ordinarily have. The
26704 value of this macro is used instead of that alignment to align the
26705 object. */
26707 unsigned int
26710 {
26714 {
26717 }
26718 else
26719 {
26722 }
26724 /* Don't do dynamic stack realignment for long long objects with
26725 -mpreferred-stack-boundary=2. */
26734 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26735 register in MODE. We will return the largest alignment of XF
26736 and DF. */
26738 {
26742 }
26744 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26745 to 16byte boundary. Exact wording is:
26747 An array uses the same alignment as its elements, except that a local or
26748 global array variable of length at least 16 bytes or
26749 a C99 variable-length array variable always has alignment of at least 16 bytes.
26751 This was added to allow use of aligned SSE instructions at arrays. This
26752 rule is meant for static storage (where compiler can not do the analysis
26753 by itself). We follow it for automatic variables only when convenient.
26754 We fully control everything in the function compiled and functions from
26755 other unit can not rely on the alignment.
26757 Exclude va_list type. It is the common case of local array where
26758 we can not benefit from the alignment.
26760 TODO: Probably one should optimize for size only when var is not escaping. */
26763 {
26773 }
26775 {
26780 }
26782 {
26788 }
26793 {
26798 }
26801 {
26807 }
26809 }
26811 /* Compute the minimum required alignment for dynamic stack realignment
26812 purposes for a local variable, parameter or a stack slot. EXP is
26813 the data type or decl itself, MODE is its mode and ALIGN is the
26814 alignment that the object would ordinarily have. */
26816 unsigned int
26819 {
26823 {
26826 }
26827 else
26828 {
26831 }
26836 /* Don't do dynamic stack realignment for long long objects with
26837 -mpreferred-stack-boundary=2. */
26844 }
26845 \f
26846 /* Find a location for the static chain incoming to a nested function.
26847 This is a register, unless all free registers are used by arguments. */
26849 static rtx
26851 {
26858 {
26859 /* We always use R10 in 64-bit mode. */
26861 }
26862 else
26863 {
26864 tree fntype;
26867 /* By default in 32-bit mode we use ECX to pass the static chain. */
26873 {
26874 /* Fastcall functions use ecx/edx for arguments, which leaves
26875 us with EAX for the static chain.
26876 Thiscall functions use ecx for arguments, which also
26877 leaves us with EAX for the static chain. */
26879 }
26881 {
26882 /* Thiscall functions use ecx for arguments, which leaves
26883 us with EAX and EDX for the static chain.
26884 We are using for abi-compatibility EAX. */
26886 }
26888 {
26889 /* For regparm 3, we have no free call-clobbered registers in
26890 which to store the static chain. In order to implement this,
26891 we have the trampoline push the static chain to the stack.
26892 However, we can't push a value below the return address when
26893 we call the nested function directly, so we have to use an
26894 alternate entry point. For this we use ESI, and have the
26895 alternate entry point push ESI, so that things appear the
26896 same once we're executing the nested function. */
26898 {
26904 }
26906 }
26907 }
26910 }
26912 /* Emit RTL insns to initialize the variable parts of a trampoline.
26913 FNDECL is the decl of the target address; M_TRAMP is a MEM for
26914 the trampoline, and CHAIN_VALUE is an RTX for the static chain
26915 to be passed to the target function. */
26917 static void
26919 {
26927 {
26930 /* Load the function address to r11. Try to load address using
26931 the shorter movl instead of movabs. We may want to support
26932 movq for kernel mode, but kernel does not use trampolines at
26933 the moment. FNADDR is a 32bit address and may not be in
26934 DImode when ptr_mode == SImode. Always use movl in this
26935 case. */
26938 {
26947 }
26948 else
26949 {
26956 }
26958 /* Load static chain using movabs to r10. Use the shorter movl
26959 instead of movabs when ptr_mode == SImode. */
26961 {
26964 }
26965 else
26966 {
26969 }
26978 /* Jump to r11; the last (unused) byte is a nop, only there to
26979 pad the write out to a single 32-bit store. */
26983 }
26984 else
26985 {
26988 /* Depending on the static chain location, either load a register
26989 with a constant, or push the constant to the stack. All of the
26990 instructions are the same size. */
26993 {
26995 {
27002 }
27003 }
27004 else
27019 /* Compute offset from the end of the jmp to the target function.
27020 In the case in which the trampoline stores the static chain on
27021 the stack, we need to skip the first insn which pushes the
27022 (call-saved) register static chain; this push is 1 byte. */
27029 }
27033 #ifdef HAVE_ENABLE_EXECUTE_STACK
27034 #ifdef CHECK_EXECUTE_STACK_ENABLED
27036 #endif
27039 #endif
27040 }
27041 \f
27042 /* The following file contains several enumerations and data structures
27043 built from the definitions in i386-builtin-types.def. */
27047 /* Table for the ix86 builtin non-function types. */
27050 /* Retrieve an element from the above table, building some of
27051 the types lazily. */
27053 static tree
27055 {
27067 {
27075 }
27076 else
27077 {
27083 else
27091 }
27095 }
27097 /* Table for the ix86 builtin function types. */
27100 /* Retrieve an element from the above table, building some of
27101 the types lazily. */
27103 static tree
27105 {
27106 tree type;
27115 {
27123 {
27126 }
27129 }
27130 else
27131 {
27137 }
27141 }
27144 /* Codes for all the SSE/MMX builtins. */
27145 enum ix86_builtins
27146 {
27147 IX86_BUILTIN_ADDPS,
27148 IX86_BUILTIN_ADDSS,
27149 IX86_BUILTIN_DIVPS,
27150 IX86_BUILTIN_DIVSS,
27151 IX86_BUILTIN_MULPS,
27152 IX86_BUILTIN_MULSS,
27153 IX86_BUILTIN_SUBPS,
27154 IX86_BUILTIN_SUBSS,
27156 IX86_BUILTIN_CMPEQPS,
27157 IX86_BUILTIN_CMPLTPS,
27158 IX86_BUILTIN_CMPLEPS,
27159 IX86_BUILTIN_CMPGTPS,
27160 IX86_BUILTIN_CMPGEPS,
27161 IX86_BUILTIN_CMPNEQPS,
27162 IX86_BUILTIN_CMPNLTPS,
27163 IX86_BUILTIN_CMPNLEPS,
27164 IX86_BUILTIN_CMPNGTPS,
27165 IX86_BUILTIN_CMPNGEPS,
27166 IX86_BUILTIN_CMPORDPS,
27167 IX86_BUILTIN_CMPUNORDPS,
27168 IX86_BUILTIN_CMPEQSS,
27169 IX86_BUILTIN_CMPLTSS,
27170 IX86_BUILTIN_CMPLESS,
27171 IX86_BUILTIN_CMPNEQSS,
27172 IX86_BUILTIN_CMPNLTSS,
27173 IX86_BUILTIN_CMPNLESS,
27174 IX86_BUILTIN_CMPORDSS,
27175 IX86_BUILTIN_CMPUNORDSS,
27177 IX86_BUILTIN_COMIEQSS,
27178 IX86_BUILTIN_COMILTSS,
27179 IX86_BUILTIN_COMILESS,
27180 IX86_BUILTIN_COMIGTSS,
27181 IX86_BUILTIN_COMIGESS,
27182 IX86_BUILTIN_COMINEQSS,
27183 IX86_BUILTIN_UCOMIEQSS,
27184 IX86_BUILTIN_UCOMILTSS,
27185 IX86_BUILTIN_UCOMILESS,
27186 IX86_BUILTIN_UCOMIGTSS,
27187 IX86_BUILTIN_UCOMIGESS,
27188 IX86_BUILTIN_UCOMINEQSS,
27190 IX86_BUILTIN_CVTPI2PS,
27191 IX86_BUILTIN_CVTPS2PI,
27192 IX86_BUILTIN_CVTSI2SS,
27193 IX86_BUILTIN_CVTSI642SS,
27194 IX86_BUILTIN_CVTSS2SI,
27195 IX86_BUILTIN_CVTSS2SI64,
27196 IX86_BUILTIN_CVTTPS2PI,
27197 IX86_BUILTIN_CVTTSS2SI,
27198 IX86_BUILTIN_CVTTSS2SI64,
27200 IX86_BUILTIN_MAXPS,
27201 IX86_BUILTIN_MAXSS,
27202 IX86_BUILTIN_MINPS,
27203 IX86_BUILTIN_MINSS,
27205 IX86_BUILTIN_LOADUPS,
27206 IX86_BUILTIN_STOREUPS,
27207 IX86_BUILTIN_MOVSS,
27209 IX86_BUILTIN_MOVHLPS,
27210 IX86_BUILTIN_MOVLHPS,
27211 IX86_BUILTIN_LOADHPS,
27212 IX86_BUILTIN_LOADLPS,
27213 IX86_BUILTIN_STOREHPS,
27214 IX86_BUILTIN_STORELPS,
27216 IX86_BUILTIN_MASKMOVQ,
27217 IX86_BUILTIN_MOVMSKPS,
27218 IX86_BUILTIN_PMOVMSKB,
27220 IX86_BUILTIN_MOVNTPS,
27221 IX86_BUILTIN_MOVNTQ,
27223 IX86_BUILTIN_LOADDQU,
27224 IX86_BUILTIN_STOREDQU,
27226 IX86_BUILTIN_PACKSSWB,
27227 IX86_BUILTIN_PACKSSDW,
27228 IX86_BUILTIN_PACKUSWB,
27230 IX86_BUILTIN_PADDB,
27231 IX86_BUILTIN_PADDW,
27232 IX86_BUILTIN_PADDD,
27233 IX86_BUILTIN_PADDQ,
27234 IX86_BUILTIN_PADDSB,
27235 IX86_BUILTIN_PADDSW,
27236 IX86_BUILTIN_PADDUSB,
27237 IX86_BUILTIN_PADDUSW,
27238 IX86_BUILTIN_PSUBB,
27239 IX86_BUILTIN_PSUBW,
27240 IX86_BUILTIN_PSUBD,
27241 IX86_BUILTIN_PSUBQ,
27242 IX86_BUILTIN_PSUBSB,
27243 IX86_BUILTIN_PSUBSW,
27244 IX86_BUILTIN_PSUBUSB,
27245 IX86_BUILTIN_PSUBUSW,
27247 IX86_BUILTIN_PAND,
27248 IX86_BUILTIN_PANDN,
27249 IX86_BUILTIN_POR,
27250 IX86_BUILTIN_PXOR,
27252 IX86_BUILTIN_PAVGB,
27253 IX86_BUILTIN_PAVGW,
27255 IX86_BUILTIN_PCMPEQB,
27256 IX86_BUILTIN_PCMPEQW,
27257 IX86_BUILTIN_PCMPEQD,
27258 IX86_BUILTIN_PCMPGTB,
27259 IX86_BUILTIN_PCMPGTW,
27260 IX86_BUILTIN_PCMPGTD,
27262 IX86_BUILTIN_PMADDWD,
27264 IX86_BUILTIN_PMAXSW,
27265 IX86_BUILTIN_PMAXUB,
27266 IX86_BUILTIN_PMINSW,
27267 IX86_BUILTIN_PMINUB,
27269 IX86_BUILTIN_PMULHUW,
27270 IX86_BUILTIN_PMULHW,
27271 IX86_BUILTIN_PMULLW,
27273 IX86_BUILTIN_PSADBW,
27274 IX86_BUILTIN_PSHUFW,
27276 IX86_BUILTIN_PSLLW,
27277 IX86_BUILTIN_PSLLD,
27278 IX86_BUILTIN_PSLLQ,
27279 IX86_BUILTIN_PSRAW,
27280 IX86_BUILTIN_PSRAD,
27281 IX86_BUILTIN_PSRLW,
27282 IX86_BUILTIN_PSRLD,
27283 IX86_BUILTIN_PSRLQ,
27284 IX86_BUILTIN_PSLLWI,
27285 IX86_BUILTIN_PSLLDI,
27286 IX86_BUILTIN_PSLLQI,
27287 IX86_BUILTIN_PSRAWI,
27288 IX86_BUILTIN_PSRADI,
27289 IX86_BUILTIN_PSRLWI,
27290 IX86_BUILTIN_PSRLDI,
27291 IX86_BUILTIN_PSRLQI,
27293 IX86_BUILTIN_PUNPCKHBW,
27294 IX86_BUILTIN_PUNPCKHWD,
27295 IX86_BUILTIN_PUNPCKHDQ,
27296 IX86_BUILTIN_PUNPCKLBW,
27297 IX86_BUILTIN_PUNPCKLWD,
27298 IX86_BUILTIN_PUNPCKLDQ,
27300 IX86_BUILTIN_SHUFPS,
27302 IX86_BUILTIN_RCPPS,
27303 IX86_BUILTIN_RCPSS,
27304 IX86_BUILTIN_RSQRTPS,
27305 IX86_BUILTIN_RSQRTPS_NR,
27306 IX86_BUILTIN_RSQRTSS,
27307 IX86_BUILTIN_RSQRTF,
27308 IX86_BUILTIN_SQRTPS,
27309 IX86_BUILTIN_SQRTPS_NR,
27310 IX86_BUILTIN_SQRTSS,
27312 IX86_BUILTIN_UNPCKHPS,
27313 IX86_BUILTIN_UNPCKLPS,
27315 IX86_BUILTIN_ANDPS,
27316 IX86_BUILTIN_ANDNPS,
27317 IX86_BUILTIN_ORPS,
27318 IX86_BUILTIN_XORPS,
27320 IX86_BUILTIN_EMMS,
27321 IX86_BUILTIN_LDMXCSR,
27322 IX86_BUILTIN_STMXCSR,
27323 IX86_BUILTIN_SFENCE,
27325 IX86_BUILTIN_FXSAVE,
27326 IX86_BUILTIN_FXRSTOR,
27327 IX86_BUILTIN_FXSAVE64,
27328 IX86_BUILTIN_FXRSTOR64,
27330 IX86_BUILTIN_XSAVE,
27331 IX86_BUILTIN_XRSTOR,
27332 IX86_BUILTIN_XSAVE64,
27333 IX86_BUILTIN_XRSTOR64,
27335 IX86_BUILTIN_XSAVEOPT,
27336 IX86_BUILTIN_XSAVEOPT64,
27338 IX86_BUILTIN_XSAVEC,
27339 IX86_BUILTIN_XSAVEC64,
27341 IX86_BUILTIN_XSAVES,
27342 IX86_BUILTIN_XRSTORS,
27343 IX86_BUILTIN_XSAVES64,
27344 IX86_BUILTIN_XRSTORS64,
27346 /* 3DNow! Original */
27347 IX86_BUILTIN_FEMMS,
27348 IX86_BUILTIN_PAVGUSB,
27349 IX86_BUILTIN_PF2ID,
27350 IX86_BUILTIN_PFACC,
27351 IX86_BUILTIN_PFADD,
27352 IX86_BUILTIN_PFCMPEQ,
27353 IX86_BUILTIN_PFCMPGE,
27354 IX86_BUILTIN_PFCMPGT,
27355 IX86_BUILTIN_PFMAX,
27356 IX86_BUILTIN_PFMIN,
27357 IX86_BUILTIN_PFMUL,
27358 IX86_BUILTIN_PFRCP,
27359 IX86_BUILTIN_PFRCPIT1,
27360 IX86_BUILTIN_PFRCPIT2,
27361 IX86_BUILTIN_PFRSQIT1,
27362 IX86_BUILTIN_PFRSQRT,
27363 IX86_BUILTIN_PFSUB,
27364 IX86_BUILTIN_PFSUBR,
27365 IX86_BUILTIN_PI2FD,
27366 IX86_BUILTIN_PMULHRW,
27368 /* 3DNow! Athlon Extensions */
27369 IX86_BUILTIN_PF2IW,
27370 IX86_BUILTIN_PFNACC,
27371 IX86_BUILTIN_PFPNACC,
27372 IX86_BUILTIN_PI2FW,
27373 IX86_BUILTIN_PSWAPDSI,
27374 IX86_BUILTIN_PSWAPDSF,
27376 /* SSE2 */
27377 IX86_BUILTIN_ADDPD,
27378 IX86_BUILTIN_ADDSD,
27379 IX86_BUILTIN_DIVPD,
27380 IX86_BUILTIN_DIVSD,
27381 IX86_BUILTIN_MULPD,
27382 IX86_BUILTIN_MULSD,
27383 IX86_BUILTIN_SUBPD,
27384 IX86_BUILTIN_SUBSD,
27386 IX86_BUILTIN_CMPEQPD,
27387 IX86_BUILTIN_CMPLTPD,
27388 IX86_BUILTIN_CMPLEPD,
27389 IX86_BUILTIN_CMPGTPD,
27390 IX86_BUILTIN_CMPGEPD,
27391 IX86_BUILTIN_CMPNEQPD,
27392 IX86_BUILTIN_CMPNLTPD,
27393 IX86_BUILTIN_CMPNLEPD,
27394 IX86_BUILTIN_CMPNGTPD,
27395 IX86_BUILTIN_CMPNGEPD,
27396 IX86_BUILTIN_CMPORDPD,
27397 IX86_BUILTIN_CMPUNORDPD,
27398 IX86_BUILTIN_CMPEQSD,
27399 IX86_BUILTIN_CMPLTSD,
27400 IX86_BUILTIN_CMPLESD,
27401 IX86_BUILTIN_CMPNEQSD,
27402 IX86_BUILTIN_CMPNLTSD,
27403 IX86_BUILTIN_CMPNLESD,
27404 IX86_BUILTIN_CMPORDSD,
27405 IX86_BUILTIN_CMPUNORDSD,
27407 IX86_BUILTIN_COMIEQSD,
27408 IX86_BUILTIN_COMILTSD,
27409 IX86_BUILTIN_COMILESD,
27410 IX86_BUILTIN_COMIGTSD,
27411 IX86_BUILTIN_COMIGESD,
27412 IX86_BUILTIN_COMINEQSD,
27413 IX86_BUILTIN_UCOMIEQSD,
27414 IX86_BUILTIN_UCOMILTSD,
27415 IX86_BUILTIN_UCOMILESD,
27416 IX86_BUILTIN_UCOMIGTSD,
27417 IX86_BUILTIN_UCOMIGESD,
27418 IX86_BUILTIN_UCOMINEQSD,
27420 IX86_BUILTIN_MAXPD,
27421 IX86_BUILTIN_MAXSD,
27422 IX86_BUILTIN_MINPD,
27423 IX86_BUILTIN_MINSD,
27425 IX86_BUILTIN_ANDPD,
27426 IX86_BUILTIN_ANDNPD,
27427 IX86_BUILTIN_ORPD,
27428 IX86_BUILTIN_XORPD,
27430 IX86_BUILTIN_SQRTPD,
27431 IX86_BUILTIN_SQRTSD,
27433 IX86_BUILTIN_UNPCKHPD,
27434 IX86_BUILTIN_UNPCKLPD,
27436 IX86_BUILTIN_SHUFPD,
27438 IX86_BUILTIN_LOADUPD,
27439 IX86_BUILTIN_STOREUPD,
27440 IX86_BUILTIN_MOVSD,
27442 IX86_BUILTIN_LOADHPD,
27443 IX86_BUILTIN_LOADLPD,
27445 IX86_BUILTIN_CVTDQ2PD,
27446 IX86_BUILTIN_CVTDQ2PS,
27448 IX86_BUILTIN_CVTPD2DQ,
27449 IX86_BUILTIN_CVTPD2PI,
27450 IX86_BUILTIN_CVTPD2PS,
27451 IX86_BUILTIN_CVTTPD2DQ,
27452 IX86_BUILTIN_CVTTPD2PI,
27454 IX86_BUILTIN_CVTPI2PD,
27455 IX86_BUILTIN_CVTSI2SD,
27456 IX86_BUILTIN_CVTSI642SD,
27458 IX86_BUILTIN_CVTSD2SI,
27459 IX86_BUILTIN_CVTSD2SI64,
27460 IX86_BUILTIN_CVTSD2SS,
27461 IX86_BUILTIN_CVTSS2SD,
27462 IX86_BUILTIN_CVTTSD2SI,
27463 IX86_BUILTIN_CVTTSD2SI64,
27465 IX86_BUILTIN_CVTPS2DQ,
27466 IX86_BUILTIN_CVTPS2PD,
27467 IX86_BUILTIN_CVTTPS2DQ,
27469 IX86_BUILTIN_MOVNTI,
27470 IX86_BUILTIN_MOVNTI64,
27471 IX86_BUILTIN_MOVNTPD,
27472 IX86_BUILTIN_MOVNTDQ,
27474 IX86_BUILTIN_MOVQ128,
27476 /* SSE2 MMX */
27477 IX86_BUILTIN_MASKMOVDQU,
27478 IX86_BUILTIN_MOVMSKPD,
27479 IX86_BUILTIN_PMOVMSKB128,
27481 IX86_BUILTIN_PACKSSWB128,
27482 IX86_BUILTIN_PACKSSDW128,
27483 IX86_BUILTIN_PACKUSWB128,
27485 IX86_BUILTIN_PADDB128,
27486 IX86_BUILTIN_PADDW128,
27487 IX86_BUILTIN_PADDD128,
27488 IX86_BUILTIN_PADDQ128,
27489 IX86_BUILTIN_PADDSB128,
27490 IX86_BUILTIN_PADDSW128,
27491 IX86_BUILTIN_PADDUSB128,
27492 IX86_BUILTIN_PADDUSW128,
27493 IX86_BUILTIN_PSUBB128,
27494 IX86_BUILTIN_PSUBW128,
27495 IX86_BUILTIN_PSUBD128,
27496 IX86_BUILTIN_PSUBQ128,
27497 IX86_BUILTIN_PSUBSB128,
27498 IX86_BUILTIN_PSUBSW128,
27499 IX86_BUILTIN_PSUBUSB128,
27500 IX86_BUILTIN_PSUBUSW128,
27502 IX86_BUILTIN_PAND128,
27503 IX86_BUILTIN_PANDN128,
27504 IX86_BUILTIN_POR128,
27505 IX86_BUILTIN_PXOR128,
27507 IX86_BUILTIN_PAVGB128,
27508 IX86_BUILTIN_PAVGW128,
27510 IX86_BUILTIN_PCMPEQB128,
27511 IX86_BUILTIN_PCMPEQW128,
27512 IX86_BUILTIN_PCMPEQD128,
27513 IX86_BUILTIN_PCMPGTB128,
27514 IX86_BUILTIN_PCMPGTW128,
27515 IX86_BUILTIN_PCMPGTD128,
27517 IX86_BUILTIN_PMADDWD128,
27519 IX86_BUILTIN_PMAXSW128,
27520 IX86_BUILTIN_PMAXUB128,
27521 IX86_BUILTIN_PMINSW128,
27522 IX86_BUILTIN_PMINUB128,
27524 IX86_BUILTIN_PMULUDQ,
27525 IX86_BUILTIN_PMULUDQ128,
27526 IX86_BUILTIN_PMULHUW128,
27527 IX86_BUILTIN_PMULHW128,
27528 IX86_BUILTIN_PMULLW128,
27530 IX86_BUILTIN_PSADBW128,
27531 IX86_BUILTIN_PSHUFHW,
27532 IX86_BUILTIN_PSHUFLW,
27533 IX86_BUILTIN_PSHUFD,
27535 IX86_BUILTIN_PSLLDQI128,
27536 IX86_BUILTIN_PSLLWI128,
27537 IX86_BUILTIN_PSLLDI128,
27538 IX86_BUILTIN_PSLLQI128,
27539 IX86_BUILTIN_PSRAWI128,
27540 IX86_BUILTIN_PSRADI128,
27541 IX86_BUILTIN_PSRLDQI128,
27542 IX86_BUILTIN_PSRLWI128,
27543 IX86_BUILTIN_PSRLDI128,
27544 IX86_BUILTIN_PSRLQI128,
27546 IX86_BUILTIN_PSLLDQ128,
27547 IX86_BUILTIN_PSLLW128,
27548 IX86_BUILTIN_PSLLD128,
27549 IX86_BUILTIN_PSLLQ128,
27550 IX86_BUILTIN_PSRAW128,
27551 IX86_BUILTIN_PSRAD128,
27552 IX86_BUILTIN_PSRLW128,
27553 IX86_BUILTIN_PSRLD128,
27554 IX86_BUILTIN_PSRLQ128,
27556 IX86_BUILTIN_PUNPCKHBW128,
27557 IX86_BUILTIN_PUNPCKHWD128,
27558 IX86_BUILTIN_PUNPCKHDQ128,
27559 IX86_BUILTIN_PUNPCKHQDQ128,
27560 IX86_BUILTIN_PUNPCKLBW128,
27561 IX86_BUILTIN_PUNPCKLWD128,
27562 IX86_BUILTIN_PUNPCKLDQ128,
27563 IX86_BUILTIN_PUNPCKLQDQ128,
27565 IX86_BUILTIN_CLFLUSH,
27566 IX86_BUILTIN_MFENCE,
27567 IX86_BUILTIN_LFENCE,
27568 IX86_BUILTIN_PAUSE,
27570 IX86_BUILTIN_FNSTENV,
27571 IX86_BUILTIN_FLDENV,
27572 IX86_BUILTIN_FNSTSW,
27573 IX86_BUILTIN_FNCLEX,
27575 IX86_BUILTIN_BSRSI,
27576 IX86_BUILTIN_BSRDI,
27577 IX86_BUILTIN_RDPMC,
27578 IX86_BUILTIN_RDTSC,
27579 IX86_BUILTIN_RDTSCP,
27580 IX86_BUILTIN_ROLQI,
27581 IX86_BUILTIN_ROLHI,
27582 IX86_BUILTIN_RORQI,
27583 IX86_BUILTIN_RORHI,
27585 /* SSE3. */
27586 IX86_BUILTIN_ADDSUBPS,
27587 IX86_BUILTIN_HADDPS,
27588 IX86_BUILTIN_HSUBPS,
27589 IX86_BUILTIN_MOVSHDUP,
27590 IX86_BUILTIN_MOVSLDUP,
27591 IX86_BUILTIN_ADDSUBPD,
27592 IX86_BUILTIN_HADDPD,
27593 IX86_BUILTIN_HSUBPD,
27594 IX86_BUILTIN_LDDQU,
27596 IX86_BUILTIN_MONITOR,
27597 IX86_BUILTIN_MWAIT,
27599 /* SSSE3. */
27600 IX86_BUILTIN_PHADDW,
27601 IX86_BUILTIN_PHADDD,
27602 IX86_BUILTIN_PHADDSW,
27603 IX86_BUILTIN_PHSUBW,
27604 IX86_BUILTIN_PHSUBD,
27605 IX86_BUILTIN_PHSUBSW,
27606 IX86_BUILTIN_PMADDUBSW,
27607 IX86_BUILTIN_PMULHRSW,
27608 IX86_BUILTIN_PSHUFB,
27609 IX86_BUILTIN_PSIGNB,
27610 IX86_BUILTIN_PSIGNW,
27611 IX86_BUILTIN_PSIGND,
27612 IX86_BUILTIN_PALIGNR,
27613 IX86_BUILTIN_PABSB,
27614 IX86_BUILTIN_PABSW,
27615 IX86_BUILTIN_PABSD,
27617 IX86_BUILTIN_PHADDW128,
27618 IX86_BUILTIN_PHADDD128,
27619 IX86_BUILTIN_PHADDSW128,
27620 IX86_BUILTIN_PHSUBW128,
27621 IX86_BUILTIN_PHSUBD128,
27622 IX86_BUILTIN_PHSUBSW128,
27623 IX86_BUILTIN_PMADDUBSW128,
27624 IX86_BUILTIN_PMULHRSW128,
27625 IX86_BUILTIN_PSHUFB128,
27626 IX86_BUILTIN_PSIGNB128,
27627 IX86_BUILTIN_PSIGNW128,
27628 IX86_BUILTIN_PSIGND128,
27629 IX86_BUILTIN_PALIGNR128,
27630 IX86_BUILTIN_PABSB128,
27631 IX86_BUILTIN_PABSW128,
27632 IX86_BUILTIN_PABSD128,
27634 /* AMDFAM10 - SSE4A New Instructions. */
27635 IX86_BUILTIN_MOVNTSD,
27636 IX86_BUILTIN_MOVNTSS,
27637 IX86_BUILTIN_EXTRQI,
27638 IX86_BUILTIN_EXTRQ,
27639 IX86_BUILTIN_INSERTQI,
27640 IX86_BUILTIN_INSERTQ,
27642 /* SSE4.1. */
27643 IX86_BUILTIN_BLENDPD,
27644 IX86_BUILTIN_BLENDPS,
27645 IX86_BUILTIN_BLENDVPD,
27646 IX86_BUILTIN_BLENDVPS,
27647 IX86_BUILTIN_PBLENDVB128,
27648 IX86_BUILTIN_PBLENDW128,
27650 IX86_BUILTIN_DPPD,
27651 IX86_BUILTIN_DPPS,
27653 IX86_BUILTIN_INSERTPS128,
27655 IX86_BUILTIN_MOVNTDQA,
27656 IX86_BUILTIN_MPSADBW128,
27657 IX86_BUILTIN_PACKUSDW128,
27658 IX86_BUILTIN_PCMPEQQ,
27659 IX86_BUILTIN_PHMINPOSUW128,
27661 IX86_BUILTIN_PMAXSB128,
27662 IX86_BUILTIN_PMAXSD128,
27663 IX86_BUILTIN_PMAXUD128,
27664 IX86_BUILTIN_PMAXUW128,
27666 IX86_BUILTIN_PMINSB128,
27667 IX86_BUILTIN_PMINSD128,
27668 IX86_BUILTIN_PMINUD128,
27669 IX86_BUILTIN_PMINUW128,
27671 IX86_BUILTIN_PMOVSXBW128,
27672 IX86_BUILTIN_PMOVSXBD128,
27673 IX86_BUILTIN_PMOVSXBQ128,
27674 IX86_BUILTIN_PMOVSXWD128,
27675 IX86_BUILTIN_PMOVSXWQ128,
27676 IX86_BUILTIN_PMOVSXDQ128,
27678 IX86_BUILTIN_PMOVZXBW128,
27679 IX86_BUILTIN_PMOVZXBD128,
27680 IX86_BUILTIN_PMOVZXBQ128,
27681 IX86_BUILTIN_PMOVZXWD128,
27682 IX86_BUILTIN_PMOVZXWQ128,
27683 IX86_BUILTIN_PMOVZXDQ128,
27685 IX86_BUILTIN_PMULDQ128,
27686 IX86_BUILTIN_PMULLD128,
27688 IX86_BUILTIN_ROUNDSD,
27689 IX86_BUILTIN_ROUNDSS,
27691 IX86_BUILTIN_ROUNDPD,
27692 IX86_BUILTIN_ROUNDPS,
27694 IX86_BUILTIN_FLOORPD,
27695 IX86_BUILTIN_CEILPD,
27696 IX86_BUILTIN_TRUNCPD,
27697 IX86_BUILTIN_RINTPD,
27698 IX86_BUILTIN_ROUNDPD_AZ,
27700 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27701 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27702 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27704 IX86_BUILTIN_FLOORPS,
27705 IX86_BUILTIN_CEILPS,
27706 IX86_BUILTIN_TRUNCPS,
27707 IX86_BUILTIN_RINTPS,
27708 IX86_BUILTIN_ROUNDPS_AZ,
27710 IX86_BUILTIN_FLOORPS_SFIX,
27711 IX86_BUILTIN_CEILPS_SFIX,
27712 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27714 IX86_BUILTIN_PTESTZ,
27715 IX86_BUILTIN_PTESTC,
27716 IX86_BUILTIN_PTESTNZC,
27718 IX86_BUILTIN_VEC_INIT_V2SI,
27719 IX86_BUILTIN_VEC_INIT_V4HI,
27720 IX86_BUILTIN_VEC_INIT_V8QI,
27721 IX86_BUILTIN_VEC_EXT_V2DF,
27722 IX86_BUILTIN_VEC_EXT_V2DI,
27723 IX86_BUILTIN_VEC_EXT_V4SF,
27724 IX86_BUILTIN_VEC_EXT_V4SI,
27725 IX86_BUILTIN_VEC_EXT_V8HI,
27726 IX86_BUILTIN_VEC_EXT_V2SI,
27727 IX86_BUILTIN_VEC_EXT_V4HI,
27728 IX86_BUILTIN_VEC_EXT_V16QI,
27729 IX86_BUILTIN_VEC_SET_V2DI,
27730 IX86_BUILTIN_VEC_SET_V4SF,
27731 IX86_BUILTIN_VEC_SET_V4SI,
27732 IX86_BUILTIN_VEC_SET_V8HI,
27733 IX86_BUILTIN_VEC_SET_V4HI,
27734 IX86_BUILTIN_VEC_SET_V16QI,
27736 IX86_BUILTIN_VEC_PACK_SFIX,
27737 IX86_BUILTIN_VEC_PACK_SFIX256,
27739 /* SSE4.2. */
27740 IX86_BUILTIN_CRC32QI,
27741 IX86_BUILTIN_CRC32HI,
27742 IX86_BUILTIN_CRC32SI,
27743 IX86_BUILTIN_CRC32DI,
27745 IX86_BUILTIN_PCMPESTRI128,
27746 IX86_BUILTIN_PCMPESTRM128,
27747 IX86_BUILTIN_PCMPESTRA128,
27748 IX86_BUILTIN_PCMPESTRC128,
27749 IX86_BUILTIN_PCMPESTRO128,
27750 IX86_BUILTIN_PCMPESTRS128,
27751 IX86_BUILTIN_PCMPESTRZ128,
27752 IX86_BUILTIN_PCMPISTRI128,
27753 IX86_BUILTIN_PCMPISTRM128,
27754 IX86_BUILTIN_PCMPISTRA128,
27755 IX86_BUILTIN_PCMPISTRC128,
27756 IX86_BUILTIN_PCMPISTRO128,
27757 IX86_BUILTIN_PCMPISTRS128,
27758 IX86_BUILTIN_PCMPISTRZ128,
27760 IX86_BUILTIN_PCMPGTQ,
27762 /* AES instructions */
27763 IX86_BUILTIN_AESENC128,
27764 IX86_BUILTIN_AESENCLAST128,
27765 IX86_BUILTIN_AESDEC128,
27766 IX86_BUILTIN_AESDECLAST128,
27767 IX86_BUILTIN_AESIMC128,
27768 IX86_BUILTIN_AESKEYGENASSIST128,
27770 /* PCLMUL instruction */
27771 IX86_BUILTIN_PCLMULQDQ128,
27773 /* AVX */
27774 IX86_BUILTIN_ADDPD256,
27775 IX86_BUILTIN_ADDPS256,
27776 IX86_BUILTIN_ADDSUBPD256,
27777 IX86_BUILTIN_ADDSUBPS256,
27778 IX86_BUILTIN_ANDPD256,
27779 IX86_BUILTIN_ANDPS256,
27780 IX86_BUILTIN_ANDNPD256,
27781 IX86_BUILTIN_ANDNPS256,
27782 IX86_BUILTIN_BLENDPD256,
27783 IX86_BUILTIN_BLENDPS256,
27784 IX86_BUILTIN_BLENDVPD256,
27785 IX86_BUILTIN_BLENDVPS256,
27786 IX86_BUILTIN_DIVPD256,
27787 IX86_BUILTIN_DIVPS256,
27788 IX86_BUILTIN_DPPS256,
27789 IX86_BUILTIN_HADDPD256,
27790 IX86_BUILTIN_HADDPS256,
27791 IX86_BUILTIN_HSUBPD256,
27792 IX86_BUILTIN_HSUBPS256,
27793 IX86_BUILTIN_MAXPD256,
27794 IX86_BUILTIN_MAXPS256,
27795 IX86_BUILTIN_MINPD256,
27796 IX86_BUILTIN_MINPS256,
27797 IX86_BUILTIN_MULPD256,
27798 IX86_BUILTIN_MULPS256,
27799 IX86_BUILTIN_ORPD256,
27800 IX86_BUILTIN_ORPS256,
27801 IX86_BUILTIN_SHUFPD256,
27802 IX86_BUILTIN_SHUFPS256,
27803 IX86_BUILTIN_SUBPD256,
27804 IX86_BUILTIN_SUBPS256,
27805 IX86_BUILTIN_XORPD256,
27806 IX86_BUILTIN_XORPS256,
27807 IX86_BUILTIN_CMPSD,
27808 IX86_BUILTIN_CMPSS,
27809 IX86_BUILTIN_CMPPD,
27810 IX86_BUILTIN_CMPPS,
27811 IX86_BUILTIN_CMPPD256,
27812 IX86_BUILTIN_CMPPS256,
27813 IX86_BUILTIN_CVTDQ2PD256,
27814 IX86_BUILTIN_CVTDQ2PS256,
27815 IX86_BUILTIN_CVTPD2PS256,
27816 IX86_BUILTIN_CVTPS2DQ256,
27817 IX86_BUILTIN_CVTPS2PD256,
27818 IX86_BUILTIN_CVTTPD2DQ256,
27819 IX86_BUILTIN_CVTPD2DQ256,
27820 IX86_BUILTIN_CVTTPS2DQ256,
27821 IX86_BUILTIN_EXTRACTF128PD256,
27822 IX86_BUILTIN_EXTRACTF128PS256,
27823 IX86_BUILTIN_EXTRACTF128SI256,
27824 IX86_BUILTIN_VZEROALL,
27825 IX86_BUILTIN_VZEROUPPER,
27826 IX86_BUILTIN_VPERMILVARPD,
27827 IX86_BUILTIN_VPERMILVARPS,
27828 IX86_BUILTIN_VPERMILVARPD256,
27829 IX86_BUILTIN_VPERMILVARPS256,
27830 IX86_BUILTIN_VPERMILPD,
27831 IX86_BUILTIN_VPERMILPS,
27832 IX86_BUILTIN_VPERMILPD256,
27833 IX86_BUILTIN_VPERMILPS256,
27834 IX86_BUILTIN_VPERMIL2PD,
27835 IX86_BUILTIN_VPERMIL2PS,
27836 IX86_BUILTIN_VPERMIL2PD256,
27837 IX86_BUILTIN_VPERMIL2PS256,
27838 IX86_BUILTIN_VPERM2F128PD256,
27839 IX86_BUILTIN_VPERM2F128PS256,
27840 IX86_BUILTIN_VPERM2F128SI256,
27841 IX86_BUILTIN_VBROADCASTSS,
27842 IX86_BUILTIN_VBROADCASTSD256,
27843 IX86_BUILTIN_VBROADCASTSS256,
27844 IX86_BUILTIN_VBROADCASTPD256,
27845 IX86_BUILTIN_VBROADCASTPS256,
27846 IX86_BUILTIN_VINSERTF128PD256,
27847 IX86_BUILTIN_VINSERTF128PS256,
27848 IX86_BUILTIN_VINSERTF128SI256,
27849 IX86_BUILTIN_LOADUPD256,
27850 IX86_BUILTIN_LOADUPS256,
27851 IX86_BUILTIN_STOREUPD256,
27852 IX86_BUILTIN_STOREUPS256,
27853 IX86_BUILTIN_LDDQU256,
27854 IX86_BUILTIN_MOVNTDQ256,
27855 IX86_BUILTIN_MOVNTPD256,
27856 IX86_BUILTIN_MOVNTPS256,
27857 IX86_BUILTIN_LOADDQU256,
27858 IX86_BUILTIN_STOREDQU256,
27859 IX86_BUILTIN_MASKLOADPD,
27860 IX86_BUILTIN_MASKLOADPS,
27861 IX86_BUILTIN_MASKSTOREPD,
27862 IX86_BUILTIN_MASKSTOREPS,
27863 IX86_BUILTIN_MASKLOADPD256,
27864 IX86_BUILTIN_MASKLOADPS256,
27865 IX86_BUILTIN_MASKSTOREPD256,
27866 IX86_BUILTIN_MASKSTOREPS256,
27867 IX86_BUILTIN_MOVSHDUP256,
27868 IX86_BUILTIN_MOVSLDUP256,
27869 IX86_BUILTIN_MOVDDUP256,
27871 IX86_BUILTIN_SQRTPD256,
27872 IX86_BUILTIN_SQRTPS256,
27873 IX86_BUILTIN_SQRTPS_NR256,
27874 IX86_BUILTIN_RSQRTPS256,
27875 IX86_BUILTIN_RSQRTPS_NR256,
27877 IX86_BUILTIN_RCPPS256,
27879 IX86_BUILTIN_ROUNDPD256,
27880 IX86_BUILTIN_ROUNDPS256,
27882 IX86_BUILTIN_FLOORPD256,
27883 IX86_BUILTIN_CEILPD256,
27884 IX86_BUILTIN_TRUNCPD256,
27885 IX86_BUILTIN_RINTPD256,
27886 IX86_BUILTIN_ROUNDPD_AZ256,
27888 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
27889 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
27890 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
27892 IX86_BUILTIN_FLOORPS256,
27893 IX86_BUILTIN_CEILPS256,
27894 IX86_BUILTIN_TRUNCPS256,
27895 IX86_BUILTIN_RINTPS256,
27896 IX86_BUILTIN_ROUNDPS_AZ256,
27898 IX86_BUILTIN_FLOORPS_SFIX256,
27899 IX86_BUILTIN_CEILPS_SFIX256,
27900 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
27902 IX86_BUILTIN_UNPCKHPD256,
27903 IX86_BUILTIN_UNPCKLPD256,
27904 IX86_BUILTIN_UNPCKHPS256,
27905 IX86_BUILTIN_UNPCKLPS256,
27907 IX86_BUILTIN_SI256_SI,
27908 IX86_BUILTIN_PS256_PS,
27909 IX86_BUILTIN_PD256_PD,
27910 IX86_BUILTIN_SI_SI256,
27911 IX86_BUILTIN_PS_PS256,
27912 IX86_BUILTIN_PD_PD256,
27914 IX86_BUILTIN_VTESTZPD,
27915 IX86_BUILTIN_VTESTCPD,
27916 IX86_BUILTIN_VTESTNZCPD,
27917 IX86_BUILTIN_VTESTZPS,
27918 IX86_BUILTIN_VTESTCPS,
27919 IX86_BUILTIN_VTESTNZCPS,
27920 IX86_BUILTIN_VTESTZPD256,
27921 IX86_BUILTIN_VTESTCPD256,
27922 IX86_BUILTIN_VTESTNZCPD256,
27923 IX86_BUILTIN_VTESTZPS256,
27924 IX86_BUILTIN_VTESTCPS256,
27925 IX86_BUILTIN_VTESTNZCPS256,
27926 IX86_BUILTIN_PTESTZ256,
27927 IX86_BUILTIN_PTESTC256,
27928 IX86_BUILTIN_PTESTNZC256,
27930 IX86_BUILTIN_MOVMSKPD256,
27931 IX86_BUILTIN_MOVMSKPS256,
27933 /* AVX2 */
27934 IX86_BUILTIN_MPSADBW256,
27935 IX86_BUILTIN_PABSB256,
27936 IX86_BUILTIN_PABSW256,
27937 IX86_BUILTIN_PABSD256,
27938 IX86_BUILTIN_PACKSSDW256,
27939 IX86_BUILTIN_PACKSSWB256,
27940 IX86_BUILTIN_PACKUSDW256,
27941 IX86_BUILTIN_PACKUSWB256,
27942 IX86_BUILTIN_PADDB256,
27943 IX86_BUILTIN_PADDW256,
27944 IX86_BUILTIN_PADDD256,
27945 IX86_BUILTIN_PADDQ256,
27946 IX86_BUILTIN_PADDSB256,
27947 IX86_BUILTIN_PADDSW256,
27948 IX86_BUILTIN_PADDUSB256,
27949 IX86_BUILTIN_PADDUSW256,
27950 IX86_BUILTIN_PALIGNR256,
27951 IX86_BUILTIN_AND256I,
27952 IX86_BUILTIN_ANDNOT256I,
27953 IX86_BUILTIN_PAVGB256,
27954 IX86_BUILTIN_PAVGW256,
27955 IX86_BUILTIN_PBLENDVB256,
27956 IX86_BUILTIN_PBLENDVW256,
27957 IX86_BUILTIN_PCMPEQB256,
27958 IX86_BUILTIN_PCMPEQW256,
27959 IX86_BUILTIN_PCMPEQD256,
27960 IX86_BUILTIN_PCMPEQQ256,
27961 IX86_BUILTIN_PCMPGTB256,
27962 IX86_BUILTIN_PCMPGTW256,
27963 IX86_BUILTIN_PCMPGTD256,
27964 IX86_BUILTIN_PCMPGTQ256,
27965 IX86_BUILTIN_PHADDW256,
27966 IX86_BUILTIN_PHADDD256,
27967 IX86_BUILTIN_PHADDSW256,
27968 IX86_BUILTIN_PHSUBW256,
27969 IX86_BUILTIN_PHSUBD256,
27970 IX86_BUILTIN_PHSUBSW256,
27971 IX86_BUILTIN_PMADDUBSW256,
27972 IX86_BUILTIN_PMADDWD256,
27973 IX86_BUILTIN_PMAXSB256,
27974 IX86_BUILTIN_PMAXSW256,
27975 IX86_BUILTIN_PMAXSD256,
27976 IX86_BUILTIN_PMAXUB256,
27977 IX86_BUILTIN_PMAXUW256,
27978 IX86_BUILTIN_PMAXUD256,
27979 IX86_BUILTIN_PMINSB256,
27980 IX86_BUILTIN_PMINSW256,
27981 IX86_BUILTIN_PMINSD256,
27982 IX86_BUILTIN_PMINUB256,
27983 IX86_BUILTIN_PMINUW256,
27984 IX86_BUILTIN_PMINUD256,
27985 IX86_BUILTIN_PMOVMSKB256,
27986 IX86_BUILTIN_PMOVSXBW256,
27987 IX86_BUILTIN_PMOVSXBD256,
27988 IX86_BUILTIN_PMOVSXBQ256,
27989 IX86_BUILTIN_PMOVSXWD256,
27990 IX86_BUILTIN_PMOVSXWQ256,
27991 IX86_BUILTIN_PMOVSXDQ256,
27992 IX86_BUILTIN_PMOVZXBW256,
27993 IX86_BUILTIN_PMOVZXBD256,
27994 IX86_BUILTIN_PMOVZXBQ256,
27995 IX86_BUILTIN_PMOVZXWD256,
27996 IX86_BUILTIN_PMOVZXWQ256,
27997 IX86_BUILTIN_PMOVZXDQ256,
27998 IX86_BUILTIN_PMULDQ256,
27999 IX86_BUILTIN_PMULHRSW256,
28000 IX86_BUILTIN_PMULHUW256,
28001 IX86_BUILTIN_PMULHW256,
28002 IX86_BUILTIN_PMULLW256,
28003 IX86_BUILTIN_PMULLD256,
28004 IX86_BUILTIN_PMULUDQ256,
28005 IX86_BUILTIN_POR256,
28006 IX86_BUILTIN_PSADBW256,
28007 IX86_BUILTIN_PSHUFB256,
28008 IX86_BUILTIN_PSHUFD256,
28009 IX86_BUILTIN_PSHUFHW256,
28010 IX86_BUILTIN_PSHUFLW256,
28011 IX86_BUILTIN_PSIGNB256,
28012 IX86_BUILTIN_PSIGNW256,
28013 IX86_BUILTIN_PSIGND256,
28014 IX86_BUILTIN_PSLLDQI256,
28015 IX86_BUILTIN_PSLLWI256,
28016 IX86_BUILTIN_PSLLW256,
28017 IX86_BUILTIN_PSLLDI256,
28018 IX86_BUILTIN_PSLLD256,
28019 IX86_BUILTIN_PSLLQI256,
28020 IX86_BUILTIN_PSLLQ256,
28021 IX86_BUILTIN_PSRAWI256,
28022 IX86_BUILTIN_PSRAW256,
28023 IX86_BUILTIN_PSRADI256,
28024 IX86_BUILTIN_PSRAD256,
28025 IX86_BUILTIN_PSRLDQI256,
28026 IX86_BUILTIN_PSRLWI256,
28027 IX86_BUILTIN_PSRLW256,
28028 IX86_BUILTIN_PSRLDI256,
28029 IX86_BUILTIN_PSRLD256,
28030 IX86_BUILTIN_PSRLQI256,
28031 IX86_BUILTIN_PSRLQ256,
28032 IX86_BUILTIN_PSUBB256,
28033 IX86_BUILTIN_PSUBW256,
28034 IX86_BUILTIN_PSUBD256,
28035 IX86_BUILTIN_PSUBQ256,
28036 IX86_BUILTIN_PSUBSB256,
28037 IX86_BUILTIN_PSUBSW256,
28038 IX86_BUILTIN_PSUBUSB256,
28039 IX86_BUILTIN_PSUBUSW256,
28040 IX86_BUILTIN_PUNPCKHBW256,
28041 IX86_BUILTIN_PUNPCKHWD256,
28042 IX86_BUILTIN_PUNPCKHDQ256,
28043 IX86_BUILTIN_PUNPCKHQDQ256,
28044 IX86_BUILTIN_PUNPCKLBW256,
28045 IX86_BUILTIN_PUNPCKLWD256,
28046 IX86_BUILTIN_PUNPCKLDQ256,
28047 IX86_BUILTIN_PUNPCKLQDQ256,
28048 IX86_BUILTIN_PXOR256,
28049 IX86_BUILTIN_MOVNTDQA256,
28050 IX86_BUILTIN_VBROADCASTSS_PS,
28051 IX86_BUILTIN_VBROADCASTSS_PS256,
28052 IX86_BUILTIN_VBROADCASTSD_PD256,
28053 IX86_BUILTIN_VBROADCASTSI256,
28054 IX86_BUILTIN_PBLENDD256,
28055 IX86_BUILTIN_PBLENDD128,
28056 IX86_BUILTIN_PBROADCASTB256,
28057 IX86_BUILTIN_PBROADCASTW256,
28058 IX86_BUILTIN_PBROADCASTD256,
28059 IX86_BUILTIN_PBROADCASTQ256,
28060 IX86_BUILTIN_PBROADCASTB128,
28061 IX86_BUILTIN_PBROADCASTW128,
28062 IX86_BUILTIN_PBROADCASTD128,
28063 IX86_BUILTIN_PBROADCASTQ128,
28064 IX86_BUILTIN_VPERMVARSI256,
28065 IX86_BUILTIN_VPERMDF256,
28066 IX86_BUILTIN_VPERMVARSF256,
28067 IX86_BUILTIN_VPERMDI256,
28068 IX86_BUILTIN_VPERMTI256,
28069 IX86_BUILTIN_VEXTRACT128I256,
28070 IX86_BUILTIN_VINSERT128I256,
28071 IX86_BUILTIN_MASKLOADD,
28072 IX86_BUILTIN_MASKLOADQ,
28073 IX86_BUILTIN_MASKLOADD256,
28074 IX86_BUILTIN_MASKLOADQ256,
28075 IX86_BUILTIN_MASKSTORED,
28076 IX86_BUILTIN_MASKSTOREQ,
28077 IX86_BUILTIN_MASKSTORED256,
28078 IX86_BUILTIN_MASKSTOREQ256,
28079 IX86_BUILTIN_PSLLVV4DI,
28080 IX86_BUILTIN_PSLLVV2DI,
28081 IX86_BUILTIN_PSLLVV8SI,
28082 IX86_BUILTIN_PSLLVV4SI,
28083 IX86_BUILTIN_PSRAVV8SI,
28084 IX86_BUILTIN_PSRAVV4SI,
28085 IX86_BUILTIN_PSRLVV4DI,
28086 IX86_BUILTIN_PSRLVV2DI,
28087 IX86_BUILTIN_PSRLVV8SI,
28088 IX86_BUILTIN_PSRLVV4SI,
28090 IX86_BUILTIN_GATHERSIV2DF,
28091 IX86_BUILTIN_GATHERSIV4DF,
28092 IX86_BUILTIN_GATHERDIV2DF,
28093 IX86_BUILTIN_GATHERDIV4DF,
28094 IX86_BUILTIN_GATHERSIV4SF,
28095 IX86_BUILTIN_GATHERSIV8SF,
28096 IX86_BUILTIN_GATHERDIV4SF,
28097 IX86_BUILTIN_GATHERDIV8SF,
28098 IX86_BUILTIN_GATHERSIV2DI,
28099 IX86_BUILTIN_GATHERSIV4DI,
28100 IX86_BUILTIN_GATHERDIV2DI,
28101 IX86_BUILTIN_GATHERDIV4DI,
28102 IX86_BUILTIN_GATHERSIV4SI,
28103 IX86_BUILTIN_GATHERSIV8SI,
28104 IX86_BUILTIN_GATHERDIV4SI,
28105 IX86_BUILTIN_GATHERDIV8SI,
28107 /* AVX512F */
28108 IX86_BUILTIN_ADDPD512,
28109 IX86_BUILTIN_ADDPS512,
28110 IX86_BUILTIN_ADDSD_ROUND,
28111 IX86_BUILTIN_ADDSS_ROUND,
28112 IX86_BUILTIN_ALIGND512,
28113 IX86_BUILTIN_ALIGNQ512,
28114 IX86_BUILTIN_BLENDMD512,
28115 IX86_BUILTIN_BLENDMPD512,
28116 IX86_BUILTIN_BLENDMPS512,
28117 IX86_BUILTIN_BLENDMQ512,
28118 IX86_BUILTIN_BROADCASTF32X4_512,
28119 IX86_BUILTIN_BROADCASTF64X4_512,
28120 IX86_BUILTIN_BROADCASTI32X4_512,
28121 IX86_BUILTIN_BROADCASTI64X4_512,
28122 IX86_BUILTIN_BROADCASTSD512,
28123 IX86_BUILTIN_BROADCASTSS512,
28124 IX86_BUILTIN_CMPD512,
28125 IX86_BUILTIN_CMPPD512,
28126 IX86_BUILTIN_CMPPS512,
28127 IX86_BUILTIN_CMPQ512,
28128 IX86_BUILTIN_CMPSD_MASK,
28129 IX86_BUILTIN_CMPSS_MASK,
28130 IX86_BUILTIN_COMIDF,
28131 IX86_BUILTIN_COMISF,
28132 IX86_BUILTIN_COMPRESSPD512,
28133 IX86_BUILTIN_COMPRESSPDSTORE512,
28134 IX86_BUILTIN_COMPRESSPS512,
28135 IX86_BUILTIN_COMPRESSPSSTORE512,
28136 IX86_BUILTIN_CVTDQ2PD512,
28137 IX86_BUILTIN_CVTDQ2PS512,
28138 IX86_BUILTIN_CVTPD2DQ512,
28139 IX86_BUILTIN_CVTPD2PS512,
28140 IX86_BUILTIN_CVTPD2UDQ512,
28141 IX86_BUILTIN_CVTPH2PS512,
28142 IX86_BUILTIN_CVTPS2DQ512,
28143 IX86_BUILTIN_CVTPS2PD512,
28144 IX86_BUILTIN_CVTPS2PH512,
28145 IX86_BUILTIN_CVTPS2UDQ512,
28146 IX86_BUILTIN_CVTSD2SS_ROUND,
28147 IX86_BUILTIN_CVTSI2SD64,
28148 IX86_BUILTIN_CVTSI2SS32,
28149 IX86_BUILTIN_CVTSI2SS64,
28150 IX86_BUILTIN_CVTSS2SD_ROUND,
28151 IX86_BUILTIN_CVTTPD2DQ512,
28152 IX86_BUILTIN_CVTTPD2UDQ512,
28153 IX86_BUILTIN_CVTTPS2DQ512,
28154 IX86_BUILTIN_CVTTPS2UDQ512,
28155 IX86_BUILTIN_CVTUDQ2PD512,
28156 IX86_BUILTIN_CVTUDQ2PS512,
28157 IX86_BUILTIN_CVTUSI2SD32,
28158 IX86_BUILTIN_CVTUSI2SD64,
28159 IX86_BUILTIN_CVTUSI2SS32,
28160 IX86_BUILTIN_CVTUSI2SS64,
28161 IX86_BUILTIN_DIVPD512,
28162 IX86_BUILTIN_DIVPS512,
28163 IX86_BUILTIN_DIVSD_ROUND,
28164 IX86_BUILTIN_DIVSS_ROUND,
28165 IX86_BUILTIN_EXPANDPD512,
28166 IX86_BUILTIN_EXPANDPD512Z,
28167 IX86_BUILTIN_EXPANDPDLOAD512,
28168 IX86_BUILTIN_EXPANDPDLOAD512Z,
28169 IX86_BUILTIN_EXPANDPS512,
28170 IX86_BUILTIN_EXPANDPS512Z,
28171 IX86_BUILTIN_EXPANDPSLOAD512,
28172 IX86_BUILTIN_EXPANDPSLOAD512Z,
28173 IX86_BUILTIN_EXTRACTF32X4,
28174 IX86_BUILTIN_EXTRACTF64X4,
28175 IX86_BUILTIN_EXTRACTI32X4,
28176 IX86_BUILTIN_EXTRACTI64X4,
28177 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28178 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28179 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28180 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28181 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28182 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28183 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28184 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28185 IX86_BUILTIN_GETEXPPD512,
28186 IX86_BUILTIN_GETEXPPS512,
28187 IX86_BUILTIN_GETEXPSD128,
28188 IX86_BUILTIN_GETEXPSS128,
28189 IX86_BUILTIN_GETMANTPD512,
28190 IX86_BUILTIN_GETMANTPS512,
28191 IX86_BUILTIN_GETMANTSD128,
28192 IX86_BUILTIN_GETMANTSS128,
28193 IX86_BUILTIN_INSERTF32X4,
28194 IX86_BUILTIN_INSERTF64X4,
28195 IX86_BUILTIN_INSERTI32X4,
28196 IX86_BUILTIN_INSERTI64X4,
28197 IX86_BUILTIN_LOADAPD512,
28198 IX86_BUILTIN_LOADAPS512,
28199 IX86_BUILTIN_LOADDQUDI512,
28200 IX86_BUILTIN_LOADDQUSI512,
28201 IX86_BUILTIN_LOADUPD512,
28202 IX86_BUILTIN_LOADUPS512,
28203 IX86_BUILTIN_MAXPD512,
28204 IX86_BUILTIN_MAXPS512,
28205 IX86_BUILTIN_MAXSD_ROUND,
28206 IX86_BUILTIN_MAXSS_ROUND,
28207 IX86_BUILTIN_MINPD512,
28208 IX86_BUILTIN_MINPS512,
28209 IX86_BUILTIN_MINSD_ROUND,
28210 IX86_BUILTIN_MINSS_ROUND,
28211 IX86_BUILTIN_MOVAPD512,
28212 IX86_BUILTIN_MOVAPS512,
28213 IX86_BUILTIN_MOVDDUP512,
28214 IX86_BUILTIN_MOVDQA32LOAD512,
28215 IX86_BUILTIN_MOVDQA32STORE512,
28216 IX86_BUILTIN_MOVDQA32_512,
28217 IX86_BUILTIN_MOVDQA64LOAD512,
28218 IX86_BUILTIN_MOVDQA64STORE512,
28219 IX86_BUILTIN_MOVDQA64_512,
28220 IX86_BUILTIN_MOVNTDQ512,
28221 IX86_BUILTIN_MOVNTDQA512,
28222 IX86_BUILTIN_MOVNTPD512,
28223 IX86_BUILTIN_MOVNTPS512,
28224 IX86_BUILTIN_MOVSHDUP512,
28225 IX86_BUILTIN_MOVSLDUP512,
28226 IX86_BUILTIN_MULPD512,
28227 IX86_BUILTIN_MULPS512,
28228 IX86_BUILTIN_MULSD_ROUND,
28229 IX86_BUILTIN_MULSS_ROUND,
28230 IX86_BUILTIN_PABSD512,
28231 IX86_BUILTIN_PABSQ512,
28232 IX86_BUILTIN_PADDD512,
28233 IX86_BUILTIN_PADDQ512,
28234 IX86_BUILTIN_PANDD512,
28235 IX86_BUILTIN_PANDND512,
28236 IX86_BUILTIN_PANDNQ512,
28237 IX86_BUILTIN_PANDQ512,
28238 IX86_BUILTIN_PBROADCASTD512,
28239 IX86_BUILTIN_PBROADCASTD512_GPR,
28240 IX86_BUILTIN_PBROADCASTMB512,
28241 IX86_BUILTIN_PBROADCASTMW512,
28242 IX86_BUILTIN_PBROADCASTQ512,
28243 IX86_BUILTIN_PBROADCASTQ512_GPR,
28244 IX86_BUILTIN_PBROADCASTQ512_MEM,
28245 IX86_BUILTIN_PCMPEQD512_MASK,
28246 IX86_BUILTIN_PCMPEQQ512_MASK,
28247 IX86_BUILTIN_PCMPGTD512_MASK,
28248 IX86_BUILTIN_PCMPGTQ512_MASK,
28249 IX86_BUILTIN_PCOMPRESSD512,
28250 IX86_BUILTIN_PCOMPRESSDSTORE512,
28251 IX86_BUILTIN_PCOMPRESSQ512,
28252 IX86_BUILTIN_PCOMPRESSQSTORE512,
28253 IX86_BUILTIN_PEXPANDD512,
28254 IX86_BUILTIN_PEXPANDD512Z,
28255 IX86_BUILTIN_PEXPANDDLOAD512,
28256 IX86_BUILTIN_PEXPANDDLOAD512Z,
28257 IX86_BUILTIN_PEXPANDQ512,
28258 IX86_BUILTIN_PEXPANDQ512Z,
28259 IX86_BUILTIN_PEXPANDQLOAD512,
28260 IX86_BUILTIN_PEXPANDQLOAD512Z,
28261 IX86_BUILTIN_PMAXSD512,
28262 IX86_BUILTIN_PMAXSQ512,
28263 IX86_BUILTIN_PMAXUD512,
28264 IX86_BUILTIN_PMAXUQ512,
28265 IX86_BUILTIN_PMINSD512,
28266 IX86_BUILTIN_PMINSQ512,
28267 IX86_BUILTIN_PMINUD512,
28268 IX86_BUILTIN_PMINUQ512,
28269 IX86_BUILTIN_PMOVDB512,
28270 IX86_BUILTIN_PMOVDB512_MEM,
28271 IX86_BUILTIN_PMOVDW512,
28272 IX86_BUILTIN_PMOVDW512_MEM,
28273 IX86_BUILTIN_PMOVQB512,
28274 IX86_BUILTIN_PMOVQB512_MEM,
28275 IX86_BUILTIN_PMOVQD512,
28276 IX86_BUILTIN_PMOVQD512_MEM,
28277 IX86_BUILTIN_PMOVQW512,
28278 IX86_BUILTIN_PMOVQW512_MEM,
28279 IX86_BUILTIN_PMOVSDB512,
28280 IX86_BUILTIN_PMOVSDB512_MEM,
28281 IX86_BUILTIN_PMOVSDW512,
28282 IX86_BUILTIN_PMOVSDW512_MEM,
28283 IX86_BUILTIN_PMOVSQB512,
28284 IX86_BUILTIN_PMOVSQB512_MEM,
28285 IX86_BUILTIN_PMOVSQD512,
28286 IX86_BUILTIN_PMOVSQD512_MEM,
28287 IX86_BUILTIN_PMOVSQW512,
28288 IX86_BUILTIN_PMOVSQW512_MEM,
28289 IX86_BUILTIN_PMOVSXBD512,
28290 IX86_BUILTIN_PMOVSXBQ512,
28291 IX86_BUILTIN_PMOVSXDQ512,
28292 IX86_BUILTIN_PMOVSXWD512,
28293 IX86_BUILTIN_PMOVSXWQ512,
28294 IX86_BUILTIN_PMOVUSDB512,
28295 IX86_BUILTIN_PMOVUSDB512_MEM,
28296 IX86_BUILTIN_PMOVUSDW512,
28297 IX86_BUILTIN_PMOVUSDW512_MEM,
28298 IX86_BUILTIN_PMOVUSQB512,
28299 IX86_BUILTIN_PMOVUSQB512_MEM,
28300 IX86_BUILTIN_PMOVUSQD512,
28301 IX86_BUILTIN_PMOVUSQD512_MEM,
28302 IX86_BUILTIN_PMOVUSQW512,
28303 IX86_BUILTIN_PMOVUSQW512_MEM,
28304 IX86_BUILTIN_PMOVZXBD512,
28305 IX86_BUILTIN_PMOVZXBQ512,
28306 IX86_BUILTIN_PMOVZXDQ512,
28307 IX86_BUILTIN_PMOVZXWD512,
28308 IX86_BUILTIN_PMOVZXWQ512,
28309 IX86_BUILTIN_PMULDQ512,
28310 IX86_BUILTIN_PMULLD512,
28311 IX86_BUILTIN_PMULUDQ512,
28312 IX86_BUILTIN_PORD512,
28313 IX86_BUILTIN_PORQ512,
28314 IX86_BUILTIN_PROLD512,
28315 IX86_BUILTIN_PROLQ512,
28316 IX86_BUILTIN_PROLVD512,
28317 IX86_BUILTIN_PROLVQ512,
28318 IX86_BUILTIN_PRORD512,
28319 IX86_BUILTIN_PRORQ512,
28320 IX86_BUILTIN_PRORVD512,
28321 IX86_BUILTIN_PRORVQ512,
28322 IX86_BUILTIN_PSHUFD512,
28323 IX86_BUILTIN_PSLLD512,
28324 IX86_BUILTIN_PSLLDI512,
28325 IX86_BUILTIN_PSLLQ512,
28326 IX86_BUILTIN_PSLLQI512,
28327 IX86_BUILTIN_PSLLVV16SI,
28328 IX86_BUILTIN_PSLLVV8DI,
28329 IX86_BUILTIN_PSRAD512,
28330 IX86_BUILTIN_PSRADI512,
28331 IX86_BUILTIN_PSRAQ512,
28332 IX86_BUILTIN_PSRAQI512,
28333 IX86_BUILTIN_PSRAVV16SI,
28334 IX86_BUILTIN_PSRAVV8DI,
28335 IX86_BUILTIN_PSRLD512,
28336 IX86_BUILTIN_PSRLDI512,
28337 IX86_BUILTIN_PSRLQ512,
28338 IX86_BUILTIN_PSRLQI512,
28339 IX86_BUILTIN_PSRLVV16SI,
28340 IX86_BUILTIN_PSRLVV8DI,
28341 IX86_BUILTIN_PSUBD512,
28342 IX86_BUILTIN_PSUBQ512,
28343 IX86_BUILTIN_PTESTMD512,
28344 IX86_BUILTIN_PTESTMQ512,
28345 IX86_BUILTIN_PTESTNMD512,
28346 IX86_BUILTIN_PTESTNMQ512,
28347 IX86_BUILTIN_PUNPCKHDQ512,
28348 IX86_BUILTIN_PUNPCKHQDQ512,
28349 IX86_BUILTIN_PUNPCKLDQ512,
28350 IX86_BUILTIN_PUNPCKLQDQ512,
28351 IX86_BUILTIN_PXORD512,
28352 IX86_BUILTIN_PXORQ512,
28353 IX86_BUILTIN_RCP14PD512,
28354 IX86_BUILTIN_RCP14PS512,
28355 IX86_BUILTIN_RCP14SD,
28356 IX86_BUILTIN_RCP14SS,
28357 IX86_BUILTIN_RNDSCALEPD,
28358 IX86_BUILTIN_RNDSCALEPS,
28359 IX86_BUILTIN_RNDSCALESD,
28360 IX86_BUILTIN_RNDSCALESS,
28361 IX86_BUILTIN_RSQRT14PD512,
28362 IX86_BUILTIN_RSQRT14PS512,
28363 IX86_BUILTIN_RSQRT14SD,
28364 IX86_BUILTIN_RSQRT14SS,
28365 IX86_BUILTIN_SCALEFPD512,
28366 IX86_BUILTIN_SCALEFPS512,
28367 IX86_BUILTIN_SCALEFSD,
28368 IX86_BUILTIN_SCALEFSS,
28369 IX86_BUILTIN_SHUFPD512,
28370 IX86_BUILTIN_SHUFPS512,
28371 IX86_BUILTIN_SHUF_F32x4,
28372 IX86_BUILTIN_SHUF_F64x2,
28373 IX86_BUILTIN_SHUF_I32x4,
28374 IX86_BUILTIN_SHUF_I64x2,
28375 IX86_BUILTIN_SQRTPD512,
28376 IX86_BUILTIN_SQRTPD512_MASK,
28377 IX86_BUILTIN_SQRTPS512_MASK,
28378 IX86_BUILTIN_SQRTPS_NR512,
28379 IX86_BUILTIN_SQRTSD_ROUND,
28380 IX86_BUILTIN_SQRTSS_ROUND,
28381 IX86_BUILTIN_STOREAPD512,
28382 IX86_BUILTIN_STOREAPS512,
28383 IX86_BUILTIN_STOREDQUDI512,
28384 IX86_BUILTIN_STOREDQUSI512,
28385 IX86_BUILTIN_STOREUPD512,
28386 IX86_BUILTIN_STOREUPS512,
28387 IX86_BUILTIN_SUBPD512,
28388 IX86_BUILTIN_SUBPS512,
28389 IX86_BUILTIN_SUBSD_ROUND,
28390 IX86_BUILTIN_SUBSS_ROUND,
28391 IX86_BUILTIN_UCMPD512,
28392 IX86_BUILTIN_UCMPQ512,
28393 IX86_BUILTIN_UNPCKHPD512,
28394 IX86_BUILTIN_UNPCKHPS512,
28395 IX86_BUILTIN_UNPCKLPD512,
28396 IX86_BUILTIN_UNPCKLPS512,
28397 IX86_BUILTIN_VCVTSD2SI32,
28398 IX86_BUILTIN_VCVTSD2SI64,
28399 IX86_BUILTIN_VCVTSD2USI32,
28400 IX86_BUILTIN_VCVTSD2USI64,
28401 IX86_BUILTIN_VCVTSS2SI32,
28402 IX86_BUILTIN_VCVTSS2SI64,
28403 IX86_BUILTIN_VCVTSS2USI32,
28404 IX86_BUILTIN_VCVTSS2USI64,
28405 IX86_BUILTIN_VCVTTSD2SI32,
28406 IX86_BUILTIN_VCVTTSD2SI64,
28407 IX86_BUILTIN_VCVTTSD2USI32,
28408 IX86_BUILTIN_VCVTTSD2USI64,
28409 IX86_BUILTIN_VCVTTSS2SI32,
28410 IX86_BUILTIN_VCVTTSS2SI64,
28411 IX86_BUILTIN_VCVTTSS2USI32,
28412 IX86_BUILTIN_VCVTTSS2USI64,
28413 IX86_BUILTIN_VFMADDPD512_MASK,
28414 IX86_BUILTIN_VFMADDPD512_MASK3,
28415 IX86_BUILTIN_VFMADDPD512_MASKZ,
28416 IX86_BUILTIN_VFMADDPS512_MASK,
28417 IX86_BUILTIN_VFMADDPS512_MASK3,
28418 IX86_BUILTIN_VFMADDPS512_MASKZ,
28419 IX86_BUILTIN_VFMADDSD3_ROUND,
28420 IX86_BUILTIN_VFMADDSS3_ROUND,
28421 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28422 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28423 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28424 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28425 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28426 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28427 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28428 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28429 IX86_BUILTIN_VFMSUBPD512_MASK3,
28430 IX86_BUILTIN_VFMSUBPS512_MASK3,
28431 IX86_BUILTIN_VFMSUBSD3_MASK3,
28432 IX86_BUILTIN_VFMSUBSS3_MASK3,
28433 IX86_BUILTIN_VFNMADDPD512_MASK,
28434 IX86_BUILTIN_VFNMADDPS512_MASK,
28435 IX86_BUILTIN_VFNMSUBPD512_MASK,
28436 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28437 IX86_BUILTIN_VFNMSUBPS512_MASK,
28438 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28439 IX86_BUILTIN_VPCLZCNTD512,
28440 IX86_BUILTIN_VPCLZCNTQ512,
28441 IX86_BUILTIN_VPCONFLICTD512,
28442 IX86_BUILTIN_VPCONFLICTQ512,
28443 IX86_BUILTIN_VPERMDF512,
28444 IX86_BUILTIN_VPERMDI512,
28445 IX86_BUILTIN_VPERMI2VARD512,
28446 IX86_BUILTIN_VPERMI2VARPD512,
28447 IX86_BUILTIN_VPERMI2VARPS512,
28448 IX86_BUILTIN_VPERMI2VARQ512,
28449 IX86_BUILTIN_VPERMILPD512,
28450 IX86_BUILTIN_VPERMILPS512,
28451 IX86_BUILTIN_VPERMILVARPD512,
28452 IX86_BUILTIN_VPERMILVARPS512,
28453 IX86_BUILTIN_VPERMT2VARD512,
28454 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28455 IX86_BUILTIN_VPERMT2VARPD512,
28456 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28457 IX86_BUILTIN_VPERMT2VARPS512,
28458 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28459 IX86_BUILTIN_VPERMT2VARQ512,
28460 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28461 IX86_BUILTIN_VPERMVARDF512,
28462 IX86_BUILTIN_VPERMVARDI512,
28463 IX86_BUILTIN_VPERMVARSF512,
28464 IX86_BUILTIN_VPERMVARSI512,
28465 IX86_BUILTIN_VTERNLOGD512_MASK,
28466 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28467 IX86_BUILTIN_VTERNLOGQ512_MASK,
28468 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28470 /* Mask arithmetic operations */
28471 IX86_BUILTIN_KAND16,
28472 IX86_BUILTIN_KANDN16,
28473 IX86_BUILTIN_KNOT16,
28474 IX86_BUILTIN_KOR16,
28475 IX86_BUILTIN_KORTESTC16,
28476 IX86_BUILTIN_KORTESTZ16,
28477 IX86_BUILTIN_KUNPCKBW,
28478 IX86_BUILTIN_KXNOR16,
28479 IX86_BUILTIN_KXOR16,
28480 IX86_BUILTIN_KMOV16,
28482 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28483 where all operands are 32-byte or 64-byte wide respectively. */
28484 IX86_BUILTIN_GATHERALTSIV4DF,
28485 IX86_BUILTIN_GATHERALTDIV8SF,
28486 IX86_BUILTIN_GATHERALTSIV4DI,
28487 IX86_BUILTIN_GATHERALTDIV8SI,
28488 IX86_BUILTIN_GATHER3ALTDIV16SF,
28489 IX86_BUILTIN_GATHER3ALTDIV16SI,
28490 IX86_BUILTIN_GATHER3ALTSIV8DF,
28491 IX86_BUILTIN_GATHER3ALTSIV8DI,
28492 IX86_BUILTIN_GATHER3DIV16SF,
28493 IX86_BUILTIN_GATHER3DIV16SI,
28494 IX86_BUILTIN_GATHER3DIV8DF,
28495 IX86_BUILTIN_GATHER3DIV8DI,
28496 IX86_BUILTIN_GATHER3SIV16SF,
28497 IX86_BUILTIN_GATHER3SIV16SI,
28498 IX86_BUILTIN_GATHER3SIV8DF,
28499 IX86_BUILTIN_GATHER3SIV8DI,
28500 IX86_BUILTIN_SCATTERDIV16SF,
28501 IX86_BUILTIN_SCATTERDIV16SI,
28502 IX86_BUILTIN_SCATTERDIV8DF,
28503 IX86_BUILTIN_SCATTERDIV8DI,
28504 IX86_BUILTIN_SCATTERSIV16SF,
28505 IX86_BUILTIN_SCATTERSIV16SI,
28506 IX86_BUILTIN_SCATTERSIV8DF,
28507 IX86_BUILTIN_SCATTERSIV8DI,
28509 /* AVX512PF */
28510 IX86_BUILTIN_GATHERPFQPD,
28511 IX86_BUILTIN_GATHERPFDPS,
28512 IX86_BUILTIN_GATHERPFDPD,
28513 IX86_BUILTIN_GATHERPFQPS,
28514 IX86_BUILTIN_SCATTERPFDPD,
28515 IX86_BUILTIN_SCATTERPFDPS,
28516 IX86_BUILTIN_SCATTERPFQPD,
28517 IX86_BUILTIN_SCATTERPFQPS,
28519 /* AVX-512ER */
28520 IX86_BUILTIN_EXP2PD_MASK,
28521 IX86_BUILTIN_EXP2PS_MASK,
28522 IX86_BUILTIN_EXP2PS,
28523 IX86_BUILTIN_RCP28PD,
28524 IX86_BUILTIN_RCP28PS,
28525 IX86_BUILTIN_RCP28SD,
28526 IX86_BUILTIN_RCP28SS,
28527 IX86_BUILTIN_RSQRT28PD,
28528 IX86_BUILTIN_RSQRT28PS,
28529 IX86_BUILTIN_RSQRT28SD,
28530 IX86_BUILTIN_RSQRT28SS,
28532 /* SHA builtins. */
28533 IX86_BUILTIN_SHA1MSG1,
28534 IX86_BUILTIN_SHA1MSG2,
28535 IX86_BUILTIN_SHA1NEXTE,
28536 IX86_BUILTIN_SHA1RNDS4,
28537 IX86_BUILTIN_SHA256MSG1,
28538 IX86_BUILTIN_SHA256MSG2,
28539 IX86_BUILTIN_SHA256RNDS2,
28541 /* CLFLUSHOPT instructions. */
28542 IX86_BUILTIN_CLFLUSHOPT,
28544 /* TFmode support builtins. */
28545 IX86_BUILTIN_INFQ,
28546 IX86_BUILTIN_HUGE_VALQ,
28547 IX86_BUILTIN_FABSQ,
28548 IX86_BUILTIN_COPYSIGNQ,
28550 /* Vectorizer support builtins. */
28551 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28552 IX86_BUILTIN_CPYSGNPS,
28553 IX86_BUILTIN_CPYSGNPD,
28554 IX86_BUILTIN_CPYSGNPS256,
28555 IX86_BUILTIN_CPYSGNPS512,
28556 IX86_BUILTIN_CPYSGNPD256,
28557 IX86_BUILTIN_CPYSGNPD512,
28558 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28559 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28562 /* FMA4 instructions. */
28563 IX86_BUILTIN_VFMADDSS,
28564 IX86_BUILTIN_VFMADDSD,
28565 IX86_BUILTIN_VFMADDPS,
28566 IX86_BUILTIN_VFMADDPD,
28567 IX86_BUILTIN_VFMADDPS256,
28568 IX86_BUILTIN_VFMADDPD256,
28569 IX86_BUILTIN_VFMADDSUBPS,
28570 IX86_BUILTIN_VFMADDSUBPD,
28571 IX86_BUILTIN_VFMADDSUBPS256,
28572 IX86_BUILTIN_VFMADDSUBPD256,
28574 /* FMA3 instructions. */
28575 IX86_BUILTIN_VFMADDSS3,
28576 IX86_BUILTIN_VFMADDSD3,
28578 /* XOP instructions. */
28579 IX86_BUILTIN_VPCMOV,
28580 IX86_BUILTIN_VPCMOV_V2DI,
28581 IX86_BUILTIN_VPCMOV_V4SI,
28582 IX86_BUILTIN_VPCMOV_V8HI,
28583 IX86_BUILTIN_VPCMOV_V16QI,
28584 IX86_BUILTIN_VPCMOV_V4SF,
28585 IX86_BUILTIN_VPCMOV_V2DF,
28586 IX86_BUILTIN_VPCMOV256,
28587 IX86_BUILTIN_VPCMOV_V4DI256,
28588 IX86_BUILTIN_VPCMOV_V8SI256,
28589 IX86_BUILTIN_VPCMOV_V16HI256,
28590 IX86_BUILTIN_VPCMOV_V32QI256,
28591 IX86_BUILTIN_VPCMOV_V8SF256,
28592 IX86_BUILTIN_VPCMOV_V4DF256,
28594 IX86_BUILTIN_VPPERM,
28596 IX86_BUILTIN_VPMACSSWW,
28597 IX86_BUILTIN_VPMACSWW,
28598 IX86_BUILTIN_VPMACSSWD,
28599 IX86_BUILTIN_VPMACSWD,
28600 IX86_BUILTIN_VPMACSSDD,
28601 IX86_BUILTIN_VPMACSDD,
28602 IX86_BUILTIN_VPMACSSDQL,
28603 IX86_BUILTIN_VPMACSSDQH,
28604 IX86_BUILTIN_VPMACSDQL,
28605 IX86_BUILTIN_VPMACSDQH,
28606 IX86_BUILTIN_VPMADCSSWD,
28607 IX86_BUILTIN_VPMADCSWD,
28609 IX86_BUILTIN_VPHADDBW,
28610 IX86_BUILTIN_VPHADDBD,
28611 IX86_BUILTIN_VPHADDBQ,
28612 IX86_BUILTIN_VPHADDWD,
28613 IX86_BUILTIN_VPHADDWQ,
28614 IX86_BUILTIN_VPHADDDQ,
28615 IX86_BUILTIN_VPHADDUBW,
28616 IX86_BUILTIN_VPHADDUBD,
28617 IX86_BUILTIN_VPHADDUBQ,
28618 IX86_BUILTIN_VPHADDUWD,
28619 IX86_BUILTIN_VPHADDUWQ,
28620 IX86_BUILTIN_VPHADDUDQ,
28621 IX86_BUILTIN_VPHSUBBW,
28622 IX86_BUILTIN_VPHSUBWD,
28623 IX86_BUILTIN_VPHSUBDQ,
28625 IX86_BUILTIN_VPROTB,
28626 IX86_BUILTIN_VPROTW,
28627 IX86_BUILTIN_VPROTD,
28628 IX86_BUILTIN_VPROTQ,
28629 IX86_BUILTIN_VPROTB_IMM,
28630 IX86_BUILTIN_VPROTW_IMM,
28631 IX86_BUILTIN_VPROTD_IMM,
28632 IX86_BUILTIN_VPROTQ_IMM,
28634 IX86_BUILTIN_VPSHLB,
28635 IX86_BUILTIN_VPSHLW,
28636 IX86_BUILTIN_VPSHLD,
28637 IX86_BUILTIN_VPSHLQ,
28638 IX86_BUILTIN_VPSHAB,
28639 IX86_BUILTIN_VPSHAW,
28640 IX86_BUILTIN_VPSHAD,
28641 IX86_BUILTIN_VPSHAQ,
28643 IX86_BUILTIN_VFRCZSS,
28644 IX86_BUILTIN_VFRCZSD,
28645 IX86_BUILTIN_VFRCZPS,
28646 IX86_BUILTIN_VFRCZPD,
28647 IX86_BUILTIN_VFRCZPS256,
28648 IX86_BUILTIN_VFRCZPD256,
28650 IX86_BUILTIN_VPCOMEQUB,
28651 IX86_BUILTIN_VPCOMNEUB,
28652 IX86_BUILTIN_VPCOMLTUB,
28653 IX86_BUILTIN_VPCOMLEUB,
28654 IX86_BUILTIN_VPCOMGTUB,
28655 IX86_BUILTIN_VPCOMGEUB,
28656 IX86_BUILTIN_VPCOMFALSEUB,
28657 IX86_BUILTIN_VPCOMTRUEUB,
28659 IX86_BUILTIN_VPCOMEQUW,
28660 IX86_BUILTIN_VPCOMNEUW,
28661 IX86_BUILTIN_VPCOMLTUW,
28662 IX86_BUILTIN_VPCOMLEUW,
28663 IX86_BUILTIN_VPCOMGTUW,
28664 IX86_BUILTIN_VPCOMGEUW,
28665 IX86_BUILTIN_VPCOMFALSEUW,
28666 IX86_BUILTIN_VPCOMTRUEUW,
28668 IX86_BUILTIN_VPCOMEQUD,
28669 IX86_BUILTIN_VPCOMNEUD,
28670 IX86_BUILTIN_VPCOMLTUD,
28671 IX86_BUILTIN_VPCOMLEUD,
28672 IX86_BUILTIN_VPCOMGTUD,
28673 IX86_BUILTIN_VPCOMGEUD,
28674 IX86_BUILTIN_VPCOMFALSEUD,
28675 IX86_BUILTIN_VPCOMTRUEUD,
28677 IX86_BUILTIN_VPCOMEQUQ,
28678 IX86_BUILTIN_VPCOMNEUQ,
28679 IX86_BUILTIN_VPCOMLTUQ,
28680 IX86_BUILTIN_VPCOMLEUQ,
28681 IX86_BUILTIN_VPCOMGTUQ,
28682 IX86_BUILTIN_VPCOMGEUQ,
28683 IX86_BUILTIN_VPCOMFALSEUQ,
28684 IX86_BUILTIN_VPCOMTRUEUQ,
28686 IX86_BUILTIN_VPCOMEQB,
28687 IX86_BUILTIN_VPCOMNEB,
28688 IX86_BUILTIN_VPCOMLTB,
28689 IX86_BUILTIN_VPCOMLEB,
28690 IX86_BUILTIN_VPCOMGTB,
28691 IX86_BUILTIN_VPCOMGEB,
28692 IX86_BUILTIN_VPCOMFALSEB,
28693 IX86_BUILTIN_VPCOMTRUEB,
28695 IX86_BUILTIN_VPCOMEQW,
28696 IX86_BUILTIN_VPCOMNEW,
28697 IX86_BUILTIN_VPCOMLTW,
28698 IX86_BUILTIN_VPCOMLEW,
28699 IX86_BUILTIN_VPCOMGTW,
28700 IX86_BUILTIN_VPCOMGEW,
28701 IX86_BUILTIN_VPCOMFALSEW,
28702 IX86_BUILTIN_VPCOMTRUEW,
28704 IX86_BUILTIN_VPCOMEQD,
28705 IX86_BUILTIN_VPCOMNED,
28706 IX86_BUILTIN_VPCOMLTD,
28707 IX86_BUILTIN_VPCOMLED,
28708 IX86_BUILTIN_VPCOMGTD,
28709 IX86_BUILTIN_VPCOMGED,
28710 IX86_BUILTIN_VPCOMFALSED,
28711 IX86_BUILTIN_VPCOMTRUED,
28713 IX86_BUILTIN_VPCOMEQQ,
28714 IX86_BUILTIN_VPCOMNEQ,
28715 IX86_BUILTIN_VPCOMLTQ,
28716 IX86_BUILTIN_VPCOMLEQ,
28717 IX86_BUILTIN_VPCOMGTQ,
28718 IX86_BUILTIN_VPCOMGEQ,
28719 IX86_BUILTIN_VPCOMFALSEQ,
28720 IX86_BUILTIN_VPCOMTRUEQ,
28722 /* LWP instructions. */
28723 IX86_BUILTIN_LLWPCB,
28724 IX86_BUILTIN_SLWPCB,
28725 IX86_BUILTIN_LWPVAL32,
28726 IX86_BUILTIN_LWPVAL64,
28727 IX86_BUILTIN_LWPINS32,
28728 IX86_BUILTIN_LWPINS64,
28730 IX86_BUILTIN_CLZS,
28732 /* RTM */
28733 IX86_BUILTIN_XBEGIN,
28734 IX86_BUILTIN_XEND,
28735 IX86_BUILTIN_XABORT,
28736 IX86_BUILTIN_XTEST,
28738 /* BMI instructions. */
28739 IX86_BUILTIN_BEXTR32,
28740 IX86_BUILTIN_BEXTR64,
28741 IX86_BUILTIN_CTZS,
28743 /* TBM instructions. */
28744 IX86_BUILTIN_BEXTRI32,
28745 IX86_BUILTIN_BEXTRI64,
28747 /* BMI2 instructions. */
28748 IX86_BUILTIN_BZHI32,
28749 IX86_BUILTIN_BZHI64,
28750 IX86_BUILTIN_PDEP32,
28751 IX86_BUILTIN_PDEP64,
28752 IX86_BUILTIN_PEXT32,
28753 IX86_BUILTIN_PEXT64,
28755 /* ADX instructions. */
28756 IX86_BUILTIN_ADDCARRYX32,
28757 IX86_BUILTIN_ADDCARRYX64,
28759 /* FSGSBASE instructions. */
28760 IX86_BUILTIN_RDFSBASE32,
28761 IX86_BUILTIN_RDFSBASE64,
28762 IX86_BUILTIN_RDGSBASE32,
28763 IX86_BUILTIN_RDGSBASE64,
28764 IX86_BUILTIN_WRFSBASE32,
28765 IX86_BUILTIN_WRFSBASE64,
28766 IX86_BUILTIN_WRGSBASE32,
28767 IX86_BUILTIN_WRGSBASE64,
28769 /* RDRND instructions. */
28770 IX86_BUILTIN_RDRAND16_STEP,
28771 IX86_BUILTIN_RDRAND32_STEP,
28772 IX86_BUILTIN_RDRAND64_STEP,
28774 /* RDSEED instructions. */
28775 IX86_BUILTIN_RDSEED16_STEP,
28776 IX86_BUILTIN_RDSEED32_STEP,
28777 IX86_BUILTIN_RDSEED64_STEP,
28779 /* F16C instructions. */
28780 IX86_BUILTIN_CVTPH2PS,
28781 IX86_BUILTIN_CVTPH2PS256,
28782 IX86_BUILTIN_CVTPS2PH,
28783 IX86_BUILTIN_CVTPS2PH256,
28785 /* CFString built-in for darwin */
28786 IX86_BUILTIN_CFSTRING,
28788 /* Builtins to get CPU type and supported features. */
28789 IX86_BUILTIN_CPU_INIT,
28790 IX86_BUILTIN_CPU_IS,
28791 IX86_BUILTIN_CPU_SUPPORTS,
28793 /* Read/write FLAGS register built-ins. */
28794 IX86_BUILTIN_READ_FLAGS,
28795 IX86_BUILTIN_WRITE_FLAGS,
28797 IX86_BUILTIN_MAX
28798 };
28800 /* Table for the ix86 builtin decls. */
28803 /* Table of all of the builtin functions that are possible with different ISA's
28804 but are waiting to be built until a function is declared to use that
28805 ISA. */
28812 };
28817 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
28818 of which isa_flags to use in the ix86_builtins_isa array. Stores the
28819 function decl in the ix86_builtins array. Returns the function decl or
28820 NULL_TREE, if the builtin was not added.
28822 If the front end has a special hook for builtin functions, delay adding
28823 builtin functions that aren't in the current ISA until the ISA is changed
28824 with function specific optimization. Doing so, can save about 300K for the
28825 default compiler. When the builtin is expanded, check at that time whether
28826 it is valid.
28828 If the front end doesn't have a special hook, record all builtins, even if
28829 it isn't an instruction set in the current ISA in case the user uses
28830 function specific options for a different ISA, so that we don't get scope
28831 errors if a builtin is added in the middle of a function scope. */
28837 {
28841 {
28850 {
28856 }
28857 else
28858 {
28864 }
28865 }
28868 }
28870 /* Like def_builtin, but also marks the function decl "const". */
28875 {
28879 else
28883 }
28885 /* Add any new builtin functions for a given ISA that may not have been
28886 declared. This saves a bit of space compared to adding all of the
28887 declarations to the tree, even if we didn't use them. */
28889 static void
28891 {
28895 {
28898 {
28901 /* Don't define the builtin again. */
28907 NULL_TREE);
28912 }
28913 }
28914 }
28916 /* Bits for builtin_description.flag. */
28918 /* Set when we don't support the comparison natively, and should
28919 swap_comparison in order to support it. */
28920 #define BUILTIN_DESC_SWAP_OPERANDS 1
28922 struct builtin_description
28923 {
28930 };
28933 {
28934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
28935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
28936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
28937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
28938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
28939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
28940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
28941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
28942 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
28943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
28944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
28945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
28946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
28947 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
28948 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
28949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
28950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
28951 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
28952 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
28953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
28954 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
28955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
28956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
28957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
28958 };
28961 {
28962 /* SSE4.2 */
28963 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
28964 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
28965 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
28966 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
28967 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
28968 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
28969 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
28970 };
28973 {
28974 /* SSE4.2 */
28975 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
28976 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
28977 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
28978 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
28979 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
28980 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
28981 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
28982 };
28984 /* Special builtins with variable number of arguments. */
28986 {
28987 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
28988 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
28989 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
28991 /* 80387 (for use internally for atomic compound assignment). */
28992 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
28993 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
28994 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
28995 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
28997 /* MMX */
28998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29000 /* 3DNow! */
29001 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29003 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
29004 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29005 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29006 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29007 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29008 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29009 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29010 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29011 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29013 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29014 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29015 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29016 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29017 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29018 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29019 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29020 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29022 /* SSE */
29023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29029 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29030 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29032 /* SSE or 3DNow!A */
29033 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29034 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29036 /* SSE2 */
29037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29044 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29051 /* SSE3 */
29052 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29054 /* SSE4.1 */
29055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29057 /* SSE4A */
29058 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29059 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29061 /* AVX */
29062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29065 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29066 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29067 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29085 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29086 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29087 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29088 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29089 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29090 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29092 /* AVX2 */
29093 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29094 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29095 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29096 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29097 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29098 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29099 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29100 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29101 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29103 /* AVX512F */
29104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29152 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29153 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29154 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29155 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29156 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29157 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29159 /* FSGSBASE */
29160 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29161 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29162 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29163 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29164 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29165 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29166 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29167 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29169 /* RTM */
29170 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29171 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29172 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29173 };
29175 /* Builtins with variable number of arguments. */
29177 {
29178 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29179 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29180 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29181 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29182 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29183 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29184 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29186 /* MMX */
29187 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29188 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29189 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29190 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29191 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29192 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29194 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29196 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29197 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29198 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29199 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29200 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29201 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29203 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29204 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29206 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29207 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29208 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29209 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29211 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29212 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29213 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29214 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29218 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29248 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29250 /* 3DNow! */
29251 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29252 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29253 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29254 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29256 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29257 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29258 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29259 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29260 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29261 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29262 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29263 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29264 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29265 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29266 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29267 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29268 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29269 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29270 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29272 /* 3DNow!A */
29273 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29274 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29275 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29276 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29277 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29278 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29280 /* SSE */
29281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29282 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29283 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29285 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29286 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29287 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29288 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29290 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29291 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29294 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29296 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29297 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29298 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29299 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29300 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29301 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29315 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29317 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29318 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29321 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29323 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29326 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29327 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29331 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29333 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29334 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29336 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29341 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29342 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29346 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29348 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29352 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29354 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29355 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29357 /* SSE MMX or 3Dnow!A */
29358 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29359 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29360 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29362 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29363 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29364 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29365 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29367 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29368 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29370 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29372 /* SSE2 */
29373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29375 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29379 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29391 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29392 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29396 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29398 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29399 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29400 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29401 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29429 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29433 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29435 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29436 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29438 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29441 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29442 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29444 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29446 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29447 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29448 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29449 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29450 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29451 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29452 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29453 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29464 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29465 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29467 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29469 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29470 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29482 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29483 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29484 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29487 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29488 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29489 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29490 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29491 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29492 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29493 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29494 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29500 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29504 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29509 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29514 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29515 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29516 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29517 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29518 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29519 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29522 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29523 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29524 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29525 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29526 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29527 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29529 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29530 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29531 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29532 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29540 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29542 /* SSE2 MMX */
29543 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29544 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29546 /* SSE3 */
29547 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29548 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29550 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29551 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29552 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29553 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29554 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29555 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29557 /* SSSE3 */
29558 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29559 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29560 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29561 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29562 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29563 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29565 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29566 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29567 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29568 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29569 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29570 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29571 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29572 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29573 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29574 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29575 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29576 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29577 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29578 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29579 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29580 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29581 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29582 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29583 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29584 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29585 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29586 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29587 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29588 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29590 /* SSSE3. */
29591 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29592 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29594 /* SSE4.1 */
29595 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29596 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29597 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29598 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29599 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29600 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29601 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29602 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29603 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29604 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29606 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29607 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29608 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29609 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29610 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29611 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29612 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29613 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29614 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29615 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29617 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29618 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29620 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29621 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29623 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29624 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29625 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29626 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29627 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29628 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29629 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29630 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29631 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29633 /* SSE4.1 */
29634 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29635 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29636 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29637 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29639 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29640 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29641 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29642 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29644 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29645 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29647 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29648 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29650 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29651 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29652 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29653 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29655 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29656 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29658 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29659 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29661 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29662 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29663 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29665 /* SSE4.2 */
29666 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29667 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29668 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29669 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29670 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29672 /* SSE4A */
29673 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29674 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29675 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29676 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29678 /* AES */
29679 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29680 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29682 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29683 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29684 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29685 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29687 /* PCLMUL */
29688 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29690 /* AVX */
29691 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29692 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29695 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29696 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29699 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29705 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29706 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29707 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29708 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29709 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29710 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29711 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29712 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29713 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29714 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29715 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29716 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29739 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29740 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29744 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29746 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29762 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29764 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29766 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
29774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
29775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
29776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
29778 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29779 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
29784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
29785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
29786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
29787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
29789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
29790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
29792 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29793 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29803 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
29804 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
29805 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
29807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
29810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
29813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
29816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
29819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
29823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
29824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
29826 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29827 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29829 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
29831 /* AVX2 */
29832 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
29833 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
29834 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
29835 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
29836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
29839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
29840 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29841 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29842 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29843 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29845 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29846 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29847 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29848 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
29849 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29850 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29851 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29852 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29853 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
29854 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
29855 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29856 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29857 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29858 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
29871 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29872 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29873 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29874 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29875 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29876 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29877 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29878 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29879 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29880 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29881 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29882 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
29884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
29891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
29892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
29893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
29894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
29895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
29896 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29898 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29899 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29900 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29901 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29902 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
29903 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
29905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
29907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
29909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29911 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29912 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29913 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29914 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29915 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29916 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29917 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29918 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29919 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29920 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29921 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29922 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
29924 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
29925 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
29926 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
29927 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
29928 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
29929 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
29930 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29931 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29932 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29933 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
29943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
29944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29946 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
29949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
29950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
29952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
29954 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
29955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
29956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
29957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
29965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
29966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
29967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
29968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29969 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29970 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29973 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29974 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
29975 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29976 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
29977 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29979 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29981 /* BMI */
29982 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29983 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29984 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
29986 /* TBM */
29987 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29988 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29990 /* F16C */
29991 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
29992 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
29993 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
29994 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
29996 /* BMI2 */
29997 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29998 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29999 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30000 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30001 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30002 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30004 /* AVX512F */
30005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30054 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30055 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30057 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30058 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30166 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30167 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30168 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30169 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30201 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30206 /* Mask arithmetic operations */
30207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30218 /* SHA */
30219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30226 };
30228 /* Builtins with rounding support. */
30230 {
30231 /* AVX512F */
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30251 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30253 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30260 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30262 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30312 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30314 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30316 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30318 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30320 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30322 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30324 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30326 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30350 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30352 /* AVX512ER */
30353 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30354 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30355 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30356 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30357 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30358 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30359 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30360 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30361 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30362 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30363 };
30365 /* FMA4 and XOP. */
30366 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30367 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30368 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30369 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30370 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30371 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30372 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30373 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30374 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30375 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30376 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30377 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30378 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30379 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30380 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30381 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30382 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30383 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30384 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30385 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30386 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30387 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30388 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30389 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30390 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30391 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30392 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30393 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30394 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30395 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30396 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30397 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30398 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30399 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30400 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30401 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30402 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30403 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30404 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30405 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30406 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30407 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30408 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30409 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30410 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30411 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30412 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30413 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30414 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30415 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30416 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30417 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30420 {
30461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30619 };
30620 \f
30621 /* TM vector builtins. */
30623 /* Reuse the existing x86-specific `struct builtin_description' cause
30624 we're lazy. Add casts to make them fit. */
30626 {
30627 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30628 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30629 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30630 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30631 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30632 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30633 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30635 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30636 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30637 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30638 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30639 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30640 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30641 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30643 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30644 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30645 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30646 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30647 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30648 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30649 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30651 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30652 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30653 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30654 };
30656 /* TM callbacks. */
30658 /* Return the builtin decl needed to load a vector of TYPE. */
30660 static tree
30662 {
30664 {
30666 {
30673 }
30674 }
30676 }
30678 /* Return the builtin decl needed to store a vector of TYPE. */
30680 static tree
30682 {
30684 {
30686 {
30693 }
30694 }
30696 }
30697 \f
30698 /* Initialize the transactional memory vector load/store builtins. */
30700 static void
30702 {
30706 tree decl;
30713 /* If there are no builtins defined, we must be compiling in a
30714 language without trans-mem support. */
30718 /* Use whatever attributes a normal TM load has. */
30722 /* Use whatever attributes a normal TM store has. */
30726 /* Use whatever attributes a normal TM log has. */
30734 {
30738 {
30746 {
30749 }
30751 {
30754 }
30755 else
30756 {
30759 }
30761 /* The builtin without the prefix for
30762 calling it directly. */
30764 attrs);
30765 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
30766 set the TYPE_ATTRIBUTES. */
30770 }
30771 }
30772 }
30774 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
30775 in the current target ISA to allow the user to compile particular modules
30776 with different target specific options that differ from the command line
30777 options. */
30778 static void
30780 {
30785 /* Add all special builtins with variable number of operands. */
30789 {
30795 }
30797 /* Add all builtins with variable number of operands. */
30801 {
30807 }
30809 /* Add all builtins with rounding. */
30813 {
30819 }
30821 /* pcmpestr[im] insns. */
30825 {
30828 else
30831 }
30833 /* pcmpistr[im] insns. */
30837 {
30840 else
30843 }
30845 /* comi/ucomi insns. */
30847 {
30850 else
30853 }
30855 /* SSE */
30861 /* SSE or 3DNow!A */
30864 IX86_BUILTIN_MASKMOVQ);
30866 /* SSE2 */
30875 /* SSE3. */
30881 /* AES */
30895 /* PCLMUL */
30899 /* RDRND */
30906 IX86_BUILTIN_RDRAND64_STEP);
30908 /* AVX2 */
30910 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
30911 IX86_BUILTIN_GATHERSIV2DF);
30914 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
30915 IX86_BUILTIN_GATHERSIV4DF);
30918 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
30919 IX86_BUILTIN_GATHERDIV2DF);
30922 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
30923 IX86_BUILTIN_GATHERDIV4DF);
30926 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
30927 IX86_BUILTIN_GATHERSIV4SF);
30930 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
30931 IX86_BUILTIN_GATHERSIV8SF);
30934 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
30935 IX86_BUILTIN_GATHERDIV4SF);
30938 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
30939 IX86_BUILTIN_GATHERDIV8SF);
30942 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
30943 IX86_BUILTIN_GATHERSIV2DI);
30946 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
30947 IX86_BUILTIN_GATHERSIV4DI);
30950 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
30951 IX86_BUILTIN_GATHERDIV2DI);
30954 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
30955 IX86_BUILTIN_GATHERDIV4DI);
30958 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
30959 IX86_BUILTIN_GATHERSIV4SI);
30962 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
30963 IX86_BUILTIN_GATHERSIV8SI);
30966 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
30967 IX86_BUILTIN_GATHERDIV4SI);
30970 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
30971 IX86_BUILTIN_GATHERDIV8SI);
30974 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
30975 IX86_BUILTIN_GATHERALTSIV4DF);
30978 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
30979 IX86_BUILTIN_GATHERALTDIV8SF);
30982 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
30983 IX86_BUILTIN_GATHERALTSIV4DI);
30986 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
30987 IX86_BUILTIN_GATHERALTDIV8SI);
30989 /* AVX512F */
30991 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
30992 IX86_BUILTIN_GATHER3SIV16SF);
30995 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
30996 IX86_BUILTIN_GATHER3SIV8DF);
30999 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
31000 IX86_BUILTIN_GATHER3DIV16SF);
31003 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31004 IX86_BUILTIN_GATHER3DIV8DF);
31007 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31008 IX86_BUILTIN_GATHER3SIV16SI);
31011 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31012 IX86_BUILTIN_GATHER3SIV8DI);
31015 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31016 IX86_BUILTIN_GATHER3DIV16SI);
31019 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31020 IX86_BUILTIN_GATHER3DIV8DI);
31023 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31024 IX86_BUILTIN_GATHER3ALTSIV8DF);
31027 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31028 IX86_BUILTIN_GATHER3ALTDIV16SF);
31031 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31032 IX86_BUILTIN_GATHER3ALTSIV8DI);
31035 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31036 IX86_BUILTIN_GATHER3ALTDIV16SI);
31039 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31040 IX86_BUILTIN_SCATTERSIV16SF);
31043 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31044 IX86_BUILTIN_SCATTERSIV8DF);
31047 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31048 IX86_BUILTIN_SCATTERDIV16SF);
31051 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31052 IX86_BUILTIN_SCATTERDIV8DF);
31055 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31056 IX86_BUILTIN_SCATTERSIV16SI);
31059 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31060 IX86_BUILTIN_SCATTERSIV8DI);
31063 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31064 IX86_BUILTIN_SCATTERDIV16SI);
31067 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31068 IX86_BUILTIN_SCATTERDIV8DI);
31070 /* AVX512PF */
31072 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31073 IX86_BUILTIN_GATHERPFDPD);
31075 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31076 IX86_BUILTIN_GATHERPFDPS);
31078 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31079 IX86_BUILTIN_GATHERPFQPD);
31081 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31082 IX86_BUILTIN_GATHERPFQPS);
31084 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31085 IX86_BUILTIN_SCATTERPFDPD);
31087 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31088 IX86_BUILTIN_SCATTERPFDPS);
31090 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31091 IX86_BUILTIN_SCATTERPFQPD);
31093 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31094 IX86_BUILTIN_SCATTERPFQPS);
31096 /* SHA */
31112 /* RTM. */
31116 /* MMX access to the vec_init patterns. */
31121 V4HI_FTYPE_HI_HI_HI_HI,
31122 IX86_BUILTIN_VEC_INIT_V4HI);
31125 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31126 IX86_BUILTIN_VEC_INIT_V8QI);
31128 /* Access to the vec_extract patterns. */
31150 /* Access to the vec_set patterns. */
31171 /* RDSEED */
31180 /* ADCX */
31185 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31186 IX86_BUILTIN_ADDCARRYX64);
31188 /* Read/write FLAGS. */
31198 /* CLFLUSHOPT. */
31202 /* Add FMA4 multi-arg argument instructions */
31204 {
31210 }
31211 }
31213 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31214 to return a pointer to VERSION_DECL if the outcome of the expression
31215 formed by PREDICATE_CHAIN is true. This function will be called during
31216 version dispatch to decide which function version to execute. It returns
31217 the basic block at the end, to which more conditions can be added. */
31219 static basic_block
31222 {
31223 gimple return_stmt;
31225 gimple convert_stmt;
31226 gimple call_cond_stmt;
31227 gimple if_else_stmt;
31233 gimple_seq gseq;
31250 {
31258 }
31261 {
31276 else
31277 {
31278 gimple assign_stmt;
31279 /* Use MIN_EXPR to check if any integer is zero?.
31280 and_expr_var = min_expr <cond_var, and_expr_var> */
31288 }
31289 }
31292 integer_zero_node,
31322 }
31324 /* This parses the attribute arguments to target in DECL and determines
31325 the right builtin to use to match the platform specification.
31326 It returns the priority value for this version decl. If PREDICATE_LIST
31327 is not NULL, it stores the list of cpu features that need to be checked
31328 before dispatching this function. */
31330 static unsigned int
31332 {
31333 tree attrs;
31335 tree target_node;
31342 /* Priority of i386 features, greater value is higher priority. This is
31343 used to decide the order in which function dispatch must happen. For
31344 instance, a version specialized for SSE4.2 should be checked for dispatch
31345 before a version for SSE3, as SSE4.2 implies SSE3. */
31346 enum feature_priority
31347 {
31349 P_MMX,
31350 P_SSE,
31351 P_SSE2,
31352 P_SSE3,
31353 P_SSSE3,
31354 P_PROC_SSSE3,
31355 P_SSE4_A,
31356 P_PROC_SSE4_A,
31357 P_SSE4_1,
31358 P_SSE4_2,
31359 P_PROC_SSE4_2,
31360 P_POPCNT,
31361 P_AVX,
31362 P_PROC_AVX,
31363 P_FMA4,
31364 P_XOP,
31365 P_PROC_XOP,
31366 P_FMA,
31367 P_PROC_FMA,
31368 P_AVX2,
31369 P_PROC_AVX2
31370 };
31374 /* These are the target attribute strings for which a dispatcher is
31375 available, from fold_builtin_cpu. */
31377 static struct _feature_list
31378 {
31381 }
31383 {
31398 };
31401 static unsigned int NUM_FEATURES
31417 /* Return priority zero for default function. */
31421 /* Handle arch= if specified. For priority, set it to be 1 more than
31422 the best instruction set the processor can handle. For instance, if
31423 there is a version for atom and a version for ssse3 (the highest ISA
31424 priority for atom), the atom version must be checked for dispatch
31425 before the ssse3 version. */
31427 {
31437 {
31439 {
31447 else
31448 /* We translate "arch=corei7" and "arch=nehalem" to
31449 "corei7" so that it will be mapped to M_INTEL_COREI7
31450 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31457 else
31464 else
31504 }
31505 }
31510 {
31514 }
31517 {
31519 /* For a C string literal the length includes the trailing NULL. */
31522 predicate_chain);
31523 }
31524 }
31526 /* Process feature name. */
31533 {
31534 /* Do not process "arch=" */
31536 {
31539 }
31541 {
31543 {
31545 {
31550 predicate_chain);
31551 }
31552 /* Find the maximum priority feature. */
31557 }
31558 }
31560 {
31564 }
31566 }
31570 {
31573 attrs_str);
31575 }
31577 {
31580 }
31583 }
31585 /* This compares the priority of target features in function DECL1
31586 and DECL2. It returns positive value if DECL1 is higher priority,
31587 negative value if DECL2 is higher priority and 0 if they are the
31588 same. */
31590 static int
31592 {
31597 }
31599 /* V1 and V2 point to function versions with different priorities
31600 based on the target ISA. This function compares their priorities. */
31602 static int
31604 {
31606 {
31607 tree version_decl;
31608 tree predicate_chain;
31615 }
31617 /* This function generates the dispatch function for
31618 multi-versioned functions. DISPATCH_DECL is the function which will
31619 contain the dispatch logic. FNDECLS are the function choices for
31620 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31621 in DISPATCH_DECL in which the dispatch code is generated. */
31623 static int
31627 {
31628 tree default_decl;
31629 gimple ifunc_cpu_init_stmt;
31630 gimple_seq gseq;
31632 tree ele;
31638 struct _function_version_info
31639 {
31640 tree version_decl;
31641 tree predicate_chain;
31649 /*fndecls_p is actually a vector. */
31652 /* At least one more version other than the default. */
31659 /* The first version in the vector is the default decl. */
31665 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31666 constructors, so explicity call __builtin_cpu_init here. */
31677 {
31681 /* Get attribute string, parse it and find the right predicate decl.
31682 The predicate function could be a lengthy combination of many
31683 features, like arch-type and various isa-variants. */
31694 actual_versions++;
31695 }
31697 /* Sort the versions according to descending order of dispatch priority. The
31698 priority is based on the ISA. This is not a perfect solution. There
31699 could still be ambiguity. If more than one function version is suitable
31700 to execute, which one should be dispatched? In future, allow the user
31701 to specify a dispatch priority next to the version. */
31711 /* dispatch default version at the end. */
31717 }
31719 /* Comparator function to be used in qsort routine to sort attribute
31720 specification strings to "target". */
31722 static int
31724 {
31728 }
31730 /* ARGLIST is the argument to target attribute. This function tokenizes
31731 the comma separated arguments, sorts them and returns a string which
31732 is a unique identifier for the comma separated arguments. It also
31733 replaces non-identifier characters "=,-" with "_". */
31737 {
31738 tree arg;
31747 {
31752 argnum++;
31755 argnum++;
31756 }
31761 {
31767 }
31769 /* Replace "=,-" with "_". */
31782 {
31784 i++;
31786 }
31793 {
31798 }
31803 }
31805 /* This function changes the assembler name for functions that are
31806 versions. If DECL is a function version and has a "target"
31807 attribute, it appends the attribute string to its assembler name. */
31809 static tree
31811 {
31812 tree version_attr;
31820 "Function versions cannot be marked as gnu_inline,"
31829 /* target attribute string cannot be NULL. */
31833 version_string
31844 /* Allow assembler name to be modified if already set. */
31852 }
31854 /* This function returns true if FN1 and FN2 are versions of the same function,
31855 that is, the target strings of the function decls are different. This assumes
31856 that FN1 and FN2 have the same signature. */
31858 static bool
31860 {
31872 /* At least one function decl should have the target attribute specified. */
31876 /* Diagnose missing target attribute if one of the decls is already
31877 multi-versioned. */
31879 {
31881 {
31883 {
31888 }
31891 fn2);
31894 /* Prevent diagnosing of the same error multiple times. */
31899 }
31901 }
31906 /* The sorted target strings must be different for fn1 and fn2
31907 to be versions. */
31910 else
31917 }
31919 static tree
31921 {
31922 /* For function version, add the target suffix to the assembler name. */
31926 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
31928 #endif
31931 }
31933 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
31934 is true, append the full path name of the source file. */
31938 {
31946 /* Get a unique name that can be used globally without any chances
31947 of collision at link time. */
31957 /* Use '.' to concatenate names as it is demangler friendly. */
31960 suffix);
31961 else
31965 }
31967 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
31969 /* Make a dispatcher declaration for the multi-versioned function DECL.
31970 Calls to DECL function will be replaced with calls to the dispatcher
31971 by the front-end. Return the decl created. */
31973 static tree
31975 {
31976 tree func_decl;
31996 /* Mark this func as external, the resolver will flip it again if
31997 it gets generated. */
31999 /* This will be of type IFUNCs have to be externally visible. */
32003 }
32005 #endif
32007 /* Returns true if decl is multi-versioned and DECL is the default function,
32008 that is it is not tagged with target specific optimization. */
32010 static bool
32012 {
32021 }
32023 /* Make a dispatcher declaration for the multi-versioned function DECL.
32024 Calls to DECL function will be replaced with calls to the dispatcher
32025 by the front-end. Returns the decl of the dispatcher function. */
32027 static tree
32029 {
32051 /* Find the default version and make it the first node. */
32053 /* Go to the beginning of the chain. */
32058 {
32063 }
32065 /* If there is no default node, just return NULL. */
32069 /* Make default info the first node. */
32071 {
32078 }
32082 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32084 {
32089 /* Right now, the dispatching is done via ifunc. */
32095 dispatcher_version_info
32100 /* Set the dispatcher for all the versions. */
32103 {
32106 }
32107 }
32108 else
32109 #endif
32110 {
32112 "multiversioning needs ifunc which is not supported "
32114 }
32117 }
32119 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32120 it to CHAIN. */
32122 static tree
32124 {
32125 tree attr_name;
32126 tree attr_arg_name;
32127 tree attr_args;
32128 tree attr;
32135 }
32137 /* Make the resolver function decl to dispatch the versions of
32138 a multi-versioned function, DEFAULT_DECL. Create an
32139 empty basic block in the resolver and store the pointer in
32140 EMPTY_BB. Return the decl of the resolver function. */
32142 static tree
32146 {
32151 /* IFUNC's have to be globally visible. So, if the default_decl is
32152 not, then the name of the IFUNC should be made unique. */
32156 /* Append the filename to the resolver function if the versions are
32157 not externally visible. This is because the resolver function has
32158 to be externally visible for the loader to find it. So, appending
32159 the filename will prevent conflicts with a resolver function from
32160 another module which is based on the same version name. */
32163 /* The resolver function should return a (void *). */
32174 /* IFUNC resolvers have to be externally visible. */
32178 /* Resolver is not external, body is generated. */
32188 {
32189 /* In this case, each translation unit with a call to this
32190 versioned function will put out a resolver. Ensure it
32191 is comdat to keep just one copy. */
32194 }
32195 /* Build result decl and add to function_decl. */
32211 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32215 /* Create the alias for dispatch to resolver here. */
32216 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32220 }
32222 /* Generate the dispatching code body to dispatch multi-versioned function
32223 DECL. The target hook is called to process the "target" attributes and
32224 provide the code to dispatch the right function at run-time. NODE points
32225 to the dispatcher decl whose body will be created. */
32227 static tree
32229 {
32230 tree resolver_decl;
32231 basic_block empty_bb;
32232 tree default_ver_decl;
32248 /* The first version in the chain corresponds to the default version. */
32251 /* node is going to be an alias, so remove the finalized bit. */
32265 {
32267 /* Check for virtual functions here again, as by this time it should
32268 have been determined if this function needs a vtable index or
32269 not. This happens for methods in derived classes that override
32270 virtual methods in base classes but are not explicitly marked as
32271 virtual. */
32276 }
32282 }
32283 /* This builds the processor_model struct type defined in
32284 libgcc/config/i386/cpuinfo.c */
32286 static tree
32288 {
32295 /* The first 3 fields are unsigned int. */
32297 {
32303 }
32305 /* The last field is an array of unsigned integers of size one. */
32316 }
32318 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32320 static tree
32322 {
32323 tree new_decl;
32326 VAR_DECL,
32328 type);
32341 }
32343 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32344 into an integer defined in libgcc/config/i386/cpuinfo.c */
32346 static tree
32348 {
32354 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32355 enum processor_features
32356 {
32358 F_MMX,
32359 F_POPCNT,
32360 F_SSE,
32361 F_SSE2,
32362 F_SSE3,
32363 F_SSSE3,
32364 F_SSE4_1,
32365 F_SSE4_2,
32366 F_AVX,
32367 F_AVX2,
32368 F_SSE4_A,
32369 F_FMA4,
32370 F_XOP,
32371 F_FMA,
32372 F_MAX
32373 };
32375 /* These are the values for vendor types and cpu types and subtypes
32376 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32377 the corresponding start value. */
32378 enum processor_model
32379 {
32381 M_AMD,
32382 M_CPU_TYPE_START,
32383 M_INTEL_BONNELL,
32384 M_INTEL_CORE2,
32385 M_INTEL_COREI7,
32386 M_AMDFAM10H,
32387 M_AMDFAM15H,
32388 M_INTEL_SILVERMONT,
32389 M_AMD_BTVER1,
32390 M_AMD_BTVER2,
32391 M_CPU_SUBTYPE_START,
32392 M_INTEL_COREI7_NEHALEM,
32393 M_INTEL_COREI7_WESTMERE,
32394 M_INTEL_COREI7_SANDYBRIDGE,
32395 M_AMDFAM10H_BARCELONA,
32396 M_AMDFAM10H_SHANGHAI,
32397 M_AMDFAM10H_ISTANBUL,
32398 M_AMDFAM15H_BDVER1,
32399 M_AMDFAM15H_BDVER2,
32400 M_AMDFAM15H_BDVER3,
32401 M_AMDFAM15H_BDVER4,
32402 M_INTEL_COREI7_IVYBRIDGE,
32403 M_INTEL_COREI7_HASWELL
32404 };
32406 static struct _arch_names_table
32407 {
32410 }
32412 {
32437 };
32439 static struct _isa_names_table
32440 {
32443 }
32445 {
32461 };
32475 {
32476 /* *args must be a expr that can contain other EXPRS leading to a
32477 STRING_CST. */
32479 {
32482 }
32484 }
32489 {
32490 tree ref;
32491 tree field;
32492 tree final;
32495 unsigned int NUM_ARCH_NAMES
32504 {
32508 }
32513 /* CPU types are stored in the next field. */
32516 {
32519 }
32521 /* CPU subtypes are stored in the next field. */
32523 {
32526 }
32528 /* Get the appropriate field in __cpu_model. */
32532 /* Check the value. */
32536 }
32538 {
32539 tree ref;
32540 tree array_elt;
32541 tree field;
32542 tree final;
32545 unsigned int NUM_ISA_NAMES
32554 {
32558 }
32561 /* Get the last field, which is __cpu_features. */
32565 /* Get the appropriate field: __cpu_model.__cpu_features */
32569 /* Access the 0th element of __cpu_features array. */
32574 /* Return __cpu_model.__cpu_features[0] & field_val */
32578 }
32580 }
32582 static tree
32585 {
32587 {
32592 {
32595 }
32596 }
32598 #ifdef SUBTARGET_FOLD_BUILTIN
32600 #endif
32603 }
32605 /* Make builtins to detect cpu type and features supported. NAME is
32606 the builtin name, CODE is the builtin code, and FTYPE is the function
32607 type of the builtin. */
32609 static void
32612 {
32613 tree decl;
32614 tree type;
32622 }
32624 /* Make builtins to get CPU type and features supported. The created
32625 builtins are :
32627 __builtin_cpu_init (), to detect cpu type and features,
32628 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32629 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32630 */
32632 static void
32634 {
32641 }
32643 /* Internal method for ix86_init_builtins. */
32645 static void
32647 {
32659 sysv_va_ref =
32662 fnvoid_va_end_ms =
32664 fnvoid_va_start_ms =
32666 fnvoid_va_end_sysv =
32668 fnvoid_va_start_sysv =
32670 NULL_TREE);
32671 fnvoid_va_copy_ms =
32673 NULL_TREE);
32674 fnvoid_va_copy_sysv =
32690 }
32692 static void
32694 {
32697 /* The __float80 type. */
32700 {
32701 /* The __float80 type. */
32706 }
32709 /* The __float128 type. */
32715 /* This macro is built by i386-builtin-types.awk. */
32716 DEFINE_BUILTIN_PRIMITIVE_TYPES;
32717 }
32719 static void
32721 {
32722 tree t;
32726 /* Builtins to get CPU type and features. */
32729 /* TFmode support builtins. */
32735 /* We will expand them to normal call if SSE isn't available since
32736 they are used by libgcc. */
32755 #ifdef SUBTARGET_INIT_BUILTINS
32756 SUBTARGET_INIT_BUILTINS;
32757 #endif
32758 }
32760 /* Return the ix86 builtin for CODE. */
32762 static tree
32764 {
32769 }
32771 /* Errors in the source file can cause expand_expr to return const0_rtx
32772 where we expect a vector. To avoid crashing, use one of the vector
32773 clear instructions. */
32774 static rtx
32776 {
32780 }
32782 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
32784 static rtx
32786 {
32787 rtx pat;
32807 {
32811 }
32825 }
32827 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
32829 static rtx
32833 {
32834 rtx pat;
32842 rtx op;
32849 {
32929 }
32939 {
32946 {
32948 {
32951 {
32969 xop_rotl:
32971 {
32974 gcc_checking_assert
32976 }
32977 else
32978 {
32979 gcc_checking_assert
32990 }
32994 }
32995 }
32996 }
32997 else
32998 {
32999 non_constant:
33003 /* If we aren't optimizing, only allow one memory operand to be
33004 generated. */
33006 num_memory++;
33014 }
33018 }
33021 {
33032 else
33033 {
33039 }
33052 }
33059 }
33061 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33062 insns with vec_merge. */
33064 static rtx
33066 rtx target)
33067 {
33068 rtx pat;
33095 }
33097 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33099 static rtx
33102 {
33103 rtx pat;
33108 rtx op2;
33119 /* Swap operands if we have a comparison that isn't available in
33120 hardware. */
33122 {
33127 }
33147 }
33149 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33151 static rtx
33153 rtx target)
33154 {
33155 rtx pat;
33169 /* Swap operands if we have a comparison that isn't available in
33170 hardware. */
33172 {
33176 }
33197 const0_rtx)));
33200 }
33202 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33204 static rtx
33206 rtx target)
33207 {
33208 rtx pat;
33233 }
33235 static rtx
33238 {
33239 rtx pat;
33244 rtx op2;
33271 }
33273 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33275 static rtx
33277 rtx target)
33278 {
33279 rtx pat;
33312 const0_rtx)));
33315 }
33317 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33319 static rtx
33322 {
33323 rtx pat;
33361 {
33364 }
33367 {
33376 }
33378 {
33387 }
33388 else
33389 {
33396 }
33404 {
33409 emit_insn
33413 FLAGS_REG),
33414 const0_rtx)));
33416 }
33417 else
33419 }
33422 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33424 static rtx
33427 {
33428 rtx pat;
33456 {
33459 }
33462 {
33471 }
33473 {
33482 }
33483 else
33484 {
33491 }
33499 {
33504 emit_insn
33508 FLAGS_REG),
33509 const0_rtx)));
33511 }
33512 else
33514 }
33516 /* Subroutine of ix86_expand_builtin to take care of insns with
33517 variable number of operands. */
33519 static rtx
33522 {
33528 struct
33529 {
33530 rtx op;
33542 {
33990 }
33995 {
33998 }
34001 {
34008 }
34009 else
34010 {
34013 }
34016 {
34023 {
34024 /* SIMD shift insns take either an 8-bit immediate or
34025 register as count. But builtin functions take int as
34026 count. If count doesn't match, we put it in register. */
34028 {
34032 }
34033 }
34036 {
34039 {
34115 {
34119 {
34122 }
34128 }
34130 }
34131 }
34132 else
34133 {
34137 /* If we aren't optimizing, only allow one memory operand to
34138 be generated. */
34140 num_memory++;
34143 {
34146 }
34147 else
34148 {
34151 }
34152 }
34156 }
34159 {
34184 }
34191 }
34193 /* Transform pattern of following layout:
34194 (parallel [
34195 set (A B)
34196 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34197 ])
34198 into:
34199 (set (A B))
34201 Or:
34202 (parallel [ A B
34203 ...
34204 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34205 ...
34206 ])
34207 into:
34208 (parallel [ A B ... ]) */
34210 static rtx
34212 {
34219 {
34228 }
34229 else
34230 {
34236 {
34241 }
34243 /* No more than 1 occurence was removed. */
34247 }
34248 }
34250 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34251 with rounding. */
34252 static rtx
34255 {
34272 /* See avxintrin.h for values. */
34274 {
34278 };
34280 {
34285 };
34288 {
34291 }
34293 {
34296 }
34299 {
34302 }
34325 ? CODE_FOR_sse_ucomi_round
34332 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34334 {
34340 }
34341 else
34342 {
34345 }
34351 set_dst,
34352 const0_rtx)));
34355 }
34357 static rtx
34360 {
34361 rtx pat;
34363 struct
34364 {
34365 rtx op;
34375 {
34452 }
34462 {
34469 {
34471 {
34473 {
34489 }
34490 }
34491 }
34493 {
34495 {
34498 }
34500 /* If there is no rounding use normal version of the pattern. */
34503 }
34504 else
34505 {
34510 {
34513 }
34514 else
34515 {
34518 }
34519 }
34523 }
34526 {
34551 }
34561 }
34563 /* Subroutine of ix86_expand_builtin to take care of special insns
34564 with variable number of operands. */
34566 static rtx
34569 {
34570 tree arg;
34574 struct
34575 {
34576 rtx op;
34586 {
34625 {
34633 }
34652 /* Reserve memory operand for target. */
34655 {
34656 /* These builtins and instructions require the memory
34657 to be properly aligned. */
34676 }
34701 {
34702 /* These builtins and instructions require the memory
34703 to be properly aligned. */
34712 }
34713 /* FALLTHRU */
34731 /* Reserve memory operand for target. */
34744 {
34745 /* These builtins and instructions require the memory
34746 to be properly aligned. */
34755 }
34768 }
34773 {
34778 {
34781 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
34782 on it. Try to improve it using get_pointer_alignment,
34783 and if the special builtin is one that requires strict
34784 mode alignment, also from it's GET_MODE_ALIGNMENT.
34785 Failure to do so could lead to ix86_legitimate_combined_insn
34786 rejecting all changes to such insns. */
34792 }
34793 else
34796 }
34797 else
34798 {
34805 }
34808 {
34817 {
34819 {
34825 else
34828 }
34829 }
34830 else
34831 {
34833 {
34834 /* This must be the memory operand. */
34837 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
34838 on it. Try to improve it using get_pointer_alignment,
34839 and if the special builtin is one that requires strict
34840 mode alignment, also from it's GET_MODE_ALIGNMENT.
34841 Failure to do so could lead to ix86_legitimate_combined_insn
34842 rejecting all changes to such insns. */
34848 }
34849 else
34850 {
34851 /* This must be register. */
34857 else
34858 {
34861 }
34862 }
34863 }
34867 }
34870 {
34885 }
34891 }
34893 /* Return the integer constant in ARG. Constrain it to be in the range
34894 of the subparts of VEC_TYPE; issue an error if not. */
34896 static int
34898 {
34903 {
34906 }
34909 }
34911 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34912 ix86_expand_vector_init. We DO have language-level syntax for this, in
34913 the form of (type){ init-list }. Except that since we can't place emms
34914 instructions from inside the compiler, we can't allow the use of MMX
34915 registers unless the user explicitly asks for it. So we do *not* define
34916 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
34917 we have builtins invoked by mmintrin.h that gives us license to emit
34918 these sorts of instructions. */
34920 static rtx
34922 {
34932 {
34935 }
34942 }
34944 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34945 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
34946 had a language-level syntax for referencing vector elements. */
34948 static rtx
34950 {
34954 rtx op0;
34974 }
34976 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
34977 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
34978 a language-level syntax for referencing vector elements. */
34980 static rtx
34982 {
35006 /* OP0 is the source of these builtin functions and shouldn't be
35007 modified. Create a copy, use it and return it as target. */
35013 }
35015 /* Expand an expression EXP that calls a built-in function,
35016 with result going to TARGET if that's convenient
35017 (and in mode MODE if that's convenient).
35018 SUBTARGET may be used as the target for computing one of EXP's operands.
35019 IGNORE is nonzero if the value is to be ignored. */
35021 static rtx
35024 {
35034 /* For CPU builtins that can be folded, fold first and expand the fold. */
35036 {
35038 {
35039 /* Make it call __cpu_indicator_init in libgcc. */
35045 }
35048 {
35053 }
35054 }
35056 /* Determine whether the builtin function is available under the current ISA.
35057 Originally the builtin was not created if it wasn't applicable to the
35058 current ISA based on the command line switches. With function specific
35059 options, we need to check in the context of the function making the call
35060 whether it is supported. */
35063 {
35069 else
35070 {
35074 }
35076 }
35079 {
35083 ? CODE_FOR_mmx_maskmovq
35085 /* Note the arg order is different from the operand order. */
35196 {
35197 REAL_VALUE_TYPE inf;
35198 rtx tmp;
35210 }
35220 {
35226 insn = (TARGET_64BIT
35230 }
35232 {
35233 insn = (TARGET_64BIT
35237 }
35238 else
35239 {
35242 insn = (TARGET_64BIT
35250 {
35253 }
35255 }
35258 {
35259 /* mode is VOIDmode if __builtin_rd* has been called
35260 without lhs. */
35264 }
35267 {
35272 }
35286 {
35311 }
35317 {
35320 }
35346 {
35349 }
35355 {
35359 {
35398 }
35403 }
35404 else
35405 {
35407 {
35428 }
35430 }
35460 ? CODE_FOR_tbm_bextri_si
35463 {
35466 }
35467 else
35468 {
35477 }
35493 rdrand_step:
35500 {
35503 }
35509 /* Emit SImode conditional move. */
35511 {
35514 }
35517 else
35525 const0_rtx);
35544 rdseed_step:
35551 {
35554 }
35560 const0_rtx);
35579 addcarryx:
35587 /* Generate CF from input operand. */
35592 /* Gen ADCX instruction to compute X+Y+CF. */
35607 /* Store the result. */
35610 {
35613 }
35616 /* Return current CF value. */
35658 kortest:
35672 /* Emit kortest. */
35674 /* And use setcc to return result from flags. */
35825 gather_gen:
35826 rtx half;
35839 /* Note the arg order is different from the operand order. */
35850 else
35854 {
35876 else
35883 {
35888 }
35895 else
35902 {
35907 }
35911 }
35913 /* Force memory operand only with base register here. But we
35914 don't want to do it on memory operand for other builtin
35915 functions. */
35925 {
35928 }
35929 else
35930 {
35933 }
35935 {
35938 }
35940 /* Optimize. If mask is known to have all high bits set,
35941 replace op0 with pc_rtx to signal that the instruction
35942 overwrites the whole destination and doesn't use its
35943 previous contents. */
35945 {
35947 {
35950 }
35952 {
35955 {
35959 negative++;
35962 negative++;
35963 }
35966 }
35969 {
35970 /* Recognize also when mask is like:
35971 __v2df src = _mm_setzero_pd ();
35972 __v2df mask = _mm_cmpeq_pd (src, src);
35973 or
35974 __v8sf src = _mm256_setzero_ps ();
35975 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
35976 as that is a cheaper way to load all ones into
35977 a register than having to load a constant from
35978 memory. */
35981 {
35986 {
35993 /* FALLTHRU */
36003 }
36004 }
36005 }
36006 }
36014 {
36038 }
36041 scatter_gen:
36057 /* Force memory operand only with base register here. But we
36058 don't want to do it on memory operand for other builtin
36059 functions. */
36066 {
36069 }
36070 else
36071 {
36074 }
36083 {
36086 }
36095 vec_prefetch_gen:
36113 {
36116 }
36118 {
36121 }
36126 /* Force memory operand only with base register here. But we
36127 don't want to do it on memory operand for other builtin
36128 functions. */
36135 {
36138 }
36141 {
36144 }
36160 {
36163 }
36169 }
36182 {
36186 /* Emit a normal call if SSE isn't available. */
36190 }
36219 }
36221 /* This returns the target-specific builtin with code CODE if
36222 current_function_decl has visibility on this builtin, which is checked
36223 using isa flags. Returns NULL_TREE otherwise. */
36226 {
36230 /* Determine the isa flags of current_function_decl. */
36242 else
36244 }
36246 /* Returns a function decl for a vectorized version of the builtin function
36247 with builtin function code FN and the result vector type TYPE, or NULL_TREE
36248 if it is not available. */
36250 static tree
36252 tree type_in)
36253 {
36269 {
36272 {
36279 }
36284 {
36287 }
36292 {
36299 }
36305 /* The round insn does not trap on denormals. */
36310 {
36317 }
36323 /* The round insn does not trap on denormals. */
36328 {
36333 }
36339 /* The round insn does not trap on denormals. */
36344 {
36351 }
36357 /* The round insn does not trap on denormals. */
36362 {
36367 }
36374 {
36379 }
36386 {
36391 }
36397 /* The round insn does not trap on denormals. */
36402 {
36409 }
36415 /* The round insn does not trap on denormals. */
36420 {
36425 }
36430 {
36437 }
36442 {
36449 }
36453 /* The round insn does not trap on denormals. */
36458 {
36463 }
36467 /* The round insn does not trap on denormals. */
36472 {
36477 }
36481 /* The round insn does not trap on denormals. */
36486 {
36491 }
36495 /* The round insn does not trap on denormals. */
36500 {
36505 }
36509 /* The round insn does not trap on denormals. */
36514 {
36519 }
36523 /* The round insn does not trap on denormals. */
36528 {
36533 }
36537 /* The round insn does not trap on denormals. */
36542 {
36547 }
36551 /* The round insn does not trap on denormals. */
36556 {
36561 }
36565 /* The round insn does not trap on denormals. */
36570 {
36575 }
36579 /* The round insn does not trap on denormals. */
36584 {
36589 }
36594 {
36599 }
36604 {
36609 }
36614 }
36616 /* Dispatch to a handler for a vectorization library. */
36619 type_in);
36622 }
36624 /* Handler for an SVML-style interface to
36625 a library with vectorized intrinsics. */
36627 static tree
36629 {
36637 /* The SVML is suitable for unsafe math only. */
36650 {
36697 }
36706 {
36709 }
36710 else
36713 /* Convert to uppercase. */
36718 args;
36720 arity++;
36724 else
36727 /* Build a function declaration for the vectorized function. */
36736 }
36738 /* Handler for an ACML-style interface to
36739 a library with vectorized intrinsics. */
36741 static tree
36743 {
36751 /* The ACML is 64bits only and suitable for unsafe math only as
36752 it does not correctly support parts of IEEE with the required
36753 precision such as denormals. */
36767 {
36797 }
36804 args;
36806 arity++;
36810 else
36813 /* Build a function declaration for the vectorized function. */
36822 }
36824 /* Returns a decl of a function that implements gather load with
36825 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
36826 Return NULL_TREE if it is not available. */
36828 static tree
36831 {
36847 /* v*gather* insn sign extends index to pointer mode. */
36859 {
36887 else
36893 else
36899 else
36905 else
36910 }
36913 }
36915 /* Returns a code for a target-specific builtin that implements
36916 reciprocal of the function, or NULL_TREE if not available. */
36918 static tree
36921 {
36928 /* Machine dependent builtins. */
36930 {
36931 /* Vectorized version of sqrt to rsqrt conversion. */
36940 }
36941 else
36942 /* Normal builtins. */
36944 {
36945 /* Sqrt to rsqrt conversion. */
36951 }
36952 }
36953 \f
36954 /* Helper for avx_vpermilps256_operand et al. This is also used by
36955 the expansion functions to turn the parallel back into a mask.
36956 The return value is 0 for no match and the imm8+1 for a match. */
36958 int
36960 {
36968 /* Validate that all of the elements are constants, and not totally
36969 out of range. Copy the data into an integral array to make the
36970 subsequent checks easier. */
36972 {
36982 }
36985 {
36987 /* In the 512-bit DFmode case, we can only move elements within
36988 a 128-bit lane. First fill the second part of the mask,
36989 then fallthru. */
36991 {
36995 }
36997 {
37001 }
37002 /* FALLTHRU */
37005 /* In the 256-bit DFmode case, we can only move elements within
37006 a 128-bit lane. */
37008 {
37012 }
37014 {
37018 }
37022 /* In 512 bit SFmode case, permutation in the upper 256 bits
37023 must mirror the permutation in the lower 256-bits. */
37027 /* FALLTHRU */
37030 /* In 256 bit SFmode case, we have full freedom of
37031 movement within the low 128-bit lane, but the high 128-bit
37032 lane must mirror the exact same pattern. */
37037 /* FALLTHRU */
37041 /* In the 128-bit case, we've full freedom in the placement of
37042 the elements from the source operand. */
37049 }
37051 /* Make sure success has a non-zero value by adding one. */
37053 }
37055 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37056 the expansion functions to turn the parallel back into a mask.
37057 The return value is 0 for no match and the imm8+1 for a match. */
37059 int
37061 {
37069 /* Validate that all of the elements are constants, and not totally
37070 out of range. Copy the data into an integral array to make the
37071 subsequent checks easier. */
37073 {
37083 }
37085 /* Validate that the halves of the permute are halves. */
37093 /* Reconstruct the mask. */
37095 {
37101 }
37103 /* Make sure success has a non-zero value by adding one. */
37105 }
37106 \f
37107 /* Return a register priority for hard reg REGNO. */
37108 static int
37110 {
37111 /* ebp and r13 as the base always wants a displacement, r12 as the
37112 base always wants an index. So discourage their usage in an
37113 address. */
37118 /* New x86-64 int registers result in bigger code size. Discourage
37119 them. */
37122 /* New x86-64 SSE registers result in bigger code size. Discourage
37123 them. */
37126 /* Usage of AX register results in smaller code. Prefer it. */
37130 }
37132 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37134 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37135 QImode must go into class Q_REGS.
37136 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37137 movdf to do mem-to-mem moves through integer regs. */
37139 static reg_class_t
37141 {
37144 /* We're only allowed to return a subclass of CLASS. Many of the
37145 following checks fail for NO_REGS, so eliminate that early. */
37149 /* All classes can load zeros. */
37153 /* Force constants into memory if we are loading a (nonzero) constant into
37154 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37155 instructions to load from a constant. */
37162 /* Prefer SSE regs only, if we can use them for math. */
37166 /* Floating-point constants need more complex checks. */
37168 {
37169 /* General regs can load everything. */
37173 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37174 zero above. We only want to wind up preferring 80387 registers if
37175 we plan on doing computation with them. */
37178 {
37179 /* Limit class to non-sse. */
37188 }
37191 }
37193 /* Generally when we see PLUS here, it's the function invariant
37194 (plus soft-fp const_int). Which can only be computed into general
37195 regs. */
37199 /* QImode constants are easy to load, but non-constant QImode data
37200 must go into Q_REGS. */
37202 {
37208 }
37211 }
37213 /* Discourage putting floating-point values in SSE registers unless
37214 SSE math is being used, and likewise for the 387 registers. */
37215 static reg_class_t
37217 {
37220 /* Restrict the output reload class to the register bank that we are doing
37221 math on. If we would like not to return a subset of CLASS, reject this
37222 alternative: if reload cannot do this, it will still use its choice. */
37228 {
37233 else
37235 }
37238 }
37240 static reg_class_t
37243 {
37244 /* Double-word spills from general registers to non-offsettable memory
37245 references (zero-extended addresses) require special handling. */
37251 {
37253 ? CODE_FOR_reload_noff_load
37255 /* Add the cost of moving address to a temporary. */
37259 }
37261 /* QImode spills from non-QI registers require
37262 intermediate register on 32bit targets. */
37268 {
37273 else
37279 /* Return Q_REGS if the operand is in memory. */
37282 }
37284 /* This condition handles corner case where an expression involving
37285 pointers gets vectorized. We're trying to use the address of a
37286 stack slot as a vector initializer.
37288 (set (reg:V2DI 74 [ vect_cst_.2 ])
37289 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
37291 Eventually frame gets turned into sp+offset like this:
37293 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37294 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37295 (const_int 392 [0x188]))))
37297 That later gets turned into:
37299 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37300 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
37301 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
37303 We'll have the following reload recorded:
37305 Reload 0: reload_in (DI) =
37306 (plus:DI (reg/f:DI 7 sp)
37307 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
37308 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37309 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
37310 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
37311 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
37312 reload_reg_rtx: (reg:V2DI 22 xmm1)
37314 Which isn't going to work since SSE instructions can't handle scalar
37315 additions. Returning GENERAL_REGS forces the addition into integer
37316 register and reload can handle subsequent reloads without problems. */
37324 }
37326 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
37328 static bool
37330 {
37332 {
37347 }
37350 }
37352 /* If we are copying between general and FP registers, we need a memory
37353 location. The same is true for SSE and MMX registers.
37355 To optimize register_move_cost performance, allow inline variant.
37357 The macro can't work reliably when one of the CLASSES is class containing
37358 registers from multiple units (SSE, MMX, integer). We avoid this by never
37359 combining those units in single alternative in the machine description.
37360 Ensure that this constraint holds to avoid unexpected surprises.
37362 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
37363 enforce these sanity checks. */
37368 {
37377 {
37380 }
37385 /* ??? This is a lie. We do have moves between mmx/general, and for
37386 mmx/sse2. But by saying we need secondary memory we discourage the
37387 register allocator from using the mmx registers unless needed. */
37392 {
37393 /* SSE1 doesn't have any direct moves from other classes. */
37397 /* If the target says that inter-unit moves are more expensive
37398 than moving through memory, then don't generate them. */
37403 /* Between SSE and general, we have moves no larger than word size. */
37406 }
37409 }
37411 bool
37414 {
37416 }
37418 /* Implement the TARGET_CLASS_MAX_NREGS hook.
37420 On the 80386, this is the size of MODE in words,
37421 except in the FP regs, where a single reg is always enough. */
37423 static unsigned char
37425 {
37427 {
37432 else
37434 }
37435 else
37436 {
37439 else
37441 }
37442 }
37444 /* Return true if the registers in CLASS cannot represent the change from
37445 modes FROM to TO. */
37447 bool
37450 {
37454 /* x87 registers can't do subreg at all, as all values are reformatted
37455 to extended precision. */
37460 {
37461 /* Vector registers do not support QI or HImode loads. If we don't
37462 disallow a change to these modes, reload will assume it's ok to
37463 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
37464 the vec_dupv4hi pattern. */
37468 /* Vector registers do not support subreg with nonzero offsets, which
37469 are otherwise valid for integer registers. Since we can't see
37470 whether we have a nonzero offset from here, prohibit all
37471 nonparadoxical subregs changing size. */
37474 }
37477 }
37479 /* Return the cost of moving data of mode M between a
37480 register and memory. A value of 2 is the default; this cost is
37481 relative to those in `REGISTER_MOVE_COST'.
37483 This function is used extensively by register_move_cost that is used to
37484 build tables at startup. Make it inline in this case.
37485 When IN is 2, return maximum of in and out move cost.
37487 If moving between registers and memory is more expensive than
37488 between two registers, you should define this macro to express the
37489 relative cost.
37491 Model also increased moving costs of QImode registers in non
37492 Q_REGS classes.
37493 */
37497 {
37500 {
37503 {
37515 }
37519 }
37521 {
37524 {
37536 }
37540 }
37542 {
37545 {
37554 }
37558 }
37560 {
37563 {
37569 else
37574 }
37575 else
37576 {
37581 else
37583 }
37590 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
37597 else
37601 }
37602 }
37604 static int
37607 {
37609 }
37612 /* Return the cost of moving data from a register in class CLASS1 to
37613 one in class CLASS2.
37615 It is not required that the cost always equal 2 when FROM is the same as TO;
37616 on some machines it is expensive to move between registers if they are not
37617 general registers. */
37619 static int
37621 reg_class_t class2_i)
37622 {
37626 /* In case we require secondary memory, compute cost of the store followed
37627 by load. In order to avoid bad register allocation choices, we need
37628 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
37631 {
37637 /* In case of copying from general_purpose_register we may emit multiple
37638 stores followed by single load causing memory size mismatch stall.
37639 Count this as arbitrarily high cost of 20. */
37644 /* In the case of FP/MMX moves, the registers actually overlap, and we
37645 have to switch modes in order to treat them differently. */
37651 }
37653 /* Moves between SSE/MMX and integer unit are expensive. */
37657 /* ??? By keeping returned value relatively high, we limit the number
37658 of moves between integer and MMX/SSE registers for all targets.
37659 Additionally, high value prevents problem with x86_modes_tieable_p(),
37660 where integer modes in MMX/SSE registers are not tieable
37661 because of missing QImode and HImode moves to, from or between
37662 MMX/SSE registers. */
37672 }
37674 /* Return TRUE if hard register REGNO can hold a value of machine-mode
37675 MODE. */
37677 bool
37679 {
37680 /* Flags and only flags can only hold CCmode values. */
37692 {
37693 /* We implement the move patterns for all vector modes into and
37694 out of SSE registers, even when no operation instructions
37695 are available. */
37697 /* For AVX-512 we allow, regardless of regno:
37698 - XI mode
37699 - any of 512-bit wide vector mode
37700 - any scalar mode. */
37707 /* xmm16-xmm31 are only available for AVX-512. */
37711 /* OImode and AVX modes are available only when AVX is enabled. */
37718 }
37720 {
37721 /* We implement the move patterns for 3DNOW modes even in MMX mode,
37722 so if the register is available at all, then we can move data of
37723 the given mode into or out of it. */
37726 }
37729 {
37730 /* Take care for QImode values - they can be in non-QI regs,
37731 but then they do cause partial register stalls. */
37736 /* LRA checks if the hard register is OK for the given mode.
37737 QImode values can live in non-QI regs, so we allow all
37738 registers here. */
37742 }
37743 /* We handle both integer and floats in the general purpose registers. */
37750 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
37751 on to use that value in smaller contexts, this can easily force a
37752 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
37753 supporting DImode, allow it. */
37758 }
37760 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
37761 tieable integer mode. */
37763 static bool
37765 {
37767 {
37780 }
37781 }
37783 /* Return true if MODE1 is accessible in a register that can hold MODE2
37784 without copying. That is, all register classes that can hold MODE2
37785 can also hold MODE1. */
37787 bool
37789 {
37797 /* MODE2 being XFmode implies fp stack or general regs, which means we
37798 can tie any smaller floating point modes to it. Note that we do not
37799 tie this with TFmode. */
37803 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
37804 that we can tie it with SFmode. */
37808 /* If MODE2 is only appropriate for an SSE register, then tie with
37809 any other mode acceptable to SSE registers. */
37819 /* If MODE2 is appropriate for an MMX register, then tie
37820 with any other mode acceptable to MMX registers. */
37827 }
37829 /* Return the cost of moving between two registers of mode MODE. */
37831 static int
37833 {
37837 {
37869 }
37871 /* Return the cost of moving between two registers of mode MODE,
37872 assuming that the move will be in pieces of at most UNITS bytes. */
37874 }
37876 /* Compute a (partial) cost for rtx X. Return true if the complete
37877 cost has been computed, and false if subexpressions should be
37878 scanned. In either case, *TOTAL contains the cost result. */
37880 static bool
37883 {
37884 rtx mask;
37891 {
37895 {
37898 }
37910 && !(TARGET_64BIT
37915 else
37921 {
37924 }
37926 {
37936 }
37938 {
37941 {
37950 }
37951 }
37952 /* Fall back to (MEM (SYMBOL_REF)), since that's where
37953 it'll probably end up. Add a penalty for size. */
37960 /* The zero extensions is often completely free on x86_64, so make
37961 it as cheap as possible. */
37967 else
37979 {
37982 {
37985 }
37988 {
37991 }
37992 }
37993 /* FALLTHRU */
38000 {
38001 /* ??? Should be SSE vector operation cost. */
38002 /* At least for published AMD latencies, this really is the same
38003 as the latency for a simple fpu operation like fabs. */
38004 /* V*QImode is emulated with 1-11 insns. */
38006 {
38009 {
38010 /* For XOP we use vpshab, which requires a broadcast of the
38011 value to the variable shift insn. For constants this
38012 means a V16Q const in mem; even when we can perform the
38013 shift with one insn set the cost to prefer paddb. */
38015 {
38020 }
38022 }
38026 }
38027 else
38029 }
38031 {
38033 {
38036 else
38038 }
38039 else
38040 {
38043 else
38045 }
38046 }
38047 else
38048 {
38053 {
38054 /* Return the cost after shift-and truncation. */
38057 }
38058 else
38060 }
38064 {
38065 rtx sub;
38070 /* ??? SSE scalar/vector cost should be used here. */
38071 /* ??? Bald assumption that fma has the same cost as fmul. */
38075 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38086 }
38090 {
38091 /* ??? SSE scalar cost should be used here. */
38094 }
38096 {
38099 }
38101 {
38102 /* ??? SSE vector cost should be used here. */
38105 }
38107 {
38108 /* V*QImode is emulated with 7-13 insns. */
38110 {
38117 }
38118 /* V*DImode is emulated with 5-8 insns. */
38120 {
38123 else
38125 }
38126 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38127 insns, including two PMULUDQ. */
38130 else
38133 }
38134 else
38135 {
38140 {
38143 nbits++;
38144 }
38145 else
38146 /* This is arbitrary. */
38149 /* Compute costs correctly for widening multiplication. */
38153 {
38160 {
38164 else
38166 }
38170 }
38178 }
38185 /* ??? SSE cost should be used here. */
38190 /* ??? SSE vector cost should be used here. */
38192 else
38199 {
38204 {
38207 {
38215 }
38216 }
38219 {
38222 {
38228 }
38229 }
38231 {
38239 }
38240 }
38241 /* FALLTHRU */
38245 {
38246 /* ??? SSE cost should be used here. */
38249 }
38251 {
38254 }
38256 {
38257 /* ??? SSE vector cost should be used here. */
38260 }
38261 /* FALLTHRU */
38268 {
38275 }
38276 /* FALLTHRU */
38280 {
38281 /* ??? SSE cost should be used here. */
38284 }
38286 {
38289 }
38291 {
38292 /* ??? SSE vector cost should be used here. */
38295 }
38296 /* FALLTHRU */
38300 {
38301 /* ??? Should be SSE vector operation cost. */
38302 /* At least for published AMD latencies, this really is the same
38303 as the latency for a simple fpu operation like fabs. */
38305 }
38308 else
38317 {
38318 /* This kind of construct is implemented using test[bwl].
38319 Treat it as if we had an AND. */
38324 }
38334 /* ??? SSE cost should be used here. */
38339 /* ??? SSE vector cost should be used here. */
38345 /* ??? SSE cost should be used here. */
38350 /* ??? SSE vector cost should be used here. */
38362 /* ??? Assume all of these vector manipulation patterns are
38363 recognizable. In which case they all pretty much have the
38364 same cost. */
38369 /* This is masked instruction, assume the same cost,
38370 as nonmasked variant. */
38373 else
38379 }
38380 }
38382 #if TARGET_MACHO
38386 /* Given a symbol name and its associated stub, write out the
38387 definition of the stub. */
38389 void
38391 {
38396 /* For 64-bit we shouldn't get here. */
38399 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
38416 else
38423 {
38425 }
38427 {
38428 /* PIC stub. */
38429 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38435 }
38436 else
38439 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
38440 it needs no stub-binding-helper. */
38447 {
38450 }
38451 else
38456 /* N.B. Keep the correspondence of these
38457 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
38458 old-pic/new-pic/non-pic stubs; altering this will break
38459 compatibility with existing dylibs. */
38461 {
38462 /* 25-byte PIC stub using "CALL get_pc_thunk". */
38464 }
38465 else
38466 /* 16-byte -mdynamic-no-pic stub. */
38472 }
38475 /* Order the registers for register allocator. */
38477 void
38479 {
38483 /* First allocate the local general purpose registers. */
38488 /* Global general purpose registers. */
38493 /* x87 registers come first in case we are doing FP math
38494 using them. */
38499 /* SSE registers. */
38505 /* Extended REX SSE registers. */
38509 /* Mask register. */
38513 /* x87 registers. */
38521 /* Initialize the rest of array as we do not allocate some registers
38522 at all. */
38525 }
38527 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
38528 in struct attribute_spec handler. */
38529 static tree
38531 tree args,
38534 {
38539 {
38541 name);
38544 }
38546 {
38548 name);
38551 }
38553 {
38554 tree cst;
38558 {
38561 name);
38563 }
38566 {
38569 name);
38571 }
38574 }
38577 }
38579 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
38580 struct attribute_spec.handler. */
38581 static tree
38583 tree args ATTRIBUTE_UNUSED,
38585 {
38590 {
38592 name);
38595 }
38597 /* Can combine regparm with all attributes but fastcall. */
38599 {
38601 {
38603 }
38606 }
38608 {
38610 {
38612 }
38615 }
38618 }
38620 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
38621 struct attribute_spec.handler. */
38622 static tree
38624 tree args ATTRIBUTE_UNUSED,
38626 {
38629 {
38632 }
38633 else
38637 {
38639 name);
38641 }
38647 {
38649 name);
38651 }
38654 }
38656 static tree
38658 tree args ATTRIBUTE_UNUSED,
38660 {
38662 {
38664 name);
38666 }
38668 }
38670 static bool
38672 {
38676 }
38678 /* Returns an expression indicating where the this parameter is
38679 located on entry to the FUNCTION. */
38681 static rtx
38683 {
38689 {
38694 else
38697 }
38702 {
38709 {
38714 }
38715 else
38716 {
38719 {
38725 }
38726 }
38728 }
38732 }
38734 /* Determine whether x86_output_mi_thunk can succeed. */
38736 static bool
38738 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
38740 {
38741 /* 64-bit can handle anything. */
38745 /* For 32-bit, everything's fine if we have one free register. */
38749 /* Need a free register for vcall_offset. */
38753 /* Need a free register for GOT references. */
38757 /* Otherwise ok. */
38759 }
38761 /* Output the assembler code for a thunk function. THUNK_DECL is the
38762 declaration for the thunk function itself, FUNCTION is the decl for
38763 the target function. DELTA is an immediate constant offset to be
38764 added to THIS. If VCALL_OFFSET is nonzero, the word at
38765 *(*this + vcall_offset) should be added to THIS. */
38767 static void
38771 {
38778 else
38779 {
38785 else
38787 }
38791 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
38792 pull it in now and let DELTA benefit. */
38796 {
38797 /* Put the this parameter into %eax. */
38800 }
38801 else
38804 /* Adjust the this parameter by a fixed constant. */
38806 {
38811 {
38813 {
38817 }
38818 }
38821 }
38823 /* Adjust the this parameter by a value stored in the vtable. */
38825 {
38835 /* Adjust the this parameter. */
38839 {
38843 }
38850 vcall_mem));
38851 else
38853 }
38855 /* If necessary, drop THIS back to its stack slot. */
38861 {
38864 ;
38865 else
38866 {
38870 }
38871 }
38872 else
38873 {
38875 ;
38876 #if TARGET_MACHO
38878 {
38881 }
38883 else
38884 {
38892 }
38893 }
38895 /* Our sibling call patterns do not allow memories, because we have no
38896 predicate that can distinguish between frame and non-frame memory.
38897 For our purposes here, we can get away with (ab)using a jump pattern,
38898 because we're going to do no optimization. */
38900 {
38902 {
38906 }
38907 else
38909 }
38910 else
38911 {
38917 {
38923 }
38929 }
38932 /* Emit just enough of rest_of_compilation to get the insns emitted.
38933 Note that use_thunk calls assemble_start_function et al. */
38939 }
38941 static void
38943 {
38947 #if TARGET_MACHO
38949 #endif
38956 }
38958 int
38960 {
38972 }
38974 /* Output assembler code to FILE to increment profiler label # LABELNO
38975 for profiling a function entry. */
38976 void
38978 {
38983 {
38984 #ifndef NO_PROFILE_COUNTERS
38986 #endif
38990 else
38992 }
38994 {
38995 #ifndef NO_PROFILE_COUNTERS
38998 #endif
39000 }
39001 else
39002 {
39003 #ifndef NO_PROFILE_COUNTERS
39006 #endif
39008 }
39009 }
39011 /* We don't have exact information about the insn sizes, but we may assume
39012 quite safely that we are informed about all 1 byte insns and memory
39013 address sizes. This is enough to eliminate unnecessary padding in
39014 99% of cases. */
39016 static int
39018 {
39024 /* Discard alignments we've emit and jump instructions. */
39029 /* Important case - calls are always 5 bytes.
39030 It is common to have many calls in the row. */
39039 /* For normal instructions we rely on get_attr_length being exact,
39040 with a few exceptions. */
39042 {
39046 {
39056 /* Otherwise trust get_attr_length. */
39058 }
39063 }
39066 else
39068 }
39070 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39072 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39073 window. */
39075 static void
39077 {
39082 /* Look for all minimal intervals of instructions containing 4 jumps.
39083 The intervals are bounded by START and INSN. NBYTES is the total
39084 size of instructions in the interval including INSN and not including
39085 START. When the NBYTES is smaller than 16 bytes, it is possible
39086 that the end of START and INSN ends up in the same 16byte page.
39088 The smallest offset in the page INSN can start is the case where START
39089 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39090 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39092 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39093 have to, control transfer to label(s) can be performed through other
39094 means, and also we estimate minimum length of all asm stmts as 0. */
39096 {
39100 {
39106 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39107 already in the current 16 byte page, because otherwise
39108 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39109 bytes to reach 16 byte boundary. */
39117 {
39119 {
39124 else
39127 }
39128 }
39130 }
39139 njumps++;
39140 else
39144 {
39149 else
39152 }
39159 {
39166 }
39167 }
39168 }
39169 #endif
39171 /* AMD Athlon works faster
39172 when RET is not destination of conditional jump or directly preceded
39173 by other jump instruction. We avoid the penalty by inserting NOP just
39174 before the RET instructions in such cases. */
39175 static void
39177 {
39178 edge e;
39179 edge_iterator ei;
39182 {
39185 rtx prev;
39195 {
39196 edge e;
39197 edge_iterator ei;
39202 {
39205 }
39206 }
39208 {
39214 /* Empty functions get branch mispredict even when
39215 the jump destination is not visible to us. */
39218 }
39220 {
39223 }
39224 }
39225 }
39227 /* Count the minimum number of instructions in BB. Return 4 if the
39228 number of instructions >= 4. */
39230 static int
39232 {
39233 rtx insn;
39236 /* Count number of instructions in this block. Return 4 if the number
39237 of instructions >= 4. */
39239 {
39240 /* Only happen in exit blocks. */
39248 {
39249 insn_count++;
39252 }
39253 }
39256 }
39259 /* Count the minimum number of instructions in code path in BB.
39260 Return 4 if the number of instructions >= 4. */
39262 static int
39264 {
39265 edge e;
39266 edge_iterator ei;
39269 /* Only bother counting instructions along paths with no
39270 more than 2 basic blocks between entry and exit. Given
39271 that BB has an edge to exit, determine if a predecessor
39272 of BB has an edge from entry. If so, compute the number
39273 of instructions in the predecessor block. If there
39274 happen to be multiple such blocks, compute the minimum. */
39277 {
39278 edge prev_e;
39279 edge_iterator prev_ei;
39282 {
39285 }
39287 {
39289 {
39294 }
39295 }
39296 }
39302 }
39304 /* Pad short function to 4 instructions. */
39306 static void
39308 {
39309 edge e;
39310 edge_iterator ei;
39313 {
39316 {
39319 /* Pad short function. */
39321 {
39324 /* Find epilogue. */
39333 /* Two NOPs count as one instruction. */
39336 }
39337 }
39338 }
39339 }
39341 /* Fix up a Windows system unwinder issue. If an EH region falls through into
39342 the epilogue, the Windows system unwinder will apply epilogue logic and
39343 produce incorrect offsets. This can be avoided by adding a nop between
39344 the last insn that can throw and the first insn of the epilogue. */
39346 static void
39348 {
39349 edge e;
39350 edge_iterator ei;
39353 {
39356 /* Find the beginning of the epilogue. */
39363 /* We only care about preceding insns that can throw. */
39368 /* Do not separate calls from their debug information. */
39374 else
39378 }
39379 }
39381 /* Implement machine specific optimizations. We implement padding of returns
39382 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
39383 static void
39385 {
39386 /* We are freeing block_for_insn in the toplev to keep compatibility
39387 with old MDEP_REORGS that are not CFG based. Recompute it now. */
39394 {
39399 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39402 #endif
39403 }
39404 }
39406 /* Return nonzero when QImode register that must be represented via REX prefix
39407 is used. */
39408 bool
39410 {
39418 }
39420 /* Return nonzero when P points to register encoded via REX prefix.
39421 Called via for_each_rtx. */
39422 static int
39424 {
39430 }
39432 /* Return true when INSN mentions register that must be encoded using REX
39433 prefix. */
39434 bool
39436 {
39439 }
39441 /* If profitable, negate (without causing overflow) integer constant
39442 of mode MODE at location LOC. Return true in this case. */
39443 bool
39445 {
39446 HOST_WIDE_INT val;
39452 {
39454 /* DImode x86_64 constants must fit in 32 bits. */
39467 }
39469 /* Avoid overflows. */
39475 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
39476 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
39479 {
39482 }
39485 }
39487 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
39488 optabs would emit if we didn't have TFmode patterns. */
39490 void
39492 {
39526 }
39527 \f
39528 /* AVX512F does support 64-byte integer vector operations,
39529 thus the longest vector we are faced with is V64QImode. */
39530 #define MAX_VECT_LEN 64
39532 struct expand_vec_perm_d
39533 {
39540 };
39546 /* Get a vector mode of the same size as the original but with elements
39547 twice as wide. This is only guaranteed to apply to integral vectors. */
39551 {
39552 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
39557 }
39559 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
39560 fill target with val via vec_duplicate. */
39562 static bool
39564 {
39568 /* First attempt to recognize VAL as-is. */
39572 {
39573 rtx seq;
39574 /* If that fails, force VAL into a register. */
39585 }
39587 }
39589 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39590 with all elements equal to VAR. Return true if successful. */
39592 static bool
39595 {
39599 {
39604 /* FALLTHRU */
39624 {
39625 rtx x;
39632 }
39642 {
39646 permute:
39654 /* Extend to SImode using a paradoxical SUBREG. */
39658 /* Insert the SImode value as low element of a V4SImode vector. */
39667 }
39675 widen:
39676 /* Replicate the value once into the next wider mode and recurse. */
39677 {
39679 rtx x;
39696 }
39700 {
39709 }
39714 }
39715 }
39717 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39718 whose ONE_VAR element is VAR, and other elements are zero. Return true
39719 if successful. */
39721 static bool
39724 {
39726 rtx new_target;
39731 {
39733 /* For SSE4.1, we normally use vector set. But if the second
39734 element is zero and inter-unit moves are OK, we use movq
39735 instead. */
39737 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
39759 /* Use ix86_expand_vector_set in 64bit mode only. */
39764 }
39767 {
39772 }
39775 {
39780 /* FALLTHRU */
39795 else
39802 {
39803 /* We need to shuffle the value to the correct position, so
39804 create a new pseudo to store the intermediate result. */
39806 /* With SSE2, we can use the integer shuffle insns. */
39808 {
39810 const1_rtx,
39817 }
39819 /* Otherwise convert the intermediate result to V4SFmode and
39820 use the SSE1 shuffle instructions. */
39822 {
39825 }
39826 else
39830 const1_rtx,
39839 }
39854 widen:
39858 /* Zero extend the variable element to SImode and recurse. */
39871 }
39872 }
39874 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
39875 consisting of the values in VALS. It is known that all elements
39876 except ONE_VAR are constants. Return true if successful. */
39878 static bool
39881 {
39891 {
39896 /* For the two element vectors, it's just as easy to use
39897 the general case. */
39901 /* Use ix86_expand_vector_set in 64bit mode only. */
39923 widen:
39924 /* There's no way to set one QImode entry easily. Combine
39925 the variable value with its adjacent constant value, and
39926 promote to an HImode set. */
39929 {
39934 }
39935 else
39936 {
39939 }
39953 }
39958 }
39960 /* A subroutine of ix86_expand_vector_init_general. Use vector
39961 concatenate to handle the most general case: all values variable,
39962 and none identical. */
39964 static void
39967 {
39970 rtvec v;
39974 {
39977 {
40022 }
40035 {
40050 }
40055 {
40074 }
40079 {
40092 }
40095 half:
40096 /* FIXME: We process inputs backward to help RA. PR 36222. */
40100 {
40105 }
40109 {
40113 {
40117 }
40120 {
40124 }
40127 }
40129 {
40132 {
40136 }
40139 }
40140 else
40146 }
40147 }
40149 /* A subroutine of ix86_expand_vector_init_general. Use vector
40150 interleave to handle the most general case: all values variable,
40151 and none identical. */
40153 static void
40156 {
40165 {
40186 }
40189 {
40190 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40194 /* Insert the SImode value as low element of V4SImode vector. */
40198 op0),
40200 const1_rtx);
40203 /* Cast the V4SImode vector back to a vector in orignal mode. */
40207 /* Load even elements into the second position. */
40211 const1_rtx));
40213 /* Cast vector to FIRST_IMODE vector. */
40216 }
40218 /* Interleave low FIRST_IMODE vectors. */
40220 {
40224 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40227 }
40229 /* Interleave low SECOND_IMODE vectors. */
40231 {
40234 {
40239 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
40240 vector. */
40243 }
40246 /* FALLTHRU */
40253 /* Cast the SECOND_IMODE vector back to a vector on original
40254 mode. */
40261 }
40262 }
40264 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
40265 all values variable, and none identical. */
40267 static void
40270 {
40276 {
40281 /* FALLTHRU */
40309 half:
40326 /* FALLTHRU */
40332 /* Don't use ix86_expand_vector_init_interleave if we can't
40333 move from GPR to SSE register directly. */
40349 }
40351 {
40363 {
40367 {
40373 else
40374 {
40379 }
40380 }
40383 }
40388 {
40394 }
40396 {
40402 }
40403 else
40405 }
40406 }
40408 /* Initialize vector TARGET via VALS. Suppress the use of MMX
40409 instructions unless MMX_OK is true. */
40411 void
40413 {
40420 rtx x;
40423 {
40433 }
40435 /* Constants are best loaded from the constant pool. */
40437 {
40440 }
40442 /* If all values are identical, broadcast the value. */
40448 /* Values where only one field is non-constant are best loaded from
40449 the pool and overwritten via move later. */
40451 {
40455 one_var))
40460 }
40463 }
40465 void
40467 {
40472 rtx tmp;
40474 = {
40481 };
40483 = {
40490 };
40494 {
40498 {
40503 else
40507 }
40519 else
40525 {
40528 /* For the two element vectors, we implement a VEC_CONCAT with
40529 the extraction of the other element. */
40536 else
40541 }
40550 {
40556 /* tmp = target = A B C D */
40558 /* target = A A B B */
40560 /* target = X A B B */
40562 /* target = A X C D */
40569 /* tmp = target = A B C D */
40571 /* tmp = X B C D */
40573 /* target = A B X D */
40580 /* tmp = target = A B C D */
40582 /* tmp = X B C D */
40584 /* target = A B X D */
40592 }
40600 /* Element 0 handled by vec_merge below. */
40602 {
40605 }
40608 {
40609 /* With SSE2, use integer shuffles to swap element 0 and ELT,
40610 store into element 0, then shuffle them back. */
40627 }
40628 else
40629 {
40630 /* For SSE1, we have to reuse the V4SF code. */
40634 }
40687 half:
40688 /* Compute offset. */
40694 /* Extract the half. */
40698 /* Put val in tmp at elt. */
40701 /* Put it back. */
40707 }
40710 {
40714 }
40715 else
40716 {
40725 }
40726 }
40728 void
40730 {
40734 rtx tmp;
40737 {
40742 /* FALLTHRU */
40755 {
40775 }
40787 {
40789 {
40809 }
40813 }
40814 else
40815 {
40816 /* For SSE1, we have to reuse the V4SF code. */
40820 }
40836 {
40840 else
40844 }
40849 {
40853 else
40857 }
40862 {
40866 else
40870 }
40875 {
40879 else
40883 }
40888 {
40892 else
40896 }
40901 {
40905 else
40909 }
40916 else
40925 else
40934 else
40943 else
40949 /* ??? Could extract the appropriate HImode element and shift. */
40952 }
40955 {
40959 /* Let the rtl optimizers know about the zero extension performed. */
40961 {
40964 }
40967 }
40968 else
40969 {
40976 }
40977 }
40979 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
40980 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
40981 The upper bits of DEST are undefined, though they shouldn't cause
40982 exceptions (some bits from src or all zeros are ok). */
40984 static void
40986 {
40989 {
40993 else
41011 else
41018 else
41026 {
41031 const1_rtx);
41032 }
41033 else
41034 {
41038 }
41058 else
41080 }
41084 }
41086 /* Expand a vector reduction. FN is the binary pattern to reduce;
41087 DEST is the destination; IN is the input vector. */
41089 void
41091 {
41096 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41100 {
41103 }
41108 {
41113 else
41117 }
41118 }
41119 \f
41120 /* Target hook for scalar_mode_supported_p. */
41121 static bool
41123 {
41128 else
41130 }
41132 /* Implements target hook vector_mode_supported_p. */
41133 static bool
41135 {
41149 }
41151 /* Target hook for c_mode_for_suffix. */
41152 static enum machine_mode
41154 {
41161 }
41163 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41165 We do this in the new i386 backend to maintain source compatibility
41166 with the old cc0-based compiler. */
41168 static tree
41170 tree inputs ATTRIBUTE_UNUSED,
41171 tree clobbers)
41172 {
41174 clobbers);
41176 clobbers);
41178 }
41180 /* Implements target vector targetm.asm.encode_section_info. */
41182 static void ATTRIBUTE_UNUSED
41184 {
41191 }
41193 /* Worker function for REVERSE_CONDITION. */
41195 enum rtx_code
41197 {
41201 }
41203 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41204 to OPERANDS[0]. */
41208 {
41210 {
41213 {
41217 }
41221 }
41223 {
41227 else
41228 {
41229 /* There is no non-popping store to memory for XFmode.
41230 So if we need one, follow the store with a load. */
41233 else
41235 }
41236 }
41237 else
41239 }
41241 /* Output code to perform a conditional jump to LABEL, if C2 flag in
41242 FP status register is set. */
41244 void
41246 {
41248 rtx temp;
41253 {
41258 }
41259 else
41260 {
41265 }
41269 pc_rtx);
41274 }
41276 /* Output code to perform a log1p XFmode calculation. */
41279 {
41285 rtx test;
41291 XFmode));
41305 }
41307 /* Emit code for round calculation. */
41309 {
41316 rtx insn;
41321 {
41333 }
41336 {
41357 }
41365 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
41367 /* scratch = fxam(op1) */
41370 UNSPEC_FXAM)));
41371 /* e1 = fabs(op1) */
41374 /* e2 = e1 + 0.5 */
41379 /* res = floor(e2) */
41381 {
41386 }
41387 else
41391 {
41394 {
41401 UNSPEC_TRUNC_NOOP)));
41402 }
41418 }
41420 /* flags = signbit(a) */
41423 /* if (flags) then res = -res */
41427 pc_rtx);
41438 }
41440 /* Output code to perform a Newton-Rhapson approximation of a single precision
41441 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
41444 {
41452 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
41456 /* x0 = rcp(b) estimate */
41460 UNSPEC_RCP14)));
41461 else
41464 UNSPEC_RCP)));
41466 /* e0 = x0 * b */
41470 /* e0 = x0 * e0 */
41474 /* e1 = x0 + x0 */
41478 /* x1 = e1 - e0 */
41482 /* res = a * x1 */
41485 }
41487 /* Output code to perform a Newton-Rhapson approximation of a
41488 single precision floating point [reciprocal] square root. */
41492 {
41494 REAL_VALUE_TYPE r;
41511 {
41514 /* There is no 512-bit rsqrt. There is however rsqrt14. */
41517 }
41519 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
41520 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
41524 /* x0 = rsqrt(a) estimate */
41527 unspec)));
41529 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
41531 {
41539 /* Handle masked compare. */
41541 {
41543 /* Imm value 0x4 corresponds to not-equal comparison. */
41546 }
41547 else
41548 {
41554 }
41555 }
41557 /* e0 = x0 * a */
41560 /* e1 = e0 * x0 */
41564 /* e2 = e1 - 3. */
41571 /* e3 = -.5 * x0 */
41574 else
41575 /* e3 = -.5 * e0 */
41578 /* ret = e2 * e3 */
41581 }
41583 #ifdef TARGET_SOLARIS
41584 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
41586 static void
41588 tree decl)
41589 {
41590 /* With Binutils 2.15, the "@unwind" marker must be specified on
41591 every occurrence of the ".eh_frame" section, not just the first
41592 one. */
41595 {
41599 }
41601 #ifndef USE_GAS
41603 {
41606 }
41607 #endif
41610 }
41613 /* Return the mangling of TYPE if it is an extended fundamental type. */
41617 {
41625 {
41627 /* __float128 is "g". */
41630 /* "long double" or __float80 is "e". */
41634 }
41635 }
41637 /* For 32-bit code we can save PIC register setup by using
41638 __stack_chk_fail_local hidden function instead of calling
41639 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
41640 register, so it is better to call __stack_chk_fail directly. */
41642 static tree ATTRIBUTE_UNUSED
41644 {
41645 return TARGET_64BIT
41648 }
41650 /* Select a format to encode pointers in exception handling data. CODE
41651 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
41652 true if the symbol may be affected by dynamic relocations.
41654 ??? All x86 object file formats are capable of representing this.
41655 After all, the relocation needed is the same as for the call insn.
41656 Whether or not a particular assembler allows us to enter such, I
41657 guess we'll have to see. */
41658 int
41660 {
41662 {
41669 }
41674 }
41675 \f
41676 /* Expand copysign from SIGN to the positive value ABS_VALUE
41677 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
41678 the sign-bit. */
41679 static void
41681 {
41685 {
41692 else
41697 {
41698 /* We need to generate a scalar mode mask in this case. */
41703 }
41704 }
41705 else
41711 }
41713 /* Expand fabs (OP0) and return a new rtx that holds the result. The
41714 mask for masking out the sign-bit is stored in *SMASK, if that is
41715 non-null. */
41716 static rtx
41718 {
41727 else
41731 {
41732 /* We need to generate a scalar mode mask in this case. */
41737 }
41745 }
41747 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
41748 swapping the operands if SWAP_OPERANDS is true. The expanded
41749 code is a forward jump to a newly created label in case the
41750 comparison is true. The generated label rtx is returned. */
41751 static rtx
41754 {
41759 {
41763 }
41776 }
41778 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
41779 using comparison code CODE. Operands are swapped for the comparison if
41780 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
41781 static rtx
41784 {
41790 {
41794 }
41801 }
41803 /* Generate and return a rtx of mode MODE for 2**n where n is the number
41804 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
41805 static rtx
41807 {
41808 REAL_VALUE_TYPE TWO52r;
41809 rtx TWO52;
41816 }
41818 /* Expand SSE sequence for computing lround from OP1 storing
41819 into OP0. */
41820 void
41822 {
41823 /* C code for the stuff we're doing below:
41824 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
41825 return (long)tmp;
41826 */
41830 rtx adj;
41832 /* load nextafter (0.5, 0.0) */
41837 /* adj = copysign (0.5, op1) */
41841 /* adj = op1 + adj */
41844 /* op0 = (imode)adj */
41846 }
41848 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
41849 into OPERAND0. */
41850 void
41852 {
41853 /* C code for the stuff we're doing below (for do_floor):
41854 xi = (long)op1;
41855 xi -= (double)xi > op1 ? 1 : 0;
41856 return xi;
41857 */
41862 /* reg = (long)op1 */
41866 /* freg = (double)reg */
41870 /* ireg = (freg > op1) ? ireg - 1 : ireg */
41881 }
41883 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
41884 result in OPERAND0. */
41885 void
41887 {
41888 /* C code for the stuff we're doing below:
41889 xa = fabs (operand1);
41890 if (!isless (xa, 2**52))
41891 return operand1;
41892 xa = xa + 2**52 - 2**52;
41893 return copysign (xa, operand1);
41894 */
41901 /* xa = abs (operand1) */
41904 /* if (!isless (xa, TWO52)) goto label; */
41917 }
41919 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41920 into OPERAND0. */
41921 void
41923 {
41924 /* C code for the stuff we expand below.
41925 double xa = fabs (x), x2;
41926 if (!isless (xa, TWO52))
41927 return x;
41928 xa = xa + TWO52 - TWO52;
41929 x2 = copysign (xa, x);
41930 Compensate. Floor:
41931 if (x2 > x)
41932 x2 -= 1;
41933 Compensate. Ceil:
41934 if (x2 < x)
41935 x2 -= -1;
41936 return x2;
41937 */
41943 /* Temporary for holding the result, initialized to the input
41944 operand to ease control flow. */
41948 /* xa = abs (operand1) */
41951 /* if (!isless (xa, TWO52)) goto label; */
41954 /* xa = xa + TWO52 - TWO52; */
41958 /* xa = copysign (xa, operand1) */
41961 /* generate 1.0 or -1.0 */
41966 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
41970 /* We always need to subtract here to preserve signed zero. */
41979 }
41981 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
41982 into OPERAND0. */
41983 void
41985 {
41986 /* C code for the stuff we expand below.
41987 double xa = fabs (x), x2;
41988 if (!isless (xa, TWO52))
41989 return x;
41990 x2 = (double)(long)x;
41991 Compensate. Floor:
41992 if (x2 > x)
41993 x2 -= 1;
41994 Compensate. Ceil:
41995 if (x2 < x)
41996 x2 += 1;
41997 if (HONOR_SIGNED_ZEROS (mode))
41998 return copysign (x2, x);
41999 return x2;
42000 */
42006 /* Temporary for holding the result, initialized to the input
42007 operand to ease control flow. */
42011 /* xa = abs (operand1) */
42014 /* if (!isless (xa, TWO52)) goto label; */
42017 /* xa = (double)(long)x */
42022 /* generate 1.0 */
42025 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42040 }
42042 /* Expand SSE sequence for computing round from OPERAND1 storing
42043 into OPERAND0. Sequence that works without relying on DImode truncation
42044 via cvttsd2siq that is only available on 64bit targets. */
42045 void
42047 {
42048 /* C code for the stuff we expand below.
42049 double xa = fabs (x), xa2, x2;
42050 if (!isless (xa, TWO52))
42051 return x;
42052 Using the absolute value and copying back sign makes
42053 -0.0 -> -0.0 correct.
42054 xa2 = xa + TWO52 - TWO52;
42055 Compensate.
42056 dxa = xa2 - xa;
42057 if (dxa <= -0.5)
42058 xa2 += 1;
42059 else if (dxa > 0.5)
42060 xa2 -= 1;
42061 x2 = copysign (xa2, x);
42062 return x2;
42063 */
42069 /* Temporary for holding the result, initialized to the input
42070 operand to ease control flow. */
42074 /* xa = abs (operand1) */
42077 /* if (!isless (xa, TWO52)) goto label; */
42080 /* xa2 = xa + TWO52 - TWO52; */
42084 /* dxa = xa2 - xa; */
42087 /* generate 0.5, 1.0 and -0.5 */
42093 /* Compensate. */
42095 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42100 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42106 /* res = copysign (xa2, operand1) */
42113 }
42115 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42116 into OPERAND0. */
42117 void
42119 {
42120 /* C code for SSE variant we expand below.
42121 double xa = fabs (x), x2;
42122 if (!isless (xa, TWO52))
42123 return x;
42124 x2 = (double)(long)x;
42125 if (HONOR_SIGNED_ZEROS (mode))
42126 return copysign (x2, x);
42127 return x2;
42128 */
42134 /* Temporary for holding the result, initialized to the input
42135 operand to ease control flow. */
42139 /* xa = abs (operand1) */
42142 /* if (!isless (xa, TWO52)) goto label; */
42145 /* x = (double)(long)x */
42157 }
42159 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42160 into OPERAND0. */
42161 void
42163 {
42167 /* C code for SSE variant we expand below.
42168 double xa = fabs (x), x2;
42169 if (!isless (xa, TWO52))
42170 return x;
42171 xa2 = xa + TWO52 - TWO52;
42172 Compensate:
42173 if (xa2 > xa)
42174 xa2 -= 1.0;
42175 x2 = copysign (xa2, x);
42176 return x2;
42177 */
42181 /* Temporary for holding the result, initialized to the input
42182 operand to ease control flow. */
42186 /* xa = abs (operand1) */
42189 /* if (!isless (xa, TWO52)) goto label; */
42192 /* res = xa + TWO52 - TWO52; */
42197 /* generate 1.0 */
42200 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42208 /* res = copysign (res, operand1) */
42215 }
42217 /* Expand SSE sequence for computing round from OPERAND1 storing
42218 into OPERAND0. */
42219 void
42221 {
42222 /* C code for the stuff we're doing below:
42223 double xa = fabs (x);
42224 if (!isless (xa, TWO52))
42225 return x;
42226 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42227 return copysign (xa, x);
42228 */
42234 /* Temporary for holding the result, initialized to the input
42235 operand to ease control flow. */
42243 /* load nextafter (0.5, 0.0) */
42248 /* xa = xa + 0.5 */
42252 /* xa = (double)(int64_t)xa */
42257 /* res = copysign (xa, operand1) */
42264 }
42266 /* Expand SSE sequence for computing round
42267 from OP1 storing into OP0 using sse4 round insn. */
42268 void
42270 {
42279 {
42290 }
42292 /* round (a) = trunc (a + copysign (0.5, a)) */
42294 /* load nextafter (0.5, 0.0) */
42300 /* e1 = copysign (0.5, op1) */
42304 /* e2 = op1 + e1 */
42307 /* res = trunc (e2) */
42312 }
42313 \f
42315 /* Table of valid machine attributes. */
42317 {
42318 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
42319 affects_type_identity } */
42320 /* Stdcall attribute says callee is responsible for popping arguments
42321 if they are not variable. */
42324 /* Fastcall attribute says callee is responsible for popping arguments
42325 if they are not variable. */
42328 /* Thiscall attribute says callee is responsible for popping arguments
42329 if they are not variable. */
42332 /* Cdecl attribute says the callee is a normal C declaration */
42335 /* Regparm attribute specifies how many integer arguments are to be
42336 passed in registers. */
42339 /* Sseregparm attribute says we are using x86_64 calling conventions
42340 for FP arguments. */
42343 /* The transactional memory builtins are implicitly regparm or fastcall
42344 depending on the ABI. Override the generic do-nothing attribute that
42345 these builtins were declared with. */
42348 /* force_align_arg_pointer says this function realigns the stack at entry. */
42351 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42356 #endif
42361 #ifdef SUBTARGET_ATTRIBUTE_TABLE
42362 SUBTARGET_ATTRIBUTE_TABLE,
42363 #endif
42364 /* ms_abi and sysv_abi calling convention function attributes. */
42371 /* End element. */
42373 };
42375 /* Implement targetm.vectorize.builtin_vectorization_cost. */
42376 static int
42378 tree vectype,
42380 {
42384 {
42429 }
42430 }
42432 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
42433 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
42434 insn every time. */
42438 /* Initialize vselect_insn. */
42440 static void
42442 {
42444 rtx x;
42455 }
42457 /* Construct (set target (vec_select op0 (parallel perm))) and
42458 return true if that's a valid instruction in the active ISA. */
42460 static bool
42463 {
42489 }
42491 /* Similar, but generate a vec_concat from op0 and op1 as well. */
42493 static bool
42497 {
42499 rtx x;
42514 }
42516 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42517 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
42519 static bool
42521 {
42530 ;
42532 ;
42534 ;
42535 else
42538 /* This is a blend, not a permute. Elements must stay in their
42539 respective lanes. */
42541 {
42545 }
42550 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
42551 decision should be extracted elsewhere, so that we only try that
42552 sequence once all budget==3 options have been tried. */
42559 {
42583 /* See if bytes move in pairs so we can use pblendw with
42584 an immediate argument, rather than pblendvb with a vector
42585 argument. */
42588 {
42589 use_pblendvb:
42593 finish_pblendvb:
42599 else
42604 }
42609 /* FALLTHRU */
42611 do_subreg:
42618 /* See if bytes move in pairs. If not, vpblendvb must be used. */
42622 /* See if bytes move in quadruplets. If yes, vpblendd
42623 with immediate can be used. */
42628 {
42629 /* See if bytes move the same in both lanes. If yes,
42630 vpblendw with immediate can be used. */
42635 /* Use vpblendw. */
42640 }
42642 /* Use vpblendd. */
42649 /* See if words move in pairs. If yes, vpblendd can be used. */
42654 {
42655 /* See if words move the same in both lanes. If not,
42656 vpblendvb must be used. */
42659 {
42660 /* Use vpblendvb. */
42670 }
42672 /* Use vpblendw. */
42676 }
42678 /* Use vpblendd. */
42685 /* Use vpblendd. */
42693 }
42695 /* This matches five different patterns with the different modes. */
42703 }
42705 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42706 in terms of the variable form of vpermilps.
42708 Note that we will have already failed the immediate input vpermilps,
42709 which requires that the high and low part shuffle be identical; the
42710 variable form doesn't require that. */
42712 static bool
42714 {
42721 /* We can only permute within the 128-bit lane. */
42723 {
42727 }
42733 {
42736 /* Within each 128-bit lane, the elements of op0 are numbered
42737 from 0 and the elements of op1 are numbered from 4. */
42744 }
42751 }
42753 /* Return true if permutation D can be performed as VMODE permutation
42754 instead. */
42756 static bool
42758 {
42773 else
42779 }
42781 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
42782 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
42784 static bool
42786 {
42795 {
42797 {
42800 {
42804 /* Use vperm2i128 insn. The pattern uses
42805 V4DImode instead of V2TImode. */
42818 }
42820 }
42821 }
42822 else
42823 {
42825 {
42828 }
42830 {
42834 /* V4DImode should be already handled through
42835 expand_vselect by vpermq instruction. */
42842 {
42843 /* First see if vpermq can be used for
42844 V8SImode/V16HImode/V32QImode. */
42846 {
42854 {
42858 }
42860 }
42862 /* Next see if vpermd can be used. */
42865 }
42866 /* Or if vpermps can be used. */
42871 {
42872 /* vpshufb only works intra lanes, it is not
42873 possible to shuffle bytes in between the lanes. */
42877 }
42878 }
42879 else
42881 }
42889 else
42890 {
42896 else
42900 {
42904 }
42905 }
42916 {
42923 else
42925 }
42926 else
42927 {
42930 }
42935 }
42937 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
42938 in a single instruction. */
42940 static bool
42942 {
42946 /* Check plain VEC_SELECT first, because AVX has instructions that could
42947 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
42948 input where SEL+CONCAT may not. */
42950 {
42956 {
42962 }
42965 {
42969 }
42971 {
42972 /* Use vpbroadcast{b,w,d}. */
42975 {
42994 /* For other modes prefer other shuffles this function creates. */
42996 }
42998 {
43002 }
43003 }
43008 /* There are plenty of patterns in sse.md that are written for
43009 SEL+CONCAT and are not replicated for a single op. Perhaps
43010 that should be changed, to avoid the nastiness here. */
43012 /* Recognize interleave style patterns, which means incrementing
43013 every other permutation operand. */
43015 {
43018 }
43023 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43025 {
43027 {
43032 }
43037 }
43038 }
43040 /* Finally, try the fully general two operand permute. */
43045 /* Recognize interleave style patterns with reversed operands. */
43047 {
43049 {
43053 else
43056 }
43061 }
43063 /* Try the SSE4.1 blend variable merge instructions. */
43067 /* Try one of the AVX vpermil variable permutations. */
43071 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43072 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43076 /* Try the AVX512F vpermi2 instructions. */
43090 }
43092 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43093 in terms of a pair of pshuflw + pshufhw instructions. */
43095 static bool
43097 {
43105 /* The two permutations only operate in 64-bit lanes. */
43116 /* Emit the pshuflw. */
43123 /* Emit the pshufhw. */
43131 }
43133 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43134 the permutation using the SSSE3 palignr instruction. This succeeds
43135 when all of the elements in PERM fit within one vector and we merely
43136 need to shift them down so that a single vector permutation has a
43137 chance to succeed. */
43139 static bool
43141 {
43148 /* Even with AVX, palignr only operates on 128-bit vectors. */
43154 {
43160 }
43164 /* Given that we have SSSE3, we know we'll be able to implement the
43165 single operand permutation after the palignr with pshufb. */
43180 {
43185 }
43187 /* Test for the degenerate case where the alignment by itself
43188 produces the desired permutation. */
43190 {
43193 }
43199 }
43201 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
43202 the permutation using the SSE4_1 pblendv instruction. Potentially
43203 reduces permutaion from 2 pshufb and or to 1 pshufb and pblendv. */
43205 static bool
43207 {
43213 /* Use the same checks as in expand_vec_perm_blend, but skipping
43214 AVX2 as it requires more than 2 instructions for general case. */
43218 ;
43220 ;
43221 else
43224 /* Figure out where permutation elements stay not in their
43225 respective lanes. */
43227 {
43231 }
43232 /* We can pblend the part where elements stay not in their
43233 respective lanes only when these elements are all in one
43234 half of a permutation.
43235 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
43236 lanes, but both 8 and 9 >= 8
43237 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
43238 respective lanes and 8 >= 8, but 2 not. */
43244 /* First we apply one operand permutation to the part where
43245 elements stay not in their respective lanes. */
43249 else
43259 /* Next we put permuted elements into their positions. */
43263 else
43273 }
43277 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43278 a two vector permutation into a single vector permutation by using
43279 an interleave operation to merge the vectors. */
43281 static bool
43283 {
43288 rtx seq;
43292 {
43295 }
43297 {
43300 /* For 32-byte modes allow even d->one_operand_p.
43301 The lack of cross-lane shuffling in some instructions
43302 might prevent a single insn shuffle. */
43305 /* If expand_vec_perm_interleave3 can expand this into
43306 a 3 insn sequence, give up and let it be expanded as
43307 3 insn sequence. While that is one insn longer,
43308 it doesn't need a memory operand and in the common
43309 case that both interleave low and high permutations
43310 with the same operands are adjacent needs 4 insns
43311 for both after CSE. */
43314 }
43315 else
43318 /* Examine from whence the elements come. */
43327 {
43330 /* Split the two input vectors into 4 halves. */
43336 /* If the elements from the low halves use interleave low, and similarly
43337 for interleave high. If the elements are from mis-matched halves, we
43338 can use shufps for V4SF/V4SI or do a DImode shuffle. */
43340 {
43341 /* punpckl* */
43343 {
43348 }
43351 }
43353 {
43354 /* punpckh* */
43356 {
43361 }
43364 }
43366 {
43367 /* shufps */
43369 {
43374 }
43376 {
43377 /* shufpd */
43382 }
43383 }
43385 {
43386 /* shufps */
43388 {
43393 }
43395 {
43396 /* shufpd */
43401 }
43402 }
43403 else
43405 }
43406 else
43407 {
43412 /* Split the two input vectors into 8 quarters. */
43418 {
43421 }
43424 {
43428 }
43430 {
43433 }
43436 {
43438 {
43439 /* Attempt to increase the likelihood that dfinal
43440 shuffle will be intra-lane. */
43444 }
43446 /* vperm2f128 or vperm2i128. */
43448 {
43453 }
43458 {
43462 {
43465 }
43466 }
43467 }
43472 {
43473 /* vpunpckl* */
43475 {
43484 }
43485 }
43488 {
43489 /* vpunpckh* */
43491 {
43500 }
43501 }
43502 else
43504 }
43506 /* Use the remapping array set up above to move the elements from their
43507 swizzled locations into their final destinations. */
43510 {
43513 /* If same_halves is true, both halves of the remapped vector are the
43514 same. Avoid cross-lane accesses if possible. */
43516 {
43519 }
43520 else
43522 }
43524 {
43527 }
43531 /* Test if the final remap can be done with a single insn. For V4SFmode or
43532 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
43545 {
43548 }
43555 }
43557 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43558 a single vector cross-lane permutation into vpermq followed
43559 by any of the single insn permutations. */
43561 static bool
43563 {
43577 {
43580 }
43583 {
43588 }
43601 {
43608 }
43615 {
43620 ;
43623 else
43625 }
43634 }
43636 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
43637 a vector permutation using two instructions, vperm2f128 resp.
43638 vperm2i128 followed by any single in-lane permutation. */
43640 static bool
43642 {
43656 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
43657 immediate. For perm < 16 the second permutation uses
43658 d->op0 as first operand, for perm >= 16 it uses d->op1
43659 as first operand. The second operand is the result of
43660 vperm2[fi]128. */
43662 {
43663 /* Ignore permutations which do not move anything cross-lane. */
43665 {
43666 /* The second shuffle for e.g. V4DFmode has
43667 0123 and ABCD operands.
43668 Ignore AB23, as 23 is already in the second lane
43669 of the first operand. */
43671 /* And 01CD, as 01 is in the first lane of the first
43672 operand. */
43674 /* And 4567, as then the vperm2[fi]128 doesn't change
43675 anything on the original 4567 second operand. */
43677 }
43678 else
43679 {
43680 /* The second shuffle for e.g. V4DFmode has
43681 4567 and ABCD operands.
43682 Ignore AB67, as 67 is already in the second lane
43683 of the first operand. */
43685 /* And 45CD, as 45 is in the first lane of the first
43686 operand. */
43688 /* And 0123, as then the vperm2[fi]128 doesn't change
43689 anything on the original 0123 first operand. */
43691 }
43694 {
43700 else
43702 }
43705 {
43709 }
43710 else
43714 {
43718 /* Found a usable second shuffle. dfirst will be
43719 vperm2f128 on d->op0 and d->op1. */
43730 /* And dsecond is some single insn shuffle, taking
43731 d->op0 and result of vperm2f128 (if perm < 16) or
43732 d->op1 and result of vperm2f128 (otherwise). */
43741 }
43743 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
43746 }
43749 }
43751 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43752 a two vector permutation using 2 intra-lane interleave insns
43753 and cross-lane shuffle for 32-byte vectors. */
43755 static bool
43757 {
43764 ;
43766 ;
43767 else
43782 {
43786 else
43792 else
43798 else
43804 else
43810 else
43816 else
43821 }
43825 }
43827 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
43828 a single vector permutation using a single intra-lane vector
43829 permutation, vperm2f128 swapping the lanes and vblend* insn blending
43830 the non-swapped and swapped vectors together. */
43832 static bool
43834 {
43837 rtx seq;
43842 || TARGET_AVX2
43851 {
43858 }
43893 }
43895 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
43896 permutation using two vperm2f128, followed by a vshufpd insn blending
43897 the two vectors together. */
43899 static bool
43901 {
43944 }
43946 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
43947 permutation with two pshufb insns and an ior. We should have already
43948 failed all two instruction sequences. */
43950 static bool
43952 {
43966 /* Generate two permutation masks. If the required element is within
43967 the given vector it is shuffled into the proper lane. If the required
43968 element is in the other vector, force a zero into the lane by setting
43969 bit 7 in the permutation mask. */
43972 {
43979 {
43982 }
43983 }
44007 }
44009 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
44010 with two vpshufb insns, vpermq and vpor. We should have already failed
44011 all two or three instruction sequences. */
44013 static bool
44015 {
44030 /* Generate two permutation masks. If the required element is within
44031 the same lane, it is shuffled in. If the required element from the
44032 other lane, force a zero by setting bit 7 in the permutation mask.
44033 In the other mask the mask has non-negative elements if element
44034 is requested from the other lane, but also moved to the other lane,
44035 so that the result of vpshufb can have the two V2TImode halves
44036 swapped. */
44039 {
44044 {
44047 }
44048 }
44057 /* Swap the 128-byte lanes of h into hp. */
44061 const1_rtx));
44078 }
44080 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44081 and extract-odd permutations of two V32QImode and V16QImode operand
44082 with two vpshufb insns, vpor and vpermq. We should have already
44083 failed all two or three instruction sequences. */
44085 static bool
44087 {
44106 /* Generate two permutation masks. In the first permutation mask
44107 the first quarter will contain indexes for the first half
44108 of the op0, the second quarter will contain bit 7 set, third quarter
44109 will contain indexes for the second half of the op0 and the
44110 last quarter bit 7 set. In the second permutation mask
44111 the first quarter will contain bit 7 set, the second quarter
44112 indexes for the first half of the op1, the third quarter bit 7 set
44113 and last quarter indexes for the second half of the op1.
44114 I.e. the first mask e.g. for V32QImode extract even will be:
44115 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44116 (all values masked with 0xf except for -128) and second mask
44117 for extract even will be
44118 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44121 {
44127 {
44130 }
44131 }
44150 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44158 }
44160 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44161 and extract-odd permutations. */
44163 static bool
44165 {
44169 {
44176 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44180 /* Now an unpck[lh]pd will produce the result required. */
44183 else
44189 {
44198 /* Shuffle within the 128-bit lanes to produce:
44199 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44203 /* Shuffle the lanes around to produce:
44204 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44208 /* Shuffle within the 128-bit lanes to produce:
44209 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44212 /* Shuffle within the 128-bit lanes to produce:
44213 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44216 /* Shuffle the lanes around to produce:
44217 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44220 }
44227 /* These are always directly implementable by expand_vec_perm_1. */
44233 else
44234 {
44237 /* We need 2*log2(N)-1 operations to achieve odd/even
44238 with interleave. */
44247 else
44250 }
44256 else
44257 {
44271 else
44274 }
44283 {
44288 else
44293 {
44298 }
44300 }
44308 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44312 /* Now an vpunpck[lh]qdq will produce the result required. */
44315 else
44322 {
44327 else
44332 {
44337 }
44339 }
44350 /* Shuffle the lanes around into
44351 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
44359 /* Swap the 2nd and 3rd position in each lane into
44360 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
44366 /* Now an vpunpck[lh]qdq will produce
44367 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
44371 else
44380 }
44383 }
44385 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44386 extract-even and extract-odd permutations. */
44388 static bool
44390 {
44402 }
44404 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
44405 permutations. We assume that expand_vec_perm_1 has already failed. */
44407 static bool
44409 {
44417 {
44420 /* These are special-cased in sse.md so that we can optionally
44421 use the vbroadcast instruction. They expand to two insns
44422 if the input happens to be in a register. */
44429 /* These are always implementable using standard shuffle patterns. */
44434 /* These can be implemented via interleave. We save one insn by
44435 stopping once we have promoted to V4SImode and then use pshufd. */
44438 do
44439 {
44440 rtx dest;
44446 {
44450 }
44457 }
44472 /* For AVX2 broadcasts of the first element vpbroadcast* or
44473 vpermq should be used by expand_vec_perm_1. */
44479 }
44480 }
44482 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
44483 broadcast permutations. */
44485 static bool
44487 {
44499 }
44501 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
44502 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
44503 all the shorter instruction sequences. */
44505 static bool
44507 {
44523 /* Generate 4 permutation masks. If the required element is within
44524 the same lane, it is shuffled in. If the required element from the
44525 other lane, force a zero by setting bit 7 in the permutation mask.
44526 In the other mask the mask has non-negative elements if element
44527 is requested from the other lane, but also moved to the other lane,
44528 so that the result of vpshufb can have the two V2TImode halves
44529 swapped. */
44532 {
44537 }
44543 {
44551 }
44554 {
44556 {
44559 }
44566 }
44568 /* Swap the 128-byte lanes of h[X]. */
44570 {
44576 const1_rtx));
44578 }
44581 {
44583 {
44586 }
44592 }
44595 {
44597 {
44601 }
44604 }
44614 }
44616 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
44617 With all of the interface bits taken care of, perform the expansion
44618 in D and return true on success. */
44620 static bool
44622 {
44623 /* Try a single instruction expansion. */
44627 /* Try sequences of two instructions. */
44650 /* Try sequences of three instructions. */
44664 /* Try sequences of four instructions. */
44672 /* ??? Look for narrow permutations whose element orderings would
44673 allow the promotion to a wider mode. */
44675 /* ??? Look for sequences of interleave or a wider permute that place
44676 the data into the correct lanes for a half-vector shuffle like
44677 pshuf[lh]w or vpermilps. */
44679 /* ??? Look for sequences of interleave that produce the desired results.
44680 The combinatorics of punpck[lh] get pretty ugly... */
44685 /* Even longer sequences. */
44690 }
44692 /* If a permutation only uses one operand, make it clear. Returns true
44693 if the permutation references both operands. */
44695 static bool
44697 {
44705 {
44711 {
44714 }
44715 /* The elements of PERM do not suggest that only the first operand
44716 is used, but both operands are identical. Allow easier matching
44717 of the permutation by folding the permutation into the single
44718 input vector. */
44719 /* FALLTHRU */
44730 }
44733 }
44735 bool
44737 {
44742 rtx sel;
44759 {
44764 }
44771 /* If the selector says both arguments are needed, but the operands are the
44772 same, the above tried to expand with one_operand_p and flattened selector.
44773 If that didn't work, retry without one_operand_p; we succeeded with that
44774 during testing. */
44776 {
44780 }
44783 }
44785 /* Implement targetm.vectorize.vec_perm_const_ok. */
44787 static bool
44790 {
44799 /* Given sufficient ISA support we can just return true here
44800 for selected vector modes. */
44803 /* All implementable with a single vpermi2 insn. */
44806 {
44807 /* All implementable with a single vpperm insn. */
44810 /* All implementable with 2 pshufb + 1 ior. */
44813 /* All implementable with shufpd or unpck[lh]pd. */
44816 }
44818 /* Extract the values from the vector CST into the permutation
44819 array in D. */
44822 {
44826 }
44828 /* For all elements from second vector, fold the elements to first. */
44833 /* Check whether the mask can be applied to the vector type. */
44836 /* Implementable with shufps or pshufd. */
44840 /* Otherwise we have to go through the motions and see if we can
44841 figure out how to generate the requested permutation. */
44852 }
44854 void
44856 {
44871 /* We'll either be able to implement the permutation directly... */
44875 /* ... or we use the special-case patterns. */
44877 }
44879 static void
44881 {
44896 {
44899 }
44901 /* Note that for AVX this isn't one instruction. */
44904 }
44907 /* Expand a vector operation CODE for a V*QImode in terms of the
44908 same operation on V*HImode. */
44910 void
44912 {
44924 {
44937 }
44941 {
44943 /* Unpack data such that we've got a source byte in each low byte of
44944 each word. We don't care what goes into the high byte of each word.
44945 Rather than trying to get zero in there, most convenient is to let
44946 it be a copy of the low byte. */
44951 /* FALLTHRU */
44963 /* FALLTHRU */
44973 }
44975 /* Perform the operation. */
44982 /* Merge the data back into the right place. */
44992 {
44993 /* For SSE2, we used an full interleave, so the desired
44994 results are in the even elements. */
44997 }
44998 else
44999 {
45000 /* For AVX, the interleave used above was not cross-lane. So the
45001 extraction is evens but with the second and third quarter swapped.
45002 Happily, that is even one insn shorter than even extraction. */
45005 }
45012 }
45014 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
45015 if op is CONST_VECTOR with all odd elements equal to their
45016 preceding element. */
45018 static bool
45020 {
45030 }
45032 void
45035 {
45038 rtx x;
45046 /* We only play even/odd games with vectors of SImode. */
45049 /* If we're looking for the odd results, shift those members down to
45050 the even slots. For some cpus this is faster than a PSHUFD. */
45052 {
45053 /* For XOP use vpmacsdqh, but only for smult, as it is only
45054 signed. */
45056 {
45060 }
45071 }
45074 {
45077 else
45079 }
45081 {
45084 else
45086 }
45091 else
45092 {
45095 /* The easiest way to implement this without PMULDQ is to go through
45096 the motions as if we are performing a full 64-bit multiply. With
45097 the exception that we need to do less shuffling of the elements. */
45099 /* Compute the sign-extension, aka highparts, of the two operands. */
45105 /* Multiply LO(A) * HI(B), and vice-versa. */
45111 /* Multiply LO(A) * LO(B). */
45115 /* Combine and shift the highparts into place. */
45120 /* Combine high and low parts. */
45123 }
45125 }
45127 void
45130 {
45136 {
45141 {
45142 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45143 shuffle the elements once so that all elements are in the right
45144 place for immediate use: { A C B D }. */
45149 }
45150 else
45151 {
45152 /* Put the elements into place for the multiply. */
45156 }
45161 /* Shuffle the elements between the lanes. After this we
45162 have { A B E F | C D G H } for each operand. */
45172 /* Shuffle the elements within the lanes. After this we
45173 have { A A B B | C C D D } or { E E F F | G G H H }. */
45211 }
45212 }
45214 void
45216 {
45226 /* Move the results in element 2 down to element 1; we don't care
45227 what goes in elements 2 and 3. Then we can merge the parts
45228 back together with an interleave.
45230 Note that two other sequences were tried:
45231 (1) Use interleaves at the start instead of psrldq, which allows
45232 us to use a single shufps to merge things back at the end.
45233 (2) Use shufps here to combine the two vectors, then pshufd to
45234 put the elements in the correct order.
45235 In both cases the cost of the reformatting stall was too high
45236 and the overall sequence slower. */
45247 }
45249 void
45251 {
45256 {
45257 /* op1: A,B,C,D, op2: E,F,G,H */
45266 /* t1: B,A,D,C */
45273 /* t2: (B*E),(A*F),(D*G),(C*H) */
45276 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45279 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45282 /* Multiply lower parts and add all */
45289 }
45290 else
45291 {
45296 {
45299 }
45301 {
45304 }
45306 {
45309 }
45310 else
45314 /* Multiply low parts. */
45318 /* Shift input vectors right 32 bits so we can multiply high parts. */
45323 /* Multiply high parts by low parts. */
45329 /* Combine and shift the highparts back. */
45333 /* Combine high and low parts. */
45335 }
45339 }
45341 /* Calculate integer abs() using only SSE2 instructions. */
45343 void
45345 {
45350 {
45351 /* For 32-bit signed integer X, the best way to calculate the absolute
45352 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
45364 /* For 16-bit signed integer X, the best way to calculate the absolute
45365 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
45373 /* For 8-bit signed integer X, the best way to calculate the absolute
45374 value of X is min ((unsigned char) X, (unsigned char) (-X)),
45375 as SSE2 provides the PMINUB insn. */
45385 }
45389 }
45391 /* Expand an insert into a vector register through pinsr insn.
45392 Return true if successful. */
45394 bool
45396 {
45404 {
45407 }
45413 {
45418 {
45425 {
45457 }
45471 }
45475 }
45476 }
45477 \f
45478 /* This function returns the calling abi specific va_list type node.
45479 It returns the FNDECL specific va_list type. */
45481 static tree
45483 {
45490 else
45492 }
45494 /* Returns the canonical va_list type specified by TYPE. If there
45495 is no valid TYPE provided, it return NULL_TREE. */
45497 static tree
45499 {
45502 /* Resolve references and pointers to va_list type. */
45511 {
45516 {
45517 /* If va_list is an array type, the argument may have decayed
45518 to a pointer type, e.g. by being passed to another function.
45519 In that case, unwrap both types so that we can compare the
45520 underlying records. */
45523 {
45526 }
45527 }
45534 {
45535 /* If va_list is an array type, the argument may have decayed
45536 to a pointer type, e.g. by being passed to another function.
45537 In that case, unwrap both types so that we can compare the
45538 underlying records. */
45541 {
45544 }
45545 }
45552 {
45553 /* If va_list is an array type, the argument may have decayed
45554 to a pointer type, e.g. by being passed to another function.
45555 In that case, unwrap both types so that we can compare the
45556 underlying records. */
45559 {
45562 }
45563 }
45567 }
45569 }
45571 /* Iterate through the target-specific builtin types for va_list.
45572 IDX denotes the iterator, *PTREE is set to the result type of
45573 the va_list builtin, and *PNAME to its internal type.
45574 Returns zero if there is no element for this index, otherwise
45575 IDX should be increased upon the next call.
45576 Note, do not iterate a base builtin's name like __builtin_va_list.
45577 Used from c_common_nodes_and_builtins. */
45579 static int
45581 {
45583 {
45585 {
45598 }
45599 }
45602 }
45604 #undef TARGET_SCHED_DISPATCH
45605 #define TARGET_SCHED_DISPATCH has_dispatch
45606 #undef TARGET_SCHED_DISPATCH_DO
45607 #define TARGET_SCHED_DISPATCH_DO do_dispatch
45608 #undef TARGET_SCHED_REASSOCIATION_WIDTH
45609 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
45610 #undef TARGET_SCHED_REORDER
45611 #define TARGET_SCHED_REORDER ix86_sched_reorder
45612 #undef TARGET_SCHED_ADJUST_PRIORITY
45613 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
45614 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
45615 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
45616 ix86_dependencies_evaluation_hook
45618 /* The size of the dispatch window is the total number of bytes of
45619 object code allowed in a window. */
45620 #define DISPATCH_WINDOW_SIZE 16
45622 /* Number of dispatch windows considered for scheduling. */
45623 #define MAX_DISPATCH_WINDOWS 3
45625 /* Maximum number of instructions in a window. */
45626 #define MAX_INSN 4
45628 /* Maximum number of immediate operands in a window. */
45629 #define MAX_IMM 4
45631 /* Maximum number of immediate bits allowed in a window. */
45632 #define MAX_IMM_SIZE 128
45634 /* Maximum number of 32 bit immediates allowed in a window. */
45635 #define MAX_IMM_32 4
45637 /* Maximum number of 64 bit immediates allowed in a window. */
45638 #define MAX_IMM_64 2
45640 /* Maximum total of loads or prefetches allowed in a window. */
45641 #define MAX_LOAD 2
45643 /* Maximum total of stores allowed in a window. */
45644 #define MAX_STORE 1
45646 #undef BIG
45647 #define BIG 100
45650 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
45653 disp_load,
45654 disp_store,
45655 disp_load_store,
45656 disp_prefetch,
45657 disp_imm,
45658 disp_imm_32,
45659 disp_imm_64,
45660 disp_branch,
45661 disp_cmp,
45662 disp_jcc,
45663 disp_last
45664 };
45666 /* Number of allowable groups in a dispatch window. It is an array
45667 indexed by dispatch_group enum. 100 is used as a big number,
45668 because the number of these kind of operations does not have any
45669 effect in dispatch window, but we need them for other reasons in
45670 the table. */
45673 };
45679 };
45681 /* Instruction path. */
45687 last_path
45688 };
45690 /* sched_insn_info defines a window to the instructions scheduled in
45691 the basic block. It contains a pointer to the insn_info table and
45692 the instruction scheduled.
45694 Windows are allocated for each basic block and are linked
45695 together. */
45697 rtx insn;
45704 /* Linked list of dispatch windows. This is a two way list of
45705 dispatch windows of a basic block. It contains information about
45706 the number of uops in the window and the total number of
45707 instructions and of bytes in the object code for this dispatch
45708 window. */
45726 /* Immediate valuse used in an insn. */
45728 {
45737 /* Get dispatch group of insn. */
45739 static enum dispatch_group
45741 {
45757 }
45759 /* Return true if insn is a compare instruction. */
45761 static bool
45763 {
45771 }
45773 /* Return true if a dispatch violation encountered. */
45775 static bool
45777 {
45781 }
45783 /* Return true if insn is a branch instruction. */
45785 static bool
45787 {
45789 }
45791 /* Return true if insn is a prefetch instruction. */
45793 static bool
45795 {
45797 }
45799 /* This function initializes a dispatch window and the list container holding a
45800 pointer to the window. */
45802 static void
45804 {
45810 else
45828 {
45834 }
45836 }
45838 /* This function allocates and initializes a dispatch window and the
45839 list container holding a pointer to the window. */
45843 {
45848 }
45850 /* This routine initializes the dispatch scheduling information. It
45851 initiates building dispatch scheduler tables and constructs the
45852 first dispatch window. */
45854 static void
45856 {
45857 /* Allocate a dispatch list and a window. */
45862 }
45864 /* This function returns true if a branch is detected. End of a basic block
45865 does not have to be a branch, but here we assume only branches end a
45866 window. */
45868 static bool
45870 {
45872 }
45874 /* This function is called when the end of a window processing is reached. */
45876 static void
45878 {
45881 {
45886 }
45888 }
45890 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
45891 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
45892 for 48 bytes of instructions. Note that these windows are not dispatch
45893 windows that their sizes are DISPATCH_WINDOW_SIZE. */
45897 {
45899 {
45904 }
45910 }
45912 /* Increment the number of immediate operands of an instruction. */
45914 static int
45916 {
45921 {
45928 else
45939 {
45942 }
45947 }
45950 }
45952 /* Compute number of immediate operands of an instruction. */
45954 static void
45956 {
45959 }
45961 /* Return total size of immediate operands of an instruction along with number
45962 of corresponding immediate-operands. It initializes its parameters to zero
45963 befor calling FIND_CONSTANT.
45964 INSN is the input instruction. IMM is the total of immediates.
45965 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
45966 bit immediates. */
45968 static int
45970 {
45978 }
45980 /* This function indicates if an operand of an instruction is an
45981 immediate. */
45983 static bool
45985 {
45994 }
45996 /* Return single or double path for instructions. */
45998 static enum insn_path
46000 {
46010 }
46012 /* Return insn dispatch group. */
46014 static enum dispatch_group
46016 {
46034 }
46036 /* Count number of GROUP restricted instructions in a dispatch
46037 window WINDOW_LIST. */
46039 static int
46041 {
46052 {
46071 }
46084 }
46086 /* This function returns true if insn satisfies dispatch rules on the
46087 last window scheduled. */
46089 static bool
46091 {
46099 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46100 instructions should be given the lowest priority in the
46101 scheduling process in Haifa scheduler to make sure they will be
46102 scheduled in the same dispatch window as the reference to them. */
46106 /* Check nonrestricted. */
46110 /* Get last dispatch window. */
46115 {
46120 /* Window 1 is full. Go for next window. */
46122 }
46129 /* See if it fits in the first window. */
46131 {
46132 /* The first widow should have only single and double path
46133 uops. */
46139 }
46141 }
46143 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46144 dispatch window WINDOW_LIST. */
46146 static void
46148 {
46166 /* Initialize window with new instruction. */
46187 {
46190 }
46191 }
46193 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46194 If the total bytes of instructions or the number of instructions in
46195 the window exceed allowable, it allocates a new window. */
46197 static void
46199 {
46222 /* Get the last dispatch window. */
46230 else
46233 /* If current window is full, get a new window.
46234 Window number zero is full, if MAX_INSN uops are scheduled in it.
46235 Window number one is full, if window zero's bytes plus window
46236 one's bytes is 32, or if the bytes of the new instruction added
46237 to the total makes it greater than 48, or it has already MAX_INSN
46238 instructions in it. */
46247 {
46250 }
46253 {
46257 {
46260 }
46261 }
46263 {
46268 {
46271 }
46274 }
46275 else
46279 {
46280 /* End of basic block is reached do end-basic-block process. */
46283 }
46284 }
46286 /* Print the dispatch window, WINDOW_NUM, to FILE. */
46288 DEBUG_FUNCTION static void
46290 {
46296 else
46310 {
46313 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
46319 }
46320 }
46322 /* Print to stdout a dispatch window. */
46324 DEBUG_FUNCTION void
46326 {
46328 }
46330 /* Print INSN dispatch information to FILE. */
46332 DEBUG_FUNCTION static void
46334 {
46357 }
46359 /* Print to STDERR the status of the ready list with respect to
46360 dispatch windows. */
46362 DEBUG_FUNCTION void
46364 {
46372 }
46374 /* This routine is the driver of the dispatch scheduler. */
46376 static void
46378 {
46383 }
46385 /* Return TRUE if Dispatch Scheduling is supported. */
46387 static bool
46389 {
46393 {
46409 }
46412 }
46414 /* Implementation of reassociation_width target hook used by
46415 reassoc phase to identify parallelism level in reassociated
46416 tree. Statements tree_code is passed in OPC. Arguments type
46417 is passed in MODE.
46419 Currently parallel reassociation is enabled for Atom
46420 processors only and we set reassociation width to be 2
46421 because Atom may issue up to 2 instructions per cycle.
46423 Return value should be fixed if parallel reassociation is
46424 enabled for other processors. */
46426 static int
46429 {
46438 }
46440 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
46441 place emms and femms instructions. */
46443 static enum machine_mode
46445 {
46450 {
46467 else
46479 /* FALLTHRU */
46483 }
46484 }
46486 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
46487 vectors. If AVX512F is enabled then try vectorizing with 512bit,
46488 256bit and 128bit vectors. */
46490 static unsigned int
46492 {
46495 }
46497 \f
46499 /* Return class of registers which could be used for pseudo of MODE
46500 and of class RCLASS for spilling instead of memory. Return NO_REGS
46501 if it is not possible or non-profitable. */
46502 static reg_class_t
46504 {
46510 }
46512 /* Implement targetm.vectorize.init_cost. */
46516 {
46520 }
46522 /* Implement targetm.vectorize.add_stmt_cost. */
46524 static unsigned
46528 {
46535 /* Statements in an inner loop relative to the loop being
46536 vectorized are weighted more heavily. The value here is
46537 arbitrary and could potentially be improved with analysis. */
46543 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
46544 for Silvermont as it has out of order integer pipeline and can execute
46545 2 scalar instruction per tick, but has in order SIMD pipeline. */
46548 {
46552 }
46557 }
46559 /* Implement targetm.vectorize.finish_cost. */
46561 static void
46564 {
46569 }
46571 /* Implement targetm.vectorize.destroy_cost_data. */
46573 static void
46575 {
46577 }
46579 /* Validate target specific memory model bits in VAL. */
46581 static unsigned HOST_WIDE_INT
46583 {
46590 {
46594 }
46597 {
46601 }
46603 {
46607 }
46609 }
46611 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
46612 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
46613 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
46614 or number of vecsize_mangle variants that should be emitted. */
46616 static int
46620 {
46627 {
46631 }
46636 {
46643 /* case SCmode: */
46644 /* case DCmode: */
46650 }
46652 tree t;
46656 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
46658 {
46665 /* case SCmode: */
46666 /* case DCmode: */
46672 }
46675 {
46676 /* Parse here processor clause. If not present, default to 'b'. */
46678 }
46680 {
46681 /* If the function isn't exported, we can pick up just one ISA
46682 for the clones. */
46687 else
46690 }
46691 else
46692 {
46695 }
46697 {
46710 }
46712 {
46715 else
46720 }
46722 }
46724 /* Add target attribute to SIMD clone NODE if needed. */
46726 static void
46728 {
46732 {
46747 }
46757 }
46759 /* If SIMD clone NODE can't be used in a vectorized loop
46760 in current function, return -1, otherwise return a badness of using it
46761 (0 if it is most desirable from vecsize_mangle point of view, 1
46762 slightly less desirable, etc.). */
46764 static int
46766 {
46768 {
46786 }
46787 }
46789 /* This function gives out the number of memory references.
46790 This value determines the unrolling factor for
46791 bdver3 and bdver4 architectures. */
46793 static int
46795 {
46797 {
46806 else
46808 }
46810 }
46812 /* This function adjusts the unroll factor based on
46813 the hardware capabilities. For ex, bdver3 has
46814 a loop buffer which makes unrolling of smaller
46815 loops less important. This function decides the
46816 unroll factor using number of memory references
46817 (value 32 is used) as a heuristic. */
46819 static unsigned
46821 {
46823 rtx insn;
46830 /* Count the number of memory references within the loop body. */
46833 {
46837 }
46844 }
46847 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
46849 static bool
46851 {
46852 /* For x87 floating point with standard excess precision handling,
46853 there is no adddf3 pattern (since x87 floating point only has
46854 XFmode operations) so the default hook implementation gets this
46855 wrong. */
46857 }
46859 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
46861 static void
46863 {
46868 {
46883 hold_fnclex);
46897 }
46899 {
46908 mxcsr_orig_var,
46918 ldmxcsr_hold_call);
46921 else
46926 ldmxcsr_clear_call);
46927 else
46931 stxmcsr_update_call);
46933 {
46939 exceptions_assign);
46940 }
46941 else
46946 ldmxcsr_update_call);
46947 }
46948 tree atomic_feraiseexcept
46953 atomic_feraiseexcept_call);
46954 }
46956 /* Initialize the GCC target structure. */
46957 #undef TARGET_RETURN_IN_MEMORY
46958 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
46960 #undef TARGET_LEGITIMIZE_ADDRESS
46961 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
46963 #undef TARGET_ATTRIBUTE_TABLE
46964 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
46965 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
46966 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
46967 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46968 # undef TARGET_MERGE_DECL_ATTRIBUTES
46969 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
46970 #endif
46972 #undef TARGET_COMP_TYPE_ATTRIBUTES
46973 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
46975 #undef TARGET_INIT_BUILTINS
46976 #define TARGET_INIT_BUILTINS ix86_init_builtins
46977 #undef TARGET_BUILTIN_DECL
46978 #define TARGET_BUILTIN_DECL ix86_builtin_decl
46979 #undef TARGET_EXPAND_BUILTIN
46980 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
46982 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
46983 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
46984 ix86_builtin_vectorized_function
46986 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
46987 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
46989 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
46990 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
46992 #undef TARGET_VECTORIZE_BUILTIN_GATHER
46993 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
46995 #undef TARGET_BUILTIN_RECIPROCAL
46996 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
46998 #undef TARGET_ASM_FUNCTION_EPILOGUE
46999 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
47001 #undef TARGET_ENCODE_SECTION_INFO
47002 #ifndef SUBTARGET_ENCODE_SECTION_INFO
47003 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
47004 #else
47005 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
47006 #endif
47008 #undef TARGET_ASM_OPEN_PAREN
47010 #undef TARGET_ASM_CLOSE_PAREN
47013 #undef TARGET_ASM_BYTE_OP
47014 #define TARGET_ASM_BYTE_OP ASM_BYTE
47016 #undef TARGET_ASM_ALIGNED_HI_OP
47017 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
47018 #undef TARGET_ASM_ALIGNED_SI_OP
47019 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
47020 #ifdef ASM_QUAD
47021 #undef TARGET_ASM_ALIGNED_DI_OP
47022 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
47023 #endif
47025 #undef TARGET_PROFILE_BEFORE_PROLOGUE
47026 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
47028 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
47029 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
47031 #undef TARGET_ASM_UNALIGNED_HI_OP
47032 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
47033 #undef TARGET_ASM_UNALIGNED_SI_OP
47034 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
47035 #undef TARGET_ASM_UNALIGNED_DI_OP
47036 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
47038 #undef TARGET_PRINT_OPERAND
47039 #define TARGET_PRINT_OPERAND ix86_print_operand
47040 #undef TARGET_PRINT_OPERAND_ADDRESS
47041 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
47042 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
47043 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
47044 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
47045 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
47047 #undef TARGET_SCHED_INIT_GLOBAL
47048 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
47049 #undef TARGET_SCHED_ADJUST_COST
47050 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
47051 #undef TARGET_SCHED_ISSUE_RATE
47052 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
47053 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
47054 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
47055 ia32_multipass_dfa_lookahead
47056 #undef TARGET_SCHED_MACRO_FUSION_P
47057 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
47058 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
47059 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
47061 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
47062 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
47064 #undef TARGET_MEMMODEL_CHECK
47065 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
47067 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
47068 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
47070 #ifdef HAVE_AS_TLS
47071 #undef TARGET_HAVE_TLS
47072 #define TARGET_HAVE_TLS true
47073 #endif
47074 #undef TARGET_CANNOT_FORCE_CONST_MEM
47075 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
47076 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
47077 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
47079 #undef TARGET_DELEGITIMIZE_ADDRESS
47080 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
47082 #undef TARGET_MS_BITFIELD_LAYOUT_P
47083 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
47085 #if TARGET_MACHO
47086 #undef TARGET_BINDS_LOCAL_P
47087 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
47088 #endif
47089 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47090 #undef TARGET_BINDS_LOCAL_P
47091 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
47092 #endif
47094 #undef TARGET_ASM_OUTPUT_MI_THUNK
47095 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47096 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47097 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47099 #undef TARGET_ASM_FILE_START
47100 #define TARGET_ASM_FILE_START x86_file_start
47102 #undef TARGET_OPTION_OVERRIDE
47103 #define TARGET_OPTION_OVERRIDE ix86_option_override
47105 #undef TARGET_REGISTER_MOVE_COST
47106 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47107 #undef TARGET_MEMORY_MOVE_COST
47108 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47109 #undef TARGET_RTX_COSTS
47110 #define TARGET_RTX_COSTS ix86_rtx_costs
47111 #undef TARGET_ADDRESS_COST
47112 #define TARGET_ADDRESS_COST ix86_address_cost
47114 #undef TARGET_FIXED_CONDITION_CODE_REGS
47115 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47116 #undef TARGET_CC_MODES_COMPATIBLE
47117 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47119 #undef TARGET_MACHINE_DEPENDENT_REORG
47120 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47122 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47123 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47125 #undef TARGET_BUILD_BUILTIN_VA_LIST
47126 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47128 #undef TARGET_FOLD_BUILTIN
47129 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47131 #undef TARGET_COMPARE_VERSION_PRIORITY
47132 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47134 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47135 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47136 ix86_generate_version_dispatcher_body
47138 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47139 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47140 ix86_get_function_versions_dispatcher
47142 #undef TARGET_ENUM_VA_LIST_P
47143 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47145 #undef TARGET_FN_ABI_VA_LIST
47146 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47148 #undef TARGET_CANONICAL_VA_LIST_TYPE
47149 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47151 #undef TARGET_EXPAND_BUILTIN_VA_START
47152 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47154 #undef TARGET_MD_ASM_CLOBBERS
47155 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47157 #undef TARGET_PROMOTE_PROTOTYPES
47158 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47159 #undef TARGET_SETUP_INCOMING_VARARGS
47160 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47161 #undef TARGET_MUST_PASS_IN_STACK
47162 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47163 #undef TARGET_FUNCTION_ARG_ADVANCE
47164 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47165 #undef TARGET_FUNCTION_ARG
47166 #define TARGET_FUNCTION_ARG ix86_function_arg
47167 #undef TARGET_FUNCTION_ARG_BOUNDARY
47168 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47169 #undef TARGET_PASS_BY_REFERENCE
47170 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47171 #undef TARGET_INTERNAL_ARG_POINTER
47172 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47173 #undef TARGET_UPDATE_STACK_BOUNDARY
47174 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47175 #undef TARGET_GET_DRAP_RTX
47176 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47177 #undef TARGET_STRICT_ARGUMENT_NAMING
47178 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47179 #undef TARGET_STATIC_CHAIN
47180 #define TARGET_STATIC_CHAIN ix86_static_chain
47181 #undef TARGET_TRAMPOLINE_INIT
47182 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47183 #undef TARGET_RETURN_POPS_ARGS
47184 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47186 #undef TARGET_LEGITIMATE_COMBINED_INSN
47187 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47189 #undef TARGET_ASAN_SHADOW_OFFSET
47190 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47192 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47193 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47195 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47196 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47198 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47199 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47201 #undef TARGET_C_MODE_FOR_SUFFIX
47202 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47204 #ifdef HAVE_AS_TLS
47205 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47206 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47207 #endif
47209 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47210 #undef TARGET_INSERT_ATTRIBUTES
47211 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47212 #endif
47214 #undef TARGET_MANGLE_TYPE
47215 #define TARGET_MANGLE_TYPE ix86_mangle_type
47217 #if !TARGET_MACHO
47218 #undef TARGET_STACK_PROTECT_FAIL
47219 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47220 #endif
47222 #undef TARGET_FUNCTION_VALUE
47223 #define TARGET_FUNCTION_VALUE ix86_function_value
47225 #undef TARGET_FUNCTION_VALUE_REGNO_P
47226 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47228 #undef TARGET_PROMOTE_FUNCTION_MODE
47229 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47231 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47232 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47234 #undef TARGET_INSTANTIATE_DECLS
47235 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47237 #undef TARGET_SECONDARY_RELOAD
47238 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
47240 #undef TARGET_CLASS_MAX_NREGS
47241 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
47243 #undef TARGET_PREFERRED_RELOAD_CLASS
47244 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
47245 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
47246 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
47247 #undef TARGET_CLASS_LIKELY_SPILLED_P
47248 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
47250 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
47251 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
47252 ix86_builtin_vectorization_cost
47253 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
47254 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
47255 ix86_vectorize_vec_perm_const_ok
47256 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
47257 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
47258 ix86_preferred_simd_mode
47259 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
47260 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
47261 ix86_autovectorize_vector_sizes
47262 #undef TARGET_VECTORIZE_INIT_COST
47263 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
47264 #undef TARGET_VECTORIZE_ADD_STMT_COST
47265 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
47266 #undef TARGET_VECTORIZE_FINISH_COST
47267 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
47268 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
47269 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
47271 #undef TARGET_SET_CURRENT_FUNCTION
47272 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
47274 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
47275 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
47277 #undef TARGET_OPTION_SAVE
47278 #define TARGET_OPTION_SAVE ix86_function_specific_save
47280 #undef TARGET_OPTION_RESTORE
47281 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
47283 #undef TARGET_OPTION_PRINT
47284 #define TARGET_OPTION_PRINT ix86_function_specific_print
47286 #undef TARGET_OPTION_FUNCTION_VERSIONS
47287 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
47289 #undef TARGET_CAN_INLINE_P
47290 #define TARGET_CAN_INLINE_P ix86_can_inline_p
47292 #undef TARGET_EXPAND_TO_RTL_HOOK
47293 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
47295 #undef TARGET_LEGITIMATE_ADDRESS_P
47296 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
47298 #undef TARGET_LRA_P
47299 #define TARGET_LRA_P hook_bool_void_true
47301 #undef TARGET_REGISTER_PRIORITY
47302 #define TARGET_REGISTER_PRIORITY ix86_register_priority
47304 #undef TARGET_REGISTER_USAGE_LEVELING_P
47305 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
47307 #undef TARGET_LEGITIMATE_CONSTANT_P
47308 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
47310 #undef TARGET_FRAME_POINTER_REQUIRED
47311 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
47313 #undef TARGET_CAN_ELIMINATE
47314 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
47316 #undef TARGET_EXTRA_LIVE_ON_ENTRY
47317 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
47319 #undef TARGET_ASM_CODE_END
47320 #define TARGET_ASM_CODE_END ix86_code_end
47322 #undef TARGET_CONDITIONAL_REGISTER_USAGE
47323 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
47325 #if TARGET_MACHO
47326 #undef TARGET_INIT_LIBFUNCS
47327 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
47328 #endif
47330 #undef TARGET_LOOP_UNROLL_ADJUST
47331 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
47333 #undef TARGET_SPILL_CLASS
47334 #define TARGET_SPILL_CLASS ix86_spill_class
47336 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
47337 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
47338 ix86_simd_clone_compute_vecsize_and_simdlen
47340 #undef TARGET_SIMD_CLONE_ADJUST
47341 #define TARGET_SIMD_CLONE_ADJUST \
47342 ix86_simd_clone_adjust
47344 #undef TARGET_SIMD_CLONE_USABLE
47345 #define TARGET_SIMD_CLONE_USABLE \
47346 ix86_simd_clone_usable
47348 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
47349 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
47350 ix86_float_exceptions_rounding_supported_p
47352 #undef TARGET_MODE_EMIT
47353 #define TARGET_MODE_EMIT ix86_emit_mode_set
47355 #undef TARGET_MODE_NEEDED
47356 #define TARGET_MODE_NEEDED ix86_mode_needed
47358 #undef TARGET_MODE_AFTER
47359 #define TARGET_MODE_AFTER ix86_mode_after
47361 #undef TARGET_MODE_ENTRY
47362 #define TARGET_MODE_ENTRY ix86_mode_entry
47364 #undef TARGET_MODE_EXIT
47365 #define TARGET_MODE_EXIT ix86_mode_exit
47367 #undef TARGET_MODE_PRIORITY
47368 #define TARGET_MODE_PRIORITY ix86_mode_priority
47370 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
47371 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
47374 \f